/* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ /* Concepts and parts of this file have been contributed by Ilya Kharin. */ /** * @file STM32WBxx/stm32_registry.h * @brief STM32WBxx capabilities registry. * * @addtogroup HAL * @{ */ #ifndef STM32_REGISTRY_H #define STM32_REGISTRY_H /*===========================================================================*/ /* Platform capabilities. */ /*===========================================================================*/ /** * @name STM32WBxx capabilities * @{ */ /*===========================================================================*/ /* Common. */ /*===========================================================================*/ /* RNG attributes.*/ #define STM32_HAS_RNG1 TRUE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 80 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 18 #define STM32_RTC_WKUP_EXTI 19 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) #define STM32_HAS_HASH1 TRUE #define STM32_HAS_CRYP1 TRUE /*===========================================================================*/ /* STM32WB55xx. */ /*===========================================================================*/ #if defined(STM32WB55xx) || defined(__DOXYGEN__) /* RCC attributes.*/ #define STM32_RCC_HAS_HSI16 TRUE #define STM32_RCC_HAS_HSI48 TRUE #define STM32_RCC_HAS_MSI TRUE #define STM32_RCC_HAS_LSI FALSE #define STM32_RCC_HAS_LSI1 TRUE #define STM32_RCC_HAS_LSI2 TRUE #define STM32_RCC_LSI2_TRIM_ADDR 0x1FFF7548U #define STM32_RCC_HAS_LSE TRUE #define STM32_RCC_HAS_HSE FALSE #define STM32_RCC_HAS_HSE32 TRUE #define STM32_RCC_HAS_PLL TRUE #define STM32_RCC_PLL_HAS_P TRUE #define STM32_RCC_PLL_HAS_Q TRUE #define STM32_RCC_PLL_HAS_R TRUE #define STM32_RCC_HAS_PLLSAI1 TRUE #define STM32_RCC_PLLSAI1_HAS_P TRUE #define STM32_RCC_PLLSAI1_HAS_Q TRUE #define STM32_RCC_PLLSAI1_HAS_R TRUE /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 FALSE #define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_ADC5 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 FALSE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 FALSE #define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA TRUE #define STM32_DMA_SUPPORTS_DMAMUX TRUE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA2_NUM_CHANNELS 7 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 49 #define STM32_EXTI_IMR1_MASK 0x7FC00000U #define STM32_EXTI_IMR2_MASK 0xFFFFFCFDU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/ /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOF FALSE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ RCC_AHB2ENR_GPIOBEN | \ RCC_AHB2ENR_GPIOCEN | \ RCC_AHB2ENR_GPIODEN | \ RCC_AHB2ENR_GPIOEEN | \ RCC_AHB2ENR_GPIOHEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C3 TRUE #define STM32_HAS_I2C2 FALSE #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 TRUE /* SDMMC attributes.*/ #define STM32_HAS_SDMMC1 FALSE #define STM32_HAS_SDMMC2 FALSE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S FALSE #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 4 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM3 FALSE #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM6 FALSE #define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_HAS_LPUART1 TRUE #define STM32_HAS_USART2 FALSE #define STM32_HAS_USART3 FALSE #define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE /* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_USB_ACCESS_SCHEME_2x16 TRUE #define STM32_USB_PMA_SIZE 1024 #define STM32_USB_HAS_BCDR TRUE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32WB55xx) */ /*===========================================================================*/ /* STM32WB50xx. */ /*===========================================================================*/ #if defined(STM32WB50xx) || defined(__DOXYGEN__) #error "STM32WB50xx is not supported" #endif /* defined(STM32WB50xx) */ /*===========================================================================*/ /* STM32WB35xx. */ /*===========================================================================*/ #if defined(STM32WB35xx) || defined(__DOXYGEN__) #error "STM32WB35xx is not supported" #endif /* defined(STM32WB35xx) */ /*===========================================================================*/ /* STM32WB30xx. */ /*===========================================================================*/ #if defined(STM32WB30xx) || defined(__DOXYGEN__) #error "STM32WB30xx is not supported" #endif /* defined(STM32WB30xx) */ /** @} */ #endif /* STM32_REGISTRY_H */ /** @} */