/* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ /** * @file STM32F3xx/stm32_registry.h * @brief STM32F3xx capabilities registry. * * @addtogroup HAL * @{ */ #ifndef STM32_REGISTRY_H #define STM32_REGISTRY_H /** * @brief Sub-family identifier. */ #if !defined(STM32F3XX) || defined(__DOXYGEN__) #define STM32F3XX #endif /*===========================================================================*/ /* Platform capabilities. */ /*===========================================================================*/ /** * @name STM32F3xx capabilities * @{ */ /*===========================================================================*/ /* Common. */ /*===========================================================================*/ /* DAC attributes.*/ #define STM32_DAC_HAS_MCR FALSE /* RNG attributes.*/ #define STM32_HAS_RNG1 TRUE /*===========================================================================*/ /* STM32F303xC. */ /*===========================================================================*/ #if defined(STM32F303xC) || defined(__DOXYGEN__) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 TRUE #define STM32_ADC2_HANDLER Vector88 #define STM32_ADC2_NUMBER 18 #define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) #define STM32_ADC2_DMA_CHN 0x00000000 #define STM32_HAS_ADC3 TRUE #define STM32_ADC3_HANDLER VectorFC #define STM32_ADC3_NUMBER 47 #define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_ADC3_DMA_CHN 0x00000000 #define STM32_HAS_ADC4 TRUE #define STM32_ADC4_HANDLER Vector134 #define STM32_ADC4_NUMBER 61 #define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 4)) #define STM32_ADC4_DMA_CHN 0x00000000 #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_HAS_DAC1_CH2 TRUE #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 5 #define STM32_DMA2_CH1_HANDLER Vector120 #define STM32_DMA2_CH2_HANDLER Vector124 #define STM32_DMA2_CH3_HANDLER Vector128 #define STM32_DMA2_CH4_HANDLER Vector12C #define STM32_DMA2_CH5_HANDLER Vector130 #define STM32_DMA2_CH1_NUMBER 56 #define STM32_DMA2_CH2_NUMBER 57 #define STM32_DMA2_CH3_NUMBER 58 #define STM32_DMA2_CH4_NUMBER 59 #define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOEEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 1 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE #define STM32_TIM8_CHANNELS 6 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 TRUE #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_HAS_UART5 TRUE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_USB_ACCESS_SCHEME_2x16 FALSE #define STM32_USB_PMA_SIZE 512 #define STM32_USB_HAS_BCDR FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F303xC) */ /*===========================================================================*/ /* STM32F303xE. */ /*===========================================================================*/ #if defined(STM32F303xE) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 TRUE #define STM32_ADC2_HANDLER Vector88 #define STM32_ADC2_NUMBER 18 #define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) #define STM32_ADC2_DMA_CHN 0x00000000 #define STM32_HAS_ADC3 TRUE #define STM32_ADC3_HANDLER VectorFC #define STM32_ADC3_NUMBER 47 #define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_ADC3_DMA_CHN 0x00000000 #define STM32_HAS_ADC4 TRUE #define STM32_ADC4_HANDLER Vector134 #define STM32_ADC4_NUMBER 61 #define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 4)) #define STM32_ADC4_DMA_CHN 0x00000000 #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_HAS_DAC1_CH2 TRUE #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 5 #define STM32_DMA2_CH1_HANDLER Vector120 #define STM32_DMA2_CH2_HANDLER Vector124 #define STM32_DMA2_CH3_HANDLER Vector128 #define STM32_DMA2_CH4_HANDLER Vector12C #define STM32_DMA2_CH5_HANDLER Vector130 #define STM32_DMA2_CH1_NUMBER 56 #define STM32_DMA2_CH2_NUMBER 57 #define STM32_DMA2_CH3_NUMBER 58 #define STM32_DMA2_CH4_NUMBER 59 #define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG TRUE #define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOEEN | \ RCC_AHBENR_GPIOFEN | \ RCC_AHBENR_GPIOGEN | \ RCC_AHBENR_GPIOHEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_I2C3 TRUE #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 TRUE #define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE #define STM32_TIM8_CHANNELS 6 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM20 TRUE #define STM32_TIM20_IS_32BITS FALSE #define STM32_TIM20_CHANNELS 6 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 TRUE #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_HAS_UART5 TRUE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_USB_ACCESS_SCHEME_2x16 TRUE #define STM32_USB_PMA_SIZE 768 #define STM32_USB_HAS_BCDR FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F303xE) */ /*===========================================================================*/ /* STM32F303x8. */ /*===========================================================================*/ #if defined(STM32F303x8) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 TRUE #define STM32_ADC2_HANDLER Vector88 #define STM32_ADC2_NUMBER 18 #define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) #define STM32_ADC2_DMA_CHN 0x00000000 #define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_DAC1_CH2 TRUE #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_DAC2_CH1 TRUE #define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 32 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 FALSE #define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI2 FALSE #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F303x8) */ /*===========================================================================*/ /* STM32F301x8. */ /*===========================================================================*/ #if defined(STM32F301x8) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 FALSE #define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 FALSE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 32 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_I2C3 TRUE #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI1 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM3 FALSE #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F301x8) */ /*===========================================================================*/ /* STM32F302x8. */ /*===========================================================================*/ #if defined(STM32F302x8) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 FALSE #define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 32 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_I2C3 TRUE #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI1 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM3 FALSE #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_USB_ACCESS_SCHEME_2x16 TRUE #define STM32_USB_PMA_SIZE 768 #define STM32_USB_HAS_BCDR FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F302x8) */ /*===========================================================================*/ /* STM32F302xC. */ /*===========================================================================*/ #if defined(STM32F302xC) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 TRUE #define STM32_ADC2_HANDLER Vector88 #define STM32_ADC2_NUMBER 18 #define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) #define STM32_ADC2_DMA_CHN 0x00000000 #define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 5 #define STM32_DMA2_CH1_HANDLER Vector120 #define STM32_DMA2_CH2_HANDLER Vector124 #define STM32_DMA2_CH3_HANDLER Vector128 #define STM32_DMA2_CH4_HANDLER Vector12C #define STM32_DMA2_CH5_HANDLER Vector130 #define STM32_DMA2_CH1_NUMBER 56 #define STM32_DMA2_CH2_NUMBER 57 #define STM32_DMA2_CH3_NUMBER 58 #define STM32_DMA2_CH4_NUMBER 59 #define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOEEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 TRUE #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_HAS_UART5 TRUE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_USB_ACCESS_SCHEME_2x16 FALSE #define STM32_USB_PMA_SIZE 512 #define STM32_USB_HAS_BCDR FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F302xC) */ /*===========================================================================*/ /* STM32F302xE. */ /*===========================================================================*/ #if defined(STM32F302xE) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 TRUE #define STM32_ADC2_HANDLER Vector88 #define STM32_ADC2_NUMBER 18 #define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) #define STM32_ADC2_DMA_CHN 0x00000000 #define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 5 #define STM32_DMA2_CH1_HANDLER Vector120 #define STM32_DMA2_CH2_HANDLER Vector124 #define STM32_DMA2_CH3_HANDLER Vector128 #define STM32_DMA2_CH4_HANDLER Vector12C #define STM32_DMA2_CH5_HANDLER Vector130 #define STM32_DMA2_CH1_NUMBER 56 #define STM32_DMA2_CH2_NUMBER 57 #define STM32_DMA2_CH3_NUMBER 58 #define STM32_DMA2_CH4_NUMBER 59 #define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG TRUE #define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOEEN | \ RCC_AHBENR_GPIOFEN | \ RCC_AHBENR_GPIOGEN | \ RCC_AHBENR_GPIOHEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_I2C3 TRUE #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 TRUE #define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 TRUE #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_HAS_UART5 TRUE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_USB_ACCESS_SCHEME_2x16 TRUE #define STM32_USB_PMA_SIZE 768 #define STM32_USB_HAS_BCDR FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F302xE) */ /*===========================================================================*/ /* STM32F318x8. */ /*===========================================================================*/ #if defined(STM32F318x8) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 FALSE #define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 32 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD FALSE #define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_I2C3 TRUE #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI1 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM3 FALSE #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F318x8) */ /*===========================================================================*/ /* STM32F328x8. */ /*===========================================================================*/ #if defined(STM32F328x8) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 TRUE #define STM32_ADC2_HANDLER Vector88 #define STM32_ADC2_NUMBER 18 #define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) #define STM32_ADC2_DMA_CHN 0x00000000 #define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_DAC1_CH2 TRUE #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_DAC2_CH1 TRUE #define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 32 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 FALSE #define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI2 FALSE #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F328x8) */ /*===========================================================================*/ /* STM32F358xC. */ /*===========================================================================*/ #if defined(STM32F358xC) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 TRUE #define STM32_ADC2_HANDLER Vector88 #define STM32_ADC2_NUMBER 18 #define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) #define STM32_ADC2_DMA_CHN 0x00000000 #define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_HAS_DAC1_CH2 TRUE #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 5 #define STM32_DMA2_CH1_HANDLER Vector120 #define STM32_DMA2_CH2_HANDLER Vector124 #define STM32_DMA2_CH3_HANDLER Vector128 #define STM32_DMA2_CH4_HANDLER Vector12C #define STM32_DMA2_CH5_HANDLER Vector130 #define STM32_DMA2_CH1_NUMBER 56 #define STM32_DMA2_CH2_NUMBER 57 #define STM32_DMA2_CH3_NUMBER 58 #define STM32_DMA2_CH4_NUMBER 59 #define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOEEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 1 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 TRUE #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_HAS_UART5 TRUE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_USB_ACCESS_SCHEME_2x16 FALSE #define STM32_USB_PMA_SIZE 512 #define STM32_USB_HAS_BCDR FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F358xC) */ /*===========================================================================*/ /* STM32F334x8. */ /*===========================================================================*/ #if defined(STM32F334x8) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 TRUE #define STM32_ADC2_HANDLER Vector88 #define STM32_ADC2_NUMBER 18 #define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 4)) #define STM32_ADC2_DMA_CHN 0x00000000 #define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_DAC1_CH2 TRUE #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_DAC2_CH1 TRUE #define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 32 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 FALSE #define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 1 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI2 FALSE #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* HRTIM attributes.*/ #define STM32_HAS_HRTIM1 TRUE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F334x8) */ /*===========================================================================*/ /* STM32F398xx. */ /*===========================================================================*/ #if defined(STM32F398xx) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC1_HANDLER Vector88 #define STM32_ADC1_NUMBER 18 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 TRUE #define STM32_ADC2_HANDLER Vector88 #define STM32_ADC2_NUMBER 18 #define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 3)) #define STM32_ADC2_DMA_CHN 0x00000000 #define STM32_HAS_ADC3 TRUE #define STM32_ADC3_HANDLER VectorFC #define STM32_ADC3_NUMBER 47 #define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) #define STM32_ADC3_DMA_CHN 0x00000000 #define STM32_HAS_ADC4 TRUE #define STM32_ADC4_HANDLER Vector134 #define STM32_ADC4_NUMBER 61 #define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ STM32_DMA_STREAM_ID_MSK(2, 4)) #define STM32_ADC4_DMA_CHN 0x00000000 #define STM32_HAS_ADC5 FALSE #define STM32_HAS_SDADC1 FALSE #define STM32_HAS_SDADC2 FALSE #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE #define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 TRUE #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_HAS_DAC1_CH2 TRUE #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE #define STM32_DMA_SUPPORTS_DMAMUX FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA1_CH1_HANDLER Vector6C #define STM32_DMA1_CH2_HANDLER Vector70 #define STM32_DMA1_CH3_HANDLER Vector74 #define STM32_DMA1_CH4_HANDLER Vector78 #define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH3_NUMBER 13 #define STM32_DMA1_CH4_NUMBER 14 #define STM32_DMA1_CH5_NUMBER 15 #define STM32_DMA1_CH6_NUMBER 16 #define STM32_DMA1_CH7_NUMBER 17 #define STM32_DMA2_NUM_CHANNELS 5 #define STM32_DMA2_CH1_HANDLER Vector120 #define STM32_DMA2_CH2_HANDLER Vector124 #define STM32_DMA2_CH3_HANDLER Vector128 #define STM32_DMA2_CH4_HANDLER Vector12C #define STM32_DMA2_CH5_HANDLER Vector130 #define STM32_DMA2_CH1_NUMBER 56 #define STM32_DMA2_CH2_NUMBER 57 #define STM32_DMA2_CH3_NUMBER 58 #define STM32_DMA2_CH4_NUMBER 59 #define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 #define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* Flash attributes.*/ #define STM32_FLASH_NUMBER_OF_BANKS 1 #if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/ #endif /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG TRUE #define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOEEN | \ RCC_AHBENR_GPIOFEN | \ RCC_AHBENR_GPIOGEN | \ RCC_AHBENR_GPIOHEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_I2C3 TRUE #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 64 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 #define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 #define STM32_RTC_ALARM_NUMBER 41 #define STM32_RTC_ALARM_EXTI 17 #define STM32_RTC_TAMP_STAMP_EXTI 19 #define STM32_RTC_WKUP_EXTI 20 #define STM32_RTC_IRQ_ENABLE() do { \ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ } while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI3 TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_HAS_SPI4 TRUE #define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ #define STM32_TIM_MAX_CHANNELS 6 #define STM32_HAS_TIM1 TRUE #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 6 #define STM32_HAS_TIM2 TRUE #define STM32_TIM2_IS_32BITS TRUE #define STM32_TIM2_CHANNELS 4 #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 #define STM32_HAS_TIM4 TRUE #define STM32_TIM4_IS_32BITS FALSE #define STM32_TIM4_CHANNELS 4 #define STM32_HAS_TIM6 TRUE #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 #define STM32_HAS_TIM7 TRUE #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE #define STM32_TIM8_CHANNELS 6 #define STM32_HAS_TIM15 TRUE #define STM32_TIM15_IS_32BITS FALSE #define STM32_TIM15_CHANNELS 2 #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM20 TRUE #define STM32_TIM20_IS_32BITS FALSE #define STM32_TIM20_CHANNELS 6 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE #define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM21 FALSE #define STM32_HAS_TIM22 FALSE /* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_HAS_USART2 TRUE #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_HAS_USART3 TRUE #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_HAS_UART4 TRUE #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_HAS_UART5 TRUE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE /* IWDG attributes.*/ #define STM32_HAS_IWDG TRUE #define STM32_IWDG_IS_WINDOWED TRUE /* LTDC attributes.*/ #define STM32_HAS_LTDC FALSE /* DMA2D attributes.*/ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ #define STM32_HAS_FSMC TRUE #define STM32_FSMC_IS_FMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F398xx) */ /** @} */ #endif /* STM32_REGISTRY_H */ /** @} */