/** *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ #ifndef __GD32VF103_H #define __GD32VF103_H #ifdef __cplusplus extern "C" { #endif #include /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t STAT; __IO uint32_t CTL0; __IO uint32_t CTL1; __IO uint32_t SAMPT0; __IO uint32_t SAMPT1; __IO uint32_t IOFF0; __IO uint32_t IOFF1; __IO uint32_t IOFF2; __IO uint32_t IOFF3; __IO uint32_t WDHT; __IO uint32_t WDLT; __IO uint32_t RSQ0; __IO uint32_t RSQ1; __IO uint32_t RSQ2; __IO uint32_t ISQ; __IO uint32_t IDATA0; __IO uint32_t IDATA1; __IO uint32_t IDATA2; __IO uint32_t IDATA3; __IO uint32_t RDATA; uint32_t RESERVED[12]; __IO uint32_t OVSAMPCTL; } ADC_TypeDef; typedef struct { __IO uint32_t STAT; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC0 base address */ __IO uint32_t CTL0; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC0 base address + 0x04 */ __IO uint32_t CTL1; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC0 base address + 0x08 */ uint32_t RESERVED[16]; __IO uint32_t RDATA; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC0 base address + 0x4C */ } ADC_Common_TypeDef; /** * @brief Backup Registers */ typedef struct { uint32_t RESERVED0; __IO uint32_t DATA1; __IO uint32_t DATA2; __IO uint32_t DATA3; __IO uint32_t DATA4; __IO uint32_t DATA5; __IO uint32_t DATA6; __IO uint32_t DATA7; __IO uint32_t DATA8; __IO uint32_t DATA9; __IO uint32_t DATA10; __IO uint32_t OCTL; __IO uint32_t TPCTL; __IO uint32_t TPCS; uint32_t RESERVED13[2]; __IO uint32_t DATA11; __IO uint32_t DATA12; __IO uint32_t DATA13; __IO uint32_t DATA14; __IO uint32_t DATA15; __IO uint32_t DATA16; __IO uint32_t DATA17; __IO uint32_t DATA18; __IO uint32_t DATA19; __IO uint32_t DATA20; __IO uint32_t DATA21; __IO uint32_t DATA22; __IO uint32_t DATA23; __IO uint32_t DATA24; __IO uint32_t DATA25; __IO uint32_t DATA26; __IO uint32_t DATA27; __IO uint32_t DATA28; __IO uint32_t DATA29; __IO uint32_t DATA30; __IO uint32_t DATA31; __IO uint32_t DATA32; __IO uint32_t DATA33; __IO uint32_t DATA34; __IO uint32_t DATA35; __IO uint32_t DATA36; __IO uint32_t DATA37; __IO uint32_t DATA38; __IO uint32_t DATA39; __IO uint32_t DATA40; __IO uint32_t DATA41; __IO uint32_t DATA42; } BKP_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TMI; __IO uint32_t TMP; __IO uint32_t TMDATA0; __IO uint32_t TMDATA1; } CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RFIFOMI; __IO uint32_t RFIFOMP; __IO uint32_t RFIFOMDATA0; __IO uint32_t RFIFOMDATA1; } CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; __IO uint32_t FR2; } CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t CTL; __IO uint32_t STAT; __IO uint32_t TSTAT; __IO uint32_t RFIFO0; __IO uint32_t RFIFO1; __IO uint32_t INTEN; __IO uint32_t ERR; __IO uint32_t BT; uint32_t RESERVED0[88]; CAN_TxMailBox_TypeDef sTxMailBox[3]; CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; uint32_t RESERVED1[12]; __IO uint32_t FCTL; __IO uint32_t FMCFG; uint32_t RESERVED2; __IO uint32_t FSCFG; uint32_t RESERVED3; __IO uint32_t FAFIFO; uint32_t RESERVED4; __IO uint32_t FW; uint32_t RESERVED5[8]; CAN_FilterRegister_TypeDef sFilterRegister[28]; } CAN_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DATA; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t FDATA; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ __IO uint32_t CTL; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CTL; __IO uint32_t SWT; __IO uint32_t R12DH0; __IO uint32_t L12DH0; __IO uint32_t R8DH0; __IO uint32_t R12DH1; __IO uint32_t L12DH1; __IO uint32_t R8DH1; __IO uint32_t R12DH; __IO uint32_t L12DH; __IO uint32_t R8DH; __IO uint32_t DO0; __IO uint32_t DO1; } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; __IO uint32_t CR; } DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CTL; __IO uint32_t CNT; __IO uint32_t PADDR; __IO uint32_t MADDR; } DMA_Channel_TypeDef; typedef struct { __IO uint32_t INTF; __IO uint32_t INTC ; } DMA_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t INTEN; __IO uint32_t EVEN; __IO uint32_t RTEN; __IO uint32_t FTEN; __IO uint32_t SWIEV; __IO uint32_t PD; } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t WS; __IO uint32_t KEY; __IO uint32_t OBKEY; __IO uint32_t STAT; __IO uint32_t CTL; __IO uint32_t ADDR; __IO uint32_t RESERVED0; __IO uint32_t OBSTAT; __IO uint32_t WP; uint32_t RESERVED1[55]; __IO uint32_t PID; } FLASH_TypeDef; /** * @brief Option Bytes Registers */ typedef struct { __IO uint16_t RDP; __IO uint16_t USER; __IO uint16_t Data0; __IO uint16_t Data1; __IO uint16_t WRP0; __IO uint16_t WRP1; __IO uint16_t WRP2; __IO uint16_t WRP3; } OB_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t CTL0; __IO uint32_t CTL1; __IO uint32_t ISTAT; __IO uint32_t OCTL; __IO uint32_t BOP; __IO uint32_t BC; __IO uint32_t LOCK; } GPIO_TypeDef; /** * @brief Alternate Function I/O */ typedef struct { __IO uint32_t EC; __IO uint32_t PCF0; __IO uint32_t EXTISS[4]; uint32_t RESERVED0; __IO uint32_t PCF1; } AFIO_TypeDef; /** * @brief Inter Integrated Circuit Interface */ typedef struct { __IO uint32_t CTL0; __IO uint32_t CTL1; __IO uint32_t SADDR0; __IO uint32_t SADDR1; __IO uint32_t DATA; __IO uint32_t STAT0; __IO uint32_t STAT1; __IO uint32_t CKCFG; __IO uint32_t RT; uint32_t RESERVED[27]; __IO uint32_t FMPCFG; } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t CTL; /*!< Key register, Address offset: 0x00 */ __IO uint32_t PSC; /*!< Prescaler register, Address offset: 0x04 */ __IO uint32_t RLD; /*!< Reload register, Address offset: 0x08 */ __IO uint32_t STAT; /*!< Status register, Address offset: 0x0C */ } FWDGT_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CTL; __IO uint32_t CS; } PMU_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CTL; __IO uint32_t CFG0; __IO uint32_t INT; __IO uint32_t APB2RST; __IO uint32_t APB1RST; __IO uint32_t AHBEN; __IO uint32_t APB2EN; __IO uint32_t APB1EN; __IO uint32_t BDCTL; __IO uint32_t RSTSCK; __IO uint32_t AHBRST; __IO uint32_t CFG1; uint32_t RESERVED; __IO uint32_t DSV; } RCU_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t INTEN; __IO uint32_t CTL; __IO uint32_t PSCH; __IO uint32_t PSCL; __IO uint32_t DIVH; __IO uint32_t DIVL; __IO uint32_t CNTH; __IO uint32_t CNTL; __IO uint32_t ALRMH; __IO uint32_t ALRML; } RTC_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CTL0; __IO uint32_t CTL1; __IO uint32_t STAT; __IO uint32_t DATA; __IO uint32_t CRCPOLY; __IO uint32_t RCRC; __IO uint32_t TCRC; __IO uint32_t I2SCTL; __IO uint32_t I2SPSC; } SPI_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t STAT; /*!< USART Status register, Address offset: 0x00 */ __IO uint32_t DATA; /*!< USART Data register, Address offset: 0x04 */ __IO uint32_t BAUD; /*!< USART Baud rate register, Address offset: 0x08 */ __IO uint32_t CTL0; /*!< USART Control register 1, Address offset: 0x0C */ __IO uint32_t CTL1; /*!< USART Control register 2, Address offset: 0x10 */ __IO uint32_t CTL2; /*!< USART Control register 3, Address offset: 0x14 */ __IO uint32_t GP; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ } USART_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BANK1_END 0x0803FFFFU /*!< FLASH END address of bank1 */ #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ #define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) #define TIM1_BASE (APB1PERIPH_BASE + 0x00000000U) #define TIM2_BASE (APB1PERIPH_BASE + 0x00000400U) #define TIM3_BASE (APB1PERIPH_BASE + 0x00000800U) #define TIM4_BASE (APB1PERIPH_BASE + 0x00000C00U) #define TIM5_BASE (APB1PERIPH_BASE + 0x00001000U) #define TIM6_BASE (APB1PERIPH_BASE + 0x00001400U) #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) #define SPI1_BASE (APB1PERIPH_BASE + 0x00003800U) #define SPI2_BASE (APB1PERIPH_BASE + 0x00003C00U) #define USART1_BASE (APB1PERIPH_BASE + 0x00004400U) #define USART2_BASE (APB1PERIPH_BASE + 0x00004800U) #define UART3_BASE (APB1PERIPH_BASE + 0x00004C00U) #define UART4_BASE (APB1PERIPH_BASE + 0x00005000U) #define I2C0_BASE (APB1PERIPH_BASE + 0x00005400U) #define I2C1_BASE (APB1PERIPH_BASE + 0x5800) #define CAN0_BASE (APB1PERIPH_BASE + 0x00006400U) #define CAN1_BASE (APB1PERIPH_BASE + 0x00006800U) #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U) #define ADC0_BASE (APB2PERIPH_BASE + 0x00002400U) #define ADC1_BASE (APB2PERIPH_BASE + 0x00002800U) #define TIM0_BASE (APB2PERIPH_BASE + 0x00002C00U) #define SPI0_BASE (APB2PERIPH_BASE + 0x00003000U) #define USART0_BASE (APB2PERIPH_BASE + 0x00003800U) #define SDIO_BASE (PERIPH_BASE + 0x00018000U) #define DMA0_BASE (AHBPERIPH_BASE + 0x00000000U) #define DMA0_Channel0_BASE (AHBPERIPH_BASE + 0x00000008U) #define DMA0_Channel1_BASE (AHBPERIPH_BASE + 0x0000001CU) #define DMA0_Channel2_BASE (AHBPERIPH_BASE + 0x00000030U) #define DMA0_Channel3_BASE (AHBPERIPH_BASE + 0x00000044U) #define DMA0_Channel4_BASE (AHBPERIPH_BASE + 0x00000058U) #define DMA0_Channel5_BASE (AHBPERIPH_BASE + 0x0000006CU) #define DMA0_Channel6_BASE (AHBPERIPH_BASE + 0x00000080U) #define DMA1_BASE (AHBPERIPH_BASE + 0x00000400U) #define DMA1_Channel0_BASE (AHBPERIPH_BASE + 0x00000408U) #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0000041CU) #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x00000430U) #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000444U) #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000458U) #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */ #define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ #define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ #define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ /*!< USB registers base address */ #define USB_USBFS_PERIPH_BASE 0x50000000U #define USB_OTG_GLOBAL_BASE 0x00000000U #define USB_OTG_DEVICE_BASE 0x00000800U #define USB_OTG_IN_ENDPOINT_BASE 0x00000900U #define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00U #define USB_OTG_EP_REG_SIZE 0x00000020U #define USB_OTG_HOST_BASE 0x00000400U #define USB_OTG_HOST_PORT_BASE 0x00000440U #define USB_OTG_HOST_CHANNEL_BASE 0x00000500U #define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U #define USB_OTG_PMUCLKCTL_BASE 0x00000E00U #define USB_OTG_FIFO_BASE 0x00001000U #define USB_OTG_FIFO_SIZE 0x00001000U /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM1 ((TIM_TypeDef *)TIM1_BASE) #define TIM2 ((TIM_TypeDef *)TIM2_BASE) #define TIM3 ((TIM_TypeDef *)TIM3_BASE) #define TIM4 ((TIM_TypeDef *)TIM4_BASE) #define TIM5 ((TIM_TypeDef *)TIM5_BASE) #define TIM6 ((TIM_TypeDef *)TIM6_BASE) #define RTC ((RTC_TypeDef *)RTC_BASE) #define WWDG ((WWDG_TypeDef *)WWDG_BASE) #define FWDGT ((FWDGT_TypeDef *)FWDGT_BASE) #define SPI1 ((SPI_TypeDef *)SPI1_BASE) #define SPI2 ((SPI_TypeDef *)SPI2_BASE) #define USART1 ((USART_TypeDef *)USART1_BASE) #define USART2 ((USART_TypeDef *)USART2_BASE) #define UART3 ((USART_TypeDef *)UART3_BASE) #define UART4 ((USART_TypeDef *)UART4_BASE) #define I2C0 ((I2C_TypeDef *)I2C0_BASE) #define I2C1 ((I2C_TypeDef *)I2C1_BASE) #define CAN0 ((CAN_TypeDef *)CAN0_BASE) #define CAN1 ((CAN_TypeDef *)CAN1_BASE) #define BKP ((BKP_TypeDef *)BKP_BASE) #define PMU ((PMU_TypeDef *)PMU_BASE) #define DAC ((DAC_TypeDef *)DAC_BASE) #define AFIO ((AFIO_TypeDef *)AFIO_BASE) #define EXTI ((EXTI_TypeDef *)EXTI_BASE) #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) #define ADC0 ((ADC_TypeDef *)ADC0_BASE) #define ADC1 ((ADC_TypeDef *)ADC1_BASE) #define ADC02_COMMON ((ADC_Common_TypeDef *)ADC0_BASE) #define TIM0 ((TIM_TypeDef *)TIM0_BASE) #define SPI0 ((SPI_TypeDef *)SPI0_BASE) #define USART0 ((USART_TypeDef *)USART0_BASE) #define SDIO ((SDIO_TypeDef *)SDIO_BASE) #define DMA0 ((DMA_TypeDef *)DMA0_BASE) #define DMA1 ((DMA_TypeDef *)DMA1_BASE) #define DMA0_Channel0 ((DMA_Channel_TypeDef *)DMA0_Channel0_BASE) #define DMA0_Channel1 ((DMA_Channel_TypeDef *)DMA0_Channel1_BASE) #define DMA0_Channel2 ((DMA_Channel_TypeDef *)DMA0_Channel2_BASE) #define DMA0_Channel3 ((DMA_Channel_TypeDef *)DMA0_Channel3_BASE) #define DMA0_Channel4 ((DMA_Channel_TypeDef *)DMA0_Channel4_BASE) #define DMA0_Channel5 ((DMA_Channel_TypeDef *)DMA0_Channel5_BASE) #define DMA0_Channel6 ((DMA_Channel_TypeDef *)DMA0_Channel6_BASE) #define DMA1_Channel0 ((DMA_Channel_TypeDef *)DMA1_Channel0_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) #define RCU ((RCU_TypeDef *)RCU_BASE) #define CRC ((CRC_TypeDef *)CRC_BASE) #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) #define OB ((OB_TypeDef *)OB_BASE) #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) #define USB_USBFS ((USB_OTG_GlobalTypeDef *)USB_USBFS_PERIPH_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* CRC calculation unit (CRC) */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DATA register *********************/ #define CRC_DATA_DATA_Pos (0U) #define CRC_DATA_DATA_Msk (0xFFFFFFFFU << CRC_DATA_DATA_Pos) /*!< 0xFFFFFFFF */ #define CRC_DATA_DATA CRC_DATA_DATA_Msk /*!< Data register bits */ /******************* Bit definition for CRC_FDATA register ********************/ #define CRC_FDATA_FDATA_Pos (0U) #define CRC_FDATA_FDATA_Msk (0xFFU << CRC_FDATA_FDATA_Pos) /*!< 0x000000FF */ #define CRC_FDATA_FDATA CRC_FDATA_FDATA_Msk /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CTL register ********************/ #define CRC_CTL_RST_Pos (0U) #define CRC_CTL_RST_Msk (0x1U << CRC_CTL_RST_Pos) /*!< 0x00000001 */ #define CRC_CTL_RST CRC_CTL_RST_Msk /*!< RESET bit */ /******************************************************************************/ /* */ /* Power Control */ /* */ /******************************************************************************/ /******************** Bit definition for PMU_CTL register ********************/ #define PMU_CTL_LDOLP_Pos (0U) #define PMU_CTL_LDOLP_Msk (0x1U << PMU_CTL_LDOLP_Pos) /*!< 0x00000001 */ #define PMU_CTL_LDOLP PMU_CTL_LDOLP_Msk /*!< Low-Power Deepsleep */ #define PMU_CTL_STBMOD_Pos (1U) #define PMU_CTL_STBMOD_Msk (0x1U << PMU_CTL_STBMOD_Pos) /*!< 0x00000002 */ #define PMU_CTL_STBMOD PMU_CTL_STBMOD_Msk /*!< Power Down Deepsleep */ #define PMU_CTL_WURST_Pos (2U) #define PMU_CTL_WURST_Msk (0x1U << PMU_CTL_WURST_Pos) /*!< 0x00000004 */ #define PMU_CTL_WURST PMU_CTL_WURST_Msk /*!< Clear Wakeup Flag */ #define PMU_CTL_STBRST_Pos (3U) #define PMU_CTL_STBRST_Msk (0x1U << PMU_CTL_STBRST_Pos) /*!< 0x00000008 */ #define PMU_CTL_STBRST PMU_CTL_STBRST_Msk /*!< Clear Standby Flag */ #define PMU_CTL_LVDEN_Pos (4U) #define PMU_CTL_LVDEN_Msk (0x1U << PMU_CTL_LVDEN_Pos) /*!< 0x00000010 */ #define PMU_CTL_LVDEN PMU_CTL_LVDEN_Msk /*!< Power Voltage Detector Enable */ #define PMU_CTL_LVDT_Pos (5U) #define PMU_CTL_LVDT_Msk (0x7U << PMU_CTL_LVDT_Pos) /*!< 0x000000E0 */ #define PMU_CTL_LVDT PMU_CTL_LVDT_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ #define PMU_CTL_LVDT_0 (0x1U << PMU_CTL_LVDT_Pos) /*!< 0x00000020 */ #define PMU_CTL_LVDT_1 (0x2U << PMU_CTL_LVDT_Pos) /*!< 0x00000040 */ #define PMU_CTL_LVDT_2 (0x4U << PMU_CTL_LVDT_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ #define PMU_CTL_LVDT_LEV0 0x00000000U /*!< PVD level 2.2V */ #define PMU_CTL_LVDT_LEV1 0x00000020U /*!< PVD level 2.3V */ #define PMU_CTL_LVDT_LEV2 0x00000040U /*!< PVD level 2.4V */ #define PMU_CTL_LVDT_LEV3 0x00000060U /*!< PVD level 2.5V */ #define PMU_CTL_LVDT_LEV4 0x00000080U /*!< PVD level 2.6V */ #define PMU_CTL_LVDT_LEV5 0x000000A0U /*!< PVD level 2.7V */ #define PMU_CTL_LVDT_LEV6 0x000000C0U /*!< PVD level 2.8V */ #define PMU_CTL_LVDT_LEV7 0x000000E0U /*!< PVD level 2.9V */ /* Legacy defines */ #define PMU_CTL_LVDT_2V2 PMU_CTL_LVDT_LEV0 #define PMU_CTL_LVDT_2V3 PMU_CTL_LVDT_LEV1 #define PMU_CTL_LVDT_2V4 PMU_CTL_LVDT_LEV2 #define PMU_CTL_LVDT_2V5 PMU_CTL_LVDT_LEV3 #define PMU_CTL_LVDT_2V6 PMU_CTL_LVDT_LEV4 #define PMU_CTL_LVDT_2V7 PMU_CTL_LVDT_LEV5 #define PMU_CTL_LVDT_2V8 PMU_CTL_LVDT_LEV6 #define PMU_CTL_LVDT_2V9 PMU_CTL_LVDT_LEV7 #define PMU_CTL_BKPWEN_Pos (8U) #define PMU_CTL_BKPWEN_Msk (0x1U << PMU_CTL_BKPWEN_Pos) /*!< 0x00000100 */ #define PMU_CTL_BKPWEN PMU_CTL_BKPWEN_Msk /*!< Disable Backup Domain write protection */ /******************* Bit definition for PMU_CS register ********************/ #define PMU_CS_WUF_Pos (0U) #define PMU_CS_WUF_Msk (0x1U << PMU_CS_WUF_Pos) /*!< 0x00000001 */ #define PMU_CS_WUF PMU_CS_WUF_Msk /*!< Wakeup Flag */ #define PMU_CS_STBF_Pos (1U) #define PMU_CS_STBF_Msk (0x1U << PMU_CS_STBF_Pos) /*!< 0x00000002 */ #define PMU_CS_STBF PMU_CS_STBF_Msk /*!< Standby Flag */ #define PMU_CS_LVDF_Pos (2U) #define PMU_CS_LVDF_Msk (0x1U << PMU_CS_LVDF_Pos) /*!< 0x00000004 */ #define PMU_CS_LVDF PMU_CS_LVDF_Msk /*!< PVD Output */ #define PMU_CS_WUPEN_Pos (8U) #define PMU_CS_WUPEN_Msk (0x1U << PMU_CS_WUPEN_Pos) /*!< 0x00000100 */ #define PMU_CS_WUPEN PMU_CS_WUPEN_Msk /*!< Enable WKUP pin */ /******************************************************************************/ /* */ /* Backup registers */ /* */ /******************************************************************************/ /******************* Bit definition for BKP_DR1 register ********************/ #define BKP_DATA1_DATA_Pos (0U) #define BKP_DATA1_DATA_Msk (0xFFFFU << BKP_DATA1_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA1_DATA BKP_DATA1_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR2 register ********************/ #define BKP_DATA2_DATA_Pos (0U) #define BKP_DATA2_DATA_Msk (0xFFFFU << BKP_DATA2_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA2_DATA BKP_DATA2_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR3 register ********************/ #define BKP_DATA3_DATA_Pos (0U) #define BKP_DATA3_DATA_Msk (0xFFFFU << BKP_DATA3_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA3_DATA BKP_DATA3_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR4 register ********************/ #define BKP_DATA4_DATA_Pos (0U) #define BKP_DATA4_DATA_Msk (0xFFFFU << BKP_DATA4_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA4_DATA BKP_DATA4_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR5 register ********************/ #define BKP_DATA5_DATA_Pos (0U) #define BKP_DATA5_DATA_Msk (0xFFFFU << BKP_DATA5_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA5_DATA BKP_DATA5_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR6 register ********************/ #define BKP_DATA6_DATA_Pos (0U) #define BKP_DATA6_DATA_Msk (0xFFFFU << BKP_DATA6_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA6_DATA BKP_DATA6_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR7 register ********************/ #define BKP_DATA7_DATA_Pos (0U) #define BKP_DATA7_DATA_Msk (0xFFFFU << BKP_DATA7_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA7_DATA BKP_DATA7_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR8 register ********************/ #define BKP_DATA8_DATA_Pos (0U) #define BKP_DATA8_DATA_Msk (0xFFFFU << BKP_DATA8_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA8_DATA BKP_DATA8_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR9 register ********************/ #define BKP_DATA9_DATA_Pos (0U) #define BKP_DATA9_DATA_Msk (0xFFFFU << BKP_DATA9_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA9_DATA BKP_DATA9_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR10 register *******************/ #define BKP_DATA10_DATA_Pos (0U) #define BKP_DATA10_DATA_Msk (0xFFFFU << BKP_DATA10_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA10_DATA BKP_DATA10_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR11 register *******************/ #define BKP_DATA11_DATA_Pos (0U) #define BKP_DATA11_DATA_Msk (0xFFFFU << BKP_DATA11_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA11_DATA BKP_DATA11_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR12 register *******************/ #define BKP_DATA12_DATA_Pos (0U) #define BKP_DATA12_DATA_Msk (0xFFFFU << BKP_DATA12_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA12_DATA BKP_DATA12_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR13 register *******************/ #define BKP_DATA13_DATA_Pos (0U) #define BKP_DATA13_DATA_Msk (0xFFFFU << BKP_DATA13_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA13_DATA BKP_DATA13_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR14 register *******************/ #define BKP_DATA14_DATA_Pos (0U) #define BKP_DATA14_DATA_Msk (0xFFFFU << BKP_DATA14_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA14_DATA BKP_DATA14_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR15 register *******************/ #define BKP_DATA15_DATA_Pos (0U) #define BKP_DATA15_DATA_Msk (0xFFFFU << BKP_DATA15_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA15_DATA BKP_DATA15_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR16 register *******************/ #define BKP_DATA16_DATA_Pos (0U) #define BKP_DATA16_DATA_Msk (0xFFFFU << BKP_DATA16_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA16_DATA BKP_DATA16_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR17 register *******************/ #define BKP_DATA17_DATA_Pos (0U) #define BKP_DATA17_DATA_Msk (0xFFFFU << BKP_DATA17_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA17_DATA BKP_DATA17_DATA_Msk /*!< Backup data */ /****************** Bit definition for BKP_DR18 register ********************/ #define BKP_DATA18_DATA_Pos (0U) #define BKP_DATA18_DATA_Msk (0xFFFFU << BKP_DATA18_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA18_DATA BKP_DATA18_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR19 register *******************/ #define BKP_DATA19_DATA_Pos (0U) #define BKP_DATA19_DATA_Msk (0xFFFFU << BKP_DATA19_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA19_DATA BKP_DATA19_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR20 register *******************/ #define BKP_DATA20_DATA_Pos (0U) #define BKP_DATA20_DATA_Msk (0xFFFFU << BKP_DATA20_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA20_DATA BKP_DATA20_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR21 register *******************/ #define BKP_DATA21_DATA_Pos (0U) #define BKP_DATA21_DATA_Msk (0xFFFFU << BKP_DATA21_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA21_DATA BKP_DATA21_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR22 register *******************/ #define BKP_DATA22_DATA_Pos (0U) #define BKP_DATA22_DATA_Msk (0xFFFFU << BKP_DATA22_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA22_DATA BKP_DATA22_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR23 register *******************/ #define BKP_DATA23_DATA_Pos (0U) #define BKP_DATA23_DATA_Msk (0xFFFFU << BKP_DATA23_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA23_DATA BKP_DATA23_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR24 register *******************/ #define BKP_DATA24_DATA_Pos (0U) #define BKP_DATA24_DATA_Msk (0xFFFFU << BKP_DATA24_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA24_DATA BKP_DATA24_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR25 register *******************/ #define BKP_DATA25_DATA_Pos (0U) #define BKP_DATA25_DATA_Msk (0xFFFFU << BKP_DATA25_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA25_DATA BKP_DATA25_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR26 register *******************/ #define BKP_DATA26_DATA_Pos (0U) #define BKP_DATA26_DATA_Msk (0xFFFFU << BKP_DATA26_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA26_DATA BKP_DATA26_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR27 register *******************/ #define BKP_DATA27_DATA_Pos (0U) #define BKP_DATA27_DATA_Msk (0xFFFFU << BKP_DATA27_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA27_DATA BKP_DATA27_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR28 register *******************/ #define BKP_DATA28_DATA_Pos (0U) #define BKP_DATA28_DATA_Msk (0xFFFFU << BKP_DATA28_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA28_DATA BKP_DATA28_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR29 register *******************/ #define BKP_DATA29_DATA_Pos (0U) #define BKP_DATA29_DATA_Msk (0xFFFFU << BKP_DATA29_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA29_DATA BKP_DATA29_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR30 register *******************/ #define BKP_DATA30_DATA_Pos (0U) #define BKP_DATA30_DATA_Msk (0xFFFFU << BKP_DATA30_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA30_DATA BKP_DATA30_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR31 register *******************/ #define BKP_DATA31_DATA_Pos (0U) #define BKP_DATA31_DATA_Msk (0xFFFFU << BKP_DATA31_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA31_DATA BKP_DATA31_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR32 register *******************/ #define BKP_DATA32_DATA_Pos (0U) #define BKP_DATA32_DATA_Msk (0xFFFFU << BKP_DATA32_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA32_DATA BKP_DATA32_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR33 register *******************/ #define BKP_DATA33_DATA_Pos (0U) #define BKP_DATA33_DATA_Msk (0xFFFFU << BKP_DATA33_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA33_DATA BKP_DATA33_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR34 register *******************/ #define BKP_DATA34_DATA_Pos (0U) #define BKP_DATA34_DATA_Msk (0xFFFFU << BKP_DATA34_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA34_DATA BKP_DATA34_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR35 register *******************/ #define BKP_DATA35_DATA_Pos (0U) #define BKP_DATA35_DATA_Msk (0xFFFFU << BKP_DATA35_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA35_DATA BKP_DATA35_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR36 register *******************/ #define BKP_DATA36_DATA_Pos (0U) #define BKP_DATA36_DATA_Msk (0xFFFFU << BKP_DATA36_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA36_DATA BKP_DATA36_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR37 register *******************/ #define BKP_DATA37_DATA_Pos (0U) #define BKP_DATA37_DATA_Msk (0xFFFFU << BKP_DATA37_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA37_DATA BKP_DATA37_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR38 register *******************/ #define BKP_DATA38_DATA_Pos (0U) #define BKP_DATA38_DATA_Msk (0xFFFFU << BKP_DATA38_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA38_DATA BKP_DATA38_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR39 register *******************/ #define BKP_DATA39_DATA_Pos (0U) #define BKP_DATA39_DATA_Msk (0xFFFFU << BKP_DATA39_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA39_DATA BKP_DATA39_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR40 register *******************/ #define BKP_DATA40_DATA_Pos (0U) #define BKP_DATA40_DATA_Msk (0xFFFFU << BKP_DATA40_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA40_DATA BKP_DATA40_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR41 register *******************/ #define BKP_DATA41_DATA_Pos (0U) #define BKP_DATA41_DATA_Msk (0xFFFFU << BKP_DATA41_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA41_DATA BKP_DATA41_DATA_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR42 register *******************/ #define BKP_DATA42_DATA_Pos (0U) #define BKP_DATA42_DATA_Msk (0xFFFFU << BKP_DATA42_DATA_Pos) /*!< 0x0000FFFF */ #define BKP_DATA42_DATA BKP_DATA42_DATA_Msk /*!< Backup data */ #define RTC_BKP_NUMBER 42 /****************** Bit definition for BKP_OCTL register *******************/ #define BKP_OCTL_RCCV_Pos (0U) #define BKP_OCTL_RCCV_Msk (0x7FU << BKP_OCTL_RCCV_Pos) /*!< 0x0000007F */ #define BKP_OCTL_RCCV BKP_OCTL_RCCV_Msk /*!< Calibration value */ #define BKP_OCTL_COEN_Pos (7U) #define BKP_OCTL_COEN_Msk (0x1U << BKP_OCTL_COEN_Pos) /*!< 0x00000080 */ #define BKP_OCTL_COEN BKP_OCTL_COEN_Msk /*!< Calibration Clock Output */ #define BKP_OCTL_ASOEN_Pos (8U) #define BKP_OCTL_ASOEN_Msk (0x1U << BKP_OCTL_ASOEN_Pos) /*!< 0x00000100 */ #define BKP_OCTL_ASOEN BKP_OCTL_ASOEN_Msk /*!< Alarm or Second Output Enable */ #define BKP_OCTL_ROSEL_Pos (9U) #define BKP_OCTL_ROSEL_Msk (0x1U << BKP_OCTL_ROSEL_Pos) /*!< 0x00000200 */ #define BKP_OCTL_ROSEL BKP_OCTL_ROSEL_Msk /*!< Alarm or Second Output Selection */ /******************** Bit definition for BKP_TPCTL register ********************/ #define BKP_TPCTL_TPEN_Pos (0U) #define BKP_TPCTL_TPEN_Msk (0x1U << BKP_TPCTL_TPEN_Pos) /*!< 0x00000001 */ #define BKP_TPCTL_TPEN BKP_TPCTL_TPEN_Msk /*!< TAMPER pin enable */ #define BKP_TPCTL_TPAL_Pos (1U) #define BKP_TPCTL_TPAL_Msk (0x1U << BKP_TPCTL_TPAL_Pos) /*!< 0x00000002 */ #define BKP_TPCTL_TPAL BKP_TPCTL_TPAL_Msk /*!< TAMPER pin active level */ /******************* Bit definition for BKP_TPCS register ********************/ #define BKP_TPCS_TER_Pos (0U) #define BKP_TPCS_TER_Msk (0x1U << BKP_TPCS_TER_Pos) /*!< 0x00000001 */ #define BKP_TPCS_TER BKP_TPCS_TER_Msk /*!< Clear Tamper event */ #define BKP_TPCS_TIR_Pos (1U) #define BKP_TPCS_TIR_Msk (0x1U << BKP_TPCS_TIR_Pos) /*!< 0x00000002 */ #define BKP_TPCS_TIR BKP_TPCS_TIR_Msk /*!< Clear Tamper Interrupt */ #define BKP_TPCS_TPIE_Pos (2U) #define BKP_TPCS_TPIE_Msk (0x1U << BKP_TPCS_TPIE_Pos) /*!< 0x00000004 */ #define BKP_TPCS_TPIE BKP_TPCS_TPIE_Msk /*!< TAMPER Pin interrupt enable */ #define BKP_TPCS_TEF_Pos (8U) #define BKP_TPCS_TEF_Msk (0x1U << BKP_TPCS_TEF_Pos) /*!< 0x00000100 */ #define BKP_TPCS_TEF BKP_TPCS_TEF_Msk /*!< Tamper Event Flag */ #define BKP_TPCS_TIF_Pos (9U) #define BKP_TPCS_TIF_Msk (0x1U << BKP_TPCS_TIF_Pos) /*!< 0x00000200 */ #define BKP_TPCS_TIF BKP_TPCS_TIF_Msk /*!< Tamper Interrupt Flag */ /******************************************************************************/ /* */ /* Reset and Clock Control */ /* */ /******************************************************************************/ /******************** Bit definition for RCU_CTL register ********************/ #define RCU_CTL_IRC8MEN_Pos (0U) #define RCU_CTL_IRC8MEN_Msk (0x1U << RCU_CTL_IRC8MEN_Pos) /*!< 0x00000001 */ #define RCU_CTL_IRC8MEN RCU_CTL_IRC8MEN_Msk /*!< Internal High Speed clock enable */ #define RCU_CTL_IRC8MSTB_Pos (1U) #define RCU_CTL_IRC8MSTB_Msk (0x1U << RCU_CTL_IRC8MSTB_Pos) /*!< 0x00000002 */ #define RCU_CTL_IRC8MSTB RCU_CTL_IRC8MSTB_Msk /*!< Internal High Speed clock ready flag */ #define RCU_CTL_IRC8MADJ_Pos (3U) #define RCU_CTL_IRC8MADJ_Msk (0x1FU << RCU_CTL_IRC8MADJ_Pos) /*!< 0x000000F8 */ #define RCU_CTL_IRC8MADJ RCU_CTL_IRC8MADJ_Msk /*!< Internal High Speed clock trimming */ #define RCU_CTL_IRC8CALIB_Pos (8U) #define RCU_CTL_IRC8CALIB_Msk (0xFFU << RCU_CTL_IRC8CALIB_Pos) /*!< 0x0000FF00 */ #define RCU_CTL_IRC8CALIB RCU_CTL_IRC8CALIB_Msk /*!< Internal High Speed clock Calibration */ #define RCU_CTL_HXTALEN_Pos (16U) #define RCU_CTL_HXTALEN_Msk (0x1U << RCU_CTL_HXTALEN_Pos) /*!< 0x00010000 */ #define RCU_CTL_HXTALEN RCU_CTL_HXTALEN_Msk /*!< External High Speed clock enable */ #define RCU_CTL_HXTALSTB_Pos (17U) #define RCU_CTL_HXTALSTB_Msk (0x1U << RCU_CTL_HXTALSTB_Pos) /*!< 0x00020000 */ #define RCU_CTL_HXTALSTB RCU_CTL_HXTALSTB_Msk /*!< External High Speed clock ready flag */ #define RCU_CTL_HXTALBPS_Pos (18U) #define RCU_CTL_HXTALBPS_Msk (0x1U << RCU_CTL_HXTALBPS_Pos) /*!< 0x00040000 */ #define RCU_CTL_HXTALBPS RCU_CTL_HXTALBPS_Msk /*!< External High Speed clock Bypass */ #define RCU_CTL_CKMEN_Pos (19U) #define RCU_CTL_CKMEN_Msk (0x1U << RCU_CTL_CKMEN_Pos) /*!< 0x00080000 */ #define RCU_CTL_CKMEN RCU_CTL_CKMEN_Msk /*!< Clock Security System enable */ #define RCU_CTL_PLLEN_Pos (24U) #define RCU_CTL_PLLEN_Msk (0x1U << RCU_CTL_PLLEN_Pos) /*!< 0x01000000 */ #define RCU_CTL_PLLEN RCU_CTL_PLLEN_Msk /*!< PLL enable */ #define RCU_CTL_PLLSTB_Pos (25U) #define RCU_CTL_PLLSTB_Msk (0x1U << RCU_CTL_PLLSTB_Pos) /*!< 0x02000000 */ #define RCU_CTL_PLLSTB RCU_CTL_PLLSTB_Msk /*!< PLL clock ready flag */ #define RCU_CTL_PLL1EN_Pos (26U) #define RCU_CTL_PLL1EN_Msk (0x1U << RCU_CTL_PLL1EN_Pos) /*!< 0x04000000 */ #define RCU_CTL_PLL1EN RCU_CTL_PLL1EN_Msk /*!< PLL2 enable */ #define RCU_CTL_PLL1STB_Pos (27U) #define RCU_CTL_PLL1STB_Msk (0x1U << RCU_CTL_PLL1STB_Pos) /*!< 0x08000000 */ #define RCU_CTL_PLL1STB RCU_CTL_PLL1STB_Msk /*!< PLL2 clock ready flag */ #define RCU_CTL_PLL2EN_Pos (28U) #define RCU_CTL_PLL2EN_Msk (0x1U << RCU_CTL_PLL2EN_Pos) /*!< 0x10000000 */ #define RCU_CTL_PLL2EN RCU_CTL_PLL2EN_Msk /*!< PLL3 enable */ #define RCU_CTL_PLL2STB_Pos (29U) #define RCU_CTL_PLL2STB_Msk (0x1U << RCU_CTL_PLL2STB_Pos) /*!< 0x20000000 */ #define RCU_CTL_PLL2STB RCU_CTL_PLL2STB_Msk /*!< PLL3 clock ready flag */ /******************* Bit definition for RCU_CFG0 register *******************/ /*!< SW configuration */ #define RCU_CFG0_SCS_Pos (0U) #define RCU_CFG0_SCS_Msk (0x3U << RCU_CFG0_SCS_Pos) /*!< 0x00000003 */ #define RCU_CFG0_SCS RCU_CFG0_SCS_Msk /*!< SW[1:0] bits (System clock Switch) */ #define RCU_CFG0_SCS_0 (0x1U << RCU_CFG0_SCS_Pos) /*!< 0x00000001 */ #define RCU_CFG0_SCS_1 (0x2U << RCU_CFG0_SCS_Pos) /*!< 0x00000002 */ #define RCU_CFG0_SCS_IRC8M 0x00000000U /*!< IRC8M selected as system clock */ #define RCU_CFG0_SCS_HXTAL 0x00000001U /*!< HXTAL selected as system clock */ #define RCU_CFG0_SCS_PLL 0x00000002U /*!< PLL selected as system clock */ /*!< SWS configuration */ #define RCU_CFG0_SCSS_Pos (2U) #define RCU_CFG0_SCSS_Msk (0x3U << RCU_CFG0_SCSS_Pos) /*!< 0x0000000C */ #define RCU_CFG0_SCSS RCU_CFG0_SCSS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ #define RCU_CFG0_SCSS_0 (0x1U << RCU_CFG0_SCSS_Pos) /*!< 0x00000004 */ #define RCU_CFG0_SCSS_1 (0x2U << RCU_CFG0_SCSS_Pos) /*!< 0x00000008 */ #define RCU_CFG0_SCSS_IRC8M 0x00000000U /*!< IRC8M oscillator used as system clock */ #define RCU_CFG0_SCSS_HXTAL 0x00000004U /*!< HXTAL oscillator used as system clock */ #define RCU_CFG0_SCSS_PLL 0x00000008U /*!< PLL used as system clock */ /*!< HPRE configuration */ #define RCU_CFG0_AHBPSC_Pos (4U) #define RCU_CFG0_AHBPSC_Msk (0xFU << RCU_CFG0_AHBPSC_Pos) /*!< 0x000000F0 */ #define RCU_CFG0_AHBPSC RCU_CFG0_AHBPSC_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ #define RCU_CFG0_AHBPSC_0 (0x1U << RCU_CFG0_AHBPSC_Pos) /*!< 0x00000010 */ #define RCU_CFG0_AHBPSC_1 (0x2U << RCU_CFG0_AHBPSC_Pos) /*!< 0x00000020 */ #define RCU_CFG0_AHBPSC_2 (0x4U << RCU_CFG0_AHBPSC_Pos) /*!< 0x00000040 */ #define RCU_CFG0_AHBPSC_3 (0x8U << RCU_CFG0_AHBPSC_Pos) /*!< 0x00000080 */ #define RCU_CFG0_AHBPSC_DIV1 0x00000000U /*!< SYSCLK not divided */ #define RCU_CFG0_AHBPSC_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ #define RCU_CFG0_AHBPSC_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ #define RCU_CFG0_AHBPSC_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ #define RCU_CFG0_AHBPSC_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ #define RCU_CFG0_AHBPSC_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ #define RCU_CFG0_AHBPSC_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ #define RCU_CFG0_AHBPSC_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ #define RCU_CFG0_AHBPSC_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ #define RCU_CFG0_APB1PSC_Pos (8U) #define RCU_CFG0_APB1PSC_Msk (0x7U << RCU_CFG0_APB1PSC_Pos) /*!< 0x00000700 */ #define RCU_CFG0_APB1PSC RCU_CFG0_APB1PSC_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ #define RCU_CFG0_APB1PSC_0 (0x1U << RCU_CFG0_APB1PSC_Pos) /*!< 0x00000100 */ #define RCU_CFG0_APB1PSC_1 (0x2U << RCU_CFG0_APB1PSC_Pos) /*!< 0x00000200 */ #define RCU_CFG0_APB1PSC_2 (0x4U << RCU_CFG0_APB1PSC_Pos) /*!< 0x00000400 */ #define RCU_CFG0_APB1PSC_DIV1 0x00000000U /*!< HCLK not divided */ #define RCU_CFG0_APB1PSC_DIV2 0x00000400U /*!< HCLK divided by 2 */ #define RCU_CFG0_APB1PSC_DIV4 0x00000500U /*!< HCLK divided by 4 */ #define RCU_CFG0_APB1PSC_DIV8 0x00000600U /*!< HCLK divided by 8 */ #define RCU_CFG0_APB1PSC_DIV16 0x00000700U /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ #define RCU_CFG0_APB2PSC_Pos (11U) #define RCU_CFG0_APB2PSC_Msk (0x7U << RCU_CFG0_APB2PSC_Pos) /*!< 0x00003800 */ #define RCU_CFG0_APB2PSC RCU_CFG0_APB2PSC_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ #define RCU_CFG0_APB2PSC_0 (0x1U << RCU_CFG0_APB2PSC_Pos) /*!< 0x00000800 */ #define RCU_CFG0_APB2PSC_1 (0x2U << RCU_CFG0_APB2PSC_Pos) /*!< 0x00001000 */ #define RCU_CFG0_APB2PSC_2 (0x4U << RCU_CFG0_APB2PSC_Pos) /*!< 0x00002000 */ #define RCU_CFG0_APB2PSC_DIV1 0x00000000U /*!< HCLK not divided */ #define RCU_CFG0_APB2PSC_DIV2 0x00002000U /*!< HCLK divided by 2 */ #define RCU_CFG0_APB2PSC_DIV4 0x00002800U /*!< HCLK divided by 4 */ #define RCU_CFG0_APB2PSC_DIV8 0x00003000U /*!< HCLK divided by 8 */ #define RCU_CFG0_APB2PSC_DIV16 0x00003800U /*!< HCLK divided by 16 */ /*!< ADCPPRE configuration */ #define RCU_CFG0_ADCPSC_Pos (14U) #define RCU_CFG0_ADCPSC_Msk (0x3U << RCU_CFG0_ADCPSC_Pos) /*!< 0x0000C000 */ #define RCU_CFG0_ADCPSC RCU_CFG0_ADCPSC_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ #define RCU_CFG0_ADCPSC_0 (0x1U << RCU_CFG0_ADCPSC_Pos) /*!< 0x00004000 */ #define RCU_CFG0_ADCPSC_1 (0x2U << RCU_CFG0_ADCPSC_Pos) /*!< 0x00008000 */ #define RCU_CFG0_ADCPSC_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ #define RCU_CFG0_ADCPSC_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ #define RCU_CFG0_ADCPSC_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ #define RCU_CFG0_ADCPSC_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ #define RCU_CFG0_PLLSEL_Pos (16U) #define RCU_CFG0_PLLSEL_Msk (0x1U << RCU_CFG0_PLLSEL_Pos) /*!< 0x00010000 */ #define RCU_CFG0_PLLSEL RCU_CFG0_PLLSEL_Msk /*!< PLL entry clock source */ #define RCU_CFG0_PREDV0_LSB_Pos (17U) #define RCU_CFG0_PREDV0_LSB_Msk (0x1U << RCU_CFG0_PREDV0_LSB_Pos) /*!< 0x00020000 */ #define RCU_CFG0_PREDV0_LSB RCU_CFG0_PREDV0_LSB_Msk /*!< HXTAL divider for PLL entry */ /*!< PLLMUL configuration */ #define RCU_CFG0_PLLMF_Pos (18U) #define RCU_CFG0_PLLMF_Msk (0xFU << RCU_CFG0_PLLMF_Pos) /*!< 0x003C0000 */ #define RCU_CFG0_PLLMF RCU_CFG0_PLLMF_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ #define RCU_CFG0_PLLMF_0 (0x1U << RCU_CFG0_PLLMF_Pos) /*!< 0x00040000 */ #define RCU_CFG0_PLLMF_1 (0x2U << RCU_CFG0_PLLMF_Pos) /*!< 0x00080000 */ #define RCU_CFG0_PLLMF_2 (0x4U << RCU_CFG0_PLLMF_Pos) /*!< 0x00100000 */ #define RCU_CFG0_PLLMF_3 (0x8U << RCU_CFG0_PLLMF_Pos) /*!< 0x00200000 */ #define RCU_CFG0_PREDV0_LSB_PREDV0 0x00000000U /*!< PREDV0 clock not divided for PLL entry */ #define RCU_CFG0_PREDV0_LSB_PREDV0_DIV2 0x00020000U /*!< PREDV0 clock divided by 2 for PLL entry */ #define RCU_CFG0_PLLMF4_Pos (19U) #define RCU_CFG0_PLLMF4_Msk (0x1U << RCU_CFG0_PLLMF4_Pos) /*!< 0x00080000 */ #define RCU_CFG0_PLLMF4 RCU_CFG0_PLLMF4_Msk /*!< PLL input clock * 4 */ #define RCU_CFG0_PLLMF5_Pos (18U) #define RCU_CFG0_PLLMF5_Msk (0x3U << RCU_CFG0_PLLMF5_Pos) /*!< 0x000C0000 */ #define RCU_CFG0_PLLMF5 RCU_CFG0_PLLMF5_Msk /*!< PLL input clock * 5 */ #define RCU_CFG0_PLLMF6_Pos (20U) #define RCU_CFG0_PLLMF6_Msk (0x1U << RCU_CFG0_PLLMF6_Pos) /*!< 0x00100000 */ #define RCU_CFG0_PLLMF6 RCU_CFG0_PLLMF6_Msk /*!< PLL input clock * 6 */ #define RCU_CFG0_PLLMF7_Pos (18U) #define RCU_CFG0_PLLMF7_Msk (0x5U << RCU_CFG0_PLLMF7_Pos) /*!< 0x00140000 */ #define RCU_CFG0_PLLMF7 RCU_CFG0_PLLMF7_Msk /*!< PLL input clock * 7 */ #define RCU_CFG0_PLLMF8_Pos (19U) #define RCU_CFG0_PLLMF8_Msk (0x3U << RCU_CFG0_PLLMF8_Pos) /*!< 0x00180000 */ #define RCU_CFG0_PLLMF8 RCU_CFG0_PLLMF8_Msk /*!< PLL input clock * 8 */ #define RCU_CFG0_PLLMF9_Pos (18U) #define RCU_CFG0_PLLMF9_Msk (0x7U << RCU_CFG0_PLLMF9_Pos) /*!< 0x001C0000 */ #define RCU_CFG0_PLLMF9 RCU_CFG0_PLLMF9_Msk /*!< PLL input clock * 9 */ #define RCU_CFG0_PLLMF6_5 0x00340000U /*!< PLL input clock * 6.5 */ #define RCU_CFG0_USBFSPSC_Pos (22U) #define RCU_CFG0_USBFSPSC_Msk (0x1U << RCU_CFG0_USBFSPSC_Pos) /*!< 0x00400000 */ #define RCU_CFG0_USBFSPSC RCU_CFG0_USBFSPSC_Msk /*!< USB OTG FS prescaler */ /*!< MCO configuration */ #define RCU_CFG0_CKOUT0SEL_Pos (24U) #define RCU_CFG0_CKOUT0SEL_Msk (0xFU << RCU_CFG0_CKOUT0SEL_Pos) /*!< 0x0F000000 */ #define RCU_CFG0_CKOUT0SEL RCU_CFG0_CKOUT0SEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ #define RCU_CFG0_CKOUT0SEL_0 (0x1U << RCU_CFG0_CKOUT0SEL_Pos) /*!< 0x01000000 */ #define RCU_CFG0_CKOUT0SEL_1 (0x2U << RCU_CFG0_CKOUT0SEL_Pos) /*!< 0x02000000 */ #define RCU_CFG0_CKOUT0SEL_2 (0x4U << RCU_CFG0_CKOUT0SEL_Pos) /*!< 0x04000000 */ #define RCU_CFG0_CKOUT0SEL_3 (0x8U << RCU_CFG0_CKOUT0SEL_Pos) /*!< 0x08000000 */ #define RCU_CFG0_CKOUT0SEL_NOCLOCK 0x00000000U /*!< No clock */ #define RCU_CFG0_CKOUT0SEL_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ #define RCU_CFG0_CKOUT0SEL_IRC8M 0x05000000U /*!< IRC8M clock selected as MCO source */ #define RCU_CFG0_CKOUT0SEL_HXTAL 0x06000000U /*!< HXTAL clock selected as MCO source */ #define RCU_CFG0_CKOUT0SEL_CK_PLL_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ #define RCU_CFG0_CKOUT0SEL_CK_PLL1 0x08000000U /*!< PLL2 clock selected as MCO source*/ #define RCU_CFG0_CKOUT0SEL_CK_PLL2_DIV2 0x09000000U /*!< PLL3 clock divided by 2 selected as MCO source*/ #define RCU_CFG0_CKOUT0SEL_EXT_HXTAL 0x0A000000U /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ #define RCU_CFG0_CKOUT0SEL_CK_PLL2 0x0B000000U /*!< PLL3 clock selected as MCO source */ /*!<****************** Bit definition for RCU_INT register ********************/ #define RCU_INT_IRC40KSTBIF_Pos (0U) #define RCU_INT_IRC40KSTBIF_Msk (0x1U << RCU_INT_IRC40KSTBIF_Pos) /*!< 0x00000001 */ #define RCU_INT_IRC40KSTBIF RCU_INT_IRC40KSTBIF_Msk /*!< IRC40K Ready Interrupt flag */ #define RCU_INT_LXTALSTBIF_Pos (1U) #define RCU_INT_LXTALSTBIF_Msk (0x1U << RCU_INT_LXTALSTBIF_Pos) /*!< 0x00000002 */ #define RCU_INT_LXTALSTBIF RCU_INT_LXTALSTBIF_Msk /*!< LXTAL Ready Interrupt flag */ #define RCU_INT_IRC8MSTBIF_Pos (2U) #define RCU_INT_IRC8MSTBIF_Msk (0x1U << RCU_INT_IRC8MSTBIF_Pos) /*!< 0x00000004 */ #define RCU_INT_IRC8MSTBIF RCU_INT_IRC8MSTBIF_Msk /*!< IRC8M Ready Interrupt flag */ #define RCU_INT_HXTALSTBIF_Pos (3U) #define RCU_INT_HXTALSTBIF_Msk (0x1U << RCU_INT_HXTALSTBIF_Pos) /*!< 0x00000008 */ #define RCU_INT_HXTALSTBIF RCU_INT_HXTALSTBIF_Msk /*!< HXTAL Ready Interrupt flag */ #define RCU_INT_PLLSTBIF_Pos (4U) #define RCU_INT_PLLSTBIF_Msk (0x1U << RCU_INT_PLLSTBIF_Pos) /*!< 0x00000010 */ #define RCU_INT_PLLSTBIF RCU_INT_PLLSTBIF_Msk /*!< PLL Ready Interrupt flag */ #define RCU_INT_CKMIF_Pos (7U) #define RCU_INT_CKMIF_Msk (0x1U << RCU_INT_CKMIF_Pos) /*!< 0x00000080 */ #define RCU_INT_CKMIF RCU_INT_CKMIF_Msk /*!< Clock Security System Interrupt flag */ #define RCU_INT_IRC40KSTBIE_Pos (8U) #define RCU_INT_IRC40KSTBIE_Msk (0x1U << RCU_INT_IRC40KSTBIE_Pos) /*!< 0x00000100 */ #define RCU_INT_IRC40KSTBIE RCU_INT_IRC40KSTBIE_Msk /*!< IRC40K Ready Interrupt Enable */ #define RCU_INT_LXTALSTBIE_Pos (9U) #define RCU_INT_LXTALSTBIE_Msk (0x1U << RCU_INT_LXTALSTBIE_Pos) /*!< 0x00000200 */ #define RCU_INT_LXTALSTBIE RCU_INT_LXTALSTBIE_Msk /*!< LXTAL Ready Interrupt Enable */ #define RCU_INT_IRC8MSTBIE_Pos (10U) #define RCU_INT_IRC8MSTBIE_Msk (0x1U << RCU_INT_IRC8MSTBIE_Pos) /*!< 0x00000400 */ #define RCU_INT_IRC8MSTBIE RCU_INT_IRC8MSTBIE_Msk /*!< IRC8M Ready Interrupt Enable */ #define RCU_INT_HXTALSTBIE_Pos (11U) #define RCU_INT_HXTALSTBIE_Msk (0x1U << RCU_INT_HXTALSTBIE_Pos) /*!< 0x00000800 */ #define RCU_INT_HXTALSTBIE RCU_INT_HXTALSTBIE_Msk /*!< HXTAL Ready Interrupt Enable */ #define RCU_INT_PLLSTBIE_Pos (12U) #define RCU_INT_PLLSTBIE_Msk (0x1U << RCU_INT_PLLSTBIE_Pos) /*!< 0x00001000 */ #define RCU_INT_PLLSTBIE RCU_INT_PLLSTBIE_Msk /*!< PLL Ready Interrupt Enable */ #define RCU_INT_IRC40KSTBIC_Pos (16U) #define RCU_INT_IRC40KSTBIC_Msk (0x1U << RCU_INT_IRC40KSTBIC_Pos) /*!< 0x00010000 */ #define RCU_INT_IRC40KSTBIC RCU_INT_IRC40KSTBIC_Msk /*!< IRC40K Ready Interrupt Clear */ #define RCU_INT_LXTALSTBIC_Pos (17U) #define RCU_INT_LXTALSTBIC_Msk (0x1U << RCU_INT_LXTALSTBIC_Pos) /*!< 0x00020000 */ #define RCU_INT_LXTALSTBIC RCU_INT_LXTALSTBIC_Msk /*!< LXTAL Ready Interrupt Clear */ #define RCU_INT_IRC8MSTBIC_Pos (18U) #define RCU_INT_IRC8MSTBIC_Msk (0x1U << RCU_INT_IRC8MSTBIC_Pos) /*!< 0x00040000 */ #define RCU_INT_IRC8MSTBIC RCU_INT_IRC8MSTBIC_Msk /*!< IRC8M Ready Interrupt Clear */ #define RCU_INT_HXTALSTBIC_Pos (19U) #define RCU_INT_HXTALSTBIC_Msk (0x1U << RCU_INT_HXTALSTBIC_Pos) /*!< 0x00080000 */ #define RCU_INT_HXTALSTBIC RCU_INT_HXTALSTBIC_Msk /*!< HXTAL Ready Interrupt Clear */ #define RCU_INT_PLLSTBIC_Pos (20U) #define RCU_INT_PLLSTBIC_Msk (0x1U << RCU_INT_PLLSTBIC_Pos) /*!< 0x00100000 */ #define RCU_INT_PLLSTBIC RCU_INT_PLLSTBIC_Msk /*!< PLL Ready Interrupt Clear */ #define RCU_INT_CKMIC_Pos (23U) #define RCU_INT_CKMIC_Msk (0x1U << RCU_INT_CKMIC_Pos) /*!< 0x00800000 */ #define RCU_INT_CKMIC RCU_INT_CKMIC_Msk /*!< Clock Security System Interrupt Clear */ #define RCU_INT_PLL1STBIF_Pos (5U) #define RCU_INT_PLL1STBIF_Msk (0x1U << RCU_INT_PLL1STBIF_Pos) /*!< 0x00000020 */ #define RCU_INT_PLL1STBIF RCU_INT_PLL1STBIF_Msk /*!< PLL2 Ready Interrupt flag */ #define RCU_INT_PLL2STBIF_Pos (6U) #define RCU_INT_PLL2STBIF_Msk (0x1U << RCU_INT_PLL2STBIF_Pos) /*!< 0x00000040 */ #define RCU_INT_PLL2STBIF RCU_INT_PLL2STBIF_Msk /*!< PLL3 Ready Interrupt flag */ #define RCU_INT_PLL1STBIE_Pos (13U) #define RCU_INT_PLL1STBIE_Msk (0x1U << RCU_INT_PLL1STBIE_Pos) /*!< 0x00002000 */ #define RCU_INT_PLL1STBIE RCU_INT_PLL1STBIE_Msk /*!< PLL2 Ready Interrupt Enable */ #define RCU_INT_PLL2STBIE_Pos (14U) #define RCU_INT_PLL2STBIE_Msk (0x1U << RCU_INT_PLL2STBIE_Pos) /*!< 0x00004000 */ #define RCU_INT_PLL2STBIE RCU_INT_PLL2STBIE_Msk /*!< PLL3 Ready Interrupt Enable */ #define RCU_INT_PLL1STBIC_Pos (21U) #define RCU_INT_PLL1STBIC_Msk (0x1U << RCU_INT_PLL1STBIC_Pos) /*!< 0x00200000 */ #define RCU_INT_PLL1STBIC RCU_INT_PLL1STBIC_Msk /*!< PLL2 Ready Interrupt Clear */ #define RCU_INT_PLL2STBIC_Pos (22U) #define RCU_INT_PLL2STBIC_Msk (0x1U << RCU_INT_PLL2STBIC_Pos) /*!< 0x00400000 */ #define RCU_INT_PLL2STBIC RCU_INT_PLL2STBIC_Msk /*!< PLL3 Ready Interrupt Clear */ /***************** Bit definition for RCU_APB2RST register *****************/ #define RCU_APB2RST_AFRST_Pos (0U) #define RCU_APB2RST_AFRST_Msk (0x1U << RCU_APB2RST_AFRST_Pos) /*!< 0x00000001 */ #define RCU_APB2RST_AFRST RCU_APB2RST_AFRST_Msk /*!< Alternate Function I/O reset */ #define RCU_APB2RST_PARST_Pos (2U) #define RCU_APB2RST_PARST_Msk (0x1U << RCU_APB2RST_PARST_Pos) /*!< 0x00000004 */ #define RCU_APB2RST_PARST RCU_APB2RST_PARST_Msk /*!< I/O port A reset */ #define RCU_APB2RST_PBRST_Pos (3U) #define RCU_APB2RST_PBRST_Msk (0x1U << RCU_APB2RST_PBRST_Pos) /*!< 0x00000008 */ #define RCU_APB2RST_PBRST RCU_APB2RST_PBRST_Msk /*!< I/O port B reset */ #define RCU_APB2RST_PCRST_Pos (4U) #define RCU_APB2RST_PCRST_Msk (0x1U << RCU_APB2RST_PCRST_Pos) /*!< 0x00000010 */ #define RCU_APB2RST_PCRST RCU_APB2RST_PCRST_Msk /*!< I/O port C reset */ #define RCU_APB2RST_PDRST_Pos (5U) #define RCU_APB2RST_PDRST_Msk (0x1U << RCU_APB2RST_PDRST_Pos) /*!< 0x00000020 */ #define RCU_APB2RST_PDRST RCU_APB2RST_PDRST_Msk /*!< I/O port D reset */ #define RCU_APB2RST_ADC0RST_Pos (9U) #define RCU_APB2RST_ADC0RST_Msk (0x1U << RCU_APB2RST_ADC0RST_Pos) /*!< 0x00000200 */ #define RCU_APB2RST_ADC0RST RCU_APB2RST_ADC0RST_Msk /*!< ADC 1 interface reset */ #define RCU_APB2RST_ADC1RST_Pos (10U) #define RCU_APB2RST_ADC1RST_Msk (0x1U << RCU_APB2RST_ADC1RST_Pos) /*!< 0x00000400 */ #define RCU_APB2RST_ADC1RST RCU_APB2RST_ADC1RST_Msk /*!< ADC 2 interface reset */ #define RCU_APB2RST_TIMER0RST_Pos (11U) #define RCU_APB2RST_TIMER0RST_Msk (0x1U << RCU_APB2RST_TIMER0RST_Pos) /*!< 0x00000800 */ #define RCU_APB2RST_TIMER0RST RCU_APB2RST_TIMER0RST_Msk /*!< TIM0 Timer reset */ #define RCU_APB2RST_SPI0RST_Pos (12U) #define RCU_APB2RST_SPI0RST_Msk (0x1U << RCU_APB2RST_SPI0RST_Pos) /*!< 0x00001000 */ #define RCU_APB2RST_SPI0RST RCU_APB2RST_SPI0RST_Msk /*!< SPI 1 reset */ #define RCU_APB2RST_USART0RST_Pos (14U) #define RCU_APB2RST_USART0RST_Msk (0x1U << RCU_APB2RST_USART0RST_Pos) /*!< 0x00004000 */ #define RCU_APB2RST_USART0RST RCU_APB2RST_USART0RST_Msk /*!< USART0 reset */ #define RCU_APB2RST_PERST_Pos (6U) #define RCU_APB2RST_PERST_Msk (0x1U << RCU_APB2RST_PERST_Pos) /*!< 0x00000040 */ #define RCU_APB2RST_PERST RCU_APB2RST_PERST_Msk /*!< I/O port E reset */ /***************** Bit definition for RCU_APB1RST register *****************/ #define RCU_APB1RST_TIMER1RST_Pos (0U) #define RCU_APB1RST_TIMER1RST_Msk (0x1U << RCU_APB1RST_TIMER1RST_Pos) /*!< 0x00000001 */ #define RCU_APB1RST_TIMER1RST RCU_APB1RST_TIMER1RST_Msk /*!< Timer 2 reset */ #define RCU_APB1RST_TIMER2RST_Pos (1U) #define RCU_APB1RST_TIMER2RST_Msk (0x1U << RCU_APB1RST_TIMER2RST_Pos) /*!< 0x00000002 */ #define RCU_APB1RST_TIMER2RST RCU_APB1RST_TIMER2RST_Msk /*!< Timer 3 reset */ #define RCU_APB1RST_WWDGTRST_Pos (11U) #define RCU_APB1RST_WWDGTRST_Msk (0x1U << RCU_APB1RST_WWDGTRST_Pos) /*!< 0x00000800 */ #define RCU_APB1RST_WWDGTRST RCU_APB1RST_WWDGTRST_Msk /*!< Window Watchdog reset */ #define RCU_APB1RST_USART1RST_Pos (17U) #define RCU_APB1RST_USART1RST_Msk (0x1U << RCU_APB1RST_USART1RST_Pos) /*!< 0x00020000 */ #define RCU_APB1RST_USART1RST RCU_APB1RST_USART1RST_Msk /*!< USART 2 reset */ #define RCU_APB1RST_I2C0RST_Pos (21U) #define RCU_APB1RST_I2C0RST_Msk (0x1U << RCU_APB1RST_I2C0RST_Pos) /*!< 0x00200000 */ #define RCU_APB1RST_I2C0RST RCU_APB1RST_I2C0RST_Msk /*!< I2C 1 reset */ #define RCU_APB1RST_CAN0RST_Pos (25U) #define RCU_APB1RST_CAN0RST_Msk (0x1U << RCU_APB1RST_CAN0RST_Pos) /*!< 0x02000000 */ #define RCU_APB1RST_CAN0RST RCU_APB1RST_CAN0RST_Msk /*!< CAN0 reset */ #define RCU_APB1RST_BKPIRST_Pos (27U) #define RCU_APB1RST_BKPIRST_Msk (0x1U << RCU_APB1RST_BKPIRST_Pos) /*!< 0x08000000 */ #define RCU_APB1RST_BKPIRST RCU_APB1RST_BKPIRST_Msk /*!< Backup interface reset */ #define RCU_APB1RST_PMURST_Pos (28U) #define RCU_APB1RST_PMURST_Msk (0x1U << RCU_APB1RST_PMURST_Pos) /*!< 0x10000000 */ #define RCU_APB1RST_PMURST RCU_APB1RST_PMURST_Msk /*!< Power interface reset */ #define RCU_APB1RST_TIMER3RST_Pos (2U) #define RCU_APB1RST_TIMER3RST_Msk (0x1U << RCU_APB1RST_TIMER3RST_Pos) /*!< 0x00000004 */ #define RCU_APB1RST_TIMER3RST RCU_APB1RST_TIMER3RST_Msk /*!< Timer 4 reset */ #define RCU_APB1RST_SPI1RST_Pos (14U) #define RCU_APB1RST_SPI1RST_Msk (0x1U << RCU_APB1RST_SPI1RST_Pos) /*!< 0x00004000 */ #define RCU_APB1RST_SPI1RST RCU_APB1RST_SPI1RST_Msk /*!< SPI 2 reset */ #define RCU_APB1RST_USART2RST_Pos (18U) #define RCU_APB1RST_USART2RST_Msk (0x1U << RCU_APB1RST_USART2RST_Pos) /*!< 0x00040000 */ #define RCU_APB1RST_USART2RST RCU_APB1RST_USART2RST_Msk /*!< USART 3 reset */ #define RCU_APB1RST_I2C1RST_Pos (22U) #define RCU_APB1RST_I2C1RST_Msk (0x1U << RCU_APB1RST_I2C1RST_Pos) /*!< 0x00400000 */ #define RCU_APB1RST_I2C1RST RCU_APB1RST_I2C1RST_Msk /*!< I2C 2 reset */ #define RCU_APB1RST_TIMER4RST_Pos (3U) #define RCU_APB1RST_TIMER4RST_Msk (0x1U << RCU_APB1RST_TIMER4RST_Pos) /*!< 0x00000008 */ #define RCU_APB1RST_TIMER4RST RCU_APB1RST_TIMER4RST_Msk /*!< Timer 5 reset */ #define RCU_APB1RST_TIMER5RST_Pos (4U) #define RCU_APB1RST_TIMER5RST_Msk (0x1U << RCU_APB1RST_TIMER5RST_Pos) /*!< 0x00000010 */ #define RCU_APB1RST_TIMER5RST RCU_APB1RST_TIMER5RST_Msk /*!< Timer 6 reset */ #define RCU_APB1RST_TIMER6RST_Pos (5U) #define RCU_APB1RST_TIMER6RST_Msk (0x1U << RCU_APB1RST_TIMER6RST_Pos) /*!< 0x00000020 */ #define RCU_APB1RST_TIMER6RST RCU_APB1RST_TIMER6RST_Msk /*!< Timer 7 reset */ #define RCU_APB1RST_SPI2RST_Pos (15U) #define RCU_APB1RST_SPI2RST_Msk (0x1U << RCU_APB1RST_SPI2RST_Pos) /*!< 0x00008000 */ #define RCU_APB1RST_SPI2RST RCU_APB1RST_SPI2RST_Msk /*!< SPI 3 reset */ #define RCU_APB1RST_UART3RST_Pos (19U) #define RCU_APB1RST_UART3RST_Msk (0x1U << RCU_APB1RST_UART3RST_Pos) /*!< 0x00080000 */ #define RCU_APB1RST_UART3RST RCU_APB1RST_UART3RST_Msk /*!< UART 4 reset */ #define RCU_APB1RST_UART4RST_Pos (20U) #define RCU_APB1RST_UART4RST_Msk (0x1U << RCU_APB1RST_UART4RST_Pos) /*!< 0x00100000 */ #define RCU_APB1RST_UART4RST RCU_APB1RST_UART4RST_Msk /*!< UART 5 reset */ #define RCU_APB1RST_CAN1RST_Pos (26U) #define RCU_APB1RST_CAN1RST_Msk (0x1U << RCU_APB1RST_CAN1RST_Pos) /*!< 0x04000000 */ #define RCU_APB1RST_CAN1RST RCU_APB1RST_CAN1RST_Msk /*!< CAN1 reset */ #define RCU_APB1RST_DACRST_Pos (29U) #define RCU_APB1RST_DACRST_Msk (0x1U << RCU_APB1RST_DACRST_Pos) /*!< 0x20000000 */ #define RCU_APB1RST_DACRST RCU_APB1RST_DACRST_Msk /*!< DAC interface reset */ /****************** Bit definition for RCU_AHBEN register ******************/ #define RCU_AHBEN_DMA0EN_Pos (0U) #define RCU_AHBEN_DMA0EN_Msk (0x1U << RCU_AHBEN_DMA0EN_Pos) /*!< 0x00000001 */ #define RCU_AHBEN_DMA0EN RCU_AHBEN_DMA0EN_Msk /*!< DMA0 clock enable */ #define RCU_AHBEN_SRAMSPEN_Pos (2U) #define RCU_AHBEN_SRAMSPEN_Msk (0x1U << RCU_AHBEN_SRAMSPEN_Pos) /*!< 0x00000004 */ #define RCU_AHBEN_SRAMSPEN RCU_AHBEN_SRAMSPEN_Msk /*!< SRAM interface clock enable */ #define RCU_AHBEN_FMCSPEN_Pos (4U) #define RCU_AHBEN_FMCSPEN_Msk (0x1U << RCU_AHBEN_FMCSPEN_Pos) /*!< 0x00000010 */ #define RCU_AHBEN_FMCSPEN RCU_AHBEN_FMCSPEN_Msk /*!< FLITF clock enable */ #define RCU_AHBEN_CRCEN_Pos (6U) #define RCU_AHBEN_CRCEN_Msk (0x1U << RCU_AHBEN_CRCEN_Pos) /*!< 0x00000040 */ #define RCU_AHBEN_CRCEN RCU_AHBEN_CRCEN_Msk /*!< CRC clock enable */ #define RCU_AHBEN_DMA1EN_Pos (1U) #define RCU_AHBEN_DMA1EN_Msk (0x1U << RCU_AHBEN_DMA1EN_Pos) /*!< 0x00000002 */ #define RCU_AHBEN_DMA1EN RCU_AHBEN_DMA1EN_Msk /*!< DMA1 clock enable */ #define RCU_AHBEN_EXMCEN_Pos (8U) #define RCU_AHBEN_EXMCEN_Msk (0x1U << RCU_AHBEN_USBFSEN_Pos) /*!< 0x00001000 */ #define RCU_AHBEN_EXMCEN RCU_AHBEN_USBFSEN_Msk /*!< USB OTG FS clock enable */ #define RCU_AHBEN_USBFSEN_Pos (12U) #define RCU_AHBEN_USBFSEN_Msk (0x1U << RCU_AHBEN_USBFSEN_Pos) /*!< 0x00001000 */ #define RCU_AHBEN_USBFSEN RCU_AHBEN_USBFSEN_Msk /*!< USB OTG FS clock enable */ /****************** Bit definition for RCU_APB2EN register *****************/ #define RCU_APB2EN_AFEN_Pos (0U) #define RCU_APB2EN_AFEN_Msk (0x1U << RCU_APB2EN_AFEN_Pos) /*!< 0x00000001 */ #define RCU_APB2EN_AFEN RCU_APB2EN_AFEN_Msk /*!< Alternate Function I/O clock enable */ #define RCU_APB2EN_PAEN_Pos (2U) #define RCU_APB2EN_PAEN_Msk (0x1U << RCU_APB2EN_PAEN_Pos) /*!< 0x00000004 */ #define RCU_APB2EN_PAEN RCU_APB2EN_PAEN_Msk /*!< I/O port A clock enable */ #define RCU_APB2EN_PBEN_Pos (3U) #define RCU_APB2EN_PBEN_Msk (0x1U << RCU_APB2EN_PBEN_Pos) /*!< 0x00000008 */ #define RCU_APB2EN_PBEN RCU_APB2EN_PBEN_Msk /*!< I/O port B clock enable */ #define RCU_APB2EN_PCEN_Pos (4U) #define RCU_APB2EN_PCEN_Msk (0x1U << RCU_APB2EN_PCEN_Pos) /*!< 0x00000010 */ #define RCU_APB2EN_PCEN RCU_APB2EN_PCEN_Msk /*!< I/O port C clock enable */ #define RCU_APB2EN_PDEN_Pos (5U) #define RCU_APB2EN_PDEN_Msk (0x1U << RCU_APB2EN_PDEN_Pos) /*!< 0x00000020 */ #define RCU_APB2EN_PDEN RCU_APB2EN_PDEN_Msk /*!< I/O port D clock enable */ #define RCU_APB2EN_ADC0EN_Pos (9U) #define RCU_APB2EN_ADC0EN_Msk (0x1U << RCU_APB2EN_ADC0EN_Pos) /*!< 0x00000200 */ #define RCU_APB2EN_ADC0EN RCU_APB2EN_ADC0EN_Msk /*!< ADC 1 interface clock enable */ #define RCU_APB2EN_ADC1EN_Pos (10U) #define RCU_APB2EN_ADC1EN_Msk (0x1U << RCU_APB2EN_ADC1EN_Pos) /*!< 0x00000400 */ #define RCU_APB2EN_ADC1EN RCU_APB2EN_ADC1EN_Msk /*!< ADC 2 interface clock enable */ #define RCU_APB2EN_TIMER0EN_Pos (11U) #define RCU_APB2EN_TIMER0EN_Msk (0x1U << RCU_APB2EN_TIMER0EN_Pos) /*!< 0x00000800 */ #define RCU_APB2EN_TIMER0EN RCU_APB2EN_TIMER0EN_Msk /*!< TIM0 Timer clock enable */ #define RCU_APB2EN_SPI0EN_Pos (12U) #define RCU_APB2EN_SPI0EN_Msk (0x1U << RCU_APB2EN_SPI0EN_Pos) /*!< 0x00001000 */ #define RCU_APB2EN_SPI0EN RCU_APB2EN_SPI0EN_Msk /*!< SPI 1 clock enable */ #define RCU_APB2EN_USART0EN_Pos (14U) #define RCU_APB2EN_USART0EN_Msk (0x1U << RCU_APB2EN_USART0EN_Pos) /*!< 0x00004000 */ #define RCU_APB2EN_USART0EN RCU_APB2EN_USART0EN_Msk /*!< USART0 clock enable */ #define RCU_APB2EN_PEEN_Pos (6U) #define RCU_APB2EN_PEEN_Msk (0x1U << RCU_APB2EN_PEEN_Pos) /*!< 0x00000040 */ #define RCU_APB2EN_PEEN RCU_APB2EN_PEEN_Msk /*!< I/O port E clock enable */ /***************** Bit definition for RCU_APB1EN register ******************/ #define RCU_APB1EN_TIMER1EN_Pos (0U) #define RCU_APB1EN_TIMER1EN_Msk (0x1U << RCU_APB1EN_TIMER1EN_Pos) /*!< 0x00000001 */ #define RCU_APB1EN_TIMER1EN RCU_APB1EN_TIMER1EN_Msk /*!< Timer 2 clock enabled*/ #define RCU_APB1EN_TIMER2EN_Pos (1U) #define RCU_APB1EN_TIMER2EN_Msk (0x1U << RCU_APB1EN_TIMER2EN_Pos) /*!< 0x00000002 */ #define RCU_APB1EN_TIMER2EN RCU_APB1EN_TIMER2EN_Msk /*!< Timer 3 clock enable */ #define RCU_APB1EN_WWDGTEN_Pos (11U) #define RCU_APB1EN_WWDGTEN_Msk (0x1U << RCU_APB1EN_WWDGTEN_Pos) /*!< 0x00000800 */ #define RCU_APB1EN_WWDGTEN RCU_APB1EN_WWDGTEN_Msk /*!< Window Watchdog clock enable */ #define RCU_APB1EN_USART1EN_Pos (17U) #define RCU_APB1EN_USART1EN_Msk (0x1U << RCU_APB1EN_USART1EN_Pos) /*!< 0x00020000 */ #define RCU_APB1EN_USART1EN RCU_APB1EN_USART1EN_Msk /*!< USART 2 clock enable */ #define RCU_APB1EN_I2C0EN_Pos (21U) #define RCU_APB1EN_I2C0EN_Msk (0x1U << RCU_APB1EN_I2C0EN_Pos) /*!< 0x00200000 */ #define RCU_APB1EN_I2C0EN RCU_APB1EN_I2C0EN_Msk /*!< I2C 1 clock enable */ #define RCU_APB1EN_CAN0EN_Pos (25U) #define RCU_APB1EN_CAN0EN_Msk (0x1U << RCU_APB1EN_CAN0EN_Pos) /*!< 0x02000000 */ #define RCU_APB1EN_CAN0EN RCU_APB1EN_CAN0EN_Msk /*!< CAN0 clock enable */ #define RCU_APB1EN_BKPIEN_Pos (27U) #define RCU_APB1EN_BKPIEN_Msk (0x1U << RCU_APB1EN_BKPIEN_Pos) /*!< 0x08000000 */ #define RCU_APB1EN_BKPIEN RCU_APB1EN_BKPIEN_Msk /*!< Backup interface clock enable */ #define RCU_APB1EN_PMUEN_Pos (28U) #define RCU_APB1EN_PMUEN_Msk (0x1U << RCU_APB1EN_PMUEN_Pos) /*!< 0x10000000 */ #define RCU_APB1EN_PMUEN RCU_APB1EN_PMUEN_Msk /*!< Power interface clock enable */ #define RCU_APB1EN_TIMER3EN_Pos (2U) #define RCU_APB1EN_TIMER3EN_Msk (0x1U << RCU_APB1EN_TIMER3EN_Pos) /*!< 0x00000004 */ #define RCU_APB1EN_TIMER3EN RCU_APB1EN_TIMER3EN_Msk /*!< Timer 4 clock enable */ #define RCU_APB1EN_SPI1EN_Pos (14U) #define RCU_APB1EN_SPI1EN_Msk (0x1U << RCU_APB1EN_SPI1EN_Pos) /*!< 0x00004000 */ #define RCU_APB1EN_SPI1EN RCU_APB1EN_SPI1EN_Msk /*!< SPI 2 clock enable */ #define RCU_APB1EN_USART2EN_Pos (18U) #define RCU_APB1EN_USART2EN_Msk (0x1U << RCU_APB1EN_USART2EN_Pos) /*!< 0x00040000 */ #define RCU_APB1EN_USART2EN RCU_APB1EN_USART2EN_Msk /*!< USART 3 clock enable */ #define RCU_APB1EN_I2C1EN_Pos (22U) #define RCU_APB1EN_I2C1EN_Msk (0x1U << RCU_APB1EN_I2C1EN_Pos) /*!< 0x00400000 */ #define RCU_APB1EN_I2C1EN RCU_APB1EN_I2C1EN_Msk /*!< I2C 2 clock enable */ #define RCU_APB1EN_TIMER4EN_Pos (3U) #define RCU_APB1EN_TIMER4EN_Msk (0x1U << RCU_APB1EN_TIMER4EN_Pos) /*!< 0x00000008 */ #define RCU_APB1EN_TIMER4EN RCU_APB1EN_TIMER4EN_Msk /*!< Timer 5 clock enable */ #define RCU_APB1EN_TIMER5EN_Pos (4U) #define RCU_APB1EN_TIMER5EN_Msk (0x1U << RCU_APB1EN_TIMER5EN_Pos) /*!< 0x00000010 */ #define RCU_APB1EN_TIMER5EN RCU_APB1EN_TIMER5EN_Msk /*!< Timer 6 clock enable */ #define RCU_APB1EN_TIMER6EN_Pos (5U) #define RCU_APB1EN_TIMER6EN_Msk (0x1U << RCU_APB1EN_TIMER6EN_Pos) /*!< 0x00000020 */ #define RCU_APB1EN_TIMER6EN RCU_APB1EN_TIMER6EN_Msk /*!< Timer 7 clock enable */ #define RCU_APB1EN_SPI2EN_Pos (15U) #define RCU_APB1EN_SPI2EN_Msk (0x1U << RCU_APB1EN_SPI2EN_Pos) /*!< 0x00008000 */ #define RCU_APB1EN_SPI2EN RCU_APB1EN_SPI2EN_Msk /*!< SPI 3 clock enable */ #define RCU_APB1EN_UART3EN_Pos (19U) #define RCU_APB1EN_UART3EN_Msk (0x1U << RCU_APB1EN_UART3EN_Pos) /*!< 0x00080000 */ #define RCU_APB1EN_UART3EN RCU_APB1EN_UART3EN_Msk /*!< UART 4 clock enable */ #define RCU_APB1EN_UART4EN_Pos (20U) #define RCU_APB1EN_UART4EN_Msk (0x1U << RCU_APB1EN_UART4EN_Pos) /*!< 0x00100000 */ #define RCU_APB1EN_UART4EN RCU_APB1EN_UART4EN_Msk /*!< UART 5 clock enable */ #define RCU_APB1EN_CAN1EN_Pos (26U) #define RCU_APB1EN_CAN1EN_Msk (0x1U << RCU_APB1EN_CAN1EN_Pos) /*!< 0x04000000 */ #define RCU_APB1EN_CAN1EN RCU_APB1EN_CAN1EN_Msk /*!< CAN1 clock enable */ #define RCU_APB1EN_DACEN_Pos (29U) #define RCU_APB1EN_DACEN_Msk (0x1U << RCU_APB1EN_DACEN_Pos) /*!< 0x20000000 */ #define RCU_APB1EN_DACEN RCU_APB1EN_DACEN_Msk /*!< DAC interface clock enable */ /******************* Bit definition for RCU_BDCTL register *******************/ #define RCU_BDCTL_LXTALEN_Pos (0U) #define RCU_BDCTL_LXTALEN_Msk (0x1U << RCU_BDCTL_LXTALEN_Pos) /*!< 0x00000001 */ #define RCU_BDCTL_LXTALEN RCU_BDCTL_LXTALEN_Msk /*!< External Low Speed oscillator enable */ #define RCU_BDCTL_LXTALSTB_Pos (1U) #define RCU_BDCTL_LXTALSTB_Msk (0x1U << RCU_BDCTL_LXTALSTB_Pos) /*!< 0x00000002 */ #define RCU_BDCTL_LXTALSTB RCU_BDCTL_LXTALSTB_Msk /*!< External Low Speed oscillator Ready */ #define RCU_BDCTL_LXTALBPS_Pos (2U) #define RCU_BDCTL_LXTALBPS_Msk (0x1U << RCU_BDCTL_LXTALBPS_Pos) /*!< 0x00000004 */ #define RCU_BDCTL_LXTALBPS RCU_BDCTL_LXTALBPS_Msk /*!< External Low Speed oscillator Bypass */ #define RCU_BDCTL_RTCSRC_Pos (8U) #define RCU_BDCTL_RTCSRC_Msk (0x3U << RCU_BDCTL_RTCSRC_Pos) /*!< 0x00000300 */ #define RCU_BDCTL_RTCSRC RCU_BDCTL_RTCSRC_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ #define RCU_BDCTL_RTCSRC_0 (0x1U << RCU_BDCTL_RTCSRC_Pos) /*!< 0x00000100 */ #define RCU_BDCTL_RTCSRC_1 (0x2U << RCU_BDCTL_RTCSRC_Pos) /*!< 0x00000200 */ /*!< RTC congiguration */ #define RCU_BDCTL_RTCSRC_NOCLOCK 0x00000000U /*!< No clock */ #define RCU_BDCTL_RTCSRC_LXTAL 0x00000100U /*!< LXTAL oscillator clock used as RTC clock */ #define RCU_BDCTL_RTCSRC_IRC40K 0x00000200U /*!< IRC40K oscillator clock used as RTC clock */ #define RCU_BDCTL_RTCSRC_HXTAL 0x00000300U /*!< HXTAL oscillator clock divided by 128 used as RTC clock */ #define RCU_BDCTL_RTCEN_Pos (15U) #define RCU_BDCTL_RTCEN_Msk (0x1U << RCU_BDCTL_RTCEN_Pos) /*!< 0x00008000 */ #define RCU_BDCTL_RTCEN RCU_BDCTL_RTCEN_Msk /*!< RTC clock enable */ #define RCU_BDCTL_BKPRST_Pos (16U) #define RCU_BDCTL_BKPRST_Msk (0x1U << RCU_BDCTL_BKPRST_Pos) /*!< 0x00010000 */ #define RCU_BDCTL_BKPRST RCU_BDCTL_BKPRST_Msk /*!< Backup domain software reset */ /******************* Bit definition for RCU_RSTSCK register ********************/ #define RCU_RSTSCK_IRC40KEN_Pos (0U) #define RCU_RSTSCK_IRC40KEN_Msk (0x1U << RCU_RSTSCK_IRC40KEN_Pos) /*!< 0x00000001 */ #define RCU_RSTSCK_IRC40KEN RCU_RSTSCK_IRC40KEN_Msk /*!< Internal Low Speed oscillator enable */ #define RCU_RSTSCK_IRC40KSTB_Pos (1U) #define RCU_RSTSCK_IRC40KSTB_Msk (0x1U << RCU_RSTSCK_IRC40KSTB_Pos) /*!< 0x00000002 */ #define RCU_RSTSCK_IRC40KSTB RCU_RSTSCK_IRC40KSTB_Msk /*!< Internal Low Speed oscillator Ready */ #define RCU_RSTSCK_RSTCF_Pos (24U) #define RCU_RSTSCK_RSTCF_Msk (0x1U << RCU_RSTSCK_RSTCF_Pos) /*!< 0x01000000 */ #define RCU_RSTSCK_RSTCF RCU_RSTSCK_RSTCF_Msk /*!< Remove reset flag */ #define RCU_RSTSCK_EPRSTF_Pos (26U) #define RCU_RSTSCK_EPRSTF_Msk (0x1U << RCU_RSTSCK_EPRSTF_Pos) /*!< 0x04000000 */ #define RCU_RSTSCK_EPRSTF RCU_RSTSCK_EPRSTF_Msk /*!< PIN reset flag */ #define RCU_RSTSCK_PORRSTF_Pos (27U) #define RCU_RSTSCK_PORRSTF_Msk (0x1U << RCU_RSTSCK_PORRSTF_Pos) /*!< 0x08000000 */ #define RCU_RSTSCK_PORRSTF RCU_RSTSCK_PORRSTF_Msk /*!< POR/PDR reset flag */ #define RCU_RSTSCK_SWRSTF_Pos (28U) #define RCU_RSTSCK_SWRSTF_Msk (0x1U << RCU_RSTSCK_SWRSTF_Pos) /*!< 0x10000000 */ #define RCU_RSTSCK_SWRSTF RCU_RSTSCK_SWRSTF_Msk /*!< Software Reset flag */ #define RCU_RSTSCK_FWDGTRSTF_Pos (29U) #define RCU_RSTSCK_FWDGTRSTF_Msk (0x1U << RCU_RSTSCK_FWDGTRSTF_Pos) /*!< 0x20000000 */ #define RCU_RSTSCK_FWDGTRSTF RCU_RSTSCK_FWDGTRSTF_Msk /*!< Independent Watchdog reset flag */ #define RCU_RSTSCK_WWDGTRSTF_Pos (30U) #define RCU_RSTSCK_WWDGTRSTF_Msk (0x1U << RCU_RSTSCK_WWDGTRSTF_Pos) /*!< 0x40000000 */ #define RCU_RSTSCK_WWDGTRSTF RCU_RSTSCK_WWDGTRSTF_Msk /*!< Window watchdog reset flag */ #define RCU_RSTSCK_LPRSTF_Pos (31U) #define RCU_RSTSCK_LPRSTF_Msk (0x1U << RCU_RSTSCK_LPRSTF_Pos) /*!< 0x80000000 */ #define RCU_RSTSCK_LPRSTF RCU_RSTSCK_LPRSTF_Msk /*!< Low-Power reset flag */ /******************* Bit definition for RCU_AHBRST register ****************/ #define RCU_AHBRST_USBFSRST_Pos (12U) #define RCU_AHBRST_USBFSRST_Msk (0x1U << RCU_AHBRST_USBFSRST_Pos) /*!< 0x00001000 */ #define RCU_AHBRST_USBFSRST RCU_AHBRST_USBFSRST_Msk /*!< USB OTG FS reset */ /******************************************************************************/ /* */ /* General Purpose and Alternate Function I/O */ /* */ /******************************************************************************/ /******************* Bit definition for GPIO_CTL0 register *******************/ #define GPIO_CTL0_MODE_Pos (0U) #define GPIO_CTL0_MODE_Msk (0x33333333U << GPIO_CTL0_MODE_Pos) /*!< 0x33333333 */ #define GPIO_CTL0_MODE GPIO_CTL0_MODE_Msk /*!< Port x mode bits */ #define GPIO_CTL0_MD0_Pos (0U) #define GPIO_CTL0_MD0_Msk (0x3U << GPIO_CTL0_MD0_Pos) /*!< 0x00000003 */ #define GPIO_CTL0_MD0 GPIO_CTL0_MD0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ #define GPIO_CTL0_MD0_0 (0x1U << GPIO_CTL0_MD0_Pos) /*!< 0x00000001 */ #define GPIO_CTL0_MD0_1 (0x2U << GPIO_CTL0_MD0_Pos) /*!< 0x00000002 */ #define GPIO_CTL0_MD1_Pos (4U) #define GPIO_CTL0_MD1_Msk (0x3U << GPIO_CTL0_MD1_Pos) /*!< 0x00000030 */ #define GPIO_CTL0_MD1 GPIO_CTL0_MD1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ #define GPIO_CTL0_MD1_0 (0x1U << GPIO_CTL0_MD1_Pos) /*!< 0x00000010 */ #define GPIO_CTL0_MD1_1 (0x2U << GPIO_CTL0_MD1_Pos) /*!< 0x00000020 */ #define GPIO_CTL0_MD2_Pos (8U) #define GPIO_CTL0_MD2_Msk (0x3U << GPIO_CTL0_MD2_Pos) /*!< 0x00000300 */ #define GPIO_CTL0_MD2 GPIO_CTL0_MD2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ #define GPIO_CTL0_MD2_0 (0x1U << GPIO_CTL0_MD2_Pos) /*!< 0x00000100 */ #define GPIO_CTL0_MD2_1 (0x2U << GPIO_CTL0_MD2_Pos) /*!< 0x00000200 */ #define GPIO_CTL0_MD3_Pos (12U) #define GPIO_CTL0_MD3_Msk (0x3U << GPIO_CTL0_MD3_Pos) /*!< 0x00003000 */ #define GPIO_CTL0_MD3 GPIO_CTL0_MD3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ #define GPIO_CTL0_MD3_0 (0x1U << GPIO_CTL0_MD3_Pos) /*!< 0x00001000 */ #define GPIO_CTL0_MD3_1 (0x2U << GPIO_CTL0_MD3_Pos) /*!< 0x00002000 */ #define GPIO_CTL0_MD4_Pos (16U) #define GPIO_CTL0_MD4_Msk (0x3U << GPIO_CTL0_MD4_Pos) /*!< 0x00030000 */ #define GPIO_CTL0_MD4 GPIO_CTL0_MD4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ #define GPIO_CTL0_MD4_0 (0x1U << GPIO_CTL0_MD4_Pos) /*!< 0x00010000 */ #define GPIO_CTL0_MD4_1 (0x2U << GPIO_CTL0_MD4_Pos) /*!< 0x00020000 */ #define GPIO_CTL0_MD5_Pos (20U) #define GPIO_CTL0_MD5_Msk (0x3U << GPIO_CTL0_MD5_Pos) /*!< 0x00300000 */ #define GPIO_CTL0_MD5 GPIO_CTL0_MD5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ #define GPIO_CTL0_MD5_0 (0x1U << GPIO_CTL0_MD5_Pos) /*!< 0x00100000 */ #define GPIO_CTL0_MD5_1 (0x2U << GPIO_CTL0_MD5_Pos) /*!< 0x00200000 */ #define GPIO_CTL0_MD6_Pos (24U) #define GPIO_CTL0_MD6_Msk (0x3U << GPIO_CTL0_MD6_Pos) /*!< 0x03000000 */ #define GPIO_CTL0_MD6 GPIO_CTL0_MD6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ #define GPIO_CTL0_MD6_0 (0x1U << GPIO_CTL0_MD6_Pos) /*!< 0x01000000 */ #define GPIO_CTL0_MD6_1 (0x2U << GPIO_CTL0_MD6_Pos) /*!< 0x02000000 */ #define GPIO_CTL0_MD7_Pos (28U) #define GPIO_CTL0_MD7_Msk (0x3U << GPIO_CTL0_MD7_Pos) /*!< 0x30000000 */ #define GPIO_CTL0_MD7 GPIO_CTL0_MD7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ #define GPIO_CTL0_MD7_0 (0x1U << GPIO_CTL0_MD7_Pos) /*!< 0x10000000 */ #define GPIO_CTL0_MD7_1 (0x2U << GPIO_CTL0_MD7_Pos) /*!< 0x20000000 */ #define GPIO_CTL0_CTL_Pos (2U) #define GPIO_CTL0_CTL_Msk (0x33333333U << GPIO_CTL0_CTL_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CTL0_CTL GPIO_CTL0_CTL_Msk /*!< Port x configuration bits */ #define GPIO_CTL0_CTL0_Pos (2U) #define GPIO_CTL0_CTL0_Msk (0x3U << GPIO_CTL0_CTL0_Pos) /*!< 0x0000000C */ #define GPIO_CTL0_CTL0 GPIO_CTL0_CTL0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ #define GPIO_CTL0_CTL0_0 (0x1U << GPIO_CTL0_CTL0_Pos) /*!< 0x00000004 */ #define GPIO_CTL0_CTL0_1 (0x2U << GPIO_CTL0_CTL0_Pos) /*!< 0x00000008 */ #define GPIO_CTL0_CTL1_Pos (6U) #define GPIO_CTL0_CTL1_Msk (0x3U << GPIO_CTL0_CTL1_Pos) /*!< 0x000000C0 */ #define GPIO_CTL0_CTL1 GPIO_CTL0_CTL1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ #define GPIO_CTL0_CTL1_0 (0x1U << GPIO_CTL0_CTL1_Pos) /*!< 0x00000040 */ #define GPIO_CTL0_CTL1_1 (0x2U << GPIO_CTL0_CTL1_Pos) /*!< 0x00000080 */ #define GPIO_CTL0_CTL2_Pos (10U) #define GPIO_CTL0_CTL2_Msk (0x3U << GPIO_CTL0_CTL2_Pos) /*!< 0x00000C00 */ #define GPIO_CTL0_CTL2 GPIO_CTL0_CTL2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ #define GPIO_CTL0_CTL2_0 (0x1U << GPIO_CTL0_CTL2_Pos) /*!< 0x00000400 */ #define GPIO_CTL0_CTL2_1 (0x2U << GPIO_CTL0_CTL2_Pos) /*!< 0x00000800 */ #define GPIO_CTL0_CTL3_Pos (14U) #define GPIO_CTL0_CTL3_Msk (0x3U << GPIO_CTL0_CTL3_Pos) /*!< 0x0000C000 */ #define GPIO_CTL0_CTL3 GPIO_CTL0_CTL3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ #define GPIO_CTL0_CTL3_0 (0x1U << GPIO_CTL0_CTL3_Pos) /*!< 0x00004000 */ #define GPIO_CTL0_CTL3_1 (0x2U << GPIO_CTL0_CTL3_Pos) /*!< 0x00008000 */ #define GPIO_CTL0_CTL4_Pos (18U) #define GPIO_CTL0_CTL4_Msk (0x3U << GPIO_CTL0_CTL4_Pos) /*!< 0x000C0000 */ #define GPIO_CTL0_CTL4 GPIO_CTL0_CTL4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ #define GPIO_CTL0_CTL4_0 (0x1U << GPIO_CTL0_CTL4_Pos) /*!< 0x00040000 */ #define GPIO_CTL0_CTL4_1 (0x2U << GPIO_CTL0_CTL4_Pos) /*!< 0x00080000 */ #define GPIO_CTL0_CTL5_Pos (22U) #define GPIO_CTL0_CTL5_Msk (0x3U << GPIO_CTL0_CTL5_Pos) /*!< 0x00C00000 */ #define GPIO_CTL0_CTL5 GPIO_CTL0_CTL5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ #define GPIO_CTL0_CTL5_0 (0x1U << GPIO_CTL0_CTL5_Pos) /*!< 0x00400000 */ #define GPIO_CTL0_CTL5_1 (0x2U << GPIO_CTL0_CTL5_Pos) /*!< 0x00800000 */ #define GPIO_CTL0_CTL6_Pos (26U) #define GPIO_CTL0_CTL6_Msk (0x3U << GPIO_CTL0_CTL6_Pos) /*!< 0x0C000000 */ #define GPIO_CTL0_CTL6 GPIO_CTL0_CTL6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ #define GPIO_CTL0_CTL6_0 (0x1U << GPIO_CTL0_CTL6_Pos) /*!< 0x04000000 */ #define GPIO_CTL0_CTL6_1 (0x2U << GPIO_CTL0_CTL6_Pos) /*!< 0x08000000 */ #define GPIO_CTL0_CTL7_Pos (30U) #define GPIO_CTL0_CTL7_Msk (0x3U << GPIO_CTL0_CTL7_Pos) /*!< 0xC0000000 */ #define GPIO_CTL0_CTL7 GPIO_CTL0_CTL7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ #define GPIO_CTL0_CTL7_0 (0x1U << GPIO_CTL0_CTL7_Pos) /*!< 0x40000000 */ #define GPIO_CTL0_CTL7_1 (0x2U << GPIO_CTL0_CTL7_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_CTL1 register *******************/ #define GPIO_CTL1_MD_Pos (0U) #define GPIO_CTL1_MD_Msk (0x33333333U << GPIO_CTL1_MD_Pos) /*!< 0x33333333 */ #define GPIO_CTL1_MD GPIO_CTL1_MD_Msk /*!< Port x mode bits */ #define GPIO_CTL1_MD8_Pos (0U) #define GPIO_CTL1_MD8_Msk (0x3U << GPIO_CTL1_MD8_Pos) /*!< 0x00000003 */ #define GPIO_CTL1_MD8 GPIO_CTL1_MD8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ #define GPIO_CTL1_MD8_0 (0x1U << GPIO_CTL1_MD8_Pos) /*!< 0x00000001 */ #define GPIO_CTL1_MD8_1 (0x2U << GPIO_CTL1_MD8_Pos) /*!< 0x00000002 */ #define GPIO_CTL1_MD9_Pos (4U) #define GPIO_CTL1_MD9_Msk (0x3U << GPIO_CTL1_MD9_Pos) /*!< 0x00000030 */ #define GPIO_CTL1_MD9 GPIO_CTL1_MD9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ #define GPIO_CTL1_MD9_0 (0x1U << GPIO_CTL1_MD9_Pos) /*!< 0x00000010 */ #define GPIO_CTL1_MD9_1 (0x2U << GPIO_CTL1_MD9_Pos) /*!< 0x00000020 */ #define GPIO_CTL1_MD10_Pos (8U) #define GPIO_CTL1_MD10_Msk (0x3U << GPIO_CTL1_MD10_Pos) /*!< 0x00000300 */ #define GPIO_CTL1_MD10 GPIO_CTL1_MD10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ #define GPIO_CTL1_MD10_0 (0x1U << GPIO_CTL1_MD10_Pos) /*!< 0x00000100 */ #define GPIO_CTL1_MD10_1 (0x2U << GPIO_CTL1_MD10_Pos) /*!< 0x00000200 */ #define GPIO_CTL1_MD11_Pos (12U) #define GPIO_CTL1_MD11_Msk (0x3U << GPIO_CTL1_MD11_Pos) /*!< 0x00003000 */ #define GPIO_CTL1_MD11 GPIO_CTL1_MD11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ #define GPIO_CTL1_MD11_0 (0x1U << GPIO_CTL1_MD11_Pos) /*!< 0x00001000 */ #define GPIO_CTL1_MD11_1 (0x2U << GPIO_CTL1_MD11_Pos) /*!< 0x00002000 */ #define GPIO_CTL1_MD12_Pos (16U) #define GPIO_CTL1_MD12_Msk (0x3U << GPIO_CTL1_MD12_Pos) /*!< 0x00030000 */ #define GPIO_CTL1_MD12 GPIO_CTL1_MD12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ #define GPIO_CTL1_MD12_0 (0x1U << GPIO_CTL1_MD12_Pos) /*!< 0x00010000 */ #define GPIO_CTL1_MD12_1 (0x2U << GPIO_CTL1_MD12_Pos) /*!< 0x00020000 */ #define GPIO_CTL1_MD13_Pos (20U) #define GPIO_CTL1_MD13_Msk (0x3U << GPIO_CTL1_MD13_Pos) /*!< 0x00300000 */ #define GPIO_CTL1_MD13 GPIO_CTL1_MD13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ #define GPIO_CTL1_MD13_0 (0x1U << GPIO_CTL1_MD13_Pos) /*!< 0x00100000 */ #define GPIO_CTL1_MD13_1 (0x2U << GPIO_CTL1_MD13_Pos) /*!< 0x00200000 */ #define GPIO_CTL1_MD14_Pos (24U) #define GPIO_CTL1_MD14_Msk (0x3U << GPIO_CTL1_MD14_Pos) /*!< 0x03000000 */ #define GPIO_CTL1_MD14 GPIO_CTL1_MD14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ #define GPIO_CTL1_MD14_0 (0x1U << GPIO_CTL1_MD14_Pos) /*!< 0x01000000 */ #define GPIO_CTL1_MD14_1 (0x2U << GPIO_CTL1_MD14_Pos) /*!< 0x02000000 */ #define GPIO_CTL1_MD15_Pos (28U) #define GPIO_CTL1_MD15_Msk (0x3U << GPIO_CTL1_MD15_Pos) /*!< 0x30000000 */ #define GPIO_CTL1_MD15 GPIO_CTL1_MD15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ #define GPIO_CTL1_MD15_0 (0x1U << GPIO_CTL1_MD15_Pos) /*!< 0x10000000 */ #define GPIO_CTL1_MD15_1 (0x2U << GPIO_CTL1_MD15_Pos) /*!< 0x20000000 */ #define GPIO_CTL1_CNF_Pos (2U) #define GPIO_CTL1_CNF_Msk (0x33333333U << GPIO_CTL1_CNF_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CTL1_CNF GPIO_CTL1_CNF_Msk /*!< Port x configuration bits */ #define GPIO_CTL1_CTL8_Pos (2U) #define GPIO_CTL1_CTL8_Msk (0x3U << GPIO_CTL1_CTL8_Pos) /*!< 0x0000000C */ #define GPIO_CTL1_CTL8 GPIO_CTL1_CTL8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ #define GPIO_CTL1_CTL8_0 (0x1U << GPIO_CTL1_CTL8_Pos) /*!< 0x00000004 */ #define GPIO_CTL1_CTL8_1 (0x2U << GPIO_CTL1_CTL8_Pos) /*!< 0x00000008 */ #define GPIO_CTL1_CTL9_Pos (6U) #define GPIO_CTL1_CTL9_Msk (0x3U << GPIO_CTL1_CTL9_Pos) /*!< 0x000000C0 */ #define GPIO_CTL1_CTL9 GPIO_CTL1_CTL9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ #define GPIO_CTL1_CTL9_0 (0x1U << GPIO_CTL1_CTL9_Pos) /*!< 0x00000040 */ #define GPIO_CTL1_CTL9_1 (0x2U << GPIO_CTL1_CTL9_Pos) /*!< 0x00000080 */ #define GPIO_CTL1_CTL10_Pos (10U) #define GPIO_CTL1_CTL10_Msk (0x3U << GPIO_CTL1_CTL10_Pos) /*!< 0x00000C00 */ #define GPIO_CTL1_CTL10 GPIO_CTL1_CTL10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ #define GPIO_CTL1_CTL10_0 (0x1U << GPIO_CTL1_CTL10_Pos) /*!< 0x00000400 */ #define GPIO_CTL1_CTL10_1 (0x2U << GPIO_CTL1_CTL10_Pos) /*!< 0x00000800 */ #define GPIO_CTL1_CTL11_Pos (14U) #define GPIO_CTL1_CTL11_Msk (0x3U << GPIO_CTL1_CTL11_Pos) /*!< 0x0000C000 */ #define GPIO_CTL1_CTL11 GPIO_CTL1_CTL11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ #define GPIO_CTL1_CTL11_0 (0x1U << GPIO_CTL1_CTL11_Pos) /*!< 0x00004000 */ #define GPIO_CTL1_CTL11_1 (0x2U << GPIO_CTL1_CTL11_Pos) /*!< 0x00008000 */ #define GPIO_CTL1_CTL12_Pos (18U) #define GPIO_CTL1_CTL12_Msk (0x3U << GPIO_CTL1_CTL12_Pos) /*!< 0x000C0000 */ #define GPIO_CTL1_CTL12 GPIO_CTL1_CTL12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ #define GPIO_CTL1_CTL12_0 (0x1U << GPIO_CTL1_CTL12_Pos) /*!< 0x00040000 */ #define GPIO_CTL1_CTL12_1 (0x2U << GPIO_CTL1_CTL12_Pos) /*!< 0x00080000 */ #define GPIO_CTL1_CTL13_Pos (22U) #define GPIO_CTL1_CTL13_Msk (0x3U << GPIO_CTL1_CTL13_Pos) /*!< 0x00C00000 */ #define GPIO_CTL1_CTL13 GPIO_CTL1_CTL13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ #define GPIO_CTL1_CTL13_0 (0x1U << GPIO_CTL1_CTL13_Pos) /*!< 0x00400000 */ #define GPIO_CTL1_CTL13_1 (0x2U << GPIO_CTL1_CTL13_Pos) /*!< 0x00800000 */ #define GPIO_CTL1_CTL14_Pos (26U) #define GPIO_CTL1_CTL14_Msk (0x3U << GPIO_CTL1_CTL14_Pos) /*!< 0x0C000000 */ #define GPIO_CTL1_CTL14 GPIO_CTL1_CTL14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ #define GPIO_CTL1_CTL14_0 (0x1U << GPIO_CTL1_CTL14_Pos) /*!< 0x04000000 */ #define GPIO_CTL1_CTL14_1 (0x2U << GPIO_CTL1_CTL14_Pos) /*!< 0x08000000 */ #define GPIO_CTL1_CTL15_Pos (30U) #define GPIO_CTL1_CTL15_Msk (0x3U << GPIO_CTL1_CTL15_Pos) /*!< 0xC0000000 */ #define GPIO_CTL1_CTL15 GPIO_CTL1_CTL15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ #define GPIO_CTL1_CTL15_0 (0x1U << GPIO_CTL1_CTL15_Pos) /*!< 0x40000000 */ #define GPIO_CTL1_CTL15_1 (0x2U << GPIO_CTL1_CTL15_Pos) /*!< 0x80000000 */ /*!<****************** Bit definition for GPIO_IDR register *******************/ #define GPIO_ISTAT_ISTAT0_Pos (0U) #define GPIO_ISTAT_ISTAT0_Msk (0x1U << GPIO_ISTAT_ISTAT0_Pos) /*!< 0x00000001 */ #define GPIO_ISTAT_ISTAT0 GPIO_ISTAT_ISTAT0_Msk /*!< Port input data, bit 0 */ #define GPIO_ISTAT_ISTAT1_Pos (1U) #define GPIO_ISTAT_ISTAT1_Msk (0x1U << GPIO_ISTAT_ISTAT1_Pos) /*!< 0x00000002 */ #define GPIO_ISTAT_ISTAT1 GPIO_ISTAT_ISTAT1_Msk /*!< Port input data, bit 1 */ #define GPIO_ISTAT_ISTAT2_Pos (2U) #define GPIO_ISTAT_ISTAT2_Msk (0x1U << GPIO_ISTAT_ISTAT2_Pos) /*!< 0x00000004 */ #define GPIO_ISTAT_ISTAT2 GPIO_ISTAT_ISTAT2_Msk /*!< Port input data, bit 2 */ #define GPIO_ISTAT_ISTAT3_Pos (3U) #define GPIO_ISTAT_ISTAT3_Msk (0x1U << GPIO_ISTAT_ISTAT3_Pos) /*!< 0x00000008 */ #define GPIO_ISTAT_ISTAT3 GPIO_ISTAT_ISTAT3_Msk /*!< Port input data, bit 3 */ #define GPIO_ISTAT_ISTAT4_Pos (4U) #define GPIO_ISTAT_ISTAT4_Msk (0x1U << GPIO_ISTAT_ISTAT4_Pos) /*!< 0x00000010 */ #define GPIO_ISTAT_ISTAT4 GPIO_ISTAT_ISTAT4_Msk /*!< Port input data, bit 4 */ #define GPIO_ISTAT_ISTAT5_Pos (5U) #define GPIO_ISTAT_ISTAT5_Msk (0x1U << GPIO_ISTAT_ISTAT5_Pos) /*!< 0x00000020 */ #define GPIO_ISTAT_ISTAT5 GPIO_ISTAT_ISTAT5_Msk /*!< Port input data, bit 5 */ #define GPIO_ISTAT_ISTAT6_Pos (6U) #define GPIO_ISTAT_ISTAT6_Msk (0x1U << GPIO_ISTAT_ISTAT6_Pos) /*!< 0x00000040 */ #define GPIO_ISTAT_ISTAT6 GPIO_ISTAT_ISTAT6_Msk /*!< Port input data, bit 6 */ #define GPIO_ISTAT_ISTAT7_Pos (7U) #define GPIO_ISTAT_ISTAT7_Msk (0x1U << GPIO_ISTAT_ISTAT7_Pos) /*!< 0x00000080 */ #define GPIO_ISTAT_ISTAT7 GPIO_ISTAT_ISTAT7_Msk /*!< Port input data, bit 7 */ #define GPIO_ISTAT_ISTAT8_Pos (8U) #define GPIO_ISTAT_ISTAT8_Msk (0x1U << GPIO_ISTAT_ISTAT8_Pos) /*!< 0x00000100 */ #define GPIO_ISTAT_ISTAT8 GPIO_ISTAT_ISTAT8_Msk /*!< Port input data, bit 8 */ #define GPIO_ISTAT_ISTAT9_Pos (9U) #define GPIO_ISTAT_ISTAT9_Msk (0x1U << GPIO_ISTAT_ISTAT9_Pos) /*!< 0x00000200 */ #define GPIO_ISTAT_ISTAT9 GPIO_ISTAT_ISTAT9_Msk /*!< Port input data, bit 9 */ #define GPIO_ISTAT_ISTAT10_Pos (10U) #define GPIO_ISTAT_ISTAT10_Msk (0x1U << GPIO_ISTAT_ISTAT10_Pos) /*!< 0x00000400 */ #define GPIO_ISTAT_ISTAT10 GPIO_ISTAT_ISTAT10_Msk /*!< Port input data, bit 10 */ #define GPIO_ISTAT_ISTAT11_Pos (11U) #define GPIO_ISTAT_ISTAT11_Msk (0x1U << GPIO_ISTAT_ISTAT11_Pos) /*!< 0x00000800 */ #define GPIO_ISTAT_ISTAT11 GPIO_ISTAT_ISTAT11_Msk /*!< Port input data, bit 11 */ #define GPIO_ISTAT_ISTAT12_Pos (12U) #define GPIO_ISTAT_ISTAT12_Msk (0x1U << GPIO_ISTAT_ISTAT12_Pos) /*!< 0x00001000 */ #define GPIO_ISTAT_ISTAT12 GPIO_ISTAT_ISTAT12_Msk /*!< Port input data, bit 12 */ #define GPIO_ISTAT_ISTAT13_Pos (13U) #define GPIO_ISTAT_ISTAT13_Msk (0x1U << GPIO_ISTAT_ISTAT13_Pos) /*!< 0x00002000 */ #define GPIO_ISTAT_ISTAT13 GPIO_ISTAT_ISTAT13_Msk /*!< Port input data, bit 13 */ #define GPIO_ISTAT_ISTAT14_Pos (14U) #define GPIO_ISTAT_ISTAT14_Msk (0x1U << GPIO_ISTAT_ISTAT14_Pos) /*!< 0x00004000 */ #define GPIO_ISTAT_ISTAT14 GPIO_ISTAT_ISTAT14_Msk /*!< Port input data, bit 14 */ #define GPIO_ISTAT_ISTAT15_Pos (15U) #define GPIO_ISTAT_ISTAT15_Msk (0x1U << GPIO_ISTAT_ISTAT15_Pos) /*!< 0x00008000 */ #define GPIO_ISTAT_ISTAT15 GPIO_ISTAT_ISTAT15_Msk /*!< Port input data, bit 15 */ /******************* Bit definition for GPIO_ODR register *******************/ #define GPIO_OCTL_OCTL0_Pos (0U) #define GPIO_OCTL_OCTL0_Msk (0x1U << GPIO_OCTL_OCTL0_Pos) /*!< 0x00000001 */ #define GPIO_OCTL_OCTL0 GPIO_OCTL_OCTL0_Msk /*!< Port output data, bit 0 */ #define GPIO_OCTL_OCTL1_Pos (1U) #define GPIO_OCTL_OCTL1_Msk (0x1U << GPIO_OCTL_OCTL1_Pos) /*!< 0x00000002 */ #define GPIO_OCTL_OCTL1 GPIO_OCTL_OCTL1_Msk /*!< Port output data, bit 1 */ #define GPIO_OCTL_OCTL2_Pos (2U) #define GPIO_OCTL_OCTL2_Msk (0x1U << GPIO_OCTL_OCTL2_Pos) /*!< 0x00000004 */ #define GPIO_OCTL_OCTL2 GPIO_OCTL_OCTL2_Msk /*!< Port output data, bit 2 */ #define GPIO_OCTL_OCTL3_Pos (3U) #define GPIO_OCTL_OCTL3_Msk (0x1U << GPIO_OCTL_OCTL3_Pos) /*!< 0x00000008 */ #define GPIO_OCTL_OCTL3 GPIO_OCTL_OCTL3_Msk /*!< Port output data, bit 3 */ #define GPIO_OCTL_OCTL4_Pos (4U) #define GPIO_OCTL_OCTL4_Msk (0x1U << GPIO_OCTL_OCTL4_Pos) /*!< 0x00000010 */ #define GPIO_OCTL_OCTL4 GPIO_OCTL_OCTL4_Msk /*!< Port output data, bit 4 */ #define GPIO_OCTL_OCTL5_Pos (5U) #define GPIO_OCTL_OCTL5_Msk (0x1U << GPIO_OCTL_OCTL5_Pos) /*!< 0x00000020 */ #define GPIO_OCTL_OCTL5 GPIO_OCTL_OCTL5_Msk /*!< Port output data, bit 5 */ #define GPIO_OCTL_OCTL6_Pos (6U) #define GPIO_OCTL_OCTL6_Msk (0x1U << GPIO_OCTL_OCTL6_Pos) /*!< 0x00000040 */ #define GPIO_OCTL_OCTL6 GPIO_OCTL_OCTL6_Msk /*!< Port output data, bit 6 */ #define GPIO_OCTL_OCTL7_Pos (7U) #define GPIO_OCTL_OCTL7_Msk (0x1U << GPIO_OCTL_OCTL7_Pos) /*!< 0x00000080 */ #define GPIO_OCTL_OCTL7 GPIO_OCTL_OCTL7_Msk /*!< Port output data, bit 7 */ #define GPIO_OCTL_OCTL8_Pos (8U) #define GPIO_OCTL_OCTL8_Msk (0x1U << GPIO_OCTL_OCTL8_Pos) /*!< 0x00000100 */ #define GPIO_OCTL_OCTL8 GPIO_OCTL_OCTL8_Msk /*!< Port output data, bit 8 */ #define GPIO_OCTL_OCTL9_Pos (9U) #define GPIO_OCTL_OCTL9_Msk (0x1U << GPIO_OCTL_OCTL9_Pos) /*!< 0x00000200 */ #define GPIO_OCTL_OCTL9 GPIO_OCTL_OCTL9_Msk /*!< Port output data, bit 9 */ #define GPIO_OCTL_OCTL10_Pos (10U) #define GPIO_OCTL_OCTL10_Msk (0x1U << GPIO_OCTL_OCTL10_Pos) /*!< 0x00000400 */ #define GPIO_OCTL_OCTL10 GPIO_OCTL_OCTL10_Msk /*!< Port output data, bit 10 */ #define GPIO_OCTL_OCTL11_Pos (11U) #define GPIO_OCTL_OCTL11_Msk (0x1U << GPIO_OCTL_OCTL11_Pos) /*!< 0x00000800 */ #define GPIO_OCTL_OCTL11 GPIO_OCTL_OCTL11_Msk /*!< Port output data, bit 11 */ #define GPIO_OCTL_OCTL12_Pos (12U) #define GPIO_OCTL_OCTL12_Msk (0x1U << GPIO_OCTL_OCTL12_Pos) /*!< 0x00001000 */ #define GPIO_OCTL_OCTL12 GPIO_OCTL_OCTL12_Msk /*!< Port output data, bit 12 */ #define GPIO_OCTL_OCTL13_Pos (13U) #define GPIO_OCTL_OCTL13_Msk (0x1U << GPIO_OCTL_OCTL13_Pos) /*!< 0x00002000 */ #define GPIO_OCTL_OCTL13 GPIO_OCTL_OCTL13_Msk /*!< Port output data, bit 13 */ #define GPIO_OCTL_OCTL14_Pos (14U) #define GPIO_OCTL_OCTL14_Msk (0x1U << GPIO_OCTL_OCTL14_Pos) /*!< 0x00004000 */ #define GPIO_OCTL_OCTL14 GPIO_OCTL_OCTL14_Msk /*!< Port output data, bit 14 */ #define GPIO_OCTL_OCTL15_Pos (15U) #define GPIO_OCTL_OCTL15_Msk (0x1U << GPIO_OCTL_OCTL15_Pos) /*!< 0x00008000 */ #define GPIO_OCTL_OCTL15 GPIO_OCTL_OCTL15_Msk /*!< Port output data, bit 15 */ /****************** Bit definition for GPIO_BOP register *******************/ #define GPIO_BOP_BOP0_Pos (0U) #define GPIO_BOP_BOP0_Msk (0x1U << GPIO_BOP_BOP0_Pos) /*!< 0x00000001 */ #define GPIO_BOP_BOP0 GPIO_BOP_BOP0_Msk /*!< Port x Set bit 0 */ #define GPIO_BOP_BOP1_Pos (1U) #define GPIO_BOP_BOP1_Msk (0x1U << GPIO_BOP_BOP1_Pos) /*!< 0x00000002 */ #define GPIO_BOP_BOP1 GPIO_BOP_BOP1_Msk /*!< Port x Set bit 1 */ #define GPIO_BOP_BOP2_Pos (2U) #define GPIO_BOP_BOP2_Msk (0x1U << GPIO_BOP_BOP2_Pos) /*!< 0x00000004 */ #define GPIO_BOP_BOP2 GPIO_BOP_BOP2_Msk /*!< Port x Set bit 2 */ #define GPIO_BOP_BOP3_Pos (3U) #define GPIO_BOP_BOP3_Msk (0x1U << GPIO_BOP_BOP3_Pos) /*!< 0x00000008 */ #define GPIO_BOP_BOP3 GPIO_BOP_BOP3_Msk /*!< Port x Set bit 3 */ #define GPIO_BOP_BOP4_Pos (4U) #define GPIO_BOP_BOP4_Msk (0x1U << GPIO_BOP_BOP4_Pos) /*!< 0x00000010 */ #define GPIO_BOP_BOP4 GPIO_BOP_BOP4_Msk /*!< Port x Set bit 4 */ #define GPIO_BOP_BOP5_Pos (5U) #define GPIO_BOP_BOP5_Msk (0x1U << GPIO_BOP_BOP5_Pos) /*!< 0x00000020 */ #define GPIO_BOP_BOP5 GPIO_BOP_BOP5_Msk /*!< Port x Set bit 5 */ #define GPIO_BOP_BOP6_Pos (6U) #define GPIO_BOP_BOP6_Msk (0x1U << GPIO_BOP_BOP6_Pos) /*!< 0x00000040 */ #define GPIO_BOP_BOP6 GPIO_BOP_BOP6_Msk /*!< Port x Set bit 6 */ #define GPIO_BOP_BOP7_Pos (7U) #define GPIO_BOP_BOP7_Msk (0x1U << GPIO_BOP_BOP7_Pos) /*!< 0x00000080 */ #define GPIO_BOP_BOP7 GPIO_BOP_BOP7_Msk /*!< Port x Set bit 7 */ #define GPIO_BOP_BOP8_Pos (8U) #define GPIO_BOP_BOP8_Msk (0x1U << GPIO_BOP_BOP8_Pos) /*!< 0x00000100 */ #define GPIO_BOP_BOP8 GPIO_BOP_BOP8_Msk /*!< Port x Set bit 8 */ #define GPIO_BOP_BOP9_Pos (9U) #define GPIO_BOP_BOP9_Msk (0x1U << GPIO_BOP_BOP9_Pos) /*!< 0x00000200 */ #define GPIO_BOP_BOP9 GPIO_BOP_BOP9_Msk /*!< Port x Set bit 9 */ #define GPIO_BOP_BOP10_Pos (10U) #define GPIO_BOP_BOP10_Msk (0x1U << GPIO_BOP_BOP10_Pos) /*!< 0x00000400 */ #define GPIO_BOP_BOP10 GPIO_BOP_BOP10_Msk /*!< Port x Set bit 10 */ #define GPIO_BOP_BOP11_Pos (11U) #define GPIO_BOP_BOP11_Msk (0x1U << GPIO_BOP_BOP11_Pos) /*!< 0x00000800 */ #define GPIO_BOP_BOP11 GPIO_BOP_BOP11_Msk /*!< Port x Set bit 11 */ #define GPIO_BOP_BOP12_Pos (12U) #define GPIO_BOP_BOP12_Msk (0x1U << GPIO_BOP_BOP12_Pos) /*!< 0x00001000 */ #define GPIO_BOP_BOP12 GPIO_BOP_BOP12_Msk /*!< Port x Set bit 12 */ #define GPIO_BOP_BOP13_Pos (13U) #define GPIO_BOP_BOP13_Msk (0x1U << GPIO_BOP_BOP13_Pos) /*!< 0x00002000 */ #define GPIO_BOP_BOP13 GPIO_BOP_BOP13_Msk /*!< Port x Set bit 13 */ #define GPIO_BOP_BOP14_Pos (14U) #define GPIO_BOP_BOP14_Msk (0x1U << GPIO_BOP_BOP14_Pos) /*!< 0x00004000 */ #define GPIO_BOP_BOP14 GPIO_BOP_BOP14_Msk /*!< Port x Set bit 14 */ #define GPIO_BOP_BOP15_Pos (15U) #define GPIO_BOP_BOP15_Msk (0x1U << GPIO_BOP_BOP15_Pos) /*!< 0x00008000 */ #define GPIO_BOP_BOP15 GPIO_BOP_BOP15_Msk /*!< Port x Set bit 15 */ #define GPIO_BOP_CR0_Pos (16U) #define GPIO_BOP_CR0_Msk (0x1U << GPIO_BOP_CR0_Pos) /*!< 0x00010000 */ #define GPIO_BOP_CR0 GPIO_BOP_CR0_Msk /*!< Port x Reset bit 0 */ #define GPIO_BOP_CR1_Pos (17U) #define GPIO_BOP_CR1_Msk (0x1U << GPIO_BOP_CR1_Pos) /*!< 0x00020000 */ #define GPIO_BOP_CR1 GPIO_BOP_CR1_Msk /*!< Port x Reset bit 1 */ #define GPIO_BOP_CR2_Pos (18U) #define GPIO_BOP_CR2_Msk (0x1U << GPIO_BOP_CR2_Pos) /*!< 0x00040000 */ #define GPIO_BOP_CR2 GPIO_BOP_CR2_Msk /*!< Port x Reset bit 2 */ #define GPIO_BOP_CR3_Pos (19U) #define GPIO_BOP_CR3_Msk (0x1U << GPIO_BOP_CR3_Pos) /*!< 0x00080000 */ #define GPIO_BOP_CR3 GPIO_BOP_CR3_Msk /*!< Port x Reset bit 3 */ #define GPIO_BOP_CR4_Pos (20U) #define GPIO_BOP_CR4_Msk (0x1U << GPIO_BOP_CR4_Pos) /*!< 0x00100000 */ #define GPIO_BOP_CR4 GPIO_BOP_CR4_Msk /*!< Port x Reset bit 4 */ #define GPIO_BOP_CR5_Pos (21U) #define GPIO_BOP_CR5_Msk (0x1U << GPIO_BOP_CR5_Pos) /*!< 0x00200000 */ #define GPIO_BOP_CR5 GPIO_BOP_CR5_Msk /*!< Port x Reset bit 5 */ #define GPIO_BOP_CR6_Pos (22U) #define GPIO_BOP_CR6_Msk (0x1U << GPIO_BOP_CR6_Pos) /*!< 0x00400000 */ #define GPIO_BOP_CR6 GPIO_BOP_CR6_Msk /*!< Port x Reset bit 6 */ #define GPIO_BOP_CR7_Pos (23U) #define GPIO_BOP_CR7_Msk (0x1U << GPIO_BOP_CR7_Pos) /*!< 0x00800000 */ #define GPIO_BOP_CR7 GPIO_BOP_CR7_Msk /*!< Port x Reset bit 7 */ #define GPIO_BOP_CR8_Pos (24U) #define GPIO_BOP_CR8_Msk (0x1U << GPIO_BOP_CR8_Pos) /*!< 0x01000000 */ #define GPIO_BOP_CR8 GPIO_BOP_CR8_Msk /*!< Port x Reset bit 8 */ #define GPIO_BOP_CR9_Pos (25U) #define GPIO_BOP_CR9_Msk (0x1U << GPIO_BOP_CR9_Pos) /*!< 0x02000000 */ #define GPIO_BOP_CR9 GPIO_BOP_CR9_Msk /*!< Port x Reset bit 9 */ #define GPIO_BOP_CR10_Pos (26U) #define GPIO_BOP_CR10_Msk (0x1U << GPIO_BOP_CR10_Pos) /*!< 0x04000000 */ #define GPIO_BOP_CR10 GPIO_BOP_CR10_Msk /*!< Port x Reset bit 10 */ #define GPIO_BOP_CR11_Pos (27U) #define GPIO_BOP_CR11_Msk (0x1U << GPIO_BOP_CR11_Pos) /*!< 0x08000000 */ #define GPIO_BOP_CR11 GPIO_BOP_CR11_Msk /*!< Port x Reset bit 11 */ #define GPIO_BOP_CR12_Pos (28U) #define GPIO_BOP_CR12_Msk (0x1U << GPIO_BOP_CR12_Pos) /*!< 0x10000000 */ #define GPIO_BOP_CR12 GPIO_BOP_CR12_Msk /*!< Port x Reset bit 12 */ #define GPIO_BOP_CR13_Pos (29U) #define GPIO_BOP_CR13_Msk (0x1U << GPIO_BOP_CR13_Pos) /*!< 0x20000000 */ #define GPIO_BOP_CR13 GPIO_BOP_CR13_Msk /*!< Port x Reset bit 13 */ #define GPIO_BOP_CR14_Pos (30U) #define GPIO_BOP_CR14_Msk (0x1U << GPIO_BOP_CR14_Pos) /*!< 0x40000000 */ #define GPIO_BOP_CR14 GPIO_BOP_CR14_Msk /*!< Port x Reset bit 14 */ #define GPIO_BOP_CR15_Pos (31U) #define GPIO_BOP_CR15_Msk (0x1U << GPIO_BOP_CR15_Pos) /*!< 0x80000000 */ #define GPIO_BOP_CR15 GPIO_BOP_CR15_Msk /*!< Port x Reset bit 15 */ /******************* Bit definition for GPIO_BC register *******************/ #define GPIO_BC_CR0_Pos (0U) #define GPIO_BC_CR0_Msk (0x1U << GPIO_BC_CR0_Pos) /*!< 0x00000001 */ #define GPIO_BC_CR0 GPIO_BC_CR0_Msk /*!< Port x Reset bit 0 */ #define GPIO_BC_CR1_Pos (1U) #define GPIO_BC_CR1_Msk (0x1U << GPIO_BC_CR1_Pos) /*!< 0x00000002 */ #define GPIO_BC_CR1 GPIO_BC_CR1_Msk /*!< Port x Reset bit 1 */ #define GPIO_BC_CR2_Pos (2U) #define GPIO_BC_CR2_Msk (0x1U << GPIO_BC_CR2_Pos) /*!< 0x00000004 */ #define GPIO_BC_CR2 GPIO_BC_CR2_Msk /*!< Port x Reset bit 2 */ #define GPIO_BC_CR3_Pos (3U) #define GPIO_BC_CR3_Msk (0x1U << GPIO_BC_CR3_Pos) /*!< 0x00000008 */ #define GPIO_BC_CR3 GPIO_BC_CR3_Msk /*!< Port x Reset bit 3 */ #define GPIO_BC_CR4_Pos (4U) #define GPIO_BC_CR4_Msk (0x1U << GPIO_BC_CR4_Pos) /*!< 0x00000010 */ #define GPIO_BC_CR4 GPIO_BC_CR4_Msk /*!< Port x Reset bit 4 */ #define GPIO_BC_CR5_Pos (5U) #define GPIO_BC_CR5_Msk (0x1U << GPIO_BC_CR5_Pos) /*!< 0x00000020 */ #define GPIO_BC_CR5 GPIO_BC_CR5_Msk /*!< Port x Reset bit 5 */ #define GPIO_BC_CR6_Pos (6U) #define GPIO_BC_CR6_Msk (0x1U << GPIO_BC_CR6_Pos) /*!< 0x00000040 */ #define GPIO_BC_CR6 GPIO_BC_CR6_Msk /*!< Port x Reset bit 6 */ #define GPIO_BC_CR7_Pos (7U) #define GPIO_BC_CR7_Msk (0x1U << GPIO_BC_CR7_Pos) /*!< 0x00000080 */ #define GPIO_BC_CR7 GPIO_BC_CR7_Msk /*!< Port x Reset bit 7 */ #define GPIO_BC_CR8_Pos (8U) #define GPIO_BC_CR8_Msk (0x1U << GPIO_BC_CR8_Pos) /*!< 0x00000100 */ #define GPIO_BC_CR8 GPIO_BC_CR8_Msk /*!< Port x Reset bit 8 */ #define GPIO_BC_CR9_Pos (9U) #define GPIO_BC_CR9_Msk (0x1U << GPIO_BC_CR9_Pos) /*!< 0x00000200 */ #define GPIO_BC_CR9 GPIO_BC_CR9_Msk /*!< Port x Reset bit 9 */ #define GPIO_BC_CR10_Pos (10U) #define GPIO_BC_CR10_Msk (0x1U << GPIO_BC_CR10_Pos) /*!< 0x00000400 */ #define GPIO_BC_CR10 GPIO_BC_CR10_Msk /*!< Port x Reset bit 10 */ #define GPIO_BC_CR11_Pos (11U) #define GPIO_BC_CR11_Msk (0x1U << GPIO_BC_CR11_Pos) /*!< 0x00000800 */ #define GPIO_BC_CR11 GPIO_BC_CR11_Msk /*!< Port x Reset bit 11 */ #define GPIO_BC_CR12_Pos (12U) #define GPIO_BC_CR12_Msk (0x1U << GPIO_BC_CR12_Pos) /*!< 0x00001000 */ #define GPIO_BC_CR12 GPIO_BC_CR12_Msk /*!< Port x Reset bit 12 */ #define GPIO_BC_CR13_Pos (13U) #define GPIO_BC_CR13_Msk (0x1U << GPIO_BC_CR13_Pos) /*!< 0x00002000 */ #define GPIO_BC_CR13 GPIO_BC_CR13_Msk /*!< Port x Reset bit 13 */ #define GPIO_BC_CR14_Pos (14U) #define GPIO_BC_CR14_Msk (0x1U << GPIO_BC_CR14_Pos) /*!< 0x00004000 */ #define GPIO_BC_CR14 GPIO_BC_CR14_Msk /*!< Port x Reset bit 14 */ #define GPIO_BC_CR15_Pos (15U) #define GPIO_BC_CR15_Msk (0x1U << GPIO_BC_CR15_Pos) /*!< 0x00008000 */ #define GPIO_BC_CR15 GPIO_BC_CR15_Msk /*!< Port x Reset bit 15 */ /****************** Bit definition for GPIO_LOCK register *******************/ #define GPIO_LOCK_LK0_Pos (0U) #define GPIO_LOCK_LK0_Msk (0x1U << GPIO_LOCK_LK0_Pos) /*!< 0x00000001 */ #define GPIO_LOCK_LK0 GPIO_LOCK_LK0_Msk /*!< Port x Lock bit 0 */ #define GPIO_LOCK_LK1_Pos (1U) #define GPIO_LOCK_LK1_Msk (0x1U << GPIO_LOCK_LK1_Pos) /*!< 0x00000002 */ #define GPIO_LOCK_LK1 GPIO_LOCK_LK1_Msk /*!< Port x Lock bit 1 */ #define GPIO_LOCK_LK2_Pos (2U) #define GPIO_LOCK_LK2_Msk (0x1U << GPIO_LOCK_LK2_Pos) /*!< 0x00000004 */ #define GPIO_LOCK_LK2 GPIO_LOCK_LK2_Msk /*!< Port x Lock bit 2 */ #define GPIO_LOCK_LK3_Pos (3U) #define GPIO_LOCK_LK3_Msk (0x1U << GPIO_LOCK_LK3_Pos) /*!< 0x00000008 */ #define GPIO_LOCK_LK3 GPIO_LOCK_LK3_Msk /*!< Port x Lock bit 3 */ #define GPIO_LOCK_LK4_Pos (4U) #define GPIO_LOCK_LK4_Msk (0x1U << GPIO_LOCK_LK4_Pos) /*!< 0x00000010 */ #define GPIO_LOCK_LK4 GPIO_LOCK_LK4_Msk /*!< Port x Lock bit 4 */ #define GPIO_LOCK_LK5_Pos (5U) #define GPIO_LOCK_LK5_Msk (0x1U << GPIO_LOCK_LK5_Pos) /*!< 0x00000020 */ #define GPIO_LOCK_LK5 GPIO_LOCK_LK5_Msk /*!< Port x Lock bit 5 */ #define GPIO_LOCK_LK6_Pos (6U) #define GPIO_LOCK_LK6_Msk (0x1U << GPIO_LOCK_LK6_Pos) /*!< 0x00000040 */ #define GPIO_LOCK_LK6 GPIO_LOCK_LK6_Msk /*!< Port x Lock bit 6 */ #define GPIO_LOCK_LK7_Pos (7U) #define GPIO_LOCK_LK7_Msk (0x1U << GPIO_LOCK_LK7_Pos) /*!< 0x00000080 */ #define GPIO_LOCK_LK7 GPIO_LOCK_LK7_Msk /*!< Port x Lock bit 7 */ #define GPIO_LOCK_LK8_Pos (8U) #define GPIO_LOCK_LK8_Msk (0x1U << GPIO_LOCK_LK8_Pos) /*!< 0x00000100 */ #define GPIO_LOCK_LK8 GPIO_LOCK_LK8_Msk /*!< Port x Lock bit 8 */ #define GPIO_LOCK_LK9_Pos (9U) #define GPIO_LOCK_LK9_Msk (0x1U << GPIO_LOCK_LK9_Pos) /*!< 0x00000200 */ #define GPIO_LOCK_LK9 GPIO_LOCK_LK9_Msk /*!< Port x Lock bit 9 */ #define GPIO_LOCK_LK10_Pos (10U) #define GPIO_LOCK_LK10_Msk (0x1U << GPIO_LOCK_LK10_Pos) /*!< 0x00000400 */ #define GPIO_LOCK_LK10 GPIO_LOCK_LK10_Msk /*!< Port x Lock bit 10 */ #define GPIO_LOCK_LK11_Pos (11U) #define GPIO_LOCK_LK11_Msk (0x1U << GPIO_LOCK_LK11_Pos) /*!< 0x00000800 */ #define GPIO_LOCK_LK11 GPIO_LOCK_LK11_Msk /*!< Port x Lock bit 11 */ #define GPIO_LOCK_LK12_Pos (12U) #define GPIO_LOCK_LK12_Msk (0x1U << GPIO_LOCK_LK12_Pos) /*!< 0x00001000 */ #define GPIO_LOCK_LK12 GPIO_LOCK_LK12_Msk /*!< Port x Lock bit 12 */ #define GPIO_LOCK_LK13_Pos (13U) #define GPIO_LOCK_LK13_Msk (0x1U << GPIO_LOCK_LK13_Pos) /*!< 0x00002000 */ #define GPIO_LOCK_LK13 GPIO_LOCK_LK13_Msk /*!< Port x Lock bit 13 */ #define GPIO_LOCK_LK14_Pos (14U) #define GPIO_LOCK_LK14_Msk (0x1U << GPIO_LOCK_LK14_Pos) /*!< 0x00004000 */ #define GPIO_LOCK_LK14 GPIO_LOCK_LK14_Msk /*!< Port x Lock bit 14 */ #define GPIO_LOCK_LK15_Pos (15U) #define GPIO_LOCK_LK15_Msk (0x1U << GPIO_LOCK_LK15_Pos) /*!< 0x00008000 */ #define GPIO_LOCK_LK15 GPIO_LOCK_LK15_Msk /*!< Port x Lock bit 15 */ #define GPIO_LOCK_LKK_Pos (16U) #define GPIO_LOCK_LKK_Msk (0x1U << GPIO_LOCK_LKK_Pos) /*!< 0x00010000 */ #define GPIO_LOCK_LKK GPIO_LOCK_LKK_Msk /*!< Lock key */ /*----------------------------------------------------------------------------*/ /****************** Bit definition for AFIO_EC register *******************/ #define AFIO_EC_PIN_Pos (0U) #define AFIO_EC_PIN_Msk (0xFU << AFIO_EC_PIN_Pos) /*!< 0x0000000F */ #define AFIO_EC_PIN AFIO_EC_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ #define AFIO_EC_PIN_0 (0x1U << AFIO_EC_PIN_Pos) /*!< 0x00000001 */ #define AFIO_EC_PIN_1 (0x2U << AFIO_EC_PIN_Pos) /*!< 0x00000002 */ #define AFIO_EC_PIN_2 (0x4U << AFIO_EC_PIN_Pos) /*!< 0x00000004 */ #define AFIO_EC_PIN_3 (0x8U << AFIO_EC_PIN_Pos) /*!< 0x00000008 */ /*!< PIN configuration */ #define AFIO_EC_PIN_PX0 0x00000000U /*!< Pin 0 selected */ #define AFIO_EC_PIN_PX1_Pos (0U) #define AFIO_EC_PIN_PX1_Msk (0x1U << AFIO_EC_PIN_PX1_Pos) /*!< 0x00000001 */ #define AFIO_EC_PIN_PX1 AFIO_EC_PIN_PX1_Msk /*!< Pin 1 selected */ #define AFIO_EC_PIN_PX2_Pos (1U) #define AFIO_EC_PIN_PX2_Msk (0x1U << AFIO_EC_PIN_PX2_Pos) /*!< 0x00000002 */ #define AFIO_EC_PIN_PX2 AFIO_EC_PIN_PX2_Msk /*!< Pin 2 selected */ #define AFIO_EC_PIN_PX3_Pos (0U) #define AFIO_EC_PIN_PX3_Msk (0x3U << AFIO_EC_PIN_PX3_Pos) /*!< 0x00000003 */ #define AFIO_EC_PIN_PX3 AFIO_EC_PIN_PX3_Msk /*!< Pin 3 selected */ #define AFIO_EC_PIN_PX4_Pos (2U) #define AFIO_EC_PIN_PX4_Msk (0x1U << AFIO_EC_PIN_PX4_Pos) /*!< 0x00000004 */ #define AFIO_EC_PIN_PX4 AFIO_EC_PIN_PX4_Msk /*!< Pin 4 selected */ #define AFIO_EC_PIN_PX5_Pos (0U) #define AFIO_EC_PIN_PX5_Msk (0x5U << AFIO_EC_PIN_PX5_Pos) /*!< 0x00000005 */ #define AFIO_EC_PIN_PX5 AFIO_EC_PIN_PX5_Msk /*!< Pin 5 selected */ #define AFIO_EC_PIN_PX6_Pos (1U) #define AFIO_EC_PIN_PX6_Msk (0x3U << AFIO_EC_PIN_PX6_Pos) /*!< 0x00000006 */ #define AFIO_EC_PIN_PX6 AFIO_EC_PIN_PX6_Msk /*!< Pin 6 selected */ #define AFIO_EC_PIN_PX7_Pos (0U) #define AFIO_EC_PIN_PX7_Msk (0x7U << AFIO_EC_PIN_PX7_Pos) /*!< 0x00000007 */ #define AFIO_EC_PIN_PX7 AFIO_EC_PIN_PX7_Msk /*!< Pin 7 selected */ #define AFIO_EC_PIN_PX8_Pos (3U) #define AFIO_EC_PIN_PX8_Msk (0x1U << AFIO_EC_PIN_PX8_Pos) /*!< 0x00000008 */ #define AFIO_EC_PIN_PX8 AFIO_EC_PIN_PX8_Msk /*!< Pin 8 selected */ #define AFIO_EC_PIN_PX9_Pos (0U) #define AFIO_EC_PIN_PX9_Msk (0x9U << AFIO_EC_PIN_PX9_Pos) /*!< 0x00000009 */ #define AFIO_EC_PIN_PX9 AFIO_EC_PIN_PX9_Msk /*!< Pin 9 selected */ #define AFIO_EC_PIN_PX10_Pos (1U) #define AFIO_EC_PIN_PX10_Msk (0x5U << AFIO_EC_PIN_PX10_Pos) /*!< 0x0000000A */ #define AFIO_EC_PIN_PX10 AFIO_EC_PIN_PX10_Msk /*!< Pin 10 selected */ #define AFIO_EC_PIN_PX11_Pos (0U) #define AFIO_EC_PIN_PX11_Msk (0xBU << AFIO_EC_PIN_PX11_Pos) /*!< 0x0000000B */ #define AFIO_EC_PIN_PX11 AFIO_EC_PIN_PX11_Msk /*!< Pin 11 selected */ #define AFIO_EC_PIN_PX12_Pos (2U) #define AFIO_EC_PIN_PX12_Msk (0x3U << AFIO_EC_PIN_PX12_Pos) /*!< 0x0000000C */ #define AFIO_EC_PIN_PX12 AFIO_EC_PIN_PX12_Msk /*!< Pin 12 selected */ #define AFIO_EC_PIN_PX13_Pos (0U) #define AFIO_EC_PIN_PX13_Msk (0xDU << AFIO_EC_PIN_PX13_Pos) /*!< 0x0000000D */ #define AFIO_EC_PIN_PX13 AFIO_EC_PIN_PX13_Msk /*!< Pin 13 selected */ #define AFIO_EC_PIN_PX14_Pos (1U) #define AFIO_EC_PIN_PX14_Msk (0x7U << AFIO_EC_PIN_PX14_Pos) /*!< 0x0000000E */ #define AFIO_EC_PIN_PX14 AFIO_EC_PIN_PX14_Msk /*!< Pin 14 selected */ #define AFIO_EC_PIN_PX15_Pos (0U) #define AFIO_EC_PIN_PX15_Msk (0xFU << AFIO_EC_PIN_PX15_Pos) /*!< 0x0000000F */ #define AFIO_EC_PIN_PX15 AFIO_EC_PIN_PX15_Msk /*!< Pin 15 selected */ #define AFIO_EC_PORT_Pos (4U) #define AFIO_EC_PORT_Msk (0x7U << AFIO_EC_PORT_Pos) /*!< 0x00000070 */ #define AFIO_EC_PORT AFIO_EC_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ #define AFIO_EC_PORT_0 (0x1U << AFIO_EC_PORT_Pos) /*!< 0x00000010 */ #define AFIO_EC_PORT_1 (0x2U << AFIO_EC_PORT_Pos) /*!< 0x00000020 */ #define AFIO_EC_PORT_2 (0x4U << AFIO_EC_PORT_Pos) /*!< 0x00000040 */ /*!< PORT configuration */ #define AFIO_EC_PORT_PA 0x00000000 /*!< Port A selected */ #define AFIO_EC_PORT_PB_Pos (4U) #define AFIO_EC_PORT_PB_Msk (0x1U << AFIO_EC_PORT_PB_Pos) /*!< 0x00000010 */ #define AFIO_EC_PORT_PB AFIO_EC_PORT_PB_Msk /*!< Port B selected */ #define AFIO_EC_PORT_PC_Pos (5U) #define AFIO_EC_PORT_PC_Msk (0x1U << AFIO_EC_PORT_PC_Pos) /*!< 0x00000020 */ #define AFIO_EC_PORT_PC AFIO_EC_PORT_PC_Msk /*!< Port C selected */ #define AFIO_EC_PORT_PD_Pos (4U) #define AFIO_EC_PORT_PD_Msk (0x3U << AFIO_EC_PORT_PD_Pos) /*!< 0x00000030 */ #define AFIO_EC_PORT_PD AFIO_EC_PORT_PD_Msk /*!< Port D selected */ #define AFIO_EC_PORT_PE_Pos (6U) #define AFIO_EC_PORT_PE_Msk (0x1U << AFIO_EC_PORT_PE_Pos) /*!< 0x00000040 */ #define AFIO_EC_PORT_PE AFIO_EC_PORT_PE_Msk /*!< Port E selected */ #define AFIO_EC_EOE_Pos (7U) #define AFIO_EC_EOE_Msk (0x1U << AFIO_EC_EOE_Pos) /*!< 0x00000080 */ #define AFIO_EC_EOE AFIO_EC_EOE_Msk /*!< Event Output Enable */ /****************** Bit definition for AFIO_PCF0 register *******************/ #define AFIO_PCF0_SPI0_REMAP_Pos (0U) #define AFIO_PCF0_SPI0_REMAP_Msk (0x1U << AFIO_PCF0_SPI0_REMAP_Pos) /*!< 0x00000001 */ #define AFIO_PCF0_SPI0_REMAP AFIO_PCF0_SPI0_REMAP_Msk /*!< SPI0 remapping */ #define AFIO_PCF0_I2C0_REMAP_Pos (1U) #define AFIO_PCF0_I2C0_REMAP_Msk (0x1U << AFIO_PCF0_I2C0_REMAP_Pos) /*!< 0x00000002 */ #define AFIO_PCF0_I2C0_REMAP AFIO_PCF0_I2C0_REMAP_Msk /*!< I2C0 remapping */ #define AFIO_PCF0_USART0_REMAP_Pos (2U) #define AFIO_PCF0_USART0_REMAP_Msk (0x1U << AFIO_PCF0_USART0_REMAP_Pos) /*!< 0x00000004 */ #define AFIO_PCF0_USART0_REMAP AFIO_PCF0_USART0_REMAP_Msk /*!< USART1 remapping */ #define AFIO_PCF0_USART1_REMAP_Pos (3U) #define AFIO_PCF0_USART1_REMAP_Msk (0x1U << AFIO_PCF0_USART1_REMAP_Pos) /*!< 0x00000008 */ #define AFIO_PCF0_USART1_REMAP AFIO_PCF0_USART1_REMAP_Msk /*!< USART2 remapping */ #define AFIO_PCF0_USART2_REMAP_Pos (4U) #define AFIO_PCF0_USART2_REMAP_Msk (0x3U << AFIO_PCF0_USART2_REMAP_Pos) /*!< 0x00000030 */ #define AFIO_PCF0_USART2_REMAP AFIO_PCF0_USART2_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ #define AFIO_PCF0_USART2_REMAP_0 (0x1U << AFIO_PCF0_USART2_REMAP_Pos) /*!< 0x00000010 */ #define AFIO_PCF0_USART2_REMAP_1 (0x2U << AFIO_PCF0_USART2_REMAP_Pos) /*!< 0x00000020 */ /* USART3_REMAP configuration */ #define AFIO_PCF0_USART2_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ #define AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Pos (4U) #define AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ #define AFIO_PCF0_USART2_REMAP_PARTIALREMAP AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ #define AFIO_PCF0_USART2_REMAP_FULLREMAP_Pos (4U) #define AFIO_PCF0_USART2_REMAP_FULLREMAP_Msk (0x3U << AFIO_PCF0_USART2_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ #define AFIO_PCF0_USART2_REMAP_FULLREMAP AFIO_PCF0_USART2_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ #define AFIO_PCF0_TIMER0_REMAP_Pos (6U) #define AFIO_PCF0_TIMER0_REMAP_Msk (0x3U << AFIO_PCF0_TIMER0_REMAP_Pos) /*!< 0x000000C0 */ #define AFIO_PCF0_TIMER0_REMAP AFIO_PCF0_TIMER0_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ #define AFIO_PCF0_TIMER0_REMAP_0 (0x1U << AFIO_PCF0_TIMER0_REMAP_Pos) /*!< 0x00000040 */ #define AFIO_PCF0_TIMER0_REMAP_1 (0x2U << AFIO_PCF0_TIMER0_REMAP_Pos) /*!< 0x00000080 */ /*!< TIM1_REMAP configuration */ #define AFIO_PCF0_TIMER0_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ #define AFIO_PCF0_TIMER0_REMAP_PARTIALREMAP_Pos (6U) #define AFIO_PCF0_TIMER0_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_PCF0_TIMER0_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ #define AFIO_PCF0_TIMER0_REMAP_PARTIALREMAP AFIO_PCF0_TIMER0_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ #define AFIO_PCF0_TIMER0_REMAP_FULLREMAP_Pos (6U) #define AFIO_PCF0_TIMER0_REMAP_FULLREMAP_Msk (0x3U << AFIO_PCF0_TIMER0_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ #define AFIO_PCF0_TIMER0_REMAP_FULLREMAP AFIO_PCF0_TIMER0_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ #define AFIO_PCF0_TIMER1_REMAP_Pos (8U) #define AFIO_PCF0_TIMER1_REMAP_Msk (0x3U << AFIO_PCF0_TIMER1_REMAP_Pos) /*!< 0x00000300 */ #define AFIO_PCF0_TIMER1_REMAP AFIO_PCF0_TIMER1_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ #define AFIO_PCF0_TIMER1_REMAP_0 (0x1U << AFIO_PCF0_TIMER1_REMAP_Pos) /*!< 0x00000100 */ #define AFIO_PCF0_TIMER1_REMAP_1 (0x2U << AFIO_PCF0_TIMER1_REMAP_Pos) /*!< 0x00000200 */ /*!< TIM2_REMAP configuration */ #define AFIO_PCF0_TIMER1_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ #define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP1_Pos (8U) #define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ #define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP1 AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ #define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP2_Pos (9U) #define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ #define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP2 AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ #define AFIO_PCF0_TIMER1_REMAP_FULLREMAP_Pos (8U) #define AFIO_PCF0_TIMER1_REMAP_FULLREMAP_Msk (0x3U << AFIO_PCF0_TIMER1_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ #define AFIO_PCF0_TIMER1_REMAP_FULLREMAP AFIO_PCF0_TIMER1_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ #define AFIO_PCF0_TIMER2_REMAP_Pos (10U) #define AFIO_PCF0_TIMER2_REMAP_Msk (0x3U << AFIO_PCF0_TIMER2_REMAP_Pos) /*!< 0x00000C00 */ #define AFIO_PCF0_TIMER2_REMAP AFIO_PCF0_TIMER2_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ #define AFIO_PCF0_TIMER2_REMAP_0 (0x1U << AFIO_PCF0_TIMER2_REMAP_Pos) /*!< 0x00000400 */ #define AFIO_PCF0_TIMER2_REMAP_1 (0x2U << AFIO_PCF0_TIMER2_REMAP_Pos) /*!< 0x00000800 */ /*!< TIM3_REMAP configuration */ #define AFIO_PCF0_TIMER2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ #define AFIO_PCF0_TIMER2_REMAP_PARTIALREMAP_Pos (11U) #define AFIO_PCF0_TIMER2_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_PCF0_TIMER2_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ #define AFIO_PCF0_TIMER2_REMAP_PARTIALREMAP AFIO_PCF0_TIMER2_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ #define AFIO_PCF0_TIMER2_REMAP_FULLREMAP_Pos (10U) #define AFIO_PCF0_TIMER2_REMAP_FULLREMAP_Msk (0x3U << AFIO_PCF0_TIMER2_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ #define AFIO_PCF0_TIMER2_REMAP_FULLREMAP AFIO_PCF0_TIMER2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ #define AFIO_PCF0_TIMER3_REMAP_Pos (12U) #define AFIO_PCF0_TIMER3_REMAP_Msk (0x1U << AFIO_PCF0_TIMER3_REMAP_Pos) /*!< 0x00001000 */ #define AFIO_PCF0_TIMER3_REMAP AFIO_PCF0_TIMER3_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ #define AFIO_PCF0_CAN0_REMAP_Pos (13U) #define AFIO_PCF0_CAN0_REMAP_Msk (0x3U << AFIO_PCF0_CAN0_REMAP_Pos) /*!< 0x00006000 */ #define AFIO_PCF0_CAN0_REMAP AFIO_PCF0_CAN0_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ #define AFIO_PCF0_CAN0_REMAP_0 (0x1U << AFIO_PCF0_CAN0_REMAP_Pos) /*!< 0x00002000 */ #define AFIO_PCF0_CAN0_REMAP_1 (0x2U << AFIO_PCF0_CAN0_REMAP_Pos) /*!< 0x00004000 */ /*!< CAN_REMAP configuration */ #define AFIO_PCF0_CAN0_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ #define AFIO_PCF0_CAN0_REMAP_REMAP2_Pos (14U) #define AFIO_PCF0_CAN0_REMAP_REMAP2_Msk (0x1U << AFIO_PCF0_CAN0_REMAP_REMAP2_Pos) /*!< 0x00004000 */ #define AFIO_PCF0_CAN0_REMAP_REMAP2 AFIO_PCF0_CAN0_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ #define AFIO_PCF0_CAN0_REMAP_REMAP3_Pos (13U) #define AFIO_PCF0_CAN0_REMAP_REMAP3_Msk (0x3U << AFIO_PCF0_CAN0_REMAP_REMAP3_Pos) /*!< 0x00006000 */ #define AFIO_PCF0_CAN0_REMAP_REMAP3 AFIO_PCF0_CAN0_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ #define AFIO_PCF0_PD01_REMAP_Pos (15U) #define AFIO_PCF0_PD01_REMAP_Msk (0x1U << AFIO_PCF0_PD01_REMAP_Pos) /*!< 0x00008000 */ #define AFIO_PCF0_PD01_REMAP AFIO_PCF0_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ #define AFIO_PCF0_TIM4CH3_IREMAP_Pos (16U) #define AFIO_PCF0_TIM4CH3_IREMAP_Msk (0x1U << AFIO_PCF0_TIM4CH3_IREMAP_Pos) /*!< 0x00010000 */ #define AFIO_PCF0_TIM4CH3_IREMAP AFIO_PCF0_TIM4CH3_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */ /*!< SWJ_CFG configuration */ #define AFIO_PCF0_SWJ_CFG_Pos (24U) #define AFIO_PCF0_SWJ_CFG_Msk (0x7U << AFIO_PCF0_SWJ_CFG_Pos) /*!< 0x07000000 */ #define AFIO_PCF0_SWJ_CFG AFIO_PCF0_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ #define AFIO_PCF0_SWJ_CFG_0 (0x1U << AFIO_PCF0_SWJ_CFG_Pos) /*!< 0x01000000 */ #define AFIO_PCF0_SWJ_CFG_1 (0x2U << AFIO_PCF0_SWJ_CFG_Pos) /*!< 0x02000000 */ #define AFIO_PCF0_SWJ_CFG_2 (0x4U << AFIO_PCF0_SWJ_CFG_Pos) /*!< 0x04000000 */ #define AFIO_PCF0_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ #define AFIO_PCF0_SWJ_CFG_NOJNTRST_Pos (24U) #define AFIO_PCF0_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_PCF0_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ #define AFIO_PCF0_SWJ_CFG_NOJNTRST AFIO_PCF0_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ #define AFIO_PCF0_SWJ_CFG_JTAGDISABLE_Pos (25U) #define AFIO_PCF0_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_PCF0_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ #define AFIO_PCF0_SWJ_CFG_JTAGDISABLE AFIO_PCF0_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ #define AFIO_PCF0_SWJ_CFG_DISABLE_Pos (26U) #define AFIO_PCF0_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_PCF0_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ #define AFIO_PCF0_SWJ_CFG_DISABLE AFIO_PCF0_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ /*!< CAN2_REMAP configuration */ #define AFIO_PCF0_CAN1_REMAP_Pos (22U) #define AFIO_PCF0_CAN1_REMAP_Msk (0x1U << AFIO_PCF0_CAN1_REMAP_Pos) /*!< 0x00400000 */ #define AFIO_PCF0_CAN1_REMAP AFIO_PCF0_CAN1_REMAP_Msk /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ /*!< SPI2_REMAP configuration */ #define AFIO_PCF0_SPI2_REMAP_Pos (28U) #define AFIO_PCF0_SPI2_REMAP_Msk (0x1U << AFIO_PCF0_SPI2_REMAP_Pos) /*!< 0x10000000 */ #define AFIO_PCF0_SPI2_REMAP AFIO_PCF0_SPI2_REMAP_Msk /*!< SPI2_REMAP bit (SPI2 remapping) */ /*!< TIM2ITR1_IREMAP configuration */ #define AFIO_PCF0_TIM1ITR1_IREMAP_Pos (29U) #define AFIO_PCF0_TIM1ITR1_IREMAP_Msk (0x1U << AFIO_PCF0_TIM1ITR1_IREMAP_Pos) /*!< 0x20000000 */ #define AFIO_PCF0_TIM1ITR1_IREMAP AFIO_PCF0_TIM1ITR1_IREMAP_Msk /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ /***************** Bit definition for AFIO_EXTISS0 register *****************/ #define AFIO_EXTISS0_EXTI0_SS_Pos (0U) #define AFIO_EXTISS0_EXTI0_SS_Msk (0xFU << AFIO_EXTISS0_EXTI0_SS_Pos) /*!< 0x0000000F */ #define AFIO_EXTISS0_EXTI0_SS AFIO_EXTISS0_EXTI0_SS_Msk /*!< EXTI 0 configuration */ #define AFIO_EXTISS0_EXTI1_SS_Pos (4U) #define AFIO_EXTISS0_EXTI1_SS_Msk (0xFU << AFIO_EXTISS0_EXTI1_SS_Pos) /*!< 0x000000F0 */ #define AFIO_EXTISS0_EXTI1_SS AFIO_EXTISS0_EXTI1_SS_Msk /*!< EXTI 1 configuration */ #define AFIO_EXTISS0_EXTI2_SS_Pos (8U) #define AFIO_EXTISS0_EXTI2_SS_Msk (0xFU << AFIO_EXTISS0_EXTI2_SS_Pos) /*!< 0x00000F00 */ #define AFIO_EXTISS0_EXTI2_SS AFIO_EXTISS0_EXTI2_SS_Msk /*!< EXTI 2 configuration */ #define AFIO_EXTISS0_EXTI3_SS_Pos (12U) #define AFIO_EXTISS0_EXTI3_SS_Msk (0xFU << AFIO_EXTISS0_EXTI3_SS_Pos) /*!< 0x0000F000 */ #define AFIO_EXTISS0_EXTI3_SS AFIO_EXTISS0_EXTI3_SS_Msk /*!< EXTI 3 configuration */ /*!< EXTI0 configuration */ #define AFIO_EXTISS0_EXTI0_SS_PA 0x00000000U /*!< PA[0] pin */ #define AFIO_EXTISS0_EXTI0_SS_PB_Pos (0U) #define AFIO_EXTISS0_EXTI0_SS_PB_Msk (0x1U << AFIO_EXTISS0_EXTI0_SS_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTISS0_EXTI0_SS_PB AFIO_EXTISS0_EXTI0_SS_PB_Msk /*!< PB[0] pin */ #define AFIO_EXTISS0_EXTI0_SS_PC_Pos (1U) #define AFIO_EXTISS0_EXTI0_SS_PC_Msk (0x1U << AFIO_EXTISS0_EXTI0_SS_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTISS0_EXTI0_SS_PC AFIO_EXTISS0_EXTI0_SS_PC_Msk /*!< PC[0] pin */ #define AFIO_EXTISS0_EXTI0_SS_PD_Pos (0U) #define AFIO_EXTISS0_EXTI0_SS_PD_Msk (0x3U << AFIO_EXTISS0_EXTI0_SS_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTISS0_EXTI0_SS_PD AFIO_EXTISS0_EXTI0_SS_PD_Msk /*!< PD[0] pin */ #define AFIO_EXTISS0_EXTI0_SS_PE_Pos (2U) #define AFIO_EXTISS0_EXTI0_SS_PE_Msk (0x1U << AFIO_EXTISS0_EXTI0_SS_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTISS0_EXTI0_SS_PE AFIO_EXTISS0_EXTI0_SS_PE_Msk /*!< PE[0] pin */ #define AFIO_EXTISS0_EXTI0_SS_PF_Pos (0U) #define AFIO_EXTISS0_EXTI0_SS_PF_Msk (0x5U << AFIO_EXTISS0_EXTI0_SS_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTISS0_EXTI0_SS_PF AFIO_EXTISS0_EXTI0_SS_PF_Msk /*!< PF[0] pin */ #define AFIO_EXTISS0_EXTI0_SS_PG_Pos (1U) #define AFIO_EXTISS0_EXTI0_SS_PG_Msk (0x3U << AFIO_EXTISS0_EXTI0_SS_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTISS0_EXTI0_SS_PG AFIO_EXTISS0_EXTI0_SS_PG_Msk /*!< PG[0] pin */ /*!< EXTI1 configuration */ #define AFIO_EXTISS0_EXTI1_SS_PA 0x00000000U /*!< PA[1] pin */ #define AFIO_EXTISS0_EXTI1_SS_PB_Pos (4U) #define AFIO_EXTISS0_EXTI1_SS_PB_Msk (0x1U << AFIO_EXTISS0_EXTI1_SS_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTISS0_EXTI1_SS_PB AFIO_EXTISS0_EXTI1_SS_PB_Msk /*!< PB[1] pin */ #define AFIO_EXTISS0_EXTI1_SS_PC_Pos (5U) #define AFIO_EXTISS0_EXTI1_SS_PC_Msk (0x1U << AFIO_EXTISS0_EXTI1_SS_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTISS0_EXTI1_SS_PC AFIO_EXTISS0_EXTI1_SS_PC_Msk /*!< PC[1] pin */ #define AFIO_EXTISS0_EXTI1_SS_PD_Pos (4U) #define AFIO_EXTISS0_EXTI1_SS_PD_Msk (0x3U << AFIO_EXTISS0_EXTI1_SS_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTISS0_EXTI1_SS_PD AFIO_EXTISS0_EXTI1_SS_PD_Msk /*!< PD[1] pin */ #define AFIO_EXTISS0_EXTI1_SS_PE_Pos (6U) #define AFIO_EXTISS0_EXTI1_SS_PE_Msk (0x1U << AFIO_EXTISS0_EXTI1_SS_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTISS0_EXTI1_SS_PE AFIO_EXTISS0_EXTI1_SS_PE_Msk /*!< PE[1] pin */ #define AFIO_EXTISS0_EXTI1_SS_PF_Pos (4U) #define AFIO_EXTISS0_EXTI1_SS_PF_Msk (0x5U << AFIO_EXTISS0_EXTI1_SS_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTISS0_EXTI1_SS_PF AFIO_EXTISS0_EXTI1_SS_PF_Msk /*!< PF[1] pin */ #define AFIO_EXTISS0_EXTI1_SS_PG_Pos (5U) #define AFIO_EXTISS0_EXTI1_SS_PG_Msk (0x3U << AFIO_EXTISS0_EXTI1_SS_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTISS0_EXTI1_SS_PG AFIO_EXTISS0_EXTI1_SS_PG_Msk /*!< PG[1] pin */ /*!< EXTI2 configuration */ #define AFIO_EXTISS0_EXTI2_SS_PA 0x00000000U /*!< PA[2] pin */ #define AFIO_EXTISS0_EXTI2_SS_PB_Pos (8U) #define AFIO_EXTISS0_EXTI2_SS_PB_Msk (0x1U << AFIO_EXTISS0_EXTI2_SS_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTISS0_EXTI2_SS_PB AFIO_EXTISS0_EXTI2_SS_PB_Msk /*!< PB[2] pin */ #define AFIO_EXTISS0_EXTI2_SS_PC_Pos (9U) #define AFIO_EXTISS0_EXTI2_SS_PC_Msk (0x1U << AFIO_EXTISS0_EXTI2_SS_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTISS0_EXTI2_SS_PC AFIO_EXTISS0_EXTI2_SS_PC_Msk /*!< PC[2] pin */ #define AFIO_EXTISS0_EXTI2_SS_PD_Pos (8U) #define AFIO_EXTISS0_EXTI2_SS_PD_Msk (0x3U << AFIO_EXTISS0_EXTI2_SS_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTISS0_EXTI2_SS_PD AFIO_EXTISS0_EXTI2_SS_PD_Msk /*!< PD[2] pin */ #define AFIO_EXTISS0_EXTI2_SS_PE_Pos (10U) #define AFIO_EXTISS0_EXTI2_SS_PE_Msk (0x1U << AFIO_EXTISS0_EXTI2_SS_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTISS0_EXTI2_SS_PE AFIO_EXTISS0_EXTI2_SS_PE_Msk /*!< PE[2] pin */ #define AFIO_EXTISS0_EXTI2_SS_PF_Pos (8U) #define AFIO_EXTISS0_EXTI2_SS_PF_Msk (0x5U << AFIO_EXTISS0_EXTI2_SS_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTISS0_EXTI2_SS_PF AFIO_EXTISS0_EXTI2_SS_PF_Msk /*!< PF[2] pin */ #define AFIO_EXTISS0_EXTI2_SS_PG_Pos (9U) #define AFIO_EXTISS0_EXTI2_SS_PG_Msk (0x3U << AFIO_EXTISS0_EXTI2_SS_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTISS0_EXTI2_SS_PG AFIO_EXTISS0_EXTI2_SS_PG_Msk /*!< PG[2] pin */ /*!< EXTI3 configuration */ #define AFIO_EXTISS0_EXTI3_SS_PA 0x00000000U /*!< PA[3] pin */ #define AFIO_EXTISS0_EXTI3_SS_PB_Pos (12U) #define AFIO_EXTISS0_EXTI3_SS_PB_Msk (0x1U << AFIO_EXTISS0_EXTI3_SS_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTISS0_EXTI3_SS_PB AFIO_EXTISS0_EXTI3_SS_PB_Msk /*!< PB[3] pin */ #define AFIO_EXTISS0_EXTI3_SS_PC_Pos (13U) #define AFIO_EXTISS0_EXTI3_SS_PC_Msk (0x1U << AFIO_EXTISS0_EXTI3_SS_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTISS0_EXTI3_SS_PC AFIO_EXTISS0_EXTI3_SS_PC_Msk /*!< PC[3] pin */ #define AFIO_EXTISS0_EXTI3_SS_PD_Pos (12U) #define AFIO_EXTISS0_EXTI3_SS_PD_Msk (0x3U << AFIO_EXTISS0_EXTI3_SS_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTISS0_EXTI3_SS_PD AFIO_EXTISS0_EXTI3_SS_PD_Msk /*!< PD[3] pin */ #define AFIO_EXTISS0_EXTI3_SS_PE_Pos (14U) #define AFIO_EXTISS0_EXTI3_SS_PE_Msk (0x1U << AFIO_EXTISS0_EXTI3_SS_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTISS0_EXTI3_SS_PE AFIO_EXTISS0_EXTI3_SS_PE_Msk /*!< PE[3] pin */ #define AFIO_EXTISS0_EXTI3_SS_PF_Pos (12U) #define AFIO_EXTISS0_EXTI3_SS_PF_Msk (0x5U << AFIO_EXTISS0_EXTI3_SS_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTISS0_EXTI3_SS_PF AFIO_EXTISS0_EXTI3_SS_PF_Msk /*!< PF[3] pin */ #define AFIO_EXTISS0_EXTI3_SS_PG_Pos (13U) #define AFIO_EXTISS0_EXTI3_SS_PG_Msk (0x3U << AFIO_EXTISS0_EXTI3_SS_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTISS0_EXTI3_SS_PG AFIO_EXTISS0_EXTI3_SS_PG_Msk /*!< PG[3] pin */ /***************** Bit definition for AFIO_EXTISS1 register *****************/ #define AFIO_EXTISS1_EXTI4_SS_Pos (0U) #define AFIO_EXTISS1_EXTI4_SS_Msk (0xFU << AFIO_EXTISS1_EXTI4_SS_Pos) /*!< 0x0000000F */ #define AFIO_EXTISS1_EXTI4_SS AFIO_EXTISS1_EXTI4_SS_Msk /*!< EXTI 4 configuration */ #define AFIO_EXTISS1_EXTI5_SS_Pos (4U) #define AFIO_EXTISS1_EXTI5_SS_Msk (0xFU << AFIO_EXTISS1_EXTI5_SS_Pos) /*!< 0x000000F0 */ #define AFIO_EXTISS1_EXTI5_SS AFIO_EXTISS1_EXTI5_SS_Msk /*!< EXTI 5 configuration */ #define AFIO_EXTISS1_EXTI6_SS_Pos (8U) #define AFIO_EXTISS1_EXTI6_SS_Msk (0xFU << AFIO_EXTISS1_EXTI6_SS_Pos) /*!< 0x00000F00 */ #define AFIO_EXTISS1_EXTI6_SS AFIO_EXTISS1_EXTI6_SS_Msk /*!< EXTI 6 configuration */ #define AFIO_EXTISS1_EXTI7_SS_Pos (12U) #define AFIO_EXTISS1_EXTI7_SS_Msk (0xFU << AFIO_EXTISS1_EXTI7_SS_Pos) /*!< 0x0000F000 */ #define AFIO_EXTISS1_EXTI7_SS AFIO_EXTISS1_EXTI7_SS_Msk /*!< EXTI 7 configuration */ /*!< EXTI4 configuration */ #define AFIO_EXTISS1_EXTI4_SS_PA 0x00000000U /*!< PA[4] pin */ #define AFIO_EXTISS1_EXTI4_SS_PB_Pos (0U) #define AFIO_EXTISS1_EXTI4_SS_PB_Msk (0x1U << AFIO_EXTISS1_EXTI4_SS_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTISS1_EXTI4_SS_PB AFIO_EXTISS1_EXTI4_SS_PB_Msk /*!< PB[4] pin */ #define AFIO_EXTISS1_EXTI4_SS_PC_Pos (1U) #define AFIO_EXTISS1_EXTI4_SS_PC_Msk (0x1U << AFIO_EXTISS1_EXTI4_SS_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTISS1_EXTI4_SS_PC AFIO_EXTISS1_EXTI4_SS_PC_Msk /*!< PC[4] pin */ #define AFIO_EXTISS1_EXTI4_SS_PD_Pos (0U) #define AFIO_EXTISS1_EXTI4_SS_PD_Msk (0x3U << AFIO_EXTISS1_EXTI4_SS_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTISS1_EXTI4_SS_PD AFIO_EXTISS1_EXTI4_SS_PD_Msk /*!< PD[4] pin */ #define AFIO_EXTISS1_EXTI4_SS_PE_Pos (2U) #define AFIO_EXTISS1_EXTI4_SS_PE_Msk (0x1U << AFIO_EXTISS1_EXTI4_SS_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTISS1_EXTI4_SS_PE AFIO_EXTISS1_EXTI4_SS_PE_Msk /*!< PE[4] pin */ #define AFIO_EXTISS1_EXTI4_SS_PF_Pos (0U) #define AFIO_EXTISS1_EXTI4_SS_PF_Msk (0x5U << AFIO_EXTISS1_EXTI4_SS_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTISS1_EXTI4_SS_PF AFIO_EXTISS1_EXTI4_SS_PF_Msk /*!< PF[4] pin */ #define AFIO_EXTISS1_EXTI4_SS_PG_Pos (1U) #define AFIO_EXTISS1_EXTI4_SS_PG_Msk (0x3U << AFIO_EXTISS1_EXTI4_SS_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTISS1_EXTI4_SS_PG AFIO_EXTISS1_EXTI4_SS_PG_Msk /*!< PG[4] pin */ /* EXTI5 configuration */ #define AFIO_EXTISS1_EXTI5_SS_PA 0x00000000U /*!< PA[5] pin */ #define AFIO_EXTISS1_EXTI5_SS_PB_Pos (4U) #define AFIO_EXTISS1_EXTI5_SS_PB_Msk (0x1U << AFIO_EXTISS1_EXTI5_SS_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTISS1_EXTI5_SS_PB AFIO_EXTISS1_EXTI5_SS_PB_Msk /*!< PB[5] pin */ #define AFIO_EXTISS1_EXTI5_SS_PC_Pos (5U) #define AFIO_EXTISS1_EXTI5_SS_PC_Msk (0x1U << AFIO_EXTISS1_EXTI5_SS_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTISS1_EXTI5_SS_PC AFIO_EXTISS1_EXTI5_SS_PC_Msk /*!< PC[5] pin */ #define AFIO_EXTISS1_EXTI5_SS_PD_Pos (4U) #define AFIO_EXTISS1_EXTI5_SS_PD_Msk (0x3U << AFIO_EXTISS1_EXTI5_SS_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTISS1_EXTI5_SS_PD AFIO_EXTISS1_EXTI5_SS_PD_Msk /*!< PD[5] pin */ #define AFIO_EXTISS1_EXTI5_SS_PE_Pos (6U) #define AFIO_EXTISS1_EXTI5_SS_PE_Msk (0x1U << AFIO_EXTISS1_EXTI5_SS_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTISS1_EXTI5_SS_PE AFIO_EXTISS1_EXTI5_SS_PE_Msk /*!< PE[5] pin */ #define AFIO_EXTISS1_EXTI5_SS_PF_Pos (4U) #define AFIO_EXTISS1_EXTI5_SS_PF_Msk (0x5U << AFIO_EXTISS1_EXTI5_SS_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTISS1_EXTI5_SS_PF AFIO_EXTISS1_EXTI5_SS_PF_Msk /*!< PF[5] pin */ #define AFIO_EXTISS1_EXTI5_SS_PG_Pos (5U) #define AFIO_EXTISS1_EXTI5_SS_PG_Msk (0x3U << AFIO_EXTISS1_EXTI5_SS_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTISS1_EXTI5_SS_PG AFIO_EXTISS1_EXTI5_SS_PG_Msk /*!< PG[5] pin */ /*!< EXTI6 configuration */ #define AFIO_EXTISS1_EXTI6_SS_PA 0x00000000U /*!< PA[6] pin */ #define AFIO_EXTISS1_EXTI6_SS_PB_Pos (8U) #define AFIO_EXTISS1_EXTI6_SS_PB_Msk (0x1U << AFIO_EXTISS1_EXTI6_SS_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTISS1_EXTI6_SS_PB AFIO_EXTISS1_EXTI6_SS_PB_Msk /*!< PB[6] pin */ #define AFIO_EXTISS1_EXTI6_SS_PC_Pos (9U) #define AFIO_EXTISS1_EXTI6_SS_PC_Msk (0x1U << AFIO_EXTISS1_EXTI6_SS_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTISS1_EXTI6_SS_PC AFIO_EXTISS1_EXTI6_SS_PC_Msk /*!< PC[6] pin */ #define AFIO_EXTISS1_EXTI6_SS_PD_Pos (8U) #define AFIO_EXTISS1_EXTI6_SS_PD_Msk (0x3U << AFIO_EXTISS1_EXTI6_SS_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTISS1_EXTI6_SS_PD AFIO_EXTISS1_EXTI6_SS_PD_Msk /*!< PD[6] pin */ #define AFIO_EXTISS1_EXTI6_SS_PE_Pos (10U) #define AFIO_EXTISS1_EXTI6_SS_PE_Msk (0x1U << AFIO_EXTISS1_EXTI6_SS_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTISS1_EXTI6_SS_PE AFIO_EXTISS1_EXTI6_SS_PE_Msk /*!< PE[6] pin */ #define AFIO_EXTISS1_EXTI6_SS_PF_Pos (8U) #define AFIO_EXTISS1_EXTI6_SS_PF_Msk (0x5U << AFIO_EXTISS1_EXTI6_SS_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTISS1_EXTI6_SS_PF AFIO_EXTISS1_EXTI6_SS_PF_Msk /*!< PF[6] pin */ #define AFIO_EXTISS1_EXTI6_SS_PG_Pos (9U) #define AFIO_EXTISS1_EXTI6_SS_PG_Msk (0x3U << AFIO_EXTISS1_EXTI6_SS_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTISS1_EXTI6_SS_PG AFIO_EXTISS1_EXTI6_SS_PG_Msk /*!< PG[6] pin */ /*!< EXTI7 configuration */ #define AFIO_EXTISS1_EXTI7_SS_PA 0x00000000U /*!< PA[7] pin */ #define AFIO_EXTISS1_EXTI7_SS_PB_Pos (12U) #define AFIO_EXTISS1_EXTI7_SS_PB_Msk (0x1U << AFIO_EXTISS1_EXTI7_SS_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTISS1_EXTI7_SS_PB AFIO_EXTISS1_EXTI7_SS_PB_Msk /*!< PB[7] pin */ #define AFIO_EXTISS1_EXTI7_SS_PC_Pos (13U) #define AFIO_EXTISS1_EXTI7_SS_PC_Msk (0x1U << AFIO_EXTISS1_EXTI7_SS_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTISS1_EXTI7_SS_PC AFIO_EXTISS1_EXTI7_SS_PC_Msk /*!< PC[7] pin */ #define AFIO_EXTISS1_EXTI7_SS_PD_Pos (12U) #define AFIO_EXTISS1_EXTI7_SS_PD_Msk (0x3U << AFIO_EXTISS1_EXTI7_SS_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTISS1_EXTI7_SS_PD AFIO_EXTISS1_EXTI7_SS_PD_Msk /*!< PD[7] pin */ #define AFIO_EXTISS1_EXTI7_SS_PE_Pos (14U) #define AFIO_EXTISS1_EXTI7_SS_PE_Msk (0x1U << AFIO_EXTISS1_EXTI7_SS_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTISS1_EXTI7_SS_PE AFIO_EXTISS1_EXTI7_SS_PE_Msk /*!< PE[7] pin */ #define AFIO_EXTISS1_EXTI7_SS_PF_Pos (12U) #define AFIO_EXTISS1_EXTI7_SS_PF_Msk (0x5U << AFIO_EXTISS1_EXTI7_SS_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTISS1_EXTI7_SS_PF AFIO_EXTISS1_EXTI7_SS_PF_Msk /*!< PF[7] pin */ #define AFIO_EXTISS1_EXTI7_SS_PG_Pos (13U) #define AFIO_EXTISS1_EXTI7_SS_PG_Msk (0x3U << AFIO_EXTISS1_EXTI7_SS_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTISS1_EXTI7_SS_PG AFIO_EXTISS1_EXTI7_SS_PG_Msk /*!< PG[7] pin */ /***************** Bit definition for AFIO_EXTISS2 register *****************/ #define AFIO_EXTISS2_EXTI8_SS_Pos (0U) #define AFIO_EXTISS2_EXTI8_SS_Msk (0xFU << AFIO_EXTISS2_EXTI8_SS_Pos) /*!< 0x0000000F */ #define AFIO_EXTISS2_EXTI8_SS AFIO_EXTISS2_EXTI8_SS_Msk /*!< EXTI 8 configuration */ #define AFIO_EXTISS2_EXTI9_SS_Pos (4U) #define AFIO_EXTISS2_EXTI9_SS_Msk (0xFU << AFIO_EXTISS2_EXTI9_SS_Pos) /*!< 0x000000F0 */ #define AFIO_EXTISS2_EXTI9_SS AFIO_EXTISS2_EXTI9_SS_Msk /*!< EXTI 9 configuration */ #define AFIO_EXTISS2_EXTI10_SS_Pos (8U) #define AFIO_EXTISS2_EXTI10_SS_Msk (0xFU << AFIO_EXTISS2_EXTI10_SS_Pos) /*!< 0x00000F00 */ #define AFIO_EXTISS2_EXTI10_SS AFIO_EXTISS2_EXTI10_SS_Msk /*!< EXTI 10 configuration */ #define AFIO_EXTISS2_EXTI11_SS_Pos (12U) #define AFIO_EXTISS2_EXTI11_SS_Msk (0xFU << AFIO_EXTISS2_EXTI11_SS_Pos) /*!< 0x0000F000 */ #define AFIO_EXTISS2_EXTI11_SS AFIO_EXTISS2_EXTI11_SS_Msk /*!< EXTI 11 configuration */ /*!< EXTI8 configuration */ #define AFIO_EXTISS2_EXTI8_SS_PA 0x00000000U /*!< PA[8] pin */ #define AFIO_EXTISS2_EXTI8_SS_PB_Pos (0U) #define AFIO_EXTISS2_EXTI8_SS_PB_Msk (0x1U << AFIO_EXTISS2_EXTI8_SS_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTISS2_EXTI8_SS_PB AFIO_EXTISS2_EXTI8_SS_PB_Msk /*!< PB[8] pin */ #define AFIO_EXTISS2_EXTI8_SS_PC_Pos (1U) #define AFIO_EXTISS2_EXTI8_SS_PC_Msk (0x1U << AFIO_EXTISS2_EXTI8_SS_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTISS2_EXTI8_SS_PC AFIO_EXTISS2_EXTI8_SS_PC_Msk /*!< PC[8] pin */ #define AFIO_EXTISS2_EXTI8_SS_PD_Pos (0U) #define AFIO_EXTISS2_EXTI8_SS_PD_Msk (0x3U << AFIO_EXTISS2_EXTI8_SS_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTISS2_EXTI8_SS_PD AFIO_EXTISS2_EXTI8_SS_PD_Msk /*!< PD[8] pin */ #define AFIO_EXTISS2_EXTI8_SS_PE_Pos (2U) #define AFIO_EXTISS2_EXTI8_SS_PE_Msk (0x1U << AFIO_EXTISS2_EXTI8_SS_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTISS2_EXTI8_SS_PE AFIO_EXTISS2_EXTI8_SS_PE_Msk /*!< PE[8] pin */ #define AFIO_EXTISS2_EXTI8_SS_PF_Pos (0U) #define AFIO_EXTISS2_EXTI8_SS_PF_Msk (0x5U << AFIO_EXTISS2_EXTI8_SS_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTISS2_EXTI8_SS_PF AFIO_EXTISS2_EXTI8_SS_PF_Msk /*!< PF[8] pin */ #define AFIO_EXTISS2_EXTI8_SS_PG_Pos (1U) #define AFIO_EXTISS2_EXTI8_SS_PG_Msk (0x3U << AFIO_EXTISS2_EXTI8_SS_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTISS2_EXTI8_SS_PG AFIO_EXTISS2_EXTI8_SS_PG_Msk /*!< PG[8] pin */ /*!< EXTI9 configuration */ #define AFIO_EXTISS2_EXTI9_SS_PA 0x00000000U /*!< PA[9] pin */ #define AFIO_EXTISS2_EXTI9_SS_PB_Pos (4U) #define AFIO_EXTISS2_EXTI9_SS_PB_Msk (0x1U << AFIO_EXTISS2_EXTI9_SS_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTISS2_EXTI9_SS_PB AFIO_EXTISS2_EXTI9_SS_PB_Msk /*!< PB[9] pin */ #define AFIO_EXTISS2_EXTI9_SS_PC_Pos (5U) #define AFIO_EXTISS2_EXTI9_SS_PC_Msk (0x1U << AFIO_EXTISS2_EXTI9_SS_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTISS2_EXTI9_SS_PC AFIO_EXTISS2_EXTI9_SS_PC_Msk /*!< PC[9] pin */ #define AFIO_EXTISS2_EXTI9_SS_PD_Pos (4U) #define AFIO_EXTISS2_EXTI9_SS_PD_Msk (0x3U << AFIO_EXTISS2_EXTI9_SS_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTISS2_EXTI9_SS_PD AFIO_EXTISS2_EXTI9_SS_PD_Msk /*!< PD[9] pin */ #define AFIO_EXTISS2_EXTI9_SS_PE_Pos (6U) #define AFIO_EXTISS2_EXTI9_SS_PE_Msk (0x1U << AFIO_EXTISS2_EXTI9_SS_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTISS2_EXTI9_SS_PE AFIO_EXTISS2_EXTI9_SS_PE_Msk /*!< PE[9] pin */ #define AFIO_EXTISS2_EXTI9_SS_PF_Pos (4U) #define AFIO_EXTISS2_EXTI9_SS_PF_Msk (0x5U << AFIO_EXTISS2_EXTI9_SS_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTISS2_EXTI9_SS_PF AFIO_EXTISS2_EXTI9_SS_PF_Msk /*!< PF[9] pin */ #define AFIO_EXTISS2_EXTI9_SS_PG_Pos (5U) #define AFIO_EXTISS2_EXTI9_SS_PG_Msk (0x3U << AFIO_EXTISS2_EXTI9_SS_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTISS2_EXTI9_SS_PG AFIO_EXTISS2_EXTI9_SS_PG_Msk /*!< PG[9] pin */ /*!< EXTI10 configuration */ #define AFIO_EXTISS2_EXTI10_SS_PA 0x00000000U /*!< PA[10] pin */ #define AFIO_EXTISS2_EXTI10_SS_PB_Pos (8U) #define AFIO_EXTISS2_EXTI10_SS_PB_Msk (0x1U << AFIO_EXTISS2_EXTI10_SS_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTISS2_EXTI10_SS_PB AFIO_EXTISS2_EXTI10_SS_PB_Msk /*!< PB[10] pin */ #define AFIO_EXTISS2_EXTI10_SS_PC_Pos (9U) #define AFIO_EXTISS2_EXTI10_SS_PC_Msk (0x1U << AFIO_EXTISS2_EXTI10_SS_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTISS2_EXTI10_SS_PC AFIO_EXTISS2_EXTI10_SS_PC_Msk /*!< PC[10] pin */ #define AFIO_EXTISS2_EXTI10_SS_PD_Pos (8U) #define AFIO_EXTISS2_EXTI10_SS_PD_Msk (0x3U << AFIO_EXTISS2_EXTI10_SS_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTISS2_EXTI10_SS_PD AFIO_EXTISS2_EXTI10_SS_PD_Msk /*!< PD[10] pin */ #define AFIO_EXTISS2_EXTI10_SS_PE_Pos (10U) #define AFIO_EXTISS2_EXTI10_SS_PE_Msk (0x1U << AFIO_EXTISS2_EXTI10_SS_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTISS2_EXTI10_SS_PE AFIO_EXTISS2_EXTI10_SS_PE_Msk /*!< PE[10] pin */ #define AFIO_EXTISS2_EXTI10_SS_PF_Pos (8U) #define AFIO_EXTISS2_EXTI10_SS_PF_Msk (0x5U << AFIO_EXTISS2_EXTI10_SS_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTISS2_EXTI10_SS_PF AFIO_EXTISS2_EXTI10_SS_PF_Msk /*!< PF[10] pin */ #define AFIO_EXTISS2_EXTI10_SS_PG_Pos (9U) #define AFIO_EXTISS2_EXTI10_SS_PG_Msk (0x3U << AFIO_EXTISS2_EXTI10_SS_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTISS2_EXTI10_SS_PG AFIO_EXTISS2_EXTI10_SS_PG_Msk /*!< PG[10] pin */ /*!< EXTI11 configuration */ #define AFIO_EXTISS2_EXTI11_SS_PA 0x00000000U /*!< PA[11] pin */ #define AFIO_EXTISS2_EXTI11_SS_PB_Pos (12U) #define AFIO_EXTISS2_EXTI11_SS_PB_Msk (0x1U << AFIO_EXTISS2_EXTI11_SS_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTISS2_EXTI11_SS_PB AFIO_EXTISS2_EXTI11_SS_PB_Msk /*!< PB[11] pin */ #define AFIO_EXTISS2_EXTI11_SS_PC_Pos (13U) #define AFIO_EXTISS2_EXTI11_SS_PC_Msk (0x1U << AFIO_EXTISS2_EXTI11_SS_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTISS2_EXTI11_SS_PC AFIO_EXTISS2_EXTI11_SS_PC_Msk /*!< PC[11] pin */ #define AFIO_EXTISS2_EXTI11_SS_PD_Pos (12U) #define AFIO_EXTISS2_EXTI11_SS_PD_Msk (0x3U << AFIO_EXTISS2_EXTI11_SS_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTISS2_EXTI11_SS_PD AFIO_EXTISS2_EXTI11_SS_PD_Msk /*!< PD[11] pin */ #define AFIO_EXTISS2_EXTI11_SS_PE_Pos (14U) #define AFIO_EXTISS2_EXTI11_SS_PE_Msk (0x1U << AFIO_EXTISS2_EXTI11_SS_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTISS2_EXTI11_SS_PE AFIO_EXTISS2_EXTI11_SS_PE_Msk /*!< PE[11] pin */ #define AFIO_EXTISS2_EXTI11_SS_PF_Pos (12U) #define AFIO_EXTISS2_EXTI11_SS_PF_Msk (0x5U << AFIO_EXTISS2_EXTI11_SS_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTISS2_EXTI11_SS_PF AFIO_EXTISS2_EXTI11_SS_PF_Msk /*!< PF[11] pin */ #define AFIO_EXTISS2_EXTI11_SS_PG_Pos (13U) #define AFIO_EXTISS2_EXTI11_SS_PG_Msk (0x3U << AFIO_EXTISS2_EXTI11_SS_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTISS2_EXTI11_SS_PG AFIO_EXTISS2_EXTI11_SS_PG_Msk /*!< PG[11] pin */ /***************** Bit definition for AFIO_EXTISS3 register *****************/ #define AFIO_EXTISS3_EXTI12_SS_Pos (0U) #define AFIO_EXTISS3_EXTI12_SS_Msk (0xFU << AFIO_EXTISS3_EXTI12_SS_Pos) /*!< 0x0000000F */ #define AFIO_EXTISS3_EXTI12_SS AFIO_EXTISS3_EXTI12_SS_Msk /*!< EXTI 12 configuration */ #define AFIO_EXTISS3_EXTI13_SS_Pos (4U) #define AFIO_EXTISS3_EXTI13_SS_Msk (0xFU << AFIO_EXTISS3_EXTI13_SS_Pos) /*!< 0x000000F0 */ #define AFIO_EXTISS3_EXTI13_SS AFIO_EXTISS3_EXTI13_SS_Msk /*!< EXTI 13 configuration */ #define AFIO_EXTISS3_EXTI14_SS_Pos (8U) #define AFIO_EXTISS3_EXTI14_SS_Msk (0xFU << AFIO_EXTISS3_EXTI14_SS_Pos) /*!< 0x00000F00 */ #define AFIO_EXTISS3_EXTI14_SS AFIO_EXTISS3_EXTI14_SS_Msk /*!< EXTI 14 configuration */ #define AFIO_EXTISS3_EXTI15_SS_Pos (12U) #define AFIO_EXTISS3_EXTI15_SS_Msk (0xFU << AFIO_EXTISS3_EXTI15_SS_Pos) /*!< 0x0000F000 */ #define AFIO_EXTISS3_EXTI15_SS AFIO_EXTISS3_EXTI15_SS_Msk /*!< EXTI 15 configuration */ /* EXTI12 configuration */ #define AFIO_EXTISS3_EXTI12_SS_PA 0x00000000U /*!< PA[12] pin */ #define AFIO_EXTISS3_EXTI12_SS_PB_Pos (0U) #define AFIO_EXTISS3_EXTI12_SS_PB_Msk (0x1U << AFIO_EXTISS3_EXTI12_SS_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTISS3_EXTI12_SS_PB AFIO_EXTISS3_EXTI12_SS_PB_Msk /*!< PB[12] pin */ #define AFIO_EXTISS3_EXTI12_SS_PC_Pos (1U) #define AFIO_EXTISS3_EXTI12_SS_PC_Msk (0x1U << AFIO_EXTISS3_EXTI12_SS_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTISS3_EXTI12_SS_PC AFIO_EXTISS3_EXTI12_SS_PC_Msk /*!< PC[12] pin */ #define AFIO_EXTISS3_EXTI12_SS_PD_Pos (0U) #define AFIO_EXTISS3_EXTI12_SS_PD_Msk (0x3U << AFIO_EXTISS3_EXTI12_SS_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTISS3_EXTI12_SS_PD AFIO_EXTISS3_EXTI12_SS_PD_Msk /*!< PD[12] pin */ #define AFIO_EXTISS3_EXTI12_SS_PE_Pos (2U) #define AFIO_EXTISS3_EXTI12_SS_PE_Msk (0x1U << AFIO_EXTISS3_EXTI12_SS_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTISS3_EXTI12_SS_PE AFIO_EXTISS3_EXTI12_SS_PE_Msk /*!< PE[12] pin */ #define AFIO_EXTISS3_EXTI12_SS_PF_Pos (0U) #define AFIO_EXTISS3_EXTI12_SS_PF_Msk (0x5U << AFIO_EXTISS3_EXTI12_SS_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTISS3_EXTI12_SS_PF AFIO_EXTISS3_EXTI12_SS_PF_Msk /*!< PF[12] pin */ #define AFIO_EXTISS3_EXTI12_SS_PG_Pos (1U) #define AFIO_EXTISS3_EXTI12_SS_PG_Msk (0x3U << AFIO_EXTISS3_EXTI12_SS_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTISS3_EXTI12_SS_PG AFIO_EXTISS3_EXTI12_SS_PG_Msk /*!< PG[12] pin */ /* EXTI13 configuration */ #define AFIO_EXTISS3_EXTI13_SS_PA 0x00000000U /*!< PA[13] pin */ #define AFIO_EXTISS3_EXTI13_SS_PB_Pos (4U) #define AFIO_EXTISS3_EXTI13_SS_PB_Msk (0x1U << AFIO_EXTISS3_EXTI13_SS_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTISS3_EXTI13_SS_PB AFIO_EXTISS3_EXTI13_SS_PB_Msk /*!< PB[13] pin */ #define AFIO_EXTISS3_EXTI13_SS_PC_Pos (5U) #define AFIO_EXTISS3_EXTI13_SS_PC_Msk (0x1U << AFIO_EXTISS3_EXTI13_SS_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTISS3_EXTI13_SS_PC AFIO_EXTISS3_EXTI13_SS_PC_Msk /*!< PC[13] pin */ #define AFIO_EXTISS3_EXTI13_SS_PD_Pos (4U) #define AFIO_EXTISS3_EXTI13_SS_PD_Msk (0x3U << AFIO_EXTISS3_EXTI13_SS_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTISS3_EXTI13_SS_PD AFIO_EXTISS3_EXTI13_SS_PD_Msk /*!< PD[13] pin */ #define AFIO_EXTISS3_EXTI13_SS_PE_Pos (6U) #define AFIO_EXTISS3_EXTI13_SS_PE_Msk (0x1U << AFIO_EXTISS3_EXTI13_SS_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTISS3_EXTI13_SS_PE AFIO_EXTISS3_EXTI13_SS_PE_Msk /*!< PE[13] pin */ #define AFIO_EXTISS3_EXTI13_SS_PF_Pos (4U) #define AFIO_EXTISS3_EXTI13_SS_PF_Msk (0x5U << AFIO_EXTISS3_EXTI13_SS_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTISS3_EXTI13_SS_PF AFIO_EXTISS3_EXTI13_SS_PF_Msk /*!< PF[13] pin */ #define AFIO_EXTISS3_EXTI13_SS_PG_Pos (5U) #define AFIO_EXTISS3_EXTI13_SS_PG_Msk (0x3U << AFIO_EXTISS3_EXTI13_SS_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTISS3_EXTI13_SS_PG AFIO_EXTISS3_EXTI13_SS_PG_Msk /*!< PG[13] pin */ /*!< EXTI14 configuration */ #define AFIO_EXTISS3_EXTI14_SS_PA 0x00000000U /*!< PA[14] pin */ #define AFIO_EXTISS3_EXTI14_SS_PB_Pos (8U) #define AFIO_EXTISS3_EXTI14_SS_PB_Msk (0x1U << AFIO_EXTISS3_EXTI14_SS_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTISS3_EXTI14_SS_PB AFIO_EXTISS3_EXTI14_SS_PB_Msk /*!< PB[14] pin */ #define AFIO_EXTISS3_EXTI14_SS_PC_Pos (9U) #define AFIO_EXTISS3_EXTI14_SS_PC_Msk (0x1U << AFIO_EXTISS3_EXTI14_SS_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTISS3_EXTI14_SS_PC AFIO_EXTISS3_EXTI14_SS_PC_Msk /*!< PC[14] pin */ #define AFIO_EXTISS3_EXTI14_SS_PD_Pos (8U) #define AFIO_EXTISS3_EXTI14_SS_PD_Msk (0x3U << AFIO_EXTISS3_EXTI14_SS_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTISS3_EXTI14_SS_PD AFIO_EXTISS3_EXTI14_SS_PD_Msk /*!< PD[14] pin */ #define AFIO_EXTISS3_EXTI14_SS_PE_Pos (10U) #define AFIO_EXTISS3_EXTI14_SS_PE_Msk (0x1U << AFIO_EXTISS3_EXTI14_SS_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTISS3_EXTI14_SS_PE AFIO_EXTISS3_EXTI14_SS_PE_Msk /*!< PE[14] pin */ #define AFIO_EXTISS3_EXTI14_SS_PF_Pos (8U) #define AFIO_EXTISS3_EXTI14_SS_PF_Msk (0x5U << AFIO_EXTISS3_EXTI14_SS_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTISS3_EXTI14_SS_PF AFIO_EXTISS3_EXTI14_SS_PF_Msk /*!< PF[14] pin */ #define AFIO_EXTISS3_EXTI14_SS_PG_Pos (9U) #define AFIO_EXTISS3_EXTI14_SS_PG_Msk (0x3U << AFIO_EXTISS3_EXTI14_SS_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTISS3_EXTI14_SS_PG AFIO_EXTISS3_EXTI14_SS_PG_Msk /*!< PG[14] pin */ /*!< EXTI15 configuration */ #define AFIO_EXTISS3_EXTI15_SS_PA 0x00000000U /*!< PA[15] pin */ #define AFIO_EXTISS3_EXTI15_SS_PB_Pos (12U) #define AFIO_EXTISS3_EXTI15_SS_PB_Msk (0x1U << AFIO_EXTISS3_EXTI15_SS_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTISS3_EXTI15_SS_PB AFIO_EXTISS3_EXTI15_SS_PB_Msk /*!< PB[15] pin */ #define AFIO_EXTISS3_EXTI15_SS_PC_Pos (13U) #define AFIO_EXTISS3_EXTI15_SS_PC_Msk (0x1U << AFIO_EXTISS3_EXTI15_SS_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTISS3_EXTI15_SS_PC AFIO_EXTISS3_EXTI15_SS_PC_Msk /*!< PC[15] pin */ #define AFIO_EXTISS3_EXTI15_SS_PD_Pos (12U) #define AFIO_EXTISS3_EXTI15_SS_PD_Msk (0x3U << AFIO_EXTISS3_EXTI15_SS_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTISS3_EXTI15_SS_PD AFIO_EXTISS3_EXTI15_SS_PD_Msk /*!< PD[15] pin */ #define AFIO_EXTISS3_EXTI15_SS_PE_Pos (14U) #define AFIO_EXTISS3_EXTI15_SS_PE_Msk (0x1U << AFIO_EXTISS3_EXTI15_SS_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTISS3_EXTI15_SS_PE AFIO_EXTISS3_EXTI15_SS_PE_Msk /*!< PE[15] pin */ #define AFIO_EXTISS3_EXTI15_SS_PF_Pos (12U) #define AFIO_EXTISS3_EXTI15_SS_PF_Msk (0x5U << AFIO_EXTISS3_EXTI15_SS_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTISS3_EXTI15_SS_PF AFIO_EXTISS3_EXTI15_SS_PF_Msk /*!< PF[15] pin */ #define AFIO_EXTISS3_EXTI15_SS_PG_Pos (13U) #define AFIO_EXTISS3_EXTI15_SS_PG_Msk (0x3U << AFIO_EXTISS3_EXTI15_SS_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTISS3_EXTI15_SS_PG AFIO_EXTISS3_EXTI15_SS_PG_Msk /*!< PG[15] pin */ /****************** Bit definition for AFIO_PCF1 register ******************/ #define AFIO_PCF1_EXMC_NADV_REMAP_Pos (10U) #define AFIO_PCF1_EXMC_NADV_REMAP_Msk (0x1U << AFIO_PCF1_EXMC_NADV_REMAP_Pos) /*!< 0x00000400 */ #define AFIO_PCF1_EXMC_NADV_REMAP AFIO_PCF1_EXMC_NADV_REMAP_Msk /*!< EXMC NADV remapping */ /******************************************************************************/ /* */ /* DMA Controller */ /* */ /******************************************************************************/ /******************* Bit definition for DMA_INTF register ********************/ #define DMA_INTF_GIF0_Pos (0U) #define DMA_INTF_GIF0_Msk (0x1U << DMA_INTF_GIF0_Pos) /*!< 0x00000001 */ #define DMA_INTF_GIF0 DMA_INTF_GIF0_Msk /*!< Channel 1 Global interrupt flag */ #define DMA_INTF_FTFIF0_Pos (1U) #define DMA_INTF_FTFIF0_Msk (0x1U << DMA_INTF_FTFIF0_Pos) /*!< 0x00000002 */ #define DMA_INTF_FTFIF0 DMA_INTF_FTFIF0_Msk /*!< Channel 1 Full Transfer finish flag */ #define DMA_INTF_HTFIF0_Pos (2U) #define DMA_INTF_HTFIF0_Msk (0x1U << DMA_INTF_HTFIF0_Pos) /*!< 0x00000004 */ #define DMA_INTF_HTFIF0 DMA_INTF_HTFIF0_Msk /*!< Channel 1 Half Transfer flag */ #define DMA_INTF_ERRIF0_Pos (3U) #define DMA_INTF_ERRIF0_Msk (0x1U << DMA_INTF_ERRIF0_Pos) /*!< 0x00000008 */ #define DMA_INTF_ERRIF0 DMA_INTF_ERRIF0_Msk /*!< Channel 1 Transfer Error flag */ #define DMA_INTF_GIF1_Pos (4U) #define DMA_INTF_GIF1_Msk (0x1U << DMA_INTF_GIF1_Pos) /*!< 0x00000010 */ #define DMA_INTF_GIF1 DMA_INTF_GIF1_Msk /*!< Channel 2 Global interrupt flag */ #define DMA_INTF_FTFIF1_Pos (5U) #define DMA_INTF_FTFIF1_Msk (0x1U << DMA_INTF_FTFIF1_Pos) /*!< 0x00000020 */ #define DMA_INTF_FTFIF1 DMA_INTF_FTFIF1_Msk /*!< Channel 2 Full Transfer finish flag */ #define DMA_INTF_HTFIF1_Pos (6U) #define DMA_INTF_HTFIF1_Msk (0x1U << DMA_INTF_HTFIF1_Pos) /*!< 0x00000040 */ #define DMA_INTF_HTFIF1 DMA_INTF_HTFIF1_Msk /*!< Channel 2 Half Transfer flag */ #define DMA_INTF_ERRIF1_Pos (7U) #define DMA_INTF_ERRIF1_Msk (0x1U << DMA_INTF_ERRIF1_Pos) /*!< 0x00000080 */ #define DMA_INTF_ERRIF1 DMA_INTF_ERRIF1_Msk /*!< Channel 2 Transfer Error flag */ #define DMA_INTF_GIF2_Pos (8U) #define DMA_INTF_GIF2_Msk (0x1U << DMA_INTF_GIF2_Pos) /*!< 0x00000100 */ #define DMA_INTF_GIF2 DMA_INTF_GIF2_Msk /*!< Channel 3 Global interrupt flag */ #define DMA_INTF_FTFIF2_Pos (9U) #define DMA_INTF_FTFIF2_Msk (0x1U << DMA_INTF_FTFIF2_Pos) /*!< 0x00000200 */ #define DMA_INTF_FTFIF2 DMA_INTF_FTFIF2_Msk /*!< Channel 3 Full Transfer finish flag */ #define DMA_INTF_HTFIF2_Pos (10U) #define DMA_INTF_HTFIF2_Msk (0x1U << DMA_INTF_HTFIF2_Pos) /*!< 0x00000400 */ #define DMA_INTF_HTFIF2 DMA_INTF_HTFIF2_Msk /*!< Channel 3 Half Transfer flag */ #define DMA_INTF_ERRIF2_Pos (11U) #define DMA_INTF_ERRIF2_Msk (0x1U << DMA_INTF_ERRIF2_Pos) /*!< 0x00000800 */ #define DMA_INTF_ERRIF2 DMA_INTF_ERRIF2_Msk /*!< Channel 3 Transfer Error flag */ #define DMA_INTF_GIF3_Pos (12U) #define DMA_INTF_GIF3_Msk (0x1U << DMA_INTF_GIF3_Pos) /*!< 0x00001000 */ #define DMA_INTF_GIF3 DMA_INTF_GIF3_Msk /*!< Channel 4 Global interrupt flag */ #define DMA_INTF_FTFIF3_Pos (13U) #define DMA_INTF_FTFIF3_Msk (0x1U << DMA_INTF_FTFIF3_Pos) /*!< 0x00002000 */ #define DMA_INTF_FTFIF3 DMA_INTF_FTFIF3_Msk /*!< Channel 4 Full Transfer finish flag */ #define DMA_INTF_HTFIF3_Pos (14U) #define DMA_INTF_HTFIF3_Msk (0x1U << DMA_INTF_HTFIF3_Pos) /*!< 0x00004000 */ #define DMA_INTF_HTFIF3 DMA_INTF_HTFIF3_Msk /*!< Channel 4 Half Transfer flag */ #define DMA_INTF_ERRIF3_Pos (15U) #define DMA_INTF_ERRIF3_Msk (0x1U << DMA_INTF_ERRIF3_Pos) /*!< 0x00008000 */ #define DMA_INTF_ERRIF3 DMA_INTF_ERRIF3_Msk /*!< Channel 4 Transfer Error flag */ #define DMA_INTF_GIF4_Pos (16U) #define DMA_INTF_GIF4_Msk (0x1U << DMA_INTF_GIF4_Pos) /*!< 0x00010000 */ #define DMA_INTF_GIF4 DMA_INTF_GIF4_Msk /*!< Channel 5 Global interrupt flag */ #define DMA_INTF_FTFIF4_Pos (17U) #define DMA_INTF_FTFIF4_Msk (0x1U << DMA_INTF_FTFIF4_Pos) /*!< 0x00020000 */ #define DMA_INTF_FTFIF4 DMA_INTF_FTFIF4_Msk /*!< Channel 5 Full Transfer finish flag */ #define DMA_INTF_HTFIF4_Pos (18U) #define DMA_INTF_HTFIF4_Msk (0x1U << DMA_INTF_HTFIF4_Pos) /*!< 0x00040000 */ #define DMA_INTF_HTFIF4 DMA_INTF_HTFIF4_Msk /*!< Channel 5 Half Transfer flag */ #define DMA_INTF_ERRIF4_Pos (19U) #define DMA_INTF_ERRIF4_Msk (0x1U << DMA_INTF_ERRIF4_Pos) /*!< 0x00080000 */ #define DMA_INTF_ERRIF4 DMA_INTF_ERRIF4_Msk /*!< Channel 5 Transfer Error flag */ #define DMA_INTF_GIF5_Pos (20U) #define DMA_INTF_GIF5_Msk (0x1U << DMA_INTF_GIF5_Pos) /*!< 0x00100000 */ #define DMA_INTF_GIF5 DMA_INTF_GIF5_Msk /*!< Channel 6 Global interrupt flag */ #define DMA_INTF_FTFIF5_Pos (21U) #define DMA_INTF_FTFIF5_Msk (0x1U << DMA_INTF_FTFIF5_Pos) /*!< 0x00200000 */ #define DMA_INTF_FTFIF5 DMA_INTF_FTFIF5_Msk /*!< Channel 6 Full Transfer finish flag */ #define DMA_INTF_HTFIF5_Pos (22U) #define DMA_INTF_HTFIF5_Msk (0x1U << DMA_INTF_HTFIF5_Pos) /*!< 0x00400000 */ #define DMA_INTF_HTFIF5 DMA_INTF_HTFIF5_Msk /*!< Channel 6 Half Transfer flag */ #define DMA_INTF_ERRIF5_Pos (23U) #define DMA_INTF_ERRIF5_Msk (0x1U << DMA_INTF_ERRIF5_Pos) /*!< 0x00800000 */ #define DMA_INTF_ERRIF5 DMA_INTF_ERRIF5_Msk /*!< Channel 6 Transfer Error flag */ #define DMA_INTF_GIF6_Pos (24U) #define DMA_INTF_GIF6_Msk (0x1U << DMA_INTF_GIF6_Pos) /*!< 0x01000000 */ #define DMA_INTF_GIF6 DMA_INTF_GIF6_Msk /*!< Channel 7 Global interrupt flag */ #define DMA_INTF_FTFIF6_Pos (25U) #define DMA_INTF_FTFIF6_Msk (0x1U << DMA_INTF_FTFIF6_Pos) /*!< 0x02000000 */ #define DMA_INTF_FTFIF6 DMA_INTF_FTFIF6_Msk /*!< Channel 7 Full Transfer finish flag */ #define DMA_INTF_HTFIF6_Pos (26U) #define DMA_INTF_HTFIF6_Msk (0x1U << DMA_INTF_HTFIF6_Pos) /*!< 0x04000000 */ #define DMA_INTF_HTFIF6 DMA_INTF_HTFIF6_Msk /*!< Channel 7 Half Transfer flag */ #define DMA_INTF_ERRIF6_Pos (27U) #define DMA_INTF_ERRIF6_Msk (0x1U << DMA_INTF_ERRIF6_Pos) /*!< 0x08000000 */ #define DMA_INTF_ERRIF6 DMA_INTF_ERRIF6_Msk /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_INTC register *******************/ #define DMA_INTC_GIFC0_Pos (0U) #define DMA_INTC_GIFC0_Msk (0x1U << DMA_INTC_GIFC0_Pos) /*!< 0x00000001 */ #define DMA_INTC_GIFC0 DMA_INTC_GIFC0_Msk /*!< Channel 1 Global interrupt clear */ #define DMA_INTC_FTFIFC0_Pos (1U) #define DMA_INTC_FTFIFC0_Msk (0x1U << DMA_INTC_FTFIFC0_Pos) /*!< 0x00000002 */ #define DMA_INTC_FTFIFC0 DMA_INTC_FTFIFC0_Msk /*!< Channel 1 Transfer Complete clear */ #define DMA_INTC_HTFIFC0_Pos (2U) #define DMA_INTC_HTFIFC0_Msk (0x1U << DMA_INTC_HTFIFC0_Pos) /*!< 0x00000004 */ #define DMA_INTC_HTFIFC0 DMA_INTC_HTFIFC0_Msk /*!< Channel 1 Half Transfer clear */ #define DMA_INTC_ERRIFC0_Pos (3U) #define DMA_INTC_ERRIFC0_Msk (0x1U << DMA_INTC_ERRIFC0_Pos) /*!< 0x00000008 */ #define DMA_INTC_ERRIFC0 DMA_INTC_ERRIFC0_Msk /*!< Channel 1 Transfer Error clear */ #define DMA_INTC_GIFC1_Pos (4U) #define DMA_INTC_GIFC1_Msk (0x1U << DMA_INTC_GIFC1_Pos) /*!< 0x00000010 */ #define DMA_INTC_GIFC1 DMA_INTC_GIFC1_Msk /*!< Channel 2 Global interrupt clear */ #define DMA_INTC_FTFIFC1_Pos (5U) #define DMA_INTC_FTFIFC1_Msk (0x1U << DMA_INTC_FTFIFC1_Pos) /*!< 0x00000020 */ #define DMA_INTC_FTFIFC1 DMA_INTC_FTFIFC1_Msk /*!< Channel 2 Transfer Complete clear */ #define DMA_INTC_HTFIFC1_Pos (6U) #define DMA_INTC_HTFIFC1_Msk (0x1U << DMA_INTC_HTFIFC1_Pos) /*!< 0x00000040 */ #define DMA_INTC_HTFIFC1 DMA_INTC_HTFIFC1_Msk /*!< Channel 2 Half Transfer clear */ #define DMA_INTC_ERRIFC1_Pos (7U) #define DMA_INTC_ERRIFC1_Msk (0x1U << DMA_INTC_ERRIFC1_Pos) /*!< 0x00000080 */ #define DMA_INTC_ERRIFC1 DMA_INTC_ERRIFC1_Msk /*!< Channel 2 Transfer Error clear */ #define DMA_INTC_GIFC2_Pos (8U) #define DMA_INTC_GIFC2_Msk (0x1U << DMA_INTC_GIFC2_Pos) /*!< 0x00000100 */ #define DMA_INTC_GIFC2 DMA_INTC_GIFC2_Msk /*!< Channel 3 Global interrupt clear */ #define DMA_INTC_FTFIFC2_Pos (9U) #define DMA_INTC_FTFIFC2_Msk (0x1U << DMA_INTC_FTFIFC2_Pos) /*!< 0x00000200 */ #define DMA_INTC_FTFIFC2 DMA_INTC_FTFIFC2_Msk /*!< Channel 3 Transfer Complete clear */ #define DMA_INTC_HTFIFC2_Pos (10U) #define DMA_INTC_HTFIFC2_Msk (0x1U << DMA_INTC_HTFIFC2_Pos) /*!< 0x00000400 */ #define DMA_INTC_HTFIFC2 DMA_INTC_HTFIFC2_Msk /*!< Channel 3 Half Transfer clear */ #define DMA_INTC_ERRIFC2_Pos (11U) #define DMA_INTC_ERRIFC2_Msk (0x1U << DMA_INTC_ERRIFC2_Pos) /*!< 0x00000800 */ #define DMA_INTC_ERRIFC2 DMA_INTC_ERRIFC2_Msk /*!< Channel 3 Transfer Error clear */ #define DMA_INTC_GIFC3_Pos (12U) #define DMA_INTC_GIFC3_Msk (0x1U << DMA_INTC_GIFC3_Pos) /*!< 0x00001000 */ #define DMA_INTC_GIFC3 DMA_INTC_GIFC3_Msk /*!< Channel 4 Global interrupt clear */ #define DMA_INTC_FTFIFC3_Pos (13U) #define DMA_INTC_FTFIFC3_Msk (0x1U << DMA_INTC_FTFIFC3_Pos) /*!< 0x00002000 */ #define DMA_INTC_FTFIFC3 DMA_INTC_FTFIFC3_Msk /*!< Channel 4 Transfer Complete clear */ #define DMA_INTC_HTFIFC3_Pos (14U) #define DMA_INTC_HTFIFC3_Msk (0x1U << DMA_INTC_HTFIFC3_Pos) /*!< 0x00004000 */ #define DMA_INTC_HTFIFC3 DMA_INTC_HTFIFC3_Msk /*!< Channel 4 Half Transfer clear */ #define DMA_INTC_ERRIFC3_Pos (15U) #define DMA_INTC_ERRIFC3_Msk (0x1U << DMA_INTC_ERRIFC3_Pos) /*!< 0x00008000 */ #define DMA_INTC_ERRIFC3 DMA_INTC_ERRIFC3_Msk /*!< Channel 4 Transfer Error clear */ #define DMA_INTC_GIFC4_Pos (16U) #define DMA_INTC_GIFC4_Msk (0x1U << DMA_INTC_GIFC4_Pos) /*!< 0x00010000 */ #define DMA_INTC_GIFC4 DMA_INTC_GIFC4_Msk /*!< Channel 5 Global interrupt clear */ #define DMA_INTC_FTFIFC4_Pos (17U) #define DMA_INTC_FTFIFC4_Msk (0x1U << DMA_INTC_FTFIFC4_Pos) /*!< 0x00020000 */ #define DMA_INTC_FTFIFC4 DMA_INTC_FTFIFC4_Msk /*!< Channel 5 Transfer Complete clear */ #define DMA_INTC_HTFIFC4_Pos (18U) #define DMA_INTC_HTFIFC4_Msk (0x1U << DMA_INTC_HTFIFC4_Pos) /*!< 0x00040000 */ #define DMA_INTC_HTFIFC4 DMA_INTC_HTFIFC4_Msk /*!< Channel 5 Half Transfer clear */ #define DMA_INTC_ERRIFC4_Pos (19U) #define DMA_INTC_ERRIFC4_Msk (0x1U << DMA_INTC_ERRIFC4_Pos) /*!< 0x00080000 */ #define DMA_INTC_ERRIFC4 DMA_INTC_ERRIFC4_Msk /*!< Channel 5 Transfer Error clear */ #define DMA_INTC_GIFC5_Pos (20U) #define DMA_INTC_GIFC5_Msk (0x1U << DMA_INTC_GIFC5_Pos) /*!< 0x00100000 */ #define DMA_INTC_GIFC5 DMA_INTC_GIFC5_Msk /*!< Channel 6 Global interrupt clear */ #define DMA_INTC_FTFIFC5_Pos (21U) #define DMA_INTC_FTFIFC5_Msk (0x1U << DMA_INTC_FTFIFC5_Pos) /*!< 0x00200000 */ #define DMA_INTC_FTFIFC5 DMA_INTC_FTFIFC5_Msk /*!< Channel 6 Transfer Complete clear */ #define DMA_INTC_HTFIFC5_Pos (22U) #define DMA_INTC_HTFIFC5_Msk (0x1U << DMA_INTC_HTFIFC5_Pos) /*!< 0x00400000 */ #define DMA_INTC_HTFIFC5 DMA_INTC_HTFIFC5_Msk /*!< Channel 6 Half Transfer clear */ #define DMA_INTC_ERRIFC5_Pos (23U) #define DMA_INTC_ERRIFC5_Msk (0x1U << DMA_INTC_ERRIFC5_Pos) /*!< 0x00800000 */ #define DMA_INTC_ERRIFC5 DMA_INTC_ERRIFC5_Msk /*!< Channel 6 Transfer Error clear */ #define DMA_INTC_GIFC6_Pos (24U) #define DMA_INTC_GIFC6_Msk (0x1U << DMA_INTC_GIFC6_Pos) /*!< 0x01000000 */ #define DMA_INTC_GIFC6 DMA_INTC_GIFC6_Msk /*!< Channel 7 Global interrupt clear */ #define DMA_INTC_FTFIFC6_Pos (25U) #define DMA_INTC_FTFIFC6_Msk (0x1U << DMA_INTC_FTFIFC6_Pos) /*!< 0x02000000 */ #define DMA_INTC_FTFIFC6 DMA_INTC_FTFIFC6_Msk /*!< Channel 7 Transfer Complete clear */ #define DMA_INTC_HTFIFC6_Pos (26U) #define DMA_INTC_HTFIFC6_Msk (0x1U << DMA_INTC_HTFIFC6_Pos) /*!< 0x04000000 */ #define DMA_INTC_HTFIFC6 DMA_INTC_HTFIFC6_Msk /*!< Channel 7 Half Transfer clear */ #define DMA_INTC_ERRIFC6_Pos (27U) #define DMA_INTC_ERRIFC6_Msk (0x1U << DMA_INTC_ERRIFC6_Pos) /*!< 0x08000000 */ #define DMA_INTC_ERRIFC6 DMA_INTC_ERRIFC6_Msk /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CTL register *******************/ #define DMA_CTL_CHEN_Pos (0U) #define DMA_CTL_CHEN_Msk (0x1U << DMA_CTL_CHEN_Pos) /*!< 0x00000001 */ #define DMA_CTL_CHEN DMA_CTL_CHEN_Msk /*!< Channel enable */ #define DMA_CTL_FTFIE_Pos (1U) #define DMA_CTL_FTFIE_Msk (0x1U << DMA_CTL_FTFIE_Pos) /*!< 0x00000002 */ #define DMA_CTL_FTFIE DMA_CTL_FTFIE_Msk /*!< Transfer complete interrupt enable */ #define DMA_CTL_HTFIE_Pos (2U) #define DMA_CTL_HTFIE_Msk (0x1U << DMA_CTL_HTFIE_Pos) /*!< 0x00000004 */ #define DMA_CTL_HTFIE DMA_CTL_HTFIE_Msk /*!< Half Transfer interrupt enable */ #define DMA_CTL_ERRIE_Pos (3U) #define DMA_CTL_ERRIE_Msk (0x1U << DMA_CTL_ERRIE_Pos) /*!< 0x00000008 */ #define DMA_CTL_ERRIE DMA_CTL_ERRIE_Msk /*!< Transfer error interrupt enable */ #define DMA_CTL_DIR_Pos (4U) #define DMA_CTL_DIR_Msk (0x1U << DMA_CTL_DIR_Pos) /*!< 0x00000010 */ #define DMA_CTL_DIR DMA_CTL_DIR_Msk /*!< Data transfer direction */ #define DMA_CTL_CMEN_Pos (5U) #define DMA_CTL_CMEN_Msk (0x1U << DMA_CTL_CMEN_Pos) /*!< 0x00000020 */ #define DMA_CTL_CMEN DMA_CTL_CMEN_Msk /*!< Circular mode */ #define DMA_CTL_PNAGA_Pos (6U) #define DMA_CTL_PNAGA_Msk (0x1U << DMA_CTL_PNAGA_Pos) /*!< 0x00000040 */ #define DMA_CTL_PNAGA DMA_CTL_PNAGA_Msk /*!< Peripheral increment mode */ #define DMA_CTL_MNAGA_Pos (7U) #define DMA_CTL_MNAGA_Msk (0x1U << DMA_CTL_MNAGA_Pos) /*!< 0x00000080 */ #define DMA_CTL_MNAGA DMA_CTL_MNAGA_Msk /*!< Memory increment mode */ #define DMA_CTL_PWIDTH_Pos (8U) #define DMA_CTL_PWIDTH_Msk (0x3U << DMA_CTL_PWIDTH_Pos) /*!< 0x00000300 */ #define DMA_CTL_PWIDTH DMA_CTL_PWIDTH_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ #define DMA_CTL_PWIDTH_0 (0x1U << DMA_CTL_PWIDTH_Pos) /*!< 0x00000100 */ #define DMA_CTL_PWIDTH_1 (0x2U << DMA_CTL_PWIDTH_Pos) /*!< 0x00000200 */ #define DMA_CTL_MWIDTH_Pos (10U) #define DMA_CTL_MWIDTH_Msk (0x3U << DMA_CTL_MWIDTH_Pos) /*!< 0x00000C00 */ #define DMA_CTL_MWIDTH DMA_CTL_MWIDTH_Msk /*!< MSIZE[1:0] bits (Memory size) */ #define DMA_CTL_MWIDTH_0 (0x1U << DMA_CTL_MWIDTH_Pos) /*!< 0x00000400 */ #define DMA_CTL_MWIDTH_1 (0x2U << DMA_CTL_MWIDTH_Pos) /*!< 0x00000800 */ #define DMA_CTL_PRIO_Pos (12U) #define DMA_CTL_PRIO_Msk (0x3U << DMA_CTL_PRIO_Pos) /*!< 0x00003000 */ #define DMA_CTL_PRIO DMA_CTL_PRIO_Msk /*!< PL[1:0] bits(Channel Priority level) */ #define DMA_CTL_PRIO_0 (0x1U << DMA_CTL_PRIO_Pos) /*!< 0x00001000 */ #define DMA_CTL_PRIO_1 (0x2U << DMA_CTL_PRIO_Pos) /*!< 0x00002000 */ #define DMA_CTL_M2M_Pos (14U) #define DMA_CTL_M2M_Msk (0x1U << DMA_CTL_M2M_Pos) /*!< 0x00004000 */ #define DMA_CTL_M2M DMA_CTL_M2M_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNT register ******************/ #define DMA_CNT_CNT_Pos (0U) #define DMA_CNT_CNT_Msk (0xFFFFU << DMA_CNT_CNT_Pos) /*!< 0x0000FFFF */ #define DMA_CNT_CNT DMA_CNT_CNT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_PADDR register *******************/ #define DMA_PADDR_PADDR_Pos (0U) #define DMA_PADDR_PADDR_Msk (0xFFFFFFFFU << DMA_PADDR_PADDR_Pos) /*!< 0xFFFFFFFF */ #define DMA_PADDR_PADDR DMA_PADDR_PADDR_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_MADDR register *******************/ #define DMA_MADDR_MADDR_Pos (0U) #define DMA_MADDR_MADDR_Msk (0xFFFFFFFFU << DMA_MADDR_MADDR_Pos) /*!< 0xFFFFFFFF */ #define DMA_MADDR_MADDR DMA_MADDR_MADDR_Msk /*!< Memory Address */ /******************************************************************************/ /* */ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the GD32VF103 family) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_STAT register ********************/ #define ADC_STAT_WDE_Pos (0U) #define ADC_STAT_WDE_Msk (0x1U << ADC_STAT_WDE_Pos) /*!< 0x00000001 */ #define ADC_STAT_WDE ADC_STAT_WDE_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_STAT_EOC_Pos (1U) #define ADC_STAT_EOC_Msk (0x1U << ADC_STAT_EOC_Pos) /*!< 0x00000002 */ #define ADC_STAT_EOC ADC_STAT_EOC_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_STAT_EOIC_Pos (2U) #define ADC_STAT_EOIC_Msk (0x1U << ADC_STAT_EOIC_Pos) /*!< 0x00000004 */ #define ADC_STAT_EOIC ADC_STAT_EOIC_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_STAT_STIC_Pos (3U) #define ADC_STAT_STIC_Msk (0x1U << ADC_STAT_STIC_Pos) /*!< 0x00000008 */ #define ADC_STAT_STIC ADC_STAT_STIC_Msk /*!< ADC group injected conversion start flag */ #define ADC_STAT_STRC_Pos (4U) #define ADC_STAT_STRC_Msk (0x1U << ADC_STAT_STRC_Pos) /*!< 0x00000010 */ #define ADC_STAT_STRC ADC_STAT_STRC_Msk /*!< ADC group regular conversion start flag */ /******************* Bit definition for ADC_CTL0 register ********************/ #define ADC_CTL0_WDCHSEL_Pos (0U) #define ADC_CTL0_WDCHSEL_Msk (0x1FU << ADC_CTL0_WDCHSEL_Pos) /*!< 0x0000001F */ #define ADC_CTL0_WDCHSEL ADC_CTL0_WDCHSEL_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CTL0_WDCHSEL_0 (0x01U << ADC_CTL0_WDCHSEL_Pos) /*!< 0x00000001 */ #define ADC_CTL0_WDCHSEL_1 (0x02U << ADC_CTL0_WDCHSEL_Pos) /*!< 0x00000002 */ #define ADC_CTL0_WDCHSEL_2 (0x04U << ADC_CTL0_WDCHSEL_Pos) /*!< 0x00000004 */ #define ADC_CTL0_WDCHSEL_3 (0x08U << ADC_CTL0_WDCHSEL_Pos) /*!< 0x00000008 */ #define ADC_CTL0_WDCHSEL_4 (0x10U << ADC_CTL0_WDCHSEL_Pos) /*!< 0x00000010 */ #define ADC_CTL0_EOCIE_Pos (5U) #define ADC_CTL0_EOCIE_Msk (0x1U << ADC_CTL0_EOCIE_Pos) /*!< 0x00000020 */ #define ADC_CTL0_EOCIE ADC_CTL0_EOCIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_CTL0_WDEIE_Pos (6U) #define ADC_CTL0_WDEIE_Msk (0x1U << ADC_CTL0_WDEIE_Pos) /*!< 0x00000040 */ #define ADC_CTL0_WDEIE ADC_CTL0_WDEIE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_CTL0_EOICIE_Pos (7U) #define ADC_CTL0_EOICIE_Msk (0x1U << ADC_CTL0_EOICIE_Pos) /*!< 0x00000080 */ #define ADC_CTL0_EOICIE ADC_CTL0_EOICIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_CTL0_SM_Pos (8U) #define ADC_CTL0_SM_Msk (0x1U << ADC_CTL0_SM_Pos) /*!< 0x00000100 */ #define ADC_CTL0_SM ADC_CTL0_SM_Msk /*!< ADC scan mode */ #define ADC_CTL0_WDSC_Pos (9U) #define ADC_CTL0_WDSC_Msk (0x1U << ADC_CTL0_WDSC_Pos) /*!< 0x00000200 */ #define ADC_CTL0_WDSC ADC_CTL0_WDSC_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CTL0_ICA_Pos (10U) #define ADC_CTL0_ICA_Msk (0x1U << ADC_CTL0_ICA_Pos) /*!< 0x00000400 */ #define ADC_CTL0_ICA ADC_CTL0_ICA_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CTL0_DISRC_Pos (11U) #define ADC_CTL0_DISRC_Msk (0x1U << ADC_CTL0_DISRC_Pos) /*!< 0x00000800 */ #define ADC_CTL0_DISRC ADC_CTL0_DISRC_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CTL0_DISIC_Pos (12U) #define ADC_CTL0_DISIC_Msk (0x1U << ADC_CTL0_DISIC_Pos) /*!< 0x00001000 */ #define ADC_CTL0_DISIC ADC_CTL0_DISIC_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CTL0_DISNUM_Pos (13U) #define ADC_CTL0_DISNUM_Msk (0x7U << ADC_CTL0_DISNUM_Pos) /*!< 0x0000E000 */ #define ADC_CTL0_DISNUM ADC_CTL0_DISNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CTL0_DISNUM_0 (0x1U << ADC_CTL0_DISNUM_Pos) /*!< 0x00002000 */ #define ADC_CTL0_DISNUM_1 (0x2U << ADC_CTL0_DISNUM_Pos) /*!< 0x00004000 */ #define ADC_CTL0_DISNUM_2 (0x4U << ADC_CTL0_DISNUM_Pos) /*!< 0x00008000 */ #define ADC_CTL0_SYNCM_Pos (16U) #define ADC_CTL0_SYNCM_Msk (0xFU << ADC_CTL0_SYNCM_Pos) /*!< 0x000F0000 */ #define ADC_CTL0_SYNCM ADC_CTL0_SYNCM_Msk /*!< ADC multimode mode selection */ #define ADC_CTL0_SYNCM_0 (0x1U << ADC_CTL0_SYNCM_Pos) /*!< 0x00010000 */ #define ADC_CTL0_SYNCM_1 (0x2U << ADC_CTL0_SYNCM_Pos) /*!< 0x00020000 */ #define ADC_CTL0_SYNCM_2 (0x4U << ADC_CTL0_SYNCM_Pos) /*!< 0x00040000 */ #define ADC_CTL0_SYNCM_3 (0x8U << ADC_CTL0_SYNCM_Pos) /*!< 0x00080000 */ #define ADC_CTL0_IWDEN_Pos (22U) #define ADC_CTL0_IWDEN_Msk (0x1U << ADC_CTL0_IWDEN_Pos) /*!< 0x00400000 */ #define ADC_CTL0_IWDEN ADC_CTL0_IWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CTL0_RWDEN_Pos (23U) #define ADC_CTL0_RWDEN_Msk (0x1U << ADC_CTL0_RWDEN_Pos) /*!< 0x00800000 */ #define ADC_CTL0_RWDEN ADC_CTL0_RWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ /******************* Bit definition for ADC_CTL1 register ********************/ #define ADC_CTL1_ADCON_Pos (0U) #define ADC_CTL1_ADCON_Msk (0x1U << ADC_CTL1_ADCON_Pos) /*!< 0x00000001 */ #define ADC_CTL1_ADCON ADC_CTL1_ADCON_Msk /*!< ADC enable */ #define ADC_CTL1_CTN_Pos (1U) #define ADC_CTL1_CTN_Msk (0x1U << ADC_CTL1_CTN_Pos) /*!< 0x00000002 */ #define ADC_CTL1_CTN ADC_CTL1_CTN_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CTL1_CLB_Pos (2U) #define ADC_CTL1_CLB_Msk (0x1U << ADC_CTL1_CLB_Pos) /*!< 0x00000004 */ #define ADC_CTL1_CLB ADC_CTL1_CLB_Msk /*!< ADC calibration start */ #define ADC_CTL1_RSTCLB_Pos (3U) #define ADC_CTL1_RSTCLB_Msk (0x1U << ADC_CTL1_RSTCLB_Pos) /*!< 0x00000008 */ #define ADC_CTL1_RSTCLB ADC_CTL1_RSTCLB_Msk /*!< ADC calibration reset */ #define ADC_CTL1_DMA_Pos (8U) #define ADC_CTL1_DMA_Msk (0x1U << ADC_CTL1_DMA_Pos) /*!< 0x00000100 */ #define ADC_CTL1_DMA ADC_CTL1_DMA_Msk /*!< ADC DMA transfer enable */ #define ADC_CTL1_DAL_Pos (11U) #define ADC_CTL1_DAL_Msk (0x1U << ADC_CTL1_DAL_Pos) /*!< 0x00000800 */ #define ADC_CTL1_DAL ADC_CTL1_DAL_Msk /*!< ADC data alignement */ #define ADC_CTL1_ETSIC_Pos (12U) #define ADC_CTL1_ETSIC_Msk (0x7U << ADC_CTL1_ETSIC_Pos) /*!< 0x00007000 */ #define ADC_CTL1_ETSIC ADC_CTL1_ETSIC_Msk /*!< ADC group injected external trigger source */ #define ADC_CTL1_ETSIC_0 (0x1U << ADC_CTL1_ETSIC_Pos) /*!< 0x00001000 */ #define ADC_CTL1_ETSIC_1 (0x2U << ADC_CTL1_ETSIC_Pos) /*!< 0x00002000 */ #define ADC_CTL1_ETSIC_2 (0x4U << ADC_CTL1_ETSIC_Pos) /*!< 0x00004000 */ #define ADC_CTL1_ETEIC_Pos (15U) #define ADC_CTL1_ETEIC_Msk (0x1U << ADC_CTL1_ETEIC_Pos) /*!< 0x00008000 */ #define ADC_CTL1_ETEIC ADC_CTL1_ETEIC_Msk /*!< ADC group injected external trigger enable */ #define ADC_CTL1_ETSRC_Pos (17U) #define ADC_CTL1_ETSRC_Msk (0x7U << ADC_CTL1_ETSRC_Pos) /*!< 0x000E0000 */ #define ADC_CTL1_ETSRC ADC_CTL1_ETSRC_Msk /*!< ADC group regular external trigger source */ #define ADC_CTL1_ETSRC_0 (0x1U << ADC_CTL1_ETSRC_Pos) /*!< 0x00020000 */ #define ADC_CTL1_ETSRC_1 (0x2U << ADC_CTL1_ETSRC_Pos) /*!< 0x00040000 */ #define ADC_CTL1_ETSRC_2 (0x4U << ADC_CTL1_ETSRC_Pos) /*!< 0x00080000 */ #define ADC_CTL1_ETERC_Pos (20U) #define ADC_CTL1_ETERC_Msk (0x1U << ADC_CTL1_ETERC_Pos) /*!< 0x00100000 */ #define ADC_CTL1_ETERC ADC_CTL1_ETERC_Msk /*!< ADC group regular external trigger enable */ #define ADC_CTL1_SWICST_Pos (21U) #define ADC_CTL1_SWICST_Msk (0x1U << ADC_CTL1_SWICST_Pos) /*!< 0x00200000 */ #define ADC_CTL1_SWICST ADC_CTL1_SWICST_Msk /*!< ADC group injected conversion start */ #define ADC_CTL1_SWRCST_Pos (22U) #define ADC_CTL1_SWRCST_Msk (0x1U << ADC_CTL1_SWRCST_Pos) /*!< 0x00400000 */ #define ADC_CTL1_SWRCST ADC_CTL1_SWRCST_Msk /*!< ADC group regular conversion start */ #define ADC_CTL1_TSVREN_Pos (23U) #define ADC_CTL1_TSVREN_Msk (0x1U << ADC_CTL1_TSVREN_Pos) /*!< 0x00800000 */ #define ADC_CTL1_TSVREN ADC_CTL1_TSVREN_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ /****************** Bit definition for ADC_SAMPT0 register *******************/ #define ADC_SAMPT0_SPT10_Pos (0U) #define ADC_SAMPT0_SPT10_Msk (0x7U << ADC_SAMPT0_SPT10_Pos) /*!< 0x00000007 */ #define ADC_SAMPT0_SPT10 ADC_SAMPT0_SPT10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SAMPT0_SPT10_0 (0x1U << ADC_SAMPT0_SPT10_Pos) /*!< 0x00000001 */ #define ADC_SAMPT0_SPT10_1 (0x2U << ADC_SAMPT0_SPT10_Pos) /*!< 0x00000002 */ #define ADC_SAMPT0_SPT10_2 (0x4U << ADC_SAMPT0_SPT10_Pos) /*!< 0x00000004 */ #define ADC_SAMPT0_SPT11_Pos (3U) #define ADC_SAMPT0_SPT11_Msk (0x7U << ADC_SAMPT0_SPT11_Pos) /*!< 0x00000038 */ #define ADC_SAMPT0_SPT11 ADC_SAMPT0_SPT11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SAMPT0_SPT11_0 (0x1U << ADC_SAMPT0_SPT11_Pos) /*!< 0x00000008 */ #define ADC_SAMPT0_SPT11_1 (0x2U << ADC_SAMPT0_SPT11_Pos) /*!< 0x00000010 */ #define ADC_SAMPT0_SPT11_2 (0x4U << ADC_SAMPT0_SPT11_Pos) /*!< 0x00000020 */ #define ADC_SAMPT0_SPT12_Pos (6U) #define ADC_SAMPT0_SPT12_Msk (0x7U << ADC_SAMPT0_SPT12_Pos) /*!< 0x000001C0 */ #define ADC_SAMPT0_SPT12 ADC_SAMPT0_SPT12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SAMPT0_SPT12_0 (0x1U << ADC_SAMPT0_SPT12_Pos) /*!< 0x00000040 */ #define ADC_SAMPT0_SPT12_1 (0x2U << ADC_SAMPT0_SPT12_Pos) /*!< 0x00000080 */ #define ADC_SAMPT0_SPT12_2 (0x4U << ADC_SAMPT0_SPT12_Pos) /*!< 0x00000100 */ #define ADC_SAMPT0_SPT13_Pos (9U) #define ADC_SAMPT0_SPT13_Msk (0x7U << ADC_SAMPT0_SPT13_Pos) /*!< 0x00000E00 */ #define ADC_SAMPT0_SPT13 ADC_SAMPT0_SPT13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SAMPT0_SPT13_0 (0x1U << ADC_SAMPT0_SPT13_Pos) /*!< 0x00000200 */ #define ADC_SAMPT0_SPT13_1 (0x2U << ADC_SAMPT0_SPT13_Pos) /*!< 0x00000400 */ #define ADC_SAMPT0_SPT13_2 (0x4U << ADC_SAMPT0_SPT13_Pos) /*!< 0x00000800 */ #define ADC_SAMPT0_SPT14_Pos (12U) #define ADC_SAMPT0_SPT14_Msk (0x7U << ADC_SAMPT0_SPT14_Pos) /*!< 0x00007000 */ #define ADC_SAMPT0_SPT14 ADC_SAMPT0_SPT14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SAMPT0_SPT14_0 (0x1U << ADC_SAMPT0_SPT14_Pos) /*!< 0x00001000 */ #define ADC_SAMPT0_SPT14_1 (0x2U << ADC_SAMPT0_SPT14_Pos) /*!< 0x00002000 */ #define ADC_SAMPT0_SPT14_2 (0x4U << ADC_SAMPT0_SPT14_Pos) /*!< 0x00004000 */ #define ADC_SAMPT0_SPT15_Pos (15U) #define ADC_SAMPT0_SPT15_Msk (0x7U << ADC_SAMPT0_SPT15_Pos) /*!< 0x00038000 */ #define ADC_SAMPT0_SPT15 ADC_SAMPT0_SPT15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SAMPT0_SPT15_0 (0x1U << ADC_SAMPT0_SPT15_Pos) /*!< 0x00008000 */ #define ADC_SAMPT0_SPT15_1 (0x2U << ADC_SAMPT0_SPT15_Pos) /*!< 0x00010000 */ #define ADC_SAMPT0_SPT15_2 (0x4U << ADC_SAMPT0_SPT15_Pos) /*!< 0x00020000 */ #define ADC_SAMPT0_SPT16_Pos (18U) #define ADC_SAMPT0_SPT16_Msk (0x7U << ADC_SAMPT0_SPT16_Pos) /*!< 0x001C0000 */ #define ADC_SAMPT0_SPT16 ADC_SAMPT0_SPT16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SAMPT0_SPT16_0 (0x1U << ADC_SAMPT0_SPT16_Pos) /*!< 0x00040000 */ #define ADC_SAMPT0_SPT16_1 (0x2U << ADC_SAMPT0_SPT16_Pos) /*!< 0x00080000 */ #define ADC_SAMPT0_SPT16_2 (0x4U << ADC_SAMPT0_SPT16_Pos) /*!< 0x00100000 */ #define ADC_SAMPT0_SPT17_Pos (21U) #define ADC_SAMPT0_SPT17_Msk (0x7U << ADC_SAMPT0_SPT17_Pos) /*!< 0x00E00000 */ #define ADC_SAMPT0_SPT17 ADC_SAMPT0_SPT17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SAMPT0_SPT17_0 (0x1U << ADC_SAMPT0_SPT17_Pos) /*!< 0x00200000 */ #define ADC_SAMPT0_SPT17_1 (0x2U << ADC_SAMPT0_SPT17_Pos) /*!< 0x00400000 */ #define ADC_SAMPT0_SPT17_2 (0x4U << ADC_SAMPT0_SPT17_Pos) /*!< 0x00800000 */ /****************** Bit definition for ADC_SAMPT1 register *******************/ #define ADC_SAMPT1_SPT0_Pos (0U) #define ADC_SAMPT1_SPT0_Msk (0x7U << ADC_SAMPT1_SPT0_Pos) /*!< 0x00000007 */ #define ADC_SAMPT1_SPT0 ADC_SAMPT1_SPT0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SAMPT1_SPT0_0 (0x1U << ADC_SAMPT1_SPT0_Pos) /*!< 0x00000001 */ #define ADC_SAMPT1_SPT0_1 (0x2U << ADC_SAMPT1_SPT0_Pos) /*!< 0x00000002 */ #define ADC_SAMPT1_SPT0_2 (0x4U << ADC_SAMPT1_SPT0_Pos) /*!< 0x00000004 */ #define ADC_SAMPT1_SPT1_Pos (3U) #define ADC_SAMPT1_SPT1_Msk (0x7U << ADC_SAMPT1_SPT1_Pos) /*!< 0x00000038 */ #define ADC_SAMPT1_SPT1 ADC_SAMPT1_SPT1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SAMPT1_SPT1_0 (0x1U << ADC_SAMPT1_SPT1_Pos) /*!< 0x00000008 */ #define ADC_SAMPT1_SPT1_1 (0x2U << ADC_SAMPT1_SPT1_Pos) /*!< 0x00000010 */ #define ADC_SAMPT1_SPT1_2 (0x4U << ADC_SAMPT1_SPT1_Pos) /*!< 0x00000020 */ #define ADC_SAMPT1_SPT2_Pos (6U) #define ADC_SAMPT1_SPT2_Msk (0x7U << ADC_SAMPT1_SPT2_Pos) /*!< 0x000001C0 */ #define ADC_SAMPT1_SPT2 ADC_SAMPT1_SPT2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SAMPT1_SPT2_0 (0x1U << ADC_SAMPT1_SPT2_Pos) /*!< 0x00000040 */ #define ADC_SAMPT1_SPT2_1 (0x2U << ADC_SAMPT1_SPT2_Pos) /*!< 0x00000080 */ #define ADC_SAMPT1_SPT2_2 (0x4U << ADC_SAMPT1_SPT2_Pos) /*!< 0x00000100 */ #define ADC_SAMPT1_SPT3_Pos (9U) #define ADC_SAMPT1_SPT3_Msk (0x7U << ADC_SAMPT1_SPT3_Pos) /*!< 0x00000E00 */ #define ADC_SAMPT1_SPT3 ADC_SAMPT1_SPT3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SAMPT1_SPT3_0 (0x1U << ADC_SAMPT1_SPT3_Pos) /*!< 0x00000200 */ #define ADC_SAMPT1_SPT3_1 (0x2U << ADC_SAMPT1_SPT3_Pos) /*!< 0x00000400 */ #define ADC_SAMPT1_SPT3_2 (0x4U << ADC_SAMPT1_SPT3_Pos) /*!< 0x00000800 */ #define ADC_SAMPT1_SPT4_Pos (12U) #define ADC_SAMPT1_SPT4_Msk (0x7U << ADC_SAMPT1_SPT4_Pos) /*!< 0x00007000 */ #define ADC_SAMPT1_SPT4 ADC_SAMPT1_SPT4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SAMPT1_SPT4_0 (0x1U << ADC_SAMPT1_SPT4_Pos) /*!< 0x00001000 */ #define ADC_SAMPT1_SPT4_1 (0x2U << ADC_SAMPT1_SPT4_Pos) /*!< 0x00002000 */ #define ADC_SAMPT1_SPT4_2 (0x4U << ADC_SAMPT1_SPT4_Pos) /*!< 0x00004000 */ #define ADC_SAMPT1_SPT5_Pos (15U) #define ADC_SAMPT1_SPT5_Msk (0x7U << ADC_SAMPT1_SPT5_Pos) /*!< 0x00038000 */ #define ADC_SAMPT1_SPT5 ADC_SAMPT1_SPT5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SAMPT1_SPT5_0 (0x1U << ADC_SAMPT1_SPT5_Pos) /*!< 0x00008000 */ #define ADC_SAMPT1_SPT5_1 (0x2U << ADC_SAMPT1_SPT5_Pos) /*!< 0x00010000 */ #define ADC_SAMPT1_SPT5_2 (0x4U << ADC_SAMPT1_SPT5_Pos) /*!< 0x00020000 */ #define ADC_SAMPT1_SPT6_Pos (18U) #define ADC_SAMPT1_SPT6_Msk (0x7U << ADC_SAMPT1_SPT6_Pos) /*!< 0x001C0000 */ #define ADC_SAMPT1_SPT6 ADC_SAMPT1_SPT6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SAMPT1_SPT6_0 (0x1U << ADC_SAMPT1_SPT6_Pos) /*!< 0x00040000 */ #define ADC_SAMPT1_SPT6_1 (0x2U << ADC_SAMPT1_SPT6_Pos) /*!< 0x00080000 */ #define ADC_SAMPT1_SPT6_2 (0x4U << ADC_SAMPT1_SPT6_Pos) /*!< 0x00100000 */ #define ADC_SAMPT1_SPT7_Pos (21U) #define ADC_SAMPT1_SPT7_Msk (0x7U << ADC_SAMPT1_SPT7_Pos) /*!< 0x00E00000 */ #define ADC_SAMPT1_SPT7 ADC_SAMPT1_SPT7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SAMPT1_SPT7_0 (0x1U << ADC_SAMPT1_SPT7_Pos) /*!< 0x00200000 */ #define ADC_SAMPT1_SPT7_1 (0x2U << ADC_SAMPT1_SPT7_Pos) /*!< 0x00400000 */ #define ADC_SAMPT1_SPT7_2 (0x4U << ADC_SAMPT1_SPT7_Pos) /*!< 0x00800000 */ #define ADC_SAMPT1_SPT8_Pos (24U) #define ADC_SAMPT1_SPT8_Msk (0x7U << ADC_SAMPT1_SPT8_Pos) /*!< 0x07000000 */ #define ADC_SAMPT1_SPT8 ADC_SAMPT1_SPT8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SAMPT1_SPT8_0 (0x1U << ADC_SAMPT1_SPT8_Pos) /*!< 0x01000000 */ #define ADC_SAMPT1_SPT8_1 (0x2U << ADC_SAMPT1_SPT8_Pos) /*!< 0x02000000 */ #define ADC_SAMPT1_SPT8_2 (0x4U << ADC_SAMPT1_SPT8_Pos) /*!< 0x04000000 */ #define ADC_SAMPT1_SPT9_Pos (27U) #define ADC_SAMPT1_SPT9_Msk (0x7U << ADC_SAMPT1_SPT9_Pos) /*!< 0x38000000 */ #define ADC_SAMPT1_SPT9 ADC_SAMPT1_SPT9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SAMPT1_SPT9_0 (0x1U << ADC_SAMPT1_SPT9_Pos) /*!< 0x08000000 */ #define ADC_SAMPT1_SPT9_1 (0x2U << ADC_SAMPT1_SPT9_Pos) /*!< 0x10000000 */ #define ADC_SAMPT1_SPT9_2 (0x4U << ADC_SAMPT1_SPT9_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_IOFF0 register *******************/ #define ADC_IOFF0_IOFF_Pos (0U) #define ADC_IOFF0_IOFF_Msk (0xFFFU << ADC_IOFF0_IOFF_Pos) /*!< 0x00000FFF */ #define ADC_IOFF0_IOFF ADC_IOFF0_IOFF_Msk /*!< ADC group injected sequencer rank 1 offset value */ /****************** Bit definition for ADC_IOFF1 register *******************/ #define ADC_IOFF1_IOFF_Pos (0U) #define ADC_IOFF1_IOFF_Msk (0xFFFU << ADC_IOFF1_IOFF_Pos) /*!< 0x00000FFF */ #define ADC_IOFF1_IOFF ADC_IOFF1_IOFF_Msk /*!< ADC group injected sequencer rank 2 offset value */ /****************** Bit definition for ADC_IOFF2 register *******************/ #define ADC_IOFF2_IOFF_Pos (0U) #define ADC_IOFF2_IOFF_Msk (0xFFFU << ADC_IOFF2_IOFF_Pos) /*!< 0x00000FFF */ #define ADC_IOFF2_IOFF ADC_IOFF2_IOFF_Msk /*!< ADC group injected sequencer rank 3 offset value */ /****************** Bit definition for ADC_IOFF3 register *******************/ #define ADC_IOFF3_IOFF_Pos (0U) #define ADC_IOFF3_IOFF_Msk (0xFFFU << ADC_IOFF3_IOFF_Pos) /*!< 0x00000FFF */ #define ADC_IOFF3_IOFF ADC_IOFF3_IOFF_Msk /*!< ADC group injected sequencer rank 4 offset value */ /******************* Bit definition for ADC_WDHT register ********************/ #define ADC_WDHT_WDHT_Pos (0U) #define ADC_WDHT_WDHT_Msk (0xFFFU << ADC_WDHT_WDHT_Pos) /*!< 0x00000FFF */ #define ADC_WDHT_WDHT ADC_WDHT_WDHT_Msk /*!< ADC analog watchdog 1 threshold high */ /******************* Bit definition for ADC_WDLT register ********************/ #define ADC_WDLT_WDLT_Pos (0U) #define ADC_WDLT_WDLT_Msk (0xFFFU << ADC_WDLT_WDLT_Pos) /*!< 0x00000FFF */ #define ADC_WDLT_WDLT ADC_WDLT_WDLT_Msk /*!< ADC analog watchdog 1 threshold low */ /******************* Bit definition for ADC_RSQ0 register *******************/ #define ADC_RSQ0_RSQ13_Pos (0U) #define ADC_RSQ0_RSQ13_Msk (0x1FU << ADC_RSQ0_RSQ13_Pos) /*!< 0x0000001F */ #define ADC_RSQ0_RSQ13 ADC_RSQ0_RSQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_RSQ0_RSQ13_0 (0x01U << ADC_RSQ0_RSQ13_Pos) /*!< 0x00000001 */ #define ADC_RSQ0_RSQ13_1 (0x02U << ADC_RSQ0_RSQ13_Pos) /*!< 0x00000002 */ #define ADC_RSQ0_RSQ13_2 (0x04U << ADC_RSQ0_RSQ13_Pos) /*!< 0x00000004 */ #define ADC_RSQ0_RSQ13_3 (0x08U << ADC_RSQ0_RSQ13_Pos) /*!< 0x00000008 */ #define ADC_RSQ0_RSQ13_4 (0x10U << ADC_RSQ0_RSQ13_Pos) /*!< 0x00000010 */ #define ADC_RSQ0_RSQ14_Pos (5U) #define ADC_RSQ0_RSQ14_Msk (0x1FU << ADC_RSQ0_RSQ14_Pos) /*!< 0x000003E0 */ #define ADC_RSQ0_RSQ14 ADC_RSQ0_RSQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_RSQ0_RSQ14_0 (0x01U << ADC_RSQ0_RSQ14_Pos) /*!< 0x00000020 */ #define ADC_RSQ0_RSQ14_1 (0x02U << ADC_RSQ0_RSQ14_Pos) /*!< 0x00000040 */ #define ADC_RSQ0_RSQ14_2 (0x04U << ADC_RSQ0_RSQ14_Pos) /*!< 0x00000080 */ #define ADC_RSQ0_RSQ14_3 (0x08U << ADC_RSQ0_RSQ14_Pos) /*!< 0x00000100 */ #define ADC_RSQ0_RSQ14_4 (0x10U << ADC_RSQ0_RSQ14_Pos) /*!< 0x00000200 */ #define ADC_RSQ0_RSQ15_Pos (10U) #define ADC_RSQ0_RSQ15_Msk (0x1FU << ADC_RSQ0_RSQ15_Pos) /*!< 0x00007C00 */ #define ADC_RSQ0_RSQ15 ADC_RSQ0_RSQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_RSQ0_RSQ15_0 (0x01U << ADC_RSQ0_RSQ15_Pos) /*!< 0x00000400 */ #define ADC_RSQ0_RSQ15_1 (0x02U << ADC_RSQ0_RSQ15_Pos) /*!< 0x00000800 */ #define ADC_RSQ0_RSQ15_2 (0x04U << ADC_RSQ0_RSQ15_Pos) /*!< 0x00001000 */ #define ADC_RSQ0_RSQ15_3 (0x08U << ADC_RSQ0_RSQ15_Pos) /*!< 0x00002000 */ #define ADC_RSQ0_RSQ15_4 (0x10U << ADC_RSQ0_RSQ15_Pos) /*!< 0x00004000 */ #define ADC_RSQ0_RSQ16_Pos (15U) #define ADC_RSQ0_RSQ16_Msk (0x1FU << ADC_RSQ0_RSQ16_Pos) /*!< 0x000F8000 */ #define ADC_RSQ0_RSQ16 ADC_RSQ0_RSQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_RSQ0_RSQ16_0 (0x01U << ADC_RSQ0_RSQ16_Pos) /*!< 0x00008000 */ #define ADC_RSQ0_RSQ16_1 (0x02U << ADC_RSQ0_RSQ16_Pos) /*!< 0x00010000 */ #define ADC_RSQ0_RSQ16_2 (0x04U << ADC_RSQ0_RSQ16_Pos) /*!< 0x00020000 */ #define ADC_RSQ0_RSQ16_3 (0x08U << ADC_RSQ0_RSQ16_Pos) /*!< 0x00040000 */ #define ADC_RSQ0_RSQ16_4 (0x10U << ADC_RSQ0_RSQ16_Pos) /*!< 0x00080000 */ #define ADC_RSQ0_RL_Pos (20U) #define ADC_RSQ0_RL_Msk (0xFU << ADC_RSQ0_RL_Pos) /*!< 0x00F00000 */ #define ADC_RSQ0_RL ADC_RSQ0_RL_Msk /*!< ADC group regular sequencer scan length */ #define ADC_RSQ0_RL_0 (0x1U << ADC_RSQ0_RL_Pos) /*!< 0x00100000 */ #define ADC_RSQ0_RL_1 (0x2U << ADC_RSQ0_RL_Pos) /*!< 0x00200000 */ #define ADC_RSQ0_RL_2 (0x4U << ADC_RSQ0_RL_Pos) /*!< 0x00400000 */ #define ADC_RSQ0_RL_3 (0x8U << ADC_RSQ0_RL_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_RSQ1 register *******************/ #define ADC_RSQ1_RSQ7_Pos (0U) #define ADC_RSQ1_RSQ7_Msk (0x1FU << ADC_RSQ1_RSQ7_Pos) /*!< 0x0000001F */ #define ADC_RSQ1_RSQ7 ADC_RSQ1_RSQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_RSQ1_RSQ7_0 (0x01U << ADC_RSQ1_RSQ7_Pos) /*!< 0x00000001 */ #define ADC_RSQ1_RSQ7_1 (0x02U << ADC_RSQ1_RSQ7_Pos) /*!< 0x00000002 */ #define ADC_RSQ1_RSQ7_2 (0x04U << ADC_RSQ1_RSQ7_Pos) /*!< 0x00000004 */ #define ADC_RSQ1_RSQ7_3 (0x08U << ADC_RSQ1_RSQ7_Pos) /*!< 0x00000008 */ #define ADC_RSQ1_RSQ7_4 (0x10U << ADC_RSQ1_RSQ7_Pos) /*!< 0x00000010 */ #define ADC_RSQ1_RSQ8_Pos (5U) #define ADC_RSQ1_RSQ8_Msk (0x1FU << ADC_RSQ1_RSQ8_Pos) /*!< 0x000003E0 */ #define ADC_RSQ1_RSQ8 ADC_RSQ1_RSQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_RSQ1_RSQ8_0 (0x01U << ADC_RSQ1_RSQ8_Pos) /*!< 0x00000020 */ #define ADC_RSQ1_RSQ8_1 (0x02U << ADC_RSQ1_RSQ8_Pos) /*!< 0x00000040 */ #define ADC_RSQ1_RSQ8_2 (0x04U << ADC_RSQ1_RSQ8_Pos) /*!< 0x00000080 */ #define ADC_RSQ1_RSQ8_3 (0x08U << ADC_RSQ1_RSQ8_Pos) /*!< 0x00000100 */ #define ADC_RSQ1_RSQ8_4 (0x10U << ADC_RSQ1_RSQ8_Pos) /*!< 0x00000200 */ #define ADC_RSQ1_RSQ9_Pos (10U) #define ADC_RSQ1_RSQ9_Msk (0x1FU << ADC_RSQ1_RSQ9_Pos) /*!< 0x00007C00 */ #define ADC_RSQ1_RSQ9 ADC_RSQ1_RSQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_RSQ1_RSQ9_0 (0x01U << ADC_RSQ1_RSQ9_Pos) /*!< 0x00000400 */ #define ADC_RSQ1_RSQ9_1 (0x02U << ADC_RSQ1_RSQ9_Pos) /*!< 0x00000800 */ #define ADC_RSQ1_RSQ9_2 (0x04U << ADC_RSQ1_RSQ9_Pos) /*!< 0x00001000 */ #define ADC_RSQ1_RSQ9_3 (0x08U << ADC_RSQ1_RSQ9_Pos) /*!< 0x00002000 */ #define ADC_RSQ1_RSQ9_4 (0x10U << ADC_RSQ1_RSQ9_Pos) /*!< 0x00004000 */ #define ADC_RSQ1_RSQ10_Pos (15U) #define ADC_RSQ1_RSQ10_Msk (0x1FU << ADC_RSQ1_RSQ10_Pos) /*!< 0x000F8000 */ #define ADC_RSQ1_RSQ10 ADC_RSQ1_RSQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_RSQ1_RSQ10_0 (0x01U << ADC_RSQ1_RSQ10_Pos) /*!< 0x00008000 */ #define ADC_RSQ1_RSQ10_1 (0x02U << ADC_RSQ1_RSQ10_Pos) /*!< 0x00010000 */ #define ADC_RSQ1_RSQ10_2 (0x04U << ADC_RSQ1_RSQ10_Pos) /*!< 0x00020000 */ #define ADC_RSQ1_RSQ10_3 (0x08U << ADC_RSQ1_RSQ10_Pos) /*!< 0x00040000 */ #define ADC_RSQ1_RSQ10_4 (0x10U << ADC_RSQ1_RSQ10_Pos) /*!< 0x00080000 */ #define ADC_RSQ1_RSQ11_Pos (20U) #define ADC_RSQ1_RSQ11_Msk (0x1FU << ADC_RSQ1_RSQ11_Pos) /*!< 0x01F00000 */ #define ADC_RSQ1_RSQ11 ADC_RSQ1_RSQ11_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_RSQ1_RSQ11_0 (0x01U << ADC_RSQ1_RSQ11_Pos) /*!< 0x00100000 */ #define ADC_RSQ1_RSQ11_1 (0x02U << ADC_RSQ1_RSQ11_Pos) /*!< 0x00200000 */ #define ADC_RSQ1_RSQ11_2 (0x04U << ADC_RSQ1_RSQ11_Pos) /*!< 0x00400000 */ #define ADC_RSQ1_RSQ11_3 (0x08U << ADC_RSQ1_RSQ11_Pos) /*!< 0x00800000 */ #define ADC_RSQ1_RSQ11_4 (0x10U << ADC_RSQ1_RSQ11_Pos) /*!< 0x01000000 */ #define ADC_RSQ1_RSQ12_Pos (25U) #define ADC_RSQ1_RSQ12_Msk (0x1FU << ADC_RSQ1_RSQ12_Pos) /*!< 0x3E000000 */ #define ADC_RSQ1_RSQ12 ADC_RSQ1_RSQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_RSQ1_RSQ12_0 (0x01U << ADC_RSQ1_RSQ12_Pos) /*!< 0x02000000 */ #define ADC_RSQ1_RSQ12_1 (0x02U << ADC_RSQ1_RSQ12_Pos) /*!< 0x04000000 */ #define ADC_RSQ1_RSQ12_2 (0x04U << ADC_RSQ1_RSQ12_Pos) /*!< 0x08000000 */ #define ADC_RSQ1_RSQ12_3 (0x08U << ADC_RSQ1_RSQ12_Pos) /*!< 0x10000000 */ #define ADC_RSQ1_RSQ12_4 (0x10U << ADC_RSQ1_RSQ12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_RSQ2 register *******************/ #define ADC_RSQ2_RSQ1_Pos (0U) #define ADC_RSQ2_RSQ1_Msk (0x1FU << ADC_RSQ2_RSQ1_Pos) /*!< 0x0000001F */ #define ADC_RSQ2_RSQ1 ADC_RSQ2_RSQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_RSQ2_RSQ1_0 (0x01U << ADC_RSQ2_RSQ1_Pos) /*!< 0x00000001 */ #define ADC_RSQ2_RSQ1_1 (0x02U << ADC_RSQ2_RSQ1_Pos) /*!< 0x00000002 */ #define ADC_RSQ2_RSQ1_2 (0x04U << ADC_RSQ2_RSQ1_Pos) /*!< 0x00000004 */ #define ADC_RSQ2_RSQ1_3 (0x08U << ADC_RSQ2_RSQ1_Pos) /*!< 0x00000008 */ #define ADC_RSQ2_RSQ1_4 (0x10U << ADC_RSQ2_RSQ1_Pos) /*!< 0x00000010 */ #define ADC_RSQ2_RSQ2_Pos (5U) #define ADC_RSQ2_RSQ2_Msk (0x1FU << ADC_RSQ2_RSQ2_Pos) /*!< 0x000003E0 */ #define ADC_RSQ2_RSQ2 ADC_RSQ2_RSQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_RSQ2_RSQ2_0 (0x01U << ADC_RSQ2_RSQ2_Pos) /*!< 0x00000020 */ #define ADC_RSQ2_RSQ2_1 (0x02U << ADC_RSQ2_RSQ2_Pos) /*!< 0x00000040 */ #define ADC_RSQ2_RSQ2_2 (0x04U << ADC_RSQ2_RSQ2_Pos) /*!< 0x00000080 */ #define ADC_RSQ2_RSQ2_3 (0x08U << ADC_RSQ2_RSQ2_Pos) /*!< 0x00000100 */ #define ADC_RSQ2_RSQ2_4 (0x10U << ADC_RSQ2_RSQ2_Pos) /*!< 0x00000200 */ #define ADC_RSQ2_RSQ3_Pos (10U) #define ADC_RSQ2_RSQ3_Msk (0x1FU << ADC_RSQ2_RSQ3_Pos) /*!< 0x00007C00 */ #define ADC_RSQ2_RSQ3 ADC_RSQ2_RSQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_RSQ2_RSQ3_0 (0x01U << ADC_RSQ2_RSQ3_Pos) /*!< 0x00000400 */ #define ADC_RSQ2_RSQ3_1 (0x02U << ADC_RSQ2_RSQ3_Pos) /*!< 0x00000800 */ #define ADC_RSQ2_RSQ3_2 (0x04U << ADC_RSQ2_RSQ3_Pos) /*!< 0x00001000 */ #define ADC_RSQ2_RSQ3_3 (0x08U << ADC_RSQ2_RSQ3_Pos) /*!< 0x00002000 */ #define ADC_RSQ2_RSQ3_4 (0x10U << ADC_RSQ2_RSQ3_Pos) /*!< 0x00004000 */ #define ADC_RSQ2_RSQ4_Pos (15U) #define ADC_RSQ2_RSQ4_Msk (0x1FU << ADC_RSQ2_RSQ4_Pos) /*!< 0x000F8000 */ #define ADC_RSQ2_RSQ4 ADC_RSQ2_RSQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_RSQ2_RSQ4_0 (0x01U << ADC_RSQ2_RSQ4_Pos) /*!< 0x00008000 */ #define ADC_RSQ2_RSQ4_1 (0x02U << ADC_RSQ2_RSQ4_Pos) /*!< 0x00010000 */ #define ADC_RSQ2_RSQ4_2 (0x04U << ADC_RSQ2_RSQ4_Pos) /*!< 0x00020000 */ #define ADC_RSQ2_RSQ4_3 (0x08U << ADC_RSQ2_RSQ4_Pos) /*!< 0x00040000 */ #define ADC_RSQ2_RSQ4_4 (0x10U << ADC_RSQ2_RSQ4_Pos) /*!< 0x00080000 */ #define ADC_RSQ2_RSQ5_Pos (20U) #define ADC_RSQ2_RSQ5_Msk (0x1FU << ADC_RSQ2_RSQ5_Pos) /*!< 0x01F00000 */ #define ADC_RSQ2_RSQ5 ADC_RSQ2_RSQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_RSQ2_RSQ5_0 (0x01U << ADC_RSQ2_RSQ5_Pos) /*!< 0x00100000 */ #define ADC_RSQ2_RSQ5_1 (0x02U << ADC_RSQ2_RSQ5_Pos) /*!< 0x00200000 */ #define ADC_RSQ2_RSQ5_2 (0x04U << ADC_RSQ2_RSQ5_Pos) /*!< 0x00400000 */ #define ADC_RSQ2_RSQ5_3 (0x08U << ADC_RSQ2_RSQ5_Pos) /*!< 0x00800000 */ #define ADC_RSQ2_RSQ5_4 (0x10U << ADC_RSQ2_RSQ5_Pos) /*!< 0x01000000 */ #define ADC_RSQ2_RSQ6_Pos (25U) #define ADC_RSQ2_RSQ6_Msk (0x1FU << ADC_RSQ2_RSQ6_Pos) /*!< 0x3E000000 */ #define ADC_RSQ2_RSQ6 ADC_RSQ2_RSQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_RSQ2_RSQ6_0 (0x01U << ADC_RSQ2_RSQ6_Pos) /*!< 0x02000000 */ #define ADC_RSQ2_RSQ6_1 (0x02U << ADC_RSQ2_RSQ6_Pos) /*!< 0x04000000 */ #define ADC_RSQ2_RSQ6_2 (0x04U << ADC_RSQ2_RSQ6_Pos) /*!< 0x08000000 */ #define ADC_RSQ2_RSQ6_3 (0x08U << ADC_RSQ2_RSQ6_Pos) /*!< 0x10000000 */ #define ADC_RSQ2_RSQ6_4 (0x10U << ADC_RSQ2_RSQ6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_ISQ register *******************/ #define ADC_ISQ_ISQ1_Pos (0U) #define ADC_ISQ_ISQ1_Msk (0x1FU << ADC_ISQ_ISQ1_Pos) /*!< 0x0000001F */ #define ADC_ISQ_ISQ1 ADC_ISQ_ISQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_ISQ_ISQ1_0 (0x01U << ADC_ISQ_ISQ1_Pos) /*!< 0x00000001 */ #define ADC_ISQ_ISQ1_1 (0x02U << ADC_ISQ_ISQ1_Pos) /*!< 0x00000002 */ #define ADC_ISQ_ISQ1_2 (0x04U << ADC_ISQ_ISQ1_Pos) /*!< 0x00000004 */ #define ADC_ISQ_ISQ1_3 (0x08U << ADC_ISQ_ISQ1_Pos) /*!< 0x00000008 */ #define ADC_ISQ_ISQ1_4 (0x10U << ADC_ISQ_ISQ1_Pos) /*!< 0x00000010 */ #define ADC_ISQ_ISQ2_Pos (5U) #define ADC_ISQ_ISQ2_Msk (0x1FU << ADC_ISQ_ISQ2_Pos) /*!< 0x000003E0 */ #define ADC_ISQ_ISQ2 ADC_ISQ_ISQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_ISQ_ISQ2_0 (0x01U << ADC_ISQ_ISQ2_Pos) /*!< 0x00000020 */ #define ADC_ISQ_ISQ2_1 (0x02U << ADC_ISQ_ISQ2_Pos) /*!< 0x00000040 */ #define ADC_ISQ_ISQ2_2 (0x04U << ADC_ISQ_ISQ2_Pos) /*!< 0x00000080 */ #define ADC_ISQ_ISQ2_3 (0x08U << ADC_ISQ_ISQ2_Pos) /*!< 0x00000100 */ #define ADC_ISQ_ISQ2_4 (0x10U << ADC_ISQ_ISQ2_Pos) /*!< 0x00000200 */ #define ADC_ISQ_ISQ3_Pos (10U) #define ADC_ISQ_ISQ3_Msk (0x1FU << ADC_ISQ_ISQ3_Pos) /*!< 0x00007C00 */ #define ADC_ISQ_ISQ3 ADC_ISQ_ISQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_ISQ_ISQ3_0 (0x01U << ADC_ISQ_ISQ3_Pos) /*!< 0x00000400 */ #define ADC_ISQ_ISQ3_1 (0x02U << ADC_ISQ_ISQ3_Pos) /*!< 0x00000800 */ #define ADC_ISQ_ISQ3_2 (0x04U << ADC_ISQ_ISQ3_Pos) /*!< 0x00001000 */ #define ADC_ISQ_ISQ3_3 (0x08U << ADC_ISQ_ISQ3_Pos) /*!< 0x00002000 */ #define ADC_ISQ_ISQ3_4 (0x10U << ADC_ISQ_ISQ3_Pos) /*!< 0x00004000 */ #define ADC_ISQ_ISQ4_Pos (15U) #define ADC_ISQ_ISQ4_Msk (0x1FU << ADC_ISQ_ISQ4_Pos) /*!< 0x000F8000 */ #define ADC_ISQ_ISQ4 ADC_ISQ_ISQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_ISQ_ISQ4_0 (0x01U << ADC_ISQ_ISQ4_Pos) /*!< 0x00008000 */ #define ADC_ISQ_ISQ4_1 (0x02U << ADC_ISQ_ISQ4_Pos) /*!< 0x00010000 */ #define ADC_ISQ_ISQ4_2 (0x04U << ADC_ISQ_ISQ4_Pos) /*!< 0x00020000 */ #define ADC_ISQ_ISQ4_3 (0x08U << ADC_ISQ_ISQ4_Pos) /*!< 0x00040000 */ #define ADC_ISQ_ISQ4_4 (0x10U << ADC_ISQ_ISQ4_Pos) /*!< 0x00080000 */ #define ADC_ISQ_IL_Pos (20U) #define ADC_ISQ_IL_Msk (0x3U << ADC_ISQ_IL_Pos) /*!< 0x00300000 */ #define ADC_ISQ_IL ADC_ISQ_IL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_ISQ_IL_0 (0x1U << ADC_ISQ_IL_Pos) /*!< 0x00100000 */ #define ADC_ISQ_IL_1 (0x2U << ADC_ISQ_IL_Pos) /*!< 0x00200000 */ /******************* Bit definition for ADC_IDATA0 register *******************/ #define ADC_IDATA0_IDATA_Pos (0U) #define ADC_IDATA0_IDATA_Msk (0xFFFFU << ADC_IDATA0_IDATA_Pos) /*!< 0x0000FFFF */ #define ADC_IDATA0_IDATA ADC_IDATA0_IDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************* Bit definition for ADC_IDATA1 register *******************/ #define ADC_IDATA1_IDATA_Pos (0U) #define ADC_IDATA1_IDATA_Msk (0xFFFFU << ADC_IDATA1_IDATA_Pos) /*!< 0x0000FFFF */ #define ADC_IDATA1_IDATA ADC_IDATA1_IDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************* Bit definition for ADC_IDATA2 register *******************/ #define ADC_IDATA2_IDATA_Pos (0U) #define ADC_IDATA2_IDATA_Msk (0xFFFFU << ADC_IDATA2_IDATA_Pos) /*!< 0x0000FFFF */ #define ADC_IDATA2_IDATA ADC_IDATA2_IDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************* Bit definition for ADC_IDATA3 register *******************/ #define ADC_IDATA3_IDATA_Pos (0U) #define ADC_IDATA3_IDATA_Msk (0xFFFFU << ADC_IDATA3_IDATA_Pos) /*!< 0x0000FFFF */ #define ADC_IDATA3_IDATA ADC_IDATA3_IDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_RDATA register ********************/ #define ADC_RDATA_RDATA_Pos (0U) #define ADC_RDATA_RDATA_Msk (0xFFFFU << ADC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_RDATA_RDATA ADC_RDATA_RDATA_Msk /*!< ADC group regular conversion data */ #define ADC_RDATA_ADC1RDTR_Pos (16U) #define ADC_RDATA_ADC1RDTR_Msk (0xFFFFU << ADC_RDATA_ADC1RDTR_Pos) /*!< 0xFFFF0000 */ #define ADC_RDATA_ADC1RDTR ADC_RDATA_ADC1RDTR_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ /******************************************************************************/ /* */ /* Digital to Analog Converter */ /* */ /******************************************************************************/ /******************** Bit definition for DAC_CTL register ********************/ #define DAC_CTL_DEN0_Pos (0U) #define DAC_CTL_DEN0_Msk (0x1U << DAC_CTL_DEN0_Pos) /*!< 0x00000001 */ #define DAC_CTL_DEN0 DAC_CTL_DEN0_Msk /*!< DAC channel1 enable */ #define DAC_CTL_DBOFF0_Pos (1U) #define DAC_CTL_DBOFF0_Msk (0x1U << DAC_CTL_DBOFF0_Pos) /*!< 0x00000002 */ #define DAC_CTL_DBOFF0 DAC_CTL_DBOFF0_Msk /*!< DAC channel1 output buffer disable */ #define DAC_CTL_DTEN0_Pos (2U) #define DAC_CTL_DTEN0_Msk (0x1U << DAC_CTL_DTEN0_Pos) /*!< 0x00000004 */ #define DAC_CTL_DTEN0 DAC_CTL_DTEN0_Msk /*!< DAC channel1 Trigger enable */ #define DAC_CTL_DTSEL0_Pos (3U) #define DAC_CTL_DTSEL0_Msk (0x7U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000038 */ #define DAC_CTL_DTSEL0 DAC_CTL_DTSEL0_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ #define DAC_CTL_DTSEL0_0 (0x1U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000008 */ #define DAC_CTL_DTSEL0_1 (0x2U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000010 */ #define DAC_CTL_DTSEL0_2 (0x4U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000020 */ #define DAC_CTL_DWM0_Pos (6U) #define DAC_CTL_DWM0_Msk (0x3U << DAC_CTL_DWM0_Pos) /*!< 0x000000C0 */ #define DAC_CTL_DWM0 DAC_CTL_DWM0_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ #define DAC_CTL_DWM0_0 (0x1U << DAC_CTL_DWM0_Pos) /*!< 0x00000040 */ #define DAC_CTL_DWM0_1 (0x2U << DAC_CTL_DWM0_Pos) /*!< 0x00000080 */ #define DAC_CTL_DWBW0_Pos (8U) #define DAC_CTL_DWBW0_Msk (0xFU << DAC_CTL_DWBW0_Pos) /*!< 0x00000F00 */ #define DAC_CTL_DWBW0 DAC_CTL_DWBW0_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ #define DAC_CTL_DWBW0_0 (0x1U << DAC_CTL_DWBW0_Pos) /*!< 0x00000100 */ #define DAC_CTL_DWBW0_1 (0x2U << DAC_CTL_DWBW0_Pos) /*!< 0x00000200 */ #define DAC_CTL_DWBW0_2 (0x4U << DAC_CTL_DWBW0_Pos) /*!< 0x00000400 */ #define DAC_CTL_DWBW0_3 (0x8U << DAC_CTL_DWBW0_Pos) /*!< 0x00000800 */ #define DAC_CTL_DDMAEN0_Pos (12U) #define DAC_CTL_DDMAEN0_Msk (0x1U << DAC_CTL_DDMAEN0_Pos) /*!< 0x00001000 */ #define DAC_CTL_DDMAEN0 DAC_CTL_DDMAEN0_Msk /*!< DAC channel1 DMA enable */ #define DAC_CTL_DEN1_Pos (16U) #define DAC_CTL_DEN1_Msk (0x1U << DAC_CTL_DEN1_Pos) /*!< 0x00010000 */ #define DAC_CTL_DEN1 DAC_CTL_DEN1_Msk /*!< DAC channel2 enable */ #define DAC_CTL_DBOFF1_Pos (17U) #define DAC_CTL_DBOFF1_Msk (0x1U << DAC_CTL_DBOFF1_Pos) /*!< 0x00020000 */ #define DAC_CTL_DBOFF1 DAC_CTL_DBOFF1_Msk /*!< DAC channel2 output buffer disable */ #define DAC_CTL_DTEN1_Pos (18U) #define DAC_CTL_DTEN1_Msk (0x1U << DAC_CTL_DTEN1_Pos) /*!< 0x00040000 */ #define DAC_CTL_DTEN1 DAC_CTL_DTEN1_Msk /*!< DAC channel2 Trigger enable */ #define DAC_CTL_DTSEL1_Pos (19U) #define DAC_CTL_DTSEL1_Msk (0x7U << DAC_CTL_DTSEL1_Pos) /*!< 0x00380000 */ #define DAC_CTL_DTSEL1 DAC_CTL_DTSEL1_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ #define DAC_CTL_DTSEL1_0 (0x1U << DAC_CTL_DTSEL1_Pos) /*!< 0x00080000 */ #define DAC_CTL_DTSEL1_1 (0x2U << DAC_CTL_DTSEL1_Pos) /*!< 0x00100000 */ #define DAC_CTL_DTSEL1_2 (0x4U << DAC_CTL_DTSEL1_Pos) /*!< 0x00200000 */ #define DAC_CTL_DWM1_Pos (22U) #define DAC_CTL_DWM1_Msk (0x3U << DAC_CTL_DWM1_Pos) /*!< 0x00C00000 */ #define DAC_CTL_DWM1 DAC_CTL_DWM1_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ #define DAC_CTL_DWM1_0 (0x1U << DAC_CTL_DWM1_Pos) /*!< 0x00400000 */ #define DAC_CTL_DWM1_1 (0x2U << DAC_CTL_DWM1_Pos) /*!< 0x00800000 */ #define DAC_CTL_DWBW1_Pos (24U) #define DAC_CTL_DWBW1_Msk (0xFU << DAC_CTL_DWBW1_Pos) /*!< 0x0F000000 */ #define DAC_CTL_DWBW1 DAC_CTL_DWBW1_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ #define DAC_CTL_DWBW1_0 (0x1U << DAC_CTL_DWBW1_Pos) /*!< 0x01000000 */ #define DAC_CTL_DWBW1_1 (0x2U << DAC_CTL_DWBW1_Pos) /*!< 0x02000000 */ #define DAC_CTL_DWBW1_2 (0x4U << DAC_CTL_DWBW1_Pos) /*!< 0x04000000 */ #define DAC_CTL_DWBW1_3 (0x8U << DAC_CTL_DWBW1_Pos) /*!< 0x08000000 */ #define DAC_CTL_DDMAEN1_Pos (28U) #define DAC_CTL_DDMAEN1_Msk (0x1U << DAC_CTL_DDMAEN1_Pos) /*!< 0x10000000 */ #define DAC_CTL_DDMAEN1 DAC_CTL_DDMAEN1_Msk /*!< DAC channel2 DMA enabled */ /***************** Bit definition for DAC_SWT register ******************/ #define DAC_SWT_SWTR0_Pos (0U) #define DAC_SWT_SWTR0_Msk (0x1U << DAC_SWT_SWTR0_Pos) /*!< 0x00000001 */ #define DAC_SWT_SWTR0 DAC_SWT_SWTR0_Msk /*!< DAC channel1 software trigger */ #define DAC_SWT_SWTR1_Pos (1U) #define DAC_SWT_SWTR1_Msk (0x1U << DAC_SWT_SWTR1_Pos) /*!< 0x00000002 */ #define DAC_SWT_SWTR1 DAC_SWT_SWTR1_Msk /*!< DAC channel2 software trigger */ /***************** Bit definition for DAC_DAC0_R12DH register ******************/ #define DAC_DAC0_R12DH_DAC0_DH_Pos (0U) #define DAC_DAC0_R12DH_DAC0_DH_Msk (0xFFFU << DAC_DAC0_R12DH_DAC0_DH_Pos) /*!< 0x00000FFF */ #define DAC_DAC0_R12DH_DAC0_DH DAC_DAC0_R12DH_DAC0_DH_Msk /*!< DAC channel1 12-bit Right aligned data */ /***************** Bit definition for DAC_DAC0_L12DH register ******************/ #define DAC_DAC0_L12DH_DAC0_DH_Pos (4U) #define DAC_DAC0_L12DH_DAC0_DH_Msk (0xFFFU << DAC_DAC0_L12DH_DAC0_DH_Pos) /*!< 0x0000FFF0 */ #define DAC_DAC0_L12DH_DAC0_DH DAC_DAC0_L12DH_DAC0_DH_Msk /*!< DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_DAC0_R8DH register ******************/ #define DAC_DAC0_R8DH_DAC0_DH_Pos (0U) #define DAC_DAC0_R8DH_DAC0_DH_Msk (0xFFU << DAC_DAC0_R8DH_DAC0_DH_Pos) /*!< 0x000000FF */ #define DAC_DAC0_R8DH_DAC0_DH DAC_DAC0_R8DH_DAC0_DH_Msk /*!< DAC channel1 8-bit Right aligned data */ /***************** Bit definition for DAC_DAC1_R12DH register ******************/ #define DAC_DAC1_R12DH_DAC1_DH_Pos (0U) #define DAC_DAC1_R12DH_DAC1_DH_Msk (0xFFFU << DAC_DAC1_R12DH_DAC1_DH_Pos) /*!< 0x00000FFF */ #define DAC_DAC1_R12DH_DAC1_DH DAC_DAC1_R12DH_DAC1_DH_Msk /*!< DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_DAC1_L12DH register ******************/ #define DAC_DAC1_L12DH_DAC1_DH_Pos (4U) #define DAC_DAC1_L12DH_DAC1_DH_Msk (0xFFFU << DAC_DAC1_L12DH_DAC1_DH_Pos) /*!< 0x0000FFF0 */ #define DAC_DAC1_L12DH_DAC1_DH DAC_DAC1_L12DH_DAC1_DH_Msk /*!< DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_DAC1_R8DH register ******************/ #define DAC_DAC1_R8DH_DAC1_DH_Pos (0U) #define DAC_DAC1_R8DH_DAC1_DH_Msk (0xFFU << DAC_DAC1_R8DH_DAC1_DH_Pos) /*!< 0x000000FF */ #define DAC_DAC1_R8DH_DAC1_DH DAC_DAC1_R8DH_DAC1_DH_Msk /*!< DAC channel2 8-bit Right aligned data */ /***************** Bit definition for DAC_DACC_R12DH register ******************/ #define DAC_DACC_R12DH_DAC0_DH_Pos (0U) #define DAC_DACC_R12DH_DAC0_DH_Msk (0xFFFU << DAC_DACC_R12DH_DAC0_DH_Pos) /*!< 0x00000FFF */ #define DAC_DACC_R12DH_DAC0_DH DAC_DACC_R12DH_DAC0_DH_Msk /*!< DAC channel1 12-bit Right aligned data */ #define DAC_DACC_R12DH_DAC1_DH_Pos (16U) #define DAC_DACC_R12DH_DAC1_DH_Msk (0xFFFU << DAC_DACC_R12DH_DAC1_DH_Pos) /*!< 0x0FFF0000 */ #define DAC_DACC_R12DH_DAC1_DH DAC_DACC_R12DH_DAC1_DH_Msk /*!< DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_DACC_L12DH register ******************/ #define DAC_DACC_L12DH_DAC0_DH_Pos (4U) #define DAC_DACC_L12DH_DAC0_DH_Msk (0xFFFU << DAC_DACC_L12DH_DAC0_DH_Pos) /*!< 0x0000FFF0 */ #define DAC_DACC_L12DH_DAC0_DH DAC_DACC_L12DH_DAC0_DH_Msk /*!< DAC channel1 12-bit Left aligned data */ #define DAC_DACC_L12DH_DAC1_DH_Pos (20U) #define DAC_DACC_L12DH_DAC1_DH_Msk (0xFFFU << DAC_DACC_L12DH_DAC1_DH_Pos) /*!< 0xFFF00000 */ #define DAC_DACC_L12DH_DAC1_DH DAC_DACC_L12DH_DAC1_DH_Msk /*!< DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_DACC_R8DH register ******************/ #define DAC_DACC_R8DH_DAC0_DH_Pos (0U) #define DAC_DACC_R8DH_DAC0_DH_Msk (0xFFU << DAC_DACC_R8DH_DAC0_DH_Pos) /*!< 0x000000FF */ #define DAC_DACC_R8DH_DAC0_DH DAC_DACC_R8DH_DAC0_DH_Msk /*!< DAC channel1 8-bit Right aligned data */ #define DAC_DACC_R8DH_DAC1_DH_Pos (8U) #define DAC_DACC_R8DH_DAC1_DH_Msk (0xFFU << DAC_DACC_R8DH_DAC1_DH_Pos) /*!< 0x0000FF00 */ #define DAC_DACC_R8DH_DAC1_DH DAC_DACC_R8DH_DAC1_DH_Msk /*!< DAC channel2 8-bit Right aligned data */ /******************* Bit definition for DAC_DAC0_DO register *******************/ #define DAC_DAC0_DO_DAC0_DO_Pos (0U) #define DAC_DAC0_DO_DAC0_DO_Msk (0xFFFU << DAC_DAC0_DO_DAC0_DO_Pos) /*!< 0x00000FFF */ #define DAC_DAC0_DO_DAC0_DO DAC_DAC0_DO_DAC0_DO_Msk /*!< DAC channel1 data output */ /******************* Bit definition for DAC_DAC1_DO register *******************/ #define DAC_DAC1_DO_DAC1_DO_Pos (0U) #define DAC_DAC1_DO_DAC1_DO_Msk (0xFFFU << DAC_DAC1_DO_DAC1_DO_Pos) /*!< 0x00000FFF */ #define DAC_DAC1_DO_DAC1_DO DAC_DAC1_DO_DAC1_DO_Msk /*!< DAC channel2 data output */ /*****************************************************************************/ /* */ /* Timers (TIM) */ /* */ /*****************************************************************************/ /******************* Bit definition for TIM_CR1 register *******************/ #define TIM_CR1_CEN_Pos (0U) #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!