/* ** ################################################################### ** Processors: MKE15Z128VLH7 ** MKE15Z128VLL7 ** MKE15Z256VLH7 ** MKE15Z256VLL7 ** ** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** ** Reference manual: KE1xZP100M72SF0RM, Rev. 2, Aug. 2016 ** Version: rev. 6.0, 2016-09-20 ** Build: b200925 ** ** Abstract: ** CMSIS Peripheral Access Layer for MKE15Z7 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2015-08-19) ** Initial version. ** - rev. 2.0 (2015-09-22) ** Based on rev0final RDP, add PCC/TRGMUX. ** - rev. 3.0 (2015-12-29) ** Align LPFLL register names. ** - rev. 4.0 (2016-02-19) ** Based on rev1final RDP. ** - rev. 5.0 (2016-08-02) ** Based on rev1.x RDP. ** - rev. 6.0 (2016-09-20) ** Based on rev2 RDP. ** ** ################################################################### */ /*! * @file MKE15Z7.h * @version 6.0 * @date 2016-09-20 * @brief CMSIS Peripheral Access Layer for MKE15Z7 * * CMSIS Peripheral Access Layer for MKE15Z7 */ #ifndef _MKE15Z7_H_ #define _MKE15Z7_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0600U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ /* Device specific interrupts */ DMA0_04_IRQn = 0, /**< DMA channel 0 or 4 transfer complete */ DMA0_15_IRQn = 1, /**< DMA channel 1 or 5 transfer complete */ DMA0_26_IRQn = 2, /**< DMA channel 2 or 6 transfer complete */ DMA0_37_IRQn = 3, /**< DMA channel 3 or 7 transfer complete */ DMA_Error_IRQn = 4, /**< DMA error interrupt channels 0-7 */ FTFE_IRQn = 5, /**< Single interrupt vector for all sources */ LVD_LVW_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ PORTAE_IRQn = 7, /**< Pin detect (Port A, E) */ LPI2C0_IRQn = 8, /**< Inter-integrated circuit 0 interrupt */ LPI2C1_IRQn = 9, /**< Inter-integrated circuit 1 interrupt */ LPSPI0_IRQn = 10, /**< Serial peripheral Interface 0 interrupt */ LPSPI1_IRQn = 11, /**< Serial peripheral Interface 1 interrupt */ LPUART0_IRQn = 12, /**< Single interrupt vector for all sources */ LPUART1_IRQn = 13, /**< Single interrupt vector for all sources */ LPUART2_IRQn = 14, /**< Single interrupt vector for all sources */ ADC0_IRQn = 15, /**< ADC0 conversion complete interrupt */ CMP0_IRQn = 16, /**< CMP0 interrupt */ FTM0_IRQn = 17, /**< FTM0 single interrupt vector for all sources */ FTM1_IRQn = 18, /**< FTM1 single interrupt vector for all sources */ FTM2_IRQn = 19, /**< FTM2 single interrupt vector for all sources */ RTC_IRQn = 20, /**< Single interrupt vector for all sources */ CMP1_IRQn = 21, /**< CMP1 interrupt */ LPIT0_IRQn = 22, /**< LPIT interrupt */ FLEXIO_IRQn = 23, /**< FLEXIO interrupt */ TSI_IRQn = 24, /**< TSI interrupt */ PDB0_IRQn = 25, /**< Programmable delay block interrupt */ PORTBCD_IRQn = 26, /**< Pin detect (Port B, C, D) */ SCG_IRQn = 27, /**< System clock generator interrupt */ WDOG_EWM_IRQn = 28, /**< Single interrupt vector for WDOG and EWM */ PWT_LPTMR0_IRQn = 29, /**< Single interrupt vector for PWT and LPTMR0 */ ADC1_IRQn = 30, /**< ADC1 conversion complete interrupt */ RCM_IRQn = 31 /**< RCM interrupt */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Cortex M0 Core Configuration ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration * @{ */ #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #include "core_cm0plus.h" /* Core Peripheral Access Layer */ #include "system_MKE15Z7.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Mapping Information ---------------------------------------------------------------------------- */ /*! * @addtogroup Mapping_Information Mapping Information * @{ */ /** Mapping Information */ /*! * @addtogroup edma_request * @{ */ /******************************************************************************* * Definitions ******************************************************************************/ /*! * @brief Structure for the DMA hardware request * * Defines the structure for the DMA hardware request collections. The user can configure the * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index * of the hardware request varies according to the to SoC. */ typedef enum _dma_request_source { kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled */ kDmaRequestMux0TSI = 1|0x100U, /**< TSI */ kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive */ kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit */ kDmaRequestMux0LPUART1Rx = 4|0x100U, /**< LPUART1 Receive */ kDmaRequestMux0LPUART1Tx = 5|0x100U, /**< LPUART1 Transmit */ kDmaRequestMux0LPUART2Rx = 6|0x100U, /**< LPUART2 Receive */ kDmaRequestMux0LPUART2Tx = 7|0x100U, /**< LPUART2 Transmit */ kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ kDmaRequestMux0FlexIOChannel0 = 10|0x100U, /**< FLEXIO Shifter0 */ kDmaRequestMux0FlexIOChannel1 = 11|0x100U, /**< FLEXIO Shifter1 */ kDmaRequestMux0FlexIOChannel2 = 12|0x100U, /**< FLEXIO Shifter2 */ kDmaRequestMux0FlexIOChannel3 = 13|0x100U, /**< FLEXIO Shifter3 */ kDmaRequestMux0LPSPI0Rx = 14|0x100U, /**< LPSPI0 Receive */ kDmaRequestMux0LPSPI0Tx = 15|0x100U, /**< LPSPI0 Transmit */ kDmaRequestMux0LPSPI1Rx = 16|0x100U, /**< LPSPI1 Receive */ kDmaRequestMux0LPSPI1Tx = 17|0x100U, /**< LPSPI1 Transmit */ kDmaRequestMux0LPI2C0Rx = 18|0x100U, /**< LPI2C0 Receive */ kDmaRequestMux0LPI2C0Tx = 19|0x100U, /**< LPI2C0 Transmit */ kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V */ kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V */ kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V */ kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V */ kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V */ kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V */ kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V */ kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V */ kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V */ kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V */ kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V */ kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V */ kDmaRequestMux0LPI2C1Rx = 32|0x100U, /**< LPI2C1 Receive */ kDmaRequestMux0LPI2C1Tx = 33|0x100U, /**< LPI2C1 Transmit */ kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */ kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */ kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0 COCO */ kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1 COCO */ kDmaRequestMux0Reserved42 = 42|0x100U, /**< Reserved42 */ kDmaRequestMux0CMP0 = 43|0x100U, /**< CMP0 */ kDmaRequestMux0CMP1 = 44|0x100U, /**< CMP1 */ kDmaRequestMux0Reserved45 = 45|0x100U, /**< Reserved45 */ kDmaRequestMux0PDB0 = 46|0x100U, /**< PDB0 */ kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */ kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ kDmaRequestMux0PortA = 49|0x100U, /**< PTA PortA */ kDmaRequestMux0PortB = 50|0x100U, /**< PTB PortB */ kDmaRequestMux0PortC = 51|0x100U, /**< PTC PortC */ kDmaRequestMux0PortD = 52|0x100U, /**< PTD PortD */ kDmaRequestMux0PortE = 53|0x100U, /**< PTE PortE */ kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */ kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */ kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */ kDmaRequestMux0FTM1Channel2 = 57|0x100U, /**< FTM1 Channel2 */ kDmaRequestMux0FTM1Channel3 = 57|0x100U, /**< FTM1 Channel3 */ kDmaRequestMux0FTM2Channel2 = 58|0x100U, /**< FTM2 Channel2 */ kDmaRequestMux0FTM2Channel3 = 58|0x100U, /**< FTM2 Channel3 */ kDmaRequestMux0LPTMR0 = 59|0x100U, /**< LPTMR0 */ kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot */ kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot */ kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot */ kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot */ } dma_request_source_t; /* @} */ /*! * @addtogroup trgmux_source * @{ */ /******************************************************************************* * Definitions *******************************************************************************/ /*! * @brief Structure for the TRGMUX source * * Defines the structure for the TRGMUX source collections. */ typedef enum _trgmux_source { kTRGMUX_SourceTriggerMuxInput0 = 0U, /**< Trigger Mux input 0 is selected */ kTRGMUX_SourceDisabled0 = 0U, /**< Trigger function is disabled */ kTRGMUX_SourceTriggerMuxInput1 = 1U, /**< Trigger Mux input 1 is selected */ kTRGMUX_SourceDisabled1 = 1U, /**< Trigger function is disabled */ kTRGMUX_SourceTriggerMuxInput2 = 2U, /**< Trigger Mux input 2 is selected */ kTRGMUX_SimSoftwareTrigger = 2U, /**< SIM Software Trigger is selected */ kTRGMUX_SourceTriggerMuxInput3 = 3U, /**< Trigger Mux input 3 is selected */ kTRGMUX_SourceTriggerMuxInput4 = 3U, /**< Trigger Mux input 4 is selected */ kTRGMUX_SourceRtcSeconds = 4U, /**< RTC Seconds input is selected */ kTRGMUX_SourceTriggerMuxInput5 = 4U, /**< Trigger Mux input 5 is selected */ kTRGMUX_SourceRtcAlarm = 5U, /**< RTC Alarm input is selected */ kTRGMUX_SourceTriggerMuxInput6 = 5U, /**< Trigger Mux input 6 is selected */ kTRGMUX_SourceLptmr0 = 6U, /**< LPTMR0 input is selected */ kTRGMUX_SourceTriggerMuxInput7 = 6U, /**< Trigger Mux input 7 is selected */ kTRGMUX_SourceLpit0Ch0 = 7U, /**< LPIT0 Channel0 is selected */ kTRGMUX_SourceLpuart0RxData = 7U, /**< LPUART0 RX Data is selected */ kTRGMUX_SourceLpit0Ch1 = 8U, /**< LPIT0 Channel1 is selected */ kTRGMUX_SourceLpuart0TxData = 8U, /**< LPUART0 TX Data is selected */ kTRGMUX_SourceLpit0Ch2 = 9U, /**< LPIT0 Channel2 is selected */ kTRGMUX_SourceLpuart0Idle = 9U, /**< LPUART0 Idle is selected */ kTRGMUX_SourceLpit0Ch3 = 10U, /**< LPIT0 Channel3 is selected */ kTRGMUX_SourceLpi2c0MasterStop = 10U, /**< LPI2C0 Master STOP is selected */ kTRGMUX_SourceFtm0 = 11U, /**< FTM0 is selected */ kTRGMUX_SourceLpi2c0SlaveStop = 11U, /**< LPI2C0 Slave STOP is selected */ kTRGMUX_SourceFtm1 = 12U, /**< FTM1 is selected */ kTRGMUX_SourceLpspi0Frame = 12U, /**< LPSPI0 Frame is selected */ kTRGMUX_SourceFtm2 = 13U, /**< FTM2 is selected */ kTRGMUX_SourceLpspi0RxData = 13U, /**< LPSPI0 RX Data is selected */ kTRGMUX_SourceAdc0CocoA = 15U, /**< ADC0 COCOA is selected */ kTRGMUX_SourceLpuart1TxData = 15U, /**< LPUART1 TX Data is selected */ kTRGMUX_SourceAdc0CocoB = 16U, /**< ADC0 COCOB is selected */ kTRGMUX_SourceLpuart1RxIdle = 16U, /**< LPUART1 RX Idle is selected */ kTRGMUX_SourceCmp0Output = 17U, /**< CMP0 Output is selected */ kTRGMUX_SourceLpi2c1MasterStop = 17U, /**< LPI2C1 Master STOP is selected */ kTRGMUX_SourceCmp1Output = 18U, /**< CMP1 Output is selected */ kTRGMUX_SourceLpi2c1SlaveStop = 18U, /**< LPI2C1 Slave STOP is selected */ kTRGMUX_SourceFlexIOTimer0 = 20U, /**< FLEXIO Trigger 0 is selected */ kTRGMUX_SourceLpspi1RxData = 20U, /**< LPSPI1 RX Data is selected */ kTRGMUX_SourceFlexIOTimer1 = 21U, /**< FLEXIO Trigger 1 is selected */ kTRGMUX_SourceAdc1CocoA = 21U, /**< ADC1 COCOA is selected */ kTRGMUX_SourceFlexIOTimer2 = 22U, /**< FLEXIO Trigger 2 is selected */ kTRGMUX_SourceAdc1CocoB = 22U, /**< ADC1 COCOB is selected */ kTRGMUX_SourceFlexIOTimer3 = 23U, /**< FLEXIO Trigger 3 is selected */ kTRGMUX_SourcePdb0Pulse0 = 23U, /**< PDB0 Pulse0 is selected */ kTRGMUX_SourceTrgmux1Output0 = 24U, /**< TRGMUX1 Output 0 is selected */ kTRGMUX_SourcePdb0Pulse1 = 24U, /**< PDB0 Pulse1 is selected */ kTRGMUX_SourceTrgmux1Output1 = 25U, /**< TRGMUX1 Output 1 is selected */ kTRGMUX_SourceTrgmux1Output2 = 26U, /**< TRGMUX1 Output 2 is selected */ kTRGMUX_SourceTrgmux1Output3 = 27U, /**< TRGMUX1 Output 3 is selected */ kTRGMUX_SourceTrgmux1Output4 = 28U, /**< TRGMUX1 Output 4 is selected */ kTRGMUX_SourceTrgmux1Output5 = 29U, /**< TRGMUX1 Output 5 is selected */ kTRGMUX_SourceTrgmux1Output6 = 30U, /**< TRGMUX1 Output 6 is selected */ kTRGMUX_SourceTrgmux1Output7 = 31U, /**< TRGMUX1 Output 7 is selected */ kTRGMUX_SourceLpuart1RxData = 14U, /**< LPUART1 RX Data is selected */ kTRGMUX_SourceLpspi1Frame = 19U, /**< LPSPI1 Frame is selected */ } trgmux_source_t; /*! * @brief Structure for the TRGMUX device * * Defines the structure for the TRGMUX device collections. */ typedef enum _trgmux_device { kTRGMUX_Dmamux0 = 0U, /**< DMAMUX0 device trigger input */ kTRGMUX_Ctrl0 = 0U, /**< CTRL0 device trigger input */ kTRGMUX_ExtOut0_3 = 1U, /**< EXTOUT0 device trigger input */ kTRGMUX_Ctrl1 = 1U, /**< CTRL1 device trigger input */ kTRGMUX_ExtOut4_7 = 2U, /**< EXTOUT1 device trigger input */ kTRGMUX_Adc0 = 3U, /**< ADC0 device trigger input */ kTRGMUX_Adc1 = 4U, /**< ADC1 device trigger input */ kTRGMUX_Cmp0 = 7U, /**< CMP0 device trigger input */ kTRGMUX_Cmp1 = 8U, /**< CMP1 device trigger input */ kTRGMUX_Ftm0 = 10U, /**< FTM0 device trigger input */ kTRGMUX_Ftm1 = 11U, /**< FTM1 device trigger input */ kTRGMUX_Ftm2 = 12U, /**< FTM2 device trigger input */ kTRGMUX_Pdb0 = 14U, /**< PDB0 device trigger input */ kTRGMUX_Flexio = 17U, /**< FLEXIO device trigger input */ kTRGMUX_Lpit = 18U, /**< LPIT device trigger input */ kTRGMUX_Lpuart0 = 19U, /**< LPUART0 device trigger input */ kTRGMUX_Lpuart1 = 20U, /**< LPUART1 device trigger input */ kTRGMUX_Lpi2c0 = 21U, /**< LPI2C0 device trigger input */ kTRGMUX_Lpi2c1 = 22U, /**< LPI2C1 device trigger input */ kTRGMUX_Lpspi0 = 23U, /**< LPSPI0 device trigger input */ kTRGMUX_Lpspi1 = 24U, /**< LPSPI1 device trigger input */ kTRGMUX_Lptmr0 = 25U, /**< LPTMR0 device trigger input */ kTRGMUX_Tsi = 26U, /**< TSI device trigger input */ kTRGMUX_Pwt = 27U, /**< PWT device trigger input */ } trgmux_device_t; /* @} */ /*! * @} */ /* end of group Mapping_Information */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #else #pragma push #pragma anon_unions #endif #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __IO uint32_t SC1[2]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ uint8_t RESERVED_0[56]; __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ __I uint32_t R[2]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ uint8_t RESERVED_1[56]; __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x88 */ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x8C */ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ } ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /*! @name SC1 - ADC Status and Control Register 1 */ /*! @{ */ #define ADC_SC1_ADCH_MASK (0x1FU) #define ADC_SC1_ADCH_SHIFT (0U) /*! ADCH - Input channel select * 0b00000..AD0 is selected as input. * 0b00001..AD1 is selected as input. * 0b00010..AD2 is selected as input. * 0b00011..AD3 is selected as input. * 0b00100..AD4 is selected as input. * 0b00101..AD5 is selected as input. * 0b00110..AD6 is selected as input. * 0b00111..AD7 is selected as input. * 0b01000..AD8 is selected as input. * 0b01001..AD9 is selected as input. * 0b01010..AD10 is selected as input. * 0b01011..AD11 is selected as input. * 0b01100..AD12 is selected as input. * 0b01101..AD13 is selected as input. * 0b01110..AD14 is selected as input. * 0b01111..AD15 is selected as input. * 0b10000..Reserved. * 0b10001..Reserved. * 0b10010..AD18 is selected as input. * 0b10011..AD19 is selected as input. * 0b10100..Reserved. * 0b10101..AD21 is selected as input. * 0b10110..AD22 is selected as input. * 0b10111..AD23 is selected as input. * 0b11000..Reserved * 0b11001..Reserved * 0b11010..Temp Sensor * 0b11011..Band Gap * 0b11100..AD28 is selected as input. * 0b11101..VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]. * 0b11110..VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]. * 0b11111..Module is disabled */ #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) #define ADC_SC1_AIEN_MASK (0x40U) #define ADC_SC1_AIEN_SHIFT (6U) /*! AIEN - Interrupt Enable * 0b0..Conversion complete interrupt is disabled. * 0b1..Conversion complete interrupt is enabled. */ #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) #define ADC_SC1_COCO_MASK (0x80U) #define ADC_SC1_COCO_SHIFT (7U) /*! COCO - Conversion Complete Flag * 0b0..Conversion is not completed. * 0b1..Conversion is completed. */ #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) /*! @} */ /* The count of ADC_SC1 */ #define ADC_SC1_COUNT (2U) /*! @name CFG1 - ADC Configuration Register 1 */ /*! @{ */ #define ADC_CFG1_ADICLK_MASK (0x3U) #define ADC_CFG1_ADICLK_SHIFT (0U) /*! ADICLK - Input Clock Select * 0b00..Alternate clock 1 (ADC_ALTCLK1) * 0b01..Alternate clock 2 (ADC_ALTCLK2) * 0b10..Alternate clock 3 (ADC_ALTCLK3) * 0b11..Alternate clock 4 (ADC_ALTCLK4) */ #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) #define ADC_CFG1_MODE_MASK (0xCU) #define ADC_CFG1_MODE_SHIFT (2U) /*! MODE - Conversion mode selection * 0b00..8-bit conversion. * 0b01..12-bit conversion. * 0b10..10-bit conversion. * 0b11..Reserved */ #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) #define ADC_CFG1_ADIV_MASK (0x60U) #define ADC_CFG1_ADIV_SHIFT (5U) /*! ADIV - Clock Divide Select * 0b00..The divide ratio is 1 and the clock rate is input clock. * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8. */ #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) /*! @} */ /*! @name CFG2 - ADC Configuration Register 2 */ /*! @{ */ #define ADC_CFG2_SMPLTS_MASK (0xFFU) #define ADC_CFG2_SMPLTS_SHIFT (0U) /*! SMPLTS - Sample Time Select */ #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_SMPLTS_SHIFT)) & ADC_CFG2_SMPLTS_MASK) /*! @} */ /*! @name R - ADC Data Result Registers */ /*! @{ */ #define ADC_R_D_MASK (0xFFFU) #define ADC_R_D_SHIFT (0U) /*! D - Data result */ #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) /*! @} */ /* The count of ADC_R */ #define ADC_R_COUNT (2U) /*! @name CV1 - Compare Value Registers */ /*! @{ */ #define ADC_CV1_CV_MASK (0xFFFFU) #define ADC_CV1_CV_SHIFT (0U) /*! CV - Compare Value. */ #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) /*! @} */ /*! @name CV2 - Compare Value Registers */ /*! @{ */ #define ADC_CV2_CV_MASK (0xFFFFU) #define ADC_CV2_CV_SHIFT (0U) /*! CV - Compare Value. */ #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) /*! @} */ /*! @name SC2 - Status and Control Register 2 */ /*! @{ */ #define ADC_SC2_REFSEL_MASK (0x3U) #define ADC_SC2_REFSEL_SHIFT (0U) /*! REFSEL - Voltage Reference Selection * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL * 0b01..Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal * source depending on the MCU configuration. See the chip configuration information for details specific to * this MCU. * 0b10..Reserved * 0b11..Reserved */ #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) #define ADC_SC2_DMAEN_MASK (0x4U) #define ADC_SC2_DMAEN_SHIFT (2U) /*! DMAEN - DMA Enable * 0b0..DMA is disabled. * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is * indicated when any SC1n[COCO] flag is asserted. */ #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) #define ADC_SC2_ACREN_MASK (0x8U) #define ADC_SC2_ACREN_SHIFT (3U) /*! ACREN - Compare Function Range Enable */ #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) #define ADC_SC2_ACFGT_MASK (0x10U) #define ADC_SC2_ACFGT_SHIFT (4U) /*! ACFGT - Compare Function Greater Than Enable */ #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) #define ADC_SC2_ACFE_MASK (0x20U) #define ADC_SC2_ACFE_SHIFT (5U) /*! ACFE - Compare Function Enable * 0b0..Compare function disabled. * 0b1..Compare function enabled. */ #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) #define ADC_SC2_ADTRG_MASK (0x40U) #define ADC_SC2_ADTRG_SHIFT (6U) /*! ADTRG - Conversion Trigger Select * 0b0..Software trigger selected. * 0b1..Hardware trigger selected. */ #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) #define ADC_SC2_ADACT_MASK (0x80U) #define ADC_SC2_ADACT_SHIFT (7U) /*! ADACT - Conversion Active * 0b0..Conversion not in progress. * 0b1..Conversion in progress. */ #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) /*! @} */ /*! @name SC3 - Status and Control Register 3 */ /*! @{ */ #define ADC_SC3_AVGS_MASK (0x3U) #define ADC_SC3_AVGS_SHIFT (0U) /*! AVGS - Hardware Average Select * 0b00..4 samples averaged. * 0b01..8 samples averaged. * 0b10..16 samples averaged. * 0b11..32 samples averaged. */ #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) #define ADC_SC3_AVGE_MASK (0x4U) #define ADC_SC3_AVGE_SHIFT (2U) /*! AVGE - Hardware Average Enable * 0b0..Hardware average function disabled. * 0b1..Hardware average function enabled. */ #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) #define ADC_SC3_ADCO_MASK (0x8U) #define ADC_SC3_ADCO_SHIFT (3U) /*! ADCO - Continuous Conversion Enable * 0b0..One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated. * 0b1..Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated. */ #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) #define ADC_SC3_CAL_MASK (0x80U) #define ADC_SC3_CAL_SHIFT (7U) /*! CAL - Calibration */ #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) /*! @} */ /*! @name BASE_OFS - BASE Offset Register */ /*! @{ */ #define ADC_BASE_OFS_BA_OFS_MASK (0xFFU) #define ADC_BASE_OFS_BA_OFS_SHIFT (0U) /*! BA_OFS - Base Offset Error Correction Value */ #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_BASE_OFS_BA_OFS_SHIFT)) & ADC_BASE_OFS_BA_OFS_MASK) /*! @} */ /*! @name OFS - ADC Offset Correction Register */ /*! @{ */ #define ADC_OFS_OFS_MASK (0xFFFFU) #define ADC_OFS_OFS_SHIFT (0U) /*! OFS - Offset Error Correction Value */ #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) /*! @} */ /*! @name USR_OFS - USER Offset Correction Register */ /*! @{ */ #define ADC_USR_OFS_USR_OFS_MASK (0xFFU) #define ADC_USR_OFS_USR_OFS_SHIFT (0U) /*! USR_OFS - USER Offset Error Correction Value */ #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_USR_OFS_USR_OFS_SHIFT)) & ADC_USR_OFS_USR_OFS_MASK) /*! @} */ /*! @name XOFS - ADC X Offset Correction Register */ /*! @{ */ #define ADC_XOFS_XOFS_MASK (0x3FU) #define ADC_XOFS_XOFS_SHIFT (0U) /*! XOFS - X offset error correction value */ #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_XOFS_XOFS_SHIFT)) & ADC_XOFS_XOFS_MASK) /*! @} */ /*! @name YOFS - ADC Y Offset Correction Register */ /*! @{ */ #define ADC_YOFS_YOFS_MASK (0xFFU) #define ADC_YOFS_YOFS_SHIFT (0U) /*! YOFS - Y offset error correction value */ #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_YOFS_YOFS_SHIFT)) & ADC_YOFS_YOFS_MASK) /*! @} */ /*! @name G - ADC Gain Register */ /*! @{ */ #define ADC_G_G_MASK (0x7FFU) #define ADC_G_G_SHIFT (0U) #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x)) << ADC_G_G_SHIFT)) & ADC_G_G_MASK) /*! @} */ /*! @name UG - ADC User Gain Register */ /*! @{ */ #define ADC_UG_UG_MASK (0x3FFU) #define ADC_UG_UG_SHIFT (0U) #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x)) << ADC_UG_UG_SHIFT)) & ADC_UG_UG_MASK) /*! @} */ /*! @name CLPS - ADC General Calibration Value Register S */ /*! @{ */ #define ADC_CLPS_CLPS_MASK (0x7FU) #define ADC_CLPS_CLPS_SHIFT (0U) #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) /*! @} */ /*! @name CLP3 - ADC Plus-Side General Calibration Value Register 3 */ /*! @{ */ #define ADC_CLP3_CLP3_MASK (0x3FFU) #define ADC_CLP3_CLP3_SHIFT (0U) #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) /*! @} */ /*! @name CLP2 - ADC Plus-Side General Calibration Value Register 2 */ /*! @{ */ #define ADC_CLP2_CLP2_MASK (0x3FFU) #define ADC_CLP2_CLP2_SHIFT (0U) #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) /*! @} */ /*! @name CLP1 - ADC Plus-Side General Calibration Value Register 1 */ /*! @{ */ #define ADC_CLP1_CLP1_MASK (0x1FFU) #define ADC_CLP1_CLP1_SHIFT (0U) #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) /*! @} */ /*! @name CLP0 - ADC Plus-Side General Calibration Value Register 0 */ /*! @{ */ #define ADC_CLP0_CLP0_MASK (0xFFU) #define ADC_CLP0_CLP0_SHIFT (0U) #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) /*! @} */ /*! @name CLPX - ADC Plus-Side General Calibration Value Register X */ /*! @{ */ #define ADC_CLPX_CLPX_MASK (0x7FU) #define ADC_CLPX_CLPX_SHIFT (0U) #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_CLPX_SHIFT)) & ADC_CLPX_CLPX_MASK) /*! @} */ /*! @name CLP9 - ADC Plus-Side General Calibration Value Register 9 */ /*! @{ */ #define ADC_CLP9_CLP9_MASK (0x7FU) #define ADC_CLP9_CLP9_SHIFT (0U) #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_CLP9_SHIFT)) & ADC_CLP9_CLP9_MASK) /*! @} */ /*! @name CLPS_OFS - ADC General Calibration Offset Value Register S */ /*! @{ */ #define ADC_CLPS_OFS_CLPS_OFS_MASK (0xFU) #define ADC_CLPS_OFS_CLPS_OFS_SHIFT (0U) /*! CLPS_OFS - CLPS Offset */ #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_OFS_CLPS_OFS_SHIFT)) & ADC_CLPS_OFS_CLPS_OFS_MASK) /*! @} */ /*! @name CLP3_OFS - ADC Plus-Side General Calibration Offset Value Register 3 */ /*! @{ */ #define ADC_CLP3_OFS_CLP3_OFS_MASK (0xFU) #define ADC_CLP3_OFS_CLP3_OFS_SHIFT (0U) /*! CLP3_OFS - CLP3 Offset */ #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_OFS_CLP3_OFS_SHIFT)) & ADC_CLP3_OFS_CLP3_OFS_MASK) /*! @} */ /*! @name CLP2_OFS - ADC Plus-Side General Calibration Offset Value Register 2 */ /*! @{ */ #define ADC_CLP2_OFS_CLP2_OFS_MASK (0xFU) #define ADC_CLP2_OFS_CLP2_OFS_SHIFT (0U) /*! CLP2_OFS - CLP2 Offset */ #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_OFS_CLP2_OFS_SHIFT)) & ADC_CLP2_OFS_CLP2_OFS_MASK) /*! @} */ /*! @name CLP1_OFS - ADC Plus-Side General Calibration Offset Value Register 1 */ /*! @{ */ #define ADC_CLP1_OFS_CLP1_OFS_MASK (0xFU) #define ADC_CLP1_OFS_CLP1_OFS_SHIFT (0U) /*! CLP1_OFS - CLP1 Offset */ #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_OFS_CLP1_OFS_SHIFT)) & ADC_CLP1_OFS_CLP1_OFS_MASK) /*! @} */ /*! @name CLP0_OFS - ADC Plus-Side General Calibration Offset Value Register 0 */ /*! @{ */ #define ADC_CLP0_OFS_CLP0_OFS_MASK (0xFU) #define ADC_CLP0_OFS_CLP0_OFS_SHIFT (0U) /*! CLP0_OFS - CLP0 Offset */ #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_OFS_CLP0_OFS_SHIFT)) & ADC_CLP0_OFS_CLP0_OFS_MASK) /*! @} */ /*! @name CLPX_OFS - ADC Plus-Side General Calibration Offset Value Register X */ /*! @{ */ #define ADC_CLPX_OFS_CLPX_OFS_MASK (0xFFFU) #define ADC_CLPX_OFS_CLPX_OFS_SHIFT (0U) /*! CLPX_OFS - CLPX Offset */ #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_OFS_CLPX_OFS_SHIFT)) & ADC_CLPX_OFS_CLPX_OFS_MASK) /*! @} */ /*! @name CLP9_OFS - ADC Plus-Side General Calibration Offset Value Register 9 */ /*! @{ */ #define ADC_CLP9_OFS_CLP9_OFS_MASK (0xFFFU) #define ADC_CLP9_OFS_CLP9_OFS_SHIFT (0U) /*! CLP9_OFS - CLP9 Offset */ #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_OFS_CLP9_OFS_SHIFT)) & ADC_CLP9_OFS_CLP9_OFS_MASK) /*! @} */ /*! * @} */ /* end of group ADC_Register_Masks */ /* ADC - Peripheral instance base addresses */ /** Peripheral ADC0 base address */ #define ADC0_BASE (0x4003B000u) /** Peripheral ADC0 base pointer */ #define ADC0 ((ADC_Type *)ADC0_BASE) /** Peripheral ADC1 base address */ #define ADC1_BASE (0x40027000u) /** Peripheral ADC1 base pointer */ #define ADC1 ((ADC_Type *)ADC1_BASE) /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC0, ADC1 } /** Interrupt vectors for the ADC peripheral type */ #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } /*! * @} */ /* end of group ADC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CMP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer * @{ */ /** CMP - Register Layout Typedef */ typedef struct { __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ __IO uint32_t C1; /**< CMP Control Register 1, offset: 0x4 */ __IO uint32_t C2; /**< CMP Control Register 2, offset: 0x8 */ } CMP_Type; /* ---------------------------------------------------------------------------- -- CMP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Register_Masks CMP Register Masks * @{ */ /*! @name C0 - CMP Control Register 0 */ /*! @{ */ #define CMP_C0_HYSTCTR_MASK (0x3U) #define CMP_C0_HYSTCTR_SHIFT (0U) /*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level * 0b00..The hard block output has level 0 hysteresis internally. * 0b01..The hard block output has level 1 hysteresis internally. * 0b10..The hard block output has level 2 hysteresis internally. * 0b11..The hard block output has level 3 hysteresis internally. */ #define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK) #define CMP_C0_OFFSET_MASK (0x4U) #define CMP_C0_OFFSET_SHIFT (2U) /*! OFFSET - Comparator hard block offset control. See chip data sheet to get the actual offset value with each level * 0b0..The comparator hard block output has level 0 offset internally. * 0b1..The comparator hard block output has level 1 offset internally. */ #define CMP_C0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OFFSET_SHIFT)) & CMP_C0_OFFSET_MASK) #define CMP_C0_FILTER_CNT_MASK (0x70U) #define CMP_C0_FILTER_CNT_SHIFT (4U) /*! FILTER_CNT - Filter Sample Count * 0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. * 0b001..1 consecutive sample must agree (comparator output is simply sampled). * 0b010..2 consecutive samples must agree. * 0b011..3 consecutive samples must agree. * 0b100..4 consecutive samples must agree. * 0b101..5 consecutive samples must agree. * 0b110..6 consecutive samples must agree. * 0b111..7 consecutive samples must agree. */ #define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK) #define CMP_C0_EN_MASK (0x100U) #define CMP_C0_EN_SHIFT (8U) /*! EN - Comparator Module Enable * 0b0..Analog Comparator is disabled. * 0b1..Analog Comparator is enabled. */ #define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK) #define CMP_C0_OPE_MASK (0x200U) #define CMP_C0_OPE_SHIFT (9U) /*! OPE - Comparator Output Pin Enable * 0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. * 0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin. */ #define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK) #define CMP_C0_COS_MASK (0x400U) #define CMP_C0_COS_SHIFT (10U) /*! COS - Comparator Output Select * 0b0..Set CMPO to equal COUT (filtered comparator output). * 0b1..Set CMPO to equal COUTA (unfiltered comparator output). */ #define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK) #define CMP_C0_INVT_MASK (0x800U) #define CMP_C0_INVT_SHIFT (11U) /*! INVT - Comparator invert * 0b0..Does not invert the comparator output. * 0b1..Inverts the comparator output. */ #define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK) #define CMP_C0_PMODE_MASK (0x1000U) #define CMP_C0_PMODE_SHIFT (12U) /*! PMODE - Power Mode Select * 0b0..Low Speed (LS) comparison mode is selected. * 0b1..High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode. */ #define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK) #define CMP_C0_WE_MASK (0x4000U) #define CMP_C0_WE_SHIFT (14U) /*! WE - Windowing Enable * 0b0..Windowing mode is not selected. * 0b1..Windowing mode is selected. */ #define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK) #define CMP_C0_SE_MASK (0x8000U) #define CMP_C0_SE_SHIFT (15U) /*! SE - Sample Enable * 0b0..Sampling mode is not selected. * 0b1..Sampling mode is selected. */ #define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK) #define CMP_C0_FPR_MASK (0xFF0000U) #define CMP_C0_FPR_SHIFT (16U) /*! FPR - Filter Sample Period */ #define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK) #define CMP_C0_COUT_MASK (0x1000000U) #define CMP_C0_COUT_SHIFT (24U) /*! COUT - Analog Comparator Output */ #define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK) #define CMP_C0_CFF_MASK (0x2000000U) #define CMP_C0_CFF_SHIFT (25U) /*! CFF - Analog Comparator Flag Falling * 0b0..A falling edge has not been detected on COUT. * 0b1..A falling edge on COUT has occurred. */ #define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK) #define CMP_C0_CFR_MASK (0x4000000U) #define CMP_C0_CFR_SHIFT (26U) /*! CFR - Analog Comparator Flag Rising * 0b0..A rising edge has not been detected on COUT. * 0b1..A rising edge on COUT has occurred. */ #define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK) #define CMP_C0_IEF_MASK (0x8000000U) #define CMP_C0_IEF_SHIFT (27U) /*! IEF - Comparator Interrupt Enable Falling * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK) #define CMP_C0_IER_MASK (0x10000000U) #define CMP_C0_IER_SHIFT (28U) /*! IER - Comparator Interrupt Enable Rising * 0b0..Interrupt is disabled. * 0b1..Interrupt is enabled. */ #define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK) #define CMP_C0_DMAEN_MASK (0x40000000U) #define CMP_C0_DMAEN_SHIFT (30U) /*! DMAEN - DMA Enable * 0b0..DMA is disabled. * 0b1..DMA is enabled. */ #define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK) /*! @} */ /*! @name C1 - CMP Control Register 1 */ /*! @{ */ #define CMP_C1_VOSEL_MASK (0xFFU) #define CMP_C1_VOSEL_SHIFT (0U) /*! VOSEL - DAC Output Voltage Select */ #define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK) #define CMP_C1_MSEL_MASK (0x700U) #define CMP_C1_MSEL_SHIFT (8U) /*! MSEL - Minus Input MUX Control * 0b000..IN0 * 0b001..IN1 * 0b010..IN2 * 0b011..IN3 * 0b100..IN4 * 0b101..IN5 * 0b110..IN6 * 0b111..IN7 */ #define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK) #define CMP_C1_PSEL_MASK (0x3800U) #define CMP_C1_PSEL_SHIFT (11U) /*! PSEL - Plus Input MUX Control * 0b000..IN0 * 0b001..IN1 * 0b010..IN2 * 0b011..IN3 * 0b100..IN4 * 0b101..IN5 * 0b110..IN6 * 0b111..IN7 */ #define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK) #define CMP_C1_VRSEL_MASK (0x4000U) #define CMP_C1_VRSEL_SHIFT (14U) /*! VRSEL - Supply Voltage Reference Source Select * 0b0..Vin1 is selected as resistor ladder network supply reference Vin. * 0b1..Vin2 is selected as resistor ladder network supply reference Vin. */ #define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK) #define CMP_C1_DACEN_MASK (0x8000U) #define CMP_C1_DACEN_SHIFT (15U) /*! DACEN - DAC Enable * 0b0..DAC is disabled. * 0b1..DAC is enabled. */ #define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK) #define CMP_C1_CHN0_MASK (0x10000U) #define CMP_C1_CHN0_SHIFT (16U) /*! CHN0 - Channel 0 input enable */ #define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK) #define CMP_C1_CHN1_MASK (0x20000U) #define CMP_C1_CHN1_SHIFT (17U) /*! CHN1 - Channel 1 input enable */ #define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK) #define CMP_C1_CHN2_MASK (0x40000U) #define CMP_C1_CHN2_SHIFT (18U) /*! CHN2 - Channel 2 input enable */ #define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK) #define CMP_C1_CHN3_MASK (0x80000U) #define CMP_C1_CHN3_SHIFT (19U) /*! CHN3 - Channel 3 input enable */ #define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK) #define CMP_C1_CHN4_MASK (0x100000U) #define CMP_C1_CHN4_SHIFT (20U) /*! CHN4 - Channel 4 input enable */ #define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK) #define CMP_C1_CHN5_MASK (0x200000U) #define CMP_C1_CHN5_SHIFT (21U) /*! CHN5 - Channel 5 input enable */ #define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK) #define CMP_C1_CHN6_MASK (0x400000U) #define CMP_C1_CHN6_SHIFT (22U) /*! CHN6 - Channel 6 input enable */ #define CMP_C1_CHN6(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN6_SHIFT)) & CMP_C1_CHN6_MASK) #define CMP_C1_CHN7_MASK (0x800000U) #define CMP_C1_CHN7_SHIFT (23U) /*! CHN7 - Channel 7 input enable */ #define CMP_C1_CHN7(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN7_SHIFT)) & CMP_C1_CHN7_MASK) #define CMP_C1_INNSEL_MASK (0x3000000U) #define CMP_C1_INNSEL_SHIFT (24U) /*! INNSEL - Selection of the input to the negative port of the comparator * 0b00..IN0, from the 8-bit DAC output * 0b01..IN1, from the analog 8-1 mux * 0b10..Reserved * 0b11..Reserved */ #define CMP_C1_INNSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_INNSEL_SHIFT)) & CMP_C1_INNSEL_MASK) #define CMP_C1_INPSEL_MASK (0x18000000U) #define CMP_C1_INPSEL_SHIFT (27U) /*! INPSEL - Selection of the input to the positive port of the comparator * 0b00..IN0, from the 8-bit DAC output * 0b01..IN1, from the analog 8-1 mux * 0b10..Reserved * 0b11..Reserved */ #define CMP_C1_INPSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK) #define CMP_C1_DACOE_MASK (0x20000000U) #define CMP_C1_DACOE_SHIFT (29U) /*! DACOE - DAC output Enable * 0b0..DAC output is disabled to go outside. * 0b1..DAC output is enabled to go outside. */ #define CMP_C1_DACOE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACOE_SHIFT)) & CMP_C1_DACOE_MASK) /*! @} */ /*! @name C2 - CMP Control Register 2 */ /*! @{ */ #define CMP_C2_ACOn_MASK (0xFFU) #define CMP_C2_ACOn_SHIFT (0U) #define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK) #define CMP_C2_INITMOD_MASK (0x3F00U) #define CMP_C2_INITMOD_SHIFT (8U) /*! INITMOD - Comparator and DAC initialization delay modulus. * 0b000000..The modulus is set to 64(same with 111111). */ #define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK) #define CMP_C2_NSAM_MASK (0xC000U) #define CMP_C2_NSAM_SHIFT (14U) /*! NSAM - Number of sample clocks * 0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. * 0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock. * 0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock. * 0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock. */ #define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK) #define CMP_C2_CH0F_MASK (0x10000U) #define CMP_C2_CH0F_SHIFT (16U) #define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK) #define CMP_C2_CH1F_MASK (0x20000U) #define CMP_C2_CH1F_SHIFT (17U) #define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK) #define CMP_C2_CH2F_MASK (0x40000U) #define CMP_C2_CH2F_SHIFT (18U) #define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK) #define CMP_C2_CH3F_MASK (0x80000U) #define CMP_C2_CH3F_SHIFT (19U) #define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK) #define CMP_C2_CH4F_MASK (0x100000U) #define CMP_C2_CH4F_SHIFT (20U) #define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK) #define CMP_C2_CH5F_MASK (0x200000U) #define CMP_C2_CH5F_SHIFT (21U) #define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK) #define CMP_C2_CH6F_MASK (0x400000U) #define CMP_C2_CH6F_SHIFT (22U) #define CMP_C2_CH6F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH6F_SHIFT)) & CMP_C2_CH6F_MASK) #define CMP_C2_CH7F_MASK (0x800000U) #define CMP_C2_CH7F_SHIFT (23U) #define CMP_C2_CH7F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH7F_SHIFT)) & CMP_C2_CH7F_MASK) #define CMP_C2_FXMXCH_MASK (0xE000000U) #define CMP_C2_FXMXCH_SHIFT (25U) /*! FXMXCH - Fixed channel selection * 0b000..Channel 0 is selected as the fixed reference input for the fixed mux port. * 0b001..Channel 1 is selected as the fixed reference input for the fixed mux port. * 0b010..Channel 2 is selected as the fixed reference input for the fixed mux port. * 0b011..Channel 3 is selected as the fixed reference input for the fixed mux port. * 0b100..Channel 4 is selected as the fixed reference input for the fixed mux port. * 0b101..Channel 5 is selected as the fixed reference input for the fixed mux port. * 0b110..Channel 6 is selected as the fixed reference input for the fixed mux port. * 0b111..Channel 7 is selected as the fixed reference input for the fixed mux port. */ #define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK) #define CMP_C2_FXMP_MASK (0x20000000U) #define CMP_C2_FXMP_SHIFT (29U) /*! FXMP - Fixed MUX Port * 0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round. * 0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round. */ #define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK) #define CMP_C2_RRIE_MASK (0x40000000U) #define CMP_C2_RRIE_SHIFT (30U) /*! RRIE - Round-Robin interrupt enable * 0b0..The round-robin interrupt is disabled. * 0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample. */ #define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK) #define CMP_C2_RRE_MASK (0x80000000U) #define CMP_C2_RRE_SHIFT (31U) /*! RRE - Round-Robin Enable * 0b0..Round-robin operation is disabled. * 0b1..Round-robin operation is enabled. */ #define CMP_C2_RRE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRE_SHIFT)) & CMP_C2_RRE_MASK) /*! @} */ /*! * @} */ /* end of group CMP_Register_Masks */ /* CMP - Peripheral instance base addresses */ /** Peripheral CMP0 base address */ #define CMP0_BASE (0x40073000u) /** Peripheral CMP0 base pointer */ #define CMP0 ((CMP_Type *)CMP0_BASE) /** Peripheral CMP1 base address */ #define CMP1_BASE (0x40074000u) /** Peripheral CMP1 base pointer */ #define CMP1 ((CMP_Type *)CMP1_BASE) /** Array initializer of CMP peripheral base addresses */ #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } /** Array initializer of CMP peripheral base pointers */ #define CMP_BASE_PTRS { CMP0, CMP1 } /** Interrupt vectors for the CMP peripheral type */ #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn } /*! * @} */ /* end of group CMP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer * @{ */ /** CRC - Register Layout Typedef */ typedef struct { union { /* offset: 0x0 */ struct { /* offset: 0x0 */ __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ } ACCESS8BIT; struct { /* offset: 0x0 */ __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ } ACCESS16BIT; __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ }; union { /* offset: 0x4 */ struct { /* offset: 0x4 */ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ } GPOLY_ACCESS8BIT; struct { /* offset: 0x4 */ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ } GPOLY_ACCESS16BIT; __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ }; union { /* offset: 0x8 */ struct { /* offset: 0x8 */ uint8_t RESERVED_0[3]; __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ } CTRL_ACCESS8BIT; __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ }; } CRC_Type; /* ---------------------------------------------------------------------------- -- CRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CRC_Register_Masks CRC Register Masks * @{ */ /*! @name DATALL - CRC_DATALL register. */ /*! @{ */ #define CRC_DATALL_DATALL_MASK (0xFFU) #define CRC_DATALL_DATALL_SHIFT (0U) /*! DATALL - CRCLL stores the first 8 bits of the 32 bit DATA */ #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) /*! @} */ /*! @name DATALU - CRC_DATALU register. */ /*! @{ */ #define CRC_DATALU_DATALU_MASK (0xFFU) #define CRC_DATALU_DATALU_SHIFT (0U) /*! DATALU - DATALL stores the second 8 bits of the 32 bit CRC */ #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) /*! @} */ /*! @name DATAHL - CRC_DATAHL register. */ /*! @{ */ #define CRC_DATAHL_DATAHL_MASK (0xFFU) #define CRC_DATAHL_DATAHL_SHIFT (0U) /*! DATAHL - DATAHL stores the third 8 bits of the 32 bit CRC */ #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) /*! @} */ /*! @name DATAHU - CRC_DATAHU register. */ /*! @{ */ #define CRC_DATAHU_DATAHU_MASK (0xFFU) #define CRC_DATAHU_DATAHU_SHIFT (0U) /*! DATAHU - DATAHU stores the fourth 8 bits of the 32 bit CRC */ #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) /*! @} */ /*! @name DATAL - CRC_DATAL register. */ /*! @{ */ #define CRC_DATAL_DATAL_MASK (0xFFFFU) #define CRC_DATAL_DATAL_SHIFT (0U) /*! DATAL - DATAL stores the lower 16 bits of the 16/32 bit CRC */ #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) /*! @} */ /*! @name DATAH - CRC_DATAH register. */ /*! @{ */ #define CRC_DATAH_DATAH_MASK (0xFFFFU) #define CRC_DATAH_DATAH_SHIFT (0U) /*! DATAH - DATAH stores the high 16 bits of the 16/32 bit CRC */ #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) /*! @} */ /*! @name DATA - CRC Data register */ /*! @{ */ #define CRC_DATA_LL_MASK (0xFFU) #define CRC_DATA_LL_SHIFT (0U) /*! LL - CRC Low Lower Byte */ #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) #define CRC_DATA_LU_MASK (0xFF00U) #define CRC_DATA_LU_SHIFT (8U) /*! LU - CRC Low Upper Byte */ #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) #define CRC_DATA_HL_MASK (0xFF0000U) #define CRC_DATA_HL_SHIFT (16U) /*! HL - CRC High Lower Byte */ #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) #define CRC_DATA_HU_MASK (0xFF000000U) #define CRC_DATA_HU_SHIFT (24U) /*! HU - CRC High Upper Byte */ #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) /*! @} */ /*! @name GPOLYLL - CRC_GPOLYLL register. */ /*! @{ */ #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) /*! GPOLYLL - POLYLL stores the first 8 bits of the 32 bit CRC */ #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) /*! @} */ /*! @name GPOLYLU - CRC_GPOLYLU register. */ /*! @{ */ #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) /*! GPOLYLU - POLYLL stores the second 8 bits of the 32 bit CRC */ #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) /*! @} */ /*! @name GPOLYHL - CRC_GPOLYHL register. */ /*! @{ */ #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) /*! GPOLYHL - POLYHL stores the third 8 bits of the 32 bit CRC */ #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) /*! @} */ /*! @name GPOLYHU - CRC_GPOLYHU register. */ /*! @{ */ #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) /*! GPOLYHU - POLYHU stores the fourth 8 bits of the 32 bit CRC */ #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) /*! @} */ /*! @name GPOLYL - CRC_GPOLYL register. */ /*! @{ */ #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) #define CRC_GPOLYL_GPOLYL_SHIFT (0U) /*! GPOLYL - POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value */ #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) /*! @} */ /*! @name GPOLYH - CRC_GPOLYH register. */ /*! @{ */ #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) #define CRC_GPOLYH_GPOLYH_SHIFT (0U) /*! GPOLYH - POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value */ #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) /*! @} */ /*! @name GPOLY - CRC Polynomial register */ /*! @{ */ #define CRC_GPOLY_LOW_MASK (0xFFFFU) #define CRC_GPOLY_LOW_SHIFT (0U) /*! LOW - Low Polynominal Half-word */ #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) #define CRC_GPOLY_HIGH_SHIFT (16U) /*! HIGH - High Polynominal Half-word */ #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) /*! @} */ /*! @name CTRLHU - CRC_CTRLHU register. */ /*! @{ */ #define CRC_CTRLHU_TCRC_MASK (0x1U) #define CRC_CTRLHU_TCRC_SHIFT (0U) /*! TCRC * 0b0..16-bit CRC protocol. * 0b1..32-bit CRC protocol. */ #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) #define CRC_CTRLHU_WAS_MASK (0x2U) #define CRC_CTRLHU_WAS_SHIFT (1U) /*! WAS * 0b0..Writes to CRC data register are data values. * 0b1..Writes to CRC data reguster are seed values. */ #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) #define CRC_CTRLHU_FXOR_MASK (0x4U) #define CRC_CTRLHU_FXOR_SHIFT (2U) /*! FXOR * 0b0..No XOR on reading. * 0b1..Invert or complement the read value of CRC data register. */ #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) #define CRC_CTRLHU_TOTR_MASK (0x30U) #define CRC_CTRLHU_TOTR_SHIFT (4U) /*! TOTR * 0b00..No Transposition. * 0b01..Bits in bytes are transposed, bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed; no bits in a byte are transposed. */ #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) #define CRC_CTRLHU_TOT_MASK (0xC0U) #define CRC_CTRLHU_TOT_SHIFT (6U) /*! TOT * 0b00..No Transposition. * 0b01..Bits in bytes are transposed, bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed; no bits in a byte are transposed. */ #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) /*! @} */ /*! @name CTRL - CRC Control register */ /*! @{ */ #define CRC_CTRL_TCRC_MASK (0x1000000U) #define CRC_CTRL_TCRC_SHIFT (24U) /*! TCRC * 0b0..16-bit CRC protocol. * 0b1..32-bit CRC protocol. */ #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) #define CRC_CTRL_WAS_MASK (0x2000000U) #define CRC_CTRL_WAS_SHIFT (25U) /*! WAS - Write CRC Data Register As Seed * 0b0..Writes to the CRC data register are data values. * 0b1..Writes to the CRC data register are seed values. */ #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) #define CRC_CTRL_FXOR_MASK (0x4000000U) #define CRC_CTRL_FXOR_SHIFT (26U) /*! FXOR - Complement Read Of CRC Data Register * 0b0..No XOR on reading. * 0b1..Invert or complement the read value of the CRC Data register. */ #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) #define CRC_CTRL_TOTR_MASK (0x30000000U) #define CRC_CTRL_TOTR_SHIFT (28U) /*! TOTR - Type Of Transpose For Read * 0b00..No transposition. * 0b01..Bits in bytes are transposed; bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed; no bits in a byte are transposed. */ #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) #define CRC_CTRL_TOT_MASK (0xC0000000U) #define CRC_CTRL_TOT_SHIFT (30U) /*! TOT - Type Of Transpose For Writes * 0b00..No transposition. * 0b01..Bits in bytes are transposed; bytes are not transposed. * 0b10..Both bits in bytes and bytes are transposed. * 0b11..Only bytes are transposed; no bits in a byte are transposed. */ #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) /*! @} */ /*! * @} */ /* end of group CRC_Register_Masks */ /* CRC - Peripheral instance base addresses */ /** Peripheral CRC base address */ #define CRC_BASE (0x40032000u) /** Peripheral CRC base pointer */ #define CRC0 ((CRC_Type *)CRC_BASE) /** Array initializer of CRC peripheral base addresses */ #define CRC_BASE_ADDRS { CRC_BASE } /** Array initializer of CRC peripheral base pointers */ #define CRC_BASE_PTRS { CRC0 } /*! * @} */ /* end of group CRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer * @{ */ /** DMA - Register Layout Typedef */ typedef struct { __IO uint32_t CR; /**< Control Register, offset: 0x0 */ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ uint8_t RESERVED_1[4]; __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ uint8_t RESERVED_2[4]; __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ uint8_t RESERVED_3[4]; __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ uint8_t RESERVED_4[4]; __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ uint8_t RESERVED_5[12]; __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ uint8_t RESERVED_6[184]; __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ uint8_t RESERVED_7[3832]; struct { /* offset: 0x1000, array step: 0x20 */ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ union { /* offset: 0x1008, array step: 0x20 */ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ }; __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ union { /* offset: 0x1016, array step: 0x20 */ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ }; __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ union { /* offset: 0x101E, array step: 0x20 */ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ }; } TCD[8]; } DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /*! @name CR - Control Register */ /*! @{ */ #define DMA_CR_EDBG_MASK (0x2U) #define DMA_CR_EDBG_SHIFT (1U) /*! EDBG - Enable Debug * 0b0..When in debug mode, the DMA continues to operate. * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to * complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. */ #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) #define DMA_CR_ERCA_MASK (0x4U) #define DMA_CR_ERCA_SHIFT (2U) /*! ERCA - Enable Round Robin Channel Arbitration * 0b0..Fixed priority arbitration is used for channel selection . * 0b1..Round robin arbitration is used for channel selection . */ #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) #define DMA_CR_HOE_MASK (0x10U) #define DMA_CR_HOE_SHIFT (4U) /*! HOE - Halt On Error * 0b0..Normal operation * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. */ #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) #define DMA_CR_HALT_MASK (0x20U) #define DMA_CR_HALT_SHIFT (5U) /*! HALT - Halt DMA Operations * 0b0..Normal operation * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. */ #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) #define DMA_CR_CLM_MASK (0x40U) #define DMA_CR_CLM_SHIFT (6U) /*! CLM - Continuous Link Mode * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated * again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel * link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the * next minor loop. */ #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) #define DMA_CR_EMLM_MASK (0x80U) #define DMA_CR_EMLM_SHIFT (7U) /*! EMLM - Enable Minor Loop Mapping * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES * field. The individual enable fields allow the minor loop offset to be applied to the source address, the * destination address, or both. The NBYTES field is reduced when either offset is enabled. */ #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) #define DMA_CR_ECX_MASK (0x10000U) #define DMA_CR_ECX_SHIFT (16U) /*! ECX - Error Cancel Transfer * 0b0..Normal operation * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and * force the minor loop to finish. The cancel takes effect after the last write of the current read/write * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an * optional error interrupt. */ #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) #define DMA_CR_CX_MASK (0x20000U) #define DMA_CR_CX_SHIFT (17U) /*! CX - Cancel Transfer * 0b0..Normal operation * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. */ #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) #define DMA_CR_ACTIVE_MASK (0x80000000U) #define DMA_CR_ACTIVE_SHIFT (31U) /*! ACTIVE - DMA Active Status * 0b0..eDMA is idle. * 0b1..eDMA is executing a channel. */ #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) /*! @} */ /*! @name ES - Error Status Register */ /*! @{ */ #define DMA_ES_DBE_MASK (0x1U) #define DMA_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No destination bus error * 0b1..The last recorded error was a bus error on a destination write */ #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) #define DMA_ES_SBE_MASK (0x2U) #define DMA_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No source bus error * 0b1..The last recorded error was a bus error on a source read */ #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) #define DMA_ES_SGE_MASK (0x4U) #define DMA_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No scatter/gather configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. */ #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) #define DMA_ES_NCE_MASK (0x8U) #define DMA_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] */ #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) #define DMA_ES_DOE_MASK (0x10U) #define DMA_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No destination offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) #define DMA_ES_DAE_MASK (0x20U) #define DMA_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No destination address configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) #define DMA_ES_SOE_MASK (0x40U) #define DMA_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No source offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) #define DMA_ES_SAE_MASK (0x80U) #define DMA_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No source address configuration error. * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) #define DMA_ES_ERRCHN_MASK (0x700U) #define DMA_ES_ERRCHN_SHIFT (8U) /*! ERRCHN - Error Channel Number or Canceled Channel Number */ #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) #define DMA_ES_CPE_MASK (0x4000U) #define DMA_ES_CPE_SHIFT (14U) /*! CPE - Channel Priority Error * 0b0..No channel priority error * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. */ #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) #define DMA_ES_ECX_MASK (0x10000U) #define DMA_ES_ECX_SHIFT (16U) /*! ECX - Transfer Canceled * 0b0..No canceled transfers * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input */ #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) #define DMA_ES_VLD_MASK (0x80000000U) #define DMA_ES_VLD_SHIFT (31U) /*! VLD * 0b0..No ERR bits are set. * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. */ #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) /*! @} */ /*! @name ERQ - Enable Request Register */ /*! @{ */ #define DMA_ERQ_ERQ0_MASK (0x1U) #define DMA_ERQ_ERQ0_SHIFT (0U) /*! ERQ0 - Enable DMA Request 0 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) #define DMA_ERQ_ERQ1_MASK (0x2U) #define DMA_ERQ_ERQ1_SHIFT (1U) /*! ERQ1 - Enable DMA Request 1 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) #define DMA_ERQ_ERQ2_MASK (0x4U) #define DMA_ERQ_ERQ2_SHIFT (2U) /*! ERQ2 - Enable DMA Request 2 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) #define DMA_ERQ_ERQ3_MASK (0x8U) #define DMA_ERQ_ERQ3_SHIFT (3U) /*! ERQ3 - Enable DMA Request 3 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) #define DMA_ERQ_ERQ4_MASK (0x10U) #define DMA_ERQ_ERQ4_SHIFT (4U) /*! ERQ4 - Enable DMA Request 4 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) #define DMA_ERQ_ERQ5_MASK (0x20U) #define DMA_ERQ_ERQ5_SHIFT (5U) /*! ERQ5 - Enable DMA Request 5 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) #define DMA_ERQ_ERQ6_MASK (0x40U) #define DMA_ERQ_ERQ6_SHIFT (6U) /*! ERQ6 - Enable DMA Request 6 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) #define DMA_ERQ_ERQ7_MASK (0x80U) #define DMA_ERQ_ERQ7_SHIFT (7U) /*! ERQ7 - Enable DMA Request 7 * 0b0..The DMA request signal for the corresponding channel is disabled * 0b1..The DMA request signal for the corresponding channel is enabled */ #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) /*! @} */ /*! @name EEI - Enable Error Interrupt Register */ /*! @{ */ #define DMA_EEI_EEI0_MASK (0x1U) #define DMA_EEI_EEI0_SHIFT (0U) /*! EEI0 - Enable Error Interrupt 0 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) #define DMA_EEI_EEI1_MASK (0x2U) #define DMA_EEI_EEI1_SHIFT (1U) /*! EEI1 - Enable Error Interrupt 1 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) #define DMA_EEI_EEI2_MASK (0x4U) #define DMA_EEI_EEI2_SHIFT (2U) /*! EEI2 - Enable Error Interrupt 2 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) #define DMA_EEI_EEI3_MASK (0x8U) #define DMA_EEI_EEI3_SHIFT (3U) /*! EEI3 - Enable Error Interrupt 3 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) #define DMA_EEI_EEI4_MASK (0x10U) #define DMA_EEI_EEI4_SHIFT (4U) /*! EEI4 - Enable Error Interrupt 4 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) #define DMA_EEI_EEI5_MASK (0x20U) #define DMA_EEI_EEI5_SHIFT (5U) /*! EEI5 - Enable Error Interrupt 5 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) #define DMA_EEI_EEI6_MASK (0x40U) #define DMA_EEI_EEI6_SHIFT (6U) /*! EEI6 - Enable Error Interrupt 6 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) #define DMA_EEI_EEI7_MASK (0x80U) #define DMA_EEI_EEI7_SHIFT (7U) /*! EEI7 - Enable Error Interrupt 7 * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) /*! @} */ /*! @name CEEI - Clear Enable Error Interrupt Register */ /*! @{ */ #define DMA_CEEI_CEEI_MASK (0x7U) #define DMA_CEEI_CEEI_SHIFT (0U) /*! CEEI - Clear Enable Error Interrupt */ #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) #define DMA_CEEI_CAEE_MASK (0x40U) #define DMA_CEEI_CAEE_SHIFT (6U) /*! CAEE - Clear All Enable Error Interrupts * 0b0..Clear only the EEI bit specified in the CEEI field * 0b1..Clear all bits in EEI */ #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) #define DMA_CEEI_NOP_MASK (0x80U) #define DMA_CEEI_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) /*! @} */ /*! @name SEEI - Set Enable Error Interrupt Register */ /*! @{ */ #define DMA_SEEI_SEEI_MASK (0x7U) #define DMA_SEEI_SEEI_SHIFT (0U) /*! SEEI - Set Enable Error Interrupt */ #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) #define DMA_SEEI_SAEE_MASK (0x40U) #define DMA_SEEI_SAEE_SHIFT (6U) /*! SAEE - Sets All Enable Error Interrupts * 0b0..Set only the EEI bit specified in the SEEI field. * 0b1..Sets all bits in EEI */ #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) #define DMA_SEEI_NOP_MASK (0x80U) #define DMA_SEEI_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) /*! @} */ /*! @name CERQ - Clear Enable Request Register */ /*! @{ */ #define DMA_CERQ_CERQ_MASK (0x7U) #define DMA_CERQ_CERQ_SHIFT (0U) /*! CERQ - Clear Enable Request */ #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) #define DMA_CERQ_CAER_MASK (0x40U) #define DMA_CERQ_CAER_SHIFT (6U) /*! CAER - Clear All Enable Requests * 0b0..Clear only the ERQ bit specified in the CERQ field * 0b1..Clear all bits in ERQ */ #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) #define DMA_CERQ_NOP_MASK (0x80U) #define DMA_CERQ_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) /*! @} */ /*! @name SERQ - Set Enable Request Register */ /*! @{ */ #define DMA_SERQ_SERQ_MASK (0x7U) #define DMA_SERQ_SERQ_SHIFT (0U) /*! SERQ - Set Enable Request */ #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) #define DMA_SERQ_SAER_MASK (0x40U) #define DMA_SERQ_SAER_SHIFT (6U) /*! SAER - Set All Enable Requests * 0b0..Set only the ERQ bit specified in the SERQ field * 0b1..Set all bits in ERQ */ #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) #define DMA_SERQ_NOP_MASK (0x80U) #define DMA_SERQ_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) /*! @} */ /*! @name CDNE - Clear DONE Status Bit Register */ /*! @{ */ #define DMA_CDNE_CDNE_MASK (0x7U) #define DMA_CDNE_CDNE_SHIFT (0U) /*! CDNE - Clear DONE Bit */ #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) #define DMA_CDNE_CADN_MASK (0x40U) #define DMA_CDNE_CADN_SHIFT (6U) /*! CADN - Clears All DONE Bits * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field * 0b1..Clears all bits in TCDn_CSR[DONE] */ #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) #define DMA_CDNE_NOP_MASK (0x80U) #define DMA_CDNE_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) /*! @} */ /*! @name SSRT - Set START Bit Register */ /*! @{ */ #define DMA_SSRT_SSRT_MASK (0x7U) #define DMA_SSRT_SSRT_SHIFT (0U) /*! SSRT - Set START Bit */ #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) #define DMA_SSRT_SAST_MASK (0x40U) #define DMA_SSRT_SAST_SHIFT (6U) /*! SAST - Set All START Bits (activates all channels) * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field * 0b1..Set all bits in TCDn_CSR[START] */ #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) #define DMA_SSRT_NOP_MASK (0x80U) #define DMA_SSRT_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) /*! @} */ /*! @name CERR - Clear Error Register */ /*! @{ */ #define DMA_CERR_CERR_MASK (0x7U) #define DMA_CERR_CERR_SHIFT (0U) /*! CERR - Clear Error Indicator */ #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) #define DMA_CERR_CAEI_MASK (0x40U) #define DMA_CERR_CAEI_SHIFT (6U) /*! CAEI - Clear All Error Indicators * 0b0..Clear only the ERR bit specified in the CERR field * 0b1..Clear all bits in ERR */ #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) #define DMA_CERR_NOP_MASK (0x80U) #define DMA_CERR_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) /*! @} */ /*! @name CINT - Clear Interrupt Request Register */ /*! @{ */ #define DMA_CINT_CINT_MASK (0x7U) #define DMA_CINT_CINT_SHIFT (0U) /*! CINT - Clear Interrupt Request */ #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) #define DMA_CINT_CAIR_MASK (0x40U) #define DMA_CINT_CAIR_SHIFT (6U) /*! CAIR - Clear All Interrupt Requests * 0b0..Clear only the INT bit specified in the CINT field * 0b1..Clear all bits in INT */ #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) #define DMA_CINT_NOP_MASK (0x80U) #define DMA_CINT_NOP_SHIFT (7U) /*! NOP - No Op enable * 0b0..Normal operation * 0b1..No operation, ignore the other bits in this register */ #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) /*! @} */ /*! @name INT - Interrupt Request Register */ /*! @{ */ #define DMA_INT_INT0_MASK (0x1U) #define DMA_INT_INT0_SHIFT (0U) /*! INT0 - Interrupt Request 0 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) #define DMA_INT_INT1_MASK (0x2U) #define DMA_INT_INT1_SHIFT (1U) /*! INT1 - Interrupt Request 1 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) #define DMA_INT_INT2_MASK (0x4U) #define DMA_INT_INT2_SHIFT (2U) /*! INT2 - Interrupt Request 2 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) #define DMA_INT_INT3_MASK (0x8U) #define DMA_INT_INT3_SHIFT (3U) /*! INT3 - Interrupt Request 3 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) #define DMA_INT_INT4_MASK (0x10U) #define DMA_INT_INT4_SHIFT (4U) /*! INT4 - Interrupt Request 4 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) #define DMA_INT_INT5_MASK (0x20U) #define DMA_INT_INT5_SHIFT (5U) /*! INT5 - Interrupt Request 5 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) #define DMA_INT_INT6_MASK (0x40U) #define DMA_INT_INT6_SHIFT (6U) /*! INT6 - Interrupt Request 6 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) #define DMA_INT_INT7_MASK (0x80U) #define DMA_INT_INT7_SHIFT (7U) /*! INT7 - Interrupt Request 7 * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) /*! @} */ /*! @name ERR - Error Register */ /*! @{ */ #define DMA_ERR_ERR0_MASK (0x1U) #define DMA_ERR_ERR0_SHIFT (0U) /*! ERR0 - Error In Channel 0 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) #define DMA_ERR_ERR1_MASK (0x2U) #define DMA_ERR_ERR1_SHIFT (1U) /*! ERR1 - Error In Channel 1 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) #define DMA_ERR_ERR2_MASK (0x4U) #define DMA_ERR_ERR2_SHIFT (2U) /*! ERR2 - Error In Channel 2 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) #define DMA_ERR_ERR3_MASK (0x8U) #define DMA_ERR_ERR3_SHIFT (3U) /*! ERR3 - Error In Channel 3 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) #define DMA_ERR_ERR4_MASK (0x10U) #define DMA_ERR_ERR4_SHIFT (4U) /*! ERR4 - Error In Channel 4 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) #define DMA_ERR_ERR5_MASK (0x20U) #define DMA_ERR_ERR5_SHIFT (5U) /*! ERR5 - Error In Channel 5 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) #define DMA_ERR_ERR6_MASK (0x40U) #define DMA_ERR_ERR6_SHIFT (6U) /*! ERR6 - Error In Channel 6 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) #define DMA_ERR_ERR7_MASK (0x80U) #define DMA_ERR_ERR7_SHIFT (7U) /*! ERR7 - Error In Channel 7 * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) /*! @} */ /*! @name HRS - Hardware Request Status Register */ /*! @{ */ #define DMA_HRS_HRS0_MASK (0x1U) #define DMA_HRS_HRS0_SHIFT (0U) /*! HRS0 - Hardware Request Status Channel 0 * 0b0..A hardware service request for channel 0 is not present * 0b1..A hardware service request for channel 0 is present */ #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) #define DMA_HRS_HRS1_MASK (0x2U) #define DMA_HRS_HRS1_SHIFT (1U) /*! HRS1 - Hardware Request Status Channel 1 * 0b0..A hardware service request for channel 1 is not present * 0b1..A hardware service request for channel 1 is present */ #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) #define DMA_HRS_HRS2_MASK (0x4U) #define DMA_HRS_HRS2_SHIFT (2U) /*! HRS2 - Hardware Request Status Channel 2 * 0b0..A hardware service request for channel 2 is not present * 0b1..A hardware service request for channel 2 is present */ #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) #define DMA_HRS_HRS3_MASK (0x8U) #define DMA_HRS_HRS3_SHIFT (3U) /*! HRS3 - Hardware Request Status Channel 3 * 0b0..A hardware service request for channel 3 is not present * 0b1..A hardware service request for channel 3 is present */ #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) #define DMA_HRS_HRS4_MASK (0x10U) #define DMA_HRS_HRS4_SHIFT (4U) /*! HRS4 - Hardware Request Status Channel 4 * 0b0..A hardware service request for channel 4 is not present * 0b1..A hardware service request for channel 4 is present */ #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) #define DMA_HRS_HRS5_MASK (0x20U) #define DMA_HRS_HRS5_SHIFT (5U) /*! HRS5 - Hardware Request Status Channel 5 * 0b0..A hardware service request for channel 5 is not present * 0b1..A hardware service request for channel 5 is present */ #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) #define DMA_HRS_HRS6_MASK (0x40U) #define DMA_HRS_HRS6_SHIFT (6U) /*! HRS6 - Hardware Request Status Channel 6 * 0b0..A hardware service request for channel 6 is not present * 0b1..A hardware service request for channel 6 is present */ #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) #define DMA_HRS_HRS7_MASK (0x80U) #define DMA_HRS_HRS7_SHIFT (7U) /*! HRS7 - Hardware Request Status Channel 7 * 0b0..A hardware service request for channel 7 is not present * 0b1..A hardware service request for channel 7 is present */ #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) /*! @} */ /*! @name EARS - Enable Asynchronous Request in Stop Register */ /*! @{ */ #define DMA_EARS_EDREQ_0_MASK (0x1U) #define DMA_EARS_EDREQ_0_SHIFT (0U) /*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. * 0b0..Disable asynchronous DMA request for channel 0. * 0b1..Enable asynchronous DMA request for channel 0. */ #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) #define DMA_EARS_EDREQ_1_MASK (0x2U) #define DMA_EARS_EDREQ_1_SHIFT (1U) /*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. * 0b0..Disable asynchronous DMA request for channel 1 * 0b1..Enable asynchronous DMA request for channel 1. */ #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) #define DMA_EARS_EDREQ_2_MASK (0x4U) #define DMA_EARS_EDREQ_2_SHIFT (2U) /*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. * 0b0..Disable asynchronous DMA request for channel 2. * 0b1..Enable asynchronous DMA request for channel 2. */ #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) #define DMA_EARS_EDREQ_3_MASK (0x8U) #define DMA_EARS_EDREQ_3_SHIFT (3U) /*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. * 0b0..Disable asynchronous DMA request for channel 3. * 0b1..Enable asynchronous DMA request for channel 3. */ #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) #define DMA_EARS_EDREQ_4_MASK (0x10U) #define DMA_EARS_EDREQ_4_SHIFT (4U) /*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 * 0b0..Disable asynchronous DMA request for channel 4. * 0b1..Enable asynchronous DMA request for channel 4. */ #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) #define DMA_EARS_EDREQ_5_MASK (0x20U) #define DMA_EARS_EDREQ_5_SHIFT (5U) /*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 * 0b0..Disable asynchronous DMA request for channel 5. * 0b1..Enable asynchronous DMA request for channel 5. */ #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) #define DMA_EARS_EDREQ_6_MASK (0x40U) #define DMA_EARS_EDREQ_6_SHIFT (6U) /*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 * 0b0..Disable asynchronous DMA request for channel 6. * 0b1..Enable asynchronous DMA request for channel 6. */ #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) #define DMA_EARS_EDREQ_7_MASK (0x80U) #define DMA_EARS_EDREQ_7_SHIFT (7U) /*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 * 0b0..Disable asynchronous DMA request for channel 7. * 0b1..Enable asynchronous DMA request for channel 7. */ #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) /*! @} */ /*! @name DCHPRI3 - Channel n Priority Register */ /*! @{ */ #define DMA_DCHPRI3_CHPRI_MASK (0x7U) #define DMA_DCHPRI3_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) #define DMA_DCHPRI3_DPA_MASK (0x40U) #define DMA_DCHPRI3_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) #define DMA_DCHPRI3_ECP_MASK (0x80U) #define DMA_DCHPRI3_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) /*! @} */ /*! @name DCHPRI2 - Channel n Priority Register */ /*! @{ */ #define DMA_DCHPRI2_CHPRI_MASK (0x7U) #define DMA_DCHPRI2_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) #define DMA_DCHPRI2_DPA_MASK (0x40U) #define DMA_DCHPRI2_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) #define DMA_DCHPRI2_ECP_MASK (0x80U) #define DMA_DCHPRI2_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) /*! @} */ /*! @name DCHPRI1 - Channel n Priority Register */ /*! @{ */ #define DMA_DCHPRI1_CHPRI_MASK (0x7U) #define DMA_DCHPRI1_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) #define DMA_DCHPRI1_DPA_MASK (0x40U) #define DMA_DCHPRI1_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) #define DMA_DCHPRI1_ECP_MASK (0x80U) #define DMA_DCHPRI1_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) /*! @} */ /*! @name DCHPRI0 - Channel n Priority Register */ /*! @{ */ #define DMA_DCHPRI0_CHPRI_MASK (0x7U) #define DMA_DCHPRI0_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) #define DMA_DCHPRI0_DPA_MASK (0x40U) #define DMA_DCHPRI0_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) #define DMA_DCHPRI0_ECP_MASK (0x80U) #define DMA_DCHPRI0_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) /*! @} */ /*! @name DCHPRI7 - Channel n Priority Register */ /*! @{ */ #define DMA_DCHPRI7_CHPRI_MASK (0x7U) #define DMA_DCHPRI7_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) #define DMA_DCHPRI7_DPA_MASK (0x40U) #define DMA_DCHPRI7_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) #define DMA_DCHPRI7_ECP_MASK (0x80U) #define DMA_DCHPRI7_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) /*! @} */ /*! @name DCHPRI6 - Channel n Priority Register */ /*! @{ */ #define DMA_DCHPRI6_CHPRI_MASK (0x7U) #define DMA_DCHPRI6_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) #define DMA_DCHPRI6_DPA_MASK (0x40U) #define DMA_DCHPRI6_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) #define DMA_DCHPRI6_ECP_MASK (0x80U) #define DMA_DCHPRI6_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) /*! @} */ /*! @name DCHPRI5 - Channel n Priority Register */ /*! @{ */ #define DMA_DCHPRI5_CHPRI_MASK (0x7U) #define DMA_DCHPRI5_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) #define DMA_DCHPRI5_DPA_MASK (0x40U) #define DMA_DCHPRI5_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) #define DMA_DCHPRI5_ECP_MASK (0x80U) #define DMA_DCHPRI5_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) /*! @} */ /*! @name DCHPRI4 - Channel n Priority Register */ /*! @{ */ #define DMA_DCHPRI4_CHPRI_MASK (0x7U) #define DMA_DCHPRI4_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) #define DMA_DCHPRI4_DPA_MASK (0x40U) #define DMA_DCHPRI4_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. * 0b0..Channel n can suspend a lower priority channel. * 0b1..Channel n cannot suspend any channel, regardless of channel priority. */ #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) #define DMA_DCHPRI4_ECP_MASK (0x80U) #define DMA_DCHPRI4_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. * 0b0..Channel n cannot be suspended by a higher priority channel's service request. * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) /*! @} */ /*! @name SADDR - TCD Source Address */ /*! @{ */ #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_SADDR_SADDR_SHIFT (0U) /*! SADDR - Source Address */ #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) /*! @} */ /* The count of DMA_SADDR */ #define DMA_SADDR_COUNT (8U) /*! @name SOFF - TCD Signed Source Address Offset */ /*! @{ */ #define DMA_SOFF_SOFF_MASK (0xFFFFU) #define DMA_SOFF_SOFF_SHIFT (0U) /*! SOFF - Source address signed offset */ #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) /*! @} */ /* The count of DMA_SOFF */ #define DMA_SOFF_COUNT (8U) /*! @name ATTR - TCD Transfer Attributes */ /*! @{ */ #define DMA_ATTR_DSIZE_MASK (0x7U) #define DMA_ATTR_DSIZE_SHIFT (0U) /*! DSIZE - Destination data transfer size */ #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) #define DMA_ATTR_DMOD_MASK (0xF8U) #define DMA_ATTR_DMOD_SHIFT (3U) /*! DMOD - Destination Address Modulo */ #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) #define DMA_ATTR_SSIZE_MASK (0x700U) #define DMA_ATTR_SSIZE_SHIFT (8U) /*! SSIZE - Source data transfer size * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit * 0b011..Reserved * 0b100..16-byte * 0b101..32-byte * 0b110..Reserved * 0b111..Reserved */ #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) #define DMA_ATTR_SMOD_MASK (0xF800U) #define DMA_ATTR_SMOD_SHIFT (11U) /*! SMOD - Source Address Modulo * 0b00000..Source address modulo feature is disabled */ #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) /*! @} */ /* The count of DMA_ATTR */ #define DMA_ATTR_COUNT (8U) /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ /*! @{ */ #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) /*! NBYTES - Minor Byte Transfer Count */ #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) /*! @} */ /* The count of DMA_NBYTES_MLNO */ #define DMA_NBYTES_MLNO_COUNT (8U) /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ /*! @{ */ #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) /*! NBYTES - Minor Byte Transfer Count */ #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset enable * 0b0..The minor loop offset is not applied to the DADDR * 0b1..The minor loop offset is applied to the DADDR */ #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the SADDR * 0b1..The minor loop offset is applied to the SADDR */ #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) /*! @} */ /* The count of DMA_NBYTES_MLOFFNO */ #define DMA_NBYTES_MLOFFNO_COUNT (8U) /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ /*! @{ */ #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) /*! NBYTES - Minor Byte Transfer Count */ #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) /*! MLOFF - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the * source or destination address to form the next-state value after the minor loop completes. */ #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset enable * 0b0..The minor loop offset is not applied to the DADDR * 0b1..The minor loop offset is applied to the DADDR */ #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the SADDR * 0b1..The minor loop offset is applied to the SADDR */ #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) /*! @} */ /* The count of DMA_NBYTES_MLOFFYES */ #define DMA_NBYTES_MLOFFYES_COUNT (8U) /*! @name SLAST - TCD Last Source Address Adjustment */ /*! @{ */ #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) #define DMA_SLAST_SLAST_SHIFT (0U) /*! SLAST - Last Source Address Adjustment */ #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) /*! @} */ /* The count of DMA_SLAST */ #define DMA_SLAST_COUNT (8U) /*! @name DADDR - TCD Destination Address */ /*! @{ */ #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_DADDR_DADDR_SHIFT (0U) /*! DADDR - Destination Address */ #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) /*! @} */ /* The count of DMA_DADDR */ #define DMA_DADDR_COUNT (8U) /*! @name DOFF - TCD Signed Destination Address Offset */ /*! @{ */ #define DMA_DOFF_DOFF_MASK (0xFFFFU) #define DMA_DOFF_DOFF_SHIFT (0U) /*! DOFF - Destination Address Signed Offset */ #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) /*! @} */ /* The count of DMA_DOFF */ #define DMA_DOFF_COUNT (8U) /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ /*! @{ */ #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_CITER_ELINKNO */ #define DMA_CITER_ELINKNO_COUNT (8U) /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ /*! @{ */ #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) #define DMA_CITER_ELINKYES_LINKCH_MASK (0xE00U) #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Minor Loop Link Channel Number */ #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_CITER_ELINKYES */ #define DMA_CITER_ELINKYES_COUNT (8U) /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ /*! @{ */ #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) /*! @} */ /* The count of DMA_DLAST_SGA */ #define DMA_DLAST_SGA_COUNT (8U) /*! @name CSR - TCD Control and Status */ /*! @{ */ #define DMA_CSR_START_MASK (0x1U) #define DMA_CSR_START_SHIFT (0U) /*! START - Channel Start * 0b0..The channel is not explicitly started. * 0b1..The channel is explicitly started via a software initiated service request. */ #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) #define DMA_CSR_INTMAJOR_MASK (0x2U) #define DMA_CSR_INTMAJOR_SHIFT (1U) /*! INTMAJOR - Enable an interrupt when major iteration count completes. * 0b0..The end-of-major loop interrupt is disabled. * 0b1..The end-of-major loop interrupt is enabled. */ #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) #define DMA_CSR_INTHALF_MASK (0x4U) #define DMA_CSR_INTHALF_SHIFT (2U) /*! INTHALF - Enable an interrupt when major counter is half complete. * 0b0..The half-point interrupt is disabled. * 0b1..The half-point interrupt is enabled. */ #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) #define DMA_CSR_DREQ_MASK (0x8U) #define DMA_CSR_DREQ_SHIFT (3U) /*! DREQ - Disable Request * 0b0..The channel's ERQ bit is not affected. * 0b1..The channel's ERQ bit is cleared when the major loop is complete. */ #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) #define DMA_CSR_ESG_MASK (0x10U) #define DMA_CSR_ESG_SHIFT (4U) /*! ESG - Enable Scatter/Gather Processing * 0b0..The current channel's TCD is normal format. * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer * to the next TCD to be loaded into this channel after the major loop completes its execution. */ #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) #define DMA_CSR_MAJORELINK_MASK (0x20U) #define DMA_CSR_MAJORELINK_SHIFT (5U) /*! MAJORELINK - Enable channel-to-channel linking on major loop complete * 0b0..The channel-to-channel linking is disabled. * 0b1..The channel-to-channel linking is enabled. */ #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) #define DMA_CSR_ACTIVE_MASK (0x40U) #define DMA_CSR_ACTIVE_SHIFT (6U) /*! ACTIVE - Channel Active */ #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) #define DMA_CSR_DONE_MASK (0x80U) #define DMA_CSR_DONE_SHIFT (7U) /*! DONE - Channel Done */ #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) #define DMA_CSR_MAJORLINKCH_MASK (0x700U) #define DMA_CSR_MAJORLINKCH_SHIFT (8U) /*! MAJORLINKCH - Major Loop Link Channel Number */ #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) #define DMA_CSR_BWC_MASK (0xC000U) #define DMA_CSR_BWC_SHIFT (14U) /*! BWC - Bandwidth Control * 0b00..No eDMA engine stalls. * 0b01..Reserved * 0b10..eDMA engine stalls for 4 cycles after each R/W. * 0b11..eDMA engine stalls for 8 cycles after each R/W. */ #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) /*! @} */ /* The count of DMA_CSR */ #define DMA_CSR_COUNT (8U) /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ /*! @{ */ #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) /*! BITER - Starting Major Iteration Count */ #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_BITER_ELINKNO */ #define DMA_BITER_ELINKNO_COUNT (8U) /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ /*! @{ */ #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) /*! BITER - Starting major iteration count */ #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) #define DMA_BITER_ELINKYES_LINKCH_MASK (0xE00U) #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Link Channel Number */ #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_BITER_ELINKYES */ #define DMA_BITER_ELINKYES_COUNT (8U) /*! * @} */ /* end of group DMA_Register_Masks */ /* DMA - Peripheral instance base addresses */ /** Peripheral DMA base address */ #define DMA_BASE (0x40008000u) /** Peripheral DMA base pointer */ #define DMA0 ((DMA_Type *)DMA_BASE) /** Array initializer of DMA peripheral base addresses */ #define DMA_BASE_ADDRS { DMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { DMA0 } /** Interrupt vectors for the DMA peripheral type */ #define DMA_CHN_IRQS { { DMA0_04_IRQn, DMA0_15_IRQn, DMA0_26_IRQn, DMA0_37_IRQn, DMA0_04_IRQn, DMA0_15_IRQn, DMA0_26_IRQn, DMA0_37_IRQn } } #define DMA_ERROR_IRQS { DMA_Error_IRQn } /*! * @} */ /* end of group DMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMAMUX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer * @{ */ /** DMAMUX - Register Layout Typedef */ typedef struct { __IO uint8_t CHCFG[8]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ } DMAMUX_Type; /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks * @{ */ /*! @name CHCFG - Channel Configuration register */ /*! @{ */ #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) /*! SOURCE - DMA Channel Source (Slot) * 0b000000..Disable_Signal * 0b000001..TSI_Signal * 0b000010..LPUART0_Rx_Signal * 0b000011..LPUART0_Tx_Signal * 0b000100..LPUART1_Rx_Signal * 0b000101..LPUART1_Tx_Signal * 0b000110..LPUART2_Rx_Signal * 0b000111..LPUART2_Tx_Signal * 0b001010..FlexIO_Channel0_Signal * 0b001011..FlexIO_Channel1_Signal * 0b001100..FlexIO_Channel2_Signal * 0b001101..FlexIO_Channel3_Signal * 0b001110..LPSPI0_Rx_Signal * 0b001111..LPSPI0_Tx_Signal * 0b010000..LPSPI1_Rx_Signal * 0b010001..LPSPI1_Tx_Signal * 0b010010..LPI2C0_Rx_Signal * 0b010011..LPI2C0_Tx_Signal * 0b010100..FTM0_Channel0_Signal * 0b010101..FTM0_Channel1_Signal * 0b010110..FTM0_Channel2_Signal * 0b010111..FTM0_Channel3_Signal * 0b011000..FTM0_Channel4_Signal * 0b011001..FTM0_Channel5_Signal * 0b011010..FTM0_Channel6_Signal * 0b011011..FTM0_Channel7_Signal * 0b011100..FTM1_Channel0_Signal * 0b011101..FTM1_Channel1_Signal * 0b011110..FTM2_Channel0_Signal * 0b011111..FTM2_Channel1_Signal * 0b100000..LPI2C1_Rx_Signal * 0b100001..LPI2C1_Tx_Signal * 0b101000..ADC0_Signal * 0b101001..ADC1_Signal * 0b101011..CMP0_Signal * 0b101100..CMP1_Signal * 0b101110..PDB0_Signal * 0b110001..PortA_Signal * 0b110010..PortB_Signal * 0b110011..PortC_Signal * 0b110100..PortD_Signal * 0b110101..PortE_Signal * 0b111001..FTM1_Channel2_Signal * 0b111010..FTM2_Channel2_Signal * 0b111011..LPTMR0_Signal * 0b111100..AlwaysOn60_Signal * 0b111101..AlwaysOn61_Signal * 0b111110..AlwaysOn62_Signal * 0b111111..AlwaysOn63_Signal */ #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) #define DMAMUX_CHCFG_TRIG_MASK (0x40U) #define DMAMUX_CHCFG_TRIG_SHIFT (6U) /*! TRIG - DMA Channel Trigger Enable * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the * specified source to the DMA channel. (Normal mode) * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. */ #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) #define DMAMUX_CHCFG_ENBL_MASK (0x80U) #define DMAMUX_CHCFG_ENBL_SHIFT (7U) /*! ENBL - DMA Channel Enable * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has * separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. * 0b1..DMA channel is enabled */ #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) /*! @} */ /* The count of DMAMUX_CHCFG */ #define DMAMUX_CHCFG_COUNT (8U) /*! * @} */ /* end of group DMAMUX_Register_Masks */ /* DMAMUX - Peripheral instance base addresses */ /** Peripheral DMAMUX base address */ #define DMAMUX_BASE (0x40021000u) /** Peripheral DMAMUX base pointer */ #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) /** Array initializer of DMAMUX peripheral base addresses */ #define DMAMUX_BASE_ADDRS { DMAMUX_BASE } /** Array initializer of DMAMUX peripheral base pointers */ #define DMAMUX_BASE_PTRS { DMAMUX } /*! * @} */ /* end of group DMAMUX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- EWM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer * @{ */ /** EWM - Register Layout Typedef */ typedef struct { __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ __O uint8_t SERV; /**< Service Register, offset: 0x1 */ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ uint8_t RESERVED_0[1]; __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ } EWM_Type; /* ---------------------------------------------------------------------------- -- EWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EWM_Register_Masks EWM Register Masks * @{ */ /*! @name CTRL - Control Register */ /*! @{ */ #define EWM_CTRL_EWMEN_MASK (0x1U) #define EWM_CTRL_EWMEN_SHIFT (0U) /*! EWMEN - EWM enable. */ #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) #define EWM_CTRL_ASSIN_MASK (0x2U) #define EWM_CTRL_ASSIN_SHIFT (1U) /*! ASSIN - EWM_in's Assertion State Select. */ #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) #define EWM_CTRL_INEN_MASK (0x4U) #define EWM_CTRL_INEN_SHIFT (2U) /*! INEN - Input Enable. */ #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) #define EWM_CTRL_INTEN_MASK (0x8U) #define EWM_CTRL_INTEN_SHIFT (3U) /*! INTEN - Interrupt Enable. */ #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) /*! @} */ /*! @name SERV - Service Register */ /*! @{ */ #define EWM_SERV_SERVICE_MASK (0xFFU) #define EWM_SERV_SERVICE_SHIFT (0U) #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) /*! @} */ /*! @name CMPL - Compare Low Register */ /*! @{ */ #define EWM_CMPL_COMPAREL_MASK (0xFFU) #define EWM_CMPL_COMPAREL_SHIFT (0U) #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) /*! @} */ /*! @name CMPH - Compare High Register */ /*! @{ */ #define EWM_CMPH_COMPAREH_MASK (0xFFU) #define EWM_CMPH_COMPAREH_SHIFT (0U) #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) /*! @} */ /*! @name CLKPRESCALER - Clock Prescaler Register */ /*! @{ */ #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) /*! @} */ /*! * @} */ /* end of group EWM_Register_Masks */ /* EWM - Peripheral instance base addresses */ /** Peripheral EWM base address */ #define EWM_BASE (0x40061000u) /** Peripheral EWM base pointer */ #define EWM ((EWM_Type *)EWM_BASE) /** Array initializer of EWM peripheral base addresses */ #define EWM_BASE_ADDRS { EWM_BASE } /** Array initializer of EWM peripheral base pointers */ #define EWM_BASE_PTRS { EWM } /** Interrupt vectors for the EWM peripheral type */ #define EWM_IRQS { WDOG_EWM_IRQn } /*! * @} */ /* end of group EWM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FGPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer * @{ */ /** FGPIO - Register Layout Typedef */ typedef struct { __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ } FGPIO_Type; /* ---------------------------------------------------------------------------- -- FGPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FGPIO_Register_Masks FGPIO Register Masks * @{ */ /*! @name PDOR - Port Data Output Register */ /*! @{ */ #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) #define FGPIO_PDOR_PDO_SHIFT (0U) /*! PDO - Port Data Output * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. */ #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) /*! @} */ /*! @name PSOR - Port Set Output Register */ /*! @{ */ #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) #define FGPIO_PSOR_PTSO_SHIFT (0U) /*! PTSO - Port Set Output * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. */ #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) /*! @} */ /*! @name PCOR - Port Clear Output Register */ /*! @{ */ #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) #define FGPIO_PCOR_PTCO_SHIFT (0U) /*! PTCO - Port Clear Output * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. */ #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) /*! @} */ /*! @name PTOR - Port Toggle Output Register */ /*! @{ */ #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) #define FGPIO_PTOR_PTTO_SHIFT (0U) /*! PTTO - Port Toggle Output * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. */ #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) /*! @} */ /*! @name PDIR - Port Data Input Register */ /*! @{ */ #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) #define FGPIO_PDIR_PDI_SHIFT (0U) /*! PDI - Port Data Input * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. * 0b00000000000000000000000000000001..Pin logic level is logic 1. */ #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) /*! @} */ /*! @name PDDR - Port Data Direction Register */ /*! @{ */ #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) #define FGPIO_PDDR_PDD_SHIFT (0U) /*! PDD - Port Data Direction * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. */ #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) /*! @} */ /*! * @} */ /* end of group FGPIO_Register_Masks */ /* FGPIO - Peripheral instance base addresses */ /** Peripheral FGPIOA base address */ #define FGPIOA_BASE (0xF8000000u) /** Peripheral FGPIOA base pointer */ #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) /** Peripheral FGPIOB base address */ #define FGPIOB_BASE (0xF8000040u) /** Peripheral FGPIOB base pointer */ #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) /** Peripheral FGPIOC base address */ #define FGPIOC_BASE (0xF8000080u) /** Peripheral FGPIOC base pointer */ #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE) /** Peripheral FGPIOD base address */ #define FGPIOD_BASE (0xF80000C0u) /** Peripheral FGPIOD base pointer */ #define FGPIOD ((FGPIO_Type *)FGPIOD_BASE) /** Peripheral FGPIOE base address */ #define FGPIOE_BASE (0xF8000100u) /** Peripheral FGPIOE base pointer */ #define FGPIOE ((FGPIO_Type *)FGPIOE_BASE) /** Array initializer of FGPIO peripheral base addresses */ #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE } /** Array initializer of FGPIO peripheral base pointers */ #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE } /*! * @} */ /* end of group FGPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FLEXIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer * @{ */ /** FLEXIO - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ uint8_t RESERVED_2[76]; __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_3[112]; __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_4[240]; __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_5[112]; __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ uint8_t RESERVED_6[112]; __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ uint8_t RESERVED_7[112]; __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ uint8_t RESERVED_8[112]; __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ uint8_t RESERVED_9[112]; __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ uint8_t RESERVED_10[112]; __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ } FLEXIO_Type; /* ---------------------------------------------------------------------------- -- FLEXIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) #define FLEXIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard features implemented. * 0b0000000000000001..Supports state, logic and parallel modes. */ #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) #define FLEXIO_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) #define FLEXIO_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) /*! SHIFTER - Shifter Number */ #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) #define FLEXIO_PARAM_TIMER_SHIFT (8U) /*! TIMER - Timer Number */ #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) #define FLEXIO_PARAM_PIN_SHIFT (16U) /*! PIN - Pin Number */ #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) /*! TRIGGER - Trigger Number */ #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) /*! @} */ /*! @name CTRL - FlexIO Control Register */ /*! @{ */ #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) /*! FLEXEN - FlexIO Enable * 0b0..FlexIO module is disabled. * 0b1..FlexIO module is enabled. */ #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) #define FLEXIO_CTRL_SWRST_MASK (0x2U) #define FLEXIO_CTRL_SWRST_SHIFT (1U) /*! SWRST - Software Reset * 0b0..Software reset is disabled * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. */ #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) #define FLEXIO_CTRL_FASTACC_MASK (0x4U) #define FLEXIO_CTRL_FASTACC_SHIFT (2U) /*! FASTACC - Fast Access * 0b0..Configures for normal register accesses to FlexIO * 0b1..Configures for fast register accesses to FlexIO */ #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) #define FLEXIO_CTRL_DBGE_SHIFT (30U) /*! DBGE - Debug Enable * 0b0..FlexIO is disabled in debug modes. * 0b1..FlexIO is enabled in debug modes */ #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) #define FLEXIO_CTRL_DOZEN_SHIFT (31U) /*! DOZEN - Doze Enable * 0b0..FlexIO enabled in Doze modes. * 0b1..FlexIO disabled in Doze modes. */ #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) /*! @} */ /*! @name PIN - Pin State Register */ /*! @{ */ #define FLEXIO_PIN_PDI_MASK (0xFFU) #define FLEXIO_PIN_PDI_SHIFT (0U) /*! PDI - Pin Data Input */ #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /*! @} */ /*! @name SHIFTSTAT - Shifter Status Register */ /*! @{ */ #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) /*! SSF - Shifter Status Flag * 0b0000..Status flag is clear * 0b0001..Status flag is set */ #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) /*! @} */ /*! @name SHIFTERR - Shifter Error Register */ /*! @{ */ #define FLEXIO_SHIFTERR_SEF_MASK (0xFU) #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) /*! SEF - Shifter Error Flags * 0b0000..Shifter Error Flag is clear * 0b0001..Shifter Error Flag is set */ #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) /*! @} */ /*! @name TIMSTAT - Timer Status Register */ /*! @{ */ #define FLEXIO_TIMSTAT_TSF_MASK (0xFU) #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) /*! TSF - Timer Status Flags * 0b0000..Timer Status Flag is clear * 0b0001..Timer Status Flag is set */ #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) /*! @} */ /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ /*! @{ */ #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) /*! SSIE - Shifter Status Interrupt Enable * 0b0000..Shifter Status Flag interrupt disabled * 0b0001..Shifter Status Flag interrupt enabled */ #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) /*! @} */ /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ /*! @{ */ #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) /*! SEIE - Shifter Error Interrupt Enable * 0b0000..Shifter Error Flag interrupt disabled * 0b0001..Shifter Error Flag interrupt enabled */ #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) /*! @} */ /*! @name TIMIEN - Timer Interrupt Enable Register */ /*! @{ */ #define FLEXIO_TIMIEN_TEIE_MASK (0xFU) #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) /*! TEIE - Timer Status Interrupt Enable * 0b0000..Timer Status Flag interrupt is disabled * 0b0001..Timer Status Flag interrupt is enabled */ #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) /*! @} */ /*! @name SHIFTSDEN - Shifter Status DMA Enable */ /*! @{ */ #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) /*! SSDE - Shifter Status DMA Enable * 0b0000..Shifter Status Flag DMA request is disabled * 0b0001..Shifter Status Flag DMA request is enabled */ #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) /*! @} */ /*! @name SHIFTCTL - Shifter Control N Register */ /*! @{ */ #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) /*! SMOD - Shifter Mode * 0b000..Disabled. * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. * 0b011..Reserved. * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. * 0b110..Reserved. * 0b111..Reserved. */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) /*! PINPOL - Shifter Pin Polarity * 0b0..Pin is active high * 0b1..Pin is active low */ #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x700U) #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) /*! PINSEL - Shifter Pin Select */ #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) /*! PINCFG - Shifter Pin Configuration * 0b00..Shifter pin output disabled * 0b01..Shifter pin open drain or bidirectional output enable * 0b10..Shifter pin bidirectional output data * 0b11..Shifter pin output */ #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) /*! TIMPOL - Timer Polarity * 0b0..Shift on posedge of Shift clock * 0b1..Shift on negedge of Shift clock */ #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) /*! TIMSEL - Timer Select */ #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) /*! @} */ /* The count of FLEXIO_SHIFTCTL */ #define FLEXIO_SHIFTCTL_COUNT (4U) /*! @name SHIFTCFG - Shifter Configuration N Register */ /*! @{ */ #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) /*! SSTART - Shifter Start bit * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 */ #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) /*! SSTOP - Shifter Stop bit * 0b00..Stop bit disabled for transmitter/receiver/match store * 0b01..Reserved for transmitter/receiver/match store * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 */ #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) /*! INSRC - Input Source * 0b0..Pin * 0b1..Shifter N+1 Output */ #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) /*! @} */ /* The count of FLEXIO_SHIFTCFG */ #define FLEXIO_SHIFTCFG_COUNT (4U) /*! @name SHIFTBUF - Shifter Buffer N Register */ /*! @{ */ #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) /*! SHIFTBUF - Shift Buffer */ #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUF */ #define FLEXIO_SHIFTBUF_COUNT (4U) /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ /*! @{ */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) /*! SHIFTBUFBIS - Shift Buffer */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBIS */ #define FLEXIO_SHIFTBUFBIS_COUNT (4U) /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ /*! @{ */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) /*! SHIFTBUFBYS - Shift Buffer */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBYS */ #define FLEXIO_SHIFTBUFBYS_COUNT (4U) /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ /*! @{ */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) /*! SHIFTBUFBBS - Shift Buffer */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBBS */ #define FLEXIO_SHIFTBUFBBS_COUNT (4U) /*! @name TIMCTL - Timer Control N Register */ /*! @{ */ #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) /*! TIMOD - Timer Mode * 0b00..Timer Disabled. * 0b01..Dual 8-bit counters baud/bit mode. * 0b10..Dual 8-bit counters PWM mode. * 0b11..Single 16-bit counter mode. */ #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) /*! PINPOL - Timer Pin Polarity * 0b0..Pin is active high * 0b1..Pin is active low */ #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) #define FLEXIO_TIMCTL_PINSEL_MASK (0x700U) #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) /*! PINSEL - Timer Pin Select */ #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) /*! PINCFG - Timer Pin Configuration * 0b00..Timer pin output disabled * 0b01..Timer pin open drain or bidirectional output enable * 0b10..Timer pin bidirectional output data * 0b11..Timer pin output */ #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) /*! TRGSRC - Trigger Source * 0b0..External trigger selected * 0b1..Internal trigger selected */ #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) /*! TRGPOL - Trigger Polarity * 0b0..Trigger active high * 0b1..Trigger active low */ #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) #define FLEXIO_TIMCTL_TRGSEL_MASK (0xF000000U) #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) /*! TRGSEL - Trigger Select */ #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /*! @} */ /* The count of FLEXIO_TIMCTL */ #define FLEXIO_TIMCTL_COUNT (4U) /*! @name TIMCFG - Timer Configuration N Register */ /*! @{ */ #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) /*! TSTART - Timer Start Bit * 0b0..Start bit disabled * 0b1..Start bit enabled */ #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) /*! TSTOP - Timer Stop Bit * 0b00..Stop bit disabled * 0b01..Stop bit is enabled on timer compare * 0b10..Stop bit is enabled on timer disable * 0b11..Stop bit is enabled on timer compare and timer disable */ #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) /*! TIMENA - Timer Enable * 0b000..Timer always enabled * 0b001..Timer enabled on Timer N-1 enable * 0b010..Timer enabled on Trigger high * 0b011..Timer enabled on Trigger high and Pin high * 0b100..Timer enabled on Pin rising edge * 0b101..Timer enabled on Pin rising edge and Trigger high * 0b110..Timer enabled on Trigger rising edge * 0b111..Timer enabled on Trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) /*! TIMDIS - Timer Disable * 0b000..Timer never disabled * 0b001..Timer disabled on Timer N-1 disable * 0b010..Timer disabled on Timer compare * 0b011..Timer disabled on Timer compare and Trigger Low * 0b100..Timer disabled on Pin rising or falling edge * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high * 0b110..Timer disabled on Trigger falling edge * 0b111..Reserved */ #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) /*! TIMRST - Timer Reset * 0b000..Timer never reset * 0b001..Reserved * 0b010..Timer reset on Timer Pin equal to Timer Output * 0b011..Timer reset on Timer Trigger equal to Timer Output * 0b100..Timer reset on Timer Pin rising edge * 0b101..Reserved * 0b110..Timer reset on Trigger rising edge * 0b111..Timer reset on Trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) /*! TIMDEC - Timer Decrement * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. */ #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) /*! TIMOUT - Timer Output * 0b00..Timer output is logic one when enabled and is not affected by timer reset * 0b01..Timer output is logic zero when enabled and is not affected by timer reset * 0b10..Timer output is logic one when enabled and on timer reset * 0b11..Timer output is logic zero when enabled and on timer reset */ #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) /*! @} */ /* The count of FLEXIO_TIMCFG */ #define FLEXIO_TIMCFG_COUNT (4U) /*! @name TIMCMP - Timer Compare N Register */ /*! @{ */ #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) #define FLEXIO_TIMCMP_CMP_SHIFT (0U) /*! CMP - Timer Compare Value */ #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) /*! @} */ /* The count of FLEXIO_TIMCMP */ #define FLEXIO_TIMCMP_COUNT (4U) /*! * @} */ /* end of group FLEXIO_Register_Masks */ /* FLEXIO - Peripheral instance base addresses */ /** Peripheral FLEXIO base address */ #define FLEXIO_BASE (0x4005A000u) /** Peripheral FLEXIO base pointer */ #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE) /** Array initializer of FLEXIO peripheral base addresses */ #define FLEXIO_BASE_ADDRS { FLEXIO_BASE } /** Array initializer of FLEXIO peripheral base pointers */ #define FLEXIO_BASE_PTRS { FLEXIO } /** Interrupt vectors for the FLEXIO peripheral type */ #define FLEXIO_IRQS { FLEXIO_IRQn } /*! * @} */ /* end of group FLEXIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FTFE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer * @{ */ /** FTFE - Register Layout Typedef */ typedef struct { __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ uint8_t RESERVED_0[2]; __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */ __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */ __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */ __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */ __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */ __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */ __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */ __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */ __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */ __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */ __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */ __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */ __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */ __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */ __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */ __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */ __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */ uint8_t RESERVED_1[2]; __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */ } FTFE_Type; /* ---------------------------------------------------------------------------- -- FTFE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FTFE_Register_Masks FTFE Register Masks * @{ */ /*! @name FSTAT - Flash Status Register */ /*! @{ */ #define FTFE_FSTAT_MGSTAT0_MASK (0x1U) #define FTFE_FSTAT_MGSTAT0_SHIFT (0U) /*! MGSTAT0 - Memory Controller Command Completion Status Flag */ #define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK) #define FTFE_FSTAT_FPVIOL_MASK (0x10U) #define FTFE_FSTAT_FPVIOL_SHIFT (4U) /*! FPVIOL - Flash Protection Violation Flag * 0b0..No protection violation detected * 0b1..Protection violation detected */ #define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK) #define FTFE_FSTAT_ACCERR_MASK (0x20U) #define FTFE_FSTAT_ACCERR_SHIFT (5U) /*! ACCERR - Flash Access Error Flag * 0b0..No access error detected * 0b1..Access error detected */ #define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK) #define FTFE_FSTAT_RDCOLERR_MASK (0x40U) #define FTFE_FSTAT_RDCOLERR_SHIFT (6U) /*! RDCOLERR - FTFE Read Collision Error Flag * 0b0..No collision error detected * 0b1..Collision error detected */ #define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK) #define FTFE_FSTAT_CCIF_MASK (0x80U) #define FTFE_FSTAT_CCIF_SHIFT (7U) /*! CCIF - Command Complete Interrupt Flag * 0b0..FTFE command or EEPROM file system operation in progress * 0b1..FTFE command or EEPROM file system operation has completed */ #define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK) /*! @} */ /*! @name FCNFG - Flash Configuration Register */ /*! @{ */ #define FTFE_FCNFG_EEERDY_MASK (0x1U) #define FTFE_FCNFG_EEERDY_SHIFT (0U) /*! EEERDY * 0b0..FlexRAM is not available for EEPROM operation * 0b1..FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written * to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the * FlexRAM and EEPROM backup */ #define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK) #define FTFE_FCNFG_RAMRDY_MASK (0x2U) #define FTFE_FCNFG_RAMRDY_SHIFT (1U) /*! RAMRDY - RAM Ready * 0b0..FlexRAM is not available for traditional RAM access * 0b1..FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations */ #define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK) #define FTFE_FCNFG_PFLSH_MASK (0x4U) #define FTFE_FCNFG_PFLSH_SHIFT (2U) /*! PFLSH - FTFE configuration * 0b0..FTFE configuration supports one program flash block and one FlexNVM block * 0b1..Reserved */ #define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK) #define FTFE_FCNFG_ERSSUSP_MASK (0x10U) #define FTFE_FCNFG_ERSSUSP_SHIFT (4U) /*! ERSSUSP - Erase Suspend * 0b0..No suspend requested * 0b1..Suspend the current Erase Flash Sector command execution */ #define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK) #define FTFE_FCNFG_ERSAREQ_MASK (0x20U) #define FTFE_FCNFG_ERSAREQ_SHIFT (5U) /*! ERSAREQ - Erase All Request * 0b0..No request or request complete * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the * Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to * the unsecure state */ #define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK) #define FTFE_FCNFG_RDCOLLIE_MASK (0x40U) #define FTFE_FCNFG_RDCOLLIE_SHIFT (6U) /*! RDCOLLIE - Read Collision Error Interrupt Enable * 0b0..Read collision error interrupt disabled * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision * error is detected (see the description of FSTAT[RDCOLERR]). */ #define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK) #define FTFE_FCNFG_CCIE_MASK (0x80U) #define FTFE_FCNFG_CCIE_SHIFT (7U) /*! CCIE - Command Complete Interrupt Enable * 0b0..Command complete interrupt disabled * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. */ #define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK) /*! @} */ /*! @name FSEC - Flash Security Register */ /*! @{ */ #define FTFE_FSEC_SEC_MASK (0x3U) #define FTFE_FSEC_SEC_SHIFT (0U) /*! SEC - Flash Security * 0b00..MCU security status is secure * 0b01..MCU security status is secure * 0b10..MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.) * 0b11..MCU security status is secure */ #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK) #define FTFE_FSEC_FSLACC_MASK (0xCU) #define FTFE_FSEC_FSLACC_SHIFT (2U) /*! FSLACC - Factory Security Level Access Code * 0b00..Factory access granted * 0b01..Factory access denied * 0b10..Factory access denied * 0b11..Factory access granted */ #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK) #define FTFE_FSEC_MEEN_MASK (0x30U) #define FTFE_FSEC_MEEN_SHIFT (4U) /*! MEEN - Mass Erase Enable Bits * 0b00..Mass erase is enabled * 0b01..Mass erase is enabled * 0b10..Mass erase is disabled * 0b11..Mass erase is enabled */ #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK) #define FTFE_FSEC_KEYEN_MASK (0xC0U) #define FTFE_FSEC_KEYEN_SHIFT (6U) /*! KEYEN - Backdoor Key Security Enable * 0b00..Backdoor key access disabled * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) * 0b10..Backdoor key access enabled * 0b11..Backdoor key access disabled */ #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK) /*! @} */ /*! @name FOPT - Flash Option Register */ /*! @{ */ #define FTFE_FOPT_OPT_MASK (0xFFU) #define FTFE_FOPT_OPT_SHIFT (0U) /*! OPT - Nonvolatile Option */ #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK) /*! @} */ /*! @name FCCOB3 - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOB3_CCOBn_MASK (0xFFU) #define FTFE_FCCOB3_CCOBn_SHIFT (0U) #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK) /*! @} */ /*! @name FCCOB2 - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOB2_CCOBn_MASK (0xFFU) #define FTFE_FCCOB2_CCOBn_SHIFT (0U) #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK) /*! @} */ /*! @name FCCOB1 - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOB1_CCOBn_MASK (0xFFU) #define FTFE_FCCOB1_CCOBn_SHIFT (0U) #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK) /*! @} */ /*! @name FCCOB0 - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOB0_CCOBn_MASK (0xFFU) #define FTFE_FCCOB0_CCOBn_SHIFT (0U) #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK) /*! @} */ /*! @name FCCOB7 - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOB7_CCOBn_MASK (0xFFU) #define FTFE_FCCOB7_CCOBn_SHIFT (0U) #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK) /*! @} */ /*! @name FCCOB6 - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOB6_CCOBn_MASK (0xFFU) #define FTFE_FCCOB6_CCOBn_SHIFT (0U) #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK) /*! @} */ /*! @name FCCOB5 - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOB5_CCOBn_MASK (0xFFU) #define FTFE_FCCOB5_CCOBn_SHIFT (0U) #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK) /*! @} */ /*! @name FCCOB4 - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOB4_CCOBn_MASK (0xFFU) #define FTFE_FCCOB4_CCOBn_SHIFT (0U) #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK) /*! @} */ /*! @name FCCOBB - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOBB_CCOBn_MASK (0xFFU) #define FTFE_FCCOBB_CCOBn_SHIFT (0U) #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK) /*! @} */ /*! @name FCCOBA - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOBA_CCOBn_MASK (0xFFU) #define FTFE_FCCOBA_CCOBn_SHIFT (0U) #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK) /*! @} */ /*! @name FCCOB9 - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOB9_CCOBn_MASK (0xFFU) #define FTFE_FCCOB9_CCOBn_SHIFT (0U) #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK) /*! @} */ /*! @name FCCOB8 - Flash Common Command Object Registers */ /*! @{ */ #define FTFE_FCCOB8_CCOBn_MASK (0xFFU) #define FTFE_FCCOB8_CCOBn_SHIFT (0U) #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK) /*! @} */ /*! @name FPROT3 - Program Flash Protection Registers */ /*! @{ */ #define FTFE_FPROT3_PROT_MASK (0xFFU) #define FTFE_FPROT3_PROT_SHIFT (0U) /*! PROT - Program Flash Region Protect * 0b00000000..Program flash region is protected. * 0b00000001..Program flash region is not protected */ #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK) /*! @} */ /*! @name FPROT2 - Program Flash Protection Registers */ /*! @{ */ #define FTFE_FPROT2_PROT_MASK (0xFFU) #define FTFE_FPROT2_PROT_SHIFT (0U) /*! PROT - Program Flash Region Protect * 0b00000000..Program flash region is protected. * 0b00000001..Program flash region is not protected */ #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK) /*! @} */ /*! @name FPROT1 - Program Flash Protection Registers */ /*! @{ */ #define FTFE_FPROT1_PROT_MASK (0xFFU) #define FTFE_FPROT1_PROT_SHIFT (0U) /*! PROT - Program Flash Region Protect * 0b00000000..Program flash region is protected. * 0b00000001..Program flash region is not protected */ #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK) /*! @} */ /*! @name FPROT0 - Program Flash Protection Registers */ /*! @{ */ #define FTFE_FPROT0_PROT_MASK (0xFFU) #define FTFE_FPROT0_PROT_SHIFT (0U) /*! PROT - Program Flash Region Protect * 0b00000000..Program flash region is protected. * 0b00000001..Program flash region is not protected */ #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK) /*! @} */ /*! @name FEPROT - EEPROM Protection Register */ /*! @{ */ #define FTFE_FEPROT_EPROT_MASK (0xFFU) #define FTFE_FEPROT_EPROT_SHIFT (0U) /*! EPROT - EEPROM Region Protect * 0b00000000..EEPROM region is protected * 0b00000001..EEPROM region is not protected */ #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK) /*! @} */ /*! @name FDPROT - Data Flash Protection Register */ /*! @{ */ #define FTFE_FDPROT_DPROT_MASK (0xFFU) #define FTFE_FDPROT_DPROT_SHIFT (0U) /*! DPROT - Data Flash Region Protect * 0b00000000..Data Flash region is protected * 0b00000001..Data Flash region is not protected */ #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK) /*! @} */ /*! @name XACCH3 - Execute-only Access Registers */ /*! @{ */ #define FTFE_XACCH3_XA_MASK (0xFFU) #define FTFE_XACCH3_XA_SHIFT (0U) /*! XA - Execute-only access control * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) * 0b00000001..Associated segment is accessible as data or in execute mode */ #define FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK) /*! @} */ /*! @name XACCH2 - Execute-only Access Registers */ /*! @{ */ #define FTFE_XACCH2_XA_MASK (0xFFU) #define FTFE_XACCH2_XA_SHIFT (0U) /*! XA - Execute-only access control * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) * 0b00000001..Associated segment is accessible as data or in execute mode */ #define FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK) /*! @} */ /*! @name XACCH1 - Execute-only Access Registers */ /*! @{ */ #define FTFE_XACCH1_XA_MASK (0xFFU) #define FTFE_XACCH1_XA_SHIFT (0U) /*! XA - Execute-only access control * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) * 0b00000001..Associated segment is accessible as data or in execute mode */ #define FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK) /*! @} */ /*! @name XACCH0 - Execute-only Access Registers */ /*! @{ */ #define FTFE_XACCH0_XA_MASK (0xFFU) #define FTFE_XACCH0_XA_SHIFT (0U) /*! XA - Execute-only access control * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) * 0b00000001..Associated segment is accessible as data or in execute mode */ #define FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK) /*! @} */ /*! @name XACCL3 - Execute-only Access Registers */ /*! @{ */ #define FTFE_XACCL3_XA_MASK (0xFFU) #define FTFE_XACCL3_XA_SHIFT (0U) /*! XA - Execute-only access control * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) * 0b00000001..Associated segment is accessible as data or in execute mode */ #define FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK) /*! @} */ /*! @name XACCL2 - Execute-only Access Registers */ /*! @{ */ #define FTFE_XACCL2_XA_MASK (0xFFU) #define FTFE_XACCL2_XA_SHIFT (0U) /*! XA - Execute-only access control * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) * 0b00000001..Associated segment is accessible as data or in execute mode */ #define FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK) /*! @} */ /*! @name XACCL1 - Execute-only Access Registers */ /*! @{ */ #define FTFE_XACCL1_XA_MASK (0xFFU) #define FTFE_XACCL1_XA_SHIFT (0U) /*! XA - Execute-only access control * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) * 0b00000001..Associated segment is accessible as data or in execute mode */ #define FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK) /*! @} */ /*! @name XACCL0 - Execute-only Access Registers */ /*! @{ */ #define FTFE_XACCL0_XA_MASK (0xFFU) #define FTFE_XACCL0_XA_SHIFT (0U) /*! XA - Execute-only access control * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) * 0b00000001..Associated segment is accessible as data or in execute mode */ #define FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK) /*! @} */ /*! @name SACCH3 - Supervisor-only Access Registers */ /*! @{ */ #define FTFE_SACCH3_SA_MASK (0xFFU) #define FTFE_SACCH3_SA_SHIFT (0U) /*! SA - Supervisor-only access control * 0b00000000..Associated segment is accessible in supervisor mode only * 0b00000001..Associated segment is accessible in user or supervisor mode */ #define FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK) /*! @} */ /*! @name SACCH2 - Supervisor-only Access Registers */ /*! @{ */ #define FTFE_SACCH2_SA_MASK (0xFFU) #define FTFE_SACCH2_SA_SHIFT (0U) /*! SA - Supervisor-only access control * 0b00000000..Associated segment is accessible in supervisor mode only * 0b00000001..Associated segment is accessible in user or supervisor mode */ #define FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK) /*! @} */ /*! @name SACCH1 - Supervisor-only Access Registers */ /*! @{ */ #define FTFE_SACCH1_SA_MASK (0xFFU) #define FTFE_SACCH1_SA_SHIFT (0U) /*! SA - Supervisor-only access control * 0b00000000..Associated segment is accessible in supervisor mode only * 0b00000001..Associated segment is accessible in user or supervisor mode */ #define FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK) /*! @} */ /*! @name SACCH0 - Supervisor-only Access Registers */ /*! @{ */ #define FTFE_SACCH0_SA_MASK (0xFFU) #define FTFE_SACCH0_SA_SHIFT (0U) /*! SA - Supervisor-only access control * 0b00000000..Associated segment is accessible in supervisor mode only * 0b00000001..Associated segment is accessible in user or supervisor mode */ #define FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK) /*! @} */ /*! @name SACCL3 - Supervisor-only Access Registers */ /*! @{ */ #define FTFE_SACCL3_SA_MASK (0xFFU) #define FTFE_SACCL3_SA_SHIFT (0U) /*! SA - Supervisor-only access control * 0b00000000..Associated segment is accessible in supervisor mode only * 0b00000001..Associated segment is accessible in user or supervisor mode */ #define FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK) /*! @} */ /*! @name SACCL2 - Supervisor-only Access Registers */ /*! @{ */ #define FTFE_SACCL2_SA_MASK (0xFFU) #define FTFE_SACCL2_SA_SHIFT (0U) /*! SA - Supervisor-only access control * 0b00000000..Associated segment is accessible in supervisor mode only * 0b00000001..Associated segment is accessible in user or supervisor mode */ #define FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK) /*! @} */ /*! @name SACCL1 - Supervisor-only Access Registers */ /*! @{ */ #define FTFE_SACCL1_SA_MASK (0xFFU) #define FTFE_SACCL1_SA_SHIFT (0U) /*! SA - Supervisor-only access control * 0b00000000..Associated segment is accessible in supervisor mode only * 0b00000001..Associated segment is accessible in user or supervisor mode */ #define FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK) /*! @} */ /*! @name SACCL0 - Supervisor-only Access Registers */ /*! @{ */ #define FTFE_SACCL0_SA_MASK (0xFFU) #define FTFE_SACCL0_SA_SHIFT (0U) /*! SA - Supervisor-only access control * 0b00000000..Associated segment is accessible in supervisor mode only * 0b00000001..Associated segment is accessible in user or supervisor mode */ #define FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK) /*! @} */ /*! @name FACSS - Flash Access Segment Size Register */ /*! @{ */ #define FTFE_FACSS_SGSIZE_MASK (0xFFU) #define FTFE_FACSS_SGSIZE_SHIFT (0U) /*! SGSIZE - Segment Size */ #define FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK) /*! @} */ /*! @name FACSN - Flash Access Segment Number Register */ /*! @{ */ #define FTFE_FACSN_NUMSG_MASK (0xFFU) #define FTFE_FACSN_NUMSG_SHIFT (0U) /*! NUMSG - Number of Segments Indicator * 0b00110000..Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes) * 0b01000000..Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes) */ #define FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK) /*! @} */ /*! * @} */ /* end of group FTFE_Register_Masks */ /* FTFE - Peripheral instance base addresses */ /** Peripheral FTFE base address */ #define FTFE_BASE (0x40020000u) /** Peripheral FTFE base pointer */ #define FTFE ((FTFE_Type *)FTFE_BASE) /** Array initializer of FTFE peripheral base addresses */ #define FTFE_BASE_ADDRS { FTFE_BASE } /** Array initializer of FTFE peripheral base pointers */ #define FTFE_BASE_PTRS { FTFE } /** Interrupt vectors for the FTFE peripheral type */ #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn } #define FTFE_READ_COLLISION_IRQS { FTFE_IRQn } /*! * @} */ /* end of group FTFE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FTM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer * @{ */ /** FTM - Register Layout Typedef */ typedef struct { __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ __IO uint32_t CNT; /**< Counter, offset: 0x4 */ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ struct { /* offset: 0xC, array step: 0x8 */ __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ } CONTROLS[8]; __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ __IO uint32_t DEADTIME; /**< Deadtime Configuration, offset: 0x68 */ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ __IO uint32_t HCR; /**< Half Cycle Register, offset: 0x9C */ uint8_t RESERVED_0[352]; __IO uint32_t MOD_MIRROR; /**< Mirror of Modulo Value, offset: 0x200 */ __IO uint32_t CV_MIRROR[8]; /**< Mirror of Channel (n) Match Value, array offset: 0x204, array step: 0x4 */ } FTM_Type; /* ---------------------------------------------------------------------------- -- FTM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FTM_Register_Masks FTM Register Masks * @{ */ /*! @name SC - Status And Control */ /*! @{ */ #define FTM_SC_PS_MASK (0x7U) #define FTM_SC_PS_SHIFT (0U) /*! PS - Prescale Factor Selection * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) #define FTM_SC_CLKS_MASK (0x18U) #define FTM_SC_CLKS_SHIFT (3U) /*! CLKS - Clock Source Selection * 0b00..No clock selected. This in effect disables the FTM counter. * 0b01..FTM input clock * 0b10..Fixed frequency clock * 0b11..External clock */ #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) #define FTM_SC_CPWMS_MASK (0x20U) #define FTM_SC_CPWMS_SHIFT (5U) /*! CPWMS - Center-Aligned PWM Select * 0b0..FTM counter operates in Up Counting mode. * 0b1..FTM counter operates in Up-Down Counting mode. */ #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) #define FTM_SC_RIE_MASK (0x40U) #define FTM_SC_RIE_SHIFT (6U) /*! RIE - Reload Interrupt Enable * 0b0..Reload interrupt is disabled. * 0b1..Reload interrupt is enabled. */ #define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RIE_SHIFT)) & FTM_SC_RIE_MASK) #define FTM_SC_RF_MASK (0x80U) #define FTM_SC_RF_SHIFT (7U) /*! RF - Reload Flag * 0b0..FTM counter did not reach a reload point. * 0b1..FTM counter reached a reload point. */ #define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RF_SHIFT)) & FTM_SC_RF_MASK) #define FTM_SC_TOIE_MASK (0x100U) #define FTM_SC_TOIE_SHIFT (8U) /*! TOIE - Timer Overflow Interrupt Enable * 0b0..Disable TOF interrupts. Use software polling. * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. */ #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) #define FTM_SC_TOF_MASK (0x200U) #define FTM_SC_TOF_SHIFT (9U) /*! TOF - Timer Overflow Flag * 0b0..FTM counter has not overflowed. * 0b1..FTM counter has overflowed. */ #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) #define FTM_SC_PWMEN0_MASK (0x10000U) #define FTM_SC_PWMEN0_SHIFT (16U) /*! PWMEN0 - Channel 0 PWM enable bit * 0b0..Channel output port is disabled * 0b1..Channel output port is enabled */ #define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN0_SHIFT)) & FTM_SC_PWMEN0_MASK) #define FTM_SC_PWMEN1_MASK (0x20000U) #define FTM_SC_PWMEN1_SHIFT (17U) /*! PWMEN1 - Channel 1 PWM enable bit * 0b0..Channel output port is disabled * 0b1..Channel output port is enabled */ #define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN1_SHIFT)) & FTM_SC_PWMEN1_MASK) #define FTM_SC_PWMEN2_MASK (0x40000U) #define FTM_SC_PWMEN2_SHIFT (18U) /*! PWMEN2 - Channel 2 PWM enable bit * 0b0..Channel output port is disabled * 0b1..Channel output port is enabled */ #define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN2_SHIFT)) & FTM_SC_PWMEN2_MASK) #define FTM_SC_PWMEN3_MASK (0x80000U) #define FTM_SC_PWMEN3_SHIFT (19U) /*! PWMEN3 - Channel 3 PWM enable bit * 0b0..Channel output port is disabled * 0b1..Channel output port is enabled */ #define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN3_SHIFT)) & FTM_SC_PWMEN3_MASK) #define FTM_SC_PWMEN4_MASK (0x100000U) #define FTM_SC_PWMEN4_SHIFT (20U) /*! PWMEN4 - Channel 4 PWM enable bit * 0b0..Channel output port is disabled * 0b1..Channel output port is enabled */ #define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN4_SHIFT)) & FTM_SC_PWMEN4_MASK) #define FTM_SC_PWMEN5_MASK (0x200000U) #define FTM_SC_PWMEN5_SHIFT (21U) /*! PWMEN5 - Channel 5 PWM enable bit * 0b0..Channel output port is disabled * 0b1..Channel output port is enabled */ #define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN5_SHIFT)) & FTM_SC_PWMEN5_MASK) #define FTM_SC_PWMEN6_MASK (0x400000U) #define FTM_SC_PWMEN6_SHIFT (22U) /*! PWMEN6 - Channel 6 PWM enable bit * 0b0..Channel output port is disabled * 0b1..Channel output port is enabled */ #define FTM_SC_PWMEN6(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN6_SHIFT)) & FTM_SC_PWMEN6_MASK) #define FTM_SC_PWMEN7_MASK (0x800000U) #define FTM_SC_PWMEN7_SHIFT (23U) /*! PWMEN7 - Channel 7 PWM enable bit * 0b0..Channel output port is disabled * 0b1..Channel output port is enabled */ #define FTM_SC_PWMEN7(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN7_SHIFT)) & FTM_SC_PWMEN7_MASK) /*! @} */ /*! @name CNT - Counter */ /*! @{ */ #define FTM_CNT_COUNT_MASK (0xFFFFU) #define FTM_CNT_COUNT_SHIFT (0U) /*! COUNT - Counter Value */ #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) /*! @} */ /*! @name MOD - Modulo */ /*! @{ */ #define FTM_MOD_MOD_MASK (0xFFFFU) #define FTM_MOD_MOD_SHIFT (0U) #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) /*! @} */ /*! @name CnSC - Channel (n) Status And Control */ /*! @{ */ #define FTM_CnSC_DMA_MASK (0x1U) #define FTM_CnSC_DMA_SHIFT (0U) /*! DMA - DMA Enable * 0b0..Disable DMA transfers. * 0b1..Enable DMA transfers. */ #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) #define FTM_CnSC_ICRST_MASK (0x2U) #define FTM_CnSC_ICRST_SHIFT (1U) /*! ICRST - FTM counter reset by the selected input capture event. * 0b0..FTM counter is not reset when the selected channel (n) input event is detected. * 0b1..FTM counter is reset when the selected channel (n) input event is detected. */ #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK) #define FTM_CnSC_ELSA_MASK (0x4U) #define FTM_CnSC_ELSA_SHIFT (2U) /*! ELSA - Channel (n) Edge or Level Select */ #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) #define FTM_CnSC_ELSB_MASK (0x8U) #define FTM_CnSC_ELSB_SHIFT (3U) /*! ELSB - Channel (n) Edge or Level Select */ #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) #define FTM_CnSC_MSA_MASK (0x10U) #define FTM_CnSC_MSA_SHIFT (4U) /*! MSA - Channel (n) Mode Select */ #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) #define FTM_CnSC_MSB_MASK (0x20U) #define FTM_CnSC_MSB_SHIFT (5U) /*! MSB - Channel (n) Mode Select */ #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) #define FTM_CnSC_CHIE_MASK (0x40U) #define FTM_CnSC_CHIE_SHIFT (6U) /*! CHIE - Channel (n) Interrupt Enable * 0b0..Disable channel (n) interrupt. Use software polling. * 0b1..Enable channel (n) interrupt. */ #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) #define FTM_CnSC_CHF_MASK (0x80U) #define FTM_CnSC_CHF_SHIFT (7U) /*! CHF - Channel (n) Flag * 0b0..No channel (n) event has occurred. * 0b1..A channel (n) event has occurred. */ #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) #define FTM_CnSC_TRIGMODE_MASK (0x100U) #define FTM_CnSC_TRIGMODE_SHIFT (8U) /*! TRIGMODE - Trigger mode control * 0b0..Channel outputs will generate the normal PWM outputs without generating a pulse. * 0b1..If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. */ #define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_TRIGMODE_SHIFT)) & FTM_CnSC_TRIGMODE_MASK) #define FTM_CnSC_CHIS_MASK (0x200U) #define FTM_CnSC_CHIS_SHIFT (9U) /*! CHIS - Channel (n) Input State * 0b0..The channel (n) input is zero. * 0b1..The channel (n) input is one. */ #define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIS_SHIFT)) & FTM_CnSC_CHIS_MASK) /*! @} */ /* The count of FTM_CnSC */ #define FTM_CnSC_COUNT (8U) /*! @name CnV - Channel (n) Value */ /*! @{ */ #define FTM_CnV_VAL_MASK (0xFFFFU) #define FTM_CnV_VAL_SHIFT (0U) /*! VAL - Channel Value */ #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) /*! @} */ /* The count of FTM_CnV */ #define FTM_CnV_COUNT (8U) /*! @name CNTIN - Counter Initial Value */ /*! @{ */ #define FTM_CNTIN_INIT_MASK (0xFFFFU) #define FTM_CNTIN_INIT_SHIFT (0U) #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) /*! @} */ /*! @name STATUS - Capture And Compare Status */ /*! @{ */ #define FTM_STATUS_CH0F_MASK (0x1U) #define FTM_STATUS_CH0F_SHIFT (0U) /*! CH0F - Channel 0 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) #define FTM_STATUS_CH1F_MASK (0x2U) #define FTM_STATUS_CH1F_SHIFT (1U) /*! CH1F - Channel 1 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) #define FTM_STATUS_CH2F_MASK (0x4U) #define FTM_STATUS_CH2F_SHIFT (2U) /*! CH2F - Channel 2 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) #define FTM_STATUS_CH3F_MASK (0x8U) #define FTM_STATUS_CH3F_SHIFT (3U) /*! CH3F - Channel 3 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) #define FTM_STATUS_CH4F_MASK (0x10U) #define FTM_STATUS_CH4F_SHIFT (4U) /*! CH4F - Channel 4 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) #define FTM_STATUS_CH5F_MASK (0x20U) #define FTM_STATUS_CH5F_SHIFT (5U) /*! CH5F - Channel 5 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) #define FTM_STATUS_CH6F_MASK (0x40U) #define FTM_STATUS_CH6F_SHIFT (6U) /*! CH6F - Channel 6 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) #define FTM_STATUS_CH7F_MASK (0x80U) #define FTM_STATUS_CH7F_SHIFT (7U) /*! CH7F - Channel 7 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) /*! @} */ /*! @name MODE - Features Mode Selection */ /*! @{ */ #define FTM_MODE_FTMEN_MASK (0x1U) #define FTM_MODE_FTMEN_SHIFT (0U) /*! FTMEN - FTM Enable * 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. * 0b1..Free running counter and synchronization are different from TPM behavior. */ #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) #define FTM_MODE_INIT_MASK (0x2U) #define FTM_MODE_INIT_SHIFT (1U) /*! INIT - Initialize The Channels Output */ #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) #define FTM_MODE_WPDIS_MASK (0x4U) #define FTM_MODE_WPDIS_SHIFT (2U) /*! WPDIS - Write Protection Disable * 0b0..Write protection is enabled. * 0b1..Write protection is disabled. */ #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) #define FTM_MODE_PWMSYNC_MASK (0x8U) #define FTM_MODE_PWMSYNC_SHIFT (3U) /*! PWMSYNC - PWM Synchronization Mode * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used * by OUTMASK and FTM counter synchronization. */ #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) #define FTM_MODE_CAPTEST_MASK (0x10U) #define FTM_MODE_CAPTEST_SHIFT (4U) /*! CAPTEST - Capture Test Mode Enable * 0b0..Capture test mode is disabled. * 0b1..Capture test mode is enabled. */ #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) #define FTM_MODE_FAULTM_MASK (0x60U) #define FTM_MODE_FAULTM_SHIFT (5U) /*! FAULTM - Fault Control Mode * 0b00..Fault control is disabled for all channels. * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. */ #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) #define FTM_MODE_FAULTIE_MASK (0x80U) #define FTM_MODE_FAULTIE_SHIFT (7U) /*! FAULTIE - Fault Interrupt Enable * 0b0..Fault control interrupt is disabled. * 0b1..Fault control interrupt is enabled. */ #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) /*! @} */ /*! @name SYNC - Synchronization */ /*! @{ */ #define FTM_SYNC_CNTMIN_MASK (0x1U) #define FTM_SYNC_CNTMIN_SHIFT (0U) /*! CNTMIN - Minimum Loading Point Enable * 0b0..The minimum loading point is disabled. * 0b1..The minimum loading point is enabled. */ #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) #define FTM_SYNC_CNTMAX_MASK (0x2U) #define FTM_SYNC_CNTMAX_SHIFT (1U) /*! CNTMAX - Maximum Loading Point Enable * 0b0..The maximum loading point is disabled. * 0b1..The maximum loading point is enabled. */ #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) #define FTM_SYNC_REINIT_MASK (0x4U) #define FTM_SYNC_REINIT_SHIFT (2U) /*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) * 0b0..FTM counter continues to count normally. * 0b1..FTM counter is updated with its initial value when the selected trigger is detected. */ #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) #define FTM_SYNC_SYNCHOM_MASK (0x8U) #define FTM_SYNC_SYNCHOM_SHIFT (3U) /*! SYNCHOM - Output Mask Synchronization * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock. * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization. */ #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) #define FTM_SYNC_TRIG0_MASK (0x10U) #define FTM_SYNC_TRIG0_SHIFT (4U) /*! TRIG0 - PWM Synchronization Hardware Trigger 0 * 0b0..Trigger is disabled. * 0b1..Trigger is enabled. */ #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) #define FTM_SYNC_TRIG1_MASK (0x20U) #define FTM_SYNC_TRIG1_SHIFT (5U) /*! TRIG1 - PWM Synchronization Hardware Trigger 1 * 0b0..Trigger is disabled. * 0b1..Trigger is enabled. */ #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) #define FTM_SYNC_TRIG2_MASK (0x40U) #define FTM_SYNC_TRIG2_SHIFT (6U) /*! TRIG2 - PWM Synchronization Hardware Trigger 2 * 0b0..Trigger is disabled. * 0b1..Trigger is enabled. */ #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) #define FTM_SYNC_SWSYNC_MASK (0x80U) #define FTM_SYNC_SWSYNC_SHIFT (7U) /*! SWSYNC - PWM Synchronization Software Trigger * 0b0..Software trigger is not selected. * 0b1..Software trigger is selected. */ #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) /*! @} */ /*! @name OUTINIT - Initial State For Channels Output */ /*! @{ */ #define FTM_OUTINIT_CH0OI_MASK (0x1U) #define FTM_OUTINIT_CH0OI_SHIFT (0U) /*! CH0OI - Channel 0 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) #define FTM_OUTINIT_CH1OI_MASK (0x2U) #define FTM_OUTINIT_CH1OI_SHIFT (1U) /*! CH1OI - Channel 1 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) #define FTM_OUTINIT_CH2OI_MASK (0x4U) #define FTM_OUTINIT_CH2OI_SHIFT (2U) /*! CH2OI - Channel 2 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) #define FTM_OUTINIT_CH3OI_MASK (0x8U) #define FTM_OUTINIT_CH3OI_SHIFT (3U) /*! CH3OI - Channel 3 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) #define FTM_OUTINIT_CH4OI_MASK (0x10U) #define FTM_OUTINIT_CH4OI_SHIFT (4U) /*! CH4OI - Channel 4 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) #define FTM_OUTINIT_CH5OI_MASK (0x20U) #define FTM_OUTINIT_CH5OI_SHIFT (5U) /*! CH5OI - Channel 5 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) #define FTM_OUTINIT_CH6OI_MASK (0x40U) #define FTM_OUTINIT_CH6OI_SHIFT (6U) /*! CH6OI - Channel 6 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) #define FTM_OUTINIT_CH7OI_MASK (0x80U) #define FTM_OUTINIT_CH7OI_SHIFT (7U) /*! CH7OI - Channel 7 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) /*! @} */ /*! @name OUTMASK - Output Mask */ /*! @{ */ #define FTM_OUTMASK_CH0OM_MASK (0x1U) #define FTM_OUTMASK_CH0OM_SHIFT (0U) /*! CH0OM - Channel 0 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) #define FTM_OUTMASK_CH1OM_MASK (0x2U) #define FTM_OUTMASK_CH1OM_SHIFT (1U) /*! CH1OM - Channel 1 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) #define FTM_OUTMASK_CH2OM_MASK (0x4U) #define FTM_OUTMASK_CH2OM_SHIFT (2U) /*! CH2OM - Channel 2 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) #define FTM_OUTMASK_CH3OM_MASK (0x8U) #define FTM_OUTMASK_CH3OM_SHIFT (3U) /*! CH3OM - Channel 3 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) #define FTM_OUTMASK_CH4OM_MASK (0x10U) #define FTM_OUTMASK_CH4OM_SHIFT (4U) /*! CH4OM - Channel 4 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) #define FTM_OUTMASK_CH5OM_MASK (0x20U) #define FTM_OUTMASK_CH5OM_SHIFT (5U) /*! CH5OM - Channel 5 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) #define FTM_OUTMASK_CH6OM_MASK (0x40U) #define FTM_OUTMASK_CH6OM_SHIFT (6U) /*! CH6OM - Channel 6 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) #define FTM_OUTMASK_CH7OM_MASK (0x80U) #define FTM_OUTMASK_CH7OM_SHIFT (7U) /*! CH7OM - Channel 7 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) /*! @} */ /*! @name COMBINE - Function For Linked Channels */ /*! @{ */ #define FTM_COMBINE_COMBINE0_MASK (0x1U) #define FTM_COMBINE_COMBINE0_SHIFT (0U) /*! COMBINE0 - Combine Channels For n = 0 */ #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) #define FTM_COMBINE_COMP0_MASK (0x2U) #define FTM_COMBINE_COMP0_SHIFT (1U) /*! COMP0 - Complement Of Channel (n) For n = 0 * 0b0..The channel (n+1) output is the same as the channel (n) output. * 0b1..The channel (n+1) output is the complement of the channel (n) output. */ #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) #define FTM_COMBINE_DECAPEN0_MASK (0x4U) #define FTM_COMBINE_DECAPEN0_SHIFT (2U) /*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 */ #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) #define FTM_COMBINE_DECAP0_MASK (0x8U) #define FTM_COMBINE_DECAP0_SHIFT (3U) /*! DECAP0 - Dual Edge Capture Mode Captures For n = 0 * 0b0..The dual edge captures are inactive. * 0b1..The dual edge captures are active. */ #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) #define FTM_COMBINE_DTEN0_MASK (0x10U) #define FTM_COMBINE_DTEN0_SHIFT (4U) /*! DTEN0 - Deadtime Enable For n = 0 * 0b0..The deadtime insertion in this pair of channels is disabled. * 0b1..The deadtime insertion in this pair of channels is enabled. */ #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) #define FTM_COMBINE_SYNCEN0_MASK (0x20U) #define FTM_COMBINE_SYNCEN0_SHIFT (5U) /*! SYNCEN0 - Synchronization Enable For n = 0 * 0b0..The PWM synchronization in this pair of channels is disabled. * 0b1..The PWM synchronization in this pair of channels is enabled. */ #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) #define FTM_COMBINE_FAULTEN0_MASK (0x40U) #define FTM_COMBINE_FAULTEN0_SHIFT (6U) /*! FAULTEN0 - Fault Control Enable For n = 0 * 0b0..The fault control in this pair of channels is disabled. * 0b1..The fault control in this pair of channels is enabled. */ #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) #define FTM_COMBINE_COMBINE1_MASK (0x100U) #define FTM_COMBINE_COMBINE1_SHIFT (8U) /*! COMBINE1 - Combine Channels For n = 2 */ #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) #define FTM_COMBINE_COMP1_MASK (0x200U) #define FTM_COMBINE_COMP1_SHIFT (9U) /*! COMP1 - Complement Of Channel (n) For n = 2 * 0b0..The channel (n+1) output is the same as the channel (n) output. * 0b1..The channel (n+1) output is the complement of the channel (n) output. */ #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) #define FTM_COMBINE_DECAPEN1_MASK (0x400U) #define FTM_COMBINE_DECAPEN1_SHIFT (10U) /*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 */ #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) #define FTM_COMBINE_DECAP1_MASK (0x800U) #define FTM_COMBINE_DECAP1_SHIFT (11U) /*! DECAP1 - Dual Edge Capture Mode Captures For n = 2 * 0b0..The dual edge captures are inactive. * 0b1..The dual edge captures are active. */ #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) #define FTM_COMBINE_DTEN1_MASK (0x1000U) #define FTM_COMBINE_DTEN1_SHIFT (12U) /*! DTEN1 - Deadtime Enable For n = 2 * 0b0..The deadtime insertion in this pair of channels is disabled. * 0b1..The deadtime insertion in this pair of channels is enabled. */ #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) #define FTM_COMBINE_SYNCEN1_SHIFT (13U) /*! SYNCEN1 - Synchronization Enable For n = 2 * 0b0..The PWM synchronization in this pair of channels is disabled. * 0b1..The PWM synchronization in this pair of channels is enabled. */ #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) #define FTM_COMBINE_FAULTEN1_SHIFT (14U) /*! FAULTEN1 - Fault Control Enable For n = 2 * 0b0..The fault control in this pair of channels is disabled. * 0b1..The fault control in this pair of channels is enabled. */ #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) #define FTM_COMBINE_COMBINE2_MASK (0x10000U) #define FTM_COMBINE_COMBINE2_SHIFT (16U) /*! COMBINE2 - Combine Channels For n = 4 */ #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) #define FTM_COMBINE_COMP2_MASK (0x20000U) #define FTM_COMBINE_COMP2_SHIFT (17U) /*! COMP2 - Complement Of Channel (n) For n = 4 * 0b0..The channel (n+1) output is the same as the channel (n) output. * 0b1..The channel (n+1) output is the complement of the channel (n) output. */ #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) #define FTM_COMBINE_DECAPEN2_SHIFT (18U) /*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 */ #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) #define FTM_COMBINE_DECAP2_MASK (0x80000U) #define FTM_COMBINE_DECAP2_SHIFT (19U) /*! DECAP2 - Dual Edge Capture Mode Captures For n = 4 * 0b0..The dual edge captures are inactive. * 0b1..The dual edge captures are active. */ #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) #define FTM_COMBINE_DTEN2_MASK (0x100000U) #define FTM_COMBINE_DTEN2_SHIFT (20U) /*! DTEN2 - Deadtime Enable For n = 4 * 0b0..The deadtime insertion in this pair of channels is disabled. * 0b1..The deadtime insertion in this pair of channels is enabled. */ #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) #define FTM_COMBINE_SYNCEN2_SHIFT (21U) /*! SYNCEN2 - Synchronization Enable For n = 4 * 0b0..The PWM synchronization in this pair of channels is disabled. * 0b1..The PWM synchronization in this pair of channels is enabled. */ #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) #define FTM_COMBINE_FAULTEN2_SHIFT (22U) /*! FAULTEN2 - Fault Control Enable For n = 4 * 0b0..The fault control in this pair of channels is disabled. * 0b1..The fault control in this pair of channels is enabled. */ #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) #define FTM_COMBINE_COMBINE3_SHIFT (24U) /*! COMBINE3 - Combine Channels For n = 6 */ #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) #define FTM_COMBINE_COMP3_MASK (0x2000000U) #define FTM_COMBINE_COMP3_SHIFT (25U) /*! COMP3 - Complement Of Channel (n) for n = 6 * 0b0..The channel (n+1) output is the same as the channel (n) output. * 0b1..The channel (n+1) output is the complement of the channel (n) output. */ #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) #define FTM_COMBINE_DECAPEN3_SHIFT (26U) /*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 */ #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) #define FTM_COMBINE_DECAP3_MASK (0x8000000U) #define FTM_COMBINE_DECAP3_SHIFT (27U) /*! DECAP3 - Dual Edge Capture Mode Captures For n = 6 * 0b0..The dual edge captures are inactive. * 0b1..The dual edge captures are active. */ #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) #define FTM_COMBINE_DTEN3_MASK (0x10000000U) #define FTM_COMBINE_DTEN3_SHIFT (28U) /*! DTEN3 - Deadtime Enable For n = 6 * 0b0..The deadtime insertion in this pair of channels is disabled. * 0b1..The deadtime insertion in this pair of channels is enabled. */ #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) #define FTM_COMBINE_SYNCEN3_SHIFT (29U) /*! SYNCEN3 - Synchronization Enable For n = 6 * 0b0..The PWM synchronization in this pair of channels is disabled. * 0b1..The PWM synchronization in this pair of channels is enabled. */ #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) #define FTM_COMBINE_FAULTEN3_SHIFT (30U) /*! FAULTEN3 - Fault Control Enable For n = 6 * 0b0..The fault control in this pair of channels is disabled. * 0b1..The fault control in this pair of channels is enabled. */ #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) /*! @} */ /*! @name DEADTIME - Deadtime Configuration */ /*! @{ */ #define FTM_DEADTIME_DTVAL_MASK (0x3FU) #define FTM_DEADTIME_DTVAL_SHIFT (0U) /*! DTVAL - Deadtime Value */ #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) #define FTM_DEADTIME_DTPS_MASK (0xC0U) #define FTM_DEADTIME_DTPS_SHIFT (6U) /*! DTPS - Deadtime Prescaler Value * 0b0x..Divide the FTM input clock by 1. * 0b10..Divide the FTM input clock by 4. * 0b11..Divide the FTM input clock by 16. */ #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) /*! @} */ /*! @name EXTTRIG - FTM External Trigger */ /*! @{ */ #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) /*! CH2TRIG - Channel 2 Trigger Enable * 0b0..The generation of the channel trigger is disabled. * 0b1..The generation of the channel trigger is enabled. */ #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) /*! CH3TRIG - Channel 3 Trigger Enable * 0b0..The generation of the channel trigger is disabled. * 0b1..The generation of the channel trigger is enabled. */ #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) /*! CH4TRIG - Channel 4 Trigger Enable * 0b0..The generation of the channel trigger is disabled. * 0b1..The generation of the channel trigger is enabled. */ #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) /*! CH5TRIG - Channel 5 Trigger Enable * 0b0..The generation of the channel trigger is disabled. * 0b1..The generation of the channel trigger is enabled. */ #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) /*! CH0TRIG - Channel 0 Trigger Enable * 0b0..The generation of the channel trigger is disabled. * 0b1..The generation of the channel trigger is enabled. */ #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) /*! CH1TRIG - Channel 1 Trigger Enable * 0b0..The generation of the channel trigger is disabled. * 0b1..The generation of the channel trigger is enabled. */ #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) /*! INITTRIGEN - Initialization Trigger Enable * 0b0..The generation of initialization trigger is disabled. * 0b1..The generation of initialization trigger is enabled. */ #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) #define FTM_EXTTRIG_TRIGF_MASK (0x80U) #define FTM_EXTTRIG_TRIGF_SHIFT (7U) /*! TRIGF - Channel Trigger Flag * 0b0..No channel trigger was generated. * 0b1..A channel trigger was generated. */ #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) #define FTM_EXTTRIG_CH6TRIG_MASK (0x100U) #define FTM_EXTTRIG_CH6TRIG_SHIFT (8U) /*! CH6TRIG - Channel 6 Trigger Enable * 0b0..The generation of the channel trigger is disabled. * 0b1..The generation of the channel trigger is enabled. */ #define FTM_EXTTRIG_CH6TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH6TRIG_SHIFT)) & FTM_EXTTRIG_CH6TRIG_MASK) #define FTM_EXTTRIG_CH7TRIG_MASK (0x200U) #define FTM_EXTTRIG_CH7TRIG_SHIFT (9U) /*! CH7TRIG - Channel 7 Trigger Enable * 0b0..The generation of the channel trigger is disabled. * 0b1..The generation of the channel trigger is enabled. */ #define FTM_EXTTRIG_CH7TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH7TRIG_SHIFT)) & FTM_EXTTRIG_CH7TRIG_MASK) /*! @} */ /*! @name POL - Channels Polarity */ /*! @{ */ #define FTM_POL_POL0_MASK (0x1U) #define FTM_POL_POL0_SHIFT (0U) /*! POL0 - Channel 0 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) #define FTM_POL_POL1_MASK (0x2U) #define FTM_POL_POL1_SHIFT (1U) /*! POL1 - Channel 1 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) #define FTM_POL_POL2_MASK (0x4U) #define FTM_POL_POL2_SHIFT (2U) /*! POL2 - Channel 2 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) #define FTM_POL_POL3_MASK (0x8U) #define FTM_POL_POL3_SHIFT (3U) /*! POL3 - Channel 3 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) #define FTM_POL_POL4_MASK (0x10U) #define FTM_POL_POL4_SHIFT (4U) /*! POL4 - Channel 4 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) #define FTM_POL_POL5_MASK (0x20U) #define FTM_POL_POL5_SHIFT (5U) /*! POL5 - Channel 5 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) #define FTM_POL_POL6_MASK (0x40U) #define FTM_POL_POL6_SHIFT (6U) /*! POL6 - Channel 6 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) #define FTM_POL_POL7_MASK (0x80U) #define FTM_POL_POL7_SHIFT (7U) /*! POL7 - Channel 7 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) /*! @} */ /*! @name FMS - Fault Mode Status */ /*! @{ */ #define FTM_FMS_FAULTF0_MASK (0x1U) #define FTM_FMS_FAULTF0_SHIFT (0U) /*! FAULTF0 - Fault Detection Flag 0 * 0b0..No fault condition was detected at the fault input. * 0b1..A fault condition was detected at the fault input. */ #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) #define FTM_FMS_FAULTF1_MASK (0x2U) #define FTM_FMS_FAULTF1_SHIFT (1U) /*! FAULTF1 - Fault Detection Flag 1 * 0b0..No fault condition was detected at the fault input. * 0b1..A fault condition was detected at the fault input. */ #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) #define FTM_FMS_FAULTF2_MASK (0x4U) #define FTM_FMS_FAULTF2_SHIFT (2U) /*! FAULTF2 - Fault Detection Flag 2 * 0b0..No fault condition was detected at the fault input. * 0b1..A fault condition was detected at the fault input. */ #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) #define FTM_FMS_FAULTF3_MASK (0x8U) #define FTM_FMS_FAULTF3_SHIFT (3U) /*! FAULTF3 - Fault Detection Flag 3 * 0b0..No fault condition was detected at the fault input. * 0b1..A fault condition was detected at the fault input. */ #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) #define FTM_FMS_FAULTIN_MASK (0x20U) #define FTM_FMS_FAULTIN_SHIFT (5U) /*! FAULTIN - Fault Inputs * 0b0..The logic OR of the enabled fault inputs is 0. * 0b1..The logic OR of the enabled fault inputs is 1. */ #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) #define FTM_FMS_WPEN_MASK (0x40U) #define FTM_FMS_WPEN_SHIFT (6U) /*! WPEN - Write Protection Enable * 0b0..Write protection is disabled. Write protected bits can be written. * 0b1..Write protection is enabled. Write protected bits cannot be written. */ #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) #define FTM_FMS_FAULTF_MASK (0x80U) #define FTM_FMS_FAULTF_SHIFT (7U) /*! FAULTF - Fault Detection Flag * 0b0..No fault condition was detected. * 0b1..A fault condition was detected. */ #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) /*! @} */ /*! @name FILTER - Input Capture Filter Control */ /*! @{ */ #define FTM_FILTER_CH0FVAL_MASK (0xFU) #define FTM_FILTER_CH0FVAL_SHIFT (0U) /*! CH0FVAL - Channel 0 Input Filter */ #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) #define FTM_FILTER_CH1FVAL_MASK (0xF0U) #define FTM_FILTER_CH1FVAL_SHIFT (4U) /*! CH1FVAL - Channel 1 Input Filter */ #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) #define FTM_FILTER_CH2FVAL_MASK (0xF00U) #define FTM_FILTER_CH2FVAL_SHIFT (8U) /*! CH2FVAL - Channel 2 Input Filter */ #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) #define FTM_FILTER_CH3FVAL_MASK (0xF000U) #define FTM_FILTER_CH3FVAL_SHIFT (12U) /*! CH3FVAL - Channel 3 Input Filter */ #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) /*! @} */ /*! @name FLTCTRL - Fault Control */ /*! @{ */ #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) /*! FAULT0EN - Fault Input 0 Enable * 0b0..Fault input is disabled. * 0b1..Fault input is enabled. */ #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) /*! FAULT1EN - Fault Input 1 Enable * 0b0..Fault input is disabled. * 0b1..Fault input is enabled. */ #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) /*! FAULT2EN - Fault Input 2 Enable * 0b0..Fault input is disabled. * 0b1..Fault input is enabled. */ #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) /*! FAULT3EN - Fault Input 3 Enable * 0b0..Fault input is disabled. * 0b1..Fault input is enabled. */ #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) /*! FFLTR0EN - Fault Input 0 Filter Enable * 0b0..Fault input filter is disabled. * 0b1..Fault input filter is enabled. */ #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) /*! FFLTR1EN - Fault Input 1 Filter Enable * 0b0..Fault input filter is disabled. * 0b1..Fault input filter is enabled. */ #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) /*! FFLTR2EN - Fault Input 2 Filter Enable * 0b0..Fault input filter is disabled. * 0b1..Fault input filter is enabled. */ #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) /*! FFLTR3EN - Fault Input 3 Filter Enable * 0b0..Fault input filter is disabled. * 0b1..Fault input filter is enabled. */ #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) #define FTM_FLTCTRL_FFVAL_SHIFT (8U) /*! FFVAL - Fault Input Filter */ #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) #define FTM_FLTCTRL_FSTATE_MASK (0x8000U) #define FTM_FLTCTRL_FSTATE_SHIFT (15U) /*! FSTATE - Fault output state * 0b0..FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits). * 0b1..FTM outputs will be tri-stated when fault event is ongoing */ #define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FSTATE_SHIFT)) & FTM_FLTCTRL_FSTATE_MASK) /*! @} */ /*! @name QDCTRL - Quadrature Decoder Control And Status */ /*! @{ */ #define FTM_QDCTRL_QUADEN_MASK (0x1U) #define FTM_QDCTRL_QUADEN_SHIFT (0U) /*! QUADEN - Quadrature Decoder Mode Enable * 0b0..Quadrature Decoder mode is disabled. * 0b1..Quadrature Decoder mode is enabled. */ #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) #define FTM_QDCTRL_TOFDIR_MASK (0x2U) #define FTM_QDCTRL_TOFDIR_SHIFT (1U) /*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes * from its minimum value (CNTIN register) to its maximum value (MOD register). * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from * its maximum value (MOD register) to its minimum value (CNTIN register). */ #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) #define FTM_QDCTRL_QUADIR_MASK (0x4U) #define FTM_QDCTRL_QUADIR_SHIFT (2U) /*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode * 0b0..Counting direction is decreasing (FTM counter decrement). * 0b1..Counting direction is increasing (FTM counter increment). */ #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) #define FTM_QDCTRL_QUADMODE_MASK (0x8U) #define FTM_QDCTRL_QUADMODE_SHIFT (3U) /*! QUADMODE - Quadrature Decoder Mode * 0b0..Phase A and phase B encoding mode. * 0b1..Count and direction encoding mode. */ #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) #define FTM_QDCTRL_PHBPOL_MASK (0x10U) #define FTM_QDCTRL_PHBPOL_SHIFT (4U) /*! PHBPOL - Phase B Input Polarity * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. */ #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) #define FTM_QDCTRL_PHAPOL_MASK (0x20U) #define FTM_QDCTRL_PHAPOL_SHIFT (5U) /*! PHAPOL - Phase A Input Polarity * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. */ #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) /*! PHBFLTREN - Phase B Input Filter Enable * 0b0..Phase B input filter is disabled. * 0b1..Phase B input filter is enabled. */ #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) /*! PHAFLTREN - Phase A Input Filter Enable * 0b0..Phase A input filter is disabled. * 0b1..Phase A input filter is enabled. */ #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) /*! @} */ /*! @name CONF - Configuration */ /*! @{ */ #define FTM_CONF_LDFQ_MASK (0x1FU) #define FTM_CONF_LDFQ_SHIFT (0U) /*! LDFQ - Load Frequency */ #define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_LDFQ_SHIFT)) & FTM_CONF_LDFQ_MASK) #define FTM_CONF_BDMMODE_MASK (0xC0U) #define FTM_CONF_BDMMODE_SHIFT (6U) /*! BDMMODE - Debug Mode */ #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) #define FTM_CONF_GTBEEN_MASK (0x200U) #define FTM_CONF_GTBEEN_SHIFT (9U) /*! GTBEEN - Global Time Base Enable * 0b0..Use of an external global time base is disabled. * 0b1..Use of an external global time base is enabled. */ #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) #define FTM_CONF_GTBEOUT_MASK (0x400U) #define FTM_CONF_GTBEOUT_SHIFT (10U) /*! GTBEOUT - Global Time Base Output * 0b0..A global time base signal generation is disabled. * 0b1..A global time base signal generation is enabled. */ #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) #define FTM_CONF_ITRIGR_MASK (0x800U) #define FTM_CONF_ITRIGR_SHIFT (11U) /*! ITRIGR - Initialization trigger on Reload Point * 0b0..Initialization trigger is generated on counter wrap events. * 0b1..Initialization trigger is generated when a reload point is reached. */ #define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_ITRIGR_SHIFT)) & FTM_CONF_ITRIGR_MASK) /*! @} */ /*! @name FLTPOL - FTM Fault Input Polarity */ /*! @{ */ #define FTM_FLTPOL_FLT0POL_MASK (0x1U) #define FTM_FLTPOL_FLT0POL_SHIFT (0U) /*! FLT0POL - Fault Input 0 Polarity * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. */ #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) #define FTM_FLTPOL_FLT1POL_MASK (0x2U) #define FTM_FLTPOL_FLT1POL_SHIFT (1U) /*! FLT1POL - Fault Input 1 Polarity * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. */ #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) #define FTM_FLTPOL_FLT2POL_MASK (0x4U) #define FTM_FLTPOL_FLT2POL_SHIFT (2U) /*! FLT2POL - Fault Input 2 Polarity * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. */ #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) #define FTM_FLTPOL_FLT3POL_MASK (0x8U) #define FTM_FLTPOL_FLT3POL_SHIFT (3U) /*! FLT3POL - Fault Input 3 Polarity * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. */ #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) /*! @} */ /*! @name SYNCONF - Synchronization Configuration */ /*! @{ */ #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) /*! HWTRIGMODE - Hardware Trigger Mode * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. */ #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) #define FTM_SYNCONF_CNTINC_MASK (0x4U) #define FTM_SYNCONF_CNTINC_SHIFT (2U) /*! CNTINC - CNTIN Register Synchronization * 0b0..CNTIN register is updated with its buffer value at all rising edges of FTM input clock. * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization. */ #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) #define FTM_SYNCONF_INVC_MASK (0x10U) #define FTM_SYNCONF_INVC_SHIFT (4U) /*! INVC - INVCTRL Register Synchronization * 0b0..INVCTRL register is updated with its buffer value at all rising edges of FTM input clock. * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization. */ #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) #define FTM_SYNCONF_SWOC_MASK (0x20U) #define FTM_SYNCONF_SWOC_SHIFT (5U) /*! SWOC - SWOCTRL Register Synchronization * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock. * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization. */ #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) /*! SYNCMODE - Synchronization Mode * 0b0..Legacy PWM synchronization is selected. * 0b1..Enhanced PWM synchronization is selected. */ #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) /*! SWRSTCNT * 0b0..The software trigger does not activate the FTM counter synchronization. * 0b1..The software trigger activates the FTM counter synchronization. */ #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) /*! SWWRBUF * 0b0..The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. * 0b1..The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization. */ #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) #define FTM_SYNCONF_SWOM_MASK (0x400U) #define FTM_SYNCONF_SWOM_SHIFT (10U) /*! SWOM * 0b0..The software trigger does not activate the OUTMASK register synchronization. * 0b1..The software trigger activates the OUTMASK register synchronization. */ #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) #define FTM_SYNCONF_SWINVC_MASK (0x800U) #define FTM_SYNCONF_SWINVC_SHIFT (11U) /*! SWINVC * 0b0..The software trigger does not activate the INVCTRL register synchronization. * 0b1..The software trigger activates the INVCTRL register synchronization. */ #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) #define FTM_SYNCONF_SWSOC_MASK (0x1000U) #define FTM_SYNCONF_SWSOC_SHIFT (12U) /*! SWSOC * 0b0..The software trigger does not activate the SWOCTRL register synchronization. * 0b1..The software trigger activates the SWOCTRL register synchronization. */ #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) /*! HWRSTCNT * 0b0..A hardware trigger does not activate the FTM counter synchronization. * 0b1..A hardware trigger activates the FTM counter synchronization. */ #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) /*! HWWRBUF * 0b0..A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. * 0b1..A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization. */ #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) #define FTM_SYNCONF_HWOM_MASK (0x40000U) #define FTM_SYNCONF_HWOM_SHIFT (18U) /*! HWOM * 0b0..A hardware trigger does not activate the OUTMASK register synchronization. * 0b1..A hardware trigger activates the OUTMASK register synchronization. */ #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) #define FTM_SYNCONF_HWINVC_MASK (0x80000U) #define FTM_SYNCONF_HWINVC_SHIFT (19U) /*! HWINVC * 0b0..A hardware trigger does not activate the INVCTRL register synchronization. * 0b1..A hardware trigger activates the INVCTRL register synchronization. */ #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) #define FTM_SYNCONF_HWSOC_MASK (0x100000U) #define FTM_SYNCONF_HWSOC_SHIFT (20U) /*! HWSOC * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. * 0b1..A hardware trigger activates the SWOCTRL register synchronization. */ #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) /*! @} */ /*! @name INVCTRL - FTM Inverting Control */ /*! @{ */ #define FTM_INVCTRL_INV0EN_MASK (0x1U) #define FTM_INVCTRL_INV0EN_SHIFT (0U) /*! INV0EN - Pair Channels 0 Inverting Enable * 0b0..Inverting is disabled. * 0b1..Inverting is enabled. */ #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) #define FTM_INVCTRL_INV1EN_MASK (0x2U) #define FTM_INVCTRL_INV1EN_SHIFT (1U) /*! INV1EN - Pair Channels 1 Inverting Enable * 0b0..Inverting is disabled. * 0b1..Inverting is enabled. */ #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) #define FTM_INVCTRL_INV2EN_MASK (0x4U) #define FTM_INVCTRL_INV2EN_SHIFT (2U) /*! INV2EN - Pair Channels 2 Inverting Enable * 0b0..Inverting is disabled. * 0b1..Inverting is enabled. */ #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) #define FTM_INVCTRL_INV3EN_MASK (0x8U) #define FTM_INVCTRL_INV3EN_SHIFT (3U) /*! INV3EN - Pair Channels 3 Inverting Enable * 0b0..Inverting is disabled. * 0b1..Inverting is enabled. */ #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) /*! @} */ /*! @name SWOCTRL - FTM Software Output Control */ /*! @{ */ #define FTM_SWOCTRL_CH0OC_MASK (0x1U) #define FTM_SWOCTRL_CH0OC_SHIFT (0U) /*! CH0OC - Channel 0 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) #define FTM_SWOCTRL_CH1OC_MASK (0x2U) #define FTM_SWOCTRL_CH1OC_SHIFT (1U) /*! CH1OC - Channel 1 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) #define FTM_SWOCTRL_CH2OC_MASK (0x4U) #define FTM_SWOCTRL_CH2OC_SHIFT (2U) /*! CH2OC - Channel 2 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) #define FTM_SWOCTRL_CH3OC_MASK (0x8U) #define FTM_SWOCTRL_CH3OC_SHIFT (3U) /*! CH3OC - Channel 3 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) #define FTM_SWOCTRL_CH4OC_MASK (0x10U) #define FTM_SWOCTRL_CH4OC_SHIFT (4U) /*! CH4OC - Channel 4 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) #define FTM_SWOCTRL_CH5OC_MASK (0x20U) #define FTM_SWOCTRL_CH5OC_SHIFT (5U) /*! CH5OC - Channel 5 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) #define FTM_SWOCTRL_CH6OC_MASK (0x40U) #define FTM_SWOCTRL_CH6OC_SHIFT (6U) /*! CH6OC - Channel 6 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) #define FTM_SWOCTRL_CH7OC_MASK (0x80U) #define FTM_SWOCTRL_CH7OC_SHIFT (7U) /*! CH7OC - Channel 7 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) /*! CH0OCV - Channel 0 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) /*! CH1OCV - Channel 1 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) /*! CH2OCV - Channel 2 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) /*! CH3OCV - Channel 3 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) /*! CH4OCV - Channel 4 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) /*! CH5OCV - Channel 5 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) /*! CH6OCV - Channel 6 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) /*! CH7OCV - Channel 7 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) /*! @} */ /*! @name PWMLOAD - FTM PWM Load */ /*! @{ */ #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) /*! CH0SEL - Channel 0 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) /*! CH1SEL - Channel 1 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) /*! CH2SEL - Channel 2 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) /*! CH3SEL - Channel 3 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) /*! CH4SEL - Channel 4 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) /*! CH5SEL - Channel 5 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) /*! CH6SEL - Channel 6 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) /*! CH7SEL - Channel 7 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) #define FTM_PWMLOAD_HCSEL_MASK (0x100U) #define FTM_PWMLOAD_HCSEL_SHIFT (8U) /*! HCSEL - Half Cycle Select * 0b0..Half cycle reload is disabled and it is not considered as a reload opportunity. * 0b1..Half cycle reload is enabled and it is considered as a reload opportunity. */ #define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_HCSEL_SHIFT)) & FTM_PWMLOAD_HCSEL_MASK) #define FTM_PWMLOAD_LDOK_MASK (0x200U) #define FTM_PWMLOAD_LDOK_SHIFT (9U) /*! LDOK - Load Enable * 0b0..Loading updated values is disabled. * 0b1..Loading updated values is enabled. */ #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) #define FTM_PWMLOAD_GLEN_MASK (0x400U) #define FTM_PWMLOAD_GLEN_SHIFT (10U) /*! GLEN - Global Load Enable * 0b0..Global Load Ok disabled. * 0b1..Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit. */ #define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLEN_SHIFT)) & FTM_PWMLOAD_GLEN_MASK) #define FTM_PWMLOAD_GLDOK_MASK (0x800U) #define FTM_PWMLOAD_GLDOK_SHIFT (11U) /*! GLDOK - Global Load OK * 0b0..No action. * 0b1..LDOK bit is set. */ #define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLDOK_SHIFT)) & FTM_PWMLOAD_GLDOK_MASK) /*! @} */ /*! @name HCR - Half Cycle Register */ /*! @{ */ #define FTM_HCR_HCVAL_MASK (0xFFFFU) #define FTM_HCR_HCVAL_SHIFT (0U) /*! HCVAL - Half Cycle Value */ #define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_HCR_HCVAL_SHIFT)) & FTM_HCR_HCVAL_MASK) /*! @} */ /*! @name MOD_MIRROR - Mirror of Modulo Value */ /*! @{ */ #define FTM_MOD_MIRROR_FRACMOD_MASK (0xF800U) #define FTM_MOD_MIRROR_FRACMOD_SHIFT (11U) /*! FRACMOD - Modulo Fractional Value */ #define FTM_MOD_MIRROR_FRACMOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_FRACMOD_SHIFT)) & FTM_MOD_MIRROR_FRACMOD_MASK) #define FTM_MOD_MIRROR_MOD_MASK (0xFFFF0000U) #define FTM_MOD_MIRROR_MOD_SHIFT (16U) /*! MOD - Mirror of the Modulo Integer Value */ #define FTM_MOD_MIRROR_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_MOD_SHIFT)) & FTM_MOD_MIRROR_MOD_MASK) /*! @} */ /*! @name CV_MIRROR - Mirror of Channel (n) Match Value */ /*! @{ */ #define FTM_CV_MIRROR_FRACVAL_MASK (0xF800U) #define FTM_CV_MIRROR_FRACVAL_SHIFT (11U) /*! FRACVAL - Channel (n) Match Fractional Value */ #define FTM_CV_MIRROR_FRACVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_FRACVAL_SHIFT)) & FTM_CV_MIRROR_FRACVAL_MASK) #define FTM_CV_MIRROR_VAL_MASK (0xFFFF0000U) #define FTM_CV_MIRROR_VAL_SHIFT (16U) /*! VAL - Mirror of the Channel (n) Match Integer Value */ #define FTM_CV_MIRROR_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_VAL_SHIFT)) & FTM_CV_MIRROR_VAL_MASK) /*! @} */ /* The count of FTM_CV_MIRROR */ #define FTM_CV_MIRROR_COUNT (8U) /*! * @} */ /* end of group FTM_Register_Masks */ /* FTM - Peripheral instance base addresses */ /** Peripheral FTM0 base address */ #define FTM0_BASE (0x40038000u) /** Peripheral FTM0 base pointer */ #define FTM0 ((FTM_Type *)FTM0_BASE) /** Peripheral FTM1 base address */ #define FTM1_BASE (0x40039000u) /** Peripheral FTM1 base pointer */ #define FTM1 ((FTM_Type *)FTM1_BASE) /** Peripheral FTM2 base address */ #define FTM2_BASE (0x4003A000u) /** Peripheral FTM2 base pointer */ #define FTM2 ((FTM_Type *)FTM2_BASE) /** Array initializer of FTM peripheral base addresses */ #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE } /** Array initializer of FTM peripheral base pointers */ #define FTM_BASE_PTRS { FTM0, FTM1, FTM2 } /** Interrupt vectors for the FTM peripheral type */ #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn } /*! * @} */ /* end of group FTM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer * @{ */ /** GPIO - Register Layout Typedef */ typedef struct { __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ } GPIO_Type; /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /*! @name PDOR - Port Data Output Register */ /*! @{ */ #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) #define GPIO_PDOR_PDO_SHIFT (0U) /*! PDO - Port Data Output * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. */ #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) /*! @} */ /*! @name PSOR - Port Set Output Register */ /*! @{ */ #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) #define GPIO_PSOR_PTSO_SHIFT (0U) /*! PTSO - Port Set Output * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. */ #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) /*! @} */ /*! @name PCOR - Port Clear Output Register */ /*! @{ */ #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) #define GPIO_PCOR_PTCO_SHIFT (0U) /*! PTCO - Port Clear Output * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. */ #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) /*! @} */ /*! @name PTOR - Port Toggle Output Register */ /*! @{ */ #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) #define GPIO_PTOR_PTTO_SHIFT (0U) /*! PTTO - Port Toggle Output * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. */ #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) /*! @} */ /*! @name PDIR - Port Data Input Register */ /*! @{ */ #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) #define GPIO_PDIR_PDI_SHIFT (0U) /*! PDI - Port Data Input * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. * 0b00000000000000000000000000000001..Pin logic level is logic 1. */ #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) /*! @} */ /*! @name PDDR - Port Data Direction Register */ /*! @{ */ #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) #define GPIO_PDDR_PDD_SHIFT (0U) /*! PDD - Port Data Direction * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. */ #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) /*! @} */ /*! * @} */ /* end of group GPIO_Register_Masks */ /* GPIO - Peripheral instance base addresses */ /** Peripheral GPIOA base address */ #define GPIOA_BASE (0x400FF000u) /** Peripheral GPIOA base pointer */ #define GPIOA ((GPIO_Type *)GPIOA_BASE) /** Peripheral GPIOB base address */ #define GPIOB_BASE (0x400FF040u) /** Peripheral GPIOB base pointer */ #define GPIOB ((GPIO_Type *)GPIOB_BASE) /** Peripheral GPIOC base address */ #define GPIOC_BASE (0x400FF080u) /** Peripheral GPIOC base pointer */ #define GPIOC ((GPIO_Type *)GPIOC_BASE) /** Peripheral GPIOD base address */ #define GPIOD_BASE (0x400FF0C0u) /** Peripheral GPIOD base pointer */ #define GPIOD ((GPIO_Type *)GPIOD_BASE) /** Peripheral GPIOE base address */ #define GPIOE_BASE (0x400FF100u) /** Peripheral GPIOE base pointer */ #define GPIOE ((GPIO_Type *)GPIOE_BASE) /** Array initializer of GPIO peripheral base addresses */ #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } /*! * @} */ /* end of group GPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPI2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer * @{ */ /** LPI2C - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ uint8_t RESERVED_1[16]; __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ uint8_t RESERVED_2[4]; __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ uint8_t RESERVED_3[4]; __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ uint8_t RESERVED_4[4]; __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ uint8_t RESERVED_5[12]; __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ uint8_t RESERVED_6[156]; __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ uint8_t RESERVED_7[4]; __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ uint8_t RESERVED_8[20]; __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ uint8_t RESERVED_9[12]; __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ uint8_t RESERVED_10[8]; __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ uint8_t RESERVED_11[12]; __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ } LPI2C_Type; /* ---------------------------------------------------------------------------- -- LPI2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPI2C_Register_Masks LPI2C Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) #define LPI2C_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000010..Master only with standard feature set. * 0b0000000000000011..Master and slave with standard feature set. */ #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) #define LPI2C_VERID_MINOR_MASK (0xFF0000U) #define LPI2C_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) #define LPI2C_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) /*! MTXFIFO - Master Transmit FIFO Size */ #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) /*! MRXFIFO - Master Receive FIFO Size */ #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) /*! @} */ /*! @name MCR - Master Control Register */ /*! @{ */ #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) /*! MEN - Master Enable * 0b0..Master logic is disabled. * 0b1..Master logic is enabled. */ #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) #define LPI2C_MCR_RST_MASK (0x2U) #define LPI2C_MCR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Master logic is not reset. * 0b1..Master logic is reset. */ #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) #define LPI2C_MCR_DOZEN_MASK (0x4U) #define LPI2C_MCR_DOZEN_SHIFT (2U) /*! DOZEN - Doze mode enable * 0b0..Master is enabled in Doze mode. * 0b1..Master is disabled in Doze mode. */ #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) #define LPI2C_MCR_DBGEN_MASK (0x8U) #define LPI2C_MCR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable * 0b0..Master is disabled in debug mode. * 0b1..Master is enabled in debug mode. */ #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) #define LPI2C_MCR_RTF_MASK (0x100U) #define LPI2C_MCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect. * 0b1..Transmit FIFO is reset. */ #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) #define LPI2C_MCR_RRF_MASK (0x200U) #define LPI2C_MCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect. * 0b1..Receive FIFO is reset. */ #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) /*! @} */ /*! @name MSR - Master Status Register */ /*! @{ */ #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested. * 0b1..Transmit data is requested. */ #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) #define LPI2C_MSR_RDF_MASK (0x2U) #define LPI2C_MSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive Data is not ready. * 0b1..Receive data is ready. */ #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) #define LPI2C_MSR_EPF_MASK (0x100U) #define LPI2C_MSR_EPF_SHIFT (8U) /*! EPF - End Packet Flag * 0b0..Master has not generated a STOP or Repeated START condition. * 0b1..Master has generated a STOP or Repeated START condition. */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) #define LPI2C_MSR_SDF_MASK (0x200U) #define LPI2C_MSR_SDF_SHIFT (9U) /*! SDF - STOP Detect Flag * 0b0..Master has not generated a STOP condition. * 0b1..Master has generated a STOP condition. */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) /*! NDF - NACK Detect Flag * 0b0..Unexpected NACK not detected. * 0b1..Unexpected NACK was detected. */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) #define LPI2C_MSR_ALF_MASK (0x800U) #define LPI2C_MSR_ALF_SHIFT (11U) /*! ALF - Arbitration Lost Flag * 0b0..Master has not lost arbitration. * 0b1..Master has lost arbitration. */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) #define LPI2C_MSR_FEF_MASK (0x1000U) #define LPI2C_MSR_FEF_SHIFT (12U) /*! FEF - FIFO Error Flag * 0b0..No error. * 0b1..Master sending or receiving data without START condition. */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) /*! PLTF - Pin Low Timeout Flag * 0b0..Pin low timeout has not occurred or is disabled. * 0b1..Pin low timeout has occurred. */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) #define LPI2C_MSR_DMF_MASK (0x4000U) #define LPI2C_MSR_DMF_SHIFT (14U) /*! DMF - Data Match Flag * 0b0..Have not received matching data. * 0b1..Have received matching data. */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_MBF_MASK (0x1000000U) #define LPI2C_MSR_MBF_SHIFT (24U) /*! MBF - Master Busy Flag * 0b0..I2C Master is idle. * 0b1..I2C Master is busy. */ #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) #define LPI2C_MSR_BBF_MASK (0x2000000U) #define LPI2C_MSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag * 0b0..I2C Bus is idle. * 0b1..I2C Bus is busy. */ #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) /*! @} */ /*! @name MIER - Master Interrupt Enable Register */ /*! @{ */ #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled */ #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) #define LPI2C_MIER_RDIE_MASK (0x2U) #define LPI2C_MIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) #define LPI2C_MIER_EPIE_MASK (0x100U) #define LPI2C_MIER_EPIE_SHIFT (8U) /*! EPIE - End Packet Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) #define LPI2C_MIER_SDIE_MASK (0x200U) #define LPI2C_MIER_SDIE_SHIFT (9U) /*! SDIE - STOP Detect Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) #define LPI2C_MIER_NDIE_MASK (0x400U) #define LPI2C_MIER_NDIE_SHIFT (10U) /*! NDIE - NACK Detect Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) #define LPI2C_MIER_ALIE_MASK (0x800U) #define LPI2C_MIER_ALIE_SHIFT (11U) /*! ALIE - Arbitration Lost Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) #define LPI2C_MIER_PLTIE_MASK (0x2000U) #define LPI2C_MIER_PLTIE_SHIFT (13U) /*! PLTIE - Pin Low Timeout Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) /*! DMIE - Data Match Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) /*! @} */ /*! @name MDER - Master DMA Enable Register */ /*! @{ */ #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled */ #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) /*! @} */ /*! @name MCFGR0 - Master Configuration Register 0 */ /*! @{ */ #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) /*! HREN - Host Request Enable * 0b0..Host request input is disabled. * 0b1..Host request input is enabled. */ #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) /*! HRPOL - Host Request Polarity * 0b0..Active low. * 0b1..Active high. */ #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) /*! HRSEL - Host Request Select * 0b0..Host request input is pin LPI2C_HREQ. * 0b1..Host request input is input trigger. */ #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable * 0b0..Circular FIFO is disabled. * 0b1..Circular FIFO is enabled. */ #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO as normal. * 0b1..Received data is discarded unless the RMF is set. */ #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) /*! @} */ /*! @name MCFGR1 - Master Configuration Register 1 */ /*! @{ */ #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) /*! PRESCALE - Prescaler * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 4. * 0b011..Divide by 8. * 0b100..Divide by 16. * 0b101..Divide by 32. * 0b110..Divide by 64. * 0b111..Divide by 128. */ #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) /*! AUTOSTOP - Automatic STOP Generation * 0b0..No effect. * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy. */ #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) /*! IGNACK * 0b0..LPI2C Master will receive ACK and NACK normally. * 0b1..LPI2C Master will treat a received NACK as if it was an ACK. */ #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) /*! TIMECFG - Timeout Configuration * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout. * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout. */ #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match disabled. * 0b001..Reserved. * 0b010..Match enabled (1st data word equals MATCH0 OR MATCH1). * 0b011..Match enabled (any data word equals MATCH0 OR MATCH1). * 0b100..Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). * 0b101..Match enabled (any data word equals MATCH0 AND next data word equals MATCH1). * 0b110..Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1). * 0b111..Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). */ #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b000..LPI2C configured for 2-pin open drain mode. * 0b001..LPI2C configured for 2-pin output only mode (ultra-fast mode). * 0b010..LPI2C configured for 2-pin push-pull mode. * 0b011..LPI2C configured for 4-pin push-pull mode. * 0b100..LPI2C configured for 2-pin open drain mode with separate LPI2C slave. * 0b101..LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave. * 0b110..LPI2C configured for 2-pin push-pull mode with separate LPI2C slave. * 0b111..LPI2C configured for 4-pin push-pull mode (inverted outputs). */ #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) /*! @} */ /*! @name MCFGR2 - Master Configuration Register 2 */ /*! @{ */ #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) /*! BUSIDLE - Bus Idle Timeout */ #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA */ #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) /*! @} */ /*! @name MCFGR3 - Master Configuration Register 3 */ /*! @{ */ #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) /*! PINLOW - Pin Low Timeout */ #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) /*! @} */ /*! @name MDMR - Master Data Match Register */ /*! @{ */ #define LPI2C_MDMR_MATCH0_MASK (0xFFU) #define LPI2C_MDMR_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) #define LPI2C_MDMR_MATCH1_SHIFT (16U) /*! MATCH1 - Match 1 Value */ #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) /*! @} */ /*! @name MCCR0 - Master Clock Configuration Register 0 */ /*! @{ */ #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) #define LPI2C_MCCR0_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR0_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR0_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay */ #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) /*! @} */ /*! @name MCCR1 - Master Clock Configuration Register 1 */ /*! @{ */ #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) #define LPI2C_MCCR1_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR1_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR1_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay */ #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) /*! @} */ /*! @name MFCR - Master FIFO Control Register */ /*! @{ */ #define LPI2C_MFCR_TXWATER_MASK (0xFFU) #define LPI2C_MFCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) #define LPI2C_MFCR_RXWATER_MASK (0xFF0000U) #define LPI2C_MFCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark */ #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) /*! @} */ /*! @name MFSR - Master FIFO Status Register */ /*! @{ */ #define LPI2C_MFSR_TXCOUNT_MASK (0xFFU) #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) #define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U) #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count */ #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) /*! @} */ /*! @name MTDR - Master Transmit Data Register */ /*! @{ */ #define LPI2C_MTDR_DATA_MASK (0xFFU) #define LPI2C_MTDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) /*! CMD - Command Data * 0b000..Transmit DATA[7:0]. * 0b001..Receive (DATA[7:0] + 1) bytes. * 0b010..Generate STOP condition. * 0b011..Receive and discard (DATA[7:0] + 1) bytes. * 0b100..Generate (repeated) START and transmit address in DATA[7:0]. * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. */ #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) /*! @} */ /*! @name MRDR - Master Receive Data Register */ /*! @{ */ #define LPI2C_MRDR_DATA_MASK (0xFFU) #define LPI2C_MRDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty * 0b0..Receive FIFO is not empty. * 0b1..Receive FIFO is empty. */ #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) /*! @} */ /*! @name SCR - Slave Control Register */ /*! @{ */ #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) /*! SEN - Slave Enable * 0b0..Slave mode is disabled. * 0b1..Slave mode is enabled. */ #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) #define LPI2C_SCR_RST_MASK (0x2U) #define LPI2C_SCR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Slave logic is not reset. * 0b1..Slave logic is reset. */ #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) #define LPI2C_SCR_FILTEN_MASK (0x10U) #define LPI2C_SCR_FILTEN_SHIFT (4U) /*! FILTEN - Filter Enable * 0b0..Disable digital filter and output delay counter for slave mode. * 0b1..Enable digital filter and output delay counter for slave mode. */ #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) #define LPI2C_SCR_FILTDZ_MASK (0x20U) #define LPI2C_SCR_FILTDZ_SHIFT (5U) /*! FILTDZ - Filter Doze Enable * 0b0..Filter remains enabled in Doze mode. * 0b1..Filter is disabled in Doze mode. */ #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) #define LPI2C_SCR_RTF_MASK (0x100U) #define LPI2C_SCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect. * 0b1..Transmit Data Register is now empty. */ #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) #define LPI2C_SCR_RRF_MASK (0x200U) #define LPI2C_SCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect. * 0b1..Receive Data Register is now empty. */ #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) /*! @} */ /*! @name SSR - Slave Status Register */ /*! @{ */ #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested. * 0b1..Transmit data is requested. */ #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) #define LPI2C_SSR_RDF_MASK (0x2U) #define LPI2C_SSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive Data is not ready. * 0b1..Receive data is ready. */ #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) #define LPI2C_SSR_AVF_MASK (0x4U) #define LPI2C_SSR_AVF_SHIFT (2U) /*! AVF - Address Valid Flag * 0b0..Address Status Register is not valid. * 0b1..Address Status Register is valid. */ #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) #define LPI2C_SSR_TAF_MASK (0x8U) #define LPI2C_SSR_TAF_SHIFT (3U) /*! TAF - Transmit ACK Flag * 0b0..Transmit ACK/NACK is not required. * 0b1..Transmit ACK/NACK is required. */ #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) /*! RSF - Repeated Start Flag * 0b0..Slave has not detected a Repeated START condition. * 0b1..Slave has detected a Repeated START condition. */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) #define LPI2C_SSR_SDF_MASK (0x200U) #define LPI2C_SSR_SDF_SHIFT (9U) /*! SDF - STOP Detect Flag * 0b0..Slave has not detected a STOP condition. * 0b1..Slave has detected a STOP condition. */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) #define LPI2C_SSR_BEF_MASK (0x400U) #define LPI2C_SSR_BEF_SHIFT (10U) /*! BEF - Bit Error Flag * 0b0..Slave has not detected a bit error. * 0b1..Slave has detected a bit error. */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) #define LPI2C_SSR_FEF_MASK (0x800U) #define LPI2C_SSR_FEF_SHIFT (11U) /*! FEF - FIFO Error Flag * 0b0..FIFO underflow or overflow not detected. * 0b1..FIFO underflow or overflow detected. */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) #define LPI2C_SSR_AM0F_MASK (0x1000U) #define LPI2C_SSR_AM0F_SHIFT (12U) /*! AM0F - Address Match 0 Flag * 0b0..Have not received ADDR0 matching address. * 0b1..Have received ADDR0 matching address. */ #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) #define LPI2C_SSR_AM1F_MASK (0x2000U) #define LPI2C_SSR_AM1F_SHIFT (13U) /*! AM1F - Address Match 1 Flag * 0b0..Have not received ADDR1 or ADDR0/ADDR1 range matching address. * 0b1..Have received ADDR1 or ADDR0/ADDR1 range matching address. */ #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) #define LPI2C_SSR_GCF_MASK (0x4000U) #define LPI2C_SSR_GCF_SHIFT (14U) /*! GCF - General Call Flag * 0b0..Slave has not detected the General Call Address or General Call Address disabled. * 0b1..Slave has detected the General Call Address. */ #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) #define LPI2C_SSR_SARF_MASK (0x8000U) #define LPI2C_SSR_SARF_SHIFT (15U) /*! SARF - SMBus Alert Response Flag * 0b0..SMBus Alert Response disabled or not detected. * 0b1..SMBus Alert Response enabled and detected. */ #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) #define LPI2C_SSR_SBF_MASK (0x1000000U) #define LPI2C_SSR_SBF_SHIFT (24U) /*! SBF - Slave Busy Flag * 0b0..I2C Slave is idle. * 0b1..I2C Slave is busy. */ #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag * 0b0..I2C Bus is idle. * 0b1..I2C Bus is busy. */ #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) /*! @} */ /*! @name SIER - Slave Interrupt Enable Register */ /*! @{ */ #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled */ #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) #define LPI2C_SIER_RDIE_MASK (0x2U) #define LPI2C_SIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) #define LPI2C_SIER_AVIE_MASK (0x4U) #define LPI2C_SIER_AVIE_SHIFT (2U) /*! AVIE - Address Valid Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) #define LPI2C_SIER_TAIE_MASK (0x8U) #define LPI2C_SIER_TAIE_SHIFT (3U) /*! TAIE - Transmit ACK Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) #define LPI2C_SIER_RSIE_MASK (0x100U) #define LPI2C_SIER_RSIE_SHIFT (8U) /*! RSIE - Repeated Start Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) #define LPI2C_SIER_SDIE_MASK (0x200U) #define LPI2C_SIER_SDIE_SHIFT (9U) /*! SDIE - STOP Detect Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) #define LPI2C_SIER_BEIE_MASK (0x400U) #define LPI2C_SIER_BEIE_SHIFT (10U) /*! BEIE - Bit Error Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) #define LPI2C_SIER_FEIE_MASK (0x800U) #define LPI2C_SIER_FEIE_SHIFT (11U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) #define LPI2C_SIER_AM0IE_MASK (0x1000U) #define LPI2C_SIER_AM0IE_SHIFT (12U) /*! AM0IE - Address Match 0 Interrupt Enable * 0b0..Interrupt enabled. * 0b1..Interrupt disabled. */ #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) #define LPI2C_SIER_AM1F_MASK (0x2000U) #define LPI2C_SIER_AM1F_SHIFT (13U) /*! AM1F - Address Match 1 Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) #define LPI2C_SIER_GCIE_MASK (0x4000U) #define LPI2C_SIER_GCIE_SHIFT (14U) /*! GCIE - General Call Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) /*! SARIE - SMBus Alert Response Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) /*! @} */ /*! @name SDER - Slave DMA Enable Register */ /*! @{ */ #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled */ #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) #define LPI2C_SDER_RDDE_MASK (0x2U) #define LPI2C_SDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) /*! AVDE - Address Valid DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) /*! @} */ /*! @name SCFGR1 - Slave Configuration Register 1 */ /*! @{ */ #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) /*! ADRSTALL - Address SCL Stall * 0b0..Clock stretching disabled. * 0b1..Clock stretching enabled. */ #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) /*! RXSTALL - RX SCL Stall * 0b0..Clock stretching disabled. * 0b1..Clock stretching enabled. */ #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) /*! TXDSTALL - TX Data SCL Stall * 0b0..Clock stretching disabled. * 0b1..Clock stretching enabled. */ #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) /*! ACKSTALL - ACK SCL Stall * 0b0..Clock stretching disabled. * 0b1..Clock stretching enabled. */ #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) #define LPI2C_SCFGR1_GCEN_MASK (0x100U) #define LPI2C_SCFGR1_GCEN_SHIFT (8U) /*! GCEN - General Call Enable * 0b0..General Call address is disabled. * 0b1..General call address is enabled. */ #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) #define LPI2C_SCFGR1_SAEN_MASK (0x200U) #define LPI2C_SCFGR1_SAEN_SHIFT (9U) /*! SAEN - SMBus Alert Enable * 0b0..Disables match on SMBus Alert. * 0b1..Enables match on SMBus Alert. */ #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) /*! TXCFG - Transmit Flag Configuration * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty. * 0b1..Transmit Data Flag will assert whenever the transmit data register is empty. */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration * 0b0..Reading the receive data register will return receive data and clear the receive data flag. * 0b1..Reading the receive data register when the address valid flag is set will return the address status * register and clear the address valid flag. Reading the receive data register when the address valid flag is * clear will return receive data and clear the receive data flag. */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) /*! IGNACK - Ignore NACK * 0b0..Slave will end transfer when NACK detected. * 0b1..Slave will not end transfer when NACK detected. */ #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) /*! HSMEN - High Speed Mode Enable * 0b0..Disables detection of Hs-mode master code. * 0b1..Enables detection of Hs-mode master code. */ #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) /*! ADDRCFG - Address Configuration * 0b000..Address match 0 (7-bit). * 0b001..Address match 0 (10-bit). * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit). * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit). * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit). * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit). * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit). * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit). */ #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) /*! @} */ /*! @name SCFGR2 - Slave Configuration Register 2 */ /*! @{ */ #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) /*! CLKHOLD - Clock Hold Time */ #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) /*! DATAVD - Data Valid Delay */ #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA */ #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) /*! @} */ /*! @name SAMR - Slave Address Match Register */ /*! @{ */ #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) /*! ADDR0 - Address 0 Value */ #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) /*! ADDR1 - Address 1 Value */ #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) /*! @} */ /*! @name SASR - Slave Address Status Register */ /*! @{ */ #define LPI2C_SASR_RADDR_MASK (0x7FFU) #define LPI2C_SASR_RADDR_SHIFT (0U) /*! RADDR - Received Address */ #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) /*! ANV - Address Not Valid * 0b0..RADDR is valid. * 0b1..RADDR is not valid. */ #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) /*! @} */ /*! @name STAR - Slave Transmit ACK Register */ /*! @{ */ #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) /*! TXNACK - Transmit NACK * 0b0..Transmit ACK for received word. * 0b1..Transmit NACK for received word. */ #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) /*! @} */ /*! @name STDR - Slave Transmit Data Register */ /*! @{ */ #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) /*! @} */ /*! @name SRDR - Slave Receive Data Register */ /*! @{ */ #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty * 0b0..The Receive Data Register is not empty. * 0b1..The Receive Data Register is empty. */ #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) /*! SOF - Start Of Frame * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition. * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition. */ #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) /*! @} */ /*! * @} */ /* end of group LPI2C_Register_Masks */ /* LPI2C - Peripheral instance base addresses */ /** Peripheral LPI2C0 base address */ #define LPI2C0_BASE (0x40066000u) /** Peripheral LPI2C0 base pointer */ #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) /** Peripheral LPI2C1 base address */ #define LPI2C1_BASE (0x40067000u) /** Peripheral LPI2C1 base pointer */ #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) /** Array initializer of LPI2C peripheral base addresses */ #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE } /** Array initializer of LPI2C peripheral base pointers */ #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1 } /** Interrupt vectors for the LPI2C peripheral type */ #define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn } /*! * @} */ /* end of group LPI2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPIT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer * @{ */ /** LPIT - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */ __IO uint32_t MSR; /**< Module Status Register, offset: 0xC */ __IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */ __IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */ __O uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */ uint8_t RESERVED_0[4]; struct { /* offset: 0x20, array step: 0x10 */ __IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */ __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */ uint8_t RESERVED_0[4]; } CHANNEL[4]; } LPIT_Type; /* ---------------------------------------------------------------------------- -- LPIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPIT_Register_Masks LPIT Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPIT_VERID_FEATURE_MASK (0xFFFFU) #define LPIT_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Number */ #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) #define LPIT_VERID_MINOR_MASK (0xFF0000U) #define LPIT_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) #define LPIT_VERID_MAJOR_MASK (0xFF000000U) #define LPIT_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPIT_PARAM_CHANNEL_MASK (0xFFU) #define LPIT_PARAM_CHANNEL_SHIFT (0U) /*! CHANNEL - Number of Timer Channels */ #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) #define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) #define LPIT_PARAM_EXT_TRIG_SHIFT (8U) /*! EXT_TRIG - Number of External Trigger Inputs */ #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) /*! @} */ /*! @name MCR - Module Control Register */ /*! @{ */ #define LPIT_MCR_M_CEN_MASK (0x1U) #define LPIT_MCR_M_CEN_SHIFT (0U) /*! M_CEN - Module Clock Enable * 0b0..Protocol clock to timers is disabled * 0b1..Protocol clock to timers is enabled */ #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) #define LPIT_MCR_SW_RST_MASK (0x2U) #define LPIT_MCR_SW_RST_SHIFT (1U) /*! SW_RST - Software Reset Bit * 0b0..Timer channels and registers are not reset * 0b1..Timer channels and registers are reset */ #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) #define LPIT_MCR_DOZE_EN_MASK (0x4U) #define LPIT_MCR_DOZE_EN_SHIFT (2U) /*! DOZE_EN - DOZE Mode Enable Bit * 0b0..Timer channels are stopped in DOZE mode * 0b1..Timer channels continue to run in DOZE mode */ #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) #define LPIT_MCR_DBG_EN_MASK (0x8U) #define LPIT_MCR_DBG_EN_SHIFT (3U) /*! DBG_EN - Debug Enable Bit * 0b0..Timer channels are stopped in Debug mode * 0b1..Timer channels continue to run in Debug mode */ #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) /*! @} */ /*! @name MSR - Module Status Register */ /*! @{ */ #define LPIT_MSR_TIF0_MASK (0x1U) #define LPIT_MSR_TIF0_SHIFT (0U) /*! TIF0 - Channel 0 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred */ #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) #define LPIT_MSR_TIF1_MASK (0x2U) #define LPIT_MSR_TIF1_SHIFT (1U) /*! TIF1 - Channel 1 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred */ #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) #define LPIT_MSR_TIF2_MASK (0x4U) #define LPIT_MSR_TIF2_SHIFT (2U) /*! TIF2 - Channel 2 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred */ #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) #define LPIT_MSR_TIF3_MASK (0x8U) #define LPIT_MSR_TIF3_SHIFT (3U) /*! TIF3 - Channel 3 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred */ #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) /*! @} */ /*! @name MIER - Module Interrupt Enable Register */ /*! @{ */ #define LPIT_MIER_TIE0_MASK (0x1U) #define LPIT_MIER_TIE0_SHIFT (0U) /*! TIE0 - Channel 0 Timer Interrupt Enable * 0b0..Interrupt generation is disabled * 0b1..Interrupt generation is enabled */ #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) #define LPIT_MIER_TIE1_MASK (0x2U) #define LPIT_MIER_TIE1_SHIFT (1U) /*! TIE1 - Channel 1 Timer Interrupt Enable * 0b0..Interrupt generation is disabled * 0b1..Interrupt generation is enabled */ #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) #define LPIT_MIER_TIE2_MASK (0x4U) #define LPIT_MIER_TIE2_SHIFT (2U) /*! TIE2 - Channel 2 Timer Interrupt Enable * 0b0..Interrupt generation is disabled * 0b1..Interrupt generation is enabled */ #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) #define LPIT_MIER_TIE3_MASK (0x8U) #define LPIT_MIER_TIE3_SHIFT (3U) /*! TIE3 - Channel 3 Timer Interrupt Enable * 0b0..Interrupt generation is disabled * 0b1..Interrupt generation is enabled */ #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) /*! @} */ /*! @name SETTEN - Set Timer Enable Register */ /*! @{ */ #define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) #define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) /*! SET_T_EN_0 - Set Timer 0 Enable * 0b0..No effect * 0b1..Enables the Timer Channel 0 */ #define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) #define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) #define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) /*! SET_T_EN_1 - Set Timer 1 Enable * 0b0..No Effect * 0b1..Enables the Timer Channel 1 */ #define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) #define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) #define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) /*! SET_T_EN_2 - Set Timer 2 Enable * 0b0..No Effect * 0b1..Enables the Timer Channel 2 */ #define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) #define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) #define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) /*! SET_T_EN_3 - Set Timer 3 Enable * 0b0..No effect * 0b1..Enables the Timer Channel 3 */ #define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) /*! @} */ /*! @name CLRTEN - Clear Timer Enable Register */ /*! @{ */ #define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) /*! CLR_T_EN_0 - Clear Timer 0 Enable * 0b0..No action * 0b1..Clear T_EN bit for Timer Channel 0 */ #define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) #define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) /*! CLR_T_EN_1 - Clear Timer 1 Enable * 0b0..No Action * 0b1..Clear T_EN bit for Timer Channel 1 */ #define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) #define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) /*! CLR_T_EN_2 - Clear Timer 2 Enable * 0b0..No Action * 0b1..Clear T_EN bit for Timer Channel 2 */ #define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) #define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) /*! CLR_T_EN_3 - Clear Timer 3 Enable * 0b0..No Action * 0b1..Clear T_EN bit for Timer Channel 3 */ #define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) /*! @} */ /*! @name TVAL - Timer Value Register */ /*! @{ */ #define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) #define LPIT_TVAL_TMR_VAL_SHIFT (0U) /*! TMR_VAL - Timer Value * 0b00000000000000000000000000000000..Invalid load value in compare modes */ #define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK) /*! @} */ /* The count of LPIT_TVAL */ #define LPIT_TVAL_COUNT (4U) /*! @name CVAL - Current Timer Value */ /*! @{ */ #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) #define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U) /*! TMR_CUR_VAL - Current Timer Value */ #define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK) /*! @} */ /* The count of LPIT_CVAL */ #define LPIT_CVAL_COUNT (4U) /*! @name TCTRL - Timer Control Register */ /*! @{ */ #define LPIT_TCTRL_T_EN_MASK (0x1U) #define LPIT_TCTRL_T_EN_SHIFT (0U) /*! T_EN - Timer Enable * 0b0..Timer Channel is disabled * 0b1..Timer Channel is enabled */ #define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK) #define LPIT_TCTRL_CHAIN_MASK (0x2U) #define LPIT_TCTRL_CHAIN_SHIFT (1U) /*! CHAIN - Chain Channel * 0b0..Channel Chaining is disabled. Channel Timer runs independently. * 0b1..Channel Chaining is enabled. Timer decrements on previous channel's timeout */ #define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK) #define LPIT_TCTRL_MODE_MASK (0xCU) #define LPIT_TCTRL_MODE_SHIFT (2U) /*! MODE - Timer Operation Mode * 0b00..32-bit Periodic Counter * 0b01..Dual 16-bit Periodic Counter * 0b10..32-bit Trigger Accumulator * 0b11..32-bit Trigger Input Capture */ #define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK) #define LPIT_TCTRL_TSOT_MASK (0x10000U) #define LPIT_TCTRL_TSOT_SHIFT (16U) /*! TSOT - Timer Start On Trigger * 0b0..Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) * 0b1..Timer starts to decrement when rising edge on selected trigger is detected */ #define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK) #define LPIT_TCTRL_TSOI_MASK (0x20000U) #define LPIT_TCTRL_TSOI_SHIFT (17U) /*! TSOI - Timer Stop On Interrupt * 0b0..Timer does not stop after timeout * 0b1..Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer * channel is disabled and then enabled) */ #define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK) #define LPIT_TCTRL_TROT_MASK (0x40000U) #define LPIT_TCTRL_TROT_SHIFT (18U) /*! TROT - Timer Reload On Trigger * 0b0..Timer will not reload on selected trigger * 0b1..Timer will reload on selected trigger */ #define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK) #define LPIT_TCTRL_TRG_SRC_MASK (0x800000U) #define LPIT_TCTRL_TRG_SRC_SHIFT (23U) /*! TRG_SRC - Trigger Source * 0b0..Trigger source selected in external * 0b1..Trigger source selected is the internal trigger */ #define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK) #define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U) #define LPIT_TCTRL_TRG_SEL_SHIFT (24U) /*! TRG_SEL - Trigger Select * 0b0000..Timer channel 0 trigger source is selected * 0b0001..Timer channel 1 trigger source is selected * 0b0010..Timer channel 2 trigger source is selected */ #define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK) /*! @} */ /* The count of LPIT_TCTRL */ #define LPIT_TCTRL_COUNT (4U) /*! * @} */ /* end of group LPIT_Register_Masks */ /* LPIT - Peripheral instance base addresses */ /** Peripheral LPIT0 base address */ #define LPIT0_BASE (0x40037000u) /** Peripheral LPIT0 base pointer */ #define LPIT0 ((LPIT_Type *)LPIT0_BASE) /** Array initializer of LPIT peripheral base addresses */ #define LPIT_BASE_ADDRS { LPIT0_BASE } /** Array initializer of LPIT peripheral base pointers */ #define LPIT_BASE_PTRS { LPIT0 } /** Interrupt vectors for the LPIT peripheral type */ #define LPIT_IRQS { { LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn } } /*! * @} */ /* end of group LPIT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer * @{ */ /** LPSPI - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t CR; /**< Control Register, offset: 0x10 */ __IO uint32_t SR; /**< Status Register, offset: 0x14 */ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ uint8_t RESERVED_2[8]; __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ uint8_t RESERVED_3[20]; __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ uint8_t RESERVED_4[8]; __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ } LPSPI_Type; /* ---------------------------------------------------------------------------- -- LPSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPSPI_Register_Masks LPSPI Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) #define LPSPI_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Module Identification Number * 0b0000000000000100..Standard feature set supporting 32-bit shift register. */ #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) #define LPSPI_VERID_MINOR_MASK (0xFF0000U) #define LPSPI_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) #define LPSPI_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) #define LPSPI_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) #define LPSPI_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) /*! @} */ /*! @name CR - Control Register */ /*! @{ */ #define LPSPI_CR_MEN_MASK (0x1U) #define LPSPI_CR_MEN_SHIFT (0U) /*! MEN - Module Enable * 0b0..Module is disabled. * 0b1..Module is enabled. */ #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) #define LPSPI_CR_RST_MASK (0x2U) #define LPSPI_CR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Master logic is not reset. * 0b1..Master logic is reset. */ #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) #define LPSPI_CR_DOZEN_MASK (0x4U) #define LPSPI_CR_DOZEN_SHIFT (2U) /*! DOZEN - Doze mode enable * 0b0..Module is enabled in Doze mode. * 0b1..Module is disabled in Doze mode. */ #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) #define LPSPI_CR_DBGEN_MASK (0x8U) #define LPSPI_CR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable * 0b0..Module is disabled in debug mode. * 0b1..Module is enabled in debug mode. */ #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) #define LPSPI_CR_RTF_MASK (0x100U) #define LPSPI_CR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect. * 0b1..Transmit FIFO is reset. */ #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) #define LPSPI_CR_RRF_MASK (0x200U) #define LPSPI_CR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect. * 0b1..Receive FIFO is reset. */ #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define LPSPI_SR_TDF_MASK (0x1U) #define LPSPI_SR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested. * 0b1..Transmit data is requested. */ #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) #define LPSPI_SR_RDF_MASK (0x2U) #define LPSPI_SR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive Data is not ready. * 0b1..Receive data is ready. */ #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) #define LPSPI_SR_WCF_MASK (0x100U) #define LPSPI_SR_WCF_SHIFT (8U) /*! WCF - Word Complete Flag * 0b0..Transfer word not completed. * 0b1..Transfer word completed. */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) #define LPSPI_SR_FCF_MASK (0x200U) #define LPSPI_SR_FCF_SHIFT (9U) /*! FCF - Frame Complete Flag * 0b0..Frame transfer has not completed. * 0b1..Frame transfer has completed. */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) #define LPSPI_SR_TCF_MASK (0x400U) #define LPSPI_SR_TCF_SHIFT (10U) /*! TCF - Transfer Complete Flag * 0b0..All transfers have not completed. * 0b1..All transfers have completed. */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) #define LPSPI_SR_TEF_MASK (0x800U) #define LPSPI_SR_TEF_SHIFT (11U) /*! TEF - Transmit Error Flag * 0b0..Transmit FIFO underrun has not occurred. * 0b1..Transmit FIFO underrun has occurred */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) #define LPSPI_SR_REF_MASK (0x1000U) #define LPSPI_SR_REF_SHIFT (12U) /*! REF - Receive Error Flag * 0b0..Receive FIFO has not overflowed. * 0b1..Receive FIFO has overflowed. */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) #define LPSPI_SR_DMF_MASK (0x2000U) #define LPSPI_SR_DMF_SHIFT (13U) /*! DMF - Data Match Flag * 0b0..Have not received matching data. * 0b1..Have received matching data. */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) #define LPSPI_SR_MBF_MASK (0x1000000U) #define LPSPI_SR_MBF_SHIFT (24U) /*! MBF - Module Busy Flag * 0b0..LPSPI is idle. * 0b1..LPSPI is busy. */ #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) /*! @} */ /*! @name IER - Interrupt Enable Register */ /*! @{ */ #define LPSPI_IER_TDIE_MASK (0x1U) #define LPSPI_IER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled */ #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) #define LPSPI_IER_RDIE_MASK (0x2U) #define LPSPI_IER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) #define LPSPI_IER_WCIE_MASK (0x100U) #define LPSPI_IER_WCIE_SHIFT (8U) /*! WCIE - Word Complete Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) #define LPSPI_IER_FCIE_MASK (0x200U) #define LPSPI_IER_FCIE_SHIFT (9U) /*! FCIE - Frame Complete Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) #define LPSPI_IER_TCIE_MASK (0x400U) #define LPSPI_IER_TCIE_SHIFT (10U) /*! TCIE - Transfer Complete Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) #define LPSPI_IER_TEIE_MASK (0x800U) #define LPSPI_IER_TEIE_SHIFT (11U) /*! TEIE - Transmit Error Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) #define LPSPI_IER_REIE_MASK (0x1000U) #define LPSPI_IER_REIE_SHIFT (12U) /*! REIE - Receive Error Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) #define LPSPI_IER_DMIE_MASK (0x2000U) #define LPSPI_IER_DMIE_SHIFT (13U) /*! DMIE - Data Match Interrupt Enable * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) /*! @} */ /*! @name DER - DMA Enable Register */ /*! @{ */ #define LPSPI_DER_TDDE_MASK (0x1U) #define LPSPI_DER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled */ #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) #define LPSPI_DER_RDDE_MASK (0x2U) #define LPSPI_DER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) /*! @} */ /*! @name CFGR0 - Configuration Register 0 */ /*! @{ */ #define LPSPI_CFGR0_HREN_MASK (0x1U) #define LPSPI_CFGR0_HREN_SHIFT (0U) /*! HREN - Host Request Enable * 0b0..Host request is disabled. * 0b1..Host request is enabled. */ #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) #define LPSPI_CFGR0_HRPOL_MASK (0x2U) #define LPSPI_CFGR0_HRPOL_SHIFT (1U) /*! HRPOL - Host Request Polarity * 0b0..Active low. * 0b1..Active high. */ #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) #define LPSPI_CFGR0_HRSEL_MASK (0x4U) #define LPSPI_CFGR0_HRSEL_SHIFT (2U) /*! HRSEL - Host Request Select * 0b0..Host request input is pin LPSPI_HREQ. * 0b1..Host request input is input trigger. */ #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable * 0b0..Circular FIFO is disabled. * 0b1..Circular FIFO is enabled. */ #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) #define LPSPI_CFGR0_RDMO_MASK (0x200U) #define LPSPI_CFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO as normal. * 0b1..Received data is discarded unless the DMF is set. */ #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) /*! @} */ /*! @name CFGR1 - Configuration Register 1 */ /*! @{ */ #define LPSPI_CFGR1_MASTER_MASK (0x1U) #define LPSPI_CFGR1_MASTER_SHIFT (0U) /*! MASTER - Master Mode * 0b0..Slave mode. * 0b1..Master mode. */ #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) /*! SAMPLE - Sample Point * 0b0..Input data sampled on SCK edge. * 0b1..Input data sampled on delayed SCK edge. */ #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) /*! AUTOPCS - Automatic PCS * 0b0..Automatic PCS generation disabled. * 0b1..Automatic PCS generation enabled. */ #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) /*! NOSTALL - No Stall * 0b0..Transfers will stall when transmit FIFO is empty or receive FIFO is full. * 0b1..Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur. */ #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) /*! PCSPOL - Peripheral Chip Select Polarity * 0b0000..The PCSx is active low. * 0b0001..The PCSx is active high. */ #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) #define LPSPI_CFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match disabled. * 0b001..Reserved * 0b010..Match enabled (1st data word equals MATCH0 OR MATCH1). * 0b011..Match enabled (any data word equals MATCH0 OR MATCH1). * 0b100..Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). * 0b101..Match enabled (any data word equals MATCH0 AND next data word equals MATCH1) * 0b110..Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) * 0b111..Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). */ #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) #define LPSPI_CFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b00..SIN is used for input data and SOUT for output data. * 0b01..SIN is used for both input and output data. * 0b10..SOUT is used for both input and output data. * 0b11..SOUT is used for input data and SIN for output data. */ #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) /*! OUTCFG - Output Config * 0b0..Output data retains last value when chip select is negated. * 0b1..Output data is tristated when chip select is negated. */ #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) /*! PCSCFG - Peripheral Chip Select Configuration * 0b0..PCS[3:2] are enabled. * 0b1..PCS[3:2] are disabled. */ #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) /*! @} */ /*! @name DMR0 - Data Match Register 0 */ /*! @{ */ #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) #define LPSPI_DMR0_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) /*! @} */ /*! @name DMR1 - Data Match Register 1 */ /*! @{ */ #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) #define LPSPI_DMR1_MATCH1_SHIFT (0U) /*! MATCH1 - Match 1 Value */ #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) /*! @} */ /*! @name CCR - Clock Configuration Register */ /*! @{ */ #define LPSPI_CCR_SCKDIV_MASK (0xFFU) #define LPSPI_CCR_SCKDIV_SHIFT (0U) /*! SCKDIV - SCK Divider */ #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) #define LPSPI_CCR_DBT_MASK (0xFF00U) #define LPSPI_CCR_DBT_SHIFT (8U) /*! DBT - Delay Between Transfers */ #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) #define LPSPI_CCR_PCSSCK_SHIFT (16U) /*! PCSSCK - PCS to SCK Delay */ #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) #define LPSPI_CCR_SCKPCS_SHIFT (24U) /*! SCKPCS - SCK to PCS Delay */ #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) /*! @} */ /*! @name FCR - FIFO Control Register */ /*! @{ */ #define LPSPI_FCR_TXWATER_MASK (0xFFU) #define LPSPI_FCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) #define LPSPI_FCR_RXWATER_MASK (0xFF0000U) #define LPSPI_FCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark */ #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) /*! @} */ /*! @name FSR - FIFO Status Register */ /*! @{ */ #define LPSPI_FSR_TXCOUNT_MASK (0xFFU) #define LPSPI_FSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) #define LPSPI_FSR_RXCOUNT_MASK (0xFF0000U) #define LPSPI_FSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count */ #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) /*! @} */ /*! @name TCR - Transmit Command Register */ /*! @{ */ #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) #define LPSPI_TCR_FRAMESZ_SHIFT (0U) /*! FRAMESZ - Frame Size */ #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) #define LPSPI_TCR_WIDTH_MASK (0x30000U) #define LPSPI_TCR_WIDTH_SHIFT (16U) /*! WIDTH - Transfer Width * 0b00..Single bit transfer. * 0b01..Two bit transfer. * 0b10..Four bit transfer. * 0b11..Reserved. */ #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) #define LPSPI_TCR_TXMSK_MASK (0x40000U) #define LPSPI_TCR_TXMSK_SHIFT (18U) /*! TXMSK - Transmit Data Mask * 0b0..Normal transfer. * 0b1..Mask transmit data. */ #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) #define LPSPI_TCR_RXMSK_MASK (0x80000U) #define LPSPI_TCR_RXMSK_SHIFT (19U) /*! RXMSK - Receive Data Mask * 0b0..Normal transfer. * 0b1..Receive data is masked. */ #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) #define LPSPI_TCR_CONTC_MASK (0x100000U) #define LPSPI_TCR_CONTC_SHIFT (20U) /*! CONTC - Continuing Command * 0b0..Command word for start of new transfer. * 0b1..Command word for continuing transfer. */ #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) #define LPSPI_TCR_CONT_MASK (0x200000U) #define LPSPI_TCR_CONT_SHIFT (21U) /*! CONT - Continuous Transfer * 0b0..Continuous transfer disabled. * 0b1..Continuous transfer enabled. */ #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) #define LPSPI_TCR_BYSW_MASK (0x400000U) #define LPSPI_TCR_BYSW_SHIFT (22U) /*! BYSW - Byte Swap * 0b0..Byte swap disabled. * 0b1..Byte swap enabled. */ #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) #define LPSPI_TCR_LSBF_MASK (0x800000U) #define LPSPI_TCR_LSBF_SHIFT (23U) /*! LSBF - LSB First * 0b0..Data is transferred MSB first. * 0b1..Data is transferred LSB first. */ #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) #define LPSPI_TCR_PCS_MASK (0x3000000U) #define LPSPI_TCR_PCS_SHIFT (24U) /*! PCS - Peripheral Chip Select * 0b00..Transfer using LPSPI_PCS[0] * 0b01..Transfer using LPSPI_PCS[1] * 0b10..Transfer using LPSPI_PCS[2] * 0b11..Transfer using LPSPI_PCS[3] */ #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) #define LPSPI_TCR_PRESCALE_SHIFT (27U) /*! PRESCALE - Prescaler Value * 0b000..Divide by 1. * 0b001..Divide by 2. * 0b010..Divide by 4. * 0b011..Divide by 8. * 0b100..Divide by 16. * 0b101..Divide by 32. * 0b110..Divide by 64. * 0b111..Divide by 128. */ #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) #define LPSPI_TCR_CPHA_MASK (0x40000000U) #define LPSPI_TCR_CPHA_SHIFT (30U) /*! CPHA - Clock Phase * 0b0..Data is captured on the leading edge of SCK and changed on the following edge. * 0b1..Data is changed on the leading edge of SCK and captured on the following edge. */ #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) #define LPSPI_TCR_CPOL_MASK (0x80000000U) #define LPSPI_TCR_CPOL_SHIFT (31U) /*! CPOL - Clock Polarity * 0b0..The inactive state value of SCK is low. * 0b1..The inactive state value of SCK is high. */ #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) /*! @} */ /*! @name TDR - Transmit Data Register */ /*! @{ */ #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) /*! @} */ /*! @name RSR - Receive Status Register */ /*! @{ */ #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) /*! SOF - Start Of Frame * 0b0..Subsequent data word received after LPSPI_PCS assertion. * 0b1..First data word received after LPSPI_PCS assertion. */ #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) #define LPSPI_RSR_RXEMPTY_MASK (0x2U) #define LPSPI_RSR_RXEMPTY_SHIFT (1U) /*! RXEMPTY - RX FIFO Empty * 0b0..RX FIFO is not empty. * 0b1..RX FIFO is empty. */ #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) /*! @} */ /*! @name RDR - Receive Data Register */ /*! @{ */ #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group LPSPI_Register_Masks */ /* LPSPI - Peripheral instance base addresses */ /** Peripheral LPSPI0 base address */ #define LPSPI0_BASE (0x4002C000u) /** Peripheral LPSPI0 base pointer */ #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) /** Peripheral LPSPI1 base address */ #define LPSPI1_BASE (0x4002D000u) /** Peripheral LPSPI1 base pointer */ #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) /** Array initializer of LPSPI peripheral base addresses */ #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } /** Array initializer of LPSPI peripheral base pointers */ #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } /** Interrupt vectors for the LPSPI peripheral type */ #define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } /*! * @} */ /* end of group LPSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPTMR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer * @{ */ /** LPTMR - Register Layout Typedef */ typedef struct { __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ } LPTMR_Type; /* ---------------------------------------------------------------------------- -- LPTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Register_Masks LPTMR Register Masks * @{ */ /*! @name CSR - Low Power Timer Control Status Register */ /*! @{ */ #define LPTMR_CSR_TEN_MASK (0x1U) #define LPTMR_CSR_TEN_SHIFT (0U) /*! TEN - Timer Enable * 0b0..LPTMR is disabled and internal logic is reset. * 0b1..LPTMR is enabled. */ #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) #define LPTMR_CSR_TMS_MASK (0x2U) #define LPTMR_CSR_TMS_SHIFT (1U) /*! TMS - Timer Mode Select * 0b0..Time Counter mode. * 0b1..Pulse Counter mode. */ #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) #define LPTMR_CSR_TFC_MASK (0x4U) #define LPTMR_CSR_TFC_SHIFT (2U) /*! TFC - Timer Free-Running Counter * 0b0..CNR is reset whenever TCF is set. * 0b1..CNR is reset on overflow. */ #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) #define LPTMR_CSR_TPP_MASK (0x8U) #define LPTMR_CSR_TPP_SHIFT (3U) /*! TPP - Timer Pin Polarity * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. */ #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) #define LPTMR_CSR_TPS_MASK (0x30U) #define LPTMR_CSR_TPS_SHIFT (4U) /*! TPS - Timer Pin Select * 0b00..Pulse counter input 0 is selected. * 0b01..Pulse counter input 1 is selected. * 0b10..Pulse counter input 2 is selected. * 0b11..Pulse counter input 3 is selected. */ #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) #define LPTMR_CSR_TIE_MASK (0x40U) #define LPTMR_CSR_TIE_SHIFT (6U) /*! TIE - Timer Interrupt Enable * 0b0..Timer interrupt disabled. * 0b1..Timer interrupt enabled. */ #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) #define LPTMR_CSR_TCF_MASK (0x80U) #define LPTMR_CSR_TCF_SHIFT (7U) /*! TCF - Timer Compare Flag * 0b0..The value of CNR is not equal to CMR and increments. * 0b1..The value of CNR is equal to CMR and increments. */ #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) #define LPTMR_CSR_TDRE_MASK (0x100U) #define LPTMR_CSR_TDRE_SHIFT (8U) /*! TDRE - Timer DMA Request Enable * 0b0..Timer DMA Request disabled. * 0b1..Timer DMA Request enabled. */ #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) /*! @} */ /*! @name PSR - Low Power Timer Prescale Register */ /*! @{ */ #define LPTMR_PSR_PCS_MASK (0x3U) #define LPTMR_PSR_PCS_SHIFT (0U) /*! PCS - Prescaler Clock Select * 0b00..Prescaler/glitch filter clock 0 selected. * 0b01..Prescaler/glitch filter clock 1 selected. * 0b10..Prescaler/glitch filter clock 2 selected. * 0b11..Prescaler/glitch filter clock 3 selected. */ #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) #define LPTMR_PSR_PBYP_MASK (0x4U) #define LPTMR_PSR_PBYP_SHIFT (2U) /*! PBYP - Prescaler Bypass * 0b0..Prescaler/glitch filter is enabled. * 0b1..Prescaler/glitch filter is bypassed. */ #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) #define LPTMR_PSR_PRESCALE_MASK (0x78U) #define LPTMR_PSR_PRESCALE_SHIFT (3U) /*! PRESCALE - Prescale Value * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. */ #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) /*! @} */ /*! @name CMR - Low Power Timer Compare Register */ /*! @{ */ #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) #define LPTMR_CMR_COMPARE_SHIFT (0U) /*! COMPARE - Compare Value */ #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) /*! @} */ /*! @name CNR - Low Power Timer Counter Register */ /*! @{ */ #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) #define LPTMR_CNR_COUNTER_SHIFT (0U) /*! COUNTER - Counter Value */ #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) /*! @} */ /*! * @} */ /* end of group LPTMR_Register_Masks */ /* LPTMR - Peripheral instance base addresses */ /** Peripheral LPTMR0 base address */ #define LPTMR0_BASE (0x40040000u) /** Peripheral LPTMR0 base pointer */ #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) /** Array initializer of LPTMR peripheral base addresses */ #define LPTMR_BASE_ADDRS { LPTMR0_BASE } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS { LPTMR0 } /** Interrupt vectors for the LPTMR peripheral type */ #define LPTMR_IRQS { PWT_LPTMR0_IRQn } /*! * @} */ /* end of group LPTMR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPUART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer * @{ */ /** LPUART - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ } LPUART_Type; /* ---------------------------------------------------------------------------- -- LPUART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Register_Masks LPUART Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPUART_VERID_FEATURE_MASK (0xFFFFU) #define LPUART_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number * 0b0000000000000001..Standard feature set. * 0b0000000000000011..Standard feature set with MODEM/IrDA support. */ #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) #define LPUART_VERID_MINOR_MASK (0xFF0000U) #define LPUART_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) #define LPUART_VERID_MAJOR_MASK (0xFF000000U) #define LPUART_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPUART_PARAM_TXFIFO_MASK (0xFFU) #define LPUART_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) #define LPUART_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) /*! @} */ /*! @name GLOBAL - LPUART Global Register */ /*! @{ */ #define LPUART_GLOBAL_RST_MASK (0x2U) #define LPUART_GLOBAL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Module is not reset. * 0b1..Module is reset. */ #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) /*! @} */ /*! @name PINCFG - LPUART Pin Configuration Register */ /*! @{ */ #define LPUART_PINCFG_TRGSEL_MASK (0x3U) #define LPUART_PINCFG_TRGSEL_SHIFT (0U) /*! TRGSEL - Trigger Select * 0b00..Input trigger is disabled. * 0b01..Input trigger is used instead of RXD pin input. * 0b10..Input trigger is used instead of CTS_B pin input. * 0b11..Input trigger is used to modulate the TXD pin output. */ #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) /*! @} */ /*! @name BAUD - LPUART Baud Rate Register */ /*! @{ */ #define LPUART_BAUD_SBR_MASK (0x1FFFU) #define LPUART_BAUD_SBR_SHIFT (0U) /*! SBR - Baud Rate Modulo Divisor. */ #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) #define LPUART_BAUD_SBNS_MASK (0x2000U) #define LPUART_BAUD_SBNS_SHIFT (13U) /*! SBNS - Stop Bit Number Select * 0b0..One stop bit. * 0b1..Two stop bits. */ #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) #define LPUART_BAUD_RXEDGIE_SHIFT (14U) /*! RXEDGIE - RX Input Active Edge Interrupt Enable * 0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). * 0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. */ #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) #define LPUART_BAUD_LBKDIE_MASK (0x8000U) #define LPUART_BAUD_LBKDIE_SHIFT (15U) /*! LBKDIE - LIN Break Detect Interrupt Enable * 0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). * 0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. */ #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) /*! RESYNCDIS - Resynchronization Disable * 0b0..Resynchronization during received data word is supported * 0b1..Resynchronization during received data word is disabled */ #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) /*! BOTHEDGE - Both Edge Sampling * 0b0..Receiver samples input data using the rising edge of the baud rate clock. * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. */ #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) /*! MATCFG - Match Configuration * 0b00..Address Match Wakeup * 0b01..Idle Match Wakeup * 0b10..Match On and Match Off * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) #define LPUART_BAUD_RIDMAE_MASK (0x100000U) #define LPUART_BAUD_RIDMAE_SHIFT (20U) /*! RIDMAE - Receiver Idle DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) /*! RDMAE - Receiver Full DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) #define LPUART_BAUD_TDMAE_MASK (0x800000U) #define LPUART_BAUD_TDMAE_SHIFT (23U) /*! TDMAE - Transmitter DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) #define LPUART_BAUD_OSR_MASK (0x1F000000U) #define LPUART_BAUD_OSR_SHIFT (24U) /*! OSR - Oversampling Ratio */ #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) #define LPUART_BAUD_M10_MASK (0x20000000U) #define LPUART_BAUD_M10_SHIFT (29U) /*! M10 - 10-bit Mode select * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. * 0b1..Receiver and transmitter use 10-bit data characters. */ #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) #define LPUART_BAUD_MAEN2_MASK (0x40000000U) #define LPUART_BAUD_MAEN2_SHIFT (30U) /*! MAEN2 - Match Address Mode Enable 2 * 0b0..Normal operation. * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. */ #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) /*! MAEN1 - Match Address Mode Enable 1 * 0b0..Normal operation. * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. */ #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) /*! @} */ /*! @name STAT - LPUART Status Register */ /*! @{ */ #define LPUART_STAT_MA2F_MASK (0x4000U) #define LPUART_STAT_MA2F_SHIFT (14U) /*! MA2F - Match 2 Flag * 0b0..Received data is not equal to MA2 * 0b1..Received data is equal to MA2 */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) #define LPUART_STAT_MA1F_MASK (0x8000U) #define LPUART_STAT_MA1F_SHIFT (15U) /*! MA1F - Match 1 Flag * 0b0..Received data is not equal to MA1 * 0b1..Received data is equal to MA1 */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) /*! PF - Parity Error Flag * 0b0..No parity error. * 0b1..Parity error. */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) /*! FE - Framing Error Flag * 0b0..No framing error detected. This does not guarantee the framing is correct. * 0b1..Framing error. */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) /*! NF - Noise Flag * 0b0..No noise detected. * 0b1..Noise detected in the received character in LPUART_DATA. */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) #define LPUART_STAT_OR_MASK (0x80000U) #define LPUART_STAT_OR_SHIFT (19U) /*! OR - Receiver Overrun Flag * 0b0..No overrun. * 0b1..Receive overrun (new LPUART data lost). */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) #define LPUART_STAT_IDLE_MASK (0x100000U) #define LPUART_STAT_IDLE_SHIFT (20U) /*! IDLE - Idle Line Flag * 0b0..No idle line detected. * 0b1..Idle line was detected. */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) #define LPUART_STAT_RDRF_MASK (0x200000U) #define LPUART_STAT_RDRF_SHIFT (21U) /*! RDRF - Receive Data Register Full Flag * 0b0..Receive data buffer empty. * 0b1..Receive data buffer full. */ #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) #define LPUART_STAT_TC_MASK (0x400000U) #define LPUART_STAT_TC_SHIFT (22U) /*! TC - Transmission Complete Flag * 0b0..Transmitter active (sending data, a preamble, or a break). * 0b1..Transmitter idle (transmission activity complete). */ #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) #define LPUART_STAT_TDRE_MASK (0x800000U) #define LPUART_STAT_TDRE_SHIFT (23U) /*! TDRE - Transmit Data Register Empty Flag * 0b0..Transmit data buffer full. * 0b1..Transmit data buffer empty. */ #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) #define LPUART_STAT_RAF_MASK (0x1000000U) #define LPUART_STAT_RAF_SHIFT (24U) /*! RAF - Receiver Active Flag * 0b0..LPUART receiver idle waiting for a start bit. * 0b1..LPUART receiver active (RXD input not idle). */ #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) #define LPUART_STAT_LBKDE_MASK (0x2000000U) #define LPUART_STAT_LBKDE_SHIFT (25U) /*! LBKDE - LIN Break Detection Enable * 0b0..LIN break detect is disabled, normal break character can be detected. * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). */ #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) #define LPUART_STAT_BRK13_MASK (0x4000000U) #define LPUART_STAT_BRK13_SHIFT (26U) /*! BRK13 - Break Character Generation Length * 0b0..Break character is transmitted with length of 9 to 13 bit times. * 0b1..Break character is transmitted with length of 12 to 15 bit times. */ #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) #define LPUART_STAT_RWUID_MASK (0x8000000U) #define LPUART_STAT_RWUID_SHIFT (27U) /*! RWUID - Receive Wake Up Idle Detect * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle * character. During address match wakeup, the IDLE bit does not get set when an address does not match. * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During * address match wakeup, the IDLE bit does get set when an address does not match. */ #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) #define LPUART_STAT_RXINV_MASK (0x10000000U) #define LPUART_STAT_RXINV_SHIFT (28U) /*! RXINV - Receive Data Inversion * 0b0..Receive data not inverted. * 0b1..Receive data inverted. */ #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) #define LPUART_STAT_MSBF_MASK (0x20000000U) #define LPUART_STAT_MSBF_SHIFT (29U) /*! MSBF - MSB First * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received * after the start bit is identified as bit0. * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on * the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is * identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. */ #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) #define LPUART_STAT_RXEDGIF_SHIFT (30U) /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag * 0b0..No active edge on the receive pin has occurred. * 0b1..An active edge on the receive pin has occurred. */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) #define LPUART_STAT_LBKDIF_MASK (0x80000000U) #define LPUART_STAT_LBKDIF_SHIFT (31U) /*! LBKDIF - LIN Break Detect Interrupt Flag * 0b0..No LIN break character has been detected. * 0b1..LIN break character has been detected. */ #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) /*! @} */ /*! @name CTRL - LPUART Control Register */ /*! @{ */ #define LPUART_CTRL_PT_MASK (0x1U) #define LPUART_CTRL_PT_SHIFT (0U) /*! PT - Parity Type * 0b0..Even parity. * 0b1..Odd parity. */ #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) #define LPUART_CTRL_PE_MASK (0x2U) #define LPUART_CTRL_PE_SHIFT (1U) /*! PE - Parity Enable * 0b0..No hardware parity generation or checking. * 0b1..Parity enabled. */ #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) #define LPUART_CTRL_ILT_MASK (0x4U) #define LPUART_CTRL_ILT_SHIFT (2U) /*! ILT - Idle Line Type Select * 0b0..Idle character bit count starts after start bit. * 0b1..Idle character bit count starts after stop bit. */ #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) #define LPUART_CTRL_WAKE_MASK (0x8U) #define LPUART_CTRL_WAKE_SHIFT (3U) /*! WAKE - Receiver Wakeup Method Select * 0b0..Configures RWU for idle-line wakeup. * 0b1..Configures RWU with address-mark wakeup. */ #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) #define LPUART_CTRL_M_MASK (0x10U) #define LPUART_CTRL_M_SHIFT (4U) /*! M - 9-Bit or 8-Bit Mode Select * 0b0..Receiver and transmitter use 8-bit data characters. * 0b1..Receiver and transmitter use 9-bit data characters. */ #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) #define LPUART_CTRL_RSRC_MASK (0x20U) #define LPUART_CTRL_RSRC_SHIFT (5U) /*! RSRC - Receiver Source Select * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. */ #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) #define LPUART_CTRL_DOZEEN_MASK (0x40U) #define LPUART_CTRL_DOZEEN_SHIFT (6U) /*! DOZEEN - Doze Enable * 0b0..LPUART is enabled in Doze mode. * 0b1..LPUART is disabled in Doze mode. */ #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) #define LPUART_CTRL_LOOPS_MASK (0x80U) #define LPUART_CTRL_LOOPS_SHIFT (7U) /*! LOOPS - Loop Mode Select * 0b0..Normal operation - RXD and TXD use separate pins. * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). */ #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) #define LPUART_CTRL_IDLECFG_MASK (0x700U) #define LPUART_CTRL_IDLECFG_SHIFT (8U) /*! IDLECFG - Idle Configuration * 0b000..1 idle character * 0b001..2 idle characters * 0b010..4 idle characters * 0b011..8 idle characters * 0b100..16 idle characters * 0b101..32 idle characters * 0b110..64 idle characters * 0b111..128 idle characters */ #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) #define LPUART_CTRL_M7_MASK (0x800U) #define LPUART_CTRL_M7_SHIFT (11U) /*! M7 - 7-Bit Mode Select * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. * 0b1..Receiver and transmitter use 7-bit data characters. */ #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) #define LPUART_CTRL_MA2IE_MASK (0x4000U) #define LPUART_CTRL_MA2IE_SHIFT (14U) /*! MA2IE - Match 2 Interrupt Enable * 0b0..MA2F interrupt disabled * 0b1..MA2F interrupt enabled */ #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) #define LPUART_CTRL_MA1IE_MASK (0x8000U) #define LPUART_CTRL_MA1IE_SHIFT (15U) /*! MA1IE - Match 1 Interrupt Enable * 0b0..MA1F interrupt disabled * 0b1..MA1F interrupt enabled */ #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) #define LPUART_CTRL_SBK_MASK (0x10000U) #define LPUART_CTRL_SBK_SHIFT (16U) /*! SBK - Send Break * 0b0..Normal transmitter operation. * 0b1..Queue break character(s) to be sent. */ #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) #define LPUART_CTRL_RWU_MASK (0x20000U) #define LPUART_CTRL_RWU_SHIFT (17U) /*! RWU - Receiver Wakeup Control * 0b0..Normal receiver operation. * 0b1..LPUART receiver in standby waiting for wakeup condition. */ #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) #define LPUART_CTRL_RE_MASK (0x40000U) #define LPUART_CTRL_RE_SHIFT (18U) /*! RE - Receiver Enable * 0b0..Receiver disabled. * 0b1..Receiver enabled. */ #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) #define LPUART_CTRL_TE_MASK (0x80000U) #define LPUART_CTRL_TE_SHIFT (19U) /*! TE - Transmitter Enable * 0b0..Transmitter disabled. * 0b1..Transmitter enabled. */ #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) #define LPUART_CTRL_ILIE_MASK (0x100000U) #define LPUART_CTRL_ILIE_SHIFT (20U) /*! ILIE - Idle Line Interrupt Enable * 0b0..Hardware interrupts from IDLE disabled; use polling. * 0b1..Hardware interrupt requested when IDLE flag is 1. */ #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) #define LPUART_CTRL_RIE_MASK (0x200000U) #define LPUART_CTRL_RIE_SHIFT (21U) /*! RIE - Receiver Interrupt Enable * 0b0..Hardware interrupts from RDRF disabled; use polling. * 0b1..Hardware interrupt requested when RDRF flag is 1. */ #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) #define LPUART_CTRL_TCIE_MASK (0x400000U) #define LPUART_CTRL_TCIE_SHIFT (22U) /*! TCIE - Transmission Complete Interrupt Enable for * 0b0..Hardware interrupts from TC disabled; use polling. * 0b1..Hardware interrupt requested when TC flag is 1. */ #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) #define LPUART_CTRL_TIE_MASK (0x800000U) #define LPUART_CTRL_TIE_SHIFT (23U) /*! TIE - Transmit Interrupt Enable * 0b0..Hardware interrupts from TDRE disabled; use polling. * 0b1..Hardware interrupt requested when TDRE flag is 1. */ #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) #define LPUART_CTRL_PEIE_MASK (0x1000000U) #define LPUART_CTRL_PEIE_SHIFT (24U) /*! PEIE - Parity Error Interrupt Enable * 0b0..PF interrupts disabled; use polling). * 0b1..Hardware interrupt requested when PF is set. */ #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) #define LPUART_CTRL_FEIE_MASK (0x2000000U) #define LPUART_CTRL_FEIE_SHIFT (25U) /*! FEIE - Framing Error Interrupt Enable * 0b0..FE interrupts disabled; use polling. * 0b1..Hardware interrupt requested when FE is set. */ #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) #define LPUART_CTRL_NEIE_MASK (0x4000000U) #define LPUART_CTRL_NEIE_SHIFT (26U) /*! NEIE - Noise Error Interrupt Enable * 0b0..NF interrupts disabled; use polling. * 0b1..Hardware interrupt requested when NF is set. */ #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) #define LPUART_CTRL_ORIE_MASK (0x8000000U) #define LPUART_CTRL_ORIE_SHIFT (27U) /*! ORIE - Overrun Interrupt Enable * 0b0..OR interrupts disabled; use polling. * 0b1..Hardware interrupt requested when OR is set. */ #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) #define LPUART_CTRL_TXINV_MASK (0x10000000U) #define LPUART_CTRL_TXINV_SHIFT (28U) /*! TXINV - Transmit Data Inversion * 0b0..Transmit data not inverted. * 0b1..Transmit data inverted. */ #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) #define LPUART_CTRL_TXDIR_MASK (0x20000000U) #define LPUART_CTRL_TXDIR_SHIFT (29U) /*! TXDIR - TXD Pin Direction in Single-Wire Mode * 0b0..TXD pin is an input in single-wire mode. * 0b1..TXD pin is an output in single-wire mode. */ #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) #define LPUART_CTRL_R9T8_MASK (0x40000000U) #define LPUART_CTRL_R9T8_SHIFT (30U) /*! R9T8 - Receive Bit 9 / Transmit Bit 8 */ #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) #define LPUART_CTRL_R8T9_MASK (0x80000000U) #define LPUART_CTRL_R8T9_SHIFT (31U) /*! R8T9 - Receive Bit 8 / Transmit Bit 9 */ #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) /*! @} */ /*! @name DATA - LPUART Data Register */ /*! @{ */ #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) /*! R0T0 - R0T0 */ #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) #define LPUART_DATA_R1T1_MASK (0x2U) #define LPUART_DATA_R1T1_SHIFT (1U) /*! R1T1 - R1T1 */ #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) #define LPUART_DATA_R2T2_MASK (0x4U) #define LPUART_DATA_R2T2_SHIFT (2U) /*! R2T2 - R2T2 */ #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) #define LPUART_DATA_R3T3_MASK (0x8U) #define LPUART_DATA_R3T3_SHIFT (3U) /*! R3T3 - R3T3 */ #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) #define LPUART_DATA_R4T4_MASK (0x10U) #define LPUART_DATA_R4T4_SHIFT (4U) /*! R4T4 - R4T4 */ #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) #define LPUART_DATA_R5T5_MASK (0x20U) #define LPUART_DATA_R5T5_SHIFT (5U) /*! R5T5 - R5T5 */ #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) #define LPUART_DATA_R6T6_MASK (0x40U) #define LPUART_DATA_R6T6_SHIFT (6U) /*! R6T6 - R6T6 */ #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) #define LPUART_DATA_R7T7_MASK (0x80U) #define LPUART_DATA_R7T7_SHIFT (7U) /*! R7T7 - R7T7 */ #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) #define LPUART_DATA_R8T8_MASK (0x100U) #define LPUART_DATA_R8T8_SHIFT (8U) /*! R8T8 - R8T8 */ #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) #define LPUART_DATA_R9T9_MASK (0x200U) #define LPUART_DATA_R9T9_SHIFT (9U) /*! R9T9 - R9T9 */ #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) #define LPUART_DATA_IDLINE_MASK (0x800U) #define LPUART_DATA_IDLINE_SHIFT (11U) /*! IDLINE - Idle Line * 0b0..Receiver was not idle before receiving this character. * 0b1..Receiver was idle before receiving this character. */ #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) #define LPUART_DATA_RXEMPT_MASK (0x1000U) #define LPUART_DATA_RXEMPT_SHIFT (12U) /*! RXEMPT - Receive Buffer Empty * 0b0..Receive buffer contains valid data. * 0b1..Receive buffer is empty, data returned on read is not valid. */ #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) #define LPUART_DATA_FRETSC_MASK (0x2000U) #define LPUART_DATA_FRETSC_SHIFT (13U) /*! FRETSC - Frame Error / Transmit Special Character * 0b0..The dataword was received without a frame error on read, transmit a normal character on write. * 0b1..The dataword was received with a frame error, transmit an idle or break character on transmit. */ #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) #define LPUART_DATA_PARITYE_MASK (0x4000U) #define LPUART_DATA_PARITYE_SHIFT (14U) /*! PARITYE - PARITYE * 0b0..The dataword was received without a parity error. * 0b1..The dataword was received with a parity error. */ #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) #define LPUART_DATA_NOISY_MASK (0x8000U) #define LPUART_DATA_NOISY_SHIFT (15U) /*! NOISY - NOISY * 0b0..The dataword was received without noise. * 0b1..The data was received with noise. */ #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) /*! @} */ /*! @name MATCH - LPUART Match Address Register */ /*! @{ */ #define LPUART_MATCH_MA1_MASK (0x3FFU) #define LPUART_MATCH_MA1_SHIFT (0U) /*! MA1 - Match Address 1 */ #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) #define LPUART_MATCH_MA2_MASK (0x3FF0000U) #define LPUART_MATCH_MA2_SHIFT (16U) /*! MA2 - Match Address 2 */ #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) /*! @} */ /*! @name MODIR - LPUART Modem IrDA Register */ /*! @{ */ #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) /*! TXCTSE - Transmitter clear-to-send enable * 0b0..CTS has no effect on the transmitter. * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a * character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the * mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent * do not affect its transmission. */ #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) #define LPUART_MODIR_TXRTSE_MASK (0x2U) #define LPUART_MODIR_TXRTSE_SHIFT (1U) /*! TXRTSE - Transmitter request-to-send enable * 0b0..The transmitter has no effect on RTS. * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and * shift register are completely sent, including the last stop bit. */ #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) /*! TXRTSPOL - Transmitter request-to-send polarity * 0b0..Transmitter RTS is active low. * 0b1..Transmitter RTS is active high. */ #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) #define LPUART_MODIR_RXRTSE_MASK (0x8U) #define LPUART_MODIR_RXRTSE_SHIFT (3U) /*! RXRTSE - Receiver request-to-send enable * 0b0..The receiver has no effect on RTS. * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause * the receiver data register to become full. RTS is asserted if the receiver data register is not full and * has not detected a start bit that would cause the receiver data register to become full. */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) #define LPUART_MODIR_TXCTSC_MASK (0x10U) #define LPUART_MODIR_TXCTSC_SHIFT (4U) /*! TXCTSC - Transmit CTS Configuration * 0b0..CTS input is sampled at the start of each character. * 0b1..CTS input is sampled when the transmitter is idle. */ #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) /*! TXCTSSRC - Transmit CTS Source * 0b0..CTS input is the CTS_B pin. * 0b1..CTS input is the inverted Receiver Match result. */ #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) #define LPUART_MODIR_RTSWATER_MASK (0xFF00U) #define LPUART_MODIR_RTSWATER_SHIFT (8U) /*! RTSWATER - Receive RTS Configuration */ #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) #define LPUART_MODIR_TNP_MASK (0x30000U) #define LPUART_MODIR_TNP_SHIFT (16U) /*! TNP - Transmitter narrow pulse * 0b00..1/OSR. * 0b01..2/OSR. * 0b10..3/OSR. * 0b11..4/OSR. */ #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) /*! IREN - Infrared enable * 0b0..IR disabled. * 0b1..IR enabled. */ #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) /*! @} */ /*! @name FIFO - LPUART FIFO Register */ /*! @{ */ #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - Receive FIFO. Buffer Depth * 0b000..Receive FIFO/Buffer depth = 1 dataword. * 0b001..Receive FIFO/Buffer depth = 4 datawords. * 0b010..Receive FIFO/Buffer depth = 8 datawords. * 0b011..Receive FIFO/Buffer depth = 16 datawords. * 0b100..Receive FIFO/Buffer depth = 32 datawords. * 0b101..Receive FIFO/Buffer depth = 64 datawords. * 0b110..Receive FIFO/Buffer depth = 128 datawords. * 0b111..Receive FIFO/Buffer depth = 256 datawords. */ #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) #define LPUART_FIFO_RXFE_MASK (0x8U) #define LPUART_FIFO_RXFE_SHIFT (3U) /*! RXFE - Receive FIFO Enable * 0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. */ #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) /*! TXFIFOSIZE - Transmit FIFO. Buffer Depth * 0b000..Transmit FIFO/Buffer depth = 1 dataword. * 0b001..Transmit FIFO/Buffer depth = 4 datawords. * 0b010..Transmit FIFO/Buffer depth = 8 datawords. * 0b011..Transmit FIFO/Buffer depth = 16 datawords. * 0b100..Transmit FIFO/Buffer depth = 32 datawords. * 0b101..Transmit FIFO/Buffer depth = 64 datawords. * 0b110..Transmit FIFO/Buffer depth = 128 datawords. * 0b111..Transmit FIFO/Buffer depth = 256 datawords */ #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) #define LPUART_FIFO_TXFE_MASK (0x80U) #define LPUART_FIFO_TXFE_SHIFT (7U) /*! TXFE - Transmit FIFO Enable * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. */ #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) #define LPUART_FIFO_RXUFE_MASK (0x100U) #define LPUART_FIFO_RXUFE_SHIFT (8U) /*! RXUFE - Receive FIFO Underflow Interrupt Enable * 0b0..RXUF flag does not generate an interrupt to the host. * 0b1..RXUF flag generates an interrupt to the host. */ #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) #define LPUART_FIFO_TXOFE_MASK (0x200U) #define LPUART_FIFO_TXOFE_SHIFT (9U) /*! TXOFE - Transmit FIFO Overflow Interrupt Enable * 0b0..TXOF flag does not generate an interrupt to the host. * 0b1..TXOF flag generates an interrupt to the host. */ #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) #define LPUART_FIFO_RXIDEN_SHIFT (10U) /*! RXIDEN - Receiver Idle Empty Enable * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. */ #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) #define LPUART_FIFO_RXFLUSH_SHIFT (14U) /*! RXFLUSH - Receive FIFO/Buffer Flush * 0b0..No flush operation occurs. * 0b1..All data in the receive FIFO/buffer is cleared out. */ #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) #define LPUART_FIFO_TXFLUSH_SHIFT (15U) /*! TXFLUSH - Transmit FIFO/Buffer Flush * 0b0..No flush operation occurs. * 0b1..All data in the transmit FIFO/Buffer is cleared out. */ #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) #define LPUART_FIFO_RXUF_MASK (0x10000U) #define LPUART_FIFO_RXUF_SHIFT (16U) /*! RXUF - Receiver Buffer Underflow Flag * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) #define LPUART_FIFO_TXOF_MASK (0x20000U) #define LPUART_FIFO_TXOF_SHIFT (17U) /*! TXOF - Transmitter Buffer Overflow Flag * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) #define LPUART_FIFO_RXEMPT_MASK (0x400000U) #define LPUART_FIFO_RXEMPT_SHIFT (22U) /*! RXEMPT - Receive Buffer/FIFO Empty * 0b0..Receive buffer is not empty. * 0b1..Receive buffer is empty. */ #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) #define LPUART_FIFO_TXEMPT_MASK (0x800000U) #define LPUART_FIFO_TXEMPT_SHIFT (23U) /*! TXEMPT - Transmit Buffer/FIFO Empty * 0b0..Transmit buffer is not empty. * 0b1..Transmit buffer is empty. */ #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) /*! @} */ /*! @name WATER - LPUART Watermark Register */ /*! @{ */ #define LPUART_WATER_TXWATER_MASK (0xFFU) #define LPUART_WATER_TXWATER_SHIFT (0U) /*! TXWATER - Transmit Watermark */ #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) #define LPUART_WATER_TXCOUNT_MASK (0xFF00U) #define LPUART_WATER_TXCOUNT_SHIFT (8U) /*! TXCOUNT - Transmit Counter */ #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) #define LPUART_WATER_RXWATER_MASK (0xFF0000U) #define LPUART_WATER_RXWATER_SHIFT (16U) /*! RXWATER - Receive Watermark */ #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) #define LPUART_WATER_RXCOUNT_MASK (0xFF000000U) #define LPUART_WATER_RXCOUNT_SHIFT (24U) /*! RXCOUNT - Receive Counter */ #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) /*! @} */ /*! * @} */ /* end of group LPUART_Register_Masks */ /* LPUART - Peripheral instance base addresses */ /** Peripheral LPUART0 base address */ #define LPUART0_BASE (0x4006A000u) /** Peripheral LPUART0 base pointer */ #define LPUART0 ((LPUART_Type *)LPUART0_BASE) /** Peripheral LPUART1 base address */ #define LPUART1_BASE (0x4006B000u) /** Peripheral LPUART1 base pointer */ #define LPUART1 ((LPUART_Type *)LPUART1_BASE) /** Peripheral LPUART2 base address */ #define LPUART2_BASE (0x4006C000u) /** Peripheral LPUART2 base pointer */ #define LPUART2 ((LPUART_Type *)LPUART2_BASE) /** Array initializer of LPUART peripheral base addresses */ #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2 } /** Interrupt vectors for the LPUART peripheral type */ #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn } #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn } /*! * @} */ /* end of group LPUART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer * @{ */ /** MCM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ uint8_t RESERVED_1[48]; __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ } MCM_Type; /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Masks MCM Register Masks * @{ */ /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ /*! @{ */ #define MCM_PLASC_ASC_MASK (0xFFU) #define MCM_PLASC_ASC_SHIFT (0U) /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the * crossbar switch's slave input port. * 0b00000000..A bus slave connection to AXBS input port n is absent. * 0b00000001..A bus slave connection to AXBS input port n is present. */ #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) /*! @} */ /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ /*! @{ */ #define MCM_PLAMC_AMC_MASK (0xFFU) #define MCM_PLAMC_AMC_SHIFT (0U) /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. * 0b00000000..A bus master connection to AXBS input port n is absent * 0b00000001..A bus master connection to AXBS input port n is present */ #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) /*! @} */ /*! @name PLACR - Platform Control Register */ /*! @{ */ #define MCM_PLACR_ARB_MASK (0x200U) #define MCM_PLACR_ARB_SHIFT (9U) /*! ARB - Arbitration select * 0b0..Fixed-priority arbitration for the crossbar masters * 0b1..Round-robin arbitration for the crossbar masters */ #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) #define MCM_PLACR_CFCC_MASK (0x400U) #define MCM_PLACR_CFCC_SHIFT (10U) /*! CFCC - Clear Flash Controller Cache */ #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) #define MCM_PLACR_DFCDA_MASK (0x800U) #define MCM_PLACR_DFCDA_SHIFT (11U) /*! DFCDA - Disable Flash Controller Data Caching * 0b0..Enable flash controller data caching * 0b1..Disable flash controller data caching. */ #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) #define MCM_PLACR_DFCIC_MASK (0x1000U) #define MCM_PLACR_DFCIC_SHIFT (12U) /*! DFCIC - Disable Flash Controller Instruction Caching * 0b0..Enable flash controller instruction caching. * 0b1..Disable flash controller instruction caching. */ #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) #define MCM_PLACR_DFCC_MASK (0x2000U) #define MCM_PLACR_DFCC_SHIFT (13U) /*! DFCC - Disable Flash Controller Cache * 0b0..Enable flash controller cache. * 0b1..Disable flash controller cache. */ #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) #define MCM_PLACR_EFDS_MASK (0x4000U) #define MCM_PLACR_EFDS_SHIFT (14U) /*! EFDS - Enable Flash Data Speculation * 0b0..Disable flash data speculation. * 0b1..Enable flash data speculation. */ #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) #define MCM_PLACR_DFCS_MASK (0x8000U) #define MCM_PLACR_DFCS_SHIFT (15U) /*! DFCS - Disable Flash Controller Speculation * 0b0..Enable flash controller speculation. * 0b1..Disable flash controller speculation. */ #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) #define MCM_PLACR_ESFC_MASK (0x10000U) #define MCM_PLACR_ESFC_SHIFT (16U) /*! ESFC - Enable Stalling Flash Controller * 0b0..Disable stalling flash controller when flash is busy. * 0b1..Enable stalling flash controller when flash is busy. */ #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) /*! @} */ /*! @name CPO - Compute Operation Control Register */ /*! @{ */ #define MCM_CPO_CPOREQ_MASK (0x1U) #define MCM_CPO_CPOREQ_SHIFT (0U) /*! CPOREQ - Compute Operation Request * 0b0..Request is cleared. * 0b1..Request Compute Operation. */ #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) #define MCM_CPO_CPOACK_MASK (0x2U) #define MCM_CPO_CPOACK_SHIFT (1U) /*! CPOACK - Compute Operation Acknowledge * 0b0..Compute operation entry has not completed or compute operation exit has completed. * 0b1..Compute operation entry has completed or compute operation exit has not completed. */ #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) #define MCM_CPO_CPOWOI_MASK (0x4U) #define MCM_CPO_CPOWOI_SHIFT (2U) /*! CPOWOI - Compute Operation Wake-up on Interrupt * 0b0..No effect. * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch. */ #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) /*! @} */ /*! * @} */ /* end of group MCM_Register_Masks */ /* MCM - Peripheral instance base addresses */ /** Peripheral MCM base address */ #define MCM_BASE (0xF0003000u) /** Peripheral MCM base pointer */ #define MCM ((MCM_Type *)MCM_BASE) /** Array initializer of MCM peripheral base addresses */ #define MCM_BASE_ADDRS { MCM_BASE } /** Array initializer of MCM peripheral base pointers */ #define MCM_BASE_PTRS { MCM } /*! * @} */ /* end of group MCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMDVSQ Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMDVSQ_Peripheral_Access_Layer MMDVSQ Peripheral Access Layer * @{ */ /** MMDVSQ - Register Layout Typedef */ typedef struct { __IO uint32_t DEND; /**< Dividend Register, offset: 0x0 */ __IO uint32_t DSOR; /**< Divisor Register, offset: 0x4 */ __IO uint32_t CSR; /**< Control/Status Register, offset: 0x8 */ __IO uint32_t RES; /**< Result Register, offset: 0xC */ __IO uint32_t RCND; /**< Radicand Register, offset: 0x10 */ } MMDVSQ_Type; /* ---------------------------------------------------------------------------- -- MMDVSQ Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMDVSQ_Register_Masks MMDVSQ Register Masks * @{ */ /*! @name DEND - Dividend Register */ /*! @{ */ #define MMDVSQ_DEND_DIVIDEND_MASK (0xFFFFFFFFU) #define MMDVSQ_DEND_DIVIDEND_SHIFT (0U) /*! DIVIDEND - Dividend */ #define MMDVSQ_DEND_DIVIDEND(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DEND_DIVIDEND_SHIFT)) & MMDVSQ_DEND_DIVIDEND_MASK) /*! @} */ /*! @name DSOR - Divisor Register */ /*! @{ */ #define MMDVSQ_DSOR_DIVISOR_MASK (0xFFFFFFFFU) #define MMDVSQ_DSOR_DIVISOR_SHIFT (0U) /*! DIVISOR - Divisor */ #define MMDVSQ_DSOR_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DSOR_DIVISOR_SHIFT)) & MMDVSQ_DSOR_DIVISOR_MASK) /*! @} */ /*! @name CSR - Control/Status Register */ /*! @{ */ #define MMDVSQ_CSR_SRT_MASK (0x1U) #define MMDVSQ_CSR_SRT_SHIFT (0U) /*! SRT - Start * 0b0..No operation initiated * 0b1..If CSR[DFS] = 1, then initiate a divide calculation, else ignore */ #define MMDVSQ_CSR_SRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SRT_SHIFT)) & MMDVSQ_CSR_SRT_MASK) #define MMDVSQ_CSR_USGN_MASK (0x2U) #define MMDVSQ_CSR_USGN_SHIFT (1U) /*! USGN - Unsigned calculation * 0b0..Perform a signed divide * 0b1..Perform an unsigned divide */ #define MMDVSQ_CSR_USGN(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_USGN_SHIFT)) & MMDVSQ_CSR_USGN_MASK) #define MMDVSQ_CSR_REM_MASK (0x4U) #define MMDVSQ_CSR_REM_SHIFT (2U) /*! REM - REMainder calculation * 0b0..Return the quotient in the RES for the divide calculation * 0b1..Return the remainder in the RES for the divide calculation */ #define MMDVSQ_CSR_REM(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_REM_SHIFT)) & MMDVSQ_CSR_REM_MASK) #define MMDVSQ_CSR_DZE_MASK (0x8U) #define MMDVSQ_CSR_DZE_SHIFT (3U) /*! DZE - Divide-by-Zero-Enable * 0b0..Reads of the RES register return the register contents * 0b1..If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned */ #define MMDVSQ_CSR_DZE(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZE_SHIFT)) & MMDVSQ_CSR_DZE_MASK) #define MMDVSQ_CSR_DZ_MASK (0x10U) #define MMDVSQ_CSR_DZ_SHIFT (4U) /*! DZ - Divide-by-Zero * 0b0..The last divide operation had a non-zero divisor, that is, DSOR != 0 * 0b1..The last divide operation had a zero divisor, that is, DSOR = 0 */ #define MMDVSQ_CSR_DZ(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZ_SHIFT)) & MMDVSQ_CSR_DZ_MASK) #define MMDVSQ_CSR_DFS_MASK (0x20U) #define MMDVSQ_CSR_DFS_SHIFT (5U) /*! DFS - Disable Fast Start * 0b0..A divide operation is initiated by a write to the DSOR register * 0b1..A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1 */ #define MMDVSQ_CSR_DFS(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DFS_SHIFT)) & MMDVSQ_CSR_DFS_MASK) #define MMDVSQ_CSR_SQRT_MASK (0x20000000U) #define MMDVSQ_CSR_SQRT_SHIFT (29U) /*! SQRT - SQUARE ROOT * 0b0..Current or last MMDVSQ operation was not a square root * 0b1..Current or last MMDVSQ operation was a square root */ #define MMDVSQ_CSR_SQRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SQRT_SHIFT)) & MMDVSQ_CSR_SQRT_MASK) #define MMDVSQ_CSR_DIV_MASK (0x40000000U) #define MMDVSQ_CSR_DIV_SHIFT (30U) /*! DIV - DIVIDE * 0b0..Current or last MMDVSQ operation was not a divide * 0b1..Current or last MMDVSQ operation was a divide */ #define MMDVSQ_CSR_DIV(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DIV_SHIFT)) & MMDVSQ_CSR_DIV_MASK) #define MMDVSQ_CSR_BUSY_MASK (0x80000000U) #define MMDVSQ_CSR_BUSY_SHIFT (31U) /*! BUSY - BUSY * 0b0..MMDVSQ is idle * 0b1..MMDVSQ is busy performing a divide or square root calculation */ #define MMDVSQ_CSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_BUSY_SHIFT)) & MMDVSQ_CSR_BUSY_MASK) /*! @} */ /*! @name RES - Result Register */ /*! @{ */ #define MMDVSQ_RES_RESULT_MASK (0xFFFFFFFFU) #define MMDVSQ_RES_RESULT_SHIFT (0U) /*! RESULT - Result */ #define MMDVSQ_RES_RESULT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RES_RESULT_SHIFT)) & MMDVSQ_RES_RESULT_MASK) /*! @} */ /*! @name RCND - Radicand Register */ /*! @{ */ #define MMDVSQ_RCND_RADICAND_MASK (0xFFFFFFFFU) #define MMDVSQ_RCND_RADICAND_SHIFT (0U) /*! RADICAND - Radicand */ #define MMDVSQ_RCND_RADICAND(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RCND_RADICAND_SHIFT)) & MMDVSQ_RCND_RADICAND_MASK) /*! @} */ /*! * @} */ /* end of group MMDVSQ_Register_Masks */ /* MMDVSQ - Peripheral instance base addresses */ /** Peripheral MMDVSQ base address */ #define MMDVSQ_BASE (0xF0004000u) /** Peripheral MMDVSQ base pointer */ #define MMDVSQ ((MMDVSQ_Type *)MMDVSQ_BASE) /** Array initializer of MMDVSQ peripheral base addresses */ #define MMDVSQ_BASE_ADDRS { MMDVSQ_BASE } /** Array initializer of MMDVSQ peripheral base pointers */ #define MMDVSQ_BASE_PTRS { MMDVSQ } /*! * @} */ /* end of group MMDVSQ_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MTB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer * @{ */ /** MTB - Register Layout Typedef */ typedef struct { __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ uint8_t RESERVED_0[3824]; __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ uint8_t RESERVED_1[156]; __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ uint8_t RESERVED_2[8]; __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ uint8_t RESERVED_3[8]; __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ } MTB_Type; /* ---------------------------------------------------------------------------- -- MTB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MTB_Register_Masks MTB Register Masks * @{ */ /*! @name POSITION - MTB Position Register */ /*! @{ */ #define MTB_POSITION_WRAP_MASK (0x4U) #define MTB_POSITION_WRAP_SHIFT (2U) /*! WRAP - WRAP */ #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) #define MTB_POSITION_POINTER_SHIFT (3U) /*! POINTER - Trace Packet Address Pointer[28:0] */ #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) /*! @} */ /*! @name MASTER - MTB Master Register */ /*! @{ */ #define MTB_MASTER_MASK_MASK (0x1FU) #define MTB_MASTER_MASK_SHIFT (0U) /*! MASK - Mask */ #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) #define MTB_MASTER_TSTARTEN_MASK (0x20U) #define MTB_MASTER_TSTARTEN_SHIFT (5U) /*! TSTARTEN - Trace Start Input Enable */ #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) #define MTB_MASTER_TSTOPEN_MASK (0x40U) #define MTB_MASTER_TSTOPEN_SHIFT (6U) /*! TSTOPEN - Trace Stop Input Enable */ #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) #define MTB_MASTER_SFRWPRIV_MASK (0x80U) #define MTB_MASTER_SFRWPRIV_SHIFT (7U) /*! SFRWPRIV - Special Function Register Write Privilege */ #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) #define MTB_MASTER_RAMPRIV_MASK (0x100U) #define MTB_MASTER_RAMPRIV_SHIFT (8U) /*! RAMPRIV - RAM Privilege */ #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) #define MTB_MASTER_HALTREQ_MASK (0x200U) #define MTB_MASTER_HALTREQ_SHIFT (9U) /*! HALTREQ - Halt Request */ #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) #define MTB_MASTER_EN_MASK (0x80000000U) #define MTB_MASTER_EN_SHIFT (31U) /*! EN - Main Trace Enable */ #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) /*! @} */ /*! @name FLOW - MTB Flow Register */ /*! @{ */ #define MTB_FLOW_AUTOSTOP_MASK (0x1U) #define MTB_FLOW_AUTOSTOP_SHIFT (0U) /*! AUTOSTOP - AUTOSTOP */ #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) #define MTB_FLOW_AUTOHALT_MASK (0x2U) #define MTB_FLOW_AUTOHALT_SHIFT (1U) /*! AUTOHALT - AUTOHALT */ #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) #define MTB_FLOW_WATERMARK_SHIFT (3U) /*! WATERMARK - WATERMARK[28:0] */ #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) /*! @} */ /*! @name BASE - MTB Base Register */ /*! @{ */ #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) #define MTB_BASE_BASEADDR_SHIFT (0U) /*! BASEADDR - BASEADDR */ #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) /*! @} */ /*! @name MODECTRL - Integration Mode Control Register */ /*! @{ */ #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) #define MTB_MODECTRL_MODECTRL_SHIFT (0U) /*! MODECTRL - MODECTRL */ #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) /*! @} */ /*! @name TAGSET - Claim TAG Set Register */ /*! @{ */ #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) #define MTB_TAGSET_TAGSET_SHIFT (0U) /*! TAGSET - TAGSET */ #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) /*! @} */ /*! @name TAGCLEAR - Claim TAG Clear Register */ /*! @{ */ #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) /*! TAGCLEAR - TAGCLEAR */ #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) /*! @} */ /*! @name LOCKACCESS - Lock Access Register */ /*! @{ */ #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) /*! @} */ /*! @name LOCKSTAT - Lock Status Register */ /*! @{ */ #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) /*! LOCKSTAT - LOCKSTAT */ #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) /*! @} */ /*! @name AUTHSTAT - Authentication Status Register */ /*! @{ */ #define MTB_AUTHSTAT_BIT0_MASK (0x1U) #define MTB_AUTHSTAT_BIT0_SHIFT (0U) #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) #define MTB_AUTHSTAT_BIT1_MASK (0x2U) #define MTB_AUTHSTAT_BIT1_SHIFT (1U) /*! BIT1 - BIT1 */ #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK) #define MTB_AUTHSTAT_BIT2_MASK (0x4U) #define MTB_AUTHSTAT_BIT2_SHIFT (2U) /*! BIT2 - BIT2 */ #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) #define MTB_AUTHSTAT_BIT3_MASK (0x8U) #define MTB_AUTHSTAT_BIT3_SHIFT (3U) /*! BIT3 - BIT3 */ #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK) /*! @} */ /*! @name DEVICEARCH - Device Architecture Register */ /*! @{ */ #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) /*! DEVICEARCH - DEVICEARCH */ #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) /*! @} */ /*! @name DEVICECFG - Device Configuration Register */ /*! @{ */ #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) /*! DEVICECFG - DEVICECFG */ #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) /*! @} */ /*! @name DEVICETYPID - Device Type Identifier Register */ /*! @{ */ #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) /*! DEVICETYPID - DEVICETYPID */ #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) /*! @} */ /*! @name PERIPHID4 - Peripheral ID Register */ /*! @{ */ #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) #define MTB_PERIPHID4_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID5 - Peripheral ID Register */ /*! @{ */ #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) #define MTB_PERIPHID5_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID6 - Peripheral ID Register */ /*! @{ */ #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) #define MTB_PERIPHID6_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID7 - Peripheral ID Register */ /*! @{ */ #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) #define MTB_PERIPHID7_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID0 - Peripheral ID Register */ /*! @{ */ #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) #define MTB_PERIPHID0_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID1 - Peripheral ID Register */ /*! @{ */ #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) #define MTB_PERIPHID1_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID2 - Peripheral ID Register */ /*! @{ */ #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) #define MTB_PERIPHID2_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID3 - Peripheral ID Register */ /*! @{ */ #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) #define MTB_PERIPHID3_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK) /*! @} */ /*! @name COMPID - Component ID Register */ /*! @{ */ #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) #define MTB_COMPID_COMPID_SHIFT (0U) /*! COMPID - Component ID */ #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) /*! @} */ /* The count of MTB_COMPID */ #define MTB_COMPID_COUNT (4U) /*! * @} */ /* end of group MTB_Register_Masks */ /* MTB - Peripheral instance base addresses */ /** Peripheral MTB base address */ #define MTB_BASE (0xF0000000u) /** Peripheral MTB base pointer */ #define MTB ((MTB_Type *)MTB_BASE) /** Array initializer of MTB peripheral base addresses */ #define MTB_BASE_ADDRS { MTB_BASE } /** Array initializer of MTB peripheral base pointers */ #define MTB_BASE_PTRS { MTB } /*! * @} */ /* end of group MTB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MTBDWT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer * @{ */ /** MTBDWT - Register Layout Typedef */ typedef struct { __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ uint8_t RESERVED_0[28]; struct { /* offset: 0x20, array step: 0x10 */ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ uint8_t RESERVED_0[4]; } COMPARATOR[2]; uint8_t RESERVED_1[448]; __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ uint8_t RESERVED_2[3524]; __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ } MTBDWT_Type; /* ---------------------------------------------------------------------------- -- MTBDWT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks * @{ */ /*! @name CTRL - MTB DWT Control Register */ /*! @{ */ #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) /*! DWTCFGCTRL - DWT configuration controls */ #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) #define MTBDWT_CTRL_NUMCMP_SHIFT (28U) /*! NUMCMP - Number of comparators */ #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) /*! @} */ /*! @name COMP - MTB_DWT Comparator Register */ /*! @{ */ #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) #define MTBDWT_COMP_COMP_SHIFT (0U) /*! COMP - Reference value for comparison */ #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) /*! @} */ /* The count of MTBDWT_COMP */ #define MTBDWT_COMP_COUNT (2U) /*! @name MASK - MTB_DWT Comparator Mask Register */ /*! @{ */ #define MTBDWT_MASK_MASK_MASK (0x1FU) #define MTBDWT_MASK_MASK_SHIFT (0U) /*! MASK - MASK */ #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) /*! @} */ /* The count of MTBDWT_MASK */ #define MTBDWT_MASK_COUNT (2U) /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ /*! @{ */ #define MTBDWT_FCT_FUNCTION_MASK (0xFU) #define MTBDWT_FCT_FUNCTION_SHIFT (0U) /*! FUNCTION - Function * 0b0000..Disabled. * 0b0100..Instruction fetch. * 0b0101..Data operand read. * 0b0110..Data operand write. * 0b0111..Data operand (read + write). */ #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) /*! DATAVMATCH - Data Value Match * 0b0..Perform address comparison. * 0b1..Perform data value comparison. */ #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) /*! DATAVSIZE - Data Value Size * 0b00..Byte. * 0b01..Halfword. * 0b10..Word. * 0b11..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. */ #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) /*! DATAVADDR0 - Data Value Address 0 */ #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) #define MTBDWT_FCT_MATCHED_MASK (0x1000000U) #define MTBDWT_FCT_MATCHED_SHIFT (24U) /*! MATCHED - Comparator match * 0b0..No match. * 0b1..Match occurred. */ #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) /*! @} */ /* The count of MTBDWT_FCT */ #define MTBDWT_FCT_COUNT (2U) /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ /*! @{ */ #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) /*! ACOMP0 - Action based on Comparator 0 match * 0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. * 0b1..Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. */ #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) /*! ACOMP1 - Action based on Comparator 1 match * 0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. * 0b1..Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. */ #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) /*! NUMCOMP - Number of Comparators */ #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) /*! @} */ /*! @name DEVICECFG - Device Configuration Register */ /*! @{ */ #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) /*! DEVICECFG - DEVICECFG */ #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) /*! @} */ /*! @name DEVICETYPID - Device Type Identifier Register */ /*! @{ */ #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) /*! DEVICETYPID - DEVICETYPID */ #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) /*! @} */ /*! @name PERIPHID4 - Peripheral ID Register */ /*! @{ */ #define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) #define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID5 - Peripheral ID Register */ /*! @{ */ #define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) #define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID6 - Peripheral ID Register */ /*! @{ */ #define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) #define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID7 - Peripheral ID Register */ /*! @{ */ #define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) #define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID0 - Peripheral ID Register */ /*! @{ */ #define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) #define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID1 - Peripheral ID Register */ /*! @{ */ #define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) #define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID2 - Peripheral ID Register */ /*! @{ */ #define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) #define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID3 - Peripheral ID Register */ /*! @{ */ #define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) #define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK) /*! @} */ /*! @name COMPID - Component ID Register */ /*! @{ */ #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) #define MTBDWT_COMPID_COMPID_SHIFT (0U) /*! COMPID - Component ID */ #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) /*! @} */ /* The count of MTBDWT_COMPID */ #define MTBDWT_COMPID_COUNT (4U) /*! * @} */ /* end of group MTBDWT_Register_Masks */ /* MTBDWT - Peripheral instance base addresses */ /** Peripheral MTBDWT base address */ #define MTBDWT_BASE (0xF0001000u) /** Peripheral MTBDWT base pointer */ #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) /** Array initializer of MTBDWT peripheral base addresses */ #define MTBDWT_BASE_ADDRS { MTBDWT_BASE } /** Array initializer of MTBDWT peripheral base pointers */ #define MTBDWT_BASE_PTRS { MTBDWT } /*! * @} */ /* end of group MTBDWT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NV Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer * @{ */ /** NV - Register Layout Typedef */ typedef struct { __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */ __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */ } NV_Type; /* ---------------------------------------------------------------------------- -- NV Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NV_Register_Masks NV Register Masks * @{ */ /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ /*! @{ */ #define NV_BACKKEY3_KEY_MASK (0xFFU) #define NV_BACKKEY3_KEY_SHIFT (0U) /*! KEY - Backdoor Comparison Key. */ #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) /*! @} */ /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ /*! @{ */ #define NV_BACKKEY2_KEY_MASK (0xFFU) #define NV_BACKKEY2_KEY_SHIFT (0U) /*! KEY - Backdoor Comparison Key. */ #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) /*! @} */ /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ /*! @{ */ #define NV_BACKKEY1_KEY_MASK (0xFFU) #define NV_BACKKEY1_KEY_SHIFT (0U) /*! KEY - Backdoor Comparison Key. */ #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) /*! @} */ /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ /*! @{ */ #define NV_BACKKEY0_KEY_MASK (0xFFU) #define NV_BACKKEY0_KEY_SHIFT (0U) /*! KEY - Backdoor Comparison Key. */ #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) /*! @} */ /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ /*! @{ */ #define NV_BACKKEY7_KEY_MASK (0xFFU) #define NV_BACKKEY7_KEY_SHIFT (0U) /*! KEY - Backdoor Comparison Key. */ #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) /*! @} */ /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ /*! @{ */ #define NV_BACKKEY6_KEY_MASK (0xFFU) #define NV_BACKKEY6_KEY_SHIFT (0U) /*! KEY - Backdoor Comparison Key. */ #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) /*! @} */ /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ /*! @{ */ #define NV_BACKKEY5_KEY_MASK (0xFFU) #define NV_BACKKEY5_KEY_SHIFT (0U) /*! KEY - Backdoor Comparison Key. */ #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) /*! @} */ /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ /*! @{ */ #define NV_BACKKEY4_KEY_MASK (0xFFU) #define NV_BACKKEY4_KEY_SHIFT (0U) /*! KEY - Backdoor Comparison Key. */ #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) /*! @} */ /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ /*! @{ */ #define NV_FPROT3_PROT_MASK (0xFFU) #define NV_FPROT3_PROT_SHIFT (0U) /*! PROT - P-Flash Region Protect */ #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) /*! @} */ /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ /*! @{ */ #define NV_FPROT2_PROT_MASK (0xFFU) #define NV_FPROT2_PROT_SHIFT (0U) /*! PROT - P-Flash Region Protect */ #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) /*! @} */ /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ /*! @{ */ #define NV_FPROT1_PROT_MASK (0xFFU) #define NV_FPROT1_PROT_SHIFT (0U) /*! PROT - P-Flash Region Protect */ #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) /*! @} */ /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ /*! @{ */ #define NV_FPROT0_PROT_MASK (0xFFU) #define NV_FPROT0_PROT_SHIFT (0U) /*! PROT - P-Flash Region Protect */ #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) /*! @} */ /*! @name FSEC - Non-volatile Flash Security Register */ /*! @{ */ #define NV_FSEC_SEC_MASK (0x3U) #define NV_FSEC_SEC_SHIFT (0U) /*! SEC - Flash Security * 0b10..MCU security status is unsecure * 0b11..MCU security status is secure */ #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) #define NV_FSEC_FSLACC_MASK (0xCU) #define NV_FSEC_FSLACC_SHIFT (2U) /*! FSLACC - Freescale Failure Analysis Access Code * 0b10..Freescale factory access denied * 0b11..Freescale factory access granted */ #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) #define NV_FSEC_MEEN_MASK (0x30U) #define NV_FSEC_MEEN_SHIFT (4U) /*! MEEN * 0b10..Mass erase is disabled * 0b11..Mass erase is enabled */ #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) #define NV_FSEC_KEYEN_MASK (0xC0U) #define NV_FSEC_KEYEN_SHIFT (6U) /*! KEYEN - Backdoor Key Security Enable * 0b10..Backdoor key access enabled * 0b11..Backdoor key access disabled */ #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) /*! @} */ /*! @name FOPT - Non-volatile Flash Option Register */ /*! @{ */ #define NV_FOPT_LPBOOT_MASK (0x1U) #define NV_FOPT_LPBOOT_SHIFT (0U) /*! LPBOOT * 0b0..Low-power boot * 0b1..Normal boot */ #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) #define NV_FOPT_BOOTPIN_OPT_MASK (0x2U) #define NV_FOPT_BOOTPIN_OPT_SHIFT (1U) /*! BOOTPIN_OPT * 0b0..Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin * 0b1..Boot source configured by FOPT (BOOTSRC_SEL) bits */ #define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK) #define NV_FOPT_NMI_DIS_MASK (0x4U) #define NV_FOPT_NMI_DIS_SHIFT (2U) /*! NMI_DIS * 0b0..NMI interrupts are always blocked * 0b1..NMI_b pin/interrupts reset default to enabled */ #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U) #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U) /*! RESET_PIN_CFG * 0b0..RESET pin is disabled following a POR and cannot be enabled as reset function * 0b1..RESET_b pin is dedicated */ #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK) #define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U) #define NV_FOPT_BOOTSRC_SEL_SHIFT (6U) /*! BOOTSRC_SEL - Boot source selection * 0b00..Boot from Flash * 0b10..Boot from ROM * 0b11..Boot from ROM */ #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK) /*! @} */ /*! @name FEPROT - Non-volatile EERAM Protection Register */ /*! @{ */ #define NV_FEPROT_EPROT_MASK (0xFFU) #define NV_FEPROT_EPROT_SHIFT (0U) #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK) /*! @} */ /*! @name FDPROT - Non-volatile D-Flash Protection Register */ /*! @{ */ #define NV_FDPROT_DPROT_MASK (0xFFU) #define NV_FDPROT_DPROT_SHIFT (0U) /*! DPROT - D-Flash Region Protect */ #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK) /*! @} */ /*! * @} */ /* end of group NV_Register_Masks */ /* NV - Peripheral instance base addresses */ /** Peripheral FTFE_FlashConfig base address */ #define FTFE_FlashConfig_BASE (0x400u) /** Peripheral FTFE_FlashConfig base pointer */ #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE) /** Array initializer of NV peripheral base addresses */ #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE } /** Array initializer of NV peripheral base pointers */ #define NV_BASE_PTRS { FTFE_FlashConfig } /*! * @} */ /* end of group NV_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OSC32 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OSC32_Peripheral_Access_Layer OSC32 Peripheral Access Layer * @{ */ /** OSC32 - Register Layout Typedef */ typedef struct { __IO uint8_t CR; /**< RTC Oscillator Control Register, offset: 0x0 */ } OSC32_Type; /* ---------------------------------------------------------------------------- -- OSC32 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OSC32_Register_Masks OSC32 Register Masks * @{ */ /*! @name CR - RTC Oscillator Control Register */ /*! @{ */ #define OSC32_CR_ROSCEREFS_MASK (0x10U) #define OSC32_CR_ROSCEREFS_SHIFT (4U) /*! ROSCEREFS - RTC 32k Oscillator external reference clcok selection * 0b0..Bypass mode. RTC oscillator selects the external 32k clock. * 0b1..Crystal mode. */ #define OSC32_CR_ROSCEREFS(x) (((uint8_t)(((uint8_t)(x)) << OSC32_CR_ROSCEREFS_SHIFT)) & OSC32_CR_ROSCEREFS_MASK) #define OSC32_CR_ROSCSTB_MASK (0x20U) #define OSC32_CR_ROSCSTB_SHIFT (5U) /*! ROSCSTB - RTC 32k Oscillator stable flag * 0b0..RTC 32k oscillator is unstable now and no clock will go out of the block. * 0b1..RTC 32k oscillator is stable. */ #define OSC32_CR_ROSCSTB(x) (((uint8_t)(((uint8_t)(x)) << OSC32_CR_ROSCSTB_SHIFT)) & OSC32_CR_ROSCSTB_MASK) #define OSC32_CR_ROSCSTPEN_MASK (0x40U) #define OSC32_CR_ROSCSTPEN_SHIFT (6U) /*! ROSCSTPEN - RTC 32k Oscillator stop mode enable * 0b0..Oscillator is disabled regardless the state of ROSCEN. * 0b1..Oscillator is enabled in Stop mode when ROSCEN is set. */ #define OSC32_CR_ROSCSTPEN(x) (((uint8_t)(((uint8_t)(x)) << OSC32_CR_ROSCSTPEN_SHIFT)) & OSC32_CR_ROSCSTPEN_MASK) #define OSC32_CR_ROSCEN_MASK (0x80U) #define OSC32_CR_ROSCEN_SHIFT (7U) /*! ROSCEN - RTC 32k Oscillator enable * 0b0..Oscillator is disabled. * 0b1..Oscillator is enabled. */ #define OSC32_CR_ROSCEN(x) (((uint8_t)(((uint8_t)(x)) << OSC32_CR_ROSCEN_SHIFT)) & OSC32_CR_ROSCEN_MASK) /*! @} */ /*! * @} */ /* end of group OSC32_Register_Masks */ /* OSC32 - Peripheral instance base addresses */ /** Peripheral OSC32 base address */ #define OSC32_BASE (0x40060000u) /** Peripheral OSC32 base pointer */ #define OSC32 ((OSC32_Type *)OSC32_BASE) /** Array initializer of OSC32 peripheral base addresses */ #define OSC32_BASE_ADDRS { OSC32_BASE } /** Array initializer of OSC32 peripheral base pointers */ #define OSC32_BASE_PTRS { OSC32 } /*! * @} */ /* end of group OSC32_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PCC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PCC_Peripheral_Access_Layer PCC Peripheral Access Layer * @{ */ /** PCC - Register Layout Typedef */ typedef struct { __IO uint32_t CLKCFG[117]; /**< PCC Register, array offset: 0x0, array step: 0x4 */ } PCC_Type; /* ---------------------------------------------------------------------------- -- PCC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCC_Register_Masks PCC Register Masks * @{ */ /*! @name CLKCFG - PCC Register */ /*! @{ */ #define PCC_CLKCFG_PCS_MASK (0x7000000U) #define PCC_CLKCFG_PCS_SHIFT (24U) /*! PCS - Peripheral Clock Source Select * 0b000..Clock is off (or test clock is enabled). * 0b001..OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). * 0b010..SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). * 0b011..SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). * 0b100..Reserved. * 0b101..Reserved. * 0b110..SCGPCLK System PLL clock(scg_spll_slow_clk). * 0b111..Reserved. */ #define PCC_CLKCFG_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCS_SHIFT)) & PCC_CLKCFG_PCS_MASK) #define PCC_CLKCFG_INUSE_MASK (0x20000000U) #define PCC_CLKCFG_INUSE_SHIFT (29U) /*! INUSE - Clock Gate Control * 0b0..Peripheral is not being used. * 0b1..Peripheral is being used. Software cannot modify the existing clocking configuration. */ #define PCC_CLKCFG_INUSE(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_INUSE_SHIFT)) & PCC_CLKCFG_INUSE_MASK) #define PCC_CLKCFG_CGC_MASK (0x40000000U) #define PCC_CLKCFG_CGC_SHIFT (30U) /*! CGC - Clock Control * 0b0..Clock disabled * 0b1..Clock enabled */ #define PCC_CLKCFG_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_CGC_SHIFT)) & PCC_CLKCFG_CGC_MASK) #define PCC_CLKCFG_PR_MASK (0x80000000U) #define PCC_CLKCFG_PR_SHIFT (31U) /*! PR - Enable * 0b0..Peripheral is not present. * 0b1..Peripheral is present. */ #define PCC_CLKCFG_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PR_SHIFT)) & PCC_CLKCFG_PR_MASK) /*! @} */ /* The count of PCC_CLKCFG */ #define PCC_CLKCFG_COUNT (117U) /*! * @} */ /* end of group PCC_Register_Masks */ /* PCC - Peripheral instance base addresses */ /** Peripheral PCC base address */ #define PCC_BASE (0x40065000u) /** Peripheral PCC base pointer */ #define PCC ((PCC_Type *)PCC_BASE) /** Array initializer of PCC peripheral base addresses */ #define PCC_BASE_ADDRS { PCC_BASE } /** Array initializer of PCC peripheral base pointers */ #define PCC_BASE_PTRS { PCC } #define PCC_INSTANCE_MASK 0xF #define PCC_INSTANCE_SHIFT 12 #define PCC_PERIPHERAL_MASK 0xFFF #define PCC_PERIPHERAL_SHIFT 0 #define PCC_INSTANCE_0 0 #define PCC_DMA0_INDEX 8 #define PCC_FLASH_INDEX 32 #define PCC_DMAMUX0_INDEX 33 #define PCC_ADC1_INDEX 39 #define PCC_LPSPI0_INDEX 44 #define PCC_LPSPI1_INDEX 45 #define PCC_CRC_INDEX 50 #define PCC_PDB0_INDEX 54 #define PCC_LPIT0_INDEX 55 #define PCC_FLEXTMR0_INDEX 56 #define PCC_FLEXTMR1_INDEX 57 #define PCC_FLEXTMR2_INDEX 58 #define PCC_ADC0_INDEX 59 #define PCC_RTC_INDEX 61 #define PCC_LPTMR0_INDEX 64 #define PCC_TSI0_INDEX 69 #define PCC_PORTA_INDEX 73 #define PCC_PORTB_INDEX 74 #define PCC_PORTC_INDEX 75 #define PCC_PORTD_INDEX 76 #define PCC_PORTE_INDEX 77 #define PCC_PWT_INDEX 86 #define PCC_FLEXIO_INDEX 90 #define PCC_RTC_OSC_INDEX 96 #define PCC_EWM_INDEX 97 #define PCC_LPI2C0_INDEX 102 #define PCC_LPI2C1_INDEX 103 #define PCC_LPUART0_INDEX 106 #define PCC_LPUART1_INDEX 107 #define PCC_LPUART2_INDEX 108 #define PCC_CMP0_INDEX 115 #define PCC_CMP1_INDEX 116 /*! * @} */ /* end of group PCC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PDB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer * @{ */ /** PDB - Register Layout Typedef */ typedef struct { __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ __I uint32_t CNT; /**< Counter register, offset: 0x8 */ __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ struct { /* offset: 0x10, array step: 0x28 */ __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ uint8_t RESERVED_0[24]; } CH[2]; uint8_t RESERVED_0[304]; __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ } PDB_Type; /* ---------------------------------------------------------------------------- -- PDB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PDB_Register_Masks PDB Register Masks * @{ */ /*! @name SC - Status and Control register */ /*! @{ */ #define PDB_SC_LDOK_MASK (0x1U) #define PDB_SC_LDOK_SHIFT (0U) /*! LDOK - Load OK */ #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) #define PDB_SC_CONT_MASK (0x2U) #define PDB_SC_CONT_SHIFT (1U) /*! CONT - Continuous Mode Enable * 0b0..PDB operation in One-Shot mode * 0b1..PDB operation in Continuous mode */ #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) #define PDB_SC_MULT_MASK (0xCU) #define PDB_SC_MULT_SHIFT (2U) /*! MULT - Multiplication Factor Select for Prescaler * 0b00..Multiplication factor is 1. * 0b01..Multiplication factor is 10. * 0b10..Multiplication factor is 20. * 0b11..Multiplication factor is 40. */ #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) #define PDB_SC_PDBIE_MASK (0x20U) #define PDB_SC_PDBIE_SHIFT (5U) /*! PDBIE - PDB Interrupt Enable * 0b0..PDB interrupt disabled. * 0b1..PDB interrupt enabled. */ #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) #define PDB_SC_PDBIF_MASK (0x40U) #define PDB_SC_PDBIF_SHIFT (6U) /*! PDBIF - PDB Interrupt Flag */ #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) #define PDB_SC_PDBEN_MASK (0x80U) #define PDB_SC_PDBEN_SHIFT (7U) /*! PDBEN - PDB Enable * 0b0..PDB disabled. Counter is off. * 0b1..PDB enabled. */ #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) #define PDB_SC_TRGSEL_MASK (0xF00U) #define PDB_SC_TRGSEL_SHIFT (8U) /*! TRGSEL - Trigger Input Source Select * 0b0000..Trigger-In 0 is selected. * 0b0001..Trigger-In 1 is selected. * 0b0010..Trigger-In 2 is selected. * 0b0011..Trigger-In 3 is selected. * 0b0100..Trigger-In 4 is selected. * 0b0101..Trigger-In 5 is selected. * 0b0110..Trigger-In 6 is selected. * 0b0111..Trigger-In 7 is selected. * 0b1000..Trigger-In 8 is selected. * 0b1001..Trigger-In 9 is selected. * 0b1010..Trigger-In 10 is selected. * 0b1011..Trigger-In 11 is selected. * 0b1100..Trigger-In 12 is selected. * 0b1101..Trigger-In 13 is selected. * 0b1110..Trigger-In 14 is selected. * 0b1111..Software trigger is selected. */ #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) #define PDB_SC_PRESCALER_MASK (0x7000U) #define PDB_SC_PRESCALER_SHIFT (12U) /*! PRESCALER - Prescaler Divider Select * 0b000..Counting uses the peripheral clock divided by multiplication factor selected by MULT. * 0b001..Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. * 0b010..Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. * 0b011..Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. * 0b100..Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. * 0b101..Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. * 0b110..Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. * 0b111..Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. */ #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) #define PDB_SC_DMAEN_MASK (0x8000U) #define PDB_SC_DMAEN_SHIFT (15U) /*! DMAEN - DMA Enable * 0b0..DMA disabled. * 0b1..DMA enabled. */ #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) #define PDB_SC_SWTRIG_MASK (0x10000U) #define PDB_SC_SWTRIG_SHIFT (16U) /*! SWTRIG - Software Trigger */ #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) #define PDB_SC_PDBEIE_MASK (0x20000U) #define PDB_SC_PDBEIE_SHIFT (17U) /*! PDBEIE - PDB Sequence Error Interrupt Enable * 0b0..PDB sequence error interrupt disabled. * 0b1..PDB sequence error interrupt enabled. */ #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) #define PDB_SC_LDMOD_MASK (0xC0000U) #define PDB_SC_LDMOD_SHIFT (18U) /*! LDMOD - Load Mode Select * 0b00..The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. * 0b01..The internal registers are loaded with the values from their buffers when the PDB counter reaches the * MOD register value after 1 is written to LDOK. * 0b10..The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. * 0b11..The internal registers are loaded with the values from their buffers when either the PDB counter reaches * the MOD register value or a trigger input event is detected, after 1 is written to LDOK. */ #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) /*! @} */ /*! @name MOD - Modulus register */ /*! @{ */ #define PDB_MOD_MOD_MASK (0xFFFFU) #define PDB_MOD_MOD_SHIFT (0U) /*! MOD - PDB Modulus */ #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) /*! @} */ /*! @name CNT - Counter register */ /*! @{ */ #define PDB_CNT_CNT_MASK (0xFFFFU) #define PDB_CNT_CNT_SHIFT (0U) /*! CNT - PDB Counter */ #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) /*! @} */ /*! @name IDLY - Interrupt Delay register */ /*! @{ */ #define PDB_IDLY_IDLY_MASK (0xFFFFU) #define PDB_IDLY_IDLY_SHIFT (0U) /*! IDLY - PDB Interrupt Delay */ #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) /*! @} */ /*! @name C1 - Channel n Control register 1 */ /*! @{ */ #define PDB_C1_EN_MASK (0xFFU) #define PDB_C1_EN_SHIFT (0U) /*! EN - PDB Channel Pre-Trigger Enable * 0b00000000..PDB channel's corresponding pre-trigger disabled. * 0b00000001..PDB channel's corresponding pre-trigger enabled. */ #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) #define PDB_C1_TOS_MASK (0xFF00U) #define PDB_C1_TOS_SHIFT (8U) /*! TOS - PDB Channel Pre-Trigger Output Select * 0b00000000..PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one * peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger * is selected and SWTRIG is written with 1. * 0b00000001..PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay * register and one peripheral clock cycle after a rising edge is detected on selected trigger input source * or software trigger is selected and SETRIG is written with 1. */ #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) #define PDB_C1_BB_MASK (0xFF0000U) #define PDB_C1_BB_SHIFT (16U) /*! BB - PDB Channel Pre-Trigger Back-to-Back Operation Enable * 0b00000000..PDB channel's corresponding pre-trigger back-to-back operation disabled. * 0b00000001..PDB channel's corresponding pre-trigger back-to-back operation enabled. */ #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) /*! @} */ /* The count of PDB_C1 */ #define PDB_C1_COUNT (2U) /*! @name S - Channel n Status register */ /*! @{ */ #define PDB_S_ERR_MASK (0xFFU) #define PDB_S_ERR_SHIFT (0U) /*! ERR - PDB Channel Sequence Error Flags * 0b00000000..Sequence error not detected on PDB channel's corresponding pre-trigger. * 0b00000001..Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered * for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by * one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's * corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence * error flags. */ #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) #define PDB_S_CF_MASK (0xFF0000U) #define PDB_S_CF_SHIFT (16U) /*! CF - PDB Channel Flags */ #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) /*! @} */ /* The count of PDB_S */ #define PDB_S_COUNT (2U) /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */ /*! @{ */ #define PDB_DLY_DLY_MASK (0xFFFFU) #define PDB_DLY_DLY_SHIFT (0U) /*! DLY - PDB Channel Delay */ #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) /*! @} */ /* The count of PDB_DLY */ #define PDB_DLY_COUNT (2U) /* The count of PDB_DLY */ #define PDB_DLY_COUNT2 (2U) /*! @name POEN - Pulse-Out n Enable register */ /*! @{ */ #define PDB_POEN_POEN_MASK (0xFFU) #define PDB_POEN_POEN_SHIFT (0U) /*! POEN - PDB Pulse-Out Enable * 0b00000000..PDB Pulse-Out disabled * 0b00000001..PDB Pulse-Out enabled */ #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) /*! @} */ /*! @name PODLY - Pulse-Out n Delay register */ /*! @{ */ #define PDB_PODLY_DLY2_MASK (0xFFFFU) #define PDB_PODLY_DLY2_SHIFT (0U) /*! DLY2 - PDB Pulse-Out Delay 2 */ #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) #define PDB_PODLY_DLY1_MASK (0xFFFF0000U) #define PDB_PODLY_DLY1_SHIFT (16U) /*! DLY1 - PDB Pulse-Out Delay 1 */ #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) /*! @} */ /* The count of PDB_PODLY */ #define PDB_PODLY_COUNT (2U) /*! * @} */ /* end of group PDB_Register_Masks */ /* PDB - Peripheral instance base addresses */ /** Peripheral PDB0 base address */ #define PDB0_BASE (0x40036000u) /** Peripheral PDB0 base pointer */ #define PDB0 ((PDB_Type *)PDB0_BASE) /** Array initializer of PDB peripheral base addresses */ #define PDB_BASE_ADDRS { PDB0_BASE } /** Array initializer of PDB peripheral base pointers */ #define PDB_BASE_PTRS { PDB0 } /** Interrupt vectors for the PDB peripheral type */ #define PDB_IRQS { PDB0_IRQn } /*! * @} */ /* end of group PDB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer * @{ */ /** PMC - Register Layout Typedef */ typedef struct { __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */ __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */ uint8_t RESERVED_0[1]; __IO uint8_t LPOTRIM; /**< Low Power Oscillator Trim Register, offset: 0x4 */ } PMC_Type; /* ---------------------------------------------------------------------------- -- PMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC_Register_Masks PMC Register Masks * @{ */ /*! @name LVDSC1 - Low Voltage Detect Status and Control 1 Register */ /*! @{ */ #define PMC_LVDSC1_LVDRE_MASK (0x10U) #define PMC_LVDSC1_LVDRE_SHIFT (4U) /*! LVDRE - Low Voltage Detect Reset Enable * 0b0..No system resets on low voltage detect events. * 0b1..If the supply voltage falls below VLVD, a system reset will be generated. */ #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) #define PMC_LVDSC1_LVDIE_MASK (0x20U) #define PMC_LVDSC1_LVDIE_SHIFT (5U) /*! LVDIE - Low Voltage Detect Interrupt Enable * 0b0..Hardware interrupt disabled (use polling) * 0b1..Request a hardware interrupt when LVDF = 1 */ #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) #define PMC_LVDSC1_LVDACK_MASK (0x40U) #define PMC_LVDSC1_LVDACK_SHIFT (6U) /*! LVDACK - Low Voltage Detect Acknowledge */ #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) #define PMC_LVDSC1_LVDF_MASK (0x80U) #define PMC_LVDSC1_LVDF_SHIFT (7U) /*! LVDF - Low Voltage Detect Flag * 0b0..Low-voltage event not detected * 0b1..Low-voltage event detected */ #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) /*! @} */ /*! @name LVDSC2 - Low Voltage Detect Status and Control 2 Register */ /*! @{ */ #define PMC_LVDSC2_LVWIE_MASK (0x20U) #define PMC_LVDSC2_LVWIE_SHIFT (5U) /*! LVWIE - Low-Voltage Warning Interrupt Enable * 0b0..Hardware interrupt disabled (use polling) * 0b1..Request a hardware interrupt when LVWF=1 */ #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) #define PMC_LVDSC2_LVWACK_MASK (0x40U) #define PMC_LVDSC2_LVWACK_SHIFT (6U) /*! LVWACK - Low-Voltage Warning Acknowledge */ #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) #define PMC_LVDSC2_LVWF_MASK (0x80U) #define PMC_LVDSC2_LVWF_SHIFT (7U) /*! LVWF - Low-Voltage Warning Flag * 0b0..Low-voltage warning event not detected * 0b1..Low-voltage warning event detected */ #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) /*! @} */ /*! @name REGSC - Regulator Status and Control Register */ /*! @{ */ #define PMC_REGSC_BIASEN_MASK (0x1U) #define PMC_REGSC_BIASEN_SHIFT (0U) /*! BIASEN - Bias Enable Bit * 0b0..Biasing disabled, core logic can run in full performance * 0b1..Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see Data Sheet for details) */ #define PMC_REGSC_BIASEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BIASEN_SHIFT)) & PMC_REGSC_BIASEN_MASK) #define PMC_REGSC_CLKBIASDIS_MASK (0x2U) #define PMC_REGSC_CLKBIASDIS_SHIFT (1U) /*! CLKBIASDIS - Clock Bias Disable Bit * 0b0..No effect * 0b1..In STOP or VLPS mode the bias currents and reference voltages for the following clock modules are * disabled: SIRC, FIRC, PLL. (if available on device) */ #define PMC_REGSC_CLKBIASDIS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_CLKBIASDIS_SHIFT)) & PMC_REGSC_CLKBIASDIS_MASK) #define PMC_REGSC_REGFPM_MASK (0x4U) #define PMC_REGSC_REGFPM_SHIFT (2U) /*! REGFPM - Regulator in Full Performance Mode Status Bit * 0b0..Regulator is in low power mode or transition to/from * 0b1..Regulator is in full performance mode */ #define PMC_REGSC_REGFPM(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGFPM_SHIFT)) & PMC_REGSC_REGFPM_MASK) #define PMC_REGSC_LPOSTAT_MASK (0x40U) #define PMC_REGSC_LPOSTAT_SHIFT (6U) /*! LPOSTAT - LPO Status Bit * 0b0..Low power oscillator in low phase * 0b1..Low power oscillator in high phase */ #define PMC_REGSC_LPOSTAT(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_LPOSTAT_SHIFT)) & PMC_REGSC_LPOSTAT_MASK) #define PMC_REGSC_LPODIS_MASK (0x80U) #define PMC_REGSC_LPODIS_SHIFT (7U) /*! LPODIS - LPO Disable Bit * 0b0..Low power oscillator enabled * 0b1..Low power oscillator disabled */ #define PMC_REGSC_LPODIS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_LPODIS_SHIFT)) & PMC_REGSC_LPODIS_MASK) /*! @} */ /*! @name LPOTRIM - Low Power Oscillator Trim Register */ /*! @{ */ #define PMC_LPOTRIM_LPOTRIM_MASK (0x1FU) #define PMC_LPOTRIM_LPOTRIM_SHIFT (0U) /*! LPOTRIM - LPO trimming bits */ #define PMC_LPOTRIM_LPOTRIM(x) (((uint8_t)(((uint8_t)(x)) << PMC_LPOTRIM_LPOTRIM_SHIFT)) & PMC_LPOTRIM_LPOTRIM_MASK) /*! @} */ /*! * @} */ /* end of group PMC_Register_Masks */ /* PMC - Peripheral instance base addresses */ /** Peripheral PMC base address */ #define PMC_BASE (0x4007D000u) /** Peripheral PMC base pointer */ #define PMC ((PMC_Type *)PMC_BASE) /** Array initializer of PMC peripheral base addresses */ #define PMC_BASE_ADDRS { PMC_BASE } /** Array initializer of PMC peripheral base pointers */ #define PMC_BASE_PTRS { PMC } /** Interrupt vectors for the PMC peripheral type */ #define PMC_IRQS { LVD_LVW_IRQn } /*! * @} */ /* end of group PMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PORT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer * @{ */ /** PORT - Register Layout Typedef */ typedef struct { __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ uint8_t RESERVED_0[24]; __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ uint8_t RESERVED_1[28]; __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ } PORT_Type; /* ---------------------------------------------------------------------------- -- PORT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Register_Masks PORT Register Masks * @{ */ /*! @name PCR - Pin Control Register n */ /*! @{ */ #define PORT_PCR_PS_MASK (0x1U) #define PORT_PCR_PS_SHIFT (0U) /*! PS - Pull Select * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. */ #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) #define PORT_PCR_PE_MASK (0x2U) #define PORT_PCR_PE_SHIFT (1U) /*! PE - Pull Enable * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. */ #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) #define PORT_PCR_PFE_MASK (0x10U) #define PORT_PCR_PFE_SHIFT (4U) /*! PFE - Passive Filter Enable * 0b0..Passive input filter is disabled on the corresponding pin. * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. * Refer to the device data sheet for filter characteristics. */ #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) #define PORT_PCR_DSE_MASK (0x40U) #define PORT_PCR_DSE_SHIFT (6U) /*! DSE - Drive Strength Enable * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output. */ #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) #define PORT_PCR_MUX_MASK (0x700U) #define PORT_PCR_MUX_SHIFT (8U) /*! MUX - Pin Mux Control * 0b000..Pin disabled (Alternative 0) (analog). * 0b001..Alternative 1 (GPIO). * 0b010..Alternative 2 (chip-specific). * 0b011..Alternative 3 (chip-specific). * 0b100..Alternative 4 (chip-specific). * 0b101..Alternative 5 (chip-specific). * 0b110..Alternative 6 (chip-specific). * 0b111..Alternative 7 (chip-specific). */ #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) #define PORT_PCR_LK_MASK (0x8000U) #define PORT_PCR_LK_SHIFT (15U) /*! LK - Lock Register * 0b0..Pin Control Register fields [15:0] are not locked. * 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. */ #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) #define PORT_PCR_IRQC_MASK (0xF0000U) #define PORT_PCR_IRQC_SHIFT (16U) /*! IRQC - Interrupt Configuration * 0b0000..Interrupt Status Flag (ISF) is disabled. * 0b0001..ISF flag and DMA request on rising edge. * 0b0010..ISF flag and DMA request on falling edge. * 0b0011..ISF flag and DMA request on either edge. * 0b0100..Reserved. * 0b0101..Reserved. * 0b0110..Reserved. * 0b0111..Reserved. * 0b1000..ISF flag and Interrupt when logic 0. * 0b1001..ISF flag and Interrupt on rising-edge. * 0b1010..ISF flag and Interrupt on falling-edge. * 0b1011..ISF flag and Interrupt on either edge. * 0b1100..ISF flag and Interrupt when logic 1. * 0b1101..Reserved. * 0b1110..Reserved. * 0b1111..Reserved. */ #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) #define PORT_PCR_ISF_MASK (0x1000000U) #define PORT_PCR_ISF_SHIFT (24U) /*! ISF - Interrupt Status Flag * 0b0..Configured interrupt is not detected. * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the * corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the * flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive * interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. */ #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) /*! @} */ /* The count of PORT_PCR */ #define PORT_PCR_COUNT (32U) /*! @name GPCLR - Global Pin Control Low Register */ /*! @{ */ #define PORT_GPCLR_GPWD_MASK (0xFFFFU) #define PORT_GPCLR_GPWD_SHIFT (0U) /*! GPWD - Global Pin Write Data */ #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) #define PORT_GPCLR_GPWE_SHIFT (16U) /*! GPWE - Global Pin Write Enable * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. */ #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) /*! @} */ /*! @name GPCHR - Global Pin Control High Register */ /*! @{ */ #define PORT_GPCHR_GPWD_MASK (0xFFFFU) #define PORT_GPCHR_GPWD_SHIFT (0U) /*! GPWD - Global Pin Write Data */ #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) #define PORT_GPCHR_GPWE_SHIFT (16U) /*! GPWE - Global Pin Write Enable * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. */ #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) /*! @} */ /*! @name ISFR - Interrupt Status Flag Register */ /*! @{ */ #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) #define PORT_ISFR_ISF_SHIFT (0U) /*! ISF - Interrupt Status Flag * 0b00000000000000000000000000000000..Configured interrupt is not detected. * 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a * DMA request, then the corresponding flag will be cleared automatically at * the completion of the requested DMA transfer. Otherwise, the flag remains set * until a logic 1 is written to the flag. If the pin is configured for a * level sensitive interrupt and the pin remains asserted, then the flag is set * again immediately after it is cleared. */ #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) /*! @} */ /*! @name DFER - Digital Filter Enable Register */ /*! @{ */ #define PORT_DFER_DFE_MASK (0xFFFFFFFFU) #define PORT_DFER_DFE_SHIFT (0U) /*! DFE - Digital Filter Enable * 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. * 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. */ #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) /*! @} */ /*! @name DFCR - Digital Filter Clock Register */ /*! @{ */ #define PORT_DFCR_CS_MASK (0x1U) #define PORT_DFCR_CS_SHIFT (0U) /*! CS - Clock Source * 0b0..Digital filters are clocked by the bus clock. * 0b1..Digital filters are clocked by the LPO clock. */ #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) /*! @} */ /*! @name DFWR - Digital Filter Width Register */ /*! @{ */ #define PORT_DFWR_FILT_MASK (0x1FU) #define PORT_DFWR_FILT_SHIFT (0U) /*! FILT - Filter Length */ #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) /*! @} */ /*! * @} */ /* end of group PORT_Register_Masks */ /* PORT - Peripheral instance base addresses */ /** Peripheral PORTA base address */ #define PORTA_BASE (0x40049000u) /** Peripheral PORTA base pointer */ #define PORTA ((PORT_Type *)PORTA_BASE) /** Peripheral PORTB base address */ #define PORTB_BASE (0x4004A000u) /** Peripheral PORTB base pointer */ #define PORTB ((PORT_Type *)PORTB_BASE) /** Peripheral PORTC base address */ #define PORTC_BASE (0x4004B000u) /** Peripheral PORTC base pointer */ #define PORTC ((PORT_Type *)PORTC_BASE) /** Peripheral PORTD base address */ #define PORTD_BASE (0x4004C000u) /** Peripheral PORTD base pointer */ #define PORTD ((PORT_Type *)PORTD_BASE) /** Peripheral PORTE base address */ #define PORTE_BASE (0x4004D000u) /** Peripheral PORTE base pointer */ #define PORTE ((PORT_Type *)PORTE_BASE) /** Array initializer of PORT peripheral base addresses */ #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } /** Array initializer of PORT peripheral base pointers */ #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } /** Interrupt vectors for the PORT peripheral type */ #define PORT_IRQS { PORTAE_IRQn, PORTBCD_IRQn, PORTBCD_IRQn, PORTBCD_IRQn, PORTAE_IRQn } /*! * @} */ /* end of group PORT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PWT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PWT_Peripheral_Access_Layer PWT Peripheral Access Layer * @{ */ /** PWT - Register Layout Typedef */ typedef struct { __IO uint8_t CS; /**< Pulse Width Timer Control and Status Register, offset: 0x0 */ __IO uint8_t CR; /**< Pulse Width Timer Control Register, offset: 0x1 */ __I uint8_t PPH; /**< Pulse Width Timer Positive Pulse Width Register: High, offset: 0x2 */ __I uint8_t PPL; /**< Pulse Width Timer Positive Pulse Width Register: Loq, offset: 0x3 */ __I uint8_t NPH; /**< Pulse Width Timer Negative Pulse Width Register: High, offset: 0x4 */ __I uint8_t NPL; /**< Pulse Width Timer Negative Pulse Width Register: Low, offset: 0x5 */ __I uint8_t CNTH; /**< Pulse Width Timer Counter Register: High, offset: 0x6 */ __I uint8_t CNTL; /**< Pulse Width Timer Counter Register: Low, offset: 0x7 */ } PWT_Type; /* ---------------------------------------------------------------------------- -- PWT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PWT_Register_Masks PWT Register Masks * @{ */ /*! @name CS - Pulse Width Timer Control and Status Register */ /*! @{ */ #define PWT_CS_PWTOV_MASK (0x1U) #define PWT_CS_PWTOV_SHIFT (0U) /*! PWTOV - PWT Counter Overflow * 0b0..PWT counter no overflow. * 0b1..PWT counter runs from 0xFFFF to 0x0000. */ #define PWT_CS_PWTOV(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PWTOV_SHIFT)) & PWT_CS_PWTOV_MASK) #define PWT_CS_PWTRDY_MASK (0x2U) #define PWT_CS_PWTRDY_SHIFT (1U) /*! PWTRDY - PWT Pulse Width Valid * 0b0..PWT pulse width register(s) is not up-to-date. * 0b1..PWT pulse width register(s) has been updated. */ #define PWT_CS_PWTRDY(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PWTRDY_SHIFT)) & PWT_CS_PWTRDY_MASK) #define PWT_CS_FCTLE_MASK (0x4U) #define PWT_CS_FCTLE_SHIFT (2U) /*! FCTLE - First counter load enable after enable * 0b0..Do not load the first counter values to corresponding registers * 0b1..Load the first coutner value to corresponding registers depended by the PWTIN level */ #define PWT_CS_FCTLE(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_FCTLE_SHIFT)) & PWT_CS_FCTLE_MASK) #define PWT_CS_PWTSR_MASK (0x8U) #define PWT_CS_PWTSR_SHIFT (3U) /*! PWTSR - PWT Soft Reset * 0b0..No action taken. * 0b1..Writing 1 to this field will perform soft reset to PWT. */ #define PWT_CS_PWTSR(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PWTSR_SHIFT)) & PWT_CS_PWTSR_MASK) #define PWT_CS_POVIE_MASK (0x10U) #define PWT_CS_POVIE_SHIFT (4U) /*! POVIE - PWT Counter Overflow Interrupt Enable * 0b0..Disable PWT to generate interrupt when PWTOV is set. * 0b1..Enable PWT to generate interrupt when PWTOV is set. */ #define PWT_CS_POVIE(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_POVIE_SHIFT)) & PWT_CS_POVIE_MASK) #define PWT_CS_PRDYIE_MASK (0x20U) #define PWT_CS_PRDYIE_SHIFT (5U) /*! PRDYIE - PWT Pulse Width Data Ready Interrupt Enable * 0b0..Disable PWT to generate interrupt when PWTRDY is set. * 0b1..Enable PWT to generate interrupt when PWTRDY is set. */ #define PWT_CS_PRDYIE(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PRDYIE_SHIFT)) & PWT_CS_PRDYIE_MASK) #define PWT_CS_PWTIE_MASK (0x40U) #define PWT_CS_PWTIE_SHIFT (6U) /*! PWTIE - PWT Module Interrupt Enable * 0b0..Disables the PWT to generate interrupt. * 0b1..Enables the PWT to generate interrupt. */ #define PWT_CS_PWTIE(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PWTIE_SHIFT)) & PWT_CS_PWTIE_MASK) #define PWT_CS_PWTEN_MASK (0x80U) #define PWT_CS_PWTEN_SHIFT (7U) /*! PWTEN - PWT Module Enable * 0b0..The PWT is disabled. * 0b1..The PWT is enabled. */ #define PWT_CS_PWTEN(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PWTEN_SHIFT)) & PWT_CS_PWTEN_MASK) /*! @} */ /*! @name CR - Pulse Width Timer Control Register */ /*! @{ */ #define PWT_CR_PRE_MASK (0x7U) #define PWT_CR_PRE_SHIFT (0U) /*! PRE - PWT Clock Prescaler (CLKPRE) Setting * 0b000..Clock divided by 1. * 0b001..Clock divided by 2. * 0b010..Clock divided by 4. * 0b011..Clock divided by 8. * 0b100..Clock divided by 16. * 0b101..Clock divided by 32. * 0b110..Clock divided by 64. * 0b111..Clock divided by 128. */ #define PWT_CR_PRE(x) (((uint8_t)(((uint8_t)(x)) << PWT_CR_PRE_SHIFT)) & PWT_CR_PRE_MASK) #define PWT_CR_LVL_MASK (0x8U) #define PWT_CR_LVL_SHIFT (3U) /*! LVL - PWTIN Level when Overflows */ #define PWT_CR_LVL(x) (((uint8_t)(((uint8_t)(x)) << PWT_CR_LVL_SHIFT)) & PWT_CR_LVL_MASK) #define PWT_CR_TGL_MASK (0x10U) #define PWT_CR_TGL_SHIFT (4U) /*! TGL - PWTIN states Toggled from last state * 0b0..The selected PWTIN hasn't changed its original states from last time. * 0b1..The selected PWTIN has toggled its states. */ #define PWT_CR_TGL(x) (((uint8_t)(((uint8_t)(x)) << PWT_CR_TGL_SHIFT)) & PWT_CR_TGL_MASK) #define PWT_CR_PINSEL_MASK (0x60U) #define PWT_CR_PINSEL_SHIFT (5U) /*! PINSEL - PWT Pulse Inputs Selection * 0b00..PWTIN[0] is enabled. * 0b01..PWTIN[1] is enabled. * 0b10..PWTIN[2] enabled. * 0b11..PWTIN[3] enabled. */ #define PWT_CR_PINSEL(x) (((uint8_t)(((uint8_t)(x)) << PWT_CR_PINSEL_SHIFT)) & PWT_CR_PINSEL_MASK) #define PWT_CR_PCLKS_MASK (0x80U) #define PWT_CR_PCLKS_SHIFT (7U) /*! PCLKS - PWT Clock Source Selection * 0b0..BUS_CLK is selected as the clock source of PWT counter. * 0b1..Alternative clock is selected as the clock source of PWT counter. */ #define PWT_CR_PCLKS(x) (((uint8_t)(((uint8_t)(x)) << PWT_CR_PCLKS_SHIFT)) & PWT_CR_PCLKS_MASK) /*! @} */ /*! @name PPH - Pulse Width Timer Positive Pulse Width Register: High */ /*! @{ */ #define PWT_PPH_PPWH_MASK (0xFFU) #define PWT_PPH_PPWH_SHIFT (0U) /*! PPWH - Positive Pulse Width[15:8] */ #define PWT_PPH_PPWH(x) (((uint8_t)(((uint8_t)(x)) << PWT_PPH_PPWH_SHIFT)) & PWT_PPH_PPWH_MASK) /*! @} */ /*! @name PPL - Pulse Width Timer Positive Pulse Width Register: Loq */ /*! @{ */ #define PWT_PPL_PPWL_MASK (0xFFU) #define PWT_PPL_PPWL_SHIFT (0U) /*! PPWL - Positive Pulse Width[7:0] */ #define PWT_PPL_PPWL(x) (((uint8_t)(((uint8_t)(x)) << PWT_PPL_PPWL_SHIFT)) & PWT_PPL_PPWL_MASK) /*! @} */ /*! @name NPH - Pulse Width Timer Negative Pulse Width Register: High */ /*! @{ */ #define PWT_NPH_NPWH_MASK (0xFFU) #define PWT_NPH_NPWH_SHIFT (0U) /*! NPWH - Negative Pulse Width[15:8] */ #define PWT_NPH_NPWH(x) (((uint8_t)(((uint8_t)(x)) << PWT_NPH_NPWH_SHIFT)) & PWT_NPH_NPWH_MASK) /*! @} */ /*! @name NPL - Pulse Width Timer Negative Pulse Width Register: Low */ /*! @{ */ #define PWT_NPL_NPWL_MASK (0xFFU) #define PWT_NPL_NPWL_SHIFT (0U) /*! NPWL - Negative Pulse Width[7:0] */ #define PWT_NPL_NPWL(x) (((uint8_t)(((uint8_t)(x)) << PWT_NPL_NPWL_SHIFT)) & PWT_NPL_NPWL_MASK) /*! @} */ /*! @name CNTH - Pulse Width Timer Counter Register: High */ /*! @{ */ #define PWT_CNTH_PWTH_MASK (0xFFU) #define PWT_CNTH_PWTH_SHIFT (0U) /*! PWTH - PWT counter[15:8] */ #define PWT_CNTH_PWTH(x) (((uint8_t)(((uint8_t)(x)) << PWT_CNTH_PWTH_SHIFT)) & PWT_CNTH_PWTH_MASK) /*! @} */ /*! @name CNTL - Pulse Width Timer Counter Register: Low */ /*! @{ */ #define PWT_CNTL_PWTL_MASK (0xFFU) #define PWT_CNTL_PWTL_SHIFT (0U) /*! PWTL - PWT counter[7:0] */ #define PWT_CNTL_PWTL(x) (((uint8_t)(((uint8_t)(x)) << PWT_CNTL_PWTL_SHIFT)) & PWT_CNTL_PWTL_MASK) /*! @} */ /*! * @} */ /* end of group PWT_Register_Masks */ /* PWT - Peripheral instance base addresses */ /** Peripheral PWT base address */ #define PWT_BASE (0x40056000u) /** Peripheral PWT base pointer */ #define PWT ((PWT_Type *)PWT_BASE) /** Array initializer of PWT peripheral base addresses */ #define PWT_BASE_ADDRS { PWT_BASE } /** Array initializer of PWT peripheral base pointers */ #define PWT_BASE_PTRS { PWT } /** Interrupt vectors for the PWT peripheral type */ #define PWT_IRQS { PWT_LPTMR0_IRQn } /*! * @} */ /* end of group PWT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer * @{ */ /** RCM - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __I uint32_t SRS; /**< System Reset Status Register, offset: 0x8 */ __IO uint32_t RPC; /**< Reset Pin Control register, offset: 0xC */ __IO uint32_t MR; /**< Mode Register, offset: 0x10 */ __IO uint32_t FM; /**< Force Mode Register, offset: 0x14 */ __IO uint32_t SSRS; /**< Sticky System Reset Status Register, offset: 0x18 */ __IO uint32_t SRIE; /**< System Reset Interrupt Enable Register, offset: 0x1C */ } RCM_Type; /* ---------------------------------------------------------------------------- -- RCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RCM_Register_Masks RCM Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define RCM_VERID_FEATURE_MASK (0xFFFFU) #define RCM_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000011..Standard feature set. */ #define RCM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_FEATURE_SHIFT)) & RCM_VERID_FEATURE_MASK) #define RCM_VERID_MINOR_MASK (0xFF0000U) #define RCM_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define RCM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_MINOR_SHIFT)) & RCM_VERID_MINOR_MASK) #define RCM_VERID_MAJOR_MASK (0xFF000000U) #define RCM_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define RCM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_MAJOR_SHIFT)) & RCM_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define RCM_PARAM_ELVD_MASK (0x2U) #define RCM_PARAM_ELVD_SHIFT (1U) /*! ELVD - Existence of SRS[LVD] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_ELVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELVD_SHIFT)) & RCM_PARAM_ELVD_MASK) #define RCM_PARAM_ELOC_MASK (0x4U) #define RCM_PARAM_ELOC_SHIFT (2U) /*! ELOC - Existence of SRS[LOC] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_ELOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELOC_SHIFT)) & RCM_PARAM_ELOC_MASK) #define RCM_PARAM_ELOL_MASK (0x8U) #define RCM_PARAM_ELOL_SHIFT (3U) /*! ELOL - Existence of SRS[LOL] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_ELOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELOL_SHIFT)) & RCM_PARAM_ELOL_MASK) #define RCM_PARAM_EWDOG_MASK (0x20U) #define RCM_PARAM_EWDOG_SHIFT (5U) /*! EWDOG - Existence of SRS[WDOG] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_EWDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EWDOG_SHIFT)) & RCM_PARAM_EWDOG_MASK) #define RCM_PARAM_EPIN_MASK (0x40U) #define RCM_PARAM_EPIN_SHIFT (6U) /*! EPIN - Existence of SRS[PIN] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_EPIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EPIN_SHIFT)) & RCM_PARAM_EPIN_MASK) #define RCM_PARAM_EPOR_MASK (0x80U) #define RCM_PARAM_EPOR_SHIFT (7U) /*! EPOR - Existence of SRS[POR] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_EPOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EPOR_SHIFT)) & RCM_PARAM_EPOR_MASK) #define RCM_PARAM_ELOCKUP_MASK (0x200U) #define RCM_PARAM_ELOCKUP_SHIFT (9U) /*! ELOCKUP - Existence of SRS[LOCKUP] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_ELOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ELOCKUP_SHIFT)) & RCM_PARAM_ELOCKUP_MASK) #define RCM_PARAM_ESW_MASK (0x400U) #define RCM_PARAM_ESW_SHIFT (10U) /*! ESW - Existence of SRS[SW] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_ESW(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ESW_SHIFT)) & RCM_PARAM_ESW_MASK) #define RCM_PARAM_EMDM_AP_MASK (0x800U) #define RCM_PARAM_EMDM_AP_SHIFT (11U) /*! EMDM_AP - Existence of SRS[MDM_AP] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_EMDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_EMDM_AP_SHIFT)) & RCM_PARAM_EMDM_AP_MASK) #define RCM_PARAM_ESACKERR_MASK (0x2000U) #define RCM_PARAM_ESACKERR_SHIFT (13U) /*! ESACKERR - Existence of SRS[SACKERR] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_ESACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ESACKERR_SHIFT)) & RCM_PARAM_ESACKERR_MASK) #define RCM_PARAM_ECORE1_MASK (0x10000U) #define RCM_PARAM_ECORE1_SHIFT (16U) /*! ECORE1 - Existence of SRS[CORE1] status indication feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define RCM_PARAM_ECORE1(x) (((uint32_t)(((uint32_t)(x)) << RCM_PARAM_ECORE1_SHIFT)) & RCM_PARAM_ECORE1_MASK) /*! @} */ /*! @name SRS - System Reset Status Register */ /*! @{ */ #define RCM_SRS_LVD_MASK (0x2U) #define RCM_SRS_LVD_SHIFT (1U) /*! LVD - Low-Voltage Detect Reset or High-Voltage Detect Reset * 0b0..Reset not caused by LVD trip, HVD trip or POR * 0b1..Reset caused by LVD trip, HVD trip or POR */ #define RCM_SRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LVD_SHIFT)) & RCM_SRS_LVD_MASK) #define RCM_SRS_LOC_MASK (0x4U) #define RCM_SRS_LOC_SHIFT (2U) /*! LOC - Loss-of-Clock Reset * 0b0..Reset not caused by a loss of external clock. * 0b1..Reset caused by a loss of external clock. */ #define RCM_SRS_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOC_SHIFT)) & RCM_SRS_LOC_MASK) #define RCM_SRS_LOL_MASK (0x8U) #define RCM_SRS_LOL_SHIFT (3U) /*! LOL - Loss-of-Lock Reset * 0b0..Reset not caused by a loss of lock in the PLL/FLL * 0b1..Reset caused by a loss of lock in the PLL/FLL */ #define RCM_SRS_LOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOL_SHIFT)) & RCM_SRS_LOL_MASK) #define RCM_SRS_WDOG_MASK (0x20U) #define RCM_SRS_WDOG_SHIFT (5U) /*! WDOG - Watchdog * 0b0..Reset not caused by watchdog timeout * 0b1..Reset caused by watchdog timeout */ #define RCM_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_WDOG_SHIFT)) & RCM_SRS_WDOG_MASK) #define RCM_SRS_PIN_MASK (0x40U) #define RCM_SRS_PIN_SHIFT (6U) /*! PIN - External Reset Pin * 0b0..Reset not caused by external reset pin * 0b1..Reset caused by external reset pin */ #define RCM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_PIN_SHIFT)) & RCM_SRS_PIN_MASK) #define RCM_SRS_POR_MASK (0x80U) #define RCM_SRS_POR_SHIFT (7U) /*! POR - Power-On Reset * 0b0..Reset not caused by POR * 0b1..Reset caused by POR */ #define RCM_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_POR_SHIFT)) & RCM_SRS_POR_MASK) #define RCM_SRS_LOCKUP_MASK (0x200U) #define RCM_SRS_LOCKUP_SHIFT (9U) /*! LOCKUP - Core Lockup * 0b0..Reset not caused by core LOCKUP event * 0b1..Reset caused by core LOCKUP event */ #define RCM_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOCKUP_SHIFT)) & RCM_SRS_LOCKUP_MASK) #define RCM_SRS_SW_MASK (0x400U) #define RCM_SRS_SW_SHIFT (10U) /*! SW - Software * 0b0..Reset not caused by software setting of SYSRESETREQ bit * 0b1..Reset caused by software setting of SYSRESETREQ bit */ #define RCM_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_SW_SHIFT)) & RCM_SRS_SW_MASK) #define RCM_SRS_MDM_AP_MASK (0x800U) #define RCM_SRS_MDM_AP_SHIFT (11U) /*! MDM_AP - MDM-AP System Reset Request * 0b0..Reset was not caused by host debugger system setting of the System Reset Request bit * 0b1..Reset was caused by host debugger system setting of the System Reset Request bit */ #define RCM_SRS_MDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_MDM_AP_SHIFT)) & RCM_SRS_MDM_AP_MASK) #define RCM_SRS_SACKERR_MASK (0x2000U) #define RCM_SRS_SACKERR_SHIFT (13U) /*! SACKERR - Stop Acknowledge Error * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode */ #define RCM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_SACKERR_SHIFT)) & RCM_SRS_SACKERR_MASK) /*! @} */ /*! @name RPC - Reset Pin Control register */ /*! @{ */ #define RCM_RPC_RSTFLTSRW_MASK (0x3U) #define RCM_RPC_RSTFLTSRW_SHIFT (0U) /*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes * 0b00..All filtering disabled * 0b01..Bus clock filter enabled for normal operation * 0b10..LPO clock filter enabled for normal operation * 0b11..Reserved */ #define RCM_RPC_RSTFLTSRW(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSRW_SHIFT)) & RCM_RPC_RSTFLTSRW_MASK) #define RCM_RPC_RSTFLTSS_MASK (0x4U) #define RCM_RPC_RSTFLTSS_SHIFT (2U) /*! RSTFLTSS - Reset Pin Filter Select in Stop Mode * 0b0..All filtering disabled * 0b1..LPO clock filter enabled */ #define RCM_RPC_RSTFLTSS(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSS_SHIFT)) & RCM_RPC_RSTFLTSS_MASK) #define RCM_RPC_RSTFLTSEL_MASK (0x1F00U) #define RCM_RPC_RSTFLTSEL_SHIFT (8U) /*! RSTFLTSEL - Reset Pin Filter Bus Clock Select */ #define RCM_RPC_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSEL_SHIFT)) & RCM_RPC_RSTFLTSEL_MASK) /*! @} */ /*! @name MR - Mode Register */ /*! @{ */ #define RCM_MR_BOOTROM_MASK (0x6U) #define RCM_MR_BOOTROM_SHIFT (1U) /*! BOOTROM - Boot ROM Configuration * 0b00..Boot from Flash * 0b01..Boot from ROM due to BOOTCFG0 pin assertion / Reserved if no Boot pin * 0b10..Boot form ROM due to FOPT[7] configuration * 0b11..Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration */ #define RCM_MR_BOOTROM(x) (((uint32_t)(((uint32_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK) /*! @} */ /*! @name FM - Force Mode Register */ /*! @{ */ #define RCM_FM_FORCEROM_MASK (0x6U) #define RCM_FM_FORCEROM_SHIFT (1U) /*! FORCEROM - Force ROM Boot * 0b00..No effect * 0b01..Force boot from ROM with RCM_MR[1] set. * 0b10..Force boot from ROM with RCM_MR[2] set. * 0b11..Force boot from ROM with RCM_MR[2:1] set. */ #define RCM_FM_FORCEROM(x) (((uint32_t)(((uint32_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK) /*! @} */ /*! @name SSRS - Sticky System Reset Status Register */ /*! @{ */ #define RCM_SSRS_SLVD_MASK (0x2U) #define RCM_SSRS_SLVD_SHIFT (1U) /*! SLVD - Sticky Low-Voltage Detect Reset * 0b0..Reset not caused by LVD trip or POR * 0b1..Reset caused by LVD trip or POR */ #define RCM_SSRS_SLVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLVD_SHIFT)) & RCM_SSRS_SLVD_MASK) #define RCM_SSRS_SLOC_MASK (0x4U) #define RCM_SSRS_SLOC_SHIFT (2U) /*! SLOC - Sticky Loss-of-Clock Reset * 0b0..Reset not caused by a loss of external clock. * 0b1..Reset caused by a loss of external clock. */ #define RCM_SSRS_SLOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOC_SHIFT)) & RCM_SSRS_SLOC_MASK) #define RCM_SSRS_SLOL_MASK (0x8U) #define RCM_SSRS_SLOL_SHIFT (3U) /*! SLOL - Sticky Loss-of-Lock Reset * 0b0..Reset not caused by a loss of lock in the PLL/FLL * 0b1..Reset caused by a loss of lock in the PLL/FLL */ #define RCM_SSRS_SLOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOL_SHIFT)) & RCM_SSRS_SLOL_MASK) #define RCM_SSRS_SWDOG_MASK (0x20U) #define RCM_SSRS_SWDOG_SHIFT (5U) /*! SWDOG - Sticky Watchdog * 0b0..Reset not caused by watchdog timeout * 0b1..Reset caused by watchdog timeout */ #define RCM_SSRS_SWDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SWDOG_SHIFT)) & RCM_SSRS_SWDOG_MASK) #define RCM_SSRS_SPIN_MASK (0x40U) #define RCM_SSRS_SPIN_SHIFT (6U) /*! SPIN - Sticky External Reset Pin * 0b0..Reset not caused by external reset pin * 0b1..Reset caused by external reset pin */ #define RCM_SSRS_SPIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SPIN_SHIFT)) & RCM_SSRS_SPIN_MASK) #define RCM_SSRS_SPOR_MASK (0x80U) #define RCM_SSRS_SPOR_SHIFT (7U) /*! SPOR - Sticky Power-On Reset * 0b0..Reset not caused by POR * 0b1..Reset caused by POR */ #define RCM_SSRS_SPOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SPOR_SHIFT)) & RCM_SSRS_SPOR_MASK) #define RCM_SSRS_SLOCKUP_MASK (0x200U) #define RCM_SSRS_SLOCKUP_SHIFT (9U) /*! SLOCKUP - Sticky Core Lockup * 0b0..Reset not caused by core LOCKUP event * 0b1..Reset caused by core LOCKUP event */ #define RCM_SSRS_SLOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOCKUP_SHIFT)) & RCM_SSRS_SLOCKUP_MASK) #define RCM_SSRS_SSW_MASK (0x400U) #define RCM_SSRS_SSW_SHIFT (10U) /*! SSW - Sticky Software * 0b0..Reset not caused by software setting of SYSRESETREQ bit * 0b1..Reset caused by software setting of SYSRESETREQ bit */ #define RCM_SSRS_SSW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SSW_SHIFT)) & RCM_SSRS_SSW_MASK) #define RCM_SSRS_SMDM_AP_MASK (0x800U) #define RCM_SSRS_SMDM_AP_SHIFT (11U) /*! SMDM_AP - Sticky MDM-AP System Reset Request * 0b0..Reset was not caused by host debugger system setting of the System Reset Request bit * 0b1..Reset was caused by host debugger system setting of the System Reset Request bit */ #define RCM_SSRS_SMDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SMDM_AP_SHIFT)) & RCM_SSRS_SMDM_AP_MASK) #define RCM_SSRS_SSACKERR_MASK (0x2000U) #define RCM_SSRS_SSACKERR_SHIFT (13U) /*! SSACKERR - Sticky Stop Acknowledge Error * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode */ #define RCM_SSRS_SSACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SSACKERR_SHIFT)) & RCM_SSRS_SSACKERR_MASK) /*! @} */ /*! @name SRIE - System Reset Interrupt Enable Register */ /*! @{ */ #define RCM_SRIE_DELAY_MASK (0x3U) #define RCM_SRIE_DELAY_SHIFT (0U) /*! DELAY - Reset Delay Time * 0b00..10 LPO cycles * 0b01..34 LPO cycles * 0b10..130 LPO cycles * 0b11..514 LPO cycles */ #define RCM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_DELAY_SHIFT)) & RCM_SRIE_DELAY_MASK) #define RCM_SRIE_LOC_MASK (0x4U) #define RCM_SRIE_LOC_SHIFT (2U) /*! LOC - Loss-of-Clock Interrupt * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define RCM_SRIE_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOC_SHIFT)) & RCM_SRIE_LOC_MASK) #define RCM_SRIE_LOL_MASK (0x8U) #define RCM_SRIE_LOL_SHIFT (3U) /*! LOL - Loss-of-Lock Interrupt * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define RCM_SRIE_LOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOL_SHIFT)) & RCM_SRIE_LOL_MASK) #define RCM_SRIE_WDOG_MASK (0x20U) #define RCM_SRIE_WDOG_SHIFT (5U) /*! WDOG - Watchdog Interrupt * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define RCM_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_WDOG_SHIFT)) & RCM_SRIE_WDOG_MASK) #define RCM_SRIE_PIN_MASK (0x40U) #define RCM_SRIE_PIN_SHIFT (6U) /*! PIN - External Reset Pin Interrupt * 0b0..Reset not caused by external reset pin * 0b1..Reset caused by external reset pin */ #define RCM_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_PIN_SHIFT)) & RCM_SRIE_PIN_MASK) #define RCM_SRIE_GIE_MASK (0x80U) #define RCM_SRIE_GIE_SHIFT (7U) /*! GIE - Global Interrupt Enable * 0b0..All interrupt sources disabled. * 0b1..All interrupt sources enabled. Note that the individual interrupt-enable bits still need to be set to generate interrupts. */ #define RCM_SRIE_GIE(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_GIE_SHIFT)) & RCM_SRIE_GIE_MASK) #define RCM_SRIE_LOCKUP_MASK (0x200U) #define RCM_SRIE_LOCKUP_SHIFT (9U) /*! LOCKUP - Core Lockup Interrupt * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define RCM_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOCKUP_SHIFT)) & RCM_SRIE_LOCKUP_MASK) #define RCM_SRIE_SW_MASK (0x400U) #define RCM_SRIE_SW_SHIFT (10U) /*! SW - Software Interrupt * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define RCM_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_SW_SHIFT)) & RCM_SRIE_SW_MASK) #define RCM_SRIE_MDM_AP_MASK (0x800U) #define RCM_SRIE_MDM_AP_SHIFT (11U) /*! MDM_AP - MDM-AP System Reset Request * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define RCM_SRIE_MDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_MDM_AP_SHIFT)) & RCM_SRIE_MDM_AP_MASK) #define RCM_SRIE_SACKERR_MASK (0x2000U) #define RCM_SRIE_SACKERR_SHIFT (13U) /*! SACKERR - Stop Acknowledge Error Interrupt * 0b0..Interrupt disabled. * 0b1..Interrupt enabled. */ #define RCM_SRIE_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_SACKERR_SHIFT)) & RCM_SRIE_SACKERR_MASK) /*! @} */ /*! * @} */ /* end of group RCM_Register_Masks */ /* RCM - Peripheral instance base addresses */ /** Peripheral RCM base address */ #define RCM_BASE (0x4007F000u) /** Peripheral RCM base pointer */ #define RCM ((RCM_Type *)RCM_BASE) /** Array initializer of RCM peripheral base addresses */ #define RCM_BASE_ADDRS { RCM_BASE } /** Array initializer of RCM peripheral base pointers */ #define RCM_BASE_PTRS { RCM } /** Interrupt vectors for the RCM peripheral type */ #define RCM_IRQS { RCM_IRQn } /*! * @} */ /* end of group RCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ROM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer * @{ */ /** ROM - Register Layout Typedef */ typedef struct { __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ uint8_t RESERVED_0[4028]; __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ } ROM_Type; /* ---------------------------------------------------------------------------- -- ROM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ROM_Register_Masks ROM Register Masks * @{ */ /*! @name ENTRY - Entry */ /*! @{ */ #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) #define ROM_ENTRY_ENTRY_SHIFT (0U) /*! ENTRY - ENTRY */ #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) /*! @} */ /* The count of ROM_ENTRY */ #define ROM_ENTRY_COUNT (3U) /*! @name TABLEMARK - End of Table Marker Register */ /*! @{ */ #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) #define ROM_TABLEMARK_MARK_SHIFT (0U) /*! MARK - MARK */ #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) /*! @} */ /*! @name SYSACCESS - System Access Register */ /*! @{ */ #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) /*! SYSACCESS - SYSACCESS */ #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) /*! @} */ /*! @name PERIPHID4 - Peripheral ID Register */ /*! @{ */ #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID5 - Peripheral ID Register */ /*! @{ */ #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID6 - Peripheral ID Register */ /*! @{ */ #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID7 - Peripheral ID Register */ /*! @{ */ #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID0 - Peripheral ID Register */ /*! @{ */ #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID1 - Peripheral ID Register */ /*! @{ */ #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID2 - Peripheral ID Register */ /*! @{ */ #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) /*! @} */ /*! @name PERIPHID3 - Peripheral ID Register */ /*! @{ */ #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) /*! PERIPHID - PERIPHID */ #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) /*! @} */ /*! @name COMPID - Component ID Register */ /*! @{ */ #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) #define ROM_COMPID_COMPID_SHIFT (0U) /*! COMPID - Component ID */ #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) /*! @} */ /* The count of ROM_COMPID */ #define ROM_COMPID_COUNT (4U) /*! * @} */ /* end of group ROM_Register_Masks */ /* ROM - Peripheral instance base addresses */ /** Peripheral ROM base address */ #define ROM_BASE (0xF0002000u) /** Peripheral ROM base pointer */ #define ROM ((ROM_Type *)ROM_BASE) /** Array initializer of ROM peripheral base addresses */ #define ROM_BASE_ADDRS { ROM_BASE } /** Array initializer of ROM peripheral base pointers */ #define ROM_BASE_PTRS { ROM } /*! * @} */ /* end of group ROM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RTC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer * @{ */ /** RTC - Register Layout Typedef */ typedef struct { __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ uint8_t RESERVED_0[2016]; __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ } RTC_Type; /* ---------------------------------------------------------------------------- -- RTC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Register_Masks RTC Register Masks * @{ */ /*! @name TSR - RTC Time Seconds Register */ /*! @{ */ #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) #define RTC_TSR_TSR_SHIFT (0U) /*! TSR - Time Seconds Register */ #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) /*! @} */ /*! @name TPR - RTC Time Prescaler Register */ /*! @{ */ #define RTC_TPR_TPR_MASK (0xFFFFU) #define RTC_TPR_TPR_SHIFT (0U) /*! TPR - Time Prescaler Register */ #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) /*! @} */ /*! @name TAR - RTC Time Alarm Register */ /*! @{ */ #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) #define RTC_TAR_TAR_SHIFT (0U) /*! TAR - Time Alarm Register */ #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) /*! @} */ /*! @name TCR - RTC Time Compensation Register */ /*! @{ */ #define RTC_TCR_TCR_MASK (0xFFU) #define RTC_TCR_TCR_SHIFT (0U) /*! TCR - Time Compensation Register * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles. */ #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) #define RTC_TCR_CIR_MASK (0xFF00U) #define RTC_TCR_CIR_SHIFT (8U) /*! CIR - Compensation Interval Register */ #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) #define RTC_TCR_TCV_MASK (0xFF0000U) #define RTC_TCR_TCV_SHIFT (16U) /*! TCV - Time Compensation Value */ #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) #define RTC_TCR_CIC_MASK (0xFF000000U) #define RTC_TCR_CIC_SHIFT (24U) /*! CIC - Compensation Interval Counter */ #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) /*! @} */ /*! @name CR - RTC Control Register */ /*! @{ */ #define RTC_CR_SWR_MASK (0x1U) #define RTC_CR_SWR_SHIFT (0U) /*! SWR - Software Reset * 0b0..No effect. * 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is * cleared by POR and by software explicitly clearing it. */ #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) #define RTC_CR_WPE_MASK (0x2U) #define RTC_CR_WPE_SHIFT (1U) /*! WPE - Wakeup Pin Enable * 0b0..Wakeup pin is disabled. * 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. */ #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) #define RTC_CR_SUP_MASK (0x4U) #define RTC_CR_SUP_SHIFT (2U) /*! SUP - Supervisor Access * 0b0..Non-supervisor mode write accesses are not supported and generate a bus error. * 0b1..Non-supervisor mode write accesses are supported. */ #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) #define RTC_CR_UM_MASK (0x8U) #define RTC_CR_UM_SHIFT (3U) /*! UM - Update Mode * 0b0..Registers cannot be written when locked. * 0b1..Registers can be written when locked under limited conditions. */ #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) #define RTC_CR_WPS_MASK (0x10U) #define RTC_CR_WPS_SHIFT (4U) /*! WPS - Wakeup Pin Select * 0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. * 0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. */ #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) #define RTC_CR_CPS_MASK (0x20U) #define RTC_CR_CPS_SHIFT (5U) /*! CPS - Clock Pin Select * 0b0..The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT. * 0b1..The RTC 32kHz crystal clock is output on RTC_CLKOUT. */ #define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPS_SHIFT)) & RTC_CR_CPS_MASK) #define RTC_CR_LPOS_MASK (0x80U) #define RTC_CR_LPOS_SHIFT (7U) /*! LPOS - LPO Select * 0b0..RTC prescaler increments using 32 kHz crystal. * 0b1..RTC prescaler increments using LPO, bits [4:0] of the prescaler are bypassed. */ #define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK) #define RTC_CR_OSCE_MASK (0x100U) #define RTC_CR_OSCE_SHIFT (8U) /*! OSCE - Oscillator Enable * 0b0..32.768 kHz oscillator is disabled. * 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before * enabling the time counter to allow the 32.768 kHz clock time to stabilize. */ #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) #define RTC_CR_CLKO_MASK (0x200U) #define RTC_CR_CLKO_SHIFT (9U) /*! CLKO - Clock Output * 0b0..The 32 kHz clock is allowed to output on RTC_CLKOUT. * 0b1..The 32 kHz clock is not allowed to output on RTC_CLKOUT. */ #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) #define RTC_CR_CPE_MASK (0x3000000U) #define RTC_CR_CPE_SHIFT (24U) /*! CPE - Clock Pin Enable * 0b00..RTC_CLKOUT is disabled. * 0b01..RTC_CLKOUT is enabled. * 0b10..Reserved. * 0b11..Reserved. */ #define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPE_SHIFT)) & RTC_CR_CPE_MASK) /*! @} */ /*! @name SR - RTC Status Register */ /*! @{ */ #define RTC_SR_TIF_MASK (0x1U) #define RTC_SR_TIF_SHIFT (0U) /*! TIF - Time Invalid Flag * 0b0..Time is valid. * 0b1..Time is invalid and time counter is read as zero. */ #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) #define RTC_SR_TOF_MASK (0x2U) #define RTC_SR_TOF_SHIFT (1U) /*! TOF - Time Overflow Flag * 0b0..Time overflow has not occurred. * 0b1..Time overflow has occurred and time counter is read as zero. */ #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) #define RTC_SR_TAF_MASK (0x4U) #define RTC_SR_TAF_SHIFT (2U) /*! TAF - Time Alarm Flag * 0b0..Time alarm has not occurred. * 0b1..Time alarm has occurred. */ #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) #define RTC_SR_TCE_MASK (0x10U) #define RTC_SR_TCE_SHIFT (4U) /*! TCE - Time Counter Enable * 0b0..Time counter is disabled. * 0b1..Time counter is enabled. */ #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) /*! @} */ /*! @name LR - RTC Lock Register */ /*! @{ */ #define RTC_LR_TCL_MASK (0x8U) #define RTC_LR_TCL_SHIFT (3U) /*! TCL - Time Compensation Lock * 0b0..Time Compensation Register is locked and writes are ignored. * 0b1..Time Compensation Register is not locked and writes complete as normal. */ #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) #define RTC_LR_CRL_MASK (0x10U) #define RTC_LR_CRL_SHIFT (4U) /*! CRL - Control Register Lock * 0b0..Control Register is locked and writes are ignored. * 0b1..Control Register is not locked and writes complete as normal. */ #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) #define RTC_LR_SRL_MASK (0x20U) #define RTC_LR_SRL_SHIFT (5U) /*! SRL - Status Register Lock * 0b0..Status Register is locked and writes are ignored. * 0b1..Status Register is not locked and writes complete as normal. */ #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) #define RTC_LR_LRL_MASK (0x40U) #define RTC_LR_LRL_SHIFT (6U) /*! LRL - Lock Register Lock * 0b0..Lock Register is locked and writes are ignored. * 0b1..Lock Register is not locked and writes complete as normal. */ #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) /*! @} */ /*! @name IER - RTC Interrupt Enable Register */ /*! @{ */ #define RTC_IER_TIIE_MASK (0x1U) #define RTC_IER_TIIE_SHIFT (0U) /*! TIIE - Time Invalid Interrupt Enable * 0b0..Time invalid flag does not generate an interrupt. * 0b1..Time invalid flag does generate an interrupt. */ #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) #define RTC_IER_TOIE_MASK (0x2U) #define RTC_IER_TOIE_SHIFT (1U) /*! TOIE - Time Overflow Interrupt Enable * 0b0..Time overflow flag does not generate an interrupt. * 0b1..Time overflow flag does generate an interrupt. */ #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) #define RTC_IER_TAIE_MASK (0x4U) #define RTC_IER_TAIE_SHIFT (2U) /*! TAIE - Time Alarm Interrupt Enable * 0b0..Time alarm flag does not generate an interrupt. * 0b1..Time alarm flag does generate an interrupt. */ #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) #define RTC_IER_TSIE_MASK (0x10U) #define RTC_IER_TSIE_SHIFT (4U) /*! TSIE - Time Seconds Interrupt Enable * 0b0..Seconds interrupt is disabled. * 0b1..Seconds interrupt is enabled. */ #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) #define RTC_IER_WPON_MASK (0x80U) #define RTC_IER_WPON_SHIFT (7U) /*! WPON - Wakeup Pin On * 0b0..No effect. * 0b1..If the wakeup pin is enabled, then the wakeup pin will assert. */ #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) #define RTC_IER_TSIC_MASK (0x70000U) #define RTC_IER_TSIC_SHIFT (16U) /*! TSIC - Timer Seconds Interrupt Configuration * 0b000..1 Hz. * 0b001..2 Hz. * 0b010..4 Hz. * 0b011..8 Hz. * 0b100..16 Hz. * 0b101..32 Hz. * 0b110..64 Hz. * 0b111..128 Hz. */ #define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK) /*! @} */ /*! @name WAR - RTC Write Access Register */ /*! @{ */ #define RTC_WAR_TSRW_MASK (0x1U) #define RTC_WAR_TSRW_SHIFT (0U) /*! TSRW - Time Seconds Register Write * 0b0..Writes to the Time Seconds Register are ignored. * 0b1..Writes to the Time Seconds Register complete as normal. */ #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) #define RTC_WAR_TPRW_MASK (0x2U) #define RTC_WAR_TPRW_SHIFT (1U) /*! TPRW - Time Prescaler Register Write * 0b0..Writes to the Time Prescaler Register are ignored. * 0b1..Writes to the Time Prescaler Register complete as normal. */ #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) #define RTC_WAR_TARW_MASK (0x4U) #define RTC_WAR_TARW_SHIFT (2U) /*! TARW - Time Alarm Register Write * 0b0..Writes to the Time Alarm Register are ignored. * 0b1..Writes to the Time Alarm Register complete as normal. */ #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) #define RTC_WAR_TCRW_MASK (0x8U) #define RTC_WAR_TCRW_SHIFT (3U) /*! TCRW - Time Compensation Register Write * 0b0..Writes to the Time Compensation Register are ignored. * 0b1..Writes to the Time Compensation Register complete as normal. */ #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) #define RTC_WAR_CRW_MASK (0x10U) #define RTC_WAR_CRW_SHIFT (4U) /*! CRW - Control Register Write * 0b0..Writes to the Control Register are ignored. * 0b1..Writes to the Control Register complete as normal. */ #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) #define RTC_WAR_SRW_MASK (0x20U) #define RTC_WAR_SRW_SHIFT (5U) /*! SRW - Status Register Write * 0b0..Writes to the Status Register are ignored. * 0b1..Writes to the Status Register complete as normal. */ #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) #define RTC_WAR_LRW_MASK (0x40U) #define RTC_WAR_LRW_SHIFT (6U) /*! LRW - Lock Register Write * 0b0..Writes to the Lock Register are ignored. * 0b1..Writes to the Lock Register complete as normal. */ #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) #define RTC_WAR_IERW_MASK (0x80U) #define RTC_WAR_IERW_SHIFT (7U) /*! IERW - Interrupt Enable Register Write * 0b0..Writes to the Interupt Enable Register are ignored. * 0b1..Writes to the Interrupt Enable Register complete as normal. */ #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) /*! @} */ /*! @name RAR - RTC Read Access Register */ /*! @{ */ #define RTC_RAR_TSRR_MASK (0x1U) #define RTC_RAR_TSRR_SHIFT (0U) /*! TSRR - Time Seconds Register Read * 0b0..Reads to the Time Seconds Register are ignored. * 0b1..Reads to the Time Seconds Register complete as normal. */ #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) #define RTC_RAR_TPRR_MASK (0x2U) #define RTC_RAR_TPRR_SHIFT (1U) /*! TPRR - Time Prescaler Register Read * 0b0..Reads to the Time Pprescaler Register are ignored. * 0b1..Reads to the Time Prescaler Register complete as normal. */ #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) #define RTC_RAR_TARR_MASK (0x4U) #define RTC_RAR_TARR_SHIFT (2U) /*! TARR - Time Alarm Register Read * 0b0..Reads to the Time Alarm Register are ignored. * 0b1..Reads to the Time Alarm Register complete as normal. */ #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) #define RTC_RAR_TCRR_MASK (0x8U) #define RTC_RAR_TCRR_SHIFT (3U) /*! TCRR - Time Compensation Register Read * 0b0..Reads to the Time Compensation Register are ignored. * 0b1..Reads to the Time Compensation Register complete as normal. */ #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) #define RTC_RAR_CRR_MASK (0x10U) #define RTC_RAR_CRR_SHIFT (4U) /*! CRR - Control Register Read * 0b0..Reads to the Control Register are ignored. * 0b1..Reads to the Control Register complete as normal. */ #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) #define RTC_RAR_SRR_MASK (0x20U) #define RTC_RAR_SRR_SHIFT (5U) /*! SRR - Status Register Read * 0b0..Reads to the Status Register are ignored. * 0b1..Reads to the Status Register complete as normal. */ #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) #define RTC_RAR_LRR_MASK (0x40U) #define RTC_RAR_LRR_SHIFT (6U) /*! LRR - Lock Register Read * 0b0..Reads to the Lock Register are ignored. * 0b1..Reads to the Lock Register complete as normal. */ #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) #define RTC_RAR_IERR_MASK (0x80U) #define RTC_RAR_IERR_SHIFT (7U) /*! IERR - Interrupt Enable Register Read * 0b0..Reads to the Interrupt Enable Register are ignored. * 0b1..Reads to the Interrupt Enable Register complete as normal. */ #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) /*! @} */ /*! * @} */ /* end of group RTC_Register_Masks */ /* RTC - Peripheral instance base addresses */ /** Peripheral RTC base address */ #define RTC_BASE (0x4003D000u) /** Peripheral RTC base pointer */ #define RTC ((RTC_Type *)RTC_BASE) /** Array initializer of RTC peripheral base addresses */ #define RTC_BASE_ADDRS { RTC_BASE } /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC } /** Interrupt vectors for the RTC peripheral type */ #define RTC_IRQS { RTC_IRQn } #define RTC_SECONDS_IRQS { RTC_IRQn } /*! * @} */ /* end of group RTC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer * @{ */ /** SCG - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ uint8_t RESERVED_1[4]; __IO uint32_t CLKOUTCNFG; /**< SCG CLKOUT Configuration Register, offset: 0x20 */ uint8_t RESERVED_2[220]; __IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: 0x100 */ __IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */ __IO uint32_t SOSCCFG; /**< System Oscillator Configuration Register, offset: 0x108 */ uint8_t RESERVED_3[244]; __IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x200 */ __IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */ __IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x208 */ uint8_t RESERVED_4[244]; __IO uint32_t FIRCCSR; /**< Fast IRC Control Status Register, offset: 0x300 */ __IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */ __IO uint32_t FIRCCFG; /**< Fast IRC Configuration Register, offset: 0x308 */ __IO uint32_t FIRCTCFG; /**< Fast IRC Trim Configuration Register, offset: 0x30C */ uint8_t RESERVED_5[8]; __IO uint32_t FIRCSTAT; /**< Fast IRC Status Register, offset: 0x318 */ uint8_t RESERVED_6[484]; __IO uint32_t LPFLLCSR; /**< Low Power FLL Control Status Register, offset: 0x500 */ __IO uint32_t LPFLLDIV; /**< Low Power FLL Divide Register, offset: 0x504 */ __IO uint32_t LPFLLCFG; /**< Low Power FLL Configuration Register, offset: 0x508 */ __IO uint32_t LPFLLTCFG; /**< Low Power FLL Trim Configuration Register, offset: 0x50C */ uint8_t RESERVED_7[4]; __IO uint32_t LPFLLSTAT; /**< Low Power FLL Status Register, offset: 0x514 */ } SCG_Type; /* ---------------------------------------------------------------------------- -- SCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SCG_Register_Masks SCG Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) #define SCG_VERID_VERSION_SHIFT (0U) /*! VERSION - SCG Version Number */ #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define SCG_PARAM_CLKPRES_MASK (0xFFU) #define SCG_PARAM_CLKPRES_SHIFT (0U) /*! CLKPRES - Clock Present */ #define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK) #define SCG_PARAM_DIVPRES_MASK (0xF8000000U) #define SCG_PARAM_DIVPRES_SHIFT (27U) /*! DIVPRES - Divider Present */ #define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK) /*! @} */ /*! @name CSR - Clock Status Register */ /*! @{ */ #define SCG_CSR_DIVSLOW_MASK (0xFU) #define SCG_CSR_DIVSLOW_SHIFT (0U) /*! DIVSLOW - Slow Clock Divide Ratio * 0b0000..Reserved * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Reserved * 0b1001..Reserved * 0b1010..Reserved * 0b1011..Reserved * 0b1100..Reserved * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK) #define SCG_CSR_DIVCORE_MASK (0xF0000U) #define SCG_CSR_DIVCORE_SHIFT (16U) /*! DIVCORE - Core Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK) #define SCG_CSR_SCS_MASK (0xF000000U) #define SCG_CSR_SCS_SHIFT (24U) /*! SCS - System Clock Source * 0b0000..Reserved * 0b0001..System OSC (SOSC_CLK) * 0b0010..Slow IRC (SIRC_CLK) * 0b0011..Fast IRC (FIRC_CLK) * 0b0100..Reserved * 0b0101..Low Power FLL (LPFLL_CLK) * 0b0110..Reserved * 0b0111..Reserved */ #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) /*! @} */ /*! @name RCCR - Run Clock Control Register */ /*! @{ */ #define SCG_RCCR_DIVSLOW_MASK (0xFU) #define SCG_RCCR_DIVSLOW_SHIFT (0U) /*! DIVSLOW - Slow Clock Divide Ratio * 0b0000..Reserved * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Reserved * 0b1001..Reserved * 0b1010..Reserved * 0b1011..Reserved * 0b1100..Reserved * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK) #define SCG_RCCR_DIVCORE_MASK (0xF0000U) #define SCG_RCCR_DIVCORE_SHIFT (16U) /*! DIVCORE - Core Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK) #define SCG_RCCR_SCS_MASK (0xF000000U) #define SCG_RCCR_SCS_SHIFT (24U) /*! SCS - System Clock Source * 0b0000..Reserved * 0b0001..System OSC (SOSC_CLK) * 0b0010..Slow IRC (SIRC_CLK) * 0b0011..Fast IRC (FIRC_CLK) * 0b0100..Reserved * 0b0101..Low Power FLL (LPFLL_CLK) * 0b0110..Reserved * 0b0111..Reserved */ #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) /*! @} */ /*! @name VCCR - VLPR Clock Control Register */ /*! @{ */ #define SCG_VCCR_DIVSLOW_MASK (0xFU) #define SCG_VCCR_DIVSLOW_SHIFT (0U) /*! DIVSLOW - Slow Clock Divide Ratio * 0b0000..Reserved * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Reserved * 0b1001..Reserved * 0b1010..Reserved * 0b1011..Reserved * 0b1100..Reserved * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK) #define SCG_VCCR_DIVCORE_MASK (0xF0000U) #define SCG_VCCR_DIVCORE_SHIFT (16U) /*! DIVCORE - Core Clock Divide Ratio * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b0010..Divide-by-3 * 0b0011..Divide-by-4 * 0b0100..Divide-by-5 * 0b0101..Divide-by-6 * 0b0110..Divide-by-7 * 0b0111..Divide-by-8 * 0b1000..Divide-by-9 * 0b1001..Divide-by-10 * 0b1010..Divide-by-11 * 0b1011..Divide-by-12 * 0b1100..Divide-by-13 * 0b1101..Divide-by-14 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK) #define SCG_VCCR_SCS_MASK (0xF000000U) #define SCG_VCCR_SCS_SHIFT (24U) /*! SCS - System Clock Source * 0b0000..Reserved * 0b0001..System OSC (SOSC_CLK) * 0b0010..Slow IRC (SIRC_CLK) * 0b0011..Reserved * 0b0100..Reserved * 0b0101..Reserved * 0b0110..Reserved * 0b0111..Reserved */ #define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK) /*! @} */ /*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */ /*! @{ */ #define SCG_CLKOUTCNFG_CLKOUTSEL_MASK (0xF000000U) #define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT (24U) /*! CLKOUTSEL - SCG Clkout Select * 0b0000..SCG SLOW Clock * 0b0001..System OSC (SOSC_CLK) * 0b0010..Slow IRC (SIRC_CLK) * 0b0011..Fast IRC (FIRC_CLK) * 0b0100..Reserved * 0b0101..Low Power FLL (LPFLL_CLK) * 0b0110..Reserved * 0b0111..Reserved * 0b1111..Reserved */ #define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK) /*! @} */ /*! @name SOSCCSR - System OSC Control Status Register */ /*! @{ */ #define SCG_SOSCCSR_SOSCEN_MASK (0x1U) #define SCG_SOSCCSR_SOSCEN_SHIFT (0U) /*! SOSCEN - System OSC Enable * 0b0..System OSC is disabled * 0b1..System OSC is enabled */ #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) #define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) #define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) /*! SOSCSTEN - System OSC Stop Enable * 0b0..System OSC is disabled in Stop modes * 0b1..System OSC is enabled in Stop modes if SOSCEN=1. */ #define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) #define SCG_SOSCCSR_SOSCLPEN_MASK (0x4U) #define SCG_SOSCCSR_SOSCLPEN_SHIFT (2U) /*! SOSCLPEN - System OSC Low Power Enable * 0b0..System OSC is disabled in VLP modes * 0b1..System OSC is enabled in VLP modes */ #define SCG_SOSCCSR_SOSCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCLPEN_SHIFT)) & SCG_SOSCCSR_SOSCLPEN_MASK) #define SCG_SOSCCSR_SOSCERCLKEN_MASK (0x8U) #define SCG_SOSCCSR_SOSCERCLKEN_SHIFT (3U) /*! SOSCERCLKEN - System OSC 3V ERCLK Enable * 0b0..System OSC 3V ERCLK output clock is disabled. * 0b1..System OSC 3V ERCLK output clock is enabled when SYSOSC is enabled. */ #define SCG_SOSCCSR_SOSCERCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERCLKEN_SHIFT)) & SCG_SOSCCSR_SOSCERCLKEN_MASK) #define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) #define SCG_SOSCCSR_SOSCCM_SHIFT (16U) /*! SOSCCM - System OSC Clock Monitor * 0b0..System OSC Clock Monitor is disabled * 0b1..System OSC Clock Monitor is enabled */ #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) #define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) #define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) /*! SOSCCMRE - System OSC Clock Monitor Reset Enable * 0b0..Clock Monitor generates interrupt when error detected * 0b1..Clock Monitor generates reset when error detected */ #define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) #define SCG_SOSCCSR_LK_MASK (0x800000U) #define SCG_SOSCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..This Control Status Register can be written. * 0b1..This Control Status Register cannot be written. */ #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) #define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) #define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) /*! SOSCVLD - System OSC Valid * 0b0..System OSC is not enabled or clock is not valid * 0b1..System OSC is enabled and output clock is valid */ #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) #define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) #define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) /*! SOSCSEL - System OSC Selected * 0b0..System OSC is not the system clock source * 0b1..System OSC is the system clock source */ #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) #define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) #define SCG_SOSCCSR_SOSCERR_SHIFT (26U) /*! SOSCERR - System OSC Clock Error * 0b0..System OSC Clock Monitor is disabled or has not detected an error * 0b1..System OSC Clock Monitor is enabled and detected an error */ #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) /*! @} */ /*! @name SOSCDIV - System OSC Divide Register */ /*! @{ */ #define SCG_SOSCDIV_SOSCDIV2_MASK (0x700U) #define SCG_SOSCDIV_SOSCDIV2_SHIFT (8U) /*! SOSCDIV2 - System OSC Clock Divide 2 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK) /*! @} */ /*! @name SOSCCFG - System Oscillator Configuration Register */ /*! @{ */ #define SCG_SOSCCFG_EREFS_MASK (0x4U) #define SCG_SOSCCFG_EREFS_SHIFT (2U) /*! EREFS - External Reference Select * 0b0..External reference clock selected * 0b1..Internal crystal oscillator of OSC selected. */ #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) #define SCG_SOSCCFG_HGO_MASK (0x8U) #define SCG_SOSCCFG_HGO_SHIFT (3U) /*! HGO - High Gain Oscillator Select * 0b0..Configure crystal oscillator for low-gain operation * 0b1..Configure crystal oscillator for high-gain operation */ #define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_HGO_SHIFT)) & SCG_SOSCCFG_HGO_MASK) #define SCG_SOSCCFG_RANGE_MASK (0x30U) #define SCG_SOSCCFG_RANGE_SHIFT (4U) /*! RANGE - System OSC Range Select * 0b00..Reserved * 0b01..Low frequency range selected for the crystal oscillator * 0b10..Medium frequency range selected for the crytstal oscillator * 0b11..High frequency range selected for the crystal oscillator */ #define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) /*! @} */ /*! @name SIRCCSR - Slow IRC Control Status Register */ /*! @{ */ #define SCG_SIRCCSR_SIRCEN_MASK (0x1U) #define SCG_SIRCCSR_SIRCEN_SHIFT (0U) /*! SIRCEN - Slow IRC Enable * 0b0..Slow IRC is disabled * 0b1..Slow IRC is enabled */ #define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK) #define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) #define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) /*! SIRCSTEN - Slow IRC Stop Enable * 0b0..Slow IRC is disabled in supported Stop modes * 0b1..Slow IRC is enabled in supported Stop modes */ #define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) #define SCG_SIRCCSR_SIRCLPEN_MASK (0x4U) #define SCG_SIRCCSR_SIRCLPEN_SHIFT (2U) /*! SIRCLPEN - Slow IRC Low Power Enable * 0b0..Slow IRC is disabled in VLP modes * 0b1..Slow IRC is enabled in VLP modes */ #define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK) #define SCG_SIRCCSR_LK_MASK (0x800000U) #define SCG_SIRCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written. * 0b1..Control Status Register cannot be written. */ #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) #define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) #define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) /*! SIRCVLD - Slow IRC Valid * 0b0..Slow IRC is not enabled or clock is not valid * 0b1..Slow IRC is enabled and output clock is valid */ #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) #define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) #define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) /*! SIRCSEL - Slow IRC Selected * 0b0..Slow IRC is not the system clock source * 0b1..Slow IRC is the system clock source */ #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) /*! @} */ /*! @name SIRCDIV - Slow IRC Divide Register */ /*! @{ */ #define SCG_SIRCDIV_SIRCDIV2_MASK (0x700U) #define SCG_SIRCDIV_SIRCDIV2_SHIFT (8U) /*! SIRCDIV2 - Slow IRC Clock Divide 2 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK) /*! @} */ /*! @name SIRCCFG - Slow IRC Configuration Register */ /*! @{ */ #define SCG_SIRCCFG_RANGE_MASK (0x1U) #define SCG_SIRCCFG_RANGE_SHIFT (0U) /*! RANGE - Frequency Range * 0b0..Slow IRC low range clock (2 MHz) * 0b1..Slow IRC high range clock (8 MHz ) */ #define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK) /*! @} */ /*! @name FIRCCSR - Fast IRC Control Status Register */ /*! @{ */ #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) #define SCG_FIRCCSR_FIRCEN_SHIFT (0U) /*! FIRCEN - Fast IRC Enable * 0b0..Fast IRC is disabled * 0b1..Fast IRC is enabled */ #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) #define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) #define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) /*! FIRCSTEN - Fast IRC Stop Enable * 0b0..Fast IRC is disabled in Stop modes. * 0b1..Fast IRC is enabled in Stop modes */ #define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) #define SCG_FIRCCSR_FIRCLPEN_MASK (0x4U) #define SCG_FIRCCSR_FIRCLPEN_SHIFT (2U) /*! FIRCLPEN - Fast IRC Low Power Enable * 0b0..Fast IRC is disabled in VLP modes * 0b1..Fast IRC is enabled in VLP modes */ #define SCG_FIRCCSR_FIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCLPEN_SHIFT)) & SCG_FIRCCSR_FIRCLPEN_MASK) #define SCG_FIRCCSR_FIRCREGOFF_MASK (0x8U) #define SCG_FIRCCSR_FIRCREGOFF_SHIFT (3U) /*! FIRCREGOFF - Fast IRC Regulator Enable * 0b0..Fast IRC Regulator is enabled. * 0b1..Fast IRC Regulator is disabled. */ #define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCREGOFF_SHIFT)) & SCG_FIRCCSR_FIRCREGOFF_MASK) #define SCG_FIRCCSR_FIRCTREN_MASK (0x100U) #define SCG_FIRCCSR_FIRCTREN_SHIFT (8U) /*! FIRCTREN - Fast IRC Trim Enable * 0b0..Disable trimming Fast IRC to an external clock source * 0b1..Enable trimming Fast IRC to an external clock source */ #define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK) #define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U) #define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U) /*! FIRCTRUP - Fast IRC Trim Update * 0b0..Disable Fast IRC trimming updates * 0b1..Enable Fast IRC trimming updates */ #define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK) #define SCG_FIRCCSR_LK_MASK (0x800000U) #define SCG_FIRCCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written. * 0b1..Control Status Register cannot be written. */ #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) #define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) #define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) /*! FIRCVLD - Fast IRC Valid status * 0b0..Fast IRC is not enabled or clock is not valid. * 0b1..Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog. */ #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) #define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) /*! FIRCSEL - Fast IRC Selected status * 0b0..Fast IRC is not the system clock source * 0b1..Fast IRC is the system clock source */ #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) #define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) #define SCG_FIRCCSR_FIRCERR_SHIFT (26U) /*! FIRCERR - Fast IRC Clock Error * 0b0..Error not detected with the Fast IRC trimming. * 0b1..Error detected with the Fast IRC trimming. */ #define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) /*! @} */ /*! @name FIRCDIV - Fast IRC Divide Register */ /*! @{ */ #define SCG_FIRCDIV_FIRCDIV2_MASK (0x700U) #define SCG_FIRCDIV_FIRCDIV2_SHIFT (8U) /*! FIRCDIV2 - Fast IRC Clock Divide 2 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK) /*! @} */ /*! @name FIRCCFG - Fast IRC Configuration Register */ /*! @{ */ #define SCG_FIRCCFG_RANGE_MASK (0x3U) #define SCG_FIRCCFG_RANGE_SHIFT (0U) /*! RANGE - Frequency Range * 0b00..Fast IRC is trimmed to 48 MHz * 0b01..Fast IRC is trimmed to 52 MHz * 0b10..Fast IRC is trimmed to 56 MHz * 0b11..Fast IRC is trimmed to 60 MHz */ #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) /*! @} */ /*! @name FIRCTCFG - Fast IRC Trim Configuration Register */ /*! @{ */ #define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U) #define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U) /*! TRIMSRC - Trim Source * 0b00..Reserved * 0b01..Reserved * 0b10..System OSC * 0b11..Reserved */ #define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK) #define SCG_FIRCTCFG_TRIMDIV_MASK (0x700U) #define SCG_FIRCTCFG_TRIMDIV_SHIFT (8U) /*! TRIMDIV - Fast IRC Trim Predivide * 0b000..Divide by 1 * 0b001..Divide by 128 * 0b010..Divide by 256 * 0b011..Divide by 512 * 0b100..Divide by 1024 * 0b101..Divide by 2048 * 0b110..Reserved. Writing this value will result in Divide by 1. * 0b111..Reserved. Writing this value will result in a Divide by 1. */ #define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK) /*! @} */ /*! @name FIRCSTAT - Fast IRC Status Register */ /*! @{ */ #define SCG_FIRCSTAT_TRIMFINE_MASK (0x7FU) #define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U) /*! TRIMFINE - Trim Fine Status */ #define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK) #define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U) #define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U) /*! TRIMCOAR - Trim Coarse */ #define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK) /*! @} */ /*! @name LPFLLCSR - Low Power FLL Control Status Register */ /*! @{ */ #define SCG_LPFLLCSR_LPFLLEN_MASK (0x1U) #define SCG_LPFLLCSR_LPFLLEN_SHIFT (0U) /*! LPFLLEN - LPFLL Enable * 0b0..LPFLL is disabled * 0b1..LPFLL is enabled */ #define SCG_LPFLLCSR_LPFLLEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLEN_SHIFT)) & SCG_LPFLLCSR_LPFLLEN_MASK) #define SCG_LPFLLCSR_LPFLLTREN_MASK (0x100U) #define SCG_LPFLLCSR_LPFLLTREN_SHIFT (8U) /*! LPFLLTREN - LPFLL Trim Enable * 0b0..Disable trimming LPFLL to an reference clock source * 0b1..Enable trimming LPFLL to an reference clock source */ #define SCG_LPFLLCSR_LPFLLTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTREN_SHIFT)) & SCG_LPFLLCSR_LPFLLTREN_MASK) #define SCG_LPFLLCSR_LPFLLTRUP_MASK (0x200U) #define SCG_LPFLLCSR_LPFLLTRUP_SHIFT (9U) /*! LPFLLTRUP - LPFLL Trim Update * 0b0..Disable LPFLL trimming updates. LPFLL frequency determined by AUTOTRIM written value. * 0b1..Enable LPFLL trimming updates. LPFLL frequency determined by reference clock multiplication */ #define SCG_LPFLLCSR_LPFLLTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRUP_SHIFT)) & SCG_LPFLLCSR_LPFLLTRUP_MASK) #define SCG_LPFLLCSR_LPFLLTRMLOCK_MASK (0x400U) #define SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT (10U) /*! LPFLLTRMLOCK - LPFLL Trim LOCK * 0b0..LPFLL not Locked * 0b1..LPFLL trimmed and Locked */ #define SCG_LPFLLCSR_LPFLLTRMLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT)) & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK) #define SCG_LPFLLCSR_LPFLLCM_MASK (0x10000U) #define SCG_LPFLLCSR_LPFLLCM_SHIFT (16U) /*! LPFLLCM - LPFLL Clock Monitor * 0b0..LPFLL Clock Monitor is disabled * 0b1..LPFLL Clock Monitor is enabled */ #define SCG_LPFLLCSR_LPFLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCM_SHIFT)) & SCG_LPFLLCSR_LPFLLCM_MASK) #define SCG_LPFLLCSR_LPFLLCMRE_MASK (0x20000U) #define SCG_LPFLLCSR_LPFLLCMRE_SHIFT (17U) /*! LPFLLCMRE - LPFLL Clock Monitor Reset Enable * 0b0..Clock Monitor generates interrupt when error detected * 0b1..Clock Monitor generates reset when error detected */ #define SCG_LPFLLCSR_LPFLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCMRE_SHIFT)) & SCG_LPFLLCSR_LPFLLCMRE_MASK) #define SCG_LPFLLCSR_LK_MASK (0x800000U) #define SCG_LPFLLCSR_LK_SHIFT (23U) /*! LK - Lock Register * 0b0..Control Status Register can be written. * 0b1..Control Status Register cannot be written. */ #define SCG_LPFLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LK_SHIFT)) & SCG_LPFLLCSR_LK_MASK) #define SCG_LPFLLCSR_LPFLLVLD_MASK (0x1000000U) #define SCG_LPFLLCSR_LPFLLVLD_SHIFT (24U) /*! LPFLLVLD - LPFLL Valid * 0b0..LPFLL is not enabled or clock is not valid. * 0b1..LPFLL is enabled and output clock is valid. */ #define SCG_LPFLLCSR_LPFLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLVLD_SHIFT)) & SCG_LPFLLCSR_LPFLLVLD_MASK) #define SCG_LPFLLCSR_LPFLLSEL_MASK (0x2000000U) #define SCG_LPFLLCSR_LPFLLSEL_SHIFT (25U) /*! LPFLLSEL - LPFLL Selected * 0b0..LPFLL is not the system clock source * 0b1..LPFLL is the system clock source */ #define SCG_LPFLLCSR_LPFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSEL_SHIFT)) & SCG_LPFLLCSR_LPFLLSEL_MASK) #define SCG_LPFLLCSR_LPFLLERR_MASK (0x4000000U) #define SCG_LPFLLCSR_LPFLLERR_SHIFT (26U) /*! LPFLLERR - LPFLL Clock Error * 0b0..Error not detected with the LPFLL trimming. * 0b1..Error detected with the LPFLL trimming. */ #define SCG_LPFLLCSR_LPFLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLERR_SHIFT)) & SCG_LPFLLCSR_LPFLLERR_MASK) /*! @} */ /*! @name LPFLLDIV - Low Power FLL Divide Register */ /*! @{ */ #define SCG_LPFLLDIV_LPFLLDIV2_MASK (0x700U) #define SCG_LPFLLDIV_LPFLLDIV2_SHIFT (8U) /*! LPFLLDIV2 - LPFLL Clock Divide 2 * 0b000..Output disabled * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 4 * 0b100..Divide by 8 * 0b101..Divide by 16 * 0b110..Divide by 32 * 0b111..Divide by 64 */ #define SCG_LPFLLDIV_LPFLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV2_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV2_MASK) /*! @} */ /*! @name LPFLLCFG - Low Power FLL Configuration Register */ /*! @{ */ #define SCG_LPFLLCFG_FSEL_MASK (0x3U) #define SCG_LPFLLCFG_FSEL_SHIFT (0U) /*! FSEL - Frequency Select * 0b00..LPFLL is trimmed to 48 MHz * 0b01..LPFLL is trimmed to 72 MHz * 0b10..Reserved * 0b11..Reserved */ #define SCG_LPFLLCFG_FSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCFG_FSEL_SHIFT)) & SCG_LPFLLCFG_FSEL_MASK) /*! @} */ /*! @name LPFLLTCFG - Low Power FLL Trim Configuration Register */ /*! @{ */ #define SCG_LPFLLTCFG_TRIMSRC_MASK (0x3U) #define SCG_LPFLLTCFG_TRIMSRC_SHIFT (0U) /*! TRIMSRC - Trim Source * 0b00..SIRC * 0b01..FIRC * 0b10..System OSC * 0b11..RTC OSC */ #define SCG_LPFLLTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMSRC_SHIFT)) & SCG_LPFLLTCFG_TRIMSRC_MASK) #define SCG_LPFLLTCFG_TRIMDIV_MASK (0x1F00U) #define SCG_LPFLLTCFG_TRIMDIV_SHIFT (8U) /*! TRIMDIV - LPFLL Trim Predivide */ #define SCG_LPFLLTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMDIV_SHIFT)) & SCG_LPFLLTCFG_TRIMDIV_MASK) #define SCG_LPFLLTCFG_LOCKW2LSB_MASK (0x10000U) #define SCG_LPFLLTCFG_LOCKW2LSB_SHIFT (16U) /*! LOCKW2LSB - Lock LPFLL with 2 LSBS * 0b0..LPFLL locks within 1LSB (0.4%) * 0b1..LPFLL locks within 2LSB (0.8%) */ #define SCG_LPFLLTCFG_LOCKW2LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_LOCKW2LSB_SHIFT)) & SCG_LPFLLTCFG_LOCKW2LSB_MASK) /*! @} */ /*! @name LPFLLSTAT - Low Power FLL Status Register */ /*! @{ */ #define SCG_LPFLLSTAT_AUTOTRIM_MASK (0xFFU) #define SCG_LPFLLSTAT_AUTOTRIM_SHIFT (0U) /*! AUTOTRIM - Auto Tune Trim Status */ #define SCG_LPFLLSTAT_AUTOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLSTAT_AUTOTRIM_SHIFT)) & SCG_LPFLLSTAT_AUTOTRIM_MASK) /*! @} */ /*! * @} */ /* end of group SCG_Register_Masks */ /* SCG - Peripheral instance base addresses */ /** Peripheral SCG base address */ #define SCG_BASE (0x40064000u) /** Peripheral SCG base pointer */ #define SCG ((SCG_Type *)SCG_BASE) /** Array initializer of SCG peripheral base addresses */ #define SCG_BASE_ADDRS { SCG_BASE } /** Array initializer of SCG peripheral base pointers */ #define SCG_BASE_PTRS { SCG } /** Interrupt vectors for the SCG peripheral type */ #define SCG_IRQS { SCG_IRQn } /*! * @} */ /* end of group SCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer * @{ */ /** SIM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t CHIPCTL; /**< Chip Control register, offset: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FTMOPT0; /**< FTM Option Register 0, offset: 0xC */ uint8_t RESERVED_2[8]; __IO uint32_t ADCOPT; /**< ADC Options Register, offset: 0x18 */ __IO uint32_t FTMOPT1; /**< FTM Option Register 1, offset: 0x1C */ uint8_t RESERVED_3[4]; __I uint32_t SDID; /**< System Device Identification Register, offset: 0x24 */ uint8_t RESERVED_4[36]; __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x4C */ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x50 */ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x54 */ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x58 */ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x5C */ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x60 */ uint8_t RESERVED_5[8]; __IO uint32_t MISCTRL; /**< Miscellaneous Control register, offset: 0x6C */ } SIM_Type; /* ---------------------------------------------------------------------------- -- SIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Register_Masks SIM Register Masks * @{ */ /*! @name CHIPCTL - Chip Control register */ /*! @{ */ #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK (0x3U) #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT (0U) /*! ADC_INTERLEAVE_EN - ADC interleave channel enable * 0b00..No interleave channel */ #define SIM_CHIPCTL_ADC_INTERLEAVE_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT)) & SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK) #define SIM_CHIPCTL_CLKOUTDIV_MASK (0x30U) #define SIM_CHIPCTL_CLKOUTDIV_SHIFT (4U) /*! CLKOUTDIV - CLKOUT divider ratio * 0b00..Divided by 1 * 0b01..Divided by 2 * 0b10..Divided by 4 * 0b11..Divided by 8 */ #define SIM_CHIPCTL_CLKOUTDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_CLKOUTDIV_SHIFT)) & SIM_CHIPCTL_CLKOUTDIV_MASK) #define SIM_CHIPCTL_CLKOUTSEL_MASK (0xC0U) #define SIM_CHIPCTL_CLKOUTSEL_SHIFT (6U) /*! CLKOUTSEL - CLKOUT Select * 0b00..Reseved * 0b01..SCGCLKOUT(SIRC/FIRC/SOSC/LPFLL), see SCG_CLKOUTCNFG register. * 0b10..RTC oscillator (OSC32) clock (32 kHz) * 0b11..LPO clock (128 kHz) */ #define SIM_CHIPCTL_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_CLKOUTSEL_SHIFT)) & SIM_CHIPCTL_CLKOUTSEL_MASK) #define SIM_CHIPCTL_PDB_BB_SEL_MASK (0x2000U) #define SIM_CHIPCTL_PDB_BB_SEL_SHIFT (13U) /*! PDB_BB_SEL - PDB back-to-back select * 0b0..PDB0 channel 0 back-to-back operation with ADC0 COCO[1:0] and PDB0 channel 1 back-to-back operation with ADC1 COCO[1:0] * 0b1..PDB0 Channel 0 back-to-back operation with COCO[0] of ADC0 and COCO[1] of ADC1 ; PDB0 Channel 1 * back-to-back operation with COCO[0] of ADC1 and COCO[1] of ADC0 */ #define SIM_CHIPCTL_PDB_BB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_PDB_BB_SEL_SHIFT)) & SIM_CHIPCTL_PDB_BB_SEL_MASK) #define SIM_CHIPCTL_PWTCLKSEL_MASK (0x30000U) #define SIM_CHIPCTL_PWTCLKSEL_SHIFT (16U) /*! PWTCLKSEL - PWT clock source select * 0b00..PWT alternative clock is from the TCLK0 pin. * 0b01..PWT alternative clock is from the TCLK1 pin. * 0b10..PWT alternative clock is from the TCLK2 pin. * 0b11..Reserved */ #define SIM_CHIPCTL_PWTCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_PWTCLKSEL_SHIFT)) & SIM_CHIPCTL_PWTCLKSEL_MASK) #define SIM_CHIPCTL_RTC32KCLKSEL_MASK (0xC0000U) #define SIM_CHIPCTL_RTC32KCLKSEL_SHIFT (18U) /*! RTC32KCLKSEL - RTC 32K clock input select * 0b00..OSC32 clock output * 0b01..RTC_CLKIN * 0b10..Reserved * 0b11..Reserved */ #define SIM_CHIPCTL_RTC32KCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_RTC32KCLKSEL_SHIFT)) & SIM_CHIPCTL_RTC32KCLKSEL_MASK) /*! @} */ /*! @name FTMOPT0 - FTM Option Register 0 */ /*! @{ */ #define SIM_FTMOPT0_FTM0FLTxSEL_MASK (0x7U) #define SIM_FTMOPT0_FTM0FLTxSEL_SHIFT (0U) /*! FTM0FLTxSEL - FTM0 Fault x Select */ #define SIM_FTMOPT0_FTM0FLTxSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM0FLTxSEL_SHIFT)) & SIM_FTMOPT0_FTM0FLTxSEL_MASK) #define SIM_FTMOPT0_FTM0CLKSEL_MASK (0x3000000U) #define SIM_FTMOPT0_FTM0CLKSEL_SHIFT (24U) /*! FTM0CLKSEL - FTM0 External Clock Pin Select * 0b00..FTM0 external clock driven by TCLK0 pin. * 0b01..FTM0 external clock driven by TCLK1 pin. * 0b10..FTM0 external clock driven by TCLK2 pin. * 0b11..No clock input */ #define SIM_FTMOPT0_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM0CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM0CLKSEL_MASK) #define SIM_FTMOPT0_FTM1CLKSEL_MASK (0xC000000U) #define SIM_FTMOPT0_FTM1CLKSEL_SHIFT (26U) /*! FTM1CLKSEL - FTM1 External Clock Pin Select * 0b00..FTM1 external clock driven by TCLK0 pin. * 0b01..FTM1 external clock driven by TCLK1 pin. * 0b10..FTM1 external clock driven by TCLK2 pin. * 0b11..No clock input */ #define SIM_FTMOPT0_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM1CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM1CLKSEL_MASK) #define SIM_FTMOPT0_FTM2CLKSEL_MASK (0x30000000U) #define SIM_FTMOPT0_FTM2CLKSEL_SHIFT (28U) /*! FTM2CLKSEL - FTM2 External Clock Pin Select * 0b00..FTM2 external clock driven by TCLK0 pin. * 0b01..FTM2 external clock driven by TCLK1 pin. * 0b10..FTM2 external clock driven by TCLK2 pin. * 0b11..No clock input */ #define SIM_FTMOPT0_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM2CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM2CLKSEL_MASK) /*! @} */ /*! @name ADCOPT - ADC Options Register */ /*! @{ */ #define SIM_ADCOPT_ADC0TRGSEL_MASK (0x1U) #define SIM_ADCOPT_ADC0TRGSEL_SHIFT (0U) /*! ADC0TRGSEL - ADC0 trigger source select * 0b0..PDB output * 0b1..TRGMUX output */ #define SIM_ADCOPT_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0TRGSEL_SHIFT)) & SIM_ADCOPT_ADC0TRGSEL_MASK) #define SIM_ADCOPT_ADC0SWPRETRG_MASK (0x6U) #define SIM_ADCOPT_ADC0SWPRETRG_SHIFT (1U) /*! ADC0SWPRETRG - ADC0 software pre-trigger sources * 0b00..disabled * 0b01..software pre-trigger 0 * 0b10..software pre-trigger 1 * 0b11..disabled */ #define SIM_ADCOPT_ADC0SWPRETRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0SWPRETRG_SHIFT)) & SIM_ADCOPT_ADC0SWPRETRG_MASK) #define SIM_ADCOPT_ADC0PRETRGSEL_MASK (0x30U) #define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT (4U) /*! ADC0PRETRGSEL - ADC0 pre-trigger source select * 0b00..PDB output * 0b01..TRGMUX output * 0b10..ADC0 software pre-trigger * 0b11..Reserved */ #define SIM_ADCOPT_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT)) & SIM_ADCOPT_ADC0PRETRGSEL_MASK) #define SIM_ADCOPT_ADC1TRGSEL_MASK (0x100U) #define SIM_ADCOPT_ADC1TRGSEL_SHIFT (8U) /*! ADC1TRGSEL - ADC1 trigger source select * 0b0..PDB output * 0b1..TRGMUX output */ #define SIM_ADCOPT_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC1TRGSEL_SHIFT)) & SIM_ADCOPT_ADC1TRGSEL_MASK) #define SIM_ADCOPT_ADC1SWPRETRG_MASK (0x600U) #define SIM_ADCOPT_ADC1SWPRETRG_SHIFT (9U) /*! ADC1SWPRETRG - ADC1 software pre-trigger sources * 0b00..disabled * 0b01..software pre-trigger 0 * 0b10..software pre-trigger 1 * 0b11..disabled */ #define SIM_ADCOPT_ADC1SWPRETRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC1SWPRETRG_SHIFT)) & SIM_ADCOPT_ADC1SWPRETRG_MASK) #define SIM_ADCOPT_ADC1PRETRGSEL_MASK (0x3000U) #define SIM_ADCOPT_ADC1PRETRGSEL_SHIFT (12U) /*! ADC1PRETRGSEL - ADC1 pre-trigger source select * 0b00..PDB output * 0b01..TRGMUX output * 0b10..ADC1 software pre-trigger * 0b11..Reserved */ #define SIM_ADCOPT_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC1PRETRGSEL_SHIFT)) & SIM_ADCOPT_ADC1PRETRGSEL_MASK) /*! @} */ /*! @name FTMOPT1 - FTM Option Register 1 */ /*! @{ */ #define SIM_FTMOPT1_FTM0SYNCBIT_MASK (0x1U) #define SIM_FTMOPT1_FTM0SYNCBIT_SHIFT (0U) /*! FTM0SYNCBIT - FTM0 Sync Bit * 0b0..No effect. * 0b1..Write 1 to assert the TRIG1 input to FTM0. Software must clear this bit to allow other trigger sources to assert. */ #define SIM_FTMOPT1_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM0SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM0SYNCBIT_MASK) #define SIM_FTMOPT1_FTM1SYNCBIT_MASK (0x2U) #define SIM_FTMOPT1_FTM1SYNCBIT_SHIFT (1U) /*! FTM1SYNCBIT - FTM1 Sync Bit * 0b0..No effect. * 0b1..Write 1 to assert the TRIG1 input to FTM1. Software must clear this bit to allow other trigger sources to assert. */ #define SIM_FTMOPT1_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM1SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM1SYNCBIT_MASK) #define SIM_FTMOPT1_FTM2SYNCBIT_MASK (0x4U) #define SIM_FTMOPT1_FTM2SYNCBIT_SHIFT (2U) /*! FTM2SYNCBIT - FTM2 Sync Bit * 0b0..No effect. * 0b1..Write 1 to assert the TRIG1 input to FTM2. Software must clear this bit to allow other trigger sources to assert. */ #define SIM_FTMOPT1_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM2SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM2SYNCBIT_MASK) #define SIM_FTMOPT1_FTM1CH0SEL_MASK (0x30U) #define SIM_FTMOPT1_FTM1CH0SEL_SHIFT (4U) /*! FTM1CH0SEL - FTM1 CH0 Select * 0b00..FTM1_CH0 input * 0b01..CMP0 output * 0b10..CMP1 output * 0b11..Reserved */ #define SIM_FTMOPT1_FTM1CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM1CH0SEL_SHIFT)) & SIM_FTMOPT1_FTM1CH0SEL_MASK) #define SIM_FTMOPT1_FTM2CH0SEL_MASK (0xC0U) #define SIM_FTMOPT1_FTM2CH0SEL_SHIFT (6U) /*! FTM2CH0SEL - FTM2 CH0 Select * 0b00..FTM2_CH0 input * 0b01..CMP0 output * 0b10..CMP1 output * 0b11..Reserved */ #define SIM_FTMOPT1_FTM2CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM2CH0SEL_SHIFT)) & SIM_FTMOPT1_FTM2CH0SEL_MASK) #define SIM_FTMOPT1_FTM2CH1SEL_MASK (0x100U) #define SIM_FTMOPT1_FTM2CH1SEL_SHIFT (8U) /*! FTM2CH1SEL - FTM2 CH1 Select * 0b0..FTM2_CH1 input * 0b1..exclusive OR of FTM2_CH0, FTM2_CH1, and FTM1_CH1 */ #define SIM_FTMOPT1_FTM2CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM2CH1SEL_SHIFT)) & SIM_FTMOPT1_FTM2CH1SEL_MASK) #define SIM_FTMOPT1_FTM0_OUTSEL_MASK (0xFF0000U) #define SIM_FTMOPT1_FTM0_OUTSEL_SHIFT (16U) /*! FTM0_OUTSEL - FTM0 channel modulation select with FTM1_CH1 * 0b00000000..No modulation with FTM1_CH1 * 0b00000001..Modulation with FTM1_CH1 */ #define SIM_FTMOPT1_FTM0_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM0_OUTSEL_SHIFT)) & SIM_FTMOPT1_FTM0_OUTSEL_MASK) /*! @} */ /*! @name SDID - System Device Identification Register */ /*! @{ */ #define SIM_SDID_PINID_MASK (0x7FU) #define SIM_SDID_PINID_SHIFT (0U) /*! PINID - Pin identification * 0b0000111..64-pin * 0b0001010..100-pin */ #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) #define SIM_SDID_PROJECTID_MASK (0xF80U) #define SIM_SDID_PROJECTID_SHIFT (7U) /*! PROJECTID - Project ID */ #define SIM_SDID_PROJECTID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PROJECTID_SHIFT)) & SIM_SDID_PROJECTID_MASK) #define SIM_SDID_REVID_MASK (0xF000U) #define SIM_SDID_REVID_SHIFT (12U) /*! REVID - Device revision number */ #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) #define SIM_SDID_RAMSIZE_MASK (0xF0000U) #define SIM_SDID_RAMSIZE_SHIFT (16U) /*! RAMSIZE - RAM size * 0b0101..16 KB * 0b0110..32 KB */ #define SIM_SDID_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_RAMSIZE_SHIFT)) & SIM_SDID_RAMSIZE_MASK) #define SIM_SDID_SERIESID_MASK (0xF00000U) #define SIM_SDID_SERIESID_SHIFT (20U) /*! SERIESID - Kinetis Series ID * 0b0010..Kinetis E+ series */ #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) #define SIM_SDID_SUBFAMID_MASK (0xF000000U) #define SIM_SDID_SUBFAMID_SHIFT (24U) /*! SUBFAMID - Kinetis E-series Sub-Family ID */ #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) #define SIM_SDID_FAMILYID_MASK (0xF0000000U) #define SIM_SDID_FAMILYID_SHIFT (28U) /*! FAMILYID - Kinetis E-series Family ID * 0b0001..KE1x Family (Enhanced features) */ #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK) /*! @} */ /*! @name FCFG1 - Flash Configuration Register 1 */ /*! @{ */ #define SIM_FCFG1_FLASHDIS_MASK (0x1U) #define SIM_FCFG1_FLASHDIS_SHIFT (0U) /*! FLASHDIS - Flash Disable * 0b0..Flash is enabled * 0b1..Flash is disabled */ #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) /*! FLASHDOZE - Flash Doze * 0b0..Flash remains enabled during Doze mode * 0b1..Flash is disabled for the duration of Doze mode */ #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) #define SIM_FCFG1_DEPART_MASK (0xF000U) #define SIM_FCFG1_DEPART_SHIFT (12U) /*! DEPART - FlexNVM partition */ #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK) #define SIM_FCFG1_EEERAMSIZE_MASK (0xF0000U) #define SIM_FCFG1_EEERAMSIZE_SHIFT (16U) /*! EEERAMSIZE - EEE SRAM SIZE * 0b0011..2 KB * 0b0100..1 KB * 0b0101..512 Bytes * 0b0110..256 Bytes * 0b0111..128 Bytes * 0b1000..64 Bytes * 0b1001..32 Bytes */ #define SIM_FCFG1_EEERAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EEERAMSIZE_SHIFT)) & SIM_FCFG1_EEERAMSIZE_MASK) #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) #define SIM_FCFG1_PFSIZE_SHIFT (24U) /*! PFSIZE - Program flash size * 0b0111..128 KB of program flash memory, 4 KB protection region * 0b1001..256 KB of program flash memory, 8 KB protection region */ #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) #define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U) #define SIM_FCFG1_NVMSIZE_SHIFT (28U) /*! NVMSIZE - FlexNVM size * 0b0000..0 KB of FlexNVM * 0b0011..32 KB of FlexNVM */ #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK) /*! @} */ /*! @name FCFG2 - Flash Configuration Register 2 */ /*! @{ */ #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) #define SIM_FCFG2_MAXADDR1_SHIFT (16U) /*! MAXADDR1 - Max address block 1 */ #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) #define SIM_FCFG2_MAXADDR0_SHIFT (24U) /*! MAXADDR0 - Max address block 0 */ #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) /*! @} */ /*! @name UIDH - Unique Identification Register High */ /*! @{ */ #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) #define SIM_UIDH_UID127_96_SHIFT (0U) /*! UID127_96 - Unique Identification */ #define SIM_UIDH_UID127_96(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK) /*! @} */ /*! @name UIDMH - Unique Identification Register Mid-High */ /*! @{ */ #define SIM_UIDMH_UID95_64_MASK (0xFFFFFFFFU) #define SIM_UIDMH_UID95_64_SHIFT (0U) /*! UID95_64 - Unique Identification */ #define SIM_UIDMH_UID95_64(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID95_64_SHIFT)) & SIM_UIDMH_UID95_64_MASK) /*! @} */ /*! @name UIDML - Unique Identification Register Mid Low */ /*! @{ */ #define SIM_UIDML_UID63_32_MASK (0xFFFFFFFFU) #define SIM_UIDML_UID63_32_SHIFT (0U) /*! UID63_32 - Unique Identification */ #define SIM_UIDML_UID63_32(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID63_32_SHIFT)) & SIM_UIDML_UID63_32_MASK) /*! @} */ /*! @name UIDL - Unique Identification Register Low */ /*! @{ */ #define SIM_UIDL_UID31_0_MASK (0xFFFFFFFFU) #define SIM_UIDL_UID31_0_SHIFT (0U) /*! UID31_0 - Unique Identification */ #define SIM_UIDL_UID31_0(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID31_0_SHIFT)) & SIM_UIDL_UID31_0_MASK) /*! @} */ /*! @name MISCTRL - Miscellaneous Control register */ /*! @{ */ #define SIM_MISCTRL_SW_TRG_MASK (0x1U) #define SIM_MISCTRL_SW_TRG_SHIFT (0U) /*! SW_TRG - Software Trigger bit to TRGMUX */ #define SIM_MISCTRL_SW_TRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL_SW_TRG_SHIFT)) & SIM_MISCTRL_SW_TRG_MASK) #define SIM_MISCTRL_DMA_INT_SEL_MASK (0xF0U) #define SIM_MISCTRL_DMA_INT_SEL_SHIFT (4U) /*! DMA_INT_SEL - DMA channel interrupt OR select */ #define SIM_MISCTRL_DMA_INT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL_DMA_INT_SEL_SHIFT)) & SIM_MISCTRL_DMA_INT_SEL_MASK) #define SIM_MISCTRL_UART0ODE_MASK (0x10000U) #define SIM_MISCTRL_UART0ODE_SHIFT (16U) /*! UART0ODE - UART0 Open Drain Enable * 0b0..Open drain is disabled on UART0 * 0b1..Open drain is enabled on UART0 */ #define SIM_MISCTRL_UART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL_UART0ODE_SHIFT)) & SIM_MISCTRL_UART0ODE_MASK) #define SIM_MISCTRL_UART1ODE_MASK (0x20000U) #define SIM_MISCTRL_UART1ODE_SHIFT (17U) /*! UART1ODE - UART1 Open Drain Enable * 0b0..Open drain is disabled on UART1 * 0b1..Open drain is enabled on UART1 */ #define SIM_MISCTRL_UART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL_UART1ODE_SHIFT)) & SIM_MISCTRL_UART1ODE_MASK) #define SIM_MISCTRL_UART2ODE_MASK (0x40000U) #define SIM_MISCTRL_UART2ODE_SHIFT (18U) /*! UART2ODE - UART2 Open Drain Enable * 0b0..Open drain is disabled on UART2 * 0b1..Open drain is enabled on UART2 */ #define SIM_MISCTRL_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL_UART2ODE_SHIFT)) & SIM_MISCTRL_UART2ODE_MASK) /*! @} */ /*! * @} */ /* end of group SIM_Register_Masks */ /* SIM - Peripheral instance base addresses */ /** Peripheral SIM base address */ #define SIM_BASE (0x40048000u) /** Peripheral SIM base pointer */ #define SIM ((SIM_Type *)SIM_BASE) /** Array initializer of SIM peripheral base addresses */ #define SIM_BASE_ADDRS { SIM_BASE } /** Array initializer of SIM peripheral base pointers */ #define SIM_BASE_PTRS { SIM } /*! * @} */ /* end of group SIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer * @{ */ /** SMC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< SMC Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< SMC Parameter Register, offset: 0x4 */ __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */ __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */ __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */ __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */ } SMC_Type; /* ---------------------------------------------------------------------------- -- SMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Register_Masks SMC Register Masks * @{ */ /*! @name VERID - SMC Version ID Register */ /*! @{ */ #define SMC_VERID_FEATURE_MASK (0xFFFFU) #define SMC_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard features implemented */ #define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK) #define SMC_VERID_MINOR_MASK (0xFF0000U) #define SMC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK) #define SMC_VERID_MAJOR_MASK (0xFF000000U) #define SMC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - SMC Parameter Register */ /*! @{ */ #define SMC_PARAM_EHSRUN_MASK (0x1U) #define SMC_PARAM_EHSRUN_SHIFT (0U) /*! EHSRUN - Existence of HSRUN feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EHSRUN_SHIFT)) & SMC_PARAM_EHSRUN_MASK) #define SMC_PARAM_ELLS_MASK (0x8U) #define SMC_PARAM_ELLS_SHIFT (3U) /*! ELLS - Existence of LLS feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS_SHIFT)) & SMC_PARAM_ELLS_MASK) #define SMC_PARAM_ELLS2_MASK (0x20U) #define SMC_PARAM_ELLS2_SHIFT (5U) /*! ELLS2 - Existence of LLS2 feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS2_SHIFT)) & SMC_PARAM_ELLS2_MASK) #define SMC_PARAM_EVLLS0_MASK (0x40U) #define SMC_PARAM_EVLLS0_SHIFT (6U) /*! EVLLS0 - Existence of VLLS0 feature * 0b0..The feature is not available. * 0b1..The feature is available. */ #define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EVLLS0_SHIFT)) & SMC_PARAM_EVLLS0_MASK) /*! @} */ /*! @name PMPROT - Power Mode Protection register */ /*! @{ */ #define SMC_PMPROT_AVLP_MASK (0x20U) #define SMC_PMPROT_AVLP_SHIFT (5U) /*! AVLP - Allow Very-Low-Power Modes * 0b0..VLPR, VLPW, and VLPS are not allowed. * 0b1..VLPR, VLPW, and VLPS are allowed. */ #define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) /*! @} */ /*! @name PMCTRL - Power Mode Control register */ /*! @{ */ #define SMC_PMCTRL_STOPM_MASK (0x7U) #define SMC_PMCTRL_STOPM_SHIFT (0U) /*! STOPM - Stop Mode Control * 0b000..Normal Stop (STOP) * 0b001..Reserved * 0b010..Very-Low-Power Stop (VLPS) * 0b011..Reserved * 0b101..Reserved * 0b110..Reseved * 0b111..Reserved */ #define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) #define SMC_PMCTRL_STOPA_MASK (0x8U) #define SMC_PMCTRL_STOPA_SHIFT (3U) /*! STOPA - Stop Aborted * 0b0..The previous stop mode entry was successful. * 0b1..The previous stop mode entry was aborted. */ #define SMC_PMCTRL_STOPA(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) #define SMC_PMCTRL_RUNM_MASK (0x60U) #define SMC_PMCTRL_RUNM_SHIFT (5U) /*! RUNM - Run Mode Control * 0b00..Normal Run mode (RUN) * 0b01..Reserved * 0b10..Very-Low-Power Run mode (VLPR) * 0b11..Reserved */ #define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) /*! @} */ /*! @name STOPCTRL - Stop Control Register */ /*! @{ */ #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) #define SMC_STOPCTRL_PSTOPO_SHIFT (6U) /*! PSTOPO - Partial Stop Option * 0b00..STOP - Normal Stop mode * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled * 0b11..Reserved */ #define SMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) /*! @} */ /*! @name PMSTAT - Power Mode Status register */ /*! @{ */ #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) #define SMC_PMSTAT_PMSTAT_SHIFT (0U) /*! PMSTAT - Power Mode Status */ #define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) /*! @} */ /*! * @} */ /* end of group SMC_Register_Masks */ /* SMC - Peripheral instance base addresses */ /** Peripheral SMC base address */ #define SMC_BASE (0x4007E000u) /** Peripheral SMC base pointer */ #define SMC ((SMC_Type *)SMC_BASE) /** Array initializer of SMC peripheral base addresses */ #define SMC_BASE_ADDRS { SMC_BASE } /** Array initializer of SMC peripheral base pointers */ #define SMC_BASE_PTRS { SMC } /*! * @} */ /* end of group SMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TRGMUX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer * @{ */ /** TRGMUX - Register Layout Typedef */ typedef struct { __IO uint32_t TRGCFG[28]; /**< TRGMUX Register, array offset: 0x0, array step: 0x4 */ } TRGMUX_Type; /* ---------------------------------------------------------------------------- -- TRGMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks * @{ */ /*! @name TRGCFG - TRGMUX Register */ /*! @{ */ #define TRGMUX_TRGCFG_SEL0_MASK (0x3FU) #define TRGMUX_TRGCFG_SEL0_SHIFT (0U) /*! SEL0 - Trigger MUX Input 0 Source Select */ #define TRGMUX_TRGCFG_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK) #define TRGMUX_TRGCFG_SEL1_MASK (0x3F00U) #define TRGMUX_TRGCFG_SEL1_SHIFT (8U) /*! SEL1 - Trigger MUX Input 1 Source Select */ #define TRGMUX_TRGCFG_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK) #define TRGMUX_TRGCFG_SEL2_MASK (0x3F0000U) #define TRGMUX_TRGCFG_SEL2_SHIFT (16U) /*! SEL2 - Trigger MUX Input 2 Source Select */ #define TRGMUX_TRGCFG_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK) #define TRGMUX_TRGCFG_SEL3_MASK (0x3F000000U) #define TRGMUX_TRGCFG_SEL3_SHIFT (24U) /*! SEL3 - Trigger MUX Input 3 Source Select */ #define TRGMUX_TRGCFG_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK) #define TRGMUX_TRGCFG_LK_MASK (0x80000000U) #define TRGMUX_TRGCFG_LK_SHIFT (31U) /*! LK - Enable * 0b0..Register can be written. * 0b1..Register cannot be written until the next system Reset. */ #define TRGMUX_TRGCFG_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK) /*! @} */ /* The count of TRGMUX_TRGCFG */ #define TRGMUX_TRGCFG_COUNT (28U) /*! * @} */ /* end of group TRGMUX_Register_Masks */ /* TRGMUX - Peripheral instance base addresses */ /** Peripheral TRGMUX0 base address */ #define TRGMUX0_BASE (0x40062000u) /** Peripheral TRGMUX0 base pointer */ #define TRGMUX0 ((TRGMUX_Type *)TRGMUX0_BASE) /** Peripheral TRGMUX1 base address */ #define TRGMUX1_BASE (0x40063000u) /** Peripheral TRGMUX1 base pointer */ #define TRGMUX1 ((TRGMUX_Type *)TRGMUX1_BASE) /** Array initializer of TRGMUX peripheral base addresses */ #define TRGMUX_BASE_ADDRS { TRGMUX0_BASE, TRGMUX1_BASE } /** Array initializer of TRGMUX peripheral base pointers */ #define TRGMUX_BASE_PTRS { TRGMUX0, TRGMUX1 } #define TRGMUX_INSTANCE_MASK 0xF #define TRGMUX_INSTANCE_SHIFT 12 #define TRGMUX_PERIPHERAL_MASK 0xFFF #define TRGMUX_PERIPHERAL_SHIFT 0 #define TRGMUX_INSTANCE_0 0 #define TRGMUX_INSTANCE_1 1 #define TRGMUX_DMAMUX0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 0) #define TRGMUX_EXTOUT0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 1) #define TRGMUX_EXTOUT1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 2) #define TRGMUX_ADC0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 3) #define TRGMUX_ADC1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 4) #define TRGMUX_CMP0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 7) #define TRGMUX_CMP1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 8) #define TRGMUX_FTM0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 10) #define TRGMUX_FTM1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 11) #define TRGMUX_FTM2_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 12) #define TRGMUX_PDB0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 14) #define TRGMUX_FLEXIO_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 17) #define TRGMUX_LPIT0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 18) #define TRGMUX_LPUART0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 19) #define TRGMUX_LPUART1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 20) #define TRGMUX_LPI2C0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 21) #define TRGMUX_LPI2C1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 22) #define TRGMUX_LPSPI0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 23) #define TRGMUX_LPSPI1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 24) #define TRGMUX_LPTMR0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 25) #define TRGMUX_TSI_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 26) #define TRGMUX_PWT_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 27) #define TRGMUX_CTRL0_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 0) #define TRGMUX_CTRL1_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 1) /*! * @} */ /* end of group TRGMUX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TSI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer * @{ */ /** TSI - Register Layout Typedef */ typedef struct { __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ __IO uint32_t MODE; /**< TSI MODE Register, offset: 0xC */ __IO uint32_t MUL0; /**< TSI MUTUAL-CAP Register 0, offset: 0x10 */ __IO uint32_t MUL1; /**< TSI MUTUAL-CAP Register 1, offset: 0x14 */ __IO uint32_t SINC; /**< TSI SINC filter Register, offset: 0x18 */ __IO uint32_t SSC0; /**< TSI SSC Register 0, offset: 0x1C */ __IO uint32_t SSC1; /**< TSI SSC Register 0, offset: 0x20 */ __IO uint32_t SSC2; /**< TSI SSC Register 2, offset: 0x24 */ } TSI_Type; /* ---------------------------------------------------------------------------- -- TSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TSI_Register_Masks TSI Register Masks * @{ */ /*! @name GENCS - TSI General Control and Status Register */ /*! @{ */ #define TSI_GENCS_EOSDMEO_MASK (0x1U) #define TSI_GENCS_EOSDMEO_SHIFT (0U) /*! EOSDMEO - End-of-Scan DMA Transfer Request Enable Only * 0b0..Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or * End-of-Scan can trigger a DMA transfer request and interrupt. * 0b1..Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set. */ #define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK) #define TSI_GENCS_EOSF_MASK (0x4U) #define TSI_GENCS_EOSF_SHIFT (2U) /*! EOSF - End of Scan Flag * 0b0..Scan not complete. * 0b1..Scan complete. */ #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK) #define TSI_GENCS_SCNIP_MASK (0x8U) #define TSI_GENCS_SCNIP_SHIFT (3U) /*! SCNIP - Scan In Progress Status * 0b0..No scan in progress. * 0b1..Scan in progress. */ #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK) #define TSI_GENCS_STM_MASK (0x10U) #define TSI_GENCS_STM_SHIFT (4U) /*! STM - Scan Trigger Mode * 0b0..Software trigger scan. * 0b1..Hardware trigger scan. */ #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK) #define TSI_GENCS_STPE_MASK (0x20U) #define TSI_GENCS_STPE_SHIFT (5U) /*! STPE - TSI STOP Enable * 0b0..TSI is disabled when MCU goes into low power mode. * 0b1..Allows TSI to continue running in all low power modes. */ #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK) #define TSI_GENCS_TSIIEN_MASK (0x40U) #define TSI_GENCS_TSIIEN_SHIFT (6U) /*! TSIIEN - Touch Sensing Input Interrupt Enable * 0b0..TSI interrupt is disabled. * 0b1..TSI interrupt is enabled. */ #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK) #define TSI_GENCS_TSIEN_MASK (0x80U) #define TSI_GENCS_TSIEN_SHIFT (7U) /*! TSIEN - Touch Sensing Input Module Enable * 0b0..TSI module disabled. * 0b1..TSI module enabled. */ #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK) #define TSI_GENCS_CLKSOC_SEL_MASK (0x800U) #define TSI_GENCS_CLKSOC_SEL_SHIFT (11U) /*! CLKSOC_SEL - CLKSOC_SEL */ #define TSI_GENCS_CLKSOC_SEL(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CLKSOC_SEL_SHIFT)) & TSI_GENCS_CLKSOC_SEL_MASK) #define TSI_GENCS_RUN_CTRL_MASK (0x1000U) #define TSI_GENCS_RUN_CTRL_SHIFT (12U) /*! RUN_CTRL - RUN_CTRL */ #define TSI_GENCS_RUN_CTRL(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_RUN_CTRL_SHIFT)) & TSI_GENCS_RUN_CTRL_MASK) #define TSI_GENCS_TSI_ANA_TEST_MASK (0xE000U) #define TSI_GENCS_TSI_ANA_TEST_SHIFT (13U) /*! TSI_ANA_TEST - TSI_ANA_TEST */ #define TSI_GENCS_TSI_ANA_TEST(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSI_ANA_TEST_SHIFT)) & TSI_GENCS_TSI_ANA_TEST_MASK) #define TSI_GENCS_DVOLT_MASK (0x180000U) #define TSI_GENCS_DVOLT_SHIFT (19U) /*! DVOLT - DVOLT * 0b00..Vm=0.3V; Vp=1.3V; dvolt=1.0V. * 0b01..Vm=0.3V; Vp=1.6V; dvolt=1.3V. * 0b10..Vm=0.3V; Vp=1.9V; dvolt=1.6V. * 0b11..Vm=0.3V; Vp=2.3V; dvolt=2.0V. */ #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK) #define TSI_GENCS_ESOR_MASK (0x10000000U) #define TSI_GENCS_ESOR_SHIFT (28U) /*! ESOR - End-of-scan or Out-of-Range Interrupt Selection * 0b0..Out-of-range interrupt is allowed. * 0b1..End-of-scan interrupt is allowed. */ #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK) #define TSI_GENCS_OUTRGF_MASK (0x80000000U) #define TSI_GENCS_OUTRGF_SHIFT (31U) /*! OUTRGF - Out of Range Flag. */ #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK) /*! @} */ /*! @name DATA - TSI DATA Register */ /*! @{ */ #define TSI_DATA_TSICNT_MASK (0xFFFFU) #define TSI_DATA_TSICNT_SHIFT (0U) /*! TSICNT - TSI Conversion Counter Value */ #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK) #define TSI_DATA_SWTS_MASK (0x400000U) #define TSI_DATA_SWTS_SHIFT (22U) /*! SWTS - Software Trigger Start * 0b0..No effect. * 0b1..Start a scan to determine which channel is specified by TSI_DATA[TSICH]. */ #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK) #define TSI_DATA_DMAEN_MASK (0x800000U) #define TSI_DATA_DMAEN_SHIFT (23U) /*! DMAEN - DMA Transfer Enabled * 0b0..Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert. * 0b1..DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert. */ #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK) #define TSI_DATA_TSICH_MASK (0xF8000000U) #define TSI_DATA_TSICH_SHIFT (27U) /*! TSICH - TSICH * 0b00000..For self-cap mode: Channel 0. * 0b00001..For self-cap mode: Channel 1. * 0b00010..For self-cap mode: Channel 2. * 0b00011..For self-cap mode: Channel 3. * 0b00100..For self-cap mode: Channel 4. * 0b00101..For self-cap mode: Channel 5. * 0b00110..For self-cap mode: Channel 6. * 0b00111..For self-cap mode: Channel 7. * 0b01000..For self-cap mode: Channel 8. * 0b01001..For self-cap mode: Channel 9. * 0b01010..For self-cap mode: Channel 10. * 0b01011..For self-cap mode: Channel 11. * 0b01100..For self-cap mode: Channel 12. * 0b01101..For self-cap mode: Channel 13. * 0b01110..For self-cap mode: Channel 14. * 0b01111..For self-cap mode: Channel 15. * 0b10000..For self-cap mode: Channel 16. * 0b10001..For self-cap mode: Channel 17. * 0b10010..For self-cap mode: Channel 18. * 0b10011..For self-cap mode: Channel 19. * 0b10100..For self-cap mode: Channel 20. * 0b10101..For self-cap mode: Channel 21. * 0b10110..For self-cap mode: Channel 22. * 0b10111..For self-cap mode: Channel 23. * 0b11000..For self-cap mode: Channel 24. */ #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK) /*! @} */ /*! @name TSHD - TSI Threshold Register */ /*! @{ */ #define TSI_TSHD_THRESL_MASK (0xFFFFU) #define TSI_TSHD_THRESL_SHIFT (0U) /*! THRESL - TSI Wakeup Channel Low-threshold */ #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK) #define TSI_TSHD_THRESH_MASK (0xFFFF0000U) #define TSI_TSHD_THRESH_SHIFT (16U) /*! THRESH - TSI Wakeup Channel High-threshold */ #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK) /*! @} */ /*! @name MODE - TSI MODE Register */ /*! @{ */ #define TSI_MODE_S_NOISE_MASK (0x1U) #define TSI_MODE_S_NOISE_SHIFT (0U) /*! S_NOISE - S_NOISE * 0b0..noise cancellation off. * 0b1..noise cancellation on. */ #define TSI_MODE_S_NOISE(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_NOISE_SHIFT)) & TSI_MODE_S_NOISE_MASK) #define TSI_MODE_MODE_MASK (0x2U) #define TSI_MODE_MODE_SHIFT (1U) /*! MODE - MODE * 0b0..self-cap mode. * 0b1..mutual-cap mode. */ #define TSI_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_MODE_SHIFT)) & TSI_MODE_MODE_MASK) #define TSI_MODE_SETCLK_MASK (0x60U) #define TSI_MODE_SETCLK_SHIFT (5U) /*! SETCLK - SETCLK * 0b00..20.72MHz. * 0b01..16.65MHz. * 0b10..13.87MHz. * 0b11..11.91MHz. */ #define TSI_MODE_SETCLK(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_SETCLK_SHIFT)) & TSI_MODE_SETCLK_MASK) #define TSI_MODE_S_XCH_MASK (0x7000U) #define TSI_MODE_S_XCH_SHIFT (12U) /*! S_XCH - S_XCH * 0b000..1/16. * 0b001..1/8. * 0b010..1/4. * 0b011..1/2. * 0b100..NA. * 0b101..NA. * 0b110..NA. * 0b111..NA. */ #define TSI_MODE_S_XCH(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_XCH_SHIFT)) & TSI_MODE_S_XCH_MASK) #define TSI_MODE_S_XIN_MASK (0x40000U) #define TSI_MODE_S_XIN_SHIFT (18U) /*! S_XIN - S_XIN * 0b0..1/8. * 0b1..1/4. */ #define TSI_MODE_S_XIN(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_XIN_SHIFT)) & TSI_MODE_S_XIN_MASK) #define TSI_MODE_S_CTRIM_MASK (0x380000U) #define TSI_MODE_S_CTRIM_SHIFT (19U) /*! S_CTRIM - Capacitor trim setting * 0b000..Ctrim=2.5p. * 0b001..Ctrim=5.0p. * 0b010..Ctrim=7.5p. * 0b011..Ctrim=10p. * 0b100..Ctrim=12.5p. * 0b101..Ctrim=15p. * 0b110..Ctrim=17.5p. * 0b111..Ctrim=20p. */ #define TSI_MODE_S_CTRIM(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_CTRIM_SHIFT)) & TSI_MODE_S_CTRIM_MASK) #define TSI_MODE_S_SEN_MASK (0x400000U) #define TSI_MODE_S_SEN_SHIFT (22U) /*! S_SEN - S_SEN * 0b0..Sensitivity boost off. * 0b1..Sensitivity boost on. */ #define TSI_MODE_S_SEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_SEN_SHIFT)) & TSI_MODE_S_SEN_MASK) #define TSI_MODE_S_W_SHIELD_MASK (0x800000U) #define TSI_MODE_S_W_SHIELD_SHIFT (23U) /*! S_W_SHIELD - S_W_SHIELD * 0b0..shield switch off. * 0b1..shield switch on. */ #define TSI_MODE_S_W_SHIELD(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_W_SHIELD_SHIFT)) & TSI_MODE_S_W_SHIELD_MASK) #define TSI_MODE_S_XDN_MASK (0x70000000U) #define TSI_MODE_S_XDN_SHIFT (28U) /*! S_XDN - S_XDN * 0b000..1/16. * 0b001..1/8. * 0b010..1/4. * 0b011..1/2. * 0b100..NA. * 0b101..NA. * 0b110..NA. * 0b111..NA. */ #define TSI_MODE_S_XDN(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_XDN_SHIFT)) & TSI_MODE_S_XDN_MASK) /*! @} */ /*! @name MUL0 - TSI MUTUAL-CAP Register 0 */ /*! @{ */ #define TSI_MUL0_M_SEL_RX_MASK (0x7U) #define TSI_MUL0_M_SEL_RX_SHIFT (0U) /*! M_SEL_RX - M_SEL_RX * 0b000..select channel 6 as rx6. * 0b001..select channel 7 as rx7. * 0b010..select channel 8 as rx8. * 0b011..select channel 9 as rx9. * 0b100..select channel 10 as rx10. * 0b101..select channel 11 as rx11. * 0b110..NA. * 0b111..NA. */ #define TSI_MUL0_M_SEL_RX(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_SEL_RX_SHIFT)) & TSI_MUL0_M_SEL_RX_MASK) #define TSI_MUL0_M_SEL_TX_MASK (0x70U) #define TSI_MUL0_M_SEL_TX_SHIFT (4U) /*! M_SEL_TX - M_SEL_TX * 0b000..select channel 0 as tx0. * 0b001..select channel 1 as tx1. * 0b010..select channel 2 as tx2. * 0b011..select channel 3 as tx3. * 0b100..select channel 4 as tx4. * 0b101..select channel 5 as tx5. * 0b110..NA. * 0b111..NA. */ #define TSI_MUL0_M_SEL_TX(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_SEL_TX_SHIFT)) & TSI_MUL0_M_SEL_TX_MASK) #define TSI_MUL0_M_SEN_RES_MASK (0xF00U) #define TSI_MUL0_M_SEN_RES_SHIFT (8U) /*! M_SEN_RES - M_SEN_RES * 0b0000..2.5k. * 0b0001..5k. * 0b0010..7.5k. * 0b0011..10k. * 0b0100..12.5k. * 0b0101..15k. * 0b0110..17.5k. * 0b0111..20k. * 0b1000..22.5k. * 0b1001..25k. * 0b1010..27.5k. * 0b1011..30k. * 0b1100..32.5k. * 0b1101..35k. * 0b1110..37.5k. * 0b1111..40k. */ #define TSI_MUL0_M_SEN_RES(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_SEN_RES_SHIFT)) & TSI_MUL0_M_SEN_RES_MASK) #define TSI_MUL0_M_PRE_RES_MASK (0xE000U) #define TSI_MUL0_M_PRE_RES_SHIFT (13U) /*! M_PRE_RES - M_PRE_RES * 0b000..1k. * 0b001..2k. * 0b010..3k. * 0b011..4k. * 0b100..5k. * 0b101..6k. * 0b110..7k. * 0b111..8k. */ #define TSI_MUL0_M_PRE_RES(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_PRE_RES_SHIFT)) & TSI_MUL0_M_PRE_RES_MASK) #define TSI_MUL0_M_PRE_CURRENT_MASK (0xE0000000U) #define TSI_MUL0_M_PRE_CURRENT_SHIFT (29U) /*! M_PRE_CURRENT - M_PRE_CURRENT * 0b000..1uA. * 0b001..2uA. * 0b010..3uA. * 0b011..4uA. * 0b100..5uA. * 0b101..6uA. * 0b110..7uA. * 0b111..8uA. */ #define TSI_MUL0_M_PRE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_PRE_CURRENT_SHIFT)) & TSI_MUL0_M_PRE_CURRENT_MASK) /*! @} */ /*! @name MUL1 - TSI MUTUAL-CAP Register 1 */ /*! @{ */ #define TSI_MUL1_M_NMIR_CTRL_MASK (0x1U) #define TSI_MUL1_M_NMIR_CTRL_SHIFT (0U) /*! M_NMIR_CTRL - M_NMIR_CTRL * 0b0..Enable NMOS mirror. * 0b1..Disable NMOS mirror. */ #define TSI_MUL1_M_NMIR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_NMIR_CTRL_SHIFT)) & TSI_MUL1_M_NMIR_CTRL_MASK) #define TSI_MUL1_M_NMIRROR_MASK (0x6U) #define TSI_MUL1_M_NMIRROR_SHIFT (1U) /*! M_NMIRROR - M_NMIRROR * 0b00..m=1. * 0b01..m=2. * 0b10..m=3. * 0b11..m=4. */ #define TSI_MUL1_M_NMIRROR(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_NMIRROR_SHIFT)) & TSI_MUL1_M_NMIRROR_MASK) #define TSI_MUL1_M_PMIRRORR_MASK (0x18U) #define TSI_MUL1_M_PMIRRORR_SHIFT (3U) /*! M_PMIRRORR - M_PMIRRORR * 0b00..m=1. * 0b01..m=2. * 0b10..m=3. * 0b11..m=4. */ #define TSI_MUL1_M_PMIRRORR(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_PMIRRORR_SHIFT)) & TSI_MUL1_M_PMIRRORR_MASK) #define TSI_MUL1_M_PMIRRORL_MASK (0xE0U) #define TSI_MUL1_M_PMIRRORL_SHIFT (5U) /*! M_PMIRRORL - M_PMIRRORL * 0b000..m=4. * 0b001..m=8. * 0b010..m=12. * 0b011..m=16. * 0b100..m=20. * 0b101..m=24. * 0b110..m=28. * 0b111..m=32. */ #define TSI_MUL1_M_PMIRRORL(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_PMIRRORL_SHIFT)) & TSI_MUL1_M_PMIRRORL_MASK) #define TSI_MUL1_M_TRIM2_MASK (0xFF00U) #define TSI_MUL1_M_TRIM2_SHIFT (8U) /*! M_TRIM2 - M_TRIM2 */ #define TSI_MUL1_M_TRIM2(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_TRIM2_SHIFT)) & TSI_MUL1_M_TRIM2_MASK) #define TSI_MUL1_M_VPRE_CHOOSE_MASK (0x10000U) #define TSI_MUL1_M_VPRE_CHOOSE_SHIFT (16U) /*! M_VPRE_CHOOSE - M_VPRE_CHOOSE * 0b0..Internal 1.2V voltage. * 0b1..1.2V PMC output. */ #define TSI_MUL1_M_VPRE_CHOOSE(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_VPRE_CHOOSE_SHIFT)) & TSI_MUL1_M_VPRE_CHOOSE_MASK) #define TSI_MUL1_M_MODE_MASK (0x40000U) #define TSI_MUL1_M_MODE_SHIFT (18U) /*! M_MODE - M_MODE * 0b0..-5V~+5V. * 0b1..0V~+5V. */ #define TSI_MUL1_M_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_MODE_SHIFT)) & TSI_MUL1_M_MODE_MASK) #define TSI_MUL1_M_SEN_BOOST_MASK (0xF80000U) #define TSI_MUL1_M_SEN_BOOST_SHIFT (19U) /*! M_SEN_BOOST - M_SEN_BOOST * 0b00000..0u. * 0b00001..2u. * 0b00010..4u. * 0b00011..6u. * 0b00100..8u. * 0b00101..10u. * 0b00110..12u. * 0b00111..14u * 0b01000..16u. * 0b01001..18u. * 0b01010..20u. * 0b01011..22u. * 0b01100..24u. * 0b01101..26u. * 0b01110..28u. * 0b01111..30u. * 0b10000..32u. * 0b10001..34u. * 0b10010..36u. * 0b10011..38u. * 0b10100..40u. * 0b10101..42u. * 0b10110..44u. * 0b10111..46u. * 0b11000..48u. * 0b11001..50u. * 0b11010..52u. * 0b11011..54u. * 0b11100..56u. * 0b11101..58u. * 0b11110..60u. * 0b11111..62u. */ #define TSI_MUL1_M_SEN_BOOST(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_SEN_BOOST_SHIFT)) & TSI_MUL1_M_SEN_BOOST_MASK) /*! @} */ /*! @name SINC - TSI SINC filter Register */ /*! @{ */ #define TSI_SINC_SSC_CONTROL_OUT_MASK (0x1U) #define TSI_SINC_SSC_CONTROL_OUT_SHIFT (0U) /*! SSC_CONTROL_OUT - SSC_CONTROL_OUT * 0b0..SSC output value is 0. * 0b1..SSC output value is 1. */ #define TSI_SINC_SSC_CONTROL_OUT(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SSC_CONTROL_OUT_SHIFT)) & TSI_SINC_SSC_CONTROL_OUT_MASK) #define TSI_SINC_SINC_VALID_MASK (0x2U) #define TSI_SINC_SINC_VALID_SHIFT (1U) /*! SINC_VALID - SINC_VALID * 0b0..SINC filter is disabled. * 0b1..SINC filter is enabled. */ #define TSI_SINC_SINC_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SINC_VALID_SHIFT)) & TSI_SINC_SINC_VALID_MASK) #define TSI_SINC_SINC_OVERFLOW_FLAG_MASK (0x4U) #define TSI_SINC_SINC_OVERFLOW_FLAG_SHIFT (2U) /*! SINC_OVERFLOW_FLAG - SINC_OVERFLOW_FLAG * 0b0..The counter result has no overflow occurrence in the last scan process. * 0b1..The counter result has an overflow occurrence in the last scan process. */ #define TSI_SINC_SINC_OVERFLOW_FLAG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SINC_OVERFLOW_FLAG_SHIFT)) & TSI_SINC_SINC_OVERFLOW_FLAG_MASK) #define TSI_SINC_SWITCH_ENABLE_MASK (0x8U) #define TSI_SINC_SWITCH_ENABLE_SHIFT (3U) /*! SWITCH_ENABLE - SWITCH_ENABLE * 0b0..SSC function is disabled. * 0b1..SSC function is enabled. */ #define TSI_SINC_SWITCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SWITCH_ENABLE_SHIFT)) & TSI_SINC_SWITCH_ENABLE_MASK) #define TSI_SINC_DECIMATION_MASK (0x1F0000U) #define TSI_SINC_DECIMATION_SHIFT (16U) /*! DECIMATION - DECIMATION * 0b00000..The TSI_DATA[TSICNT] bits is the counter value of 1 scan period. * 0b00001..The TSI_DATA[TSICNT] bits is the counter value of 2 scan periods. * 0b00010..The TSI_DATA[TSICNT] bits is the counter value of 3 scan periods. * 0b00011..The TSI_DATA[TSICNT] bits is the counter value of 4 scan periods. * 0b00100..The TSI_DATA[TSICNT] bits is the counter value of 5 scan periods. * 0b00101..The TSI_DATA[TSICNT] bits is the counter value of 6 scan periods. * 0b00110..The TSI_DATA[TSICNT] bits is the counter value of 7 scan periods. * 0b00111..The TSI_DATA[TSICNT] bits is the counter value of 8 scan periods. * 0b01000..The TSI_DATA[TSICNT] bits is the counter value of 9 scan periods. * 0b01001..The TSI_DATA[TSICNT] bits is the counter value of 10 scan periods. * 0b01010..The TSI_DATA[TSICNT] bits is the counter value of 11 scan periods. * 0b01011..The TSI_DATA[TSICNT] bits is the counter value of 12 scan periods. * 0b01100..The TSI_DATA[TSICNT] bits is the counter value of 13 scan periods. * 0b01101..The TSI_DATA[TSICNT] bits is the counter value of 14 scan periods. * 0b01110..The TSI_DATA[TSICNT] bits is the counter value of 15 scan periods. * 0b01111..The TSI_DATA[TSICNT] bits is the counter value of 16 scan periods. * 0b10000..The TSI_DATA[TSICNT] bits is the counter value of 17 scan periods. * 0b10001..The TSI_DATA[TSICNT] bits is the counter value of 18 scan periods. * 0b10010..The TSI_DATA[TSICNT] bits is the counter value of 19 scan periods. * 0b10011..The TSI_DATA[TSICNT] bits is the counter value of 20 scan periods. * 0b10100..The TSI_DATA[TSICNT] bits is the counter value of 21 scan periods. * 0b10101..The TSI_DATA[TSICNT] bits is the counter value of 22 scan periods. * 0b10110..The TSI_DATA[TSICNT] bits is the counter value of 23 scan periods. * 0b10111..The TSI_DATA[TSICNT] bits is the counter value of 24 scan periods. * 0b11000..The TSI_DATA[TSICNT] bits is the counter value of 25 scan periods. * 0b11001..The TSI_DATA[TSICNT] bits is the counter value of 26 scan periods. * 0b11010..The TSI_DATA[TSICNT] bits is the counter value of 27 scan periods. * 0b11011..The TSI_DATA[TSICNT] bits is the counter value of 28 scan periods. * 0b11100..The TSI_DATA[TSICNT] bits is the counter value of 29 scan periods. * 0b11101..The TSI_DATA[TSICNT] bits is the counter value of 30 scan periods. * 0b11110..The TSI_DATA[TSICNT] bits is the counter value of 31 scan periods. * 0b11111..The TSI_DATA[TSICNT] bits is the counter value of 32 scan periods. */ #define TSI_SINC_DECIMATION(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_DECIMATION_SHIFT)) & TSI_SINC_DECIMATION_MASK) #define TSI_SINC_ORDER_MASK (0x200000U) #define TSI_SINC_ORDER_SHIFT (21U) /*! ORDER - ORDER * 0b0..Using 1 order SINC filter. * 0b1..Using 2 order SINC filter. */ #define TSI_SINC_ORDER(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_ORDER_SHIFT)) & TSI_SINC_ORDER_MASK) #define TSI_SINC_CUTOFF_MASK (0xF000000U) #define TSI_SINC_CUTOFF_SHIFT (24U) /*! CUTOFF - CUTOFF * 0b0000..div=1. * 0b0001..div=2. * 0b0010..div=4. * 0b0011..div=8. * 0b0100..div=16. * 0b0101..div=32. * 0b0110..div=64. * 0b0111..div=128. * 0b1000..NC. * 0b1001..NC. * 0b1010..NC. * 0b1011..NC. * 0b1100..NC. * 0b1101..NC * 0b1110..NC. * 0b1111..NC. */ #define TSI_SINC_CUTOFF(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_CUTOFF_SHIFT)) & TSI_SINC_CUTOFF_MASK) /*! @} */ /*! @name SSC0 - TSI SSC Register 0 */ /*! @{ */ #define TSI_SSC0_SSC_PRESCALE_NUM_MASK (0xFFU) #define TSI_SSC0_SSC_PRESCALE_NUM_SHIFT (0U) /*! SSC_PRESCALE_NUM - SSC_PRESCALE_NUM * 0b00000000..div2(2^0*2) * 0b00000001..div4(2^1*2) * 0b00000011..div8(2^2*2) * 0b00000111..div16(2^3*2) * 0b00001111..div32(2^4*2) * 0b00011111..div64(2^5*2) * 0b00111111..div128(2^6*2) * 0b01111111..div256(2^7*2) * 0b11111111..div512(2^8*2) */ #define TSI_SSC0_SSC_PRESCALE_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_PRESCALE_NUM_SHIFT)) & TSI_SSC0_SSC_PRESCALE_NUM_MASK) #define TSI_SSC0_BASE_NOCHARGE_NUM_MASK (0xF0000U) #define TSI_SSC0_BASE_NOCHARGE_NUM_SHIFT (16U) /*! BASE_NOCHARGE_NUM - BASE_NOCHARGE_NUM * 0b0000..The SSC output bit 1's basic period will be 1 clock cycle of system clock. * 0b0001..The SSC output bit 1's basic period will be 2 clock cycles of system clock. * 0b0010..The SSC output bit 1's basic period will be 3 clock cycles of system clock. * 0b0011..The SSC output bit 1's basic period will be 4 clock cycles of system clock. * 0b0100..The SSC output bit 1's basic period will be 5 clock cycles of system clock. * 0b0101..The SSC output bit 1's basic period will be 6 clock cycles of system clock. * 0b0110..The SSC output bit 1's basic period will be 7 clock cycles of system clock. * 0b0111..The SSC output bit 1's basic period will be 8 clock cycles of system clock. * 0b1000..The SSC output bit 1's basic period will be 9 clock cycles of system clock. * 0b1001..The SSC output bit 1's basic period will be 10 clock cycles of system clock. * 0b1010..The SSC output bit 1's basic period will be 11 clock cycles of system clock. * 0b1011..The SSC output bit 1's basic period will be 12 clock cycles of system clock. * 0b1100..The SSC output bit 1's basic period will be 13 clock cycles of system clock. * 0b1101..The SSC output bit 1's basic period will be 14 clock cycles of system clock. * 0b1110..The SSC output bit 1's basic period will be 15 clock cycles of system clock. * 0b1111..The SSC output bit 1's basic period will be 16 clock cycles of system clock. */ #define TSI_SSC0_BASE_NOCHARGE_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_BASE_NOCHARGE_NUM_SHIFT)) & TSI_SSC0_BASE_NOCHARGE_NUM_MASK) #define TSI_SSC0_CHARGE_NUM_MASK (0xF00000U) #define TSI_SSC0_CHARGE_NUM_SHIFT (20U) /*! CHARGE_NUM - CHARGE_NUM * 0b0000..The SSC output bit 0's period will be 1 clock cycle of system clock. * 0b0001..The SSC output bit 0's period will be 2 clock cycles of system clock. * 0b0010..The SSC output bit 0's period will be 3 clock cycles of system clock. * 0b0011..The SSC output bit 0's period will be 4 clock cycles of system clock. * 0b0100..The SSC output bit 0's period will be 5 clock cycles of system clock. * 0b0101..The SSC output bit 0's period will be 6 clock cycles of system clock. * 0b0110..The SSC output bit 0's period will be 7 clock cycles of system clock. * 0b0111..The SSC output bit 0's period will be 8 clock cycles of system clock. * 0b1000..The SSC output bit 0's period will be 9 clock cycles of system clock. * 0b1001..The SSC output bit 0's period will be 10 clock cycles of system clock. * 0b1010..The SSC output bit 0's period will be 11 clock cycles of system clock. * 0b1011..The SSC output bit 0's period will be 12 clock cycles of system clock. * 0b1100..The SSC output bit 0's period will be 13 clock cycles of system clock. * 0b1101..The SSC output bit 0's period will be 14 clock cycles of system clock. * 0b1110..The SSC output bit 0's period will be 15 clock cycles of system clock. * 0b1111..The SSC output bit 0's period will be 16 clock cycles of system clock. */ #define TSI_SSC0_CHARGE_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_CHARGE_NUM_SHIFT)) & TSI_SSC0_CHARGE_NUM_MASK) #define TSI_SSC0_SSC_CONTROL_REVERSE_MASK (0x1000000U) #define TSI_SSC0_SSC_CONTROL_REVERSE_SHIFT (24U) /*! SSC_CONTROL_REVERSE - SSC_CONTROL_REVERSE * 0b0..Keep the polarity of the SSC output bit. * 0b1..Reverse the polarity of the SSC output bit. */ #define TSI_SSC0_SSC_CONTROL_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_CONTROL_REVERSE_SHIFT)) & TSI_SSC0_SSC_CONTROL_REVERSE_MASK) #define TSI_SSC0_SSC_MODE_MASK (0x6000000U) #define TSI_SSC0_SSC_MODE_SHIFT (25U) /*! SSC_MODE - SSC_MODE * 0b00..Using PRBS method generating SSC output bit. * 0b01..Using up-down counter generating SSC output bit. * 0b10..SSC function is disabled. * 0b11..NC. */ #define TSI_SSC0_SSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_MODE_SHIFT)) & TSI_SSC0_SSC_MODE_MASK) #define TSI_SSC0_PRBS_OUTSEL_MASK (0xF0000000U) #define TSI_SSC0_PRBS_OUTSEL_SHIFT (28U) /*! PRBS_OUTSEL - PRBS_OUTSEL * 0b0000..NC. * 0b0001..NC. * 0b0010..The length of the PRBS is 2. * 0b0011..The length of the PRBS is 3. * 0b0100..The length of the PRBS is 4. * 0b0101..The length of the PRBS is 5. * 0b0110..The length of the PRBS is 6. * 0b0111..The length of the PRBS is 7. * 0b1000..The length of the PRBS is 8. * 0b1001..The length of the PRBS is 9. * 0b1010..The length of the PRBS is 10. * 0b1011..The length of the PRBS is 11. * 0b1100..The length of the PRBS is 12. * 0b1101..The length of the PRBS is 13. * 0b1110..The length of the PRBS is 14. * 0b1111..The length of the PRBS is 15. */ #define TSI_SSC0_PRBS_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_PRBS_OUTSEL_SHIFT)) & TSI_SSC0_PRBS_OUTSEL_MASK) /*! @} */ /*! @name SSC1 - TSI SSC Register 0 */ /*! @{ */ #define TSI_SSC1_PRBS_SEED_LO_MASK (0xFFU) #define TSI_SSC1_PRBS_SEED_LO_SHIFT (0U) /*! PRBS_SEED_LO - PRBS_SEED_LO */ #define TSI_SSC1_PRBS_SEED_LO(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_SEED_LO_SHIFT)) & TSI_SSC1_PRBS_SEED_LO_MASK) #define TSI_SSC1_PRBS_SEED_HI_MASK (0xFF00U) #define TSI_SSC1_PRBS_SEED_HI_SHIFT (8U) /*! PRBS_SEED_HI - PRBS_SEED_HI */ #define TSI_SSC1_PRBS_SEED_HI(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_SEED_HI_SHIFT)) & TSI_SSC1_PRBS_SEED_HI_MASK) #define TSI_SSC1_PRBS_WEIGHT_LO_MASK (0xFF0000U) #define TSI_SSC1_PRBS_WEIGHT_LO_SHIFT (16U) /*! PRBS_WEIGHT_LO - PRBS_WEIGHT_LO */ #define TSI_SSC1_PRBS_WEIGHT_LO(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_WEIGHT_LO_SHIFT)) & TSI_SSC1_PRBS_WEIGHT_LO_MASK) #define TSI_SSC1_PRBS_WEIGHT_HI_MASK (0xFF000000U) #define TSI_SSC1_PRBS_WEIGHT_HI_SHIFT (24U) /*! PRBS_WEIGHT_HI - PRBS_WEIGHT_HI */ #define TSI_SSC1_PRBS_WEIGHT_HI(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_WEIGHT_HI_SHIFT)) & TSI_SSC1_PRBS_WEIGHT_HI_MASK) /*! @} */ /*! @name SSC2 - TSI SSC Register 2 */ /*! @{ */ #define TSI_SSC2_MOVE_REPEAT_NUM_MASK (0x1FU) #define TSI_SSC2_MOVE_REPEAT_NUM_SHIFT (0U) /*! MOVE_REPEAT_NUM - MOVE_REPEAT_NUM * 0b00000..The up_down counter will be updated for every sample-charge cycle. * 0b00001..The up_down counter will be updated for every 2 sample-charge cycles. * 0b00010..The up_down counter will be updated for every 3 sample-charge cycles. * 0b00011..The up_down counter will be updated for every 4 sample-charge cycles. * 0b00100..The up_down counter will be updated for every 5 sample-charge cycles. * 0b00101..The up_down counter will be updated for every 6 sample-charge cycles. * 0b00110..The up_down counter will be updated for every 7 sample-charge cycles. */ #define TSI_SSC2_MOVE_REPEAT_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_REPEAT_NUM_SHIFT)) & TSI_SSC2_MOVE_REPEAT_NUM_MASK) #define TSI_SSC2_MOVE_STEPS_NUM_MASK (0x700U) #define TSI_SSC2_MOVE_STEPS_NUM_SHIFT (8U) /*! MOVE_STEPS_NUM - MOVE_STEPS_NUM * 0b000..The added value for up-down counter is 0. * 0b001..The added value for up-down counter is 1. * 0b010..The added value for up-down counter is 2. * 0b011..The added value for up-down counter is 3. * 0b100..The added value for up-down counter is 4. * 0b101..The added value for up-down counter is 5. * 0b110..The added value for up-down counter is 6. * 0b111..The added value for up-down counter is 7. */ #define TSI_SSC2_MOVE_STEPS_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_STEPS_NUM_SHIFT)) & TSI_SSC2_MOVE_STEPS_NUM_MASK) #define TSI_SSC2_MOVE_NOCHARGE_MAX_MASK (0x3F0000U) #define TSI_SSC2_MOVE_NOCHARGE_MAX_SHIFT (16U) /*! MOVE_NOCHARGE_MAX - MOVE_NOCHARGE_MAX */ #define TSI_SSC2_MOVE_NOCHARGE_MAX(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_NOCHARGE_MAX_SHIFT)) & TSI_SSC2_MOVE_NOCHARGE_MAX_MASK) #define TSI_SSC2_MOVE_NOCHARGE_MIN_MASK (0xF0000000U) #define TSI_SSC2_MOVE_NOCHARGE_MIN_SHIFT (28U) /*! MOVE_NOCHARGE_MIN - MOVE_NOCHARGE_MIN * 0b0000..The SSC output bit 1's min period will be (1 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycle of system clock. * 0b0001..The SSC output bit 1's min period will be (2 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b0010..The SSC output bit 1's min period will be (3 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b0011..The SSC output bit 1's min period will be (4 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b0100..The SSC output bit 1's min period will be (5 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b0101..The SSC output bit 1's min period will be (6 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b0110..The SSC output bit 1's min period will be (7 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b0111..The SSC output bit 1's min period will be (8 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b1000..The SSC output bit 1's min period will be (9 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b1001..The SSC output bit 1's min period will be (10 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b1010..The SSC output bit 1's min period will be (11 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b1011..The SSC output bit 1's min period will be (12 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b1100..The SSC output bit 1's min period will be (13 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b1101..The SSC output bit 1's min period will be (14 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b1110..The SSC output bit 1's min period will be (15 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. * 0b1111..The SSC output bit 1's min period will be (16 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. */ #define TSI_SSC2_MOVE_NOCHARGE_MIN(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_NOCHARGE_MIN_SHIFT)) & TSI_SSC2_MOVE_NOCHARGE_MIN_MASK) /*! @} */ /*! * @} */ /* end of group TSI_Register_Masks */ /* TSI - Peripheral instance base addresses */ /** Peripheral TSI base address */ #define TSI_BASE (0x40045000u) /** Peripheral TSI base pointer */ #define TSI ((TSI_Type *)TSI_BASE) /** Array initializer of TSI peripheral base addresses */ #define TSI_BASE_ADDRS { TSI_BASE } /** Array initializer of TSI peripheral base pointers */ #define TSI_BASE_PTRS { TSI } /** Interrupt vectors for the TSI peripheral type */ #define TSI_IRQS { TSI_IRQn } /*! * @} */ /* end of group TSI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer * @{ */ /** WDOG - Register Layout Typedef */ typedef struct { __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ } WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /*! @name CS - Watchdog Control and Status Register */ /*! @{ */ #define WDOG_CS_STOP_MASK (0x1U) #define WDOG_CS_STOP_SHIFT (0U) /*! STOP - Stop Enable * 0b0..Watchdog disabled in chip stop mode. * 0b1..Watchdog enabled in chip stop mode. */ #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) #define WDOG_CS_WAIT_MASK (0x2U) #define WDOG_CS_WAIT_SHIFT (1U) /*! WAIT - Wait Enable * 0b0..Watchdog disabled in chip wait mode. * 0b1..Watchdog enabled in chip wait mode. */ #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) #define WDOG_CS_DBG_MASK (0x4U) #define WDOG_CS_DBG_SHIFT (2U) /*! DBG - Debug Enable * 0b0..Watchdog disabled in chip debug mode. * 0b1..Watchdog enabled in chip debug mode. */ #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) #define WDOG_CS_TST_MASK (0x18U) #define WDOG_CS_TST_SHIFT (3U) /*! TST - Watchdog Test * 0b00..Watchdog test mode disabled. * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should * use this setting to indicate that the watchdog is functioning normally in user mode. * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. */ #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) #define WDOG_CS_UPDATE_MASK (0x20U) #define WDOG_CS_UPDATE_SHIFT (5U) /*! UPDATE - Allow updates * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. */ #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) #define WDOG_CS_INT_MASK (0x40U) #define WDOG_CS_INT_SHIFT (6U) /*! INT - Watchdog Interrupt * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. */ #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) #define WDOG_CS_EN_MASK (0x80U) #define WDOG_CS_EN_SHIFT (7U) /*! EN - Watchdog Enable * 0b0..Watchdog disabled. * 0b1..Watchdog enabled. */ #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) #define WDOG_CS_CLK_MASK (0x300U) #define WDOG_CS_CLK_SHIFT (8U) /*! CLK - Watchdog Clock * 0b00..Bus clock * 0b01..LPO clock * 0b10..System oscillator clock (SOSC, from SCG) * 0b11..Slow internal reference clock (SIRC, from SCG) */ #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) #define WDOG_CS_RCS_MASK (0x400U) #define WDOG_CS_RCS_SHIFT (10U) /*! RCS - Reconfiguration Success * 0b0..Reconfiguring WDOG. * 0b1..Reconfiguration is successful. */ #define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK) #define WDOG_CS_ULK_MASK (0x800U) #define WDOG_CS_ULK_SHIFT (11U) /*! ULK - Unlock status * 0b0..WDOG is locked. * 0b1..WDOG is unlocked. */ #define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK) #define WDOG_CS_PRES_MASK (0x1000U) #define WDOG_CS_PRES_SHIFT (12U) /*! PRES - Watchdog prescaler * 0b0..256 prescaler disabled. * 0b1..256 prescaler enabled. */ #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) #define WDOG_CS_CMD32EN_MASK (0x2000U) #define WDOG_CS_CMD32EN_SHIFT (13U) /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. */ #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) #define WDOG_CS_FLG_MASK (0x4000U) #define WDOG_CS_FLG_SHIFT (14U) /*! FLG - Watchdog Interrupt Flag * 0b0..No interrupt occurred. * 0b1..An interrupt occurred. */ #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) #define WDOG_CS_WIN_MASK (0x8000U) #define WDOG_CS_WIN_SHIFT (15U) /*! WIN - Watchdog Window * 0b0..Window mode disabled. * 0b1..Window mode enabled. */ #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) /*! @} */ /*! @name CNT - Watchdog Counter Register */ /*! @{ */ #define WDOG_CNT_CNTLOW_MASK (0xFFU) #define WDOG_CNT_CNTLOW_SHIFT (0U) /*! CNTLOW - Low byte of the Watchdog Counter */ #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) #define WDOG_CNT_CNTHIGH_MASK (0xFF00U) #define WDOG_CNT_CNTHIGH_SHIFT (8U) /*! CNTHIGH - High byte of the Watchdog Counter */ #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) /*! @} */ /*! @name TOVAL - Watchdog Timeout Value Register */ /*! @{ */ #define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) #define WDOG_TOVAL_TOVALLOW_SHIFT (0U) /*! TOVALLOW - Low byte of the timeout value */ #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) #define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) #define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) /*! TOVALHIGH - High byte of the timeout value */ #define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) /*! @} */ /*! @name WIN - Watchdog Window Register */ /*! @{ */ #define WDOG_WIN_WINLOW_MASK (0xFFU) #define WDOG_WIN_WINLOW_SHIFT (0U) /*! WINLOW - Low byte of Watchdog Window */ #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) #define WDOG_WIN_WINHIGH_MASK (0xFF00U) #define WDOG_WIN_WINHIGH_SHIFT (8U) /*! WINHIGH - High byte of Watchdog Window */ #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) /*! @} */ /*! * @} */ /* end of group WDOG_Register_Masks */ /* WDOG - Peripheral instance base addresses */ /** Peripheral WDOG base address */ #define WDOG_BASE (0x40052000u) /** Peripheral WDOG base pointer */ #define WDOG ((WDOG_Type *)WDOG_BASE) /** Array initializer of WDOG peripheral base addresses */ #define WDOG_BASE_ADDRS { WDOG_BASE } /** Array initializer of WDOG peripheral base pointers */ #define WDOG_BASE_PTRS { WDOG } /** Interrupt vectors for the WDOG peripheral type */ #define WDOG_IRQS { WDOG_EWM_IRQn } #define WDOG_UPDATE_KEY (0xD928C520U) #define WDOG_REFRESH_KEY (0xB480A602U) /*! * @} */ /* end of group WDOG_Peripheral_Access_Layer */ /* ** End of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #else #pragma pop #endif #elif defined(__CWCC__) #pragma pop #elif defined(__GNUC__) /* leave anonymous unions enabled */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=default #else #error Not supported compiler type #endif /*! * @} */ /* end of group Peripheral_access_layer */ /* ---------------------------------------------------------------------------- -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). ---------------------------------------------------------------------------- */ /*! * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). * @{ */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang system_header #endif #elif defined(__IAR_SYSTEMS_ICC__) #pragma system_include #endif /** * @brief Mask and left-shift a bit field value for use in a register bit range. * @param field Name of the register bit field. * @param value Value of the bit field. * @return Masked and shifted value. */ #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) /** * @brief Mask and right-shift a register value to extract a bit field value. * @param field Name of the register bit field. * @param value Value of the register. * @return Masked and shifted bit field value. */ #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) /*! * @} */ /* end of group Bit_Field_Generic_Macros */ /* ---------------------------------------------------------------------------- -- SDK Compatibility ---------------------------------------------------------------------------- */ /*! * @addtogroup SDK_Compatibility_Symbols SDK Compatibility * @{ */ /* No SDK compatibility issues. */ /*! * @} */ /* end of group SDK_Compatibility_Symbols */ #endif /* _MKE15Z7_H_ */