/* ** ################################################################### ** Version: rev. 1.0, 2018-05-09 ** Build: b200927 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2018-05-09) ** Initial version. ** ** ################################################################### */ #ifndef _MKE14Z4_FEATURES_H_ #define _MKE14Z4_FEATURES_H_ /* SOC module features */ /* @brief ACMP availability on the SoC. */ #define FSL_FEATURE_SOC_ACMP_COUNT (1) /* @brief ADC12 availability on the SoC. */ #define FSL_FEATURE_SOC_ADC12_COUNT (1) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) /* @brief EWM availability on the SoC. */ #define FSL_FEATURE_SOC_EWM_COUNT (1) /* @brief FGPIO availability on the SoC. */ #define FSL_FEATURE_SOC_FGPIO_COUNT (5) /* @brief FTFA availability on the SoC. */ #define FSL_FEATURE_SOC_FTFA_COUNT (1) /* @brief FTM availability on the SoC. */ #define FSL_FEATURE_SOC_FTM_COUNT (2) /* @brief GPIO availability on the SoC. */ #define FSL_FEATURE_SOC_GPIO_COUNT (5) /* @brief LPI2C availability on the SoC. */ #define FSL_FEATURE_SOC_LPI2C_COUNT (1) /* @brief LPIT availability on the SoC. */ #define FSL_FEATURE_SOC_LPIT_COUNT (1) /* @brief LPSPI availability on the SoC. */ #define FSL_FEATURE_SOC_LPSPI_COUNT (1) /* @brief LPTMR availability on the SoC. */ #define FSL_FEATURE_SOC_LPTMR_COUNT (1) /* @brief LPUART availability on the SoC. */ #define FSL_FEATURE_SOC_LPUART_COUNT (3) /* @brief MCM availability on the SoC. */ #define FSL_FEATURE_SOC_MCM_COUNT (1) /* @brief MMDVSQ availability on the SoC. */ #define FSL_FEATURE_SOC_MMDVSQ_COUNT (1) /* @brief MTB availability on the SoC. */ #define FSL_FEATURE_SOC_MTB_COUNT (1) /* @brief MTBDWT availability on the SoC. */ #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) /* @brief PCC availability on the SoC. */ #define FSL_FEATURE_SOC_PCC_COUNT (1) /* @brief PDB availability on the SoC. */ #define FSL_FEATURE_SOC_PDB_COUNT (1) /* @brief PMC availability on the SoC. */ #define FSL_FEATURE_SOC_PMC_COUNT (1) /* @brief PORT availability on the SoC. */ #define FSL_FEATURE_SOC_PORT_COUNT (5) /* @brief PWT availability on the SoC. */ #define FSL_FEATURE_SOC_PWT_COUNT (1) /* @brief RCM availability on the SoC. */ #define FSL_FEATURE_SOC_RCM_COUNT (1) /* @brief ROM availability on the SoC. */ #define FSL_FEATURE_SOC_ROM_COUNT (1) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) /* @brief SCG availability on the SoC. */ #define FSL_FEATURE_SOC_SCG_COUNT (1) /* @brief SIM availability on the SoC. */ #define FSL_FEATURE_SOC_SIM_COUNT (1) /* @brief SMC availability on the SoC. */ #define FSL_FEATURE_SOC_SMC_COUNT (1) /* @brief TRGMUX availability on the SoC. */ #define FSL_FEATURE_SOC_TRGMUX_COUNT (2) /* @brief WDOG availability on the SoC. */ #define FSL_FEATURE_SOC_WDOG_COUNT (1) /* ADC12 module features */ /* @brief Has DMA support (bit SC2[DMAEN]. */ #define FSL_FEATURE_ADC12_HAS_DMA_SUPPORT (0) /* @brief Conversion control count (related to number of registers SC1n and Rn). */ #define FSL_FEATURE_ADC12_CONVERSION_CONTROL_COUNT (4) /* ACMP module features */ /* @brief Has CMP_C3. */ #define FSL_FEATURE_ACMP_HAS_C3_REG (0) /* @brief Has C0 LINKEN Bit */ #define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (0) /* @brief Has C0 OFFSET Bit */ #define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (1) /* @brief Has C1 INPSEL Bit */ #define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (1) /* @brief Has C1 INNSEL Bit */ #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (1) /* @brief Has C1 DACOE Bit */ #define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0) /* @brief Has C1 DMODE Bit */ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (0) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (1) /* CRC module features */ /* @brief Has data register with name CRC */ #define FSL_FEATURE_CRC_HAS_CRC_REG (0) /* EWM module features */ /* @brief Has clock select (register CLKCTRL). */ #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) /* @brief Has clock prescaler (register CLKPRESCALER). */ #define FSL_FEATURE_EWM_HAS_PRESCALER (1) /* FGPIO module features */ /* No feature definitions */ /* FLASH module features */ #if defined(CPU_MKE14Z32VFP4) || defined(CPU_MKE14Z32VLD4) || defined(CPU_MKE14Z32VLF4) /* @brief Is of type FTFA. */ #define FSL_FEATURE_FLASH_IS_FTFA (1) /* @brief Is of type FTFE. */ #define FSL_FEATURE_FLASH_IS_FTFE (0) /* @brief Is of type FTFL. */ #define FSL_FEATURE_FLASH_IS_FTFL (0) /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) /* @brief Has EEPROM region protection (register FEPROT). */ #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) /* @brief Has data flash region protection (register FDPROT). */ #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) /* @brief Has flash cache control in FMC module. */ #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) /* @brief Has flash cache control in MCM module. */ #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) /* @brief Has flash cache control in MSCM module. */ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) /* @brief Has prefetch speculation control in flash, such as kv5x. */ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) /* @brief P-Flash start address. */ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) /* @brief P-Flash sector size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) /* @brief P-Flash write unit size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) /* @brief P-Flash data path width. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) /* @brief P-Flash block swap feature. */ #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) /* @brief P-Flash protection region count. */ #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) /* @brief Has FlexNVM memory. */ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) /* @brief Has FlexNVM alias. */ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) /* @brief FlexNVM block count. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) /* @brief FlexNVM block size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) /* @brief FlexNVM sector size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) /* @brief FlexNVM write unit size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) /* @brief FlexNVM data path width. */ #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) /* @brief Has FlexRAM memory. */ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) /* @brief FlexRAM size. */ #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) /* @brief Has 0x00 Read 1s Block command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) /* @brief Has 0x01 Read 1s Section command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) /* @brief Has 0x02 Program Check command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) /* @brief Has 0x03 Read Resource command. */ #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) /* @brief Has 0x06 Program Longword command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) /* @brief Has 0x07 Program Phrase command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) /* @brief Has 0x08 Erase Flash Block command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) /* @brief Has 0x09 Erase Flash Sector command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) /* @brief Has 0x0B Program Section command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) /* @brief Has 0x40 Read 1s All Blocks command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) /* @brief Has 0x41 Read Once command. */ #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) /* @brief Has 0x43 Program Once command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) /* @brief Has 0x44 Erase All Blocks command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) /* @brief Has 0x45 Verify Backdoor Access Key command. */ #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) /* @brief Has 0x46 Swap Control command. */ #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) /* @brief Has 0x49 Erase All Blocks Unsecure command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) /* @brief Has 0x4B Erase All Execute-only Segments command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) /* @brief Has 0x80 Program Partition command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) /* @brief Has 0x81 Set FlexRAM Function command. */ #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) /* @brief P-Flash Erase/Read 1st all block command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Erase sector command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Rrogram/Verify section command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Read resource command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Program check command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Program check command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Erase sector command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Rrogram/Verify section command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Read resource command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Program check command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) #elif defined(CPU_MKE14Z64VFP4) || defined(CPU_MKE14Z64VLD4) || defined(CPU_MKE14Z64VLF4) /* @brief Is of type FTFA. */ #define FSL_FEATURE_FLASH_IS_FTFA (1) /* @brief Is of type FTFE. */ #define FSL_FEATURE_FLASH_IS_FTFE (0) /* @brief Is of type FTFL. */ #define FSL_FEATURE_FLASH_IS_FTFL (0) /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) /* @brief Has EEPROM region protection (register FEPROT). */ #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) /* @brief Has data flash region protection (register FDPROT). */ #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) /* @brief Has flash cache control in FMC module. */ #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) /* @brief Has flash cache control in MCM module. */ #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) /* @brief Has flash cache control in MSCM module. */ #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) /* @brief Has prefetch speculation control in flash, such as kv5x. */ #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) /* @brief P-Flash start address. */ #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) /* @brief P-Flash block count. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) /* @brief P-Flash block size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) /* @brief P-Flash sector size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) /* @brief P-Flash write unit size. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) /* @brief P-Flash data path width. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) /* @brief P-Flash block swap feature. */ #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) /* @brief P-Flash protection region count. */ #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) /* @brief Has FlexNVM memory. */ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) /* @brief Has FlexNVM alias. */ #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) /* @brief FlexNVM block count. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) /* @brief FlexNVM block size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) /* @brief FlexNVM sector size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) /* @brief FlexNVM write unit size. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) /* @brief FlexNVM data path width. */ #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) /* @brief Has FlexRAM memory. */ #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) /* @brief FlexRAM size. */ #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) /* @brief Has 0x00 Read 1s Block command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) /* @brief Has 0x01 Read 1s Section command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) /* @brief Has 0x02 Program Check command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) /* @brief Has 0x03 Read Resource command. */ #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) /* @brief Has 0x06 Program Longword command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) /* @brief Has 0x07 Program Phrase command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) /* @brief Has 0x08 Erase Flash Block command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) /* @brief Has 0x09 Erase Flash Sector command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) /* @brief Has 0x0B Program Section command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) /* @brief Has 0x40 Read 1s All Blocks command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) /* @brief Has 0x41 Read Once command. */ #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) /* @brief Has 0x43 Program Once command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) /* @brief Has 0x44 Erase All Blocks command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) /* @brief Has 0x45 Verify Backdoor Access Key command. */ #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) /* @brief Has 0x46 Swap Control command. */ #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) /* @brief Has 0x49 Erase All Blocks Unsecure command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) /* @brief Has 0x4B Erase All Execute-only Segments command. */ #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) /* @brief Has 0x80 Program Partition command. */ #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) /* @brief Has 0x81 Set FlexRAM Function command. */ #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) /* @brief P-Flash Erase/Read 1st all block command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Erase sector command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Rrogram/Verify section command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Read resource command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Program check command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) /* @brief P-Flash Program check command address alignment. */ #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Erase sector command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Rrogram/Verify section command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Read resource command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM Program check command address alignment. */ #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) #endif /* defined(CPU_MKE14Z32VFP4) || defined(CPU_MKE14Z32VLD4) || defined(CPU_MKE14Z32VLF4) */ /* FTM module features */ /* @brief Number of channels. */ #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ (((x) == FTM0) ? (6) : \ (((x) == FTM1) ? (2) : (-1))) /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) /* @brief Has extended deadtime value. */ #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) /* @brief Enable pwm output for the module. */ #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (1) /* @brief Has half-cycle reload for the module. */ #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (1) /* @brief Has reload interrupt. */ #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (1) /* @brief Has reload initialization trigger. */ #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (1) /* @brief Has DMA support, bitfield CnSC[DMA]. */ #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (0) /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) /* @brief If instance has only TPM function. */ #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) /* GPIO module features */ /* @brief Has GPIO attribute checker register (GACR). */ #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) /* LPI2C module features */ /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) /* LPIT module features */ /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ #define FSL_FEATURE_LPIT_TIMER_COUNT (2) /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1) /* LPSPI module features */ /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (0) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) /* LPTMR module features */ /* @brief Has shared interrupt handler with another LPTMR module. */ #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) /* @brief Whether LPTMR counter is 32 bits width. */ #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) /* LPUART module features */ /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPUART_HAS_FIFO (1) /* @brief Has 32-bit register MODIR */ #define FSL_FEATURE_LPUART_HAS_MODIR (1) /* @brief Hardware flow control (RTS, CTS) is supported. */ #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) /* @brief Infrared (modulation) is supported. */ #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) /* @brief 2 bits long stop bit is available. */ #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) /* @brief If 10-bit mode is supported. */ #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) /* @brief If 7-bit mode is supported. */ #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) /* @brief Baud rate fine adjustment is available. */ #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) /* @brief Baud rate oversampling is available. */ #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) /* @brief Baud rate oversampling is available. */ #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) /* @brief Peripheral type. */ #define FSL_FEATURE_LPUART_IS_SCI (1) /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) /* @brief Supports two match addresses to filter incoming frames. */ #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (0) /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) /* @brief Has improved smart card (ISO7816 protocol) support. */ #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) /* @brief Has local operation network (CEA709.1-B protocol) support. */ #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) /* @brief Has separate DMA RX and TX requests. */ #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) /* @brief Has separate RX and TX interrupts. */ #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) /* @brief Has LPAURT_PARAM. */ #define FSL_FEATURE_LPUART_HAS_PARAM (1) /* @brief Has LPUART_VERID. */ #define FSL_FEATURE_LPUART_HAS_VERID (1) /* @brief Has LPUART_GLOBAL. */ #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) /* MMDVSQ module features */ /* No feature definitions */ /* interrupt module features */ /* @brief Lowest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) /* @brief Highest interrupt request number. */ #define FSL_FEATURE_INTERRUPT_IRQ_MAX (29) /* PDB module features */ /* @brief Has DAC support. */ #define FSL_FEATURE_PDB_HAS_DAC (0) /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) /* @brief PDB channel number). */ #define FSL_FEATURE_PDB_CHANNEL_COUNT (1) /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (4) /* @brief DAC interval trigger number). */ #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (0) /* @brief Pulse out number). */ #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (1) /* PMC module features */ /* @brief Has Bandgap Enable In VLPx Operation support. */ #define FSL_FEATURE_PMC_HAS_BGEN (0) /* @brief Has Bandgap Buffer Enable. */ #define FSL_FEATURE_PMC_HAS_BGBE (0) /* @brief Has Bandgap Buffer Drive Select. */ #define FSL_FEATURE_PMC_HAS_BGBDS (0) /* @brief Has Low-Voltage Detect Voltage Select support. */ #define FSL_FEATURE_PMC_HAS_LVDV (0) /* @brief Has Low-Voltage Warning Voltage Select support. */ #define FSL_FEATURE_PMC_HAS_LVWV (0) /* @brief Has LPO. */ #define FSL_FEATURE_PMC_HAS_LPO (1) /* @brief Has VLPx option PMC_REGSC[VLPO]. */ #define FSL_FEATURE_PMC_HAS_VLPO (0) /* @brief Has acknowledge isolation support. */ #define FSL_FEATURE_PMC_HAS_ACKISO (0) /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ #define FSL_FEATURE_PMC_HAS_REGFPM (1) /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ #define FSL_FEATURE_PMC_HAS_REGONS (0) /* @brief Has PMC_HVDSC1. */ #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) /* @brief Has PMC_PARAM. */ #define FSL_FEATURE_PMC_HAS_PARAM (0) /* @brief Has PMC_VERID. */ #define FSL_FEATURE_PMC_HAS_VERID (0) /* PORT module features */ /* @brief Has control lock (register bit PCR[LK]). */ #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) /* @brief Has open drain control (register bit PCR[ODE]). */ #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) /* @brief Has DMA request (register bit field PCR[IRQC] values). */ #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) /* @brief Has pull resistor selection available. */ #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) /* @brief Has pull resistor enable (register bit PCR[PE]). */ #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) /* @brief Has slew rate control (register bit PCR[SRE]). */ #define FSL_FEATURE_PORT_HAS_SLEW_RATE (0) /* @brief Has passive filter (register bit field PCR[PFE]). */ #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) /* @brief Has drive strength control (register bit PCR[DSE]). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) /* @brief Has separate drive strength register (HDRVE). */ #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) /* @brief Has glitch filter (register IOFLT). */ #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) /* @brief Defines width of PCR[MUX] field. */ #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) /* @brief Has dedicated interrupt vector. */ #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) /* RCM module features */ /* @brief Has Loss-of-Lock Reset support. */ #define FSL_FEATURE_RCM_HAS_LOL (1) /* @brief Has Loss-of-Clock Reset support. */ #define FSL_FEATURE_RCM_HAS_LOC (1) /* @brief Has JTAG generated Reset support. */ #define FSL_FEATURE_RCM_HAS_JTAG (0) /* @brief Has EzPort generated Reset support. */ #define FSL_FEATURE_RCM_HAS_EZPORT (0) /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ #define FSL_FEATURE_RCM_HAS_EZPMS (0) /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ #define FSL_FEATURE_RCM_HAS_BOOTROM (1) /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ #define FSL_FEATURE_RCM_HAS_SSRS (1) /* @brief Has RCM_VERID. */ #define FSL_FEATURE_RCM_HAS_VERID (1) /* @brief Has RCM_PARAM. */ #define FSL_FEATURE_RCM_HAS_PARAM (0) /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ #define FSL_FEATURE_RCM_HAS_SRIE (1) /* @brief RCM register bit width. */ #define FSL_FEATURE_RCM_REG_WIDTH (32) /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ #define FSL_FEATURE_RCM_HAS_CORE1 (0) /* @brief Has MDM-AP system reset support RCM_SRS[MDM_AP] */ #define FSL_FEATURE_RCM_HAS_MDM_AP (1) /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ #define FSL_FEATURE_RCM_HAS_WAKEUP (0) /* RTC module features */ /* @brief Has wakeup pin. */ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) /* @brief Has wakeup pin selection (bit field CR[WPS]). */ #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) /* @brief Has low power features (registers MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) /* @brief Has read/write access control (registers WAR and RAR). */ #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ #define FSL_FEATURE_RTC_HAS_SECURITY (0) /* @brief Has RTC_CLKIN available. */ #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) /* @brief Has prescaler adjust for LPO. */ #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) /* @brief Has Clock Pin Enable field. */ #define FSL_FEATURE_RTC_HAS_CPE (1) /* @brief Has Timer Seconds Interrupt Configuration field. */ #define FSL_FEATURE_RTC_HAS_TSIC (1) /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ #define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) /* @brief Has Tamper Interrupt Register (register TIR). */ #define FSL_FEATURE_RTC_HAS_TIR (0) /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) /* @brief Has Tamper Detect Register (register TDR). */ #define FSL_FEATURE_RTC_HAS_TDR (0) /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ #define FSL_FEATURE_RTC_HAS_TDR_STF (0) /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) /* @brief Has Tamper Time Seconds Register (register TTSR). */ #define FSL_FEATURE_RTC_HAS_TTSR (0) /* @brief Has Pin Configuration Register (register PCR). */ #define FSL_FEATURE_RTC_HAS_PCR (0) /* SCG module features */ /* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */ #define FSL_FEATURE_SCG_HAS_DIVPLAT (0) /* @brief Has bus clock divider SCG_CSR[DIVBUS]. */ #define FSL_FEATURE_SCG_HAS_DIVBUS (0) /* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */ #define FSL_FEATURE_SCG_HAS_DIVEXT (0) /* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */ #define FSL_FEATURE_SCG_HAS_OSC_SCXP (0) /* @brief Has OSC freq range SOSCCFG[RANGE]. */ #define FSL_FEATURE_SCG_HAS_SOSC_RANGE (1) /* @brief Has SOSCCSR[SOSCERCLKEN]. */ #define FSL_FEATURE_SCG_HAS_OSC_ERCLK (1) /* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */ #define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1) /* @brief Has SCG_SOSCDIV[SOSCDIV1]. */ #define FSL_FEATURE_SCG_HAS_SOSCDIV1 (0) /* @brief Has SCG_SOSCDIV[SOSCDIV3]. */ #define FSL_FEATURE_SCG_HAS_SOSCDIV3 (0) /* @brief Has SCG_SIRCDIV[SIRCDIV1]. */ #define FSL_FEATURE_SCG_HAS_SIRCDIV1 (0) /* @brief Has SCG_SIRCDIV[SIRCDIV3]. */ #define FSL_FEATURE_SCG_HAS_SIRCDIV3 (0) /* @brief Has SCG_SIRCCSR[LPOPO]. */ #define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0) /* @brief Has SCG_FIRCDIV[FIRCDIV1]. */ #define FSL_FEATURE_SCG_HAS_FIRCDIV1 (0) /* @brief Has SCG_FIRCDIV[FIRCDIV3]. */ #define FSL_FEATURE_SCG_HAS_FIRCDIV3 (0) /* @brief Has SCG_FIRCCSR[FIRCLPEN]. */ #define FSL_FEATURE_SCG_HAS_FIRCLPEN (1) /* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */ #define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1) /* @brief Has SCG_SPLLDIV[SPLLDIV1]. */ #define FSL_FEATURE_SCG_HAS_SPLLDIV1 (0) /* @brief Has SCG_SPLLDIV[SPLLDIV3]. */ #define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0) /* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */ #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0) /* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */ #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0) /* @brief Has SCG_SPLLCFG[PLLS]. */ #define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0) /* @brief Has SCG_SPLLCFG[BYPASS]. */ #define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0) /* @brief Has SCG_SPLLCFG[PFDSEL]. */ #define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0) /* @brief Has SCG_SPLLCSR[SPLLCM]. */ #define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0) /* @brief Has SCG_LPFLLDIV[FLLDIV1]. */ #define FSL_FEATURE_SCG_HAS_FLLDIV1 (0) /* @brief Has SCG_LPFLLDIV[FLLDIV3]. */ #define FSL_FEATURE_SCG_HAS_FLLDIV3 (0) /* @brief Has low power FLL, SCG_LPFLLCSR. */ #define FSL_FEATURE_SCG_HAS_LPFLL (1) /* @brief Has low power FLL stop enable. */ #define FSL_FEATURE_SCG_HAS_LPFLLSTEN (0) /* @brief Has system PLL, SCG_SPLLCSR. */ #define FSL_FEATURE_SCG_HAS_SPLL (0) /* @brief Has system PLL PFD, SCG_SPLLPFD. */ #define FSL_FEATURE_SCG_HAS_SPLLPFD (0) /* @brief Has auxiliary PLL, SCG_APLLCSR. */ #define FSL_FEATURE_SCG_HAS_APLL (0) /* @brief Has RTC OSC control, SCG_ROSCCSR. */ #define FSL_FEATURE_SCG_HAS_ROSC (0) /* @brief Has RTC OSC clock source. */ #define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (0) /* @brief Has RTC OSC clock out select. */ #define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (0) /* @brief Has SIRC clock out select. */ #define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (0) /* @brief Has FIRC trim source USB0 Start of Frame. */ #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0) /* @brief Has FIRC trim source USB1 Start of Frame. */ #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0) /* @brief Has FIRC trim source system OSC. */ #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1) /* @brief Has FIRC trim source RTC OSC. */ #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (0) /* SMC module features */ /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ #define FSL_FEATURE_SMC_HAS_PSTOPO (1) /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ #define FSL_FEATURE_SMC_HAS_LPOPO (0) /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ #define FSL_FEATURE_SMC_HAS_PORPO (0) /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ #define FSL_FEATURE_SMC_HAS_LPWUI (0) /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (0) /* @brief Has stop submode. */ #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (0) /* @brief Has stop submode 0(state VLLS0 of register bit STOPCTRL[VLLSM]). */ #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (0) /* @brief Has stop submode 2(state VLLS2 of register bit STOPCTRL[VLLSM]). */ #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) /* @brief Has SMC_PARAM. */ #define FSL_FEATURE_SMC_HAS_PARAM (1) /* @brief Has SMC_VERID. */ #define FSL_FEATURE_SMC_HAS_VERID (1) /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) /* @brief Has tamper reset (register bit SRS[TAMPER]). */ #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) /* @brief Has security violation reset (register bit SRS[SECVIO]). */ #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) /* @brief Width of SMC registers. */ #define FSL_FEATURE_SMC_REG_WIDTH (32) /* SysTick module features */ /* @brief Systick has external reference clock. */ #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) /* @brief Systick external reference clock is core clock divided by this value. */ #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) /* WDOG module features */ /* @brief Watchdog is available. */ #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) /* @brief WDOG_CNT can be 32-bit written. */ #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) #endif /* _MKE14Z4_FEATURES_H_ */