/* ** ################################################################### ** Processors: MIMX8UX5AVLFZ ** MIMX8UX5AVOFZ ** MIMX8UX5CVLDZ ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019 ** Version: rev. 4.0, 2020-06-19 ** Build: b200825 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX8UX5_cm4 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2016-06-02) ** Initial version. ** - rev. 2.0 (2017-08-23) ** RevA Header EAR ** - rev. 3.0 (2018-08-22) ** RevB Header EAR ** - rev. 4.0 (2020-06-19) ** RevC Header RFP ** ** ################################################################### */ /*! * @file MIMX8UX5_cm4.h * @version 4.0 * @date 2020-06-19 * @brief CMSIS Peripheral Access Layer for MIMX8UX5_cm4 * * CMSIS Peripheral Access Layer for MIMX8UX5_cm4 */ #ifndef _MIMX8UX5_CM4_H_ #define _MIMX8UX5_CM4_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0400U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 611 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ Reserved16_IRQn = 0, /**< Reserved */ Reserved17_IRQn = 1, /**< Reserved */ Reserved18_IRQn = 2, /**< Reserved */ Reserved19_IRQn = 3, /**< Reserved */ Reserved20_IRQn = 4, /**< Reserved */ M4_MCM_IRQn = 5, /**< MCM IRQ */ Reserved22_IRQn = 6, /**< Reserved */ Reserved23_IRQn = 7, /**< Reserved */ Reserved24_IRQn = 8, /**< Reserved */ Reserved25_IRQn = 9, /**< Reserved */ Reserved26_IRQn = 10, /**< Reserved */ Reserved27_IRQn = 11, /**< Reserved */ Reserved28_IRQn = 12, /**< Reserved */ Reserved29_IRQn = 13, /**< Reserved */ Reserved30_IRQn = 14, /**< Reserved */ Reserved31_IRQn = 15, /**< Reserved */ Reserved32_IRQn = 16, /**< Reserved */ Reserved33_IRQn = 17, /**< Reserved */ Reserved34_IRQn = 18, /**< Reserved */ M4_TPM_IRQn = 19, /**< Timer PWM Module */ Reserved36_IRQn = 20, /**< Reserved */ Reserved37_IRQn = 21, /**< Reserved */ M4_LPIT_IRQn = 22, /**< Low-Power Periodic Interrupt Timer */ Reserved39_IRQn = 23, /**< Reserved */ Reserved40_IRQn = 24, /**< Reserved */ M4_LPUART_IRQn = 25, /**< Low Power UART */ Reserved42_IRQn = 26, /**< Reserved */ M4_LPI2C_IRQn = 27, /**< Low-Power I2C - Logical OR of master and slave interrupts */ Reserved44_IRQn = 28, /**< Reserved */ M4_MU0_B0_IRQn = 29, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts */ Reserved46_IRQn = 30, /**< Reserved */ Reserved47_IRQn = 31, /**< Reserved */ IRQSTEER_0_IRQn = 32, /**< External interrupt 0 */ IRQSTEER_1_IRQn = 33, /**< External interrupt 1 */ IRQSTEER_2_IRQn = 34, /**< External interrupt 2 */ IRQSTEER_3_IRQn = 35, /**< External interrupt 3 */ IRQSTEER_4_IRQn = 36, /**< External interrupt 4 */ IRQSTEER_5_IRQn = 37, /**< External interrupt 5 */ IRQSTEER_6_IRQn = 38, /**< External interrupt 6 */ IRQSTEER_7_IRQn = 39, /**< External interrupt 7 */ Reserved56_IRQn = 40, /**< Reserved */ Reserved57_IRQn = 41, /**< Reserved */ Reserved58_IRQn = 42, /**< Reserved */ Reserved59_IRQn = 43, /**< Reserved */ M4_MU0_B1_IRQn = 44, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts */ M4_MU0_B2_IRQn = 45, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts */ M4_MU0_B3_IRQn = 46, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts */ Reserved63_IRQn = 47, /**< Reserved */ Reserved64_IRQn = 48, /**< Reserved */ M4_MU1_A_IRQn = 49, /**< Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts */ M4_SW_IRQn = 50, /**< Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low) */ A35_NINTERRIRQ_IRQn = 83, /**< Shared Int Source nINTERRIRQ from A35 Sub-System */ A35_NEXTERRIRQ_IRQn = 84, /**< Shared Int Source nEXTERRIRQ from A35 Sub-System */ M4_INT_OUT0_IRQn = 99, /**< Shared Int Source INT_OUT[0] from M4 Sub-System */ M4_INT_OUT1_IRQn = 100, /**< Shared Int Source INT_OUT[1] from M4 Sub-System */ M4_INT_OUT2_IRQn = 101, /**< Shared Int Source INT_OUT[2] from M4 Sub-System */ M4_INT_OUT3_IRQn = 102, /**< Shared Int Source INT_OUT[3] from M4 Sub-System */ M4_INT_OUT4_IRQn = 103, /**< Shared Int Source INT_OUT[4] from M4 Sub-System */ M4_INT_OUT5_IRQn = 104, /**< Shared Int Source INT_OUT[5] from M4 Sub-System */ M4_INT_OUT6_IRQn = 105, /**< Shared Int Source INT_OUT[6] from M4 Sub-System */ M4_INT_OUT7_IRQn = 106, /**< Shared Int Source INT_OUT[7] from M4 Sub-System */ DISPLAY0_INT_OUT0_IRQn = 123, /**< Shared Int Source INT_OUT[0] from Display0 Sub-System */ DISPLAY0_INT_OUT1_IRQn = 124, /**< Shared Int Source INT_OUT[1] from Display0 Sub-System */ DISPLAY0_INT_OUT2_IRQn = 125, /**< Shared Int Source INT_OUT[2] from Display0 Sub-System */ DISPLAY0_INT_OUT3_IRQn = 126, /**< Shared Int Source INT_OUT[3] from Display0 Sub-System */ DISPLAY0_INT_OUT4_IRQn = 127, /**< Shared Int Source INT_OUT[4] from Display0 Sub-System */ DISPLAY0_INT_OUT5_IRQn = 128, /**< Shared Int Source INT_OUT[5] from Display0 Sub-System */ DISPLAY0_INT_OUT6_IRQn = 129, /**< Shared Int Source INT_OUT[6] from Display0 Sub-System */ DISPLAY0_INT_OUT7_IRQn = 130, /**< Shared Int Source INT_OUT[7] from Display0 Sub-System */ DISPLAY0_RESERVED_IRQn = 131, /**< Shared Int Source Reserved from Display0 Sub-System */ DISPLAY0_INT_OUT9_IRQn = 132, /**< Shared Int Source INT_OUT[9] from Display0 Sub-System */ DISPLAY0_INT_OUT10_IRQn = 133, /**< Shared Int Source INT_OUT[10] from Display0 Sub-System */ DISPLAY0_INT_OUT11_IRQn = 134, /**< Shared Int Source INT_OUT[11] from Display0 Sub-System */ DISPLAY0_INT_OUT12_IRQn = 135, /**< Shared Int Source INT_OUT[12] from Display0 Sub-System */ MIPI_DSI0_INT_OUT_IRQn = 142, /**< Shared Int Source INT_OUT from MIPI_DSI0 Sub-System */ MIPI_DSI1_INT_OUT_IRQn = 143, /**< Shared Int Source INT_OUT from MIPI_DSI1 Sub-System */ LCD_MOD_INT_IRQn = 145, /**< Shared Int Source INT_OUT from ADMA Sub-System */ LCD_PWM_INT_IRQn = 146, /**< Shared Int Source INT_OUT from ADMA Sub-System */ GPU0_XAQ2_INTR_IRQn = 147, /**< Shared Int Source xaq2_intr from GPU0 Sub-System */ ADMA_EDMA2_INT_IRQn = 149, /**< Shared Int Source eDMA2_INT from ADMA Sub-System */ ADMA_EDMA2_ERR_INT_IRQn = 150, /**< Shared Int Source eDMA2_ERR_INT from ADMA Sub-System */ ADMA_EDMA3_INT_IRQn = 151, /**< Shared Int Source eDMA3_INT from ADMA Sub-System */ ADMA_EDMA3_ERR_INT_IRQn = 152, /**< Shared Int Source eDMA3_ERR_INT from ADMA Sub-System */ LSIO_GPT0_INT_IRQn = 163, /**< Shared Int Source GPT0_INT from LSIO Sub-System */ LSIO_GPT1_INT_IRQn = 164, /**< Shared Int Source GPT1_INT from LSIO Sub-System */ LSIO_GPT2_INT_IRQn = 165, /**< Shared Int Source GPT2_INT from LSIO Sub-System */ LSIO_GPT3_INT_IRQn = 166, /**< Shared Int Source GPT3_INT from LSIO Sub-System */ LSIO_GPT4_INT_IRQn = 167, /**< Shared Int Source GPT4_INT from LSIO Sub-System */ LSIO_KPP_INT_IRQn = 168, /**< Shared Int Source KPP_INT from LSIO Sub-System */ LSIO_OCTASPI0_INT_IRQn = 175, /**< Shared Int Source OctaSPI0_INT from LSIO Sub-System */ LSIO_OCTASPI1_INT_IRQn = 176, /**< Shared Int Source OctaSPI1_INT from LSIO Sub-System */ LSIO_PWM0_INT_IRQn = 177, /**< Shared Int Source PWM0_INT from LSIO Sub-System */ LSIO_PWM1_INT_IRQn = 178, /**< Shared Int Source PWM1_INT from LSIO Sub-System */ LSIO_PWM2_INT_IRQn = 179, /**< Shared Int Source PWM2_INT from LSIO Sub-System */ LSIO_PWM3_INT_IRQn = 180, /**< Shared Int Source PWM3_INT from LSIO Sub-System */ LSIO_PWM4_INT_IRQn = 181, /**< Shared Int Source PWM4_INT from LSIO Sub-System */ LSIO_PWM5_INT_IRQn = 182, /**< Shared Int Source PWM5_INT from LSIO Sub-System */ LSIO_PWM6_INT_IRQn = 183, /**< Shared Int Source PWM6_INT from LSIO Sub-System */ LSIO_PWM7_INT_IRQn = 184, /**< Shared Int Source PWM7_INT from LSIO Sub-System */ HSIO_PCIEB_MSI_CTRL_INT_IRQn = 185, /**< Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System */ HSIO_PCIEB_CLK_REQ_INT_IRQn = 186, /**< Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System */ HSIO_PCIEB_DMA_INT_IRQn = 187, /**< Shared Int Source PCIeB_DMA_INT from HSIO Sub-System */ HSIO_PCIEB_INT_D_IRQn = 188, /**< Shared Int Source PCIeB_INT_D from HSIO Sub-System */ HSIO_PCIEB_INT_C_IRQn = 189, /**< Shared Int Source PCIeB_INT_C from HSIO Sub-System */ HSIO_PCIEB_INT_B_IRQn = 190, /**< Shared Int Source PCIeB_INT_B from HSIO Sub-System */ HSIO_PCIEB_INT_A_IRQn = 191, /**< Shared Int Source PCIeB_INT_A from HSIO Sub-System */ HSIO_PCIEB_SMLH_REQ_RST_IRQn = 192, /**< Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System */ HSIO_PCIEB_GPIO_WAKEUP0_IRQn = 193, /**< Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System */ HSIO_PCIEB_GPIO_WAKEUP1_IRQn = 194, /**< Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System */ SCU_INT_OUT0_IRQn = 195, /**< Shared Int Source INT_OUT[0] from SCU Sub-System */ SCU_INT_OUT1_IRQn = 196, /**< Shared Int Source INT_OUT[1] from SCU Sub-System */ SCU_INT_OUT2_IRQn = 197, /**< Shared Int Source INT_OUT[2] from SCU Sub-System */ SCU_INT_OUT3_IRQn = 198, /**< Shared Int Source INT_OUT[3] from SCU Sub-System */ SCU_INT_OUT4_IRQn = 199, /**< Shared Int Source INT_OUT[4] from SCU Sub-System */ SCU_INT_OUT5_IRQn = 200, /**< Shared Int Source INT_OUT[5] from SCU Sub-System */ SCU_INT_OUT6_IRQn = 201, /**< Shared Int Source INT_OUT[6] from SCU Sub-System */ SCU_INT_OUT7_IRQn = 202, /**< Shared Int Source INT_OUT[7] from SCU Sub-System */ SCU_SYS_COUNT_INT0_IRQn = 203, /**< Shared Int Source SYS_COUNT_INT0 from SCU Sub-System */ SCU_SYS_COUNT_INT1_IRQn = 204, /**< Shared Int Source SYS_COUNT_INT1 from SCU Sub-System */ SCU_SYS_COUNT_INT2_IRQn = 205, /**< Shared Int Source SYS_COUNT_INT2 from SCU Sub-System */ SCU_SYS_COUNT_INT3_IRQn = 206, /**< Shared Int Source SYS_COUNT_INT3 from SCU Sub-System */ DRC_ECC_CORRECT_INT_IRQn = 211, /**< Shared Int Source ECC_CORRECT_INT from DRC Sub-System */ DRC_ECC_NCORRECT_INT_IRQn = 212, /**< Shared Int Source ECC_NCORRECT_INT from DRC Sub-System */ DRC_SBR_DONE_INT_IRQn = 213, /**< Shared Int Source SBR_DONE_INT from DRC Sub-System */ DRC_PERF_CNT_INT_IRQn = 214, /**< Shared Int Source PERF_CNT_INT from DRC Sub-System */ LSIO_GPIO_INT0_IRQn = 219, /**< Shared Int Source GPIO_INT[0] from LSIO Sub-System */ LSIO_GPIO_INT1_IRQn = 220, /**< Shared Int Source GPIO_INT[1] from LSIO Sub-System */ LSIO_GPIO_INT2_IRQn = 221, /**< Shared Int Source GPIO_INT[2] from LSIO Sub-System */ LSIO_GPIO_INT3_IRQn = 222, /**< Shared Int Source GPIO_INT[3] from LSIO Sub-System */ LSIO_GPIO_INT4_IRQn = 223, /**< Shared Int Source GPIO_INT[4] from LSIO Sub-System */ LSIO_GPIO_INT5_IRQn = 224, /**< Shared Int Source GPIO_INT[5] from LSIO Sub-System */ LSIO_GPIO_INT6_IRQn = 225, /**< Shared Int Source GPIO_INT[6] from LSIO Sub-System */ LSIO_GPIO_INT7_IRQn = 226, /**< Shared Int Source GPIO_INT[7] from LSIO Sub-System */ LSIO_MU0_INT_IRQn = 259, /**< Shared Int Source MU0_INT from LSIO Sub-System */ LSIO_MU1_INT_IRQn = 260, /**< Shared Int Source MU1_INT from LSIO Sub-System */ LSIO_MU2_INT_IRQn = 261, /**< Shared Int Source MU2_INT from LSIO Sub-System */ LSIO_MU3_INT_IRQn = 262, /**< Shared Int Source MU3_INT from LSIO Sub-System */ LSIO_MU4_INT_IRQn = 263, /**< Shared Int Source MU4_INT from LSIO Sub-System */ LSIO_MU5_INT_A_IRQn = 267, /**< Shared Int Source MU5_INT_A from LSIO Sub-System */ LSIO_MU6_INT_A_IRQn = 268, /**< Shared Int Source MU6_INT_A from LSIO Sub-System */ LSIO_MU7_INT_A_IRQn = 269, /**< Shared Int Source MU7_INT_A from LSIO Sub-System */ LSIO_MU8_INT_A_IRQn = 270, /**< Shared Int Source MU8_INT_A from LSIO Sub-System */ LSIO_MU9_INT_A_IRQn = 271, /**< Shared Int Source MU9_INT_A from LSIO Sub-System */ LSIO_MU10_INT_A_IRQn = 272, /**< Shared Int Source MU10_INT_A from LSIO Sub-System */ LSIO_MU11_INT_A_IRQn = 273, /**< Shared Int Source MU11_INT_A from LSIO Sub-System */ LSIO_MU12_INT_A_IRQn = 274, /**< Shared Int Source MU12_INT_A from LSIO Sub-System */ LSIO_MU13_INT_A_IRQn = 275, /**< Shared Int Source MU13_INT_A from LSIO Sub-System */ LSIO_MU5_INT_B_IRQn = 283, /**< Shared Int Source MU5_INT_B from LSIO Sub-System */ LSIO_MU6_INT_B_IRQn = 284, /**< Shared Int Source MU6_INT_B from LSIO Sub-System */ LSIO_MU7_INT_B_IRQn = 285, /**< Shared Int Source MU7_INT_B from LSIO Sub-System */ LSIO_MU8_INT_B_IRQn = 286, /**< Shared Int Source MU8_INT_B from LSIO Sub-System */ LSIO_MU9_INT_B_IRQn = 287, /**< Shared Int Source MU9_INT_B from LSIO Sub-System */ LSIO_MU10_INT_B_IRQn = 288, /**< Shared Int Source MU10_INT_B from LSIO Sub-System */ LSIO_MU11_INT_B_IRQn = 289, /**< Shared Int Source MU11_INT_B from LSIO Sub-System */ LSIO_MU12_INT_B_IRQn = 290, /**< Shared Int Source MU12_INT_B from LSIO Sub-System */ LSIO_MU13_INT_B_IRQn = 291, /**< Shared Int Source MU13_INT_B from LSIO Sub-System */ ADMA_SPI0_INT_IRQn = 299, /**< Shared Int Source SPI0_INT from ADMA Sub-System */ ADMA_SPI1_INT_IRQn = 300, /**< Shared Int Source SPI1_INT from ADMA Sub-System */ ADMA_SPI2_INT_IRQn = 301, /**< Shared Int Source SPI2_INT from ADMA Sub-System */ ADMA_SPI3_INT_IRQn = 302, /**< Shared Int Source SPI3_INT from ADMA Sub-System */ ADMA_I2C0_INT_IRQn = 303, /**< Shared Int Source I2C0_INT from ADMA Sub-System */ ADMA_I2C1_INT_IRQn = 304, /**< Shared Int Source I2C1_INT from ADMA Sub-System */ ADMA_I2C2_INT_IRQn = 305, /**< Shared Int Source I2C2_INT from ADMA Sub-System */ ADMA_I2C3_INT_IRQn = 306, /**< Shared Int Source I2C3_INT from ADMA Sub-System */ ADMA_UART0_INT_IRQn = 308, /**< Shared Int Source UART0_INT from ADMA Sub-System */ ADMA_UART1_INT_IRQn = 309, /**< Shared Int Source UART1_INT from ADMA Sub-System */ ADMA_UART2_INT_IRQn = 310, /**< Shared Int Source UART2_INT from ADMA Sub-System */ ADMA_UART3_INT_IRQn = 311, /**< Shared Int Source UART3_INT from ADMA Sub-System */ CONNECTIVITY_USDHC0_INT_IRQn = 315, /**< Shared Int Source uSDHC0_INT from Connectivity Sub-System */ CONNECTIVITY_USDHC1_INT_IRQn = 316, /**< Shared Int Source uSDHC1_INT from Connectivity Sub-System */ CONNECTIVITY_USDHC2_INT_IRQn = 317, /**< Shared Int Source uSDHC2_INT from Connectivity Sub-System */ ADMA_FLEXCAN0_INT_IRQn = 318, /**< Shared Int Source FlexCAN0_INT from ADMA Sub-System */ ADMA_FLEXCAN1_INT_IRQn = 319, /**< Shared Int Source FlexCAN1_INT from ADMA Sub-System */ ADMA_FLEXCAN2_INT_IRQn = 320, /**< Shared Int Source FlexCAN2_INT from ADMA Sub-System */ ADMA_FTM0_INT_IRQn = 321, /**< Shared Int Source FTM0_INT from ADMA Sub-System */ ADMA_FTM1_INT_IRQn = 322, /**< Shared Int Source FTM1_INT from ADMA Sub-System */ ADMA_ADC0_INT_IRQn = 323, /**< Shared Int Source ADC0_INT from ADMA Sub-System */ ADMA_EXTERNAL_DMA_INT_0_IRQn = 325, /**< Shared Int Source EXTERNAL_DMA_INT_0 from ADMA Sub-System */ ADMA_EXTERNAL_DMA_INT_1_IRQn = 326, /**< Shared Int Source EXTERNAL_DMA_INT_1 from ADMA Sub-System */ ADMA_EXTERNAL_DMA_INT_2_IRQn = 327, /**< Shared Int Source EXTERNAL_DMA_INT_2 from ADMA Sub-System */ ADMA_EXTERNAL_DMA_INT_3_IRQn = 328, /**< Shared Int Source EXTERNAL_DMA_INT_3 from ADMA Sub-System */ ADMA_EXTERNAL_DMA_INT_4_IRQn = 329, /**< Shared Int Source EXTERNAL_DMA_INT_4 from ADMA Sub-System */ ADMA_EXTERNAL_DMA_INT_5_IRQn = 330, /**< Shared Int Source EXTERNAL_DMA_INT_5 from ADMA Sub-System */ CONNECTIVITY_ENET0_FRAME1_INT_IRQn = 339, /**< Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System */ CONNECTIVITY_ENET0_FRAME2_INT_IRQn = 340, /**< Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System */ CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQn = 341, /**< Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System */ CONNECTIVITY_ENET0_TIMER_INT_IRQn = 342, /**< Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System */ CONNECTIVITY_ENET1_FRAME1_INT_IRQn = 343, /**< Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System */ CONNECTIVITY_ENET1_FRAME2_INT_IRQn = 344, /**< Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System */ CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQn = 345, /**< Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System */ CONNECTIVITY_ENET1_TIMER_INT_IRQn = 346, /**< Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System */ CONNECTIVITY_DTCP_INT_IRQn = 347, /**< Shared Int Source DTCP_INT from Connectivity Sub-System */ CONNECTIVITY_MLB_INT_IRQn = 348, /**< Shared Int Source MLB_INT from Connectivity Sub-System */ CONNECTIVITY_MLB_AHB_INT_IRQn = 349, /**< Shared Int Source MLB_AHB_INT from Connectivity Sub-System */ CONNECTIVITY_USB_OTG_INT_IRQn = 350, /**< Shared Int Source USB_OTG_INT from Connectivity Sub-System */ CONNECTIVITY_USB_HOST_INT_IRQn = 351, /**< Shared Int Source USB_HOST_INT from Connectivity Sub-System */ CONNECTIVITY_UTMI_INT_IRQn = 352, /**< Shared Int Source UTMI_INT from Connectivity Sub-System */ CONNECTIVITY_WAKEUP_INT_IRQn = 353, /**< Shared Int Source WAKEUP_INT from Connectivity Sub-System */ CONNECTIVITY_USB3_INT_IRQn = 354, /**< Shared Int Source USB3_INT from Connectivity Sub-System */ CONNECTIVITY_ND_FLASH_BCH_INT_IRQn = 355, /**< Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System */ CONNECTIVITY_ND_FLASH_GPMI_INT_IRQn = 356, /**< Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System */ CONNECTIVITY_APBHDMA_IRQn = 357, /**< Shared Int Source APBHDMA from Connectivity Sub-System */ CONNECTIVITY_DMA_INT_IRQn = 358, /**< Shared Int Source DMA_INT from Connectivity Sub-System */ CONNECTIVITY_DMA_ERR_INT_IRQn = 359, /**< Shared Int Source DMA_ERR_INT from Connectivity Sub-System */ IMAGING_MSI_INT_IRQn = 371, /**< Shared Int Source MSI_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM0_INT_IRQn = 380, /**< Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM1_INT_IRQn = 381, /**< Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM2_INT_IRQn = 382, /**< Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM3_INT_IRQn = 383, /**< Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM4_INT_IRQn = 384, /**< Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM5_INT_IRQn = 385, /**< Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM6_INT_IRQn = 386, /**< Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System */ IMAGING_PDMA_STREAM7_INT_IRQn = 387, /**< Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System */ IMAGING_MJPEG_ENC0_INT_IRQn = 388, /**< Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System */ IMAGING_MJPEG_ENC1_INT_IRQn = 389, /**< Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System */ IMAGING_MJPEG_ENC2_INT_IRQn = 390, /**< Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System */ IMAGING_MJPEG_ENC3_INT_IRQn = 391, /**< Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System */ IMAGING_MJPEG_DEC0_INT_IRQn = 392, /**< Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System */ IMAGING_MJPEG_DEC1_INT_IRQn = 393, /**< Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System */ IMAGING_MJPEG_DEC2_INT_IRQn = 394, /**< Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System */ IMAGING_MJPEG_DEC3_INT_IRQn = 395, /**< Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System */ ADMA_SAI0_MOD_INT_IRQn = 397, /**< Shared Int Source SAI0_MOD_INT from ADMA Sub-System */ ADMA_SAI0_DMA_INT_IRQn = 398, /**< Shared Int Source SAI0_DMA_INT from ADMA Sub-System */ ADMA_SAI1_MOD_INT_IRQn = 399, /**< Shared Int Source SAI1_MOD_INT from ADMA Sub-System */ ADMA_SAI1_DMA_INT_IRQn = 400, /**< Shared Int Source SAI1_DMA_INT from ADMA Sub-System */ ADMA_SAI2_MOD_INT_IRQn = 401, /**< Shared Int Source SAI2_MOD_INT from ADMA Sub-System */ ADMA_SAI2_DMA_INT_IRQn = 402, /**< Shared Int Source SAI2_DMA_INT from ADMA Sub-System */ MIPI_CSI0_OUT_INT_IRQn = 403, /**< Shared Int Source OUT_INT from MIPI_CSI0 Sub-System */ ADMA_SAI3_MOD_INT_IRQn = 406, /**< Shared Int Source SAI3_MOD_INT from ADMA Sub-System */ ADMA_SAI3_DMA_INT_IRQn = 407, /**< Shared Int Source SAI3_DMA_INT from ADMA Sub-System */ ADMA_SAI4_MOD_INT_IRQn = 412, /**< Shared Int Source SAI4_MOD_INT from ADMA Sub-System */ ADMA_SAI4_DMA_INT_IRQn = 413, /**< Shared Int Source SAI4_DMA_INT from ADMA Sub-System */ ADMA_SAI5_MOD_INT_IRQn = 414, /**< Shared Int Source SAI5_MOD_INT from ADMA Sub-System */ ADMA_SAI5_DMA_INT_IRQn = 415, /**< Shared Int Source SAI5_DMA_INT from ADMA Sub-System */ ADMA_SPI0_MOD_INT_IRQn = 419, /**< Shared Int Source SPI0_MOD_INT from ADMA Sub-System */ ADMA_SPI1_MOD_INT_IRQn = 420, /**< Shared Int Source SPI1_MOD_INT from ADMA Sub-System */ ADMA_SPI2_MOD_INT_IRQn = 421, /**< Shared Int Source SPI2_MOD_INT from ADMA Sub-System */ ADMA_SPI3_MOD_INT_IRQn = 422, /**< Shared Int Source SPI3_MOD_INT from ADMA Sub-System */ ADMA_I2C0_MOD_INT_IRQn = 423, /**< Shared Int Source I2C0_MOD_INT from ADMA Sub-System */ ADMA_I2C1_MOD_INT_IRQn = 424, /**< Shared Int Source I2C1_MOD_INT from ADMA Sub-System */ ADMA_I2C2_MOD_INT_IRQn = 425, /**< Shared Int Source I2C2_MOD_INT from ADMA Sub-System */ ADMA_I2C3_MOD_INT_IRQn = 426, /**< Shared Int Source I2C3_MOD_INT from ADMA Sub-System */ ADMA_UART0_MOD_INT_IRQn = 428, /**< Shared Int Source UART0_MOD_INT from ADMA Sub-System */ ADMA_UART1_MOD_INT_IRQn = 429, /**< Shared Int Source UART1_MOD_INT from ADMA Sub-System */ ADMA_UART2_MOD_INT_IRQn = 430, /**< Shared Int Source UART2_MOD_INT from ADMA Sub-System */ ADMA_UART3_MOD_INT_IRQn = 431, /**< Shared Int Source UART3_MOD_INT from ADMA Sub-System */ ADMA_FLEXCAN0_MOD_INT_IRQn = 435, /**< Shared Int Source FLEXCAN0_MOD_INT from ADMA Sub-System */ ADMA_FLEXCAN1_MOD_INT_IRQn = 436, /**< Shared Int Source FLEXCAN1_MOD_INT from ADMA Sub-System */ ADMA_FLEXCAN2_MOD_INT_IRQn = 437, /**< Shared Int Source FLEXCAN2_MOD_INT from ADMA Sub-System */ ADMA_FTM0_MOD_INT_IRQn = 438, /**< Shared Int Source FTM0_MOD_INT from ADMA Sub-System */ ADMA_FTM1_MOD_INT_IRQn = 439, /**< Shared Int Source FTM1_MOD_INT from ADMA Sub-System */ ADMA_ADC0_MOD_INT_IRQn = 440, /**< Shared Int Source ADC0_MOD_INT from ADMA Sub-System */ ADMA_FLEXCAN0_DMA_INT_IRQn = 442, /**< Shared Int Source FLEXCAN0_DMA_INT from ADMA Sub-System */ ADMA_FLEXCAN1_DMA_INT_IRQn = 443, /**< Shared Int Source FLEXCAN1_DMA_INT from ADMA Sub-System */ ADMA_FLEXCAN2_DMA_INT_IRQn = 444, /**< Shared Int Source FLEXCAN2_DMA_INT from ADMA Sub-System */ ADMA_FTM0_DMA_INT_IRQn = 445, /**< Shared Int Source FTM0_DMA_INT from ADMA Sub-System */ ADMA_FTM1_DMA_INT_IRQn = 446, /**< Shared Int Source FTM1_DMA_INT from ADMA Sub-System */ ADMA_ADC0_DMA_INT_IRQn = 447, /**< Shared Int Source ADC0_DMA_INT from ADMA Sub-System */ ADMA_EDMA0_INT_IRQn = 451, /**< Shared Int Source eDMA0_INT from ADMA Sub-System */ ADMA_EDMA0_ERR_INT_IRQn = 452, /**< Shared Int Source eDMA0_ERR_INT from ADMA Sub-System */ ADMA_EDMA1_INT_IRQn = 453, /**< Shared Int Source eDMA1_INT from ADMA Sub-System */ ADMA_EDMA1_ERR_INT_IRQn = 454, /**< Shared Int Source eDMA1_ERR_INT from ADMA Sub-System */ ADMA_ASRC0_INT1_IRQn = 455, /**< Shared Int Source ASRC0_INT1 from ADMA Sub-System */ ADMA_ASRC0_INT2_IRQn = 456, /**< Shared Int Source ASRC0_INT2 from ADMA Sub-System */ ADMA_DMA0_CH0_INT_IRQn = 457, /**< Shared Int Source DMA0_CH0_INT from ADMA Sub-System */ ADMA_DMA0_CH1_INT_IRQn = 458, /**< Shared Int Source DMA0_CH1_INT from ADMA Sub-System */ ADMA_DMA0_CH2_INT_IRQn = 459, /**< Shared Int Source DMA0_CH2_INT from ADMA Sub-System */ ADMA_DMA0_CH3_INT_IRQn = 460, /**< Shared Int Source DMA0_CH3_INT from ADMA Sub-System */ ADMA_DMA0_CH4_INT_IRQn = 461, /**< Shared Int Source DMA0_CH4_INT from ADMA Sub-System */ ADMA_DMA0_CH5_INT_IRQn = 462, /**< Shared Int Source DMA0_CH5_INT from ADMA Sub-System */ ADMA_ASRC1_INT1_IRQn = 463, /**< Shared Int Source ASRC1_INT1 from ADMA Sub-System */ ADMA_ASRC1_INT2_IRQn = 464, /**< Shared Int Source ASRC1_INT2 from ADMA Sub-System */ ADMA_DMA1_CH0_INT_IRQn = 465, /**< Shared Int Source DMA1_CH0_INT from ADMA Sub-System */ ADMA_DMA1_CH1_INT_IRQn = 466, /**< Shared Int Source DMA1_CH1_INT from ADMA Sub-System */ ADMA_DMA1_CH2_INT_IRQn = 467, /**< Shared Int Source DMA1_CH2_INT from ADMA Sub-System */ ADMA_DMA1_CH3_INT_IRQn = 468, /**< Shared Int Source DMA1_CH3_INT from ADMA Sub-System */ ADMA_DMA1_CH4_INT_IRQn = 469, /**< Shared Int Source DMA1_CH4_INT from ADMA Sub-System */ ADMA_DMA1_CH5_INT_IRQn = 470, /**< Shared Int Source DMA1_CH5_INT from ADMA Sub-System */ ADMA_ESAI0_INT_IRQn = 471, /**< Shared Int Source ESAI0_INT from ADMA Sub-System */ ADMA_GPT0_INT_IRQn = 474, /**< Shared Int Source GPT0_INT from ADMA Sub-System */ ADMA_GPT1_INT_IRQn = 475, /**< Shared Int Source GPT1_INT from ADMA Sub-System */ ADMA_GPT2_INT_IRQn = 476, /**< Shared Int Source GPT2_INT from ADMA Sub-System */ ADMA_GPT3_INT_IRQn = 477, /**< Shared Int Source GPT3_INT from ADMA Sub-System */ ADMA_GPT4_INT_IRQn = 478, /**< Shared Int Source GPT4_INT from ADMA Sub-System */ ADMA_GPT5_INT_IRQn = 479, /**< Shared Int Source GPT5_INT from ADMA Sub-System */ ADMA_SAI0_INT_IRQn = 480, /**< Shared Int Source SAI0_INT from ADMA Sub-System */ ADMA_SAI1_INT_IRQn = 481, /**< Shared Int Source SAI1_INT from ADMA Sub-System */ ADMA_SAI2_INT_IRQn = 482, /**< Shared Int Source SAI2_INT from ADMA Sub-System */ ADMA_SAI3_INT_IRQn = 483, /**< Shared Int Source SAI3_INT from ADMA Sub-System */ ADMA_SAI4_INT_IRQn = 486, /**< Shared Int Source SAI4_INT from ADMA Sub-System */ ADMA_SAI5_INT_IRQn = 487, /**< Shared Int Source SAI5_INT from ADMA Sub-System */ ADMA_SPDIF0_RX_INT_IRQn = 488, /**< Shared Int Source SPDIF0_RX_INT from ADMA Sub-System */ ADMA_SPDIF0_TX_INT_IRQn = 489, /**< Shared Int Source SPDIF0_TX_INT from ADMA Sub-System */ ADMA_ESAI0_MOD_INT_IRQn = 492, /**< Shared Int Source ESAI0_MOD_INT from ADMA Sub-System */ ADMA_ESAI0_DMA_INT_IRQn = 493, /**< Shared Int Source ESAI0_DMA_INT from ADMA Sub-System */ ADMA_SPI0_DMA_RX_INT_IRQn = 499, /**< Shared Int Source SPI0_DMA_RX_INT from ADMA Sub-System */ ADMA_SPI0_DMA_TX_INT_IRQn = 500, /**< Shared Int Source SPI0_DMA_TX_INT from ADMA Sub-System */ ADMA_SPI1_DMA_RX_INT_IRQn = 501, /**< Shared Int Source SPI1_DMA_RX_INT from ADMA Sub-System */ ADMA_SPI1_DMA_TX_INT_IRQn = 502, /**< Shared Int Source SPI1_DMA_TX_INT from ADMA Sub-System */ ADMA_SPI2_DMA_RX_INT_IRQn = 503, /**< Shared Int Source SPI2_DMA_RX_INT from ADMA Sub-System */ ADMA_SPI2_DMA_TX_INT_IRQn = 504, /**< Shared Int Source SPI2_DMA_TX_INT from ADMA Sub-System */ ADMA_SPI3_DMA_RX_INT_IRQn = 505, /**< Shared Int Source SPI3_DMA_RX_INT from ADMA Sub-System */ ADMA_SPI3_DMA_TX_INT_IRQn = 506, /**< Shared Int Source SPI3_DMA_TX_INT from ADMA Sub-System */ ADMA_I2C0_DMA_RX_INT_IRQn = 507, /**< Shared Int Source I2C0_DMA_RX_INT from ADMA Sub-System */ ADMA_I2C0_DMA_TX_INT_IRQn = 508, /**< Shared Int Source I2C0_DMA_TX_INT from ADMA Sub-System */ ADMA_I2C1_DMA_RX_INT_IRQn = 509, /**< Shared Int Source I2C1_DMA_RX_INT from ADMA Sub-System */ ADMA_I2C1_DMA_TX_INT_IRQn = 510, /**< Shared Int Source I2C1_DMA_TX_INT from ADMA Sub-System */ ADMA_I2C2_DMA_RX_INT_IRQn = 511, /**< Shared Int Source I2C2_DMA_RX_INT from ADMA Sub-System */ ADMA_I2C2_DMA_TX_INT_IRQn = 512, /**< Shared Int Source I2C2_DMA_TX_INT from ADMA Sub-System */ ADMA_I2C3_DMA_RX_INT_IRQn = 513, /**< Shared Int Source I2C3_DMA_RX_INT from ADMA Sub-System */ ADMA_I2C3_DMA_TX_INT_IRQn = 514, /**< Shared Int Source I2C3_DMA_TX_INT from ADMA Sub-System */ ADMA_UART0_DMA_RX_INT_IRQn = 517, /**< Shared Int Source UART0_DMA_RX_INT from ADMA Sub-System */ ADMA_UART0_DMA_TX_INT_IRQn = 518, /**< Shared Int Source UART0_DMA_TX_INT from ADMA Sub-System */ ADMA_UART1_DMA_RX_INT_IRQn = 519, /**< Shared Int Source UART1_DMA_RX_INT from ADMA Sub-System */ ADMA_UART1_DMA_TX_INT_IRQn = 520, /**< Shared Int Source UART1_DMA_TX_INT from ADMA Sub-System */ ADMA_UART2_DMA_RX_INT_IRQn = 521, /**< Shared Int Source UART2_DMA_RX_INT from ADMA Sub-System */ ADMA_UART2_DMA_TX_INT_IRQn = 522, /**< Shared Int Source UART2_DMA_TX_INT from ADMA Sub-System */ ADMA_UART3_DMA_RX_INT_IRQn = 523, /**< Shared Int Source UART3_DMA_RX_INT from ADMA Sub-System */ ADMA_UART3_DMA_TX_INT_IRQn = 524, /**< Shared Int Source UART3_DMA_TX_INT from ADMA Sub-System */ SECURITY_MU1_A_INT_IRQn = 531, /**< Shared Int Source MU1_A_INT from Security Sub-System */ SECURITY_MU2_A_INT_IRQn = 532, /**< Shared Int Source MU2_A_INT from Security Sub-System */ SECURITY_MU3_A_INT_IRQn = 533, /**< Shared Int Source MU3_A_INT from Security Sub-System */ SECURITY_CAAM_INT0_IRQn = 534, /**< Shared Int Source CAAM_INT0 from Security Sub-System */ SECURITY_CAAM_INT1_IRQn = 535, /**< Shared Int Source CAAM_INT1 from Security Sub-System */ SECURITY_CAAM_INT2_IRQn = 536, /**< Shared Int Source CAAM_INT2 from Security Sub-System */ SECURITY_CAAM_INT3_IRQn = 537, /**< Shared Int Source CAAM_INT3 from Security Sub-System */ SECURITY_CAAM_RTIC_INT_IRQn = 538, /**< Shared Int Source CAAM_RTIC_INT from Security Sub-System */ ADMA_SPDIF0_RX_MOD_INT_IRQn = 539, /**< Shared Int Source SPDIF0_RX_MOD_INT from ADMA Sub-System */ ADMA_SPDIF0_RX_DMA_INT_IRQn = 540, /**< Shared Int Source SPDIF0_RX_DMA_INT from ADMA Sub-System */ ADMA_SPDIF0_TX_MOD_INT_IRQn = 541, /**< Shared Int Source SPDIF0_TX_MOD_INT from ADMA Sub-System */ ADMA_SPDIF0_TX_DMA_INT_IRQn = 542, /**< Shared Int Source SPDIF0_TX_DMA_INT from ADMA Sub-System */ VPU_VPU_INT_0_IRQn = 547, /**< Shared Int Source VPU_INT_0 from VPU Sub-System */ VPU_VPU_INT_1_IRQn = 548, /**< Shared Int Source VPU_INT_1 from VPU Sub-System */ VPU_VPU_INT_2_IRQn = 549, /**< Shared Int Source VPU_INT_2 from VPU Sub-System */ VPU_VPU_INT_3_IRQn = 550, /**< Shared Int Source VPU_INT_3 from VPU Sub-System */ VPU_VPU_INT_4_IRQn = 551, /**< Shared Int Source VPU_INT_4 from VPU Sub-System */ M4_INTMUX_SOURCE_TPM_IRQn = 564, /**< INTMUX Input source: TPM Interrupt */ M4_INTMUX_SOURCE_LPIT_IRQn = 567, /**< INTMUX Input source: LPIT Interrupt */ M4_INTMUX_SOURCE_LPUART_IRQn = 570, /**< INTMUX Input source: LPUART Interrupt */ M4_INTMUX_SOURCE_LPI2C_IRQn = 572, /**< INTMUX Input source: LPI2C Interrupt */ M4_INTMUX_SOURCE_MU0_A3_IRQn = 591, /**< INTMUX Input source: MU0_A3 Interrupt */ M4_INTMUX_SOURCE_MU0_A2_IRQn = 592, /**< INTMUX Input source: MU0_A2 Interrupt */ M4_INTMUX_SOURCE_MU0_A1_IRQn = 593, /**< INTMUX Input source: MU0_A1 Interrupt */ M4_INTMUX_SOURCE_MU0_A0_IRQn = 594 /**< INTMUX Input source: MU0_A0 Interrupt */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Configuration of the Cortex-M4 Processor and Core Peripherals ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals * @{ */ #define __CM4_REV 0x0001 /**< Core revision r0p1 */ #define __MPU_PRESENT 1 /**< MPU present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /**< FPU present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ #include "system_MIMX8UX5_cm4.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #else #pragma push #pragma anon_unions #endif #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ACM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ACM_Peripheral_Access_Layer ACM Peripheral Access Layer * @{ */ /** ACM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[14680064]; __IO uint32_t AUD_CLK0; /**< ACM_AUD_CLK0 Register, offset: 0xE00000 */ uint8_t RESERVED_1[65532]; __IO uint32_t AUD_CLK1; /**< ACM_AUD_CLK1 Register, offset: 0xE10000 */ uint8_t RESERVED_2[65532]; __IO uint32_t MCLKOUT0; /**< ACM_MCLKOUT0 Register, offset: 0xE20000 */ uint8_t RESERVED_3[65532]; __IO uint32_t MCLKOUT1; /**< ACM_MCLKOUT1 Register, offset: 0xE30000 */ uint8_t RESERVED_4[196604]; __IO uint32_t ESAI0_CLK; /**< ACM_ESAI0_CLK Register, offset: 0xE60000 */ uint8_t RESERVED_5[131068]; struct { /* offset: 0xE80000, array step: 0x10000 */ __IO uint32_t GPT_CLK; /**< ACM_GPT_CLK Register, array offset: 0xE80000, array step: 0x10000 */ uint8_t RESERVED_0[65532]; } GPT_CLK[6]; struct { /* offset: 0xEE0000, array step: 0x10000 */ __IO uint32_t SAI_MCLK; /**< ACM_SAI_MCLK Register, array offset: 0xEE0000, array step: 0x10000 */ uint8_t RESERVED_0[65532]; } SAI_MCLK[8]; uint8_t RESERVED_6[262144]; __IO uint32_t SPDIF0_TX_CLK; /**< ACM_SPDIF0_TX_CLK Register, offset: 0xFA0000 */ uint8_t RESERVED_7[131068]; __IO uint32_t MQS_HMCLK_CLK; /**< ACM_MQS_HMCLK_CLK Register, offset: 0xFC0000 */ } ACM_Type; /* ---------------------------------------------------------------------------- -- ACM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ACM_Register_Masks ACM Register Masks * @{ */ /*! @name AUD_CLK0 - ACM_AUD_CLK0 Register */ /*! @{ */ #define ACM_AUD_CLK0_SEL_MASK (0x1FU) #define ACM_AUD_CLK0_SEL_SHIFT (0U) /*! SEL - Select * 0b00000..ADMA_SLSLICE2 * 0b00001..ADMA_SLSLICE3 * 0b00010..EXT_AUD_MCLK0 * 0b00011..EXT_AUD_MCLK1 * 0b00100..ESAI0_RX_CLK * 0b00101..ESAI0_RX_HF_CLKK * 0b00110..ESAI0_TX_CLK * 0b00111..ESAI0_TX_HF_CLK * 0b01000..SPDIF0_RX * 0b01001..SAI0_RX_BCLK * 0b01010..SAI0_TX_BCLK * 0b01011..SAI1_RX_BCLK * 0b01100..SAI1_TX_BCLK * 0b01101..SAI2_RX_BCLK * 0b01110..SAI3_RX_BCLK */ #define ACM_AUD_CLK0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK0_SEL_SHIFT)) & ACM_AUD_CLK0_SEL_MASK) /*! @} */ /*! @name AUD_CLK1 - ACM_AUD_CLK1 Register */ /*! @{ */ #define ACM_AUD_CLK1_SEL_MASK (0x1FU) #define ACM_AUD_CLK1_SEL_SHIFT (0U) /*! SEL - Select * 0b00000..ADMA_SLSLICE2 * 0b00001..ADMA_SLSLICE3 * 0b00010..EXT_AUD_MCLK0 * 0b00011..EXT_AUD_MCLK1 * 0b00100..ESAI0_RX_CLK * 0b00101..ESAI0_RX_HF_CLKK * 0b00110..ESAI0_TX_CLK * 0b00111..ESAI0_TX_HF_CLK * 0b01000..SPDIF0_RX * 0b01001..SAI0_RX_BCLK * 0b01010..SAI0_TX_BCLK * 0b01011..SAI1_RX_BCLK * 0b01100..SAI1_TX_BCLK * 0b01101..SAI2_RX_BCLK * 0b01110..SAI3_RX_BCLK */ #define ACM_AUD_CLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK1_SEL_SHIFT)) & ACM_AUD_CLK1_SEL_MASK) /*! @} */ /*! @name MCLKOUT0 - ACM_MCLKOUT0 Register */ /*! @{ */ #define ACM_MCLKOUT0_SEL_MASK (0x7U) #define ACM_MCLKOUT0_SEL_SHIFT (0U) /*! SEL - Select * 0b000..ADMA_SLSLICE2 * 0b001..ADMA_SLSLICE3 * 0b010..Reserved * 0b011..Reserved * 0b100..SPDIF0_RX * 0b101..Reserved * 0b110..Reserved * 0b111..SAI4_RX_BCLK */ #define ACM_MCLKOUT0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT0_SEL_SHIFT)) & ACM_MCLKOUT0_SEL_MASK) /*! @} */ /*! @name MCLKOUT1 - ACM_MCLKOUT1 Register */ /*! @{ */ #define ACM_MCLKOUT1_SEL_MASK (0x7U) #define ACM_MCLKOUT1_SEL_SHIFT (0U) /*! SEL - Select * 0b000..ADMA_SLSLICE2 * 0b001..ADMA_SLSLICE3 * 0b010..Reserved * 0b011..Reserved * 0b100..SPDIF0_RX * 0b101..Reserved * 0b110..Reserved * 0b111..SAI4_RX_BCLK */ #define ACM_MCLKOUT1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT1_SEL_SHIFT)) & ACM_MCLKOUT1_SEL_MASK) /*! @} */ /*! @name ESAI0_CLK - ACM_ESAI0_CLK Register */ /*! @{ */ #define ACM_ESAI0_CLK_SEL_MASK (0x3U) #define ACM_ESAI0_CLK_SEL_SHIFT (0U) /*! SEL - Select * 0b00..AUD_PLL_DIV_CLK0 * 0b01..AUD_PLL_DIV_CLK1 * 0b10..AUD_CLK0 * 0b11..AUD_CLK1 */ #define ACM_ESAI0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_ESAI0_CLK_SEL_SHIFT)) & ACM_ESAI0_CLK_SEL_MASK) /*! @} */ /*! @name GPT_CLK - ACM_GPT_CLK Register */ /*! @{ */ #define ACM_GPT_CLK_SEL_MASK (0x7U) #define ACM_GPT_CLK_SEL_SHIFT (0U) /*! SEL - Select * 0b000..AUD_PLL_DIV_CLK0 * 0b001..AUD_PLL_DIV_CLK1 * 0b010..AUD_CLK0 * 0b011..AUD_CLK1 * 0b100..24M_REF_CLK */ #define ACM_GPT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT_CLK_SEL_SHIFT)) & ACM_GPT_CLK_SEL_MASK) /*! @} */ /* The count of ACM_GPT_CLK */ #define ACM_GPT_CLK_COUNT (6U) /*! @name SAI_MCLK - ACM_SAI_MCLK Register */ /*! @{ */ #define ACM_SAI_MCLK_SEL_MASK (0x3U) #define ACM_SAI_MCLK_SEL_SHIFT (0U) /*! SEL - Select * 0b00..AUD_PLL_DIV_CLK0 * 0b01..AUD_PLL_DIV_CLK1 * 0b10..AUD_CLK0 * 0b11..AUD_CLK1 */ #define ACM_SAI_MCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI_MCLK_SEL_SHIFT)) & ACM_SAI_MCLK_SEL_MASK) /*! @} */ /* The count of ACM_SAI_MCLK */ #define ACM_SAI_MCLK_COUNT (8U) /*! @name SPDIF0_TX_CLK - ACM_SPDIF0_TX_CLK Register */ /*! @{ */ #define ACM_SPDIF0_TX_CLK_SEL_MASK (0x3U) #define ACM_SPDIF0_TX_CLK_SEL_SHIFT (0U) /*! SEL - Select * 0b00..AUD_PLL_DIV_CLK0 * 0b01..AUD_PLL_DIV_CLK1 * 0b10..AUD_CLK0 * 0b11..AUD_CLK1 */ #define ACM_SPDIF0_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF0_TX_CLK_SEL_SHIFT)) & ACM_SPDIF0_TX_CLK_SEL_MASK) /*! @} */ /*! @name MQS_HMCLK_CLK - ACM_MQS_HMCLK_CLK Register */ /*! @{ */ #define ACM_MQS_HMCLK_CLK_SEL_MASK (0x3U) #define ACM_MQS_HMCLK_CLK_SEL_SHIFT (0U) /*! SEL - Select * 0b00..AUD_PLL_DIV_CLK0 * 0b01..AUD_PLL_DIV_CLK1 * 0b10..AUD_CLK0 * 0b11..AUD_CLK1 */ #define ACM_MQS_HMCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MQS_HMCLK_CLK_SEL_SHIFT)) & ACM_MQS_HMCLK_CLK_SEL_MASK) /*! @} */ /*! * @} */ /* end of group ACM_Register_Masks */ /* ACM - Peripheral instance base addresses */ /** Peripheral ADMA__ACM base address */ #define ADMA__ACM_BASE (0x59000000u) /** Peripheral ADMA__ACM base pointer */ #define ADMA__ACM ((ACM_Type *)ADMA__ACM_BASE) /** Array initializer of ACM peripheral base addresses */ #define ACM_BASE_ADDRS { ADMA__ACM_BASE } /** Array initializer of ACM peripheral base pointers */ #define ACM_BASE_PTRS { ADMA__ACM } /*! * @} */ /* end of group ACM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */ __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ uint8_t RESERVED_2[136]; __IO uint32_t TCTRL[8]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_3[32]; struct { /* offset: 0x100, array step: 0x8 */ __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ } CMD[15]; uint8_t RESERVED_4[136]; __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_5[240]; __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */ } ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define ADC_VERID_RES_MASK (0x1U) #define ADC_VERID_RES_SHIFT (0U) /*! RES - Resolution * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. * 0b1..Up to 16-bit differential/15-bit single ended resolution supported. */ #define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) #define ADC_VERID_DIFFEN_MASK (0x2U) #define ADC_VERID_DIFFEN_SHIFT (1U) /*! DIFFEN - Differential Supported * 0b0..Differential operation not supported. * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented. */ #define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) #define ADC_VERID_MVI_MASK (0x8U) #define ADC_VERID_MVI_SHIFT (3U) /*! MVI - Multi Vref Implemented * 0b0..Single voltage reference high (VREFH) input supported. * 0b1..Multiple voltage reference high (VREFH) inputs supported. */ #define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) #define ADC_VERID_CSW_MASK (0x70U) #define ADC_VERID_CSW_SHIFT (4U) /*! CSW - Channel Scale Width * 0b000..Channel scaling not supported. * 0b001..Channel scaling supported. 1-bit CSCALE control field. * 0b110..Channel scaling supported. 6-bit CSCALE control field. */ #define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) #define ADC_VERID_VR1RNGI_MASK (0x100U) #define ADC_VERID_VR1RNGI_SHIFT (8U) /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. * 0b1..Range control required. CFG[VREF1RNG] is implemented. */ #define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) #define ADC_VERID_IADCKI_MASK (0x200U) #define ADC_VERID_IADCKI_SHIFT (9U) /*! IADCKI - Internal ADC Clock implemented * 0b0..Internal clock source not implemented. * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. */ #define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) #define ADC_VERID_CALOFSI_MASK (0x400U) #define ADC_VERID_CALOFSI_SHIFT (10U) /*! CALOFSI - Calibration Offset Function Implemented * 0b0..Offset calibration and offset trimming not implemented. * 0b1..Offset calibration and offset trimming implemented. */ #define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) #define ADC_VERID_MINOR_MASK (0xFF0000U) #define ADC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) #define ADC_VERID_MAJOR_MASK (0xFF000000U) #define ADC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define ADC_PARAM_TRIG_NUM_MASK (0xFFU) #define ADC_PARAM_TRIG_NUM_SHIFT (0U) /*! TRIG_NUM - Trigger Number */ #define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) #define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) #define ADC_PARAM_FIFOSIZE_SHIFT (8U) /*! FIFOSIZE - Result FIFO Depth * 0b00000001..Result FIFO depth = 1 dataword. * 0b00000100..Result FIFO depth = 4 datawords. * 0b00001000..Result FIFO depth = 8 datawords. * 0b00010000..Result FIFO depth = 16 datawords. * 0b00100000..Result FIFO depth = 32 datawords. * 0b01000000..Result FIFO depth = 64 datawords. */ #define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) #define ADC_PARAM_CV_NUM_MASK (0xFF0000U) #define ADC_PARAM_CV_NUM_SHIFT (16U) /*! CV_NUM - Compare Value Number */ #define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) #define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) #define ADC_PARAM_CMD_NUM_SHIFT (24U) /*! CMD_NUM - Command Buffer Number */ #define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) /*! @} */ /*! @name CTRL - ADC Control Register */ /*! @{ */ #define ADC_CTRL_ADCEN_MASK (0x1U) #define ADC_CTRL_ADCEN_SHIFT (0U) /*! ADCEN - ADC Enable * 0b0..ADC is disabled. * 0b1..ADC is enabled. */ #define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) #define ADC_CTRL_RST_MASK (0x2U) #define ADC_CTRL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..ADC logic is not reset. * 0b1..ADC logic is reset. */ #define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) #define ADC_CTRL_DOZEN_MASK (0x4U) #define ADC_CTRL_DOZEN_SHIFT (2U) /*! DOZEN - Doze Enable * 0b0..ADC is enabled in Doze mode. * 0b1..ADC is disabled in Doze mode. */ #define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) #define ADC_CTRL_RSTFIFO_MASK (0x100U) #define ADC_CTRL_RSTFIFO_SHIFT (8U) /*! RSTFIFO - Reset FIFO * 0b0..No effect. * 0b1..FIFO is reset. */ #define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK) /*! @} */ /*! @name STAT - ADC Status Register */ /*! @{ */ #define ADC_STAT_RDY_MASK (0x1U) #define ADC_STAT_RDY_SHIFT (0U) /*! RDY - Result FIFO Ready Flag * 0b0..Result FIFO data level not above watermark level. * 0b1..Result FIFO holding data above watermark level. */ #define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK) #define ADC_STAT_FOF_MASK (0x2U) #define ADC_STAT_FOF_SHIFT (1U) /*! FOF - Result FIFO Overflow Flag * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared. * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared. */ #define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK) #define ADC_STAT_ADC_ACTIVE_MASK (0x100U) #define ADC_STAT_ADC_ACTIVE_SHIFT (8U) /*! ADC_ACTIVE - ADC Active * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. */ #define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) #define ADC_STAT_TRGACT_MASK (0x70000U) #define ADC_STAT_TRGACT_SHIFT (16U) /*! TRGACT - Trigger Active * 0b000..Command (sequence) associated with Trigger 0 currently being executed. * 0b001..Command (sequence) associated with Trigger 1 currently being executed. * 0b010..Command (sequence) associated with Trigger 2 currently being executed. * 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed. */ #define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) #define ADC_STAT_CMDACT_MASK (0xF000000U) #define ADC_STAT_CMDACT_SHIFT (24U) /*! CMDACT - Command Active * 0b0000..No command is currently in progress. * 0b0001..Command 1 currently being executed. * 0b0010..Command 2 currently being executed. * 0b0011-0b1111..Associated command number is currently being executed. */ #define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) /*! @} */ /*! @name IE - Interrupt Enable Register */ /*! @{ */ #define ADC_IE_FWMIE_MASK (0x1U) #define ADC_IE_FWMIE_SHIFT (0U) /*! FWMIE - FIFO Watermark Interrupt Enable * 0b0..FIFO watermark interrupts are not enabled. * 0b1..FIFO watermark interrupts are enabled. */ #define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK) #define ADC_IE_FOFIE_MASK (0x2U) #define ADC_IE_FOFIE_SHIFT (1U) /*! FOFIE - Result FIFO Overflow Interrupt Enable * 0b0..FIFO overflow interrupts are not enabled. * 0b1..FIFO overflow interrupts are enabled. */ #define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK) /*! @} */ /*! @name DE - DMA Enable Register */ /*! @{ */ #define ADC_DE_FWMDE_MASK (0x1U) #define ADC_DE_FWMDE_SHIFT (0U) /*! FWMDE - FIFO Watermark DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK) /*! @} */ /*! @name CFG - ADC Configuration Register */ /*! @{ */ #define ADC_CFG_TPRICTRL_MASK (0x1U) #define ADC_CFG_TPRICTRL_SHIFT (0U) /*! TPRICTRL - ADC trigger priority control * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and * the new command specified by the trigger is started. * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed * (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority * trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true * conversion. */ #define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) #define ADC_CFG_PWRSEL_MASK (0x30U) #define ADC_CFG_PWRSEL_SHIFT (4U) /*! PWRSEL - Power Configuration Select * 0b00..Level 1 (Lowest power setting) * 0b01..Level 2 * 0b10..Level 3 * 0b11..Level 4 (Highest power setting) */ #define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) #define ADC_CFG_REFSEL_MASK (0xC0U) #define ADC_CFG_REFSEL_SHIFT (6U) /*! REFSEL - Voltage Reference Selection * 0b00..(Default) Option 1 setting. * 0b01..Option 2 setting. * 0b10..Option 3 setting. * 0b11..Reserved */ #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) #define ADC_CFG_PUDLY_MASK (0xFF0000U) #define ADC_CFG_PUDLY_SHIFT (16U) /*! PUDLY - Power Up Delay */ #define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) #define ADC_CFG_PWREN_MASK (0x10000000U) #define ADC_CFG_PWREN_SHIFT (28U) /*! PWREN - ADC Analog Pre-Enable * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost * of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any * detected trigger does not begin ADC operation until the power up delay time has passed. */ #define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) /*! @} */ /*! @name PAUSE - ADC Pause Register */ /*! @{ */ #define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) #define ADC_PAUSE_PAUSEDLY_SHIFT (0U) /*! PAUSEDLY - Pause Delay */ #define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) #define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) #define ADC_PAUSE_PAUSEEN_SHIFT (31U) /*! PAUSEEN - PAUSE Option Enable * 0b0..Pause operation disabled * 0b1..Pause operation enabled */ #define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) /*! @} */ /*! @name FCTRL - ADC FIFO Control Register */ /*! @{ */ #define ADC_FCTRL_FCOUNT_MASK (0x1FU) #define ADC_FCTRL_FCOUNT_SHIFT (0U) /*! FCOUNT - Result FIFO counter */ #define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) #define ADC_FCTRL_FWMARK_MASK (0xF0000U) #define ADC_FCTRL_FWMARK_SHIFT (16U) /*! FWMARK - Watermark level selection */ #define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) /*! @} */ /*! @name SWTRIG - Software Trigger Register */ /*! @{ */ #define ADC_SWTRIG_SWT0_MASK (0x1U) #define ADC_SWTRIG_SWT0_SHIFT (0U) /*! SWT0 - Software trigger 0 event * 0b0..No trigger 0 event generated. * 0b1..Trigger 0 event generated. */ #define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) #define ADC_SWTRIG_SWT1_MASK (0x2U) #define ADC_SWTRIG_SWT1_SHIFT (1U) /*! SWT1 - Software trigger 1 event * 0b0..No trigger 1 event generated. * 0b1..Trigger 1 event generated. */ #define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) #define ADC_SWTRIG_SWT2_MASK (0x4U) #define ADC_SWTRIG_SWT2_SHIFT (2U) /*! SWT2 - Software trigger 2 event * 0b0..No trigger 2 event generated. * 0b1..Trigger 2 event generated. */ #define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) #define ADC_SWTRIG_SWT3_MASK (0x8U) #define ADC_SWTRIG_SWT3_SHIFT (3U) /*! SWT3 - Software trigger 3 event * 0b0..No trigger 3 event generated. * 0b1..Trigger 3 event generated. */ #define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) #define ADC_SWTRIG_SWT4_MASK (0x10U) #define ADC_SWTRIG_SWT4_SHIFT (4U) /*! SWT4 - Software trigger 4 event * 0b0..No trigger 4 event generated. * 0b1..Trigger 4 event generated. */ #define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) #define ADC_SWTRIG_SWT5_MASK (0x20U) #define ADC_SWTRIG_SWT5_SHIFT (5U) /*! SWT5 - Software trigger 5 event * 0b0..No trigger 5 event generated. * 0b1..Trigger 5 event generated. */ #define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) #define ADC_SWTRIG_SWT6_MASK (0x40U) #define ADC_SWTRIG_SWT6_SHIFT (6U) /*! SWT6 - Software trigger 6 event * 0b0..No trigger 6 event generated. * 0b1..Trigger 6 event generated. */ #define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) #define ADC_SWTRIG_SWT7_MASK (0x80U) #define ADC_SWTRIG_SWT7_SHIFT (7U) /*! SWT7 - Software trigger 7 event * 0b0..No trigger 7 event generated. * 0b1..Trigger 7 event generated. */ #define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) /*! @} */ /*! @name TCTRL - Trigger Control Register */ /*! @{ */ #define ADC_TCTRL_HTEN_MASK (0x1U) #define ADC_TCTRL_HTEN_SHIFT (0U) /*! HTEN - Trigger enable * 0b0..Hardware trigger source disabled * 0b1..Hardware trigger source enabled */ #define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) #define ADC_TCTRL_TPRI_MASK (0x700U) #define ADC_TCTRL_TPRI_SHIFT (8U) /*! TPRI - Trigger priority setting * 0b000..Set to highest priority, Level 1 * 0b001-0b110..Set to corresponding priority level * 0b111..Set to lowest priority, Level 8 */ #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) #define ADC_TCTRL_TDLY_MASK (0xF0000U) #define ADC_TCTRL_TDLY_SHIFT (16U) /*! TDLY - Trigger delay select */ #define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) #define ADC_TCTRL_TCMD_MASK (0xF000000U) #define ADC_TCTRL_TCMD_SHIFT (24U) /*! TCMD - Trigger command select * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. * 0b0001..CMD1 is executed * 0b0010-0b1110..Corresponding CMD is executed * 0b1111..CMD15 is executed */ #define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) /*! @} */ /* The count of ADC_TCTRL */ #define ADC_TCTRL_COUNT (8U) /*! @name CMDL - ADC Command Low Buffer Register */ /*! @{ */ #define ADC_CMDL_ADCH_MASK (0x1FU) #define ADC_CMDL_ADCH_SHIFT (0U) /*! ADCH - Input channel select * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. */ #define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) #define ADC_CMDL_ABSEL_MASK (0x20U) #define ADC_CMDL_ABSEL_SHIFT (5U) /*! ABSEL - A-side vs. B-side Select * 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). */ #define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK) #define ADC_CMDL_DIFF_MASK (0x40U) #define ADC_CMDL_DIFF_SHIFT (6U) /*! DIFF - Differential Mode Enable * 0b0..Single-ended mode. * 0b1..Differential mode. */ #define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK) #define ADC_CMDL_CSCALE_MASK (0x2000U) #define ADC_CMDL_CSCALE_SHIFT (13U) /*! CSCALE - Channel Scale * 0b0..Scale selected analog channel (Factor of 30/64) * 0b1..(Default) Full scale (Factor of 1) */ #define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK) /*! @} */ /* The count of ADC_CMDL */ #define ADC_CMDL_COUNT (15U) /*! @name CMDH - ADC Command High Buffer Register */ /*! @{ */ #define ADC_CMDH_CMPEN_MASK (0x3U) #define ADC_CMDH_CMPEN_SHIFT (0U) /*! CMPEN - Compare Function Enable * 0b00..Compare disabled. * 0b01..Reserved * 0b10..Compare enabled. Store on true. * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. */ #define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) #define ADC_CMDH_LWI_MASK (0x80U) #define ADC_CMDH_LWI_SHIFT (7U) /*! LWI - Loop with Increment * 0b0..Auto channel increment disabled * 0b1..Auto channel increment enabled */ #define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) #define ADC_CMDH_STS_MASK (0x700U) #define ADC_CMDH_STS_SHIFT (8U) /*! STS - Sample Time Select * 0b000..Minimum sample time of 3 ADCK cycles. * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. */ #define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) #define ADC_CMDH_AVGS_MASK (0x7000U) #define ADC_CMDH_AVGS_SHIFT (12U) /*! AVGS - Hardware Average Select * 0b000..Single conversion. * 0b001..2 conversions averaged. * 0b010..4 conversions averaged. * 0b011..8 conversions averaged. * 0b100..16 conversions averaged. * 0b101..32 conversions averaged. * 0b110..64 conversions averaged. * 0b111..128 conversions averaged. */ #define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) #define ADC_CMDH_LOOP_MASK (0xF0000U) #define ADC_CMDH_LOOP_SHIFT (16U) /*! LOOP - Loop Count Select * 0b0000..Looping not enabled. Command executes 1 time. * 0b0001..Loop 1 time. Command executes 2 times. * 0b0010..Loop 2 times. Command executes 3 times. * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. * 0b1111..Loop 15 times. Command executes 16 times. */ #define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) #define ADC_CMDH_NEXT_MASK (0xF000000U) #define ADC_CMDH_NEXT_SHIFT (24U) /*! NEXT - Next Command Select * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority * trigger pending, begin command associated with lower priority trigger. * 0b0001..Select CMD1 command buffer register as next command. * 0b0010-0b1110..Select corresponding CMD command buffer register as next command * 0b1111..Select CMD15 command buffer register as next command. */ #define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) /*! @} */ /* The count of ADC_CMDH */ #define ADC_CMDH_COUNT (15U) /*! @name CV - Compare Value Register */ /*! @{ */ #define ADC_CV_CVL_MASK (0xFFFFU) #define ADC_CV_CVL_SHIFT (0U) /*! CVL - Compare Value Low. */ #define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) #define ADC_CV_CVH_MASK (0xFFFF0000U) #define ADC_CV_CVH_SHIFT (16U) /*! CVH - Compare Value High. */ #define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) /*! @} */ /* The count of ADC_CV */ #define ADC_CV_COUNT (4U) /*! @name RESFIFO - ADC Data Result FIFO Register */ /*! @{ */ #define ADC_RESFIFO_D_MASK (0xFFFFU) #define ADC_RESFIFO_D_SHIFT (0U) /*! D - Data result */ #define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) #define ADC_RESFIFO_TSRC_MASK (0x70000U) #define ADC_RESFIFO_TSRC_SHIFT (16U) /*! TSRC - Trigger Source * 0b000..Trigger source 0 initiated this conversion. * 0b001..Trigger source 1 initiated this conversion. * 0b010-0b110..Corresponding trigger source initiated this conversion. * 0b111..Trigger source 7 initiated this conversion. */ #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) #define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) #define ADC_RESFIFO_LOOPCNT_SHIFT (20U) /*! LOOPCNT - Loop count value * 0b0000..Result is from initial conversion in command. * 0b0001..Result is from second conversion in command. * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. * 0b1111..Result is from 16th conversion in command. */ #define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) #define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) #define ADC_RESFIFO_CMDSRC_SHIFT (24U) /*! CMDSRC - Command Buffer Source * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. * 0b0001..CMD1 buffer used as control settings for this conversion. * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. * 0b1111..CMD15 buffer used as control settings for this conversion. */ #define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) #define ADC_RESFIFO_VALID_MASK (0x80000000U) #define ADC_RESFIFO_VALID_SHIFT (31U) /*! VALID - FIFO entry is valid * 0b0..FIFO is empty. Discard any read from RESFIFO. * 0b1..FIFO record read from RESFIFO is valid. */ #define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) /*! @} */ /*! * @} */ /* end of group ADC_Register_Masks */ /* ADC - Peripheral instance base addresses */ /** Peripheral ADMA__ADC0 base address */ #define ADMA__ADC0_BASE (0x5A880000u) /** Peripheral ADMA__ADC0 base pointer */ #define ADMA__ADC0 ((ADC_Type *)ADMA__ADC0_BASE) /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { ADMA__ADC0_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADMA__ADC0 } /** Interrupt vectors for the ADC peripheral type */ #define ADC_IRQS { ADMA_ADC0_INT_IRQn } /*! * @} */ /* end of group ADC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- APBH Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer * @{ */ /** APBH - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */ __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */ __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */ __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */ } CTRL0; struct { /* offset: 0x10 */ __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */ __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */ __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */ __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */ } CTRL1; struct { /* offset: 0x20 */ __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */ __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */ __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */ __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */ } CTRL2; struct { /* offset: 0x30 */ __IO uint32_t RW; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */ __IO uint32_t SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */ __IO uint32_t CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */ __IO uint32_t TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */ } CHANNEL_CTRL; uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */ uint8_t RESERVED_0[12]; __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */ uint8_t RESERVED_1[12]; __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */ uint8_t RESERVED_2[156]; struct { /* offset: 0x100, array step: 0x70 */ __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */ uint8_t RESERVED_0[12]; __IO uint32_t CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */ uint8_t RESERVED_1[12]; __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */ uint8_t RESERVED_2[12]; __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */ uint8_t RESERVED_3[12]; __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */ uint8_t RESERVED_4[12]; __I uint32_t CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */ uint8_t RESERVED_5[12]; __I uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */ uint8_t RESERVED_6[12]; } CH_CFGn[16]; __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ } APBH_Type; /* ---------------------------------------------------------------------------- -- APBH Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup APBH_Register_Masks APBH Register Masks * @{ */ /*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */ /*! @{ */ #define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU) #define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U) /*! CLKGATE_CHANNEL - CLKGATE_CHANNEL * 0b0000000000000001.. * 0b0000000000000010.. * 0b0000000000000100.. * 0b0000000000001000.. * 0b0000000000010000.. * 0b0000000000100000.. * 0b0000000001000000.. * 0b0000000010000000.. * 0b0000000100000000.. */ #define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK) #define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U) #define APBH_CTRL0_APB_BURST_EN_SHIFT (28U) /*! APB_BURST_EN - APB_BURST_EN */ #define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK) #define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U) #define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U) /*! AHB_BURST8_EN - AHB_BURST8_EN */ #define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK) #define APBH_CTRL0_CLKGATE_MASK (0x40000000U) #define APBH_CTRL0_CLKGATE_SHIFT (30U) /*! CLKGATE - CLKGATE */ #define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK) #define APBH_CTRL0_SFTRST_MASK (0x80000000U) #define APBH_CTRL0_SFTRST_SHIFT (31U) /*! SFTRST - SFTRST */ #define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK) /*! @} */ /*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */ /*! @{ */ #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U) /*! CH0_CMDCMPLT_IRQ - CH0_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U) /*! CH1_CMDCMPLT_IRQ - CH1_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U) /*! CH2_CMDCMPLT_IRQ - CH2_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U) /*! CH3_CMDCMPLT_IRQ - CH3_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U) /*! CH4_CMDCMPLT_IRQ - CH4_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U) /*! CH5_CMDCMPLT_IRQ - CH5_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U) /*! CH6_CMDCMPLT_IRQ - CH6_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U) /*! CH7_CMDCMPLT_IRQ - CH7_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U) /*! CH8_CMDCMPLT_IRQ - CH8_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U) /*! CH9_CMDCMPLT_IRQ - CH9_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U) /*! CH10_CMDCMPLT_IRQ - CH10_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U) /*! CH11_CMDCMPLT_IRQ - CH11_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U) /*! CH12_CMDCMPLT_IRQ - CH12_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U) /*! CH13_CMDCMPLT_IRQ - CH13_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U) /*! CH14_CMDCMPLT_IRQ - CH14_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U) /*! CH15_CMDCMPLT_IRQ - CH15_CMDCMPLT_IRQ */ #define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) /*! CH0_CMDCMPLT_IRQ_EN - CH0_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) /*! CH1_CMDCMPLT_IRQ_EN - CH1_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) /*! CH2_CMDCMPLT_IRQ_EN - CH2_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) /*! CH3_CMDCMPLT_IRQ_EN - CH3_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) /*! CH4_CMDCMPLT_IRQ_EN - CH4_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) /*! CH5_CMDCMPLT_IRQ_EN - CH5_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) /*! CH6_CMDCMPLT_IRQ_EN - CH6_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) /*! CH7_CMDCMPLT_IRQ_EN - CH7_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) /*! CH8_CMDCMPLT_IRQ_EN - CH8_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) /*! CH9_CMDCMPLT_IRQ_EN - CH9_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) /*! CH10_CMDCMPLT_IRQ_EN - CH10_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) /*! CH11_CMDCMPLT_IRQ_EN - CH11_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) /*! CH12_CMDCMPLT_IRQ_EN - CH12_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) /*! CH13_CMDCMPLT_IRQ_EN - CH13_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) /*! CH14_CMDCMPLT_IRQ_EN - CH14_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) /*! CH15_CMDCMPLT_IRQ_EN - CH15_CMDCMPLT_IRQ_EN */ #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK) /*! @} */ /*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */ /*! @{ */ #define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U) #define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U) /*! CH0_ERROR_IRQ - CH0_ERROR_IRQ */ #define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK) #define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U) #define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U) /*! CH1_ERROR_IRQ - CH1_ERROR_IRQ */ #define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK) #define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U) #define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U) /*! CH2_ERROR_IRQ - CH2_ERROR_IRQ */ #define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK) #define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U) #define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U) /*! CH3_ERROR_IRQ - CH3_ERROR_IRQ */ #define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK) #define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U) #define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U) /*! CH4_ERROR_IRQ - CH4_ERROR_IRQ */ #define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK) #define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U) #define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U) /*! CH5_ERROR_IRQ - CH5_ERROR_IRQ */ #define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK) #define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U) #define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U) /*! CH6_ERROR_IRQ - CH6_ERROR_IRQ */ #define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK) #define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U) #define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U) /*! CH7_ERROR_IRQ - CH7_ERROR_IRQ */ #define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK) #define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U) #define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U) /*! CH8_ERROR_IRQ - CH8_ERROR_IRQ */ #define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK) #define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U) #define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U) /*! CH9_ERROR_IRQ - CH9_ERROR_IRQ */ #define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK) #define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U) #define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U) /*! CH10_ERROR_IRQ - CH10_ERROR_IRQ */ #define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK) #define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U) #define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U) /*! CH11_ERROR_IRQ - CH11_ERROR_IRQ */ #define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK) #define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U) #define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U) /*! CH12_ERROR_IRQ - CH12_ERROR_IRQ */ #define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK) #define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U) #define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U) /*! CH13_ERROR_IRQ - CH13_ERROR_IRQ */ #define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK) #define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U) #define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U) /*! CH14_ERROR_IRQ - CH14_ERROR_IRQ */ #define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK) #define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U) #define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U) /*! CH15_ERROR_IRQ - CH15_ERROR_IRQ */ #define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK) #define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U) #define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U) /*! CH0_ERROR_STATUS - CH0_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK) #define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U) #define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U) /*! CH1_ERROR_STATUS - CH1_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK) #define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U) #define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U) /*! CH2_ERROR_STATUS - CH2_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK) #define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U) #define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U) /*! CH3_ERROR_STATUS - CH3_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK) #define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U) #define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U) /*! CH4_ERROR_STATUS - CH4_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK) #define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U) #define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U) /*! CH5_ERROR_STATUS - CH5_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK) #define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U) #define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U) /*! CH6_ERROR_STATUS - CH6_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK) #define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U) #define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U) /*! CH7_ERROR_STATUS - CH7_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK) #define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U) #define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U) /*! CH8_ERROR_STATUS - CH8_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK) #define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U) #define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U) /*! CH9_ERROR_STATUS - CH9_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK) #define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U) #define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U) /*! CH10_ERROR_STATUS - CH10_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK) #define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U) #define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U) /*! CH11_ERROR_STATUS - CH11_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK) #define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U) #define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U) /*! CH12_ERROR_STATUS - CH12_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK) #define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U) #define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U) /*! CH13_ERROR_STATUS - CH13_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK) #define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U) #define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U) /*! CH14_ERROR_STATUS - CH14_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK) #define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U) #define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U) /*! CH15_ERROR_STATUS - CH15_ERROR_STATUS * 0b0..An early termination from the device causes error IRQ. * 0b1..An AHB bus error causes error IRQ. */ #define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK) /*! @} */ /*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */ /*! @{ */ #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU) #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U) /*! FREEZE_CHANNEL - FREEZE_CHANNEL * 0b0000000000000001.. * 0b0000000000000010.. * 0b0000000000000100.. * 0b0000000000001000.. * 0b0000000000010000.. * 0b0000000000100000.. * 0b0000000001000000.. * 0b0000000010000000.. * 0b0000000100000000.. */ #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U) /*! RESET_CHANNEL - RESET_CHANNEL * 0b0000000000000001.. * 0b0000000000000010.. * 0b0000000000000100.. * 0b0000000000001000.. * 0b0000000000010000.. * 0b0000000000100000.. * 0b0000000001000000.. * 0b0000000010000000.. * 0b0000000100000000.. */ #define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK) /*! @} */ /*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */ /*! @{ */ #define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U) #define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U) /*! CH0 - CH0 */ #define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK) #define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU) #define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U) /*! CH1 - CH1 */ #define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK) #define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U) #define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U) /*! CH2 - CH2 */ #define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK) #define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U) #define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U) /*! CH3 - CH3 */ #define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK) #define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U) #define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U) /*! CH4 - CH4 */ #define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK) #define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U) #define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U) /*! CH5 - CH5 */ #define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK) #define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U) #define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U) /*! CH6 - CH6 */ #define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK) #define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U) #define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U) /*! CH7 - CH7 */ #define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK) #define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U) #define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U) /*! CH8 - CH8 * 0b00.. * 0b01.. * 0b10.. */ #define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK) /*! @} */ /*! @name DEBUG - AHB to APBH DMA Debug Register */ /*! @{ */ #define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U) #define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U) /*! GPMI_ONE_FIFO - GPMI_ONE_FIFO */ #define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK) /*! @} */ /*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */ /*! @{ */ #define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U) /*! CMD_ADDR - CMD_ADDR */ #define APBH_CH_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK) /*! @} */ /* The count of APBH_CH_CURCMDAR */ #define APBH_CH_CURCMDAR_COUNT (16U) /*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ /*! @{ */ #define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) #define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U) /*! CMD_ADDR - CMD_ADDR */ #define APBH_CH_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK) /*! @} */ /* The count of APBH_CH_NXTCMDAR */ #define APBH_CH_NXTCMDAR_COUNT (16U) /*! @name CH_CMD - APBH DMA Channel n Command Register */ /*! @{ */ #define APBH_CH_CMD_COMMAND_MASK (0x3U) #define APBH_CH_CMD_COMMAND_SHIFT (0U) /*! COMMAND - COMMAND * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer. * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain * pointer if the peripheral sense line is false. */ #define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK) #define APBH_CH_CMD_CHAIN_MASK (0x4U) #define APBH_CH_CMD_CHAIN_SHIFT (2U) /*! CHAIN - CHAIN */ #define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK) #define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U) #define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U) /*! IRQONCMPLT - IRQONCMPLT */ #define APBH_CH_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK) #define APBH_CH_CMD_NANDLOCK_MASK (0x10U) #define APBH_CH_CMD_NANDLOCK_SHIFT (4U) /*! NANDLOCK - NANDLOCK */ #define APBH_CH_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK) #define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U) #define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U) /*! NANDWAIT4READY - NANDWAIT4READY */ #define APBH_CH_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK) #define APBH_CH_CMD_SEMAPHORE_MASK (0x40U) #define APBH_CH_CMD_SEMAPHORE_SHIFT (6U) /*! SEMAPHORE - SEMAPHORE */ #define APBH_CH_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK) #define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U) #define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U) /*! WAIT4ENDCMD - WAIT4ENDCMD */ #define APBH_CH_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK) #define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U) #define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U) /*! HALTONTERMINATE - HALTONTERMINATE */ #define APBH_CH_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK) #define APBH_CH_CMD_CMDWORDS_MASK (0xF000U) #define APBH_CH_CMD_CMDWORDS_SHIFT (12U) /*! CMDWORDS - CMDWORDS */ #define APBH_CH_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK) #define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U) #define APBH_CH_CMD_XFER_COUNT_SHIFT (16U) /*! XFER_COUNT - XFER_COUNT */ #define APBH_CH_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK) /*! @} */ /* The count of APBH_CH_CMD */ #define APBH_CH_CMD_COUNT (16U) /*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */ /*! @{ */ #define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU) #define APBH_CH_BAR_ADDRESS_SHIFT (0U) /*! ADDRESS - ADDRESS */ #define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK) /*! @} */ /* The count of APBH_CH_BAR */ #define APBH_CH_BAR_COUNT (16U) /*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */ /*! @{ */ #define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU) #define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U) /*! INCREMENT_SEMA - INCREMENT_SEMA */ #define APBH_CH_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK) #define APBH_CH_SEMA_PHORE_MASK (0xFF0000U) #define APBH_CH_SEMA_PHORE_SHIFT (16U) /*! PHORE - PHORE */ #define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK) /*! @} */ /* The count of APBH_CH_SEMA */ #define APBH_CH_SEMA_COUNT (16U) /*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU) #define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U) /*! STATEMACHINE - STATEMACHINE * 0b00000..This is the idle state of the DMA state machine. * 0b00001..State in which the DMA is waiting to receive the first word of a command. * 0b00010..State in which the DMA is waiting to receive the third word of a command. * 0b00011..State in which the DMA is waiting to receive the second word of a command. * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly. * 0b00101..The state machine waits in this state for the PIO APB cycles to complete. * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the * PIO words when PIO count is greater than 1. * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers. * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and * effectively halts. A channel reset is required to exit this state * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts. * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device * indicates that the external device is ready. */ #define APBH_CH_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK) #define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) #define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U) /*! WR_FIFO_FULL - WR_FIFO_FULL */ #define APBH_CH_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK) #define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) #define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) /*! WR_FIFO_EMPTY - WR_FIFO_EMPTY */ #define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK) #define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) #define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U) /*! RD_FIFO_FULL - RD_FIFO_FULL */ #define APBH_CH_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK) #define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) #define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) /*! RD_FIFO_EMPTY - RD_FIFO_EMPTY */ #define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK) #define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) #define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) /*! NEXTCMDADDRVALID - NEXTCMDADDRVALID */ #define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK) #define APBH_CH_DEBUG1_READY_MASK (0x4000000U) #define APBH_CH_DEBUG1_READY_SHIFT (26U) /*! READY - READY */ #define APBH_CH_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK) #define APBH_CH_DEBUG1_END_MASK (0x10000000U) #define APBH_CH_DEBUG1_END_SHIFT (28U) /*! END - END */ #define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK) #define APBH_CH_DEBUG1_KICK_MASK (0x20000000U) #define APBH_CH_DEBUG1_KICK_SHIFT (29U) /*! KICK - KICK */ #define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK) #define APBH_CH_DEBUG1_BURST_MASK (0x40000000U) #define APBH_CH_DEBUG1_BURST_SHIFT (30U) /*! BURST - BURST */ #define APBH_CH_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK) #define APBH_CH_DEBUG1_REQ_MASK (0x80000000U) #define APBH_CH_DEBUG1_REQ_SHIFT (31U) /*! REQ - REQ */ #define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK) /*! @} */ /* The count of APBH_CH_DEBUG1 */ #define APBH_CH_DEBUG1_COUNT (16U) /*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ /*! @{ */ #define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU) #define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U) /*! AHB_BYTES - AHB_BYTES */ #define APBH_CH_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK) #define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) #define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U) /*! APB_BYTES - APB_BYTES */ #define APBH_CH_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK) /*! @} */ /* The count of APBH_CH_DEBUG2 */ #define APBH_CH_DEBUG2_COUNT (16U) /*! @name VERSION - APBH Bridge Version Register */ /*! @{ */ #define APBH_VERSION_STEP_MASK (0xFFFFU) #define APBH_VERSION_STEP_SHIFT (0U) /*! STEP - STEP */ #define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK) #define APBH_VERSION_MINOR_MASK (0xFF0000U) #define APBH_VERSION_MINOR_SHIFT (16U) /*! MINOR - MINOR */ #define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK) #define APBH_VERSION_MAJOR_MASK (0xFF000000U) #define APBH_VERSION_MAJOR_SHIFT (24U) /*! MAJOR - MAJOR */ #define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK) /*! @} */ /*! * @} */ /* end of group APBH_Register_Masks */ /* APBH - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__APBH base address */ #define CONNECTIVITY__APBH_BASE (0x5B810000u) /** Peripheral CONNECTIVITY__APBH base pointer */ #define CONNECTIVITY__APBH ((APBH_Type *)CONNECTIVITY__APBH_BASE) /** Array initializer of APBH peripheral base addresses */ #define APBH_BASE_ADDRS { CONNECTIVITY__APBH_BASE } /** Array initializer of APBH peripheral base pointers */ #define APBH_BASE_PTRS { CONNECTIVITY__APBH } /** Interrupt vectors for the APBH peripheral type */ #define APBH_IRQS { CONNECTIVITY_APBHDMA_IRQn } /*! * @} */ /* end of group APBH_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ASMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer * @{ */ /** ASMC - Register Layout Typedef */ typedef struct { __I uint32_t SRS; /**< System Reset Status Register, offset: 0x0 */ uint8_t RESERVED_0[4]; __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */ __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */ __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */ __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */ } ASMC_Type; /* ---------------------------------------------------------------------------- -- ASMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ASMC_Register_Masks ASMC Register Masks * @{ */ /*! @name SRS - System Reset Status Register */ /*! @{ */ #define ASMC_SRS_WAKEUP_MASK (0x1U) #define ASMC_SRS_WAKEUP_SHIFT (0U) /*! WAKEUP - Low Leakage Wakeup Reset * 0b0..Reset not caused by LLWU module wakeup source * 0b1..Reset caused by LLWU module wakeup source */ #define ASMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK) #define ASMC_SRS_WDOG1_MASK (0x20U) #define ASMC_SRS_WDOG1_SHIFT (5U) /*! WDOG1 - Watchdog * 0b0..Reset not caused by watchdog timeout * 0b1..Reset caused by watchdog timeout */ #define ASMC_SRS_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK) #define ASMC_SRS_RES_MASK (0x40U) #define ASMC_SRS_RES_SHIFT (6U) /*! RES - Chip Reset not POR * 0b0..Chip Reset did not occur * 0b1..Chip Reset caused by a source other than POR occured */ #define ASMC_SRS_RES(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK) #define ASMC_SRS_POR_MASK (0x80U) #define ASMC_SRS_POR_SHIFT (7U) /*! POR - Power-On Reset * 0b0..Reset not caused by POR * 0b1..Reset caused by POR */ #define ASMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK) #define ASMC_SRS_LOCKUP_MASK (0x200U) #define ASMC_SRS_LOCKUP_SHIFT (9U) /*! LOCKUP - Core 1 Lockup * 0b0..Reset not caused by core LOCKUP event * 0b1..Reset caused by core LOCKUP event */ #define ASMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK) #define ASMC_SRS_SW_MASK (0x400U) #define ASMC_SRS_SW_SHIFT (10U) /*! SW - Software * 0b0..Reset not caused by software setting of SYSRESETREQ bit * 0b1..Reset caused by software setting of SYSRESETREQ bit */ #define ASMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK) #define ASMC_SRS_SACKERR_MASK (0x1000U) #define ASMC_SRS_SACKERR_SHIFT (12U) /*! SACKERR - Stop Mode Acknowledge Error Reset * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode */ #define ASMC_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK) /*! @} */ /*! @name PMPROT - Power Mode Protection register */ /*! @{ */ #define ASMC_PMPROT_AVLLS_MASK (0x2U) #define ASMC_PMPROT_AVLLS_SHIFT (1U) /*! AVLLS - Allow Very-Low-Leakage Stop Mode * 0b0..Not Allowed * 0b1..Allowed */ #define ASMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK) #define ASMC_PMPROT_ALLS_MASK (0x8U) #define ASMC_PMPROT_ALLS_SHIFT (3U) /*! ALLS - Allow Low-Leakage Stop Mode * 0b0..Not Allowed * 0b1..Allowed */ #define ASMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK) #define ASMC_PMPROT_AVLP_MASK (0x20U) #define ASMC_PMPROT_AVLP_SHIFT (5U) /*! AVLP - Allow Very-Low-Power Modes * 0b0..VLPR, VLPW, and VLPS are not allowed. * 0b1..VLPR, VLPW, and VLPS are allowed. */ #define ASMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK) #define ASMC_PMPROT_AHSRUN_MASK (0x80U) #define ASMC_PMPROT_AHSRUN_SHIFT (7U) /*! AHSRUN - Allow High Speed Run mode * 0b0..HSRUN is not allowed * 0b1..HSRUN is allowed */ #define ASMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AHSRUN_SHIFT)) & ASMC_PMPROT_AHSRUN_MASK) /*! @} */ /*! @name PMCTRL - Power Mode Control register */ /*! @{ */ #define ASMC_PMCTRL_STOPM_MASK (0x7U) #define ASMC_PMCTRL_STOPM_SHIFT (0U) /*! STOPM - Stop Mode Control * 0b000..Normal Stop (STOP) * 0b001..Reserved * 0b010..Very-Low-Power Stop (VLPS) * 0b011..Low-leakage stop * 0b100..Very-low-leakage stop * 0b101..Reserved * 0b110..Reseved * 0b111..Reserved */ #define ASMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK) #define ASMC_PMCTRL_RUNM_MASK (0x60U) #define ASMC_PMCTRL_RUNM_SHIFT (5U) /*! RUNM - Run Mode Control * 0b00..Normal Run mode (RUN) * 0b01..Reserved * 0b10..Very-Low-Power Run mode (VLPR) * 0b11..High Speed Run mode (HSRUN) */ #define ASMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK) /*! @} */ /*! @name STOPCTRL - Stop Control Register */ /*! @{ */ #define ASMC_STOPCTRL_PSTOPO_MASK (0xC0U) #define ASMC_STOPCTRL_PSTOPO_SHIFT (6U) /*! PSTOPO - Partial Stop Option * 0b00..STOP - Normal Stop mode * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled * 0b11..Reserved */ #define ASMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK) /*! @} */ /*! @name PMSTAT - Power Mode Status register */ /*! @{ */ #define ASMC_PMSTAT_PMSTAT_MASK (0xFFU) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ #define ASMC_PMSTAT_PMSTAT_SHIFT (0U) /*! PMSTAT - Power Mode Status * 0b00000001..Current power mode is RUN. * 0b00000010..Current power mode is STOP. * 0b00000100..Current power mode is VLPR. * 0b00001000..Current power mode is VLPW. * 0b00010000..Current power mode is VLPS. * 0b00100000..Current power mode is LLS. * 0b01000000..Current power mode is VLLS. * 0b10000000..Current power mode is HSRUN */ #define ASMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ /*! @} */ /*! * @} */ /* end of group ASMC_Register_Masks */ /* ASMC - Peripheral instance base addresses */ /** Peripheral CM4__ASMC base address */ #define CM4__ASMC_BASE (0x41410000u) /** Peripheral CM4__ASMC base pointer */ #define CM4__ASMC ((ASMC_Type *)CM4__ASMC_BASE) /** Peripheral SCU__ASMC base address */ #define SCU__ASMC_BASE (0x33410000u) /** Peripheral SCU__ASMC base pointer */ #define SCU__ASMC ((ASMC_Type *)SCU__ASMC_BASE) /** Array initializer of ASMC peripheral base addresses */ #define ASMC_BASE_ADDRS { CM4__ASMC_BASE, SCU__ASMC_BASE } /** Array initializer of ASMC peripheral base pointers */ #define ASMC_BASE_PTRS { CM4__ASMC, SCU__ASMC } /*! * @} */ /* end of group ASMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ASRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer * @{ */ /** ASRC - Register Layout Typedef */ typedef struct { __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */ __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */ __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */ __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */ __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */ __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */ __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */ uint8_t RESERVED_1[28]; __IO uint32_t ASRPM[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */ __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */ uint8_t RESERVED_2[4]; __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */ __O uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */ __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */ __O uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */ __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */ __O uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */ __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */ uint8_t RESERVED_3[8]; __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */ __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */ __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */ __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */ __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */ __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */ __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */ __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */ __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */ __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */ __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */ __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */ __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */ __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */ uint8_t RESERVED_4[8]; __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */ } ASRC_Type; /* ---------------------------------------------------------------------------- -- ASRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ASRC_Register_Masks ASRC Register Masks * @{ */ /*! @name ASRCTR - ASRC Control Register */ /*! @{ */ #define ASRC_ASRCTR_ASRCEN_MASK (0x1U) #define ASRC_ASRCTR_ASRCEN_SHIFT (0U) /*! ASRCEN - ASRCEN */ #define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK) #define ASRC_ASRCTR_ASREA_MASK (0x2U) #define ASRC_ASRCTR_ASREA_SHIFT (1U) /*! ASREA - ASREA */ #define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK) #define ASRC_ASRCTR_ASREB_MASK (0x4U) #define ASRC_ASRCTR_ASREB_SHIFT (2U) /*! ASREB - ASREB */ #define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK) #define ASRC_ASRCTR_ASREC_MASK (0x8U) #define ASRC_ASRCTR_ASREC_SHIFT (3U) /*! ASREC - ASREC */ #define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK) #define ASRC_ASRCTR_SRST_MASK (0x10U) #define ASRC_ASRCTR_SRST_SHIFT (4U) /*! SRST - SRST */ #define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK) #define ASRC_ASRCTR_IDRA_MASK (0x2000U) #define ASRC_ASRCTR_IDRA_SHIFT (13U) /*! IDRA - IDRA */ #define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK) #define ASRC_ASRCTR_USRA_MASK (0x4000U) #define ASRC_ASRCTR_USRA_SHIFT (14U) /*! USRA - USRA */ #define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK) #define ASRC_ASRCTR_IDRB_MASK (0x8000U) #define ASRC_ASRCTR_IDRB_SHIFT (15U) /*! IDRB - IDRB */ #define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK) #define ASRC_ASRCTR_USRB_MASK (0x10000U) #define ASRC_ASRCTR_USRB_SHIFT (16U) /*! USRB - USRB */ #define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK) #define ASRC_ASRCTR_IDRC_MASK (0x20000U) #define ASRC_ASRCTR_IDRC_SHIFT (17U) /*! IDRC - IDRC */ #define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK) #define ASRC_ASRCTR_USRC_MASK (0x40000U) #define ASRC_ASRCTR_USRC_SHIFT (18U) /*! USRC - USRC */ #define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK) #define ASRC_ASRCTR_ATSA_MASK (0x100000U) #define ASRC_ASRCTR_ATSA_SHIFT (20U) /*! ATSA - ATSA */ #define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK) #define ASRC_ASRCTR_ATSB_MASK (0x200000U) #define ASRC_ASRCTR_ATSB_SHIFT (21U) /*! ATSB - ATSB */ #define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK) #define ASRC_ASRCTR_ATSC_MASK (0x400000U) #define ASRC_ASRCTR_ATSC_SHIFT (22U) /*! ATSC - ATSC */ #define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK) /*! @} */ /*! @name ASRIER - ASRC Interrupt Enable Register */ /*! @{ */ #define ASRC_ASRIER_ADIEA_MASK (0x1U) #define ASRC_ASRIER_ADIEA_SHIFT (0U) /*! ADIEA - ADIEA * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK) #define ASRC_ASRIER_ADIEB_MASK (0x2U) #define ASRC_ASRIER_ADIEB_SHIFT (1U) /*! ADIEB - ADIEB * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK) #define ASRC_ASRIER_ADIEC_MASK (0x4U) #define ASRC_ASRIER_ADIEC_SHIFT (2U) /*! ADIEC - ADIEC * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK) #define ASRC_ASRIER_ADOEA_MASK (0x8U) #define ASRC_ASRIER_ADOEA_SHIFT (3U) /*! ADOEA - ADOEA * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK) #define ASRC_ASRIER_ADOEB_MASK (0x10U) #define ASRC_ASRIER_ADOEB_SHIFT (4U) /*! ADOEB - ADOEB * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK) #define ASRC_ASRIER_ADOEC_MASK (0x20U) #define ASRC_ASRIER_ADOEC_SHIFT (5U) /*! ADOEC - ADOEC * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK) #define ASRC_ASRIER_AOLIE_MASK (0x40U) #define ASRC_ASRIER_AOLIE_SHIFT (6U) /*! AOLIE - AOLIE * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK) #define ASRC_ASRIER_AFPWE_MASK (0x80U) #define ASRC_ASRIER_AFPWE_SHIFT (7U) /*! AFPWE - AFPWE * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK) /*! @} */ /*! @name ASRCNCR - ASRC Channel Number Configuration Register */ /*! @{ */ #define ASRC_ASRCNCR_ANCA_MASK (0xFU) #define ASRC_ASRCNCR_ANCA_SHIFT (0U) /*! ANCA - ANCA * 0b0000..0 channels in A (Pair A is disabled) * 0b0001..1 channel in A * 0b0010..2 channels in A * 0b0011..3 channels in A * 0b0100..4 channels in A * 0b0101..5 channels in A * 0b0110..6 channels in A * 0b0111..7 channels in A * 0b1000..8 channels in A * 0b1001..9 channels in A * 0b1010..10 channels in A * 0b1011-0b1111..Should not be used. */ #define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK) #define ASRC_ASRCNCR_ANCB_MASK (0xF0U) #define ASRC_ASRCNCR_ANCB_SHIFT (4U) /*! ANCB - ANCB * 0b0000..0 channels in B (Pair B is disabled) * 0b0001..1 channel in B * 0b0010..2 channels in B * 0b0011..3 channels in B * 0b0100..4 channels in B * 0b0101..5 channels in B * 0b0110..6 channels in B * 0b0111..7 channels in B * 0b1000..8 channels in B * 0b1001..9 channels in B * 0b1010..10 channels in B * 0b1011-0b1111..Should not be used. */ #define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK) #define ASRC_ASRCNCR_ANCC_MASK (0xF00U) #define ASRC_ASRCNCR_ANCC_SHIFT (8U) /*! ANCC - ANCC * 0b0000..0 channels in C (Pair C is disabled) * 0b0001..1 channel in C * 0b0010..2 channels in C * 0b0011..3 channels in C * 0b0100..4 channels in C * 0b0101..5 channels in C * 0b0110..6 channels in C * 0b0111..7 channels in C * 0b1000..8 channels in C * 0b1001..9 channels in C * 0b1010..10 channels in C * 0b1011-0b1111..Should not be used. */ #define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK) /*! @} */ /*! @name ASRCFG - ASRC Filter Configuration Status Register */ /*! @{ */ #define ASRC_ASRCFG_PREMODA_MASK (0xC0U) #define ASRC_ASRCFG_PREMODA_SHIFT (6U) /*! PREMODA - PREMODA * 0b00..Select Upsampling-by-2 as defined in * 0b01..Select Direct-Connection as defined in * 0b10..Select Downsampling-by-2 as defined in * 0b11..Select passthrough mode. In this case, POSTMODA[1-0] have no use. */ #define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK) #define ASRC_ASRCFG_POSTMODA_MASK (0x300U) #define ASRC_ASRCFG_POSTMODA_SHIFT (8U) /*! POSTMODA - POSTMODA * 0b00..Select Upsampling-by-2 as defined in * 0b01..Select Direct-Connection as defined in * 0b10..Select Downsampling-by-2 as defined in */ #define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK) #define ASRC_ASRCFG_PREMODB_MASK (0xC00U) #define ASRC_ASRCFG_PREMODB_SHIFT (10U) /*! PREMODB - PREMODB * 0b00..Select Upsampling-by-2 as defined in * 0b01..Select Direct-Connection as defined in * 0b10..Select Downsampling-by-2 as defined in * 0b11..Select passthrough mode. In this case, POSTMODB[1-0] have no use. */ #define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK) #define ASRC_ASRCFG_POSTMODB_MASK (0x3000U) #define ASRC_ASRCFG_POSTMODB_SHIFT (12U) /*! POSTMODB - POSTMODB * 0b00..Select Upsampling-by-2 as defined in * 0b01..Select Direct-Connection as defined in * 0b10..Select Downsampling-by-2 as defined in */ #define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK) #define ASRC_ASRCFG_PREMODC_MASK (0xC000U) #define ASRC_ASRCFG_PREMODC_SHIFT (14U) /*! PREMODC - PREMODC * 0b00..Select Upsampling-by-2 as defined in * 0b01..Select Direct-Connection as defined in * 0b10..Select Downsampling-by-2 as defined in * 0b11..Select passthrough mode. In this case, POSTMODC[1-0] have no use. */ #define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK) #define ASRC_ASRCFG_POSTMODC_MASK (0x30000U) #define ASRC_ASRCFG_POSTMODC_SHIFT (16U) /*! POSTMODC - POSTMODC * 0b00..Select Upsampling-by-2 as defined in Signal Processing Flow. * 0b01..Select Direct-Connection as defined in Signal Processing Flow. * 0b10..Select Downsampling-by-2 as defined in Signal Processing Flow. */ #define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK) #define ASRC_ASRCFG_NDPRA_MASK (0x40000U) #define ASRC_ASRCFG_NDPRA_SHIFT (18U) /*! NDPRA - NDPRA * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM. * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. */ #define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK) #define ASRC_ASRCFG_NDPRB_MASK (0x80000U) #define ASRC_ASRCFG_NDPRB_SHIFT (19U) /*! NDPRB - NDPRB * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM. * 0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM. */ #define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK) #define ASRC_ASRCFG_NDPRC_MASK (0x100000U) #define ASRC_ASRCFG_NDPRC_SHIFT (20U) /*! NDPRC - NDPRC * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM. * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. */ #define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK) #define ASRC_ASRCFG_INIRQA_MASK (0x200000U) #define ASRC_ASRCFG_INIRQA_SHIFT (21U) /*! INIRQA - INIRQA */ #define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK) #define ASRC_ASRCFG_INIRQB_MASK (0x400000U) #define ASRC_ASRCFG_INIRQB_SHIFT (22U) /*! INIRQB - INIRQB */ #define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK) #define ASRC_ASRCFG_INIRQC_MASK (0x800000U) #define ASRC_ASRCFG_INIRQC_SHIFT (23U) /*! INIRQC - INIRQC */ #define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK) /*! @} */ /*! @name ASRCSR - ASRC Clock Source Register */ /*! @{ */ #define ASRC_ASRCSR_AICSA_MASK (0xFU) #define ASRC_ASRCSR_AICSA_SHIFT (0U) /*! AICSA - AICSA * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK) #define ASRC_ASRCSR_AICSB_MASK (0xF0U) #define ASRC_ASRCSR_AICSB_SHIFT (4U) /*! AICSB - AICSB * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK) #define ASRC_ASRCSR_AICSC_MASK (0xF00U) #define ASRC_ASRCSR_AICSC_SHIFT (8U) /*! AICSC - AICSC * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK) #define ASRC_ASRCSR_AOCSA_MASK (0xF000U) #define ASRC_ASRCSR_AOCSA_SHIFT (12U) /*! AOCSA - AOCSA * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK) #define ASRC_ASRCSR_AOCSB_MASK (0xF0000U) #define ASRC_ASRCSR_AOCSB_SHIFT (16U) /*! AOCSB - AOCSB * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK) #define ASRC_ASRCSR_AOCSC_MASK (0xF00000U) #define ASRC_ASRCSR_AOCSC_SHIFT (20U) /*! AOCSC - AOCSC * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 * 0b0011..bit clock 3 * 0b0100..bit clock 4 * 0b0101..bit clock 5 * 0b0110..bit clock 6 * 0b0111..bit clock 7 * 0b1000..bit clock 8 * 0b1001..bit clock 9 * 0b1010..bit clock A * 0b1011..bit clock B * 0b1100..bit clock C * 0b1101..bit clock D * 0b1110..bit clock E * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK) /*! @} */ /*! @name ASRCDR1 - ASRC Clock Divider Register 1 */ /*! @{ */ #define ASRC_ASRCDR1_AICPA_MASK (0x7U) #define ASRC_ASRCDR1_AICPA_SHIFT (0U) /*! AICPA - AICPA */ #define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK) #define ASRC_ASRCDR1_AICDA_MASK (0x38U) #define ASRC_ASRCDR1_AICDA_SHIFT (3U) /*! AICDA - AICDA */ #define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK) #define ASRC_ASRCDR1_AICPB_MASK (0x1C0U) #define ASRC_ASRCDR1_AICPB_SHIFT (6U) /*! AICPB - AICPB */ #define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK) #define ASRC_ASRCDR1_AICDB_MASK (0xE00U) #define ASRC_ASRCDR1_AICDB_SHIFT (9U) /*! AICDB - AICDB */ #define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK) #define ASRC_ASRCDR1_AOCPA_MASK (0x7000U) #define ASRC_ASRCDR1_AOCPA_SHIFT (12U) /*! AOCPA - AOCPA */ #define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK) #define ASRC_ASRCDR1_AOCDA_MASK (0x38000U) #define ASRC_ASRCDR1_AOCDA_SHIFT (15U) /*! AOCDA - AOCDA */ #define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK) #define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U) #define ASRC_ASRCDR1_AOCPB_SHIFT (18U) /*! AOCPB - AOCPB */ #define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK) #define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U) #define ASRC_ASRCDR1_AOCDB_SHIFT (21U) /*! AOCDB - AOCDB */ #define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK) /*! @} */ /*! @name ASRCDR2 - ASRC Clock Divider Register 2 */ /*! @{ */ #define ASRC_ASRCDR2_AICPC_MASK (0x7U) #define ASRC_ASRCDR2_AICPC_SHIFT (0U) /*! AICPC - AICPC */ #define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK) #define ASRC_ASRCDR2_AICDC_MASK (0x38U) #define ASRC_ASRCDR2_AICDC_SHIFT (3U) /*! AICDC - AICDC */ #define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK) #define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U) #define ASRC_ASRCDR2_AOCPC_SHIFT (6U) /*! AOCPC - AOCPC */ #define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK) #define ASRC_ASRCDR2_AOCDC_MASK (0xE00U) #define ASRC_ASRCDR2_AOCDC_SHIFT (9U) /*! AOCDC - AOCDC */ #define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK) /*! @} */ /*! @name ASRSTR - ASRC Status Register */ /*! @{ */ #define ASRC_ASRSTR_AIDEA_MASK (0x1U) #define ASRC_ASRSTR_AIDEA_SHIFT (0U) /*! AIDEA - AIDEA */ #define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK) #define ASRC_ASRSTR_AIDEB_MASK (0x2U) #define ASRC_ASRSTR_AIDEB_SHIFT (1U) /*! AIDEB - AIDEB */ #define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK) #define ASRC_ASRSTR_AIDEC_MASK (0x4U) #define ASRC_ASRSTR_AIDEC_SHIFT (2U) /*! AIDEC - AIDEC */ #define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK) #define ASRC_ASRSTR_AODFA_MASK (0x8U) #define ASRC_ASRSTR_AODFA_SHIFT (3U) /*! AODFA - AODFA */ #define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK) #define ASRC_ASRSTR_AODFB_MASK (0x10U) #define ASRC_ASRSTR_AODFB_SHIFT (4U) /*! AODFB - AODFB */ #define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK) #define ASRC_ASRSTR_AODFC_MASK (0x20U) #define ASRC_ASRSTR_AODFC_SHIFT (5U) /*! AODFC - AODFC */ #define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK) #define ASRC_ASRSTR_AOLE_MASK (0x40U) #define ASRC_ASRSTR_AOLE_SHIFT (6U) /*! AOLE - AOLE */ #define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK) #define ASRC_ASRSTR_FPWT_MASK (0x80U) #define ASRC_ASRSTR_FPWT_SHIFT (7U) /*! FPWT - FPWT */ #define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK) #define ASRC_ASRSTR_AIDUA_MASK (0x100U) #define ASRC_ASRSTR_AIDUA_SHIFT (8U) /*! AIDUA - AIDUA */ #define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK) #define ASRC_ASRSTR_AIDUB_MASK (0x200U) #define ASRC_ASRSTR_AIDUB_SHIFT (9U) /*! AIDUB - AIDUB */ #define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK) #define ASRC_ASRSTR_AIDUC_MASK (0x400U) #define ASRC_ASRSTR_AIDUC_SHIFT (10U) /*! AIDUC - AIDUC */ #define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK) #define ASRC_ASRSTR_AODOA_MASK (0x800U) #define ASRC_ASRSTR_AODOA_SHIFT (11U) /*! AODOA - AODOA */ #define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK) #define ASRC_ASRSTR_AODOB_MASK (0x1000U) #define ASRC_ASRSTR_AODOB_SHIFT (12U) /*! AODOB - AODOB */ #define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK) #define ASRC_ASRSTR_AODOC_MASK (0x2000U) #define ASRC_ASRSTR_AODOC_SHIFT (13U) /*! AODOC - AODOC */ #define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK) #define ASRC_ASRSTR_AIOLA_MASK (0x4000U) #define ASRC_ASRSTR_AIOLA_SHIFT (14U) /*! AIOLA - AIOLA */ #define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK) #define ASRC_ASRSTR_AIOLB_MASK (0x8000U) #define ASRC_ASRSTR_AIOLB_SHIFT (15U) /*! AIOLB - AIOLB */ #define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK) #define ASRC_ASRSTR_AIOLC_MASK (0x10000U) #define ASRC_ASRSTR_AIOLC_SHIFT (16U) /*! AIOLC - AIOLC */ #define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK) #define ASRC_ASRSTR_AOOLA_MASK (0x20000U) #define ASRC_ASRSTR_AOOLA_SHIFT (17U) /*! AOOLA - AOOLA */ #define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK) #define ASRC_ASRSTR_AOOLB_MASK (0x40000U) #define ASRC_ASRSTR_AOOLB_SHIFT (18U) /*! AOOLB - AOOLB */ #define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK) #define ASRC_ASRSTR_AOOLC_MASK (0x80000U) #define ASRC_ASRSTR_AOOLC_SHIFT (19U) /*! AOOLC - AOOLC */ #define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK) #define ASRC_ASRSTR_ATQOL_MASK (0x100000U) #define ASRC_ASRSTR_ATQOL_SHIFT (20U) /*! ATQOL - ATQOL */ #define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK) #define ASRC_ASRSTR_DSLCNT_MASK (0x200000U) #define ASRC_ASRSTR_DSLCNT_SHIFT (21U) /*! DSLCNT - DSLCNT */ #define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK) /*! @} */ /*! @name ASRPM - ASRC Parameter Register n */ /*! @{ */ #define ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU) #define ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U) /*! PARAMETER_VALUE - PARAMETER_VALUE */ #define ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK) /*! @} */ /* The count of ASRC_ASRPM */ #define ASRC_ASRPM_COUNT (5U) /*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */ /*! @{ */ #define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U) #define ASRC_ASRTFR1_TF_BASE_SHIFT (6U) /*! TF_BASE - TF_BASE */ #define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK) #define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U) #define ASRC_ASRTFR1_TF_FILL_SHIFT (13U) /*! TF_FILL - TF_FILL */ #define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK) /*! @} */ /*! @name ASRCCR - ASRC Channel Counter Register */ /*! @{ */ #define ASRC_ASRCCR_ACIA_MASK (0xFU) #define ASRC_ASRCCR_ACIA_SHIFT (0U) /*! ACIA - ACIA */ #define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK) #define ASRC_ASRCCR_ACIB_MASK (0xF0U) #define ASRC_ASRCCR_ACIB_SHIFT (4U) /*! ACIB - ACIB */ #define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK) #define ASRC_ASRCCR_ACIC_MASK (0xF00U) #define ASRC_ASRCCR_ACIC_SHIFT (8U) /*! ACIC - ACIC */ #define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK) #define ASRC_ASRCCR_ACOA_MASK (0xF000U) #define ASRC_ASRCCR_ACOA_SHIFT (12U) /*! ACOA - ACOA */ #define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK) #define ASRC_ASRCCR_ACOB_MASK (0xF0000U) #define ASRC_ASRCCR_ACOB_SHIFT (16U) /*! ACOB - ACOB */ #define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK) #define ASRC_ASRCCR_ACOC_MASK (0xF00000U) #define ASRC_ASRCCR_ACOC_SHIFT (20U) /*! ACOC - ACOC */ #define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK) /*! @} */ /*! @name ASRDIA - ASRC Data Input Register for Pair x */ /*! @{ */ #define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDIA_DATA_SHIFT (0U) /*! DATA - DATA */ #define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK) /*! @} */ /*! @name ASRDOA - ASRC Data Output Register for Pair x */ /*! @{ */ #define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDOA_DATA_SHIFT (0U) /*! DATA - DATA */ #define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK) /*! @} */ /*! @name ASRDIB - ASRC Data Input Register for Pair x */ /*! @{ */ #define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDIB_DATA_SHIFT (0U) /*! DATA - DATA */ #define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK) /*! @} */ /*! @name ASRDOB - ASRC Data Output Register for Pair x */ /*! @{ */ #define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDOB_DATA_SHIFT (0U) /*! DATA - DATA */ #define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK) /*! @} */ /*! @name ASRDIC - ASRC Data Input Register for Pair x */ /*! @{ */ #define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDIC_DATA_SHIFT (0U) /*! DATA - DATA */ #define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK) /*! @} */ /*! @name ASRDOC - ASRC Data Output Register for Pair x */ /*! @{ */ #define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDOC_DATA_SHIFT (0U) /*! DATA - DATA */ #define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK) /*! @} */ /*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */ /*! @{ */ #define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU) #define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U) /*! IDRATIOA_H - IDRATIOA_H */ #define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK) /*! @} */ /*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */ /*! @{ */ #define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU) #define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U) /*! IDRATIOA_L - IDRATIOA_L */ #define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK) /*! @} */ /*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */ /*! @{ */ #define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU) #define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U) /*! IDRATIOB_H - IDRATIOB_H */ #define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK) /*! @} */ /*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */ /*! @{ */ #define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU) #define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U) /*! IDRATIOB_L - IDRATIOB_L */ #define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK) /*! @} */ /*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */ /*! @{ */ #define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU) #define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U) /*! IDRATIOC_H - IDRATIOC_H */ #define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK) /*! @} */ /*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */ /*! @{ */ #define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU) #define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U) /*! IDRATIOC_L - IDRATIOC_L */ #define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK) /*! @} */ /*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */ /*! @{ */ #define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU) #define ASRC_ASR76K_ASR76K_SHIFT (0U) /*! ASR76K - ASR76K */ #define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK) /*! @} */ /*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */ /*! @{ */ #define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU) #define ASRC_ASR56K_ASR56K_SHIFT (0U) /*! ASR56K - ASR56K */ #define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK) /*! @} */ /*! @name ASRMCRA - ASRC Misc Control Register for Pair A */ /*! @{ */ #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU) #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U) /*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA */ #define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK) #define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U) #define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U) /*! RSYNOFA - RSYNOFA */ #define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK) #define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U) #define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U) /*! RSYNIFA - RSYNIFA */ #define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK) #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U) #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U) /*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA */ #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK) #define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U) #define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U) /*! BYPASSPOLYA - BYPASSPOLYA * 0b1..Bypass polyphase filtering. * 0b0..Don't bypass polyphase filtering. */ #define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK) #define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U) #define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U) /*! BUFSTALLA - BUFSTALLA * 0b1..Stall Pair A conversion in case of near empty/full FIFO conditions. * 0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions. */ #define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK) #define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U) #define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U) /*! EXTTHRSHA - EXTTHRSHA * 0b1..Use external defined thresholds. * 0b0..Use default thresholds. */ #define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK) #define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U) #define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U) /*! ZEROBUFA - ZEROBUFA * 0b1..Don't zeroize the buffer * 0b0..Zeroize the buffer */ #define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK) /*! @} */ /*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */ /*! @{ */ #define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU) #define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U) /*! INFIFO_FILLA - INFIFO_FILLA */ #define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK) #define ASRC_ASRFSTA_IAEA_MASK (0x800U) #define ASRC_ASRFSTA_IAEA_SHIFT (11U) /*! IAEA - IAEA */ #define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK) #define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U) #define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U) /*! OUTFIFO_FILLA - OUTFIFO_FILLA */ #define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK) #define ASRC_ASRFSTA_OAFA_MASK (0x800000U) #define ASRC_ASRFSTA_OAFA_SHIFT (23U) /*! OAFA - OAFA */ #define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK) /*! @} */ /*! @name ASRMCRB - ASRC Misc Control Register for Pair B */ /*! @{ */ #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU) #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U) /*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB */ #define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK) #define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U) #define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U) /*! RSYNOFB - RSYNOFB */ #define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK) #define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U) #define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U) /*! RSYNIFB - RSYNIFB */ #define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK) #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U) #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U) /*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB */ #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK) #define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U) #define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U) /*! BYPASSPOLYB - BYPASSPOLYB * 0b1..Bypass polyphase filtering. * 0b0..Don't bypass polyphase filtering. */ #define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK) #define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U) #define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U) /*! BUFSTALLB - BUFSTALLB * 0b1..Stall Pair B conversion in case of near empty/full FIFO conditions. * 0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions. */ #define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK) #define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U) #define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U) /*! EXTTHRSHB - EXTTHRSHB * 0b1..Use external defined thresholds. * 0b0..Use default thresholds. */ #define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK) #define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U) #define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U) /*! ZEROBUFB - ZEROBUFB * 0b1..Don't zeroize the buffer * 0b0..Zeroize the buffer */ #define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK) /*! @} */ /*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */ /*! @{ */ #define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU) #define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U) /*! INFIFO_FILLB - INFIFO_FILLB */ #define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK) #define ASRC_ASRFSTB_IAEB_MASK (0x800U) #define ASRC_ASRFSTB_IAEB_SHIFT (11U) /*! IAEB - IAEB */ #define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK) #define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U) #define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U) /*! OUTFIFO_FILLB - OUTFIFO_FILLB */ #define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK) #define ASRC_ASRFSTB_OAFB_MASK (0x800000U) #define ASRC_ASRFSTB_OAFB_SHIFT (23U) /*! OAFB - OAFB */ #define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK) /*! @} */ /*! @name ASRMCRC - ASRC Misc Control Register for Pair C */ /*! @{ */ #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU) #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U) /*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC */ #define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK) #define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U) #define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U) /*! RSYNOFC - RSYNOFC */ #define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK) #define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U) #define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U) /*! RSYNIFC - RSYNIFC */ #define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK) #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U) #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U) /*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC */ #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK) #define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U) #define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U) /*! BYPASSPOLYC - BYPASSPOLYC * 0b1..Bypass polyphase filtering. * 0b0..Don't bypass polyphase filtering. */ #define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK) #define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U) #define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U) /*! BUFSTALLC - BUFSTALLC * 0b1..Stall Pair C conversion in case of near empty/full FIFO conditions. * 0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions. */ #define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK) #define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U) #define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U) /*! EXTTHRSHC - EXTTHRSHC * 0b1..Use external defined thresholds. * 0b0..Use default thresholds. */ #define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK) #define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U) #define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U) /*! ZEROBUFC - ZEROBUFC * 0b1..Don't zeroize the buffer * 0b0..Zeroize the buffer */ #define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK) /*! @} */ /*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */ /*! @{ */ #define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU) #define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U) /*! INFIFO_FILLC - INFIFO_FILLC */ #define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK) #define ASRC_ASRFSTC_IAEC_MASK (0x800U) #define ASRC_ASRFSTC_IAEC_SHIFT (11U) /*! IAEC - IAEC */ #define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK) #define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U) #define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U) /*! OUTFIFO_FILLC - OUTFIFO_FILLC */ #define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK) #define ASRC_ASRFSTC_OAFC_MASK (0x800000U) #define ASRC_ASRFSTC_OAFC_SHIFT (23U) /*! OAFC - OAFC */ #define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK) /*! @} */ /*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */ /*! @{ */ #define ASRC_ASRMCR1_OW16_MASK (0x1U) #define ASRC_ASRMCR1_OW16_SHIFT (0U) /*! OW16 - OW16 * 0b1..16-bit output data * 0b0..24-bit output data. */ #define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK) #define ASRC_ASRMCR1_OSGN_MASK (0x2U) #define ASRC_ASRMCR1_OSGN_SHIFT (1U) /*! OSGN - OSGN * 0b1..Sign extension. * 0b0..No sign extension. */ #define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK) #define ASRC_ASRMCR1_OMSB_MASK (0x4U) #define ASRC_ASRMCR1_OMSB_SHIFT (2U) /*! OMSB - OMSB * 0b1..MSB aligned. * 0b0..LSB aligned. */ #define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK) #define ASRC_ASRMCR1_IMSB_MASK (0x100U) #define ASRC_ASRMCR1_IMSB_SHIFT (8U) /*! IMSB - IMSB * 0b1..MSB aligned. * 0b0..LSB aligned. */ #define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK) #define ASRC_ASRMCR1_IWD_MASK (0xE00U) #define ASRC_ASRMCR1_IWD_SHIFT (9U) /*! IWD - IWD */ #define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK) /*! @} */ /* The count of ASRC_ASRMCR1 */ #define ASRC_ASRMCR1_COUNT (3U) /*! * @} */ /* end of group ASRC_Register_Masks */ /* ASRC - Peripheral instance base addresses */ /** Peripheral ADMA__ASRC0 base address */ #define ADMA__ASRC0_BASE (0x59000000u) /** Peripheral ADMA__ASRC0 base pointer */ #define ADMA__ASRC0 ((ASRC_Type *)ADMA__ASRC0_BASE) /** Peripheral ADMA__ASRC1 base address */ #define ADMA__ASRC1_BASE (0x59800000u) /** Peripheral ADMA__ASRC1 base pointer */ #define ADMA__ASRC1 ((ASRC_Type *)ADMA__ASRC1_BASE) /** Array initializer of ASRC peripheral base addresses */ #define ASRC_BASE_ADDRS { ADMA__ASRC0_BASE, ADMA__ASRC1_BASE } /** Array initializer of ASRC peripheral base pointers */ #define ASRC_BASE_PTRS { ADMA__ASRC0, ADMA__ASRC1 } /*! * @} */ /* end of group ASRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BCH Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer * @{ */ /** BCH - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ __IO uint32_t SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ } CTRL; struct { /* offset: 0x10 */ __I uint32_t RW; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ __I uint32_t SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */ __I uint32_t CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */ __I uint32_t TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */ } STATUS0; struct { /* offset: 0x20 */ __IO uint32_t RW; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ __IO uint32_t SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */ __IO uint32_t CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */ __IO uint32_t TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */ } MODE; struct { /* offset: 0x30 */ __IO uint32_t RW; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ __IO uint32_t SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */ __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */ __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */ } ENCODEPTR; struct { /* offset: 0x40 */ __IO uint32_t RW; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ __IO uint32_t SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */ __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */ __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */ } DATAPTR; struct { /* offset: 0x50 */ __IO uint32_t RW; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ __IO uint32_t SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */ __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */ __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */ } METAPTR; uint8_t RESERVED_0[16]; struct { /* offset: 0x70 */ __IO uint32_t RW; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ __IO uint32_t SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */ __IO uint32_t CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */ __IO uint32_t TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */ } LAYOUTSELECT; struct { /* offset: 0x80 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */ } FLASH0LAYOUT0; struct { /* offset: 0x90 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */ } FLASH0LAYOUT1; struct { /* offset: 0xA0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */ } FLASH1LAYOUT0; struct { /* offset: 0xB0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */ } FLASH1LAYOUT1; struct { /* offset: 0xC0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */ } FLASH2LAYOUT0; struct { /* offset: 0xD0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */ } FLASH2LAYOUT1; struct { /* offset: 0xE0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */ } FLASH3LAYOUT0; struct { /* offset: 0xF0 */ __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */ __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */ __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */ } FLASH3LAYOUT1; struct { /* offset: 0x100 */ __IO uint32_t RW; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ __IO uint32_t SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ } DEBUG0; struct { /* offset: 0x110 */ __I uint32_t RW; /**< KES Debug Read Register, offset: 0x110 */ __I uint32_t SET; /**< KES Debug Read Register, offset: 0x114 */ __I uint32_t CLR; /**< KES Debug Read Register, offset: 0x118 */ __I uint32_t TOG; /**< KES Debug Read Register, offset: 0x11C */ } DBGKESREAD; struct { /* offset: 0x120 */ __I uint32_t RW; /**< Chien Search Debug Read Register, offset: 0x120 */ __I uint32_t SET; /**< Chien Search Debug Read Register, offset: 0x124 */ __I uint32_t CLR; /**< Chien Search Debug Read Register, offset: 0x128 */ __I uint32_t TOG; /**< Chien Search Debug Read Register, offset: 0x12C */ } DBGCSFEREAD; struct { /* offset: 0x130 */ __I uint32_t RW; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ __I uint32_t SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */ __I uint32_t CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */ __I uint32_t TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */ } DBGSYNDGENREAD; struct { /* offset: 0x140 */ __I uint32_t RW; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ __I uint32_t SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */ __I uint32_t CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */ __I uint32_t TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */ } DBGAHBMREAD; struct { /* offset: 0x150 */ __I uint32_t RW; /**< Block Name Register, offset: 0x150 */ __I uint32_t SET; /**< Block Name Register, offset: 0x154 */ __I uint32_t CLR; /**< Block Name Register, offset: 0x158 */ __I uint32_t TOG; /**< Block Name Register, offset: 0x15C */ } BLOCKNAME; struct { /* offset: 0x160 */ __I uint32_t RW; /**< BCH Version Register, offset: 0x160 */ __I uint32_t SET; /**< BCH Version Register, offset: 0x164 */ __I uint32_t CLR; /**< BCH Version Register, offset: 0x168 */ __I uint32_t TOG; /**< BCH Version Register, offset: 0x16C */ } VERSION; struct { /* offset: 0x170 */ __IO uint32_t RW; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ __IO uint32_t SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */ __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */ __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */ } DEBUG1; } BCH_Type; /* ---------------------------------------------------------------------------- -- BCH Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BCH_Register_Masks BCH Register Masks * @{ */ /*! @name CTRL - Hardware BCH ECC Accelerator Control Register */ /*! @{ */ #define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U) #define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U) /*! COMPLETE_IRQ - COMPLETE_IRQ */ #define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK) #define BCH_CTRL_RSVD0_MASK (0x2U) #define BCH_CTRL_RSVD0_SHIFT (1U) /*! RSVD0 - This field is reserved. */ #define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK) #define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U) #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U) /*! DEBUG_STALL_IRQ - DEBUG_STALL_IRQ */ #define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK) #define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U) #define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U) /*! BM_ERROR_IRQ - BM_ERROR_IRQ */ #define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK) #define BCH_CTRL_RSVD1_MASK (0xF0U) #define BCH_CTRL_RSVD1_SHIFT (4U) /*! RSVD1 - This field is reserved. */ #define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK) #define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U) #define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U) /*! COMPLETE_IRQ_EN - COMPLETE_IRQ_EN */ #define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK) #define BCH_CTRL_RSVD2_MASK (0x200U) #define BCH_CTRL_RSVD2_SHIFT (9U) /*! RSVD2 - This field is reserved. */ #define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK) #define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U) #define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U) /*! DEBUG_STALL_IRQ_EN - DEBUG_STALL_IRQ_EN */ #define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK) #define BCH_CTRL_RSVD3_MASK (0xF800U) #define BCH_CTRL_RSVD3_SHIFT (11U) /*! RSVD3 - This field is reserved. */ #define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK) #define BCH_CTRL_M2M_ENABLE_MASK (0x10000U) #define BCH_CTRL_M2M_ENABLE_SHIFT (16U) /*! M2M_ENABLE - M2M_ENABLE */ #define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK) #define BCH_CTRL_M2M_ENCODE_MASK (0x20000U) #define BCH_CTRL_M2M_ENCODE_SHIFT (17U) /*! M2M_ENCODE - M2M_ENCODE */ #define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK) #define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U) #define BCH_CTRL_M2M_LAYOUT_SHIFT (18U) /*! M2M_LAYOUT - M2M_LAYOUT */ #define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK) #define BCH_CTRL_RSVD4_MASK (0x300000U) #define BCH_CTRL_RSVD4_SHIFT (20U) /*! RSVD4 - This field is reserved. */ #define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK) #define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U) #define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U) /*! DEBUGSYNDROME - DEBUGSYNDROME */ #define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK) #define BCH_CTRL_RSVD5_MASK (0x3F800000U) #define BCH_CTRL_RSVD5_SHIFT (23U) /*! RSVD5 - This field is reserved. */ #define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK) #define BCH_CTRL_CLKGATE_MASK (0x40000000U) #define BCH_CTRL_CLKGATE_SHIFT (30U) /*! CLKGATE - CLKGATE * 0b0..Allow BCH to operate normally. * 0b1..Do not clock BCH gates in order to minimize power consumption. */ #define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK) #define BCH_CTRL_SFTRST_MASK (0x80000000U) #define BCH_CTRL_SFTRST_SHIFT (31U) /*! SFTRST - SFTRST * 0b0..Allow BCH to operate normally. * 0b1..Hold BCH in reset. */ #define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK) /*! @} */ /*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */ /*! @{ */ #define BCH_STATUS0_RSVD0_MASK (0x3U) #define BCH_STATUS0_RSVD0_SHIFT (0U) /*! RSVD0 - This field is reserved. */ #define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK) #define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U) #define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U) /*! UNCORRECTABLE - UNCORRECTABLE */ #define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK) #define BCH_STATUS0_CORRECTED_MASK (0x8U) #define BCH_STATUS0_CORRECTED_SHIFT (3U) /*! CORRECTED - CORRECTED */ #define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK) #define BCH_STATUS0_ALLONES_MASK (0x10U) #define BCH_STATUS0_ALLONES_SHIFT (4U) /*! ALLONES - ALLONES */ #define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK) #define BCH_STATUS0_RSVD1_MASK (0xE0U) #define BCH_STATUS0_RSVD1_SHIFT (5U) /*! RSVD1 - This field is reserved. */ #define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK) #define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U) #define BCH_STATUS0_STATUS_BLK0_SHIFT (8U) /*! STATUS_BLK0 - STATUS_BLK0 * 0b00000000..No errors found on block. * 0b00000001..One error found on block. * 0b00000010..One errors found on block. * 0b00000011..One errors found on block. * 0b00000100..One errors found on block. * 0b11111110..Block exhibited uncorrectable errors. * 0b11111111..Page is erased. */ #define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK) #define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U) #define BCH_STATUS0_COMPLETED_CE_SHIFT (16U) /*! COMPLETED_CE - COMPLETED_CE */ #define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK) #define BCH_STATUS0_HANDLE_MASK (0xFFF00000U) #define BCH_STATUS0_HANDLE_SHIFT (20U) /*! HANDLE - HANDLE */ #define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK) /*! @} */ /*! @name MODE - Hardware ECC Accelerator Mode Register */ /*! @{ */ #define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU) #define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U) /*! ERASE_THRESHOLD - ERASE_THRESHOLD */ #define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK) #define BCH_MODE_RSVD_MASK (0xFFFFFF00U) #define BCH_MODE_RSVD_SHIFT (8U) /*! RSVD - This field is reserved. */ #define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK) /*! @} */ /*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */ /*! @{ */ #define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU) #define BCH_ENCODEPTR_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK) /*! @} */ /*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */ /*! @{ */ #define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU) #define BCH_DATAPTR_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK) /*! @} */ /*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */ /*! @{ */ #define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU) #define BCH_METAPTR_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK) /*! @} */ /*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */ /*! @{ */ #define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U) #define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U) /*! CS0_SELECT - CS0_SELECT */ #define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK) #define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU) #define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U) /*! CS1_SELECT - CS1_SELECT */ #define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK) #define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U) #define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U) /*! CS2_SELECT - CS2_SELECT */ #define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK) #define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U) #define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U) /*! CS3_SELECT - CS3_SELECT */ #define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK) #define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U) #define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U) /*! CS4_SELECT - CS4_SELECT */ #define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK) #define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U) #define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U) /*! CS5_SELECT - CS5_SELECT */ #define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK) #define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U) #define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U) /*! CS6_SELECT - CS6_SELECT */ #define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK) #define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U) #define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U) /*! CS7_SELECT - CS7_SELECT */ #define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK) #define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U) #define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U) /*! CS8_SELECT - CS8_SELECT */ #define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK) #define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U) #define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U) /*! CS9_SELECT - CS9_SELECT */ #define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK) #define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U) #define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U) /*! CS10_SELECT - CS10_SELECT */ #define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK) #define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U) #define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U) /*! CS11_SELECT - CS11_SELECT */ #define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK) #define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U) #define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U) /*! CS12_SELECT - CS12_SELECT */ #define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK) #define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U) #define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U) /*! CS13_SELECT - CS13_SELECT */ #define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK) #define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U) #define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U) /*! CS14_SELECT - CS14_SELECT */ #define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK) #define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U) #define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U) /*! CS15_SELECT - CS15_SELECT */ #define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK) /*! @} */ /*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */ /*! @{ */ #define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU) #define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U) /*! DATA0_SIZE - DATA0_SIZE */ #define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U) /*! GF13_0_GF14_1 - GF13_0_GF14_1 */ #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK) #define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U) #define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U) /*! ECC0 - ECC0 * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK) #define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U) /*! META_SIZE - META_SIZE */ #define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK) #define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U) /*! NBLOCKS - NBLOCKS */ #define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */ /*! @{ */ #define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU) #define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U) /*! DATAN_SIZE - DATAN_SIZE */ #define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U) /*! GF13_0_GF14_1 - GF13_0_GF14_1 */ #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK) #define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U) #define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U) /*! ECCN - ECCN * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK) #define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U) /*! PAGE_SIZE - PAGE_SIZE */ #define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */ /*! @{ */ #define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU) #define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U) /*! DATA0_SIZE - DATA0_SIZE */ #define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U) /*! GF13_0_GF14_1 - GF13_0_GF14_1 */ #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK) #define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U) #define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U) /*! ECC0 - ECC0 * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK) #define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U) /*! META_SIZE - META_SIZE */ #define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK) #define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U) /*! NBLOCKS - NBLOCKS */ #define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */ /*! @{ */ #define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU) #define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U) /*! DATAN_SIZE - DATAN_SIZE */ #define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U) /*! GF13_0_GF14_1 - GF13_0_GF14_1 */ #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK) #define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U) #define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U) /*! ECCN - ECCN * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK) #define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U) /*! PAGE_SIZE - PAGE_SIZE */ #define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */ /*! @{ */ #define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU) #define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U) /*! DATA0_SIZE - DATA0_SIZE */ #define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U) /*! GF13_0_GF14_1 - GF13_0_GF14_1 */ #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK) #define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U) #define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U) /*! ECC0 - ECC0 * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK) #define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U) /*! META_SIZE - META_SIZE */ #define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK) #define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U) /*! NBLOCKS - NBLOCKS */ #define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */ /*! @{ */ #define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU) #define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U) /*! DATAN_SIZE - DATAN_SIZE */ #define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U) /*! GF13_0_GF14_1 - GF13_0_GF14_1 */ #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK) #define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U) #define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U) /*! ECCN - ECCN * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK) #define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U) /*! PAGE_SIZE - PAGE_SIZE */ #define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */ /*! @{ */ #define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU) #define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U) /*! DATA0_SIZE - DATA0_SIZE */ #define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U) /*! GF13_0_GF14_1 - GF13_0_GF14_1 */ #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK) #define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U) #define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U) /*! ECC0 - ECC0 * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK) #define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U) #define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U) /*! META_SIZE - META_SIZE */ #define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK) #define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U) #define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U) /*! NBLOCKS - NBLOCKS */ #define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK) /*! @} */ /*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */ /*! @{ */ #define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU) #define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U) /*! DATAN_SIZE - DATAN_SIZE */ #define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U) #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U) /*! GF13_0_GF14_1 - GF13_0_GF14_1 */ #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK) #define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U) #define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U) /*! ECCN - ECCN * 0b00000..No ECC to be performed * 0b00001..ECC 2 to be performed * 0b00010..ECC 4 to be performed * 0b11110..ECC 60 to be performed * 0b11111..ECC 62 to be performed */ #define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK) #define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) #define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U) /*! PAGE_SIZE - PAGE_SIZE */ #define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) /*! @} */ /*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */ /*! @{ */ #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU) #define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U) /*! DEBUG_REG_SELECT - DEBUG_REG_SELECT */ #define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK) #define BCH_DEBUG0_RSVD0_MASK (0xC0U) #define BCH_DEBUG0_RSVD0_SHIFT (6U) /*! RSVD0 - This field is reserved. */ #define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK) #define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U) #define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U) /*! BM_KES_TEST_BYPASS - BM_KES_TEST_BYPASS * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK) #define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U) #define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U) /*! KES_DEBUG_STALL - KES_DEBUG_STALL * 0b0..KES FSM proceeds to next block supplied by bus master. * 0b1..KES FSM waits after current equations are solved and the search engine is started. */ #define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK) #define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U) #define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U) /*! KES_DEBUG_STEP - KES_DEBUG_STEP */ #define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK) #define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U) #define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U) /*! KES_STANDALONE - KES_STANDALONE * 0b0..Bus master address generator for SYND_GEN writes operates normally. * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK) #define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U) #define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U) /*! KES_DEBUG_KICK - KES_DEBUG_KICK */ #define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK) #define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U) #define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U) /*! KES_DEBUG_MODE4K - KES_DEBUG_MODE4K * 0b1..Mode is set for 4K NAND pages. * 0b1..Mode is set for 2K NAND pages. */ #define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK) #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) /*! KES_DEBUG_PAYLOAD_FLAG - KES_DEBUG_PAYLOAD_FLAG * 0b1..Payload is set for 512 bytes data block. * 0b1..Payload is set for 65 or 19 bytes auxiliary block. */ #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK) #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U) /*! KES_DEBUG_SHIFT_SYND - KES_DEBUG_SHIFT_SYND */ #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) /*! KES_DEBUG_SYNDROME_SYMBOL - KES_DEBUG_SYNDROME_SYMBOL * 0b000000000..Bus master address generator for SYND_GEN writes operates normally. * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block. */ #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) #define BCH_DEBUG0_RSVD1_MASK (0xFE000000U) #define BCH_DEBUG0_RSVD1_SHIFT (25U) /*! RSVD1 - This field is reserved. */ #define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK) /*! @} */ /*! @name DBGKESREAD - KES Debug Read Register */ /*! @{ */ #define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGKESREAD_VALUES_SHIFT (0U) /*! VALUES - VALUES */ #define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK) /*! @} */ /*! @name DBGCSFEREAD - Chien Search Debug Read Register */ /*! @{ */ #define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGCSFEREAD_VALUES_SHIFT (0U) /*! VALUES - VALUES */ #define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK) /*! @} */ /*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */ /*! @{ */ #define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U) /*! VALUES - VALUES */ #define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK) /*! @} */ /*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */ /*! @{ */ #define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU) #define BCH_DBGAHBMREAD_VALUES_SHIFT (0U) /*! VALUES - VALUES */ #define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK) /*! @} */ /*! @name BLOCKNAME - Block Name Register */ /*! @{ */ #define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU) #define BCH_BLOCKNAME_NAME_SHIFT (0U) /*! NAME - NAME */ #define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK) /*! @} */ /*! @name VERSION - BCH Version Register */ /*! @{ */ #define BCH_VERSION_STEP_MASK (0xFFFFU) #define BCH_VERSION_STEP_SHIFT (0U) /*! STEP - STEP */ #define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK) #define BCH_VERSION_MINOR_MASK (0xFF0000U) #define BCH_VERSION_MINOR_SHIFT (16U) /*! MINOR - MINOR */ #define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK) #define BCH_VERSION_MAJOR_MASK (0xFF000000U) #define BCH_VERSION_MAJOR_SHIFT (24U) /*! MAJOR - MAJOR */ #define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK) /*! @} */ /*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */ /*! @{ */ #define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU) #define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U) /*! ERASED_ZERO_COUNT - ERASED_ZERO_COUNT */ #define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) #define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U) #define BCH_DEBUG1_RSVD_SHIFT (9U) /*! RSVD - This field is reserved. */ #define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK) #define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U) #define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U) /*! DEBUG1_PREERASECHK - DEBUG1_PREERASECHK * 0b0..Turn off pre-erase check * 0b1..Turn on pre-erase check */ #define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK) /*! @} */ /*! * @} */ /* end of group BCH_Register_Masks */ /* BCH - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__BCH base address */ #define CONNECTIVITY__BCH_BASE (0x5B814000u) /** Peripheral CONNECTIVITY__BCH base pointer */ #define CONNECTIVITY__BCH ((BCH_Type *)CONNECTIVITY__BCH_BASE) /** Array initializer of BCH peripheral base addresses */ #define BCH_BASE_ADDRS { CONNECTIVITY__BCH_BASE } /** Array initializer of BCH peripheral base pointers */ #define BCH_BASE_PTRS { CONNECTIVITY__BCH } /*! * @} */ /* end of group BCH_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAN Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer * @{ */ /** CAN - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< Module Configuration register, offset: 0x0 */ __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */ __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask register, offset: 0x10 */ __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */ __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */ __IO uint32_t IMASK2; /**< Interrupt Masks 2 register, offset: 0x24 */ __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ __IO uint32_t IFLAG2; /**< Interrupt Flags 2 register, offset: 0x2C */ __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */ __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */ __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */ uint8_t RESERVED_1[8]; __I uint32_t CRCR; /**< CRC register, offset: 0x44 */ __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */ __I uint32_t RXFIR; /**< Rx FIFO Information register, offset: 0x4C */ __IO uint32_t CBT; /**< CAN Bit Timing register, offset: 0x50 */ uint8_t RESERVED_2[4]; __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ uint8_t RESERVED_3[32]; struct { /* offset: 0x80, array step: 0x10 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ } MB[64]; uint8_t RESERVED_4[1024]; __IO uint32_t RXIMR[64]; /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */ uint8_t RESERVED_5[640]; __IO uint32_t FDCTRL; /**< CAN FD Control register, offset: 0xC00 */ __IO uint32_t FDCBT; /**< CAN FD Bit Timing register, offset: 0xC04 */ __I uint32_t FDCRC; /**< CAN FD CRC register, offset: 0xC08 */ } CAN_Type; /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Register_Masks CAN Register Masks * @{ */ /*! @name MCR - Module Configuration register */ /*! @{ */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) /*! MAXMB - Number Of The Last Message Buffer */ #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) #define CAN_MCR_IDAM_MASK (0x300U) #define CAN_MCR_IDAM_SHIFT (8U) /*! IDAM - ID Acceptance Mode * 0b00..Format A: One full ID (standard and extended) per ID filter table element. * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. * 0b11..Format D: All frames rejected. */ #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) #define CAN_MCR_FDEN_MASK (0x800U) #define CAN_MCR_FDEN_SHIFT (11U) /*! FDEN - CAN FD operation enable * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. */ #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) /*! AEN - Abort Enable * 0b0..Abort disabled. * 0b1..Abort enabled. */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) /*! LPRIOEN - Local Priority Enable * 0b0..Local Priority disabled. * 0b1..Local Priority enabled. */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) #define CAN_MCR_DMA_MASK (0x8000U) #define CAN_MCR_DMA_SHIFT (15U) /*! DMA - DMA Enable * 0b0..DMA feature for RX FIFO disabled. * 0b1..DMA feature for RX FIFO enabled. */ #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) /*! IRMQ - Individual Rx Masking And Queue Enable * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy * applications, the reading of C/S word locks the MB even if it is EMPTY. * 0b1..Individual Rx masking and queue feature are enabled. */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) /*! SRXDIS - Self Reception Disable * 0b0..Self-reception enabled. * 0b1..Self-reception disabled. */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) #define CAN_MCR_DOZE_MASK (0x40000U) #define CAN_MCR_DOZE_SHIFT (18U) /*! DOZE - Doze Mode Enable * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested. * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested. */ #define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) /*! WAKSRC - Wake Up Source * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) /*! LPMACK - Low-Power Mode Acknowledge * 0b0..FlexCAN is not in a low-power mode. * 0b1..FlexCAN is in a low-power mode. */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) /*! WRNEN - Warning Interrupt Enable * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) /*! SLFWAK - Self Wake Up * 0b0..FlexCAN Self Wake Up feature is disabled. * 0b1..FlexCAN Self Wake Up feature is enabled. */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) /*! FRZACK - Freeze Mode Acknowledge * 0b0..FlexCAN not in Freeze mode, prescaler running. * 0b1..FlexCAN in Freeze mode, prescaler stopped. */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) /*! SOFTRST - Soft Reset * 0b0..No reset request. * 0b1..Resets the registers affected by soft reset. */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) /*! WAKMSK - Wake Up Interrupt Mask * 0b0..Wake Up interrupt is disabled. * 0b1..Wake Up interrupt is enabled. */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) /*! NOTRDY - FlexCAN Not Ready * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode. * 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode. */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) /*! HALT - Halt FlexCAN * 0b0..No Freeze mode request. * 0b1..Enters Freeze mode if the FRZ bit is asserted. */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) /*! RFEN - Rx FIFO Enable * 0b0..Rx FIFO not enabled. * 0b1..Rx FIFO enabled. */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) /*! FRZ - Freeze Enable * 0b0..Not enabled to enter Freeze mode. * 0b1..Enabled to enter Freeze mode. */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) /*! MDIS - Module Disable * 0b0..Enable the FlexCAN module. * 0b1..Disable the FlexCAN module. */ #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) /*! @} */ /*! @name CTRL1 - Control 1 register */ /*! @{ */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) #define CAN_CTRL1_PROPSEG_SHIFT (0U) /*! PROPSEG - Propagation Segment */ #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) #define CAN_CTRL1_LOM_MASK (0x8U) #define CAN_CTRL1_LOM_SHIFT (3U) /*! LOM - Listen-Only Mode * 0b0..Listen-Only mode is deactivated. * 0b1..FlexCAN module operates in Listen-Only mode. */ #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) #define CAN_CTRL1_LBUF_MASK (0x10U) #define CAN_CTRL1_LBUF_SHIFT (4U) /*! LBUF - Lowest Buffer Transmitted First * 0b0..Buffer with highest priority is transmitted first. * 0b1..Lowest number buffer is transmitted first. */ #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) /*! TSYN - Timer Sync * 0b0..Timer sync feature disabled * 0b1..Timer sync feature enabled */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) /*! BOFFREC - Bus Off Recovery * 0b0..Automatic recovering from Bus Off state enabled. * 0b1..Automatic recovering from Bus Off state disabled. */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) /*! SMP - CAN Bit Sampling * 0b0..Just one sample is used to determine the bit value. * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two * preceding samples; a majority rule is used. */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) /*! RWRNMSK - Rx Warning Interrupt Mask * 0b0..Rx Warning interrupt disabled. * 0b1..Rx Warning interrupt enabled. */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) /*! TWRNMSK - Tx Warning Interrupt Mask * 0b0..Tx Warning interrupt disabled. * 0b1..Tx Warning interrupt enabled. */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) /*! LPB - Loop Back Mode * 0b0..Loop Back disabled. * 0b1..Loop Back enabled. */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_CLKSRC_MASK (0x2000U) #define CAN_CTRL1_CLKSRC_SHIFT (13U) /*! CLKSRC - CAN Engine Clock Source * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. * 0b1..The CAN engine clock source is the peripheral clock. */ #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) /*! ERRMSK - Error Interrupt Mask * 0b0..Error interrupt disabled. * 0b1..Error interrupt enabled. */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) /*! BOFFMSK - Bus Off Interrupt Mask * 0b0..Bus Off interrupt disabled. * 0b1..Bus Off interrupt enabled. */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) #define CAN_CTRL1_PSEG2_MASK (0x70000U) #define CAN_CTRL1_PSEG2_SHIFT (16U) /*! PSEG2 - Phase Segment 2 */ #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) #define CAN_CTRL1_PSEG1_MASK (0x380000U) #define CAN_CTRL1_PSEG1_SHIFT (19U) /*! PSEG1 - Phase Segment 1 */ #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) #define CAN_CTRL1_RJW_MASK (0xC00000U) #define CAN_CTRL1_RJW_SHIFT (22U) /*! RJW - Resync Jump Width */ #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) #define CAN_CTRL1_PRESDIV_SHIFT (24U) /*! PRESDIV - Prescaler Division Factor */ #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) /*! @} */ /*! @name TIMER - Free Running Timer */ /*! @{ */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) #define CAN_TIMER_TIMER_SHIFT (0U) /*! TIMER - Timer Value */ #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) /*! @} */ /*! @name RXMGMASK - Rx Mailboxes Global Mask register */ /*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) /*! MG - Rx Mailboxes Global Mask Bits */ #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) /*! @} */ /*! @name RX14MASK - Rx 14 Mask register */ /*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) /*! RX14M - Rx Buffer 14 Mask Bits */ #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) /*! @} */ /*! @name RX15MASK - Rx 15 Mask register */ /*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) /*! RX15M - Rx Buffer 15 Mask Bits */ #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) /*! @} */ /*! @name ECR - Error Counter */ /*! @{ */ #define CAN_ECR_TXERRCNT_MASK (0xFFU) #define CAN_ECR_TXERRCNT_SHIFT (0U) /*! TXERRCNT - Transmit Error Counter */ #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) #define CAN_ECR_RXERRCNT_MASK (0xFF00U) #define CAN_ECR_RXERRCNT_SHIFT (8U) /*! RXERRCNT - Receive Error Counter */ #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) #define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) #define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) /*! TXERRCNT_FAST - Transmit Error Counter for fast bits */ #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) #define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) #define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) /*! RXERRCNT_FAST - Receive Error Counter for fast bits */ #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) /*! @} */ /*! @name ESR1 - Error and Status 1 register */ /*! @{ */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) /*! WAKINT - Wake-Up Interrupt * 0b0..No such occurrence. * 0b1..Indicates a recessive to dominant transition was received on the CAN bus. */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) /*! ERRINT - Error Interrupt * 0b0..No such occurrence. * 0b1..Indicates setting of any error bit in the Error and Status register. */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) /*! BOFFINT - Bus Off Interrupt * 0b0..No such occurrence. * 0b1..FlexCAN module entered Bus Off state. */ #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) /*! RX - FlexCAN In Reception * 0b0..FlexCAN is not receiving a message. * 0b1..FlexCAN is receiving a message. */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) #define CAN_ESR1_FLTCONF_MASK (0x30U) #define CAN_ESR1_FLTCONF_SHIFT (4U) /*! FLTCONF - Fault Confinement State * 0b00..Error Active * 0b01..Error Passive * 0b1x..Bus Off */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) /*! TX - FlexCAN In Transmission * 0b0..FlexCAN is not transmitting a message. * 0b1..FlexCAN is transmitting a message. */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) /*! IDLE - IDLE * 0b0..No such occurrence. * 0b1..CAN bus is now IDLE. */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) /*! RXWRN - Rx Error Warning * 0b0..No such occurrence. * 0b1..RXERRCNT is greater than or equal to 96. */ #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) /*! TXWRN - TX Error Warning * 0b0..No such occurrence. * 0b1..TXERRCNT is greater than or equal to 96. */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) /*! STFERR - Stuffing Error * 0b0..No such occurrence. * 0b1..A stuffing error occurred since last read of this register. */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) /*! FRMERR - Form Error * 0b0..No such occurrence. * 0b1..A Form Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) /*! CRCERR - Cyclic Redundancy Check Error * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) /*! ACKERR - Acknowledge Error * 0b0..No such occurrence. * 0b1..An ACK error occurred since last read of this register. */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) /*! BIT0ERR - Bit0 Error * 0b0..No such occurrence. * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) /*! BIT1ERR - Bit1 Error * 0b0..No such occurrence. * 0b1..At least one bit sent as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) /*! RWRNINT - Rx Warning Interrupt Flag * 0b0..No such occurrence. * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) /*! TWRNINT - Tx Warning Interrupt Flag * 0b0..No such occurrence. * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) /*! SYNCH - CAN Synchronization Status * 0b0..FlexCAN is not synchronized to the CAN bus. * 0b1..FlexCAN is synchronized to the CAN bus. */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) #define CAN_ESR1_BOFFDONEINT_SHIFT (19U) /*! BOFFDONEINT - Bus Off Done Interrupt * 0b0..No such occurrence. * 0b1..FlexCAN module has completed Bus Off process. */ #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) /*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set * 0b0..No such occurrence. * 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set. */ #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) #define CAN_ESR1_ERROVR_MASK (0x200000U) #define CAN_ESR1_ERROVR_SHIFT (21U) /*! ERROVR - Error Overrun * 0b0..Overrun has not occurred. * 0b1..Overrun has occurred. */ #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) #define CAN_ESR1_STFERR_FAST_SHIFT (26U) /*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A stuffing error occurred since last read of this register. */ #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) /*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A form error occurred since last read of this register. */ #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) /*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. */ #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) /*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) /*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set * 0b0..No such occurrence. * 0b1..At least one bit sent as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) /*! @} */ /*! @name IMASK2 - Interrupt Masks 2 register */ /*! @{ */ #define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) #define CAN_IMASK2_BUF63TO32M_SHIFT (0U) /*! BUF63TO32M - Buffer MBi Mask */ #define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK) /*! @} */ /*! @name IMASK1 - Interrupt Masks 1 register */ /*! @{ */ #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) #define CAN_IMASK1_BUF31TO0M_SHIFT (0U) /*! BUF31TO0M - Buffer MBi Mask */ #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) /*! @} */ /*! @name IFLAG2 - Interrupt Flags 2 register */ /*! @{ */ #define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) #define CAN_IFLAG2_BUF63TO32I_SHIFT (0U) /*! BUF63TO32I - Buffer MBi Interrupt */ #define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK) /*! @} */ /*! @name IFLAG1 - Interrupt Flags 1 register */ /*! @{ */ #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) /*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. */ #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) /*! BUF4TO1I - Buffer MBi Interrupt Or Reserved */ #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) /*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when * MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) /*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) /*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) /*! BUF31TO8I - Buffer MBi Interrupt */ #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) /*! @} */ /*! @name CTRL2 - Control 2 register */ /*! @{ */ #define CAN_CTRL2_EDFLTDIS_MASK (0x800U) #define CAN_CTRL2_EDFLTDIS_SHIFT (11U) /*! EDFLTDIS - Edge Filter Disable * 0b0..Edge filter is enabled * 0b1..Edge filter is disabled */ #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) #define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) #define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) /*! ISOCANFDEN - ISO CAN FD Enable * 0b0..FlexCAN operates using the non-ISO CAN FD protocol. * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). */ #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) #define CAN_CTRL2_PREXCEN_MASK (0x4000U) #define CAN_CTRL2_PREXCEN_SHIFT (14U) /*! PREXCEN - Protocol Exception Enable * 0b0..Protocol exception is disabled. * 0b1..Protocol exception is enabled. */ #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes * 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. * 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within * the incoming frame. Mask bits do apply. */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) /*! RRS - Remote Request Storing * 0b0..Remote response frame is generated. * 0b1..Remote request frame is stored. */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) /*! MRP - Mailboxes Reception Priority * 0b0..Matching starts from Rx FIFO and continues on mailboxes. * 0b1..Matching starts from mailboxes and continues on Rx FIFO. */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) /*! TASD - Tx Arbitration Start Delay */ #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) #define CAN_CTRL2_RFFN_MASK (0xF000000U) #define CAN_CTRL2_RFFN_SHIFT (24U) /*! RFFN - Number Of Rx FIFO Filters */ #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) /*! BOFFDONEMSK - Bus Off Done Interrupt Mask * 0b0..Bus off done interrupt disabled. * 0b1..Bus off done interrupt enabled. */ #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) /*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames * 0b0..ERRINT_FAST error interrupt disabled. * 0b1..ERRINT_FAST error interrupt enabled. */ #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) /*! @} */ /*! @name ESR2 - Error and Status 2 register */ /*! @{ */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) /*! IMB - Inactive Mailbox * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox. * 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one. */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) /*! VPS - Valid Priority Status * 0b0..Contents of IMB and LPTM are invalid. * 0b1..Contents of IMB and LPTM are valid. */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) /*! LPTM - Lowest Priority Tx Mailbox */ #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) /*! @} */ /*! @name CRCR - CRC register */ /*! @{ */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) #define CAN_CRCR_TXCRC_SHIFT (0U) /*! TXCRC - Transmitted CRC value */ #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) /*! MBCRC - CRC Mailbox */ #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) /*! @} */ /*! @name RXFGMASK - Rx FIFO Global Mask register */ /*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) /*! FGM - Rx FIFO Global Mask Bits */ #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) /*! @} */ /*! @name RXFIR - Rx FIFO Information register */ /*! @{ */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) #define CAN_RXFIR_IDHIT_SHIFT (0U) /*! IDHIT - Identifier Acceptance Filter Hit Indicator */ #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) /*! @} */ /*! @name CBT - CAN Bit Timing register */ /*! @{ */ #define CAN_CBT_EPSEG2_MASK (0x1FU) #define CAN_CBT_EPSEG2_SHIFT (0U) /*! EPSEG2 - Extended Phase Segment 2 */ #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) #define CAN_CBT_EPSEG1_MASK (0x3E0U) #define CAN_CBT_EPSEG1_SHIFT (5U) /*! EPSEG1 - Extended Phase Segment 1 */ #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) #define CAN_CBT_EPROPSEG_MASK (0xFC00U) #define CAN_CBT_EPROPSEG_SHIFT (10U) /*! EPROPSEG - Extended Propagation Segment */ #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) #define CAN_CBT_ERJW_MASK (0x1F0000U) #define CAN_CBT_ERJW_SHIFT (16U) /*! ERJW - Extended Resync Jump Width */ #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) #define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) #define CAN_CBT_EPRESDIV_SHIFT (21U) /*! EPRESDIV - Extended Prescaler Division Factor */ #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) #define CAN_CBT_BTF_MASK (0x80000000U) #define CAN_CBT_BTF_SHIFT (31U) /*! BTF - Bit Timing Format Enable * 0b0..Extended bit time definitions disabled. * 0b1..Extended bit time definitions enabled. */ #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) /*! @} */ /*! @name DBG1 - Debug 1 register */ /*! @{ */ #define CAN_DBG1_CFSM_MASK (0x7FU) #define CAN_DBG1_CFSM_SHIFT (0U) /*! CFSM - CAN Finite State Machine */ #define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) #define CAN_DBG1_CBN_MASK (0x3FF0000U) #define CAN_DBG1_CBN_SHIFT (16U) /*! CBN - CAN Bit Number */ #define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) /*! @} */ /*! @name DBG2 - Debug 2 register */ /*! @{ */ #define CAN_DBG2_RMP_MASK (0x7FU) #define CAN_DBG2_RMP_SHIFT (0U) /*! RMP - Rx Matching Pointer */ #define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK) #define CAN_DBG2_MPP_MASK (0x80U) #define CAN_DBG2_MPP_SHIFT (7U) /*! MPP - Matching Process in Progress * 0b0..No matching process ongoing * 0b1..Matching process is in progress. */ #define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK) #define CAN_DBG2_TAP_MASK (0x7F00U) #define CAN_DBG2_TAP_SHIFT (8U) /*! TAP - Tx Arbitration Pointer */ #define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK) #define CAN_DBG2_APP_MASK (0x8000U) #define CAN_DBG2_APP_SHIFT (15U) /*! APP - Arbitration Process in Progress * 0b0..No arbitration process ongoing * 0b1..Arbitration process is in progress. */ #define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK) /*! @} */ /*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ /*! @{ */ #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) #define CAN_CS_TIME_STAMP_SHIFT (0U) /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field * appears on the CAN bus. */ #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) #define CAN_CS_DLC_MASK (0xF0000U) #define CAN_CS_DLC_SHIFT (16U) /*! DLC - Length of the data to be stored/transmitted. */ #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) #define CAN_CS_RTR_MASK (0x100000U) #define CAN_CS_RTR_SHIFT (20U) /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */ #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) #define CAN_CS_IDE_MASK (0x200000U) #define CAN_CS_IDE_SHIFT (21U) /*! IDE - ID Extended. One/zero for extended/standard format frame. */ #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) #define CAN_CS_SRR_MASK (0x400000U) #define CAN_CS_SRR_SHIFT (22U) /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */ #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) #define CAN_CS_CODE_MASK (0xF000000U) #define CAN_CS_CODE_SHIFT (24U) /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by * the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) #define CAN_CS_ESI_MASK (0x20000000U) #define CAN_CS_ESI_SHIFT (29U) /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ #define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) #define CAN_CS_BRS_MASK (0x40000000U) #define CAN_CS_BRS_SHIFT (30U) /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ #define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) #define CAN_CS_EDL_MASK (0x80000000U) #define CAN_CS_EDL_SHIFT (31U) /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ #define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) /*! @} */ /* The count of CAN_CS */ #define CAN_CS_COUNT (64U) /*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ /*! @{ */ #define CAN_ID_EXT_MASK (0x3FFFFU) #define CAN_ID_EXT_SHIFT (0U) /*! EXT - Contains extended (LOW word) identifier of message buffer. */ #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) #define CAN_ID_STD_MASK (0x1FFC0000U) #define CAN_ID_STD_SHIFT (18U) /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */ #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) #define CAN_ID_PRIO_MASK (0xE0000000U) #define CAN_ID_PRIO_SHIFT (29U) /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular * ID to define the transmission priority. */ #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) /*! @} */ /* The count of CAN_ID */ #define CAN_ID_COUNT (64U) /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ /*! @{ */ #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) /*! @} */ /* The count of CAN_WORD0 */ #define CAN_WORD0_COUNT (64U) /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ /*! @{ */ #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) /*! @} */ /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (64U) /*! @name RXIMR - Rx Individual Mask registers */ /*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) /*! MI - Individual Mask Bits */ #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) /*! @} */ /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (64U) /*! @name FDCTRL - CAN FD Control register */ /*! @{ */ #define CAN_FDCTRL_TDCVAL_MASK (0x3FU) #define CAN_FDCTRL_TDCVAL_SHIFT (0U) /*! TDCVAL - Transceiver Delay Compensation Value */ #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) #define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) #define CAN_FDCTRL_TDCOFF_SHIFT (8U) /*! TDCOFF - Transceiver Delay Compensation Offset */ #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) #define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) #define CAN_FDCTRL_TDCFAIL_SHIFT (14U) /*! TDCFAIL - Transceiver Delay Compensation Fail * 0b0..Measured loop delay is in range. * 0b1..Measured loop delay is out of range. */ #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) #define CAN_FDCTRL_TDCEN_MASK (0x8000U) #define CAN_FDCTRL_TDCEN_SHIFT (15U) /*! TDCEN - Transceiver Delay Compensation Enable * 0b0..TDC is disabled * 0b1..TDC is enabled */ #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) #define CAN_FDCTRL_MBDSR0_MASK (0x30000U) #define CAN_FDCTRL_MBDSR0_SHIFT (16U) /*! MBDSR0 - Message Buffer Data Size for Region 0 * 0b00..Selects 8 bytes per message buffer. * 0b01..Selects 16 bytes per message buffer. * 0b10..Selects 32 bytes per message buffer. * 0b11..Selects 64 bytes per message buffer. */ #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) #define CAN_FDCTRL_MBDSR1_MASK (0x180000U) #define CAN_FDCTRL_MBDSR1_SHIFT (19U) /*! MBDSR1 - Message Buffer Data Size for Region 1 * 0b00..Selects 8 bytes per message buffer. * 0b01..Selects 16 bytes per message buffer. * 0b10..Selects 32 bytes per message buffer. * 0b11..Selects 64 bytes per message buffer. */ #define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK) #define CAN_FDCTRL_FDRATE_MASK (0x80000000U) #define CAN_FDCTRL_FDRATE_SHIFT (31U) /*! FDRATE - Bit Rate Switch Enable * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. */ #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) /*! @} */ /*! @name FDCBT - CAN FD Bit Timing register */ /*! @{ */ #define CAN_FDCBT_FPSEG2_MASK (0x7U) #define CAN_FDCBT_FPSEG2_SHIFT (0U) /*! FPSEG2 - Fast Phase Segment 2 */ #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) #define CAN_FDCBT_FPSEG1_MASK (0xE0U) #define CAN_FDCBT_FPSEG1_SHIFT (5U) /*! FPSEG1 - Fast Phase Segment 1 */ #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) #define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) #define CAN_FDCBT_FPROPSEG_SHIFT (10U) /*! FPROPSEG - Fast Propagation Segment */ #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) #define CAN_FDCBT_FRJW_MASK (0x70000U) #define CAN_FDCBT_FRJW_SHIFT (16U) /*! FRJW - Fast Resync Jump Width */ #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) #define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) #define CAN_FDCBT_FPRESDIV_SHIFT (20U) /*! FPRESDIV - Fast Prescaler Division Factor */ #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) /*! @} */ /*! @name FDCRC - CAN FD CRC register */ /*! @{ */ #define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) #define CAN_FDCRC_FD_TXCRC_SHIFT (0U) /*! FD_TXCRC - Extended Transmitted CRC value */ #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) #define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) #define CAN_FDCRC_FD_MBCRC_SHIFT (24U) /*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC */ #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) /*! @} */ /*! * @} */ /* end of group CAN_Register_Masks */ /* CAN - Peripheral instance base addresses */ /** Peripheral ADMA__CAN0 base address */ #define ADMA__CAN0_BASE (0x5A8D0000u) /** Peripheral ADMA__CAN0 base pointer */ #define ADMA__CAN0 ((CAN_Type *)ADMA__CAN0_BASE) /** Peripheral ADMA__CAN1 base address */ #define ADMA__CAN1_BASE (0x5A8E0000u) /** Peripheral ADMA__CAN1 base pointer */ #define ADMA__CAN1 ((CAN_Type *)ADMA__CAN1_BASE) /** Peripheral ADMA__CAN2 base address */ #define ADMA__CAN2_BASE (0x5A8F0000u) /** Peripheral ADMA__CAN2 base pointer */ #define ADMA__CAN2 ((CAN_Type *)ADMA__CAN2_BASE) /** Array initializer of CAN peripheral base addresses */ #define CAN_BASE_ADDRS { ADMA__CAN0_BASE, ADMA__CAN1_BASE, ADMA__CAN2_BASE } /** Array initializer of CAN peripheral base pointers */ #define CAN_BASE_PTRS { ADMA__CAN0, ADMA__CAN1, ADMA__CAN2 } /** Interrupt vectors for the CAN peripheral type */ #define CAN_Rx_Warning_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn } #define CAN_Tx_Warning_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn } #define CAN_Wake_Up_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn } #define CAN_Error_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn } #define CAN_Bus_Off_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn } #define CAN_ORed_Message_buffer_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn } /*! * @} */ /* end of group CAN_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CI_PI_CSR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CI_PI_CSR_Peripheral_Access_Layer CI_PI_CSR Peripheral Access Layer * @{ */ /** CI_PI_CSR - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< CI_PI Interface Control Register, offset: 0x0 */ __IO uint32_t SET; /**< CI_PI Interface Control Register, offset: 0x4 */ __IO uint32_t CLR; /**< CI_PI Interface Control Register, offset: 0x8 */ __IO uint32_t TOG; /**< CI_PI Interface Control Register, offset: 0xC */ } IF_CTRL_REG; struct { /* offset: 0x10 */ __IO uint32_t RW; /**< CSI Interface Control Register, offset: 0x10 */ __IO uint32_t SET; /**< CSI Interface Control Register, offset: 0x14 */ __IO uint32_t CLR; /**< CSI Interface Control Register, offset: 0x18 */ __IO uint32_t TOG; /**< CSI Interface Control Register, offset: 0x1C */ } CSI_CTRL_REG; struct { /* offset: 0x20 */ __I uint32_t RW; /**< CSI Interface Status Register, offset: 0x20 */ __I uint32_t SET; /**< CSI Interface Status Register, offset: 0x24 */ __I uint32_t CLR; /**< CSI Interface Status Register, offset: 0x28 */ __I uint32_t TOG; /**< CSI Interface Status Register, offset: 0x2C */ } CSI_STATUS; struct { /* offset: 0x30 */ __IO uint32_t RW; /**< CSI Interface Control Register1, offset: 0x30 */ __IO uint32_t SET; /**< CSI Interface Control Register1, offset: 0x34 */ __IO uint32_t CLR; /**< CSI Interface Control Register1, offset: 0x38 */ __IO uint32_t TOG; /**< CSI Interface Control Register1, offset: 0x3C */ } CSI_CTRL_REG1; } CI_PI_CSR_Type; /* ---------------------------------------------------------------------------- -- CI_PI_CSR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CI_PI_CSR_Register_Masks CI_PI_CSR Register Masks * @{ */ /*! @name IF_CTRL_REG - CI_PI Interface Control Register */ /*! @{ */ #define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK (0x1U) #define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT (0U) #define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK) #define CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK (0x2U) #define CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT (1U) #define CI_PI_CSR_IF_CTRL_REG_PL_VALID(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK) #define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK (0x1CU) #define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT (2U) #define CI_PI_CSR_IF_CTRL_REG_PL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK) #define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK (0xE0U) #define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT (5U) #define CI_PI_CSR_IF_CTRL_REG_IF_FORCE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK) #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK (0x100U) #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT (8U) /*! DATA_TYPE_SEL - Pixel link data type select * 0b0..PL data type comes from the csi_interface * 0b1..PL data type comes from IF_CTRL DATA_TYPE[4:0] */ #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK) #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK (0x3E00U) #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT (9U) /*! DATA_TYPE - Data type * 0b00000..Null data * 0b00100..RGB format * 0b01000..YUV444 Format * 0b10000..YYU420 odd line * 0b10010..YYU420 even line * 0b11000..YYY odd line * 0b11010..UYVY Even line * 0b11100..Raw */ #define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK) /*! @} */ /*! @name CSI_CTRL_REG - CSI Interface Control Register */ /*! @{ */ #define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK (0x1U) #define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT (0U) /*! CSI_EN - CSI interface enable */ #define CI_PI_CSR_CSI_CTRL_REG_CSI_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK (0x2U) #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT (1U) /*! PIXEL_CLK_POL - Pixel Clock polarity control * 0b0..Pixel Clock input is not inverted * 0b1..Pixel Clock input is inverted */ #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK) #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK (0x4U) #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT (2U) /*! HSYNC_POL - HSYNC polarity control * 0b0..HSYNC output to Pixel Link is not inverted * 0b1..HSYNC output to Pixel Link is inverted */ #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK) #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK (0x8U) #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT (3U) /*! VSYNC_POL - VSYNC polarity control * 0b0..VSYNC output to Pixel Link is not inverted * 0b1..VSYNC output to Pixel Link is inverted */ #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK) #define CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK (0x10U) #define CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT (4U) /*! DE_POL - DE polarity control * 0b0..DE output to Pixel Link is not inverted * 0b1..DE output to Pixel Link is inverted */ #define CI_PI_CSR_CSI_CTRL_REG_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK) #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK (0x20U) #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT (5U) /*! PIXEL_DATA_POL - PIXEL_DATA polarity control * 0b0..PIXEL_DATA output to Pixel Link is not inverted * 0b1..PIXEL_DATA output to Pixel Link is inverted */ #define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK (0x40U) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT (6U) /*! CCIR_EXT_VSYNC_EN - External VSYNC enable */ #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK (0x80U) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT (7U) /*! CCIR_EN - CCIR mode enable * 0b0..CCIR mode disable * 0b1..CCIR mode enable */ #define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK (0x100U) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT (8U) /*! CCIR_VIDEO_MODE - CCIR_VIDEO_MODE * 0b0..Progressive mode * 0b1..Interlace mode */ #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK (0x200U) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT (9U) /*! CCIR_NTSC_EN - CCIR_NTSC enable * 0b0..PAL * 0b1..NTSC */ #define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK (0x400U) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT (10U) /*! CCIR_VSYNC_RESET_EN - CCIR_VSYNC_RESET_EN */ #define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK (0x800U) #define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT (11U) /*! CCIR_ECC_ERR_CORRECT_EN - CCIR_ECC_ERR_CORRECT_EN * 0b0..ECC error correction is disabled. * 0b1..ECC error correction is enabled. */ #define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK (0x1000U) #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT (12U) /*! HSYNC_FORCE_EN - HSYNC_FORCE_EN * 0b0..Do not override HSYNC * 0b1..Override HSYNC */ #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK (0x2000U) #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT (13U) /*! VSYNC_FORCE_EN - VSYNC_FORCE_EN * 0b0..Do not override VSYNC * 0b1..Override VSYNC */ #define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK (0x4000U) #define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT (14U) /*! GCLK_MODE_EN - GCLK_MODE_EN * 0b0..Disable * 0b1..Enable */ #define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK (0x8000U) #define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT (15U) /*! VALID_SEL - VALID_SEL */ #define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK) #define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK (0x10000U) #define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT (16U) /*! RAW_OUT_SEL - RAW_OUT_SEL * 0b0..Right justified output * 0b1..Left justified to 14bit output */ #define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK) #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK (0x20000U) #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT (17U) /*! HSYNC_OUT_SEL - HSYNC_OUT_SEL * 0b0..HSYNC output level * 0b1..HSYNC output pulse */ #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK) #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK (0x380000U) #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT (19U) /*! HSYNC_PULSE - HSYNC_PULSE */ #define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK) #define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK (0x400000U) #define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT (22U) /*! UV_SWAP_EN - UV Swap enable * 0b0..UV swap disable * 0b1..UV swap enable */ #define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK (0x7800000U) #define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT (23U) /*! DATA_TYPE_IN - CSI input data type * 0b0000..UYVY bt656 8bit * 0b0001..UYVY bt656 10bit * 0b0010..RGB 8bit * 0b0011..BGR 8bit * 0b0100..RGB 24bit * 0b0101..YVYU 8bit * 0b0110..YUV 8bit * 0b0111..YVYU 16bit * 0b1000..YUV 24bit * 0b1001..Bayer 8bit * 0b1010..Bayer 10bit * 0b1011..Bayer 12bit * 0b1100..Bayer 16bit */ #define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK) #define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK (0x18000000U) #define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT (27U) /*! MASK_VSYNC_COUNTER - CSI mask VSYNC counter * 0b00..not mask * 0b01..mask 1 frame * 0b10..mask 2 frames * 0b11..mask 3 frames */ #define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK) #define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK (0x80000000U) #define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT (31U) /*! SOFTRST - SOFTRST */ #define CI_PI_CSR_CSI_CTRL_REG_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK) /*! @} */ /*! @name CSI_STATUS - CSI Interface Status Register */ /*! @{ */ #define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK (0x1U) #define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT (0U) #define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT)) & CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK) #define CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK (0x2U) #define CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT (1U) #define CI_PI_CSR_CSI_STATUS_ECC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT)) & CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK) /*! @} */ /*! @name CSI_CTRL_REG1 - CSI Interface Control Register1 */ /*! @{ */ #define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK (0xFFFFU) #define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT (0U) /*! PIXEL_WIDTH - CSI interface enable */ #define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK) #define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK (0xFFFF0000U) #define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT (16U) /*! VSYNC_PULSE - VSYNC_PULSE */ #define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK) /*! @} */ /*! * @} */ /* end of group CI_PI_CSR_Register_Masks */ /* CI_PI_CSR - Peripheral instance base addresses */ /** Peripheral CI_PI_CSR base address */ #define CI_PI_CSR_BASE (0x58261000u) /** Peripheral CI_PI_CSR base pointer */ #define CI_PI_CSR ((CI_PI_CSR_Type *)CI_PI_CSR_BASE) /** Array initializer of CI_PI_CSR peripheral base addresses */ #define CI_PI_CSR_BASE_ADDRS { CI_PI_CSR_BASE } /** Array initializer of CI_PI_CSR peripheral base pointers */ #define CI_PI_CSR_BASE_PTRS { CI_PI_CSR } /*! * @} */ /* end of group CI_PI_CSR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPI2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPI2C_Peripheral_Access_Layer CM4_LPCG_LPI2C Peripheral Access Layer * @{ */ /** CM4_LPCG_LPI2C - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPI2C_0; /**< na, offset: 0x0 */ } CM4_LPCG_LPI2C_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPI2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPI2C_Register_Masks CM4_LPCG_LPI2C Register Masks * @{ */ /*! @name LPCG_LPI2C_0 - na */ /*! @{ */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U) /*! lpi2c1_lpi2c_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U) /*! lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U) /*! LPCG_LPI2C_0_reserved_2_2 - reserved */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U) /*! lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U) /*! LPCG_LPI2C_0_reserved_4_4 - reserved */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U) /*! lpi2c1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U) /*! LPCG_LPI2C_0_reserved_6_6 - reserved */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U) /*! lpi2c1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U) #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U) /*! LPCG_LPI2C_0_reserved_8_31 - reserved */ #define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_LPI2C_Register_Masks */ /* CM4_LPCG_LPI2C - Peripheral instance base addresses */ /** Peripheral CM4__LPCG_LPI2C base address */ #define CM4__LPCG_LPI2C_BASE (0x41630000u) /** Peripheral CM4__LPCG_LPI2C base pointer */ #define CM4__LPCG_LPI2C ((CM4_LPCG_LPI2C_Type *)CM4__LPCG_LPI2C_BASE) /** Array initializer of CM4_LPCG_LPI2C peripheral base addresses */ #define CM4_LPCG_LPI2C_BASE_ADDRS { CM4__LPCG_LPI2C_BASE } /** Array initializer of CM4_LPCG_LPI2C peripheral base pointers */ #define CM4_LPCG_LPI2C_BASE_PTRS { CM4__LPCG_LPI2C } /*! * @} */ /* end of group CM4_LPCG_LPI2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPIT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPIT_Peripheral_Access_Layer CM4_LPCG_LPIT Peripheral Access Layer * @{ */ /** CM4_LPCG_LPIT - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPIT_0; /**< na, offset: 0x0 */ } CM4_LPCG_LPIT_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPIT_Register_Masks CM4_LPCG_LPIT Register Masks * @{ */ /*! @name LPCG_LPIT_0 - na */ /*! @{ */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U) /*! lpit1_ipg_per_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U) /*! lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U) /*! LPCG_LPIT_0_reserved_2_2 - reserved */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U) /*! lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP - show clock root status, 1 means clock stopped */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U) /*! LPCG_LPIT_0_reserved_4_4 - reserved */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U) /*! lpit1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U) /*! LPCG_LPIT_0_reserved_6_6 - reserved */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U) /*! lpit1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U) #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U) /*! LPCG_LPIT_0_reserved_8_31 - reserved */ #define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_LPIT_Register_Masks */ /* CM4_LPCG_LPIT - Peripheral instance base addresses */ /** Peripheral CM4__LPCG_LPIT base address */ #define CM4__LPCG_LPIT_BASE (0x41610000u) /** Peripheral CM4__LPCG_LPIT base pointer */ #define CM4__LPCG_LPIT ((CM4_LPCG_LPIT_Type *)CM4__LPCG_LPIT_BASE) /** Array initializer of CM4_LPCG_LPIT peripheral base addresses */ #define CM4_LPCG_LPIT_BASE_ADDRS { CM4__LPCG_LPIT_BASE } /** Array initializer of CM4_LPCG_LPIT peripheral base pointers */ #define CM4_LPCG_LPIT_BASE_PTRS { CM4__LPCG_LPIT } /*! * @} */ /* end of group CM4_LPCG_LPIT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPUART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPUART_Peripheral_Access_Layer CM4_LPCG_LPUART Peripheral Access Layer * @{ */ /** CM4_LPCG_LPUART - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPUART_0; /**< na, offset: 0x0 */ } CM4_LPCG_LPUART_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_LPUART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_LPUART_Register_Masks CM4_LPCG_LPUART Register Masks * @{ */ /*! @name LPCG_LPUART_0 - na */ /*! @{ */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U) /*! lpuart1_lpuart_baud_gated_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U) /*! lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U) /*! LPCG_LPUART_0_reserved_2_2 - reserved */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U) /*! lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U) /*! LPCG_LPUART_0_reserved_4_4 - reserved */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U) /*! lpuart1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U) /*! LPCG_LPUART_0_reserved_6_6 - reserved */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U) /*! lpuart1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U) #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U) /*! LPCG_LPUART_0_reserved_8_31 - reserved */ #define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_LPUART_Register_Masks */ /* CM4_LPCG_LPUART - Peripheral instance base addresses */ /** Peripheral CM4__LPCG_LPUART base address */ #define CM4__LPCG_LPUART_BASE (0x41620000u) /** Peripheral CM4__LPCG_LPUART base pointer */ #define CM4__LPCG_LPUART ((CM4_LPCG_LPUART_Type *)CM4__LPCG_LPUART_BASE) /** Array initializer of CM4_LPCG_LPUART peripheral base addresses */ #define CM4_LPCG_LPUART_BASE_ADDRS { CM4__LPCG_LPUART_BASE } /** Array initializer of CM4_LPCG_LPUART peripheral base pointers */ #define CM4_LPCG_LPUART_BASE_PTRS { CM4__LPCG_LPUART } /*! * @} */ /* end of group CM4_LPCG_LPUART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_MMCAU_HCLK Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer CM4_LPCG_MMCAU_HCLK Peripheral Access Layer * @{ */ /** CM4_LPCG_MMCAU_HCLK - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MMCAU_HCLK_0; /**< na, offset: 0x0 */ } CM4_LPCG_MMCAU_HCLK_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_MMCAU_HCLK Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_MMCAU_HCLK_Register_Masks CM4_LPCG_MMCAU_HCLK Register Masks * @{ */ /*! @name LPCG_MMCAU_HCLK_0 - na */ /*! @{ */ #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U) /*! LPCG_MMCAU_HCLK_0_reserved_0_0 - reserved */ #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U) /*! cm4_mmcau_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U) /*! LPCG_MMCAU_HCLK_0_reserved_2_2 - reserved */ #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U) /*! cm4_mmcau_hclk_STOP - show clock root status, 1 means clock stopped */ #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U) #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U) /*! LPCG_MMCAU_HCLK_0_reserved_4_31 - reserved */ #define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_MMCAU_HCLK_Register_Masks */ /* CM4_LPCG_MMCAU_HCLK - Peripheral instance base addresses */ /** Peripheral CM4__LPCG_MMCAU_HCLK base address */ #define CM4__LPCG_MMCAU_HCLK_BASE (0x415F0000u) /** Peripheral CM4__LPCG_MMCAU_HCLK base pointer */ #define CM4__LPCG_MMCAU_HCLK ((CM4_LPCG_MMCAU_HCLK_Type *)CM4__LPCG_MMCAU_HCLK_BASE) /** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base addresses */ #define CM4_LPCG_MMCAU_HCLK_BASE_ADDRS { CM4__LPCG_MMCAU_HCLK_BASE } /** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base pointers */ #define CM4_LPCG_MMCAU_HCLK_BASE_PTRS { CM4__LPCG_MMCAU_HCLK } /*! * @} */ /* end of group CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_TCMC_HCLK Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer CM4_LPCG_TCMC_HCLK Peripheral Access Layer * @{ */ /** CM4_LPCG_TCMC_HCLK - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_TCMC_HCLK_0; /**< na, offset: 0x0 */ } CM4_LPCG_TCMC_HCLK_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_TCMC_HCLK Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_TCMC_HCLK_Register_Masks CM4_LPCG_TCMC_HCLK Register Masks * @{ */ /*! @name LPCG_TCMC_HCLK_0 - na */ /*! @{ */ #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U) /*! cm4_tcmc_hclk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U) /*! cm4_tcmc_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U) /*! LPCG_TCMC_HCLK_0_reserved_2_2 - reserved */ #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U) /*! cm4_tcmc_hclk_STOP - show clock root status, 1 means clock stopped */ #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U) #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U) /*! LPCG_TCMC_HCLK_0_reserved_4_31 - reserved */ #define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_TCMC_HCLK_Register_Masks */ /* CM4_LPCG_TCMC_HCLK - Peripheral instance base addresses */ /** Peripheral CM4__LPCG_TCMC_HCLK base address */ #define CM4__LPCG_TCMC_HCLK_BASE (0x415E0000u) /** Peripheral CM4__LPCG_TCMC_HCLK base pointer */ #define CM4__LPCG_TCMC_HCLK ((CM4_LPCG_TCMC_HCLK_Type *)CM4__LPCG_TCMC_HCLK_BASE) /** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base addresses */ #define CM4_LPCG_TCMC_HCLK_BASE_ADDRS { CM4__LPCG_TCMC_HCLK_BASE } /** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base pointers */ #define CM4_LPCG_TCMC_HCLK_BASE_PTRS { CM4__LPCG_TCMC_HCLK } /*! * @} */ /* end of group CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CM4_LPCG_TPM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_TPM_Peripheral_Access_Layer CM4_LPCG_TPM Peripheral Access Layer * @{ */ /** CM4_LPCG_TPM - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_TPM_0; /**< na, offset: 0x0 */ } CM4_LPCG_TPM_Type; /* ---------------------------------------------------------------------------- -- CM4_LPCG_TPM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CM4_LPCG_TPM_Register_Masks CM4_LPCG_TPM Register Masks * @{ */ /*! @name LPCG_TPM_0 - na */ /*! @{ */ #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U) /*! LPCG_TPM_0_reserved_0_0 - reserved */ #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U) /*! tpm1_lptpm_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U) /*! LPCG_TPM_0_reserved_2_2 - reserved */ #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U) /*! tpm1_lptpm_clk_STOP - show clock root status, 1 means clock stopped */ #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U) /*! LPCG_TPM_0_reserved_4_4 - reserved */ #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U) /*! tpm1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U) /*! LPCG_TPM_0_reserved_6_6 - reserved */ #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U) #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U) /*! tpm1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U) #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U) /*! LPCG_TPM_0_reserved_8_31 - reserved */ #define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group CM4_LPCG_TPM_Register_Masks */ /* CM4_LPCG_TPM - Peripheral instance base addresses */ /** Peripheral CM4__LPCG_TPM base address */ #define CM4__LPCG_TPM_BASE (0x41600000u) /** Peripheral CM4__LPCG_TPM base pointer */ #define CM4__LPCG_TPM ((CM4_LPCG_TPM_Type *)CM4__LPCG_TPM_BASE) /** Array initializer of CM4_LPCG_TPM peripheral base addresses */ #define CM4_LPCG_TPM_BASE_ADDRS { CM4__LPCG_TPM_BASE } /** Array initializer of CM4_LPCG_TPM peripheral base pointers */ #define CM4_LPCG_TPM_BASE_PTRS { CM4__LPCG_TPM } /*! * @} */ /* end of group CM4_LPCG_TPM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_EDMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer CONNECTIVITY_LPCG_EDMA Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_EDMA - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_EDMA_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_EDMA_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_EDMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_EDMA_Register_Masks CONNECTIVITY_LPCG_EDMA Register Masks * @{ */ /*! @name LPCG_LPCG_EDMA_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK (0x1U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT (0U) /*! edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT (1U) /*! edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_edma_0_reserved_2_2 - reserved */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT (3U) /*! edma_hclk_STOP_AND_edma_mem_dma_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK (0x1FFF0U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT (4U) /*! LPCG_lpcg_edma_0_reserved_4_16 - reserved */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT (17U) /*! edma_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_edma_0_reserved_18_18 - reserved */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT (19U) /*! edma_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK (0xFFF00000U) #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_edma_0_reserved_20_31 - reserved */ #define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_EDMA_Register_Masks */ /* CONNECTIVITY_LPCG_EDMA - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_EDMA base address */ #define CONNECTIVITY__LPCG_EDMA_BASE (0x5B2A0000u) /** Peripheral CONNECTIVITY__LPCG_EDMA base pointer */ #define CONNECTIVITY__LPCG_EDMA ((CONNECTIVITY_LPCG_EDMA_Type *)CONNECTIVITY__LPCG_EDMA_BASE) /** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base addresses */ #define CONNECTIVITY_LPCG_EDMA_BASE_ADDRS { CONNECTIVITY__LPCG_EDMA_BASE } /** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base pointers */ #define CONNECTIVITY_LPCG_EDMA_BASE_PTRS { CONNECTIVITY__LPCG_EDMA } /*! * @} */ /* end of group CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_ENET0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ENET1_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_LPCG_ENET1_4; /**< na, offset: 0x4 */ } CONNECTIVITY_LPCG_ENET0_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_ENET0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_ENET0_Register_Masks CONNECTIVITY_LPCG_ENET0 Register Masks * @{ */ /*! @name LPCG_LPCG_ENET1_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK (0x1U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT (0U) /*! enet1_ipg_clk_time_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT (1U) /*! enet1_ipg_clk_time_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_enet1_0_reserved_2_2 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT (3U) /*! enet1_ipg_clk_time_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK (0x10U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT (4U) /*! LPCG_lpcg_enet1_0_reserved_4_4 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK (0x20U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT (5U) /*! enet1_2x_txclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK (0x40U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT (6U) /*! LPCG_lpcg_enet1_0_reserved_6_6 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK (0x80U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT (7U) /*! enet1_2x_txclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK (0x100U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT (8U) /*! LPCG_lpcg_enet1_0_reserved_8_8 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK (0x200U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT (9U) /*! enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK (0x400U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT (10U) /*! LPCG_lpcg_enet1_0_reserved_10_10 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK (0x800U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT (11U) /*! enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK (0x1000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT (12U) /*! LPCG_lpcg_enet1_0_reserved_12_12 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK (0x2000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT (13U) /*! enet1_clkdiv_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK (0x4000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT (14U) /*! LPCG_lpcg_enet1_0_reserved_14_14 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK (0x8000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT (15U) /*! enet1_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT (16U) /*! enet1_ipg_clk_mac0_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT (17U) /*! enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_enet1_0_reserved_18_18 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT (19U) /*! enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK (0x100000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT (20U) /*! enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT (21U) /*! enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_enet1_0_reserved_22_22 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT (23U) /*! enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT (24U) /*! LPCG_lpcg_enet1_0_reserved_24_31 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_LPCG_ENET1_4 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_enet1_4_reserved_0_0 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT (1U) /*! enet1_mac0_rxclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_enet1_4_reserved_2_2 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT (3U) /*! enet1_mac0_rxclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK (0xFFFFFFF0U) #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_enet1_4_reserved_4_31 - reserved */ #define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_ENET0_Register_Masks */ /* CONNECTIVITY_LPCG_ENET0 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_ENET0 base address */ #define CONNECTIVITY__LPCG_ENET0_BASE (0x5B230000u) /** Peripheral CONNECTIVITY__LPCG_ENET0 base pointer */ #define CONNECTIVITY__LPCG_ENET0 ((CONNECTIVITY_LPCG_ENET0_Type *)CONNECTIVITY__LPCG_ENET0_BASE) /** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base addresses */ #define CONNECTIVITY_LPCG_ENET0_BASE_ADDRS { CONNECTIVITY__LPCG_ENET0_BASE } /** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base pointers */ #define CONNECTIVITY_LPCG_ENET0_BASE_PTRS { CONNECTIVITY__LPCG_ENET0 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_ENET1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ENET2_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_LPCG_ENET2_4; /**< na, offset: 0x4 */ } CONNECTIVITY_LPCG_ENET1_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_ENET1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_ENET1_Register_Masks CONNECTIVITY_LPCG_ENET1 Register Masks * @{ */ /*! @name LPCG_LPCG_ENET2_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK (0x1U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT (0U) /*! enet2_ipg_clk_time_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT (1U) /*! enet2_ipg_clk_time_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_enet2_0_reserved_2_2 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT (3U) /*! enet2_ipg_clk_time_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK (0x10U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT (4U) /*! LPCG_lpcg_enet2_0_reserved_4_4 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK (0x20U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT (5U) /*! enet2_2x_txclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK (0x40U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT (6U) /*! LPCG_lpcg_enet2_0_reserved_6_6 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK (0x80U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT (7U) /*! enet2_2x_txclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK (0x100U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT (8U) /*! LPCG_lpcg_enet2_0_reserved_8_8 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK (0x200U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT (9U) /*! enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK (0x400U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT (10U) /*! LPCG_lpcg_enet2_0_reserved_10_10 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK (0x800U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT (11U) /*! enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK (0x1000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT (12U) /*! LPCG_lpcg_enet2_0_reserved_12_12 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK (0x2000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT (13U) /*! enet2_clkdiv_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK (0x4000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT (14U) /*! LPCG_lpcg_enet2_0_reserved_14_14 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK (0x8000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT (15U) /*! enet2_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT (16U) /*! enet2_ipg_clk_mac0_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT (17U) /*! enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_enet2_0_reserved_18_18 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT (19U) /*! enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK (0x100000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT (20U) /*! enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT (21U) /*! enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_enet2_0_reserved_22_22 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT (23U) /*! enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT (24U) /*! LPCG_lpcg_enet2_0_reserved_24_31 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_LPCG_ENET2_4 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_enet2_4_reserved_0_0 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT (1U) /*! enet2_mac0_rxclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_enet2_4_reserved_2_2 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT (3U) /*! enet2_mac0_rxclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK (0xFFFFFFF0U) #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_enet2_4_reserved_4_31 - reserved */ #define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_ENET1_Register_Masks */ /* CONNECTIVITY_LPCG_ENET1 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_ENET1 base address */ #define CONNECTIVITY__LPCG_ENET1_BASE (0x5B240000u) /** Peripheral CONNECTIVITY__LPCG_ENET1 base pointer */ #define CONNECTIVITY__LPCG_ENET1 ((CONNECTIVITY_LPCG_ENET1_Type *)CONNECTIVITY__LPCG_ENET1_BASE) /** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base addresses */ #define CONNECTIVITY_LPCG_ENET1_BASE_ADDRS { CONNECTIVITY__LPCG_ENET1_BASE } /** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base pointers */ #define CONNECTIVITY_LPCG_ENET1_BASE_PTRS { CONNECTIVITY__LPCG_ENET1 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_MLB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer CONNECTIVITY_LPCG_MLB Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_MLB - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_MLB_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_MLB_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_MLB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_MLB_Register_Masks CONNECTIVITY_LPCG_MLB Register Masks * @{ */ /*! @name LPCG_LPCG_MLB_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_mlb_0_reserved_0_0 - reserved */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT (1U) /*! mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_mlb_0_reserved_2_2 - reserved */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT (3U) /*! mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK (0xFFF0U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_mlb_0_reserved_4_15 - reserved */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT (16U) /*! mlb_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT (17U) /*! mlb_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_mlb_0_reserved_18_18 - reserved */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT (19U) /*! mlb_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT (20U) /*! LPCG_lpcg_mlb_0_reserved_20_20 - reserved */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT (21U) /*! mlb_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_mlb_0_reserved_22_22 - reserved */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT (23U) /*! mlb_hclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT (24U) /*! LPCG_lpcg_mlb_0_reserved_24_31 - reserved */ #define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_MLB_Register_Masks */ /* CONNECTIVITY_LPCG_MLB - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_MLB base address */ #define CONNECTIVITY__LPCG_MLB_BASE (0x5B260000u) /** Peripheral CONNECTIVITY__LPCG_MLB base pointer */ #define CONNECTIVITY__LPCG_MLB ((CONNECTIVITY_LPCG_MLB_Type *)CONNECTIVITY__LPCG_MLB_BASE) /** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base addresses */ #define CONNECTIVITY_LPCG_MLB_BASE_ADDRS { CONNECTIVITY__LPCG_MLB_BASE } /** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base pointers */ #define CONNECTIVITY_LPCG_MLB_BASE_PTRS { CONNECTIVITY__LPCG_MLB } /*! * @} */ /* end of group CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_RAWNAND - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_RAWNAND_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_LPCG_RAWNAND_4; /**< na, offset: 0x4 */ } CONNECTIVITY_LPCG_RAWNAND_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_RAWNAND Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Register_Masks CONNECTIVITY_LPCG_RAWNAND Register Masks * @{ */ /*! @name LPCG_LPCG_RAWNAND_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_rawnand_0_reserved_0_0 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT (1U) /*! rawnand_u_gpmi_bch_input_bch_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_rawnand_0_reserved_2_2 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT (3U) /*! rawnand_u_gpmi_bch_input_bch_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK (0x10U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT (4U) /*! LPCG_lpcg_rawnand_0_reserved_4_4 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK (0x20U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT (5U) /*! rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK (0x40U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT (6U) /*! LPCG_lpcg_rawnand_0_reserved_6_6 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK (0x80U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT (7U) /*! rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK (0x1FF00U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT (8U) /*! LPCG_lpcg_rawnand_0_reserved_8_16 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT (17U) /*! rawnand_u_gpmi_input_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_rawnand_0_reserved_18_18 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT (19U) /*! rawnand_u_gpmi_input_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT (20U) /*! LPCG_lpcg_rawnand_0_reserved_20_20 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT (21U) /*! rawnand_u_bch_input_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_rawnand_0_reserved_22_22 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT (23U) /*! rawnand_u_bch_input_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT (24U) /*! LPCG_lpcg_rawnand_0_reserved_24_31 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_LPCG_RAWNAND_4 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK (0x1FFFFU) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT (0U) /*! LPCG_lpcg_rawnand_4_reserved_0_16 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT (17U) /*! apbhdma_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_rawnand_4_reserved_18_18 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT (19U) /*! apbhdma_hclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK (0xFFF00000U) #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_rawnand_4_reserved_20_31 - reserved */ #define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Register_Masks */ /* CONNECTIVITY_LPCG_RAWNAND - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_RAWNAND base address */ #define CONNECTIVITY__LPCG_RAWNAND_BASE (0x5B290000u) /** Peripheral CONNECTIVITY__LPCG_RAWNAND base pointer */ #define CONNECTIVITY__LPCG_RAWNAND ((CONNECTIVITY_LPCG_RAWNAND_Type *)CONNECTIVITY__LPCG_RAWNAND_BASE) /** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base addresses */ #define CONNECTIVITY_LPCG_RAWNAND_BASE_ADDRS { CONNECTIVITY__LPCG_RAWNAND_BASE } /** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base pointers */ #define CONNECTIVITY_LPCG_RAWNAND_BASE_PTRS { CONNECTIVITY__LPCG_RAWNAND } /*! * @} */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USB2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB2 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_USB2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_USB2_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_USB2_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USB2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USB2_Register_Masks CONNECTIVITY_LPCG_USB2 Register Masks * @{ */ /*! @name LPCG_LPCG_USB2_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK (0x1FFFFU) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT (0U) /*! LPCG_lpcg_usb2_0_reserved_0_16 - reserved */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT (17U) /*! usboh_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_usb2_0_reserved_18_18 - reserved */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT (19U) /*! usboh_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT (20U) /*! LPCG_lpcg_usb2_0_reserved_20_20 - reserved */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT (21U) /*! usboh_ipg_clk_s_pl301_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_usb2_0_reserved_22_22 - reserved */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT (23U) /*! usboh_ipg_clk_s_pl301_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK (0x1000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT (24U) /*! LPCG_lpcg_usb2_0_reserved_24_24 - reserved */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK (0x2000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT (25U) /*! usboh_ipg_ahb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK (0x4000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT (26U) /*! LPCG_lpcg_usb2_0_reserved_26_26 - reserved */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK (0x8000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT (27U) /*! usboh_ipg_ahb_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK (0x10000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT (28U) /*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK (0x20000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT (29U) /*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK (0x40000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT (30U) /*! LPCG_lpcg_usb2_0_reserved_30_30 - reserved */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK (0x80000000U) #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT (31U) /*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_USB2_Register_Masks */ /* CONNECTIVITY_LPCG_USB2 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_USB2 base address */ #define CONNECTIVITY__LPCG_USB2_BASE (0x5B270000u) /** Peripheral CONNECTIVITY__LPCG_USB2 base pointer */ #define CONNECTIVITY__LPCG_USB2 ((CONNECTIVITY_LPCG_USB2_Type *)CONNECTIVITY__LPCG_USB2_BASE) /** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base addresses */ #define CONNECTIVITY_LPCG_USB2_BASE_ADDRS { CONNECTIVITY__LPCG_USB2_BASE } /** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base pointers */ #define CONNECTIVITY_LPCG_USB2_BASE_PTRS { CONNECTIVITY__LPCG_USB2 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USB3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB3 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_USB3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_USB3_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_USB3_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USB3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USB3_Register_Masks CONNECTIVITY_LPCG_USB3 Register Masks * @{ */ /*! @name LPCG_LPCG_USB3_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_usb3_0_reserved_0_0 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT (1U) /*! da_ip_usb3_wrap_app_clk_125_predft_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_usb3_0_reserved_2_2 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT (3U) /*! da_ip_usb3_wrap_app_clk_125_predft_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK (0x10U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT (4U) /*! LPCG_lpcg_usb3_0_reserved_4_4 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK (0x20U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT (5U) /*! da_ip_usb3_wrap_lpm_clk_predft_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK (0x40U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT (6U) /*! LPCG_lpcg_usb3_0_reserved_6_6 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK (0x80U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT (7U) /*! da_ip_usb3_wrap_lpm_clk_predft_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK (0x1FF00U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT (8U) /*! LPCG_lpcg_usb3_0_reserved_8_16 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT (17U) /*! da_ip_usb3_wrap_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_usb3_0_reserved_18_18 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT (19U) /*! da_ip_usb3_wrap_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT (20U) /*! LPCG_lpcg_usb3_0_reserved_20_20 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT (21U) /*! da_ip_usb3_wrap_usb3_core_pclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_usb3_0_reserved_22_22 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT (23U) /*! da_ip_usb3_wrap_usb3_core_pclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK (0x1000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT (24U) /*! LPCG_lpcg_usb3_0_reserved_24_24 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK (0x2000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT (25U) /*! da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK (0x4000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT (26U) /*! LPCG_lpcg_usb3_0_reserved_26_26 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK (0x8000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT (27U) /*! da_ip_usb3_wrap_usb3_ssphy_pclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK (0x10000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT (28U) /*! LPCG_lpcg_usb3_0_reserved_28_28 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK (0x20000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT (29U) /*! da_ip_usb3_wrap_usb3_aclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK (0x40000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT (30U) /*! LPCG_lpcg_usb3_0_reserved_30_30 - reserved */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK (0x80000000U) #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT (31U) /*! da_ip_usb3_wrap_usb3_aclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_USB3_Register_Masks */ /* CONNECTIVITY_LPCG_USB3 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_USB3 base address */ #define CONNECTIVITY__LPCG_USB3_BASE (0x5B280000u) /** Peripheral CONNECTIVITY__LPCG_USB3 base pointer */ #define CONNECTIVITY__LPCG_USB3 ((CONNECTIVITY_LPCG_USB3_Type *)CONNECTIVITY__LPCG_USB3_BASE) /** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base addresses */ #define CONNECTIVITY_LPCG_USB3_BASE_ADDRS { CONNECTIVITY__LPCG_USB3_BASE } /** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base pointers */ #define CONNECTIVITY_LPCG_USB3_BASE_PTRS { CONNECTIVITY__LPCG_USB3 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_USDHC0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_USDHC1_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_USDHC0_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USDHC0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USDHC0_Register_Masks CONNECTIVITY_LPCG_USDHC0 Register Masks * @{ */ /*! @name LPCG_LPCG_USDHC1_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_usdhc1_0_reserved_0_0 - reserved */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT (1U) /*! usdhc1_ipg_clk_perclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_usdhc1_0_reserved_2_2 - reserved */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT (3U) /*! usdhc1_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK (0xFFF0U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_usdhc1_0_reserved_4_15 - reserved */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT (16U) /*! usdhc1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT (17U) /*! usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_usdhc1_0_reserved_18_18 - reserved */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT (19U) /*! usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT (20U) /*! LPCG_lpcg_usdhc1_0_reserved_20_20 - reserved */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT (21U) /*! usdhc1_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_usdhc1_0_reserved_22_22 - reserved */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT (23U) /*! usdhc1_hclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT (24U) /*! LPCG_lpcg_usdhc1_0_reserved_24_31 - reserved */ #define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_USDHC0_Register_Masks */ /* CONNECTIVITY_LPCG_USDHC0 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_USDHC0 base address */ #define CONNECTIVITY__LPCG_USDHC0_BASE (0x5B200000u) /** Peripheral CONNECTIVITY__LPCG_USDHC0 base pointer */ #define CONNECTIVITY__LPCG_USDHC0 ((CONNECTIVITY_LPCG_USDHC0_Type *)CONNECTIVITY__LPCG_USDHC0_BASE) /** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base addresses */ #define CONNECTIVITY_LPCG_USDHC0_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC0_BASE } /** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base pointers */ #define CONNECTIVITY_LPCG_USDHC0_BASE_PTRS { CONNECTIVITY__LPCG_USDHC0 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer * @{ */ /** CONNECTIVITY_LPCG_USDHC1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_USDHC2_0; /**< na, offset: 0x0 */ } CONNECTIVITY_LPCG_USDHC1_Type; /* ---------------------------------------------------------------------------- -- CONNECTIVITY_LPCG_USDHC1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CONNECTIVITY_LPCG_USDHC1_Register_Masks CONNECTIVITY_LPCG_USDHC1 Register Masks * @{ */ /*! @name LPCG_LPCG_USDHC2_0 - na */ /*! @{ */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK (0x1U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_usdhc2_0_reserved_0_0 - reserved */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK (0x2U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT (1U) /*! usdhc2_ipg_clk_perclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK (0x4U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_usdhc2_0_reserved_2_2 - reserved */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK (0x8U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT (3U) /*! usdhc2_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK (0xFFF0U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_usdhc2_0_reserved_4_15 - reserved */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK (0x10000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT (16U) /*! usdhc2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK (0x20000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT (17U) /*! usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK (0x40000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_usdhc2_0_reserved_18_18 - reserved */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK (0x80000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT (19U) /*! usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK (0x100000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT (20U) /*! LPCG_lpcg_usdhc2_0_reserved_20_20 - reserved */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK (0x200000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT (21U) /*! usdhc2_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK (0x400000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_usdhc2_0_reserved_22_22 - reserved */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK (0x800000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT (23U) /*! usdhc2_hclk_STOP - show clock root status, 1 means clock stopped */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK (0xFF000000U) #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT (24U) /*! LPCG_lpcg_usdhc2_0_reserved_24_31 - reserved */ #define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group CONNECTIVITY_LPCG_USDHC1_Register_Masks */ /* CONNECTIVITY_LPCG_USDHC1 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__LPCG_USDHC1 base address */ #define CONNECTIVITY__LPCG_USDHC1_BASE (0x5B210000u) /** Peripheral CONNECTIVITY__LPCG_USDHC1 base pointer */ #define CONNECTIVITY__LPCG_USDHC1 ((CONNECTIVITY_LPCG_USDHC1_Type *)CONNECTIVITY__LPCG_USDHC1_BASE) /** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base addresses */ #define CONNECTIVITY_LPCG_USDHC1_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC1_BASE } /** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base pointers */ #define CONNECTIVITY_LPCG_USDHC1_BASE_PTRS { CONNECTIVITY__LPCG_USDHC1 } /*! * @} */ /* end of group CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DC_LPCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DC_LPCG_Peripheral_Access_Layer DC_LPCG Peripheral Access Layer * @{ */ /** DC_LPCG - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_DC_LPCG_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_DC_LPCG_4; /**< na, offset: 0x4 */ __IO uint32_t LPCG_DC_LPCG_8; /**< na, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t LPCG_DC_LPCG_16; /**< na, offset: 0x10 */ __IO uint32_t LPCG_DC_LPCG_20; /**< na, offset: 0x14 */ __IO uint32_t LPCG_DC_LPCG_24; /**< na, offset: 0x18 */ __IO uint32_t LPCG_DC_LPCG_28; /**< na, offset: 0x1C */ __IO uint32_t LPCG_DC_LPCG_32; /**< na, offset: 0x20 */ __IO uint32_t LPCG_DC_LPCG_36; /**< na, offset: 0x24 */ __IO uint32_t LPCG_DC_LPCG_40; /**< na, offset: 0x28 */ __IO uint32_t LPCG_DC_LPCG_44; /**< na, offset: 0x2C */ __IO uint32_t LPCG_DC_LPCG_48; /**< na, offset: 0x30 */ __IO uint32_t LPCG_DC_LPCG_52; /**< na, offset: 0x34 */ __IO uint32_t LPCG_DC_LPCG_56; /**< na, offset: 0x38 */ __IO uint32_t LPCG_DC_LPCG_60; /**< na, offset: 0x3C */ __IO uint32_t LPCG_DC_LPCG_64; /**< na, offset: 0x40 */ __IO uint32_t LPCG_DC_LPCG_68; /**< na, offset: 0x44 */ __IO uint32_t LPCG_DC_LPCG_72; /**< na, offset: 0x48 */ } DC_LPCG_Type; /* ---------------------------------------------------------------------------- -- DC_LPCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DC_LPCG_Register_Masks DC_LPCG Register Masks * @{ */ /*! @name LPCG_DC_LPCG_0 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_0_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT (1U) /*! dsp0_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_0_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT (3U) /*! dsp0_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK (0x10U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT (4U) /*! LPCG_dc_lpcg_0_reserved_4_4 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK (0x20U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT (5U) /*! dsp1_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK (0x40U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT (6U) /*! LPCG_dc_lpcg_0_reserved_6_6 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK (0x80U) #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT (7U) /*! dsp1_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK (0xFFFFFF00U) #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT (8U) /*! LPCG_dc_lpcg_0_reserved_8_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_4 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT (0U) /*! LPCG_dc_lpcg_4_reserved_0_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT (16U) /*! lis_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT (17U) /*! lis_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_4_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT (19U) /*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_4_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_8 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT (0U) /*! LPCG_dc_lpcg_8_reserved_0_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT (16U) /*! display_ctrl_link_mst0_msi_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT (17U) /*! display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_8_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT (19U) /*! display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_8_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_16 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT (0U) /*! LPCG_dc_lpcg_16_reserved_0_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT (16U) /*! pixel_combiner_apb_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT (17U) /*! pixel_combiner_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_16_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT (19U) /*! pixel_combiner_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_16_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_20 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT (0U) /*! LPCG_dc_lpcg_20_reserved_0_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT (16U) /*! iris_mvpl_cfg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT (17U) /*! iris_mvpl_cfg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_20_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT (19U) /*! iris_mvpl_cfg_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK (0x100000U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT (20U) /*! LPCG_dc_lpcg_20_reserved_20_20 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK (0x200000U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT (21U) /*! iris_mvpl_axi_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK (0x400000U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT (22U) /*! LPCG_dc_lpcg_20_reserved_22_22 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK (0x800000U) #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT (23U) /*! iris_mvpl_axi_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK (0xFF000000U) #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT (24U) /*! LPCG_dc_lpcg_20_reserved_24_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_24 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT (0U) /*! LPCG_dc_lpcg_24_reserved_0_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT (16U) /*! dpr0_dpr_apb_clkg_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT (17U) /*! dpr0_dpr_apb_clkg_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_24_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT (19U) /*! dpr0_dpr_apb_clkg_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK (0x100000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT (20U) /*! dpr0_dpr_b_clkg_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK (0x200000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT (21U) /*! dpr0_dpr_b_clkg_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK (0x400000U) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT (22U) /*! LPCG_dc_lpcg_24_reserved_22_22 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK (0x800000U) #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT (23U) /*! dpr0_dpr_b_clkg_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK (0xFF000000U) #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT (24U) /*! LPCG_dc_lpcg_24_reserved_24_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_28 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_28_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT (1U) /*! rtram0_rtr_clk_g_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_28_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT (3U) /*! rtram0_rtr_clk_g_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U) #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT (4U) /*! LPCG_dc_lpcg_28_reserved_4_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_32 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_32_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT (1U) /*! prg0_rtram_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_32_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT (3U) /*! prg0_rtram_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT (4U) /*! LPCG_dc_lpcg_32_reserved_4_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT (16U) /*! prg0_apb_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT (17U) /*! prg0_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_32_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT (19U) /*! prg0_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_32_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_36 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_36_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT (1U) /*! prg1_rtram_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_36_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT (3U) /*! prg1_rtram_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT (4U) /*! LPCG_dc_lpcg_36_reserved_4_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT (16U) /*! prg1_apb_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT (17U) /*! prg1_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_36_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT (19U) /*! prg1_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_36_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_40 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_40_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT (1U) /*! prg2_rtram_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_40_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT (3U) /*! prg2_rtram_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT (4U) /*! LPCG_dc_lpcg_40_reserved_4_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT (16U) /*! prg2_apb_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT (17U) /*! prg2_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_40_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT (19U) /*! prg2_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_40_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_44 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK (0xFFFFU) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT (0U) /*! LPCG_dc_lpcg_44_reserved_0_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT (16U) /*! dpr1_dpr_apb_clkg_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT (17U) /*! dpr1_dpr_apb_clkg_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_44_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT (19U) /*! dpr1_dpr_apb_clkg_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK (0x100000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT (20U) /*! dpr1_dpr_b_clkg_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK (0x200000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT (21U) /*! dpr1_dpr_b_clkg_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK (0x400000U) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT (22U) /*! LPCG_dc_lpcg_44_reserved_22_22 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK (0x800000U) #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT (23U) /*! dpr1_dpr_b_clkg_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK (0xFF000000U) #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT (24U) /*! LPCG_dc_lpcg_44_reserved_24_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_48 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_48_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT (1U) /*! rtram1_rtr_clk_g_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_48_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT (3U) /*! rtram1_rtr_clk_g_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK (0xFFFFFFF0U) #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT (4U) /*! LPCG_dc_lpcg_48_reserved_4_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_52 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_52_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT (1U) /*! prg3_rtram_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_52_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT (3U) /*! prg3_rtram_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT (4U) /*! LPCG_dc_lpcg_52_reserved_4_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT (16U) /*! prg3_apb_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT (17U) /*! prg3_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_52_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT (19U) /*! prg3_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_52_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_56 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_56_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT (1U) /*! prg4_rtram_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_56_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT (3U) /*! prg4_rtram_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT (4U) /*! LPCG_dc_lpcg_56_reserved_4_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT (16U) /*! prg4_apb_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT (17U) /*! prg4_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_56_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT (19U) /*! prg4_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_56_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_60 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_60_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT (1U) /*! prg5_rtram_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_60_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT (3U) /*! prg5_rtram_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT (4U) /*! LPCG_dc_lpcg_60_reserved_4_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT (16U) /*! prg5_apb_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT (17U) /*! prg5_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_60_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT (19U) /*! prg5_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_60_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_64 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_64_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT (1U) /*! prg6_rtram_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_64_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT (3U) /*! prg6_rtram_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT (4U) /*! LPCG_dc_lpcg_64_reserved_4_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT (16U) /*! prg6_apb_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT (17U) /*! prg6_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_64_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT (19U) /*! prg6_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_64_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_68 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_68_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT (1U) /*! prg7_rtram_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_68_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT (3U) /*! prg7_rtram_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT (4U) /*! LPCG_dc_lpcg_68_reserved_4_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT (16U) /*! prg7_apb_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT (17U) /*! prg7_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_68_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT (19U) /*! prg7_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_68_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DC_LPCG_72 - na */ /*! @{ */ #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK (0x1U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT (0U) /*! LPCG_dc_lpcg_72_reserved_0_0 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK (0x2U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT (1U) /*! prg8_rtram_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK (0x4U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT (2U) /*! LPCG_dc_lpcg_72_reserved_2_2 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK (0x8U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT (3U) /*! prg8_rtram_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK (0xFFF0U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT (4U) /*! LPCG_dc_lpcg_72_reserved_4_15 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK (0x10000U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT (16U) /*! prg8_apb_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK (0x20000U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT (17U) /*! prg8_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK (0x40000U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT (18U) /*! LPCG_dc_lpcg_72_reserved_18_18 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK (0x80000U) #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT (19U) /*! prg8_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK (0xFFF00000U) #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT (20U) /*! LPCG_dc_lpcg_72_reserved_20_31 - reserved */ #define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group DC_LPCG_Register_Masks */ /* DC_LPCG - Peripheral instance base addresses */ /** Peripheral DC__LPCG_DSP0_CLK base address */ #define DC__LPCG_DSP0_CLK_BASE (0x56010000u) /** Peripheral DC__LPCG_DSP0_CLK base pointer */ #define DC__LPCG_DSP0_CLK ((DC_LPCG_Type *)DC__LPCG_DSP0_CLK_BASE) /** Array initializer of DC_LPCG peripheral base addresses */ #define DC_LPCG_BASE_ADDRS { DC__LPCG_DSP0_CLK_BASE } /** Array initializer of DC_LPCG peripheral base pointers */ #define DC_LPCG_BASE_PTRS { DC__LPCG_DSP0_CLK } /*! * @} */ /* end of group DC_LPCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DDRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer * @{ */ /** DDRC - Register Layout Typedef */ typedef struct { __IO uint32_t MSTR; /**< Master Register0, offset: 0x0 */ __I uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */ __IO uint32_t MSTR1; /**< Operating Mode Status Register, offset: 0x8 */ __IO uint32_t MRCTRL3; /**< Operating Mode Status Register, offset: 0xC */ __IO uint32_t MRCTRL0; /**< Mode Register Read/Write Control Register 0., offset: 0x10 */ __IO uint32_t MRCTRL1; /**< Mode Register Read/Write Control Register 1, offset: 0x14 */ __I uint32_t MRSTAT; /**< Mode Register Read/Write Status Register, offset: 0x18 */ __IO uint32_t MRCTRL2; /**< Mode Register Read/Write Control Register 2, offset: 0x1C */ __IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */ __IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */ uint8_t RESERVED_0[8]; __IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */ __IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */ __IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */ uint8_t RESERVED_1[20]; __IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */ __IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */ uint8_t RESERVED_2[8]; __IO uint32_t RFSHCTL3; /**< Refresh Control Register 3, offset: 0x60 */ __IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */ uint8_t RESERVED_3[104]; __IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */ __IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */ __IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */ __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */ __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */ __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */ __IO uint32_t INIT6; /**< SDRAM Initialization Register 6, offset: 0xE8 */ __IO uint32_t INIT7; /**< SDRAM Initialization Register 7, offset: 0xEC */ __IO uint32_t DIMMCTL; /**< DIMM Control Register, offset: 0xF0 */ __IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */ uint8_t RESERVED_4[8]; __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */ __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */ __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */ __IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */ __IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */ __IO uint32_t DRAMTMG5; /**< SDRAM Timing Register 5, offset: 0x114 */ __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */ __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */ __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */ __IO uint32_t DRAMTMG9; /**< SDRAM Timing Register 9, offset: 0x124 */ __IO uint32_t DRAMTMG10; /**< SDRAM Timing Register 10, offset: 0x128 */ __IO uint32_t DRAMTMG11; /**< SDRAM Timing Register 11, offset: 0x12C */ __IO uint32_t DRAMTMG12; /**< SDRAM Timing Register 12, offset: 0x130 */ __IO uint32_t DRAMTMG13; /**< SDRAM Timing Register 13, offset: 0x134 */ __IO uint32_t DRAMTMG14; /**< SDRAM Timing Register 14, offset: 0x138 */ __IO uint32_t DRAMTMG15; /**< SDRAM Timing Register 15, offset: 0x13C */ uint8_t RESERVED_5[64]; __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */ __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */ __I uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */ __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */ __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */ __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */ __IO uint32_t DFILPCFG1; /**< DFI Low Power Configuration Register 1, offset: 0x19C */ __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */ __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */ __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */ uint8_t RESERVED_6[4]; __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */ __IO uint32_t DFITMG2; /**< DFI Timing Register 2, offset: 0x1B4 */ __IO uint32_t DFITMG3; /**< DFI Timing Register 3, offset: 0x1B8 */ __I uint32_t DFISTAT; /**< DFI Status Register, offset: 0x1BC */ __IO uint32_t DBICTL; /**< DM/DBI Control Register, offset: 0x1C0 */ uint8_t RESERVED_7[60]; __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */ __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */ __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */ __IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */ __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */ __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */ __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */ __IO uint32_t ADDRMAP7; /**< Address Map Register 7, offset: 0x21C */ __IO uint32_t ADDRMAP8; /**< Address Map Register 8, offset: 0x220 */ __IO uint32_t ADDRMAP9; /**< Address Map Register 9, offset: 0x224 */ __IO uint32_t ADDRMAP10; /**< Address Map Register 10, offset: 0x228 */ __IO uint32_t ADDRMAP11; /**< Address Map Register 11, offset: 0x22C */ uint8_t RESERVED_8[16]; __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */ __IO uint32_t ODTMAP; /**< ODT/Rank Map Register, offset: 0x244 */ uint8_t RESERVED_9[8]; __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */ __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */ uint8_t RESERVED_10[4]; __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */ uint8_t RESERVED_11[4]; __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */ uint8_t RESERVED_12[4]; __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */ uint8_t RESERVED_13[144]; __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */ __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */ __I uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */ __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */ __I uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */ uint8_t RESERVED_14[12]; __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */ __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */ uint8_t RESERVED_15[68]; __IO uint32_t POISONCFG; /**< AXI Poison Configuration Register., offset: 0x36C */ __I uint32_t POISONSTAT; /**< AXI Poison Status Register, offset: 0x370 */ uint8_t RESERVED_16[136]; __I uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */ __IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */ __IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */ __IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */ uint8_t RESERVED_17[132]; __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */ __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */ __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */ __IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */ __IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */ uint8_t RESERVED_18[7036]; __IO uint32_t DERATEEN_SHADOW; /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */ __IO uint32_t DERATEINT_SHADOW; /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */ uint8_t RESERVED_19[40]; __IO uint32_t RFSHCTL0_SHADOW; /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */ uint8_t RESERVED_20[16]; __IO uint32_t RFSHTMG_SHADOW; /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */ uint8_t RESERVED_21[116]; __IO uint32_t INIT3_SHADOW; /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */ __IO uint32_t INIT4_SHADOW; /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */ uint8_t RESERVED_22[4]; __IO uint32_t INIT6_SHADOW; /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */ __IO uint32_t INIT7_SHADOW; /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */ uint8_t RESERVED_23[16]; __IO uint32_t DRAMTMG0_SHADOW; /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */ __IO uint32_t DRAMTMG1_SHADOW; /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */ __IO uint32_t DRAMTMG2_SHADOW; /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */ __IO uint32_t DRAMTMG3_SHADOW; /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */ __IO uint32_t DRAMTMG4_SHADOW; /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */ __IO uint32_t DRAMTMG5_SHADOW; /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */ __IO uint32_t DRAMTMG6_SHADOW; /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */ __IO uint32_t DRAMTMG7_SHADOW; /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */ __IO uint32_t DRAMTMG8_SHADOW; /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */ __IO uint32_t DRAMTMG9_SHADOW; /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */ __IO uint32_t DRAMTMG10_SHADOW; /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */ __IO uint32_t DRAMTMG11_SHADOW; /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */ __IO uint32_t DRAMTMG12_SHADOW; /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */ __IO uint32_t DRAMTMG13_SHADOW; /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */ __IO uint32_t DRAMTMG14_SHADOW; /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */ __IO uint32_t DRAMTMG15_SHADOW; /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */ uint8_t RESERVED_24[64]; __IO uint32_t ZQCTL0_SHADOW; /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */ uint8_t RESERVED_25[12]; __IO uint32_t DFITMG0_SHADOW; /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */ __IO uint32_t DFITMG1_SHADOW; /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */ uint8_t RESERVED_26[28]; __IO uint32_t DFITMG2_SHADOW; /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */ __IO uint32_t DFITMG3_SHADOW; /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */ uint8_t RESERVED_27[132]; __IO uint32_t ODTCFG_SHADOW; /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */ } DDRC_Type; /* ---------------------------------------------------------------------------- -- DDRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDRC_Register_Masks DDRC Register Masks * @{ */ /*! @name MSTR - Master Register0 */ /*! @{ */ #define DDRC_MSTR_ddr3_MASK (0x1U) #define DDRC_MSTR_ddr3_SHIFT (0U) /*! ddr3 - Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only * present in designs that support DDR3. */ #define DDRC_MSTR_ddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr3_SHIFT)) & DDRC_MSTR_ddr3_MASK) #define DDRC_MSTR_lpddr2_MASK (0x4U) #define DDRC_MSTR_lpddr2_SHIFT (2U) /*! lpddr2 - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use * Present only in designs configured to support LPDDR2. */ #define DDRC_MSTR_lpddr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr2_SHIFT)) & DDRC_MSTR_lpddr2_MASK) #define DDRC_MSTR_lpddr3_MASK (0x8U) #define DDRC_MSTR_lpddr3_SHIFT (3U) /*! lpddr3 - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use * Present only in designs configured to support LPDDR3. */ #define DDRC_MSTR_lpddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr3_SHIFT)) & DDRC_MSTR_lpddr3_MASK) #define DDRC_MSTR_ddr4_MASK (0x10U) #define DDRC_MSTR_ddr4_SHIFT (4U) /*! ddr4 - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present * only in designs configured to support DDR4. */ #define DDRC_MSTR_ddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr4_SHIFT)) & DDRC_MSTR_ddr4_MASK) #define DDRC_MSTR_lpddr4_MASK (0x20U) #define DDRC_MSTR_lpddr4_SHIFT (5U) /*! lpddr4 - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use * Present only in designs configured to support LPDDR4. */ #define DDRC_MSTR_lpddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr4_SHIFT)) & DDRC_MSTR_lpddr4_MASK) #define DDRC_MSTR_burstchop_MASK (0x200U) #define DDRC_MSTR_burstchop_SHIFT (9U) /*! burstchop - When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for Reads * is exercised only in HIF configurations (DDRC_INCL_ARB not set) and if in full bus width mode * (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. Burst Chop for Writes is * exercised only if Partial Writes enabled (DDRC_PARTIAL_WR=1) and if CRC is disabled * (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), * burst chop is not supported, and this bit must be set to '0'. BC4 (fixed) mode is not supported. */ #define DDRC_MSTR_burstchop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burstchop_SHIFT)) & DDRC_MSTR_burstchop_MASK) #define DDRC_MSTR_en_2t_timing_mode_MASK (0x400U) #define DDRC_MSTR_en_2t_timing_mode_SHIFT (10U) /*! en_2t_timing_mode - If 1, then DDRC uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all * command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is * asserted on the second cycle of the command Note: 2T timing is not supported in * LPDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE * is set Note: 2T timing is not supported in DDR4 geardown mode. Note: 2T timing is not supported * in Shared-AC dual channel mode and the register value is don't care. */ #define DDRC_MSTR_en_2t_timing_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_MSTR_en_2t_timing_mode_MASK) #define DDRC_MSTR_geardown_mode_MASK (0x800U) #define DDRC_MSTR_geardown_mode_SHIFT (11U) /*! geardown_mode - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in * normal mode (1N). This register can be changed, only when the Controller is in self-refresh * mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode is not supported * if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: Geardown mode is not supported * if the configuration parameter DDRC_SHARED_AC is set (in Shared-AC mode) and the register value * is don't care */ #define DDRC_MSTR_geardown_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_geardown_mode_SHIFT)) & DDRC_MSTR_geardown_mode_MASK) #define DDRC_MSTR_data_bus_width_MASK (0x3000U) #define DDRC_MSTR_data_bus_width_SHIFT (12U) /*! data_bus_width - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus * width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - * Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a * multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus * width (excluding any ECC width). */ #define DDRC_MSTR_data_bus_width(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_data_bus_width_SHIFT)) & DDRC_MSTR_data_bus_width_MASK) #define DDRC_MSTR_dll_off_mode_MASK (0x8000U) #define DDRC_MSTR_dll_off_mode_SHIFT (15U) /*! dll_off_mode - Set to 1 when the DDRC and DRAM has to be put in DLL-off mode for low frequency * operation. Set to 0 to put DDRC and DRAM in DLL-on mode for normal frequency operation. If DDR4 * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode is not * supported, and this bit must be set to '0'. */ #define DDRC_MSTR_dll_off_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_dll_off_mode_SHIFT)) & DDRC_MSTR_dll_off_mode_MASK) #define DDRC_MSTR_burst_rdwr_MASK (0xF0000U) #define DDRC_MSTR_burst_rdwr_SHIFT (16U) /*! burst_rdwr - SDRAM burst length used * 0b0001..Burst length of 2 (only supported for mDDR) * 0b0010..Burst length of 4 * 0b0100..Burst length of 8 * 0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) */ #define DDRC_MSTR_burst_rdwr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burst_rdwr_SHIFT)) & DDRC_MSTR_burst_rdwr_MASK) #define DDRC_MSTR_frequency_ratio_MASK (0x400000U) #define DDRC_MSTR_frequency_ratio_SHIFT (22U) /*! frequency_ratio - Selects the Frequency Ratio * 0b0..1:2 Mode * 0b1..1:1 Mode */ #define DDRC_MSTR_frequency_ratio(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_ratio_SHIFT)) & DDRC_MSTR_frequency_ratio_MASK) #define DDRC_MSTR_active_ranks_MASK (0x3000000U) #define DDRC_MSTR_active_ranks_SHIFT (24U) /*! active_ranks - Only present for multi-rank configurations. Each bit represents one rank. For * two-rank configurations, only bits[25:24] are present. */ #define DDRC_MSTR_active_ranks(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_active_ranks_SHIFT)) & DDRC_MSTR_active_ranks_MASK) #define DDRC_MSTR_frequency_mode_MASK (0x20000000U) #define DDRC_MSTR_frequency_mode_SHIFT (29U) /*! frequency_mode - Choose which registers are used. * 0b0..Original Registers * 0b1..Shadow Registers */ #define DDRC_MSTR_frequency_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_mode_SHIFT)) & DDRC_MSTR_frequency_mode_MASK) #define DDRC_MSTR_device_config_MASK (0xC0000000U) #define DDRC_MSTR_device_config_SHIFT (30U) /*! device_config - Indicates the configuration of the device used in the system. * 0b00..x4 device * 0b01..x8 device * 0b10..x16 device * 0b11..x32 device */ #define DDRC_MSTR_device_config(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_device_config_SHIFT)) & DDRC_MSTR_device_config_MASK) /*! @} */ /*! @name STAT - Operating Mode Status Register */ /*! @{ */ #define DDRC_STAT_operating_mode_MASK (0x7U) #define DDRC_STAT_operating_mode_SHIFT (0U) /*! operating_mode - Operating mode */ #define DDRC_STAT_operating_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_operating_mode_SHIFT)) & DDRC_STAT_operating_mode_MASK) #define DDRC_STAT_selfref_type_MASK (0x30U) #define DDRC_STAT_selfref_type_SHIFT (4U) /*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if * it was under Automatic Self Refresh control only or not. * 0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by * CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is * in-progress. * 0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self * Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error. * 0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under * Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software * (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity */ #define DDRC_STAT_selfref_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_type_SHIFT)) & DDRC_STAT_selfref_type_MASK) #define DDRC_STAT_selfref_state_MASK (0x300U) #define DDRC_STAT_selfref_state_SHIFT (8U) /*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state * for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh. * 0b00..SDRAM is not in Self Refresh. * 0b01..Self refresh 1 * 0b10..Self refresh power down * 0b11..Self refresh */ #define DDRC_STAT_selfref_state(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_state_SHIFT)) & DDRC_STAT_selfref_state_MASK) /*! @} */ /*! @name MSTR1 - Operating Mode Status Register */ /*! @{ */ #define DDRC_MSTR1_rank_tmgreg_sel_MASK (0x3U) #define DDRC_MSTR1_rank_tmgreg_sel_SHIFT (0U) /*! rank_tmgreg_sel - rank_tmgreg_sel * 0b00..USE DRAMTMGx registers for the rank * 0b01..USE MRAMTMGx registers for the rank */ #define DDRC_MSTR1_rank_tmgreg_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_rank_tmgreg_sel_SHIFT)) & DDRC_MSTR1_rank_tmgreg_sel_MASK) #define DDRC_MSTR1_alt_addrmap_en_MASK (0x10000U) #define DDRC_MSTR1_alt_addrmap_en_SHIFT (16U) /*! alt_addrmap_en - Enable Alternative Address Map * 0b0..Disable Alternative Address Map * 0b1..Enable Alternative Address Map */ #define DDRC_MSTR1_alt_addrmap_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_alt_addrmap_en_SHIFT)) & DDRC_MSTR1_alt_addrmap_en_MASK) /*! @} */ /*! @name MRCTRL3 - Operating Mode Status Register */ /*! @{ */ #define DDRC_MRCTRL3_mr_rank_sel_MASK (0x3U) #define DDRC_MRCTRL3_mr_rank_sel_SHIFT (0U) /*! mr_rank_sel - mr_rank_sel */ #define DDRC_MRCTRL3_mr_rank_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL3_mr_rank_sel_SHIFT)) & DDRC_MRCTRL3_mr_rank_sel_MASK) /*! @} */ /*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */ /*! @{ */ #define DDRC_MRCTRL0_mr_type_MASK (0x1U) #define DDRC_MRCTRL0_mr_type_SHIFT (0U) /*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. * 0b0..Write * 0b1..Read */ #define DDRC_MRCTRL0_mr_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_type_SHIFT)) & DDRC_MRCTRL0_mr_type_MASK) #define DDRC_MRCTRL0_mpr_en_MASK (0x2U) #define DDRC_MRCTRL0_mpr_en_SHIFT (1U) /*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4). * 0b0..MRS * 0b1..WR/RD for MPR */ #define DDRC_MRCTRL0_mpr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mpr_en_SHIFT)) & DDRC_MRCTRL0_mpr_en_MASK) #define DDRC_MRCTRL0_pda_en_MASK (0x4U) #define DDRC_MRCTRL0_pda_en_SHIFT (2U) /*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when * pba_mode=1, PBA access is initiated instead of PDA access. * 0b0..MRS * 0b1..MRS in Per DRAM Addressability */ #define DDRC_MRCTRL0_pda_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pda_en_SHIFT)) & DDRC_MRCTRL0_pda_en_MASK) #define DDRC_MRCTRL0_sw_init_int_MASK (0x8U) #define DDRC_MRCTRL0_sw_init_int_SHIFT (3U) /*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before * automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the * DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to * program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4 * independent channel mode, note that this must be programmed to both channels beforehand. Note that * this must be cleared to 0 after completing Software operation. Otherwise, SDRAM * initialization routine will not re-start. * 0b0..Software intervention is not allowed * 0b1..Software intervention is allowed */ #define DDRC_MRCTRL0_sw_init_int(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_sw_init_int_SHIFT)) & DDRC_MRCTRL0_sw_init_int_MASK) #define DDRC_MRCTRL0_mr_rank_MASK (0x30U) #define DDRC_MRCTRL0_mr_rank_SHIFT (4U) /*! mr_rank - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access * all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which * implement address mirroring, it may be necessary to access ranks individually. Examples (assume * DDRC is configured for 4 ranks): 0x1 - select rank 0 only 0x2 - select rank 1 only 0x5 - * select ranks 0 and 2 0xA - select ranks 1 and 3 0xF - select ranks 0, 1, 2 and 3 */ #define DDRC_MRCTRL0_mr_rank(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_rank_SHIFT)) & DDRC_MRCTRL0_mr_rank_MASK) #define DDRC_MRCTRL0_mr_addr_MASK (0xF000U) #define DDRC_MRCTRL0_mr_addr_SHIFT (12U) /*! mr_addr - Address of the mode register that is to be written to. * 0b0000..MR0 * 0b0001..MR1 * 0b0010..MR2 * 0b0011..MR3 * 0b0100..MR4 * 0b0101..MR5 * 0b0110..MR6 * 0b0111..MR7 */ #define DDRC_MRCTRL0_mr_addr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_addr_SHIFT)) & DDRC_MRCTRL0_mr_addr_MASK) #define DDRC_MRCTRL0_pba_mode_MASK (0x40000000U) #define DDRC_MRCTRL0_pba_mode_SHIFT (30U) /*! pba_mode - Indicates whether PBA access is executed. When setting this bit to 1 along with * setting pda_en to 1, DDRC initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability * mode - 1 - Per Buffer Addressability mode The completion of PBA access is confirmed by * MRSTAT.pda_done in the same way as PDA. */ #define DDRC_MRCTRL0_pba_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pba_mode_SHIFT)) & DDRC_MRCTRL0_pba_mode_MASK) #define DDRC_MRCTRL0_mr_wr_MASK (0x80000000U) #define DDRC_MRCTRL0_mr_wr_SHIFT (31U) /*! mr_wr - Setting this register bit to 1 triggers a mode register read or write operation. When * the MR operation is complete, the DDRC automatically clears this bit. The other register fields * of this register must be written in a separate APB transaction, before setting this mr_wr bit. * It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ #define DDRC_MRCTRL0_mr_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_wr_SHIFT)) & DDRC_MRCTRL0_mr_wr_MASK) /*! @} */ /*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */ /*! @{ */ #define DDRC_MRCTRL1_mr_data_MASK (0x3FFFFU) #define DDRC_MRCTRL1_mr_data_SHIFT (0U) /*! mr_data - Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For * LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as [15:8] MR Address [7:0] MR data for writes, * don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all * other configurations. */ #define DDRC_MRCTRL1_mr_data(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_mr_data_SHIFT)) & DDRC_MRCTRL1_mr_data_MASK) /*! @} */ /*! @name MRSTAT - Mode Register Read/Write Status Register */ /*! @{ */ #define DDRC_MRSTAT_mr_wr_busy_MASK (0x1U) #define DDRC_MRSTAT_mr_wr_busy_SHIFT (0U) /*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This * signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the * MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when * 'MRSTAT.mr_wr_busy' is high. * 0b0..Indicates that the SoC core can initiate a mode register write operation * 0b1..Indicates that mode register write operation is in progress */ #define DDRC_MRSTAT_mr_wr_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_MRSTAT_mr_wr_busy_MASK) #define DDRC_MRSTAT_pda_done_MASK (0x100U) #define DDRC_MRSTAT_pda_done_SHIFT (8U) /*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is * low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode * are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is * recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to * perform PDA operation next time * 0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet. * 0b1..Indicates that mode register write operation related to PDA/PBA has competed. */ #define DDRC_MRSTAT_pda_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_pda_done_SHIFT)) & DDRC_MRSTAT_pda_done_MASK) /*! @} */ /*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */ /*! @{ */ #define DDRC_MRCTRL2_mr_device_sel_MASK (0xFFFFFFFFU) #define DDRC_MRCTRL2_mr_device_sel_SHIFT (0U) /*! mr_device_sel - Indicates the device(s) to be selected during the MRS that happens in PDA mode. * Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to * Device 1 etc. A '1' should be programmed to indicate that the MRS command should be applied * to that device. A '0' indicates that the MRS commands should be skipped for that device. */ #define DDRC_MRCTRL2_mr_device_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_MRCTRL2_mr_device_sel_MASK) /*! @} */ /*! @name DERATEEN - Temperature Derate Enable Register */ /*! @{ */ #define DDRC_DERATEEN_derate_enable_MASK (0x1U) #define DDRC_DERATEEN_derate_enable_SHIFT (0U) /*! derate_enable - Enables derating. Present only in designs configured to support * LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. * 0b0..Timing parameter derating is disabled * 0b1..Timing parameter derating is enabled using MR4 read value. */ #define DDRC_DERATEEN_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_enable_SHIFT)) & DDRC_DERATEEN_derate_enable_MASK) #define DDRC_DERATEEN_derate_value_MASK (0x2U) #define DDRC_DERATEEN_derate_value_SHIFT (1U) /*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 * Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a * core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this * register field should be set to 1; otherwise it should be set to 0. * 0b0..Derating uses +1 * 0b1..Derating uses +2 */ #define DDRC_DERATEEN_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_value_SHIFT)) & DDRC_DERATEEN_derate_value_MASK) #define DDRC_DERATEEN_derate_byte_MASK (0xF0U) #define DDRC_DERATEEN_derate_byte_SHIFT (4U) /*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 * Indicates which byte of the MRR data is used for derating. The maximum valid value depends on * MEMC_DRAM_TOTAL_DATA_WIDTH. */ #define DDRC_DERATEEN_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_byte_SHIFT)) & DDRC_DERATEEN_derate_byte_MASK) #define DDRC_DERATEEN_rc_derate_value_MASK (0x300U) #define DDRC_DERATEEN_rc_derate_value_SHIFT (8U) /*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support * LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the * core_ddrc_core_clk period, and rounding up the next integer. * 0b00..Derating uses +1 * 0b01..Derating uses +2 * 0b10..Derating uses +3 * 0b11..Derating uses +4 */ #define DDRC_DERATEEN_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_rc_derate_value_SHIFT)) & DDRC_DERATEEN_rc_derate_value_MASK) /*! @} */ /*! @name DERATEINT - Temperature Derate Interval Register */ /*! @{ */ #define DDRC_DERATEINT_mr4_read_interval_MASK (0xFFFFFFFFU) #define DDRC_DERATEINT_mr4_read_interval_SHIFT (0U) /*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters. * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to * zero. Unit: DFI clock cycle. */ #define DDRC_DERATEINT_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_mr4_read_interval_MASK) /*! @} */ /*! @name PWRCTL - Low Power Control Register */ /*! @{ */ #define DDRC_PWRCTL_selfref_en_MASK (0x1U) #define DDRC_PWRCTL_selfref_en_SHIFT (0U) /*! selfref_en - If true then the DDRC puts the SDRAM into Self Refresh after a programmable number * of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit * may be re-programmed during the course of normal operation. */ #define DDRC_PWRCTL_selfref_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_en_SHIFT)) & DDRC_PWRCTL_selfref_en_MASK) #define DDRC_PWRCTL_powerdown_en_MASK (0x2U) #define DDRC_PWRCTL_powerdown_en_SHIFT (1U) /*! powerdown_en - If true then the DDRC goes into power-down after a programmable number of cycles * "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). This register bit may be * re-programmed during the course of normal operation. */ #define DDRC_PWRCTL_powerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_powerdown_en_SHIFT)) & DDRC_PWRCTL_powerdown_en_MASK) #define DDRC_PWRCTL_deeppowerdown_en_MASK (0x4U) #define DDRC_PWRCTL_deeppowerdown_en_SHIFT (2U) /*! deeppowerdown_en - When this is 1, DDRC puts the SDRAM into deep power-down mode when the * transaction store is empty. This register must be reset to '0' to bring DDRC out of deep power-down * mode. Controller performs automatic SDRAM initialization on deep power-down exit. Present only * in designs configured to support mDDR or LPDDR2 or LPDDR3. For * non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY. */ #define DDRC_PWRCTL_deeppowerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_PWRCTL_deeppowerdown_en_MASK) #define DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U) #define DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U) /*! en_dfi_dram_clk_disable - Enable the assertion of dfi_dram_clk_disable whenever a clock is not * required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of * dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can * be asserted in following: in Self Refresh in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, * can be asserted in following: in Self Refresh in Power Down in Deep Power Down during Normal * operation (Clock Stop) In LPDDR4, can be asserted in following: in Self Refresh Power Down in * Power Down during Normal operation (Clock Stop) */ #define DDRC_PWRCTL_en_dfi_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK) #define DDRC_PWRCTL_mpsm_en_MASK (0x10U) #define DDRC_PWRCTL_mpsm_en_SHIFT (4U) /*! mpsm_en - When this is 1, the DDRC puts the SDRAM into maximum power saving mode when the * transaction store is empty. This register must be reset to '0' to bring DDRC out of maximum power * saving mode. Present only in designs configured to support DDR4. For non-DDR4, this register * should not be set to 1. Note that MPSM is not supported when using a DDR PHY, if the PHY * parameter DDRC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to * toggle. FOR PERFORMANCE ONLY. */ #define DDRC_PWRCTL_mpsm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_mpsm_en_SHIFT)) & DDRC_PWRCTL_mpsm_en_MASK) #define DDRC_PWRCTL_selfref_sw_MASK (0x20U) #define DDRC_PWRCTL_selfref_sw_SHIFT (5U) /*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state * immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software * Entry/Exit to Self Refresh. * 0b0..Software Exit from Self Refresh * 0b1..Software Entry to Self Refresh */ #define DDRC_PWRCTL_selfref_sw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_sw_SHIFT)) & DDRC_PWRCTL_selfref_sw_MASK) #define DDRC_PWRCTL_stay_in_selfref_MASK (0x40U) #define DDRC_PWRCTL_stay_in_selfref_SHIFT (6U) /*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power * down state or exit Self refresh power down state for LPDDR4. This register controls transition * from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow * transition from Self refresh state * 0b0.. * 0b1.. */ #define DDRC_PWRCTL_stay_in_selfref(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_PWRCTL_stay_in_selfref_MASK) /*! @} */ /*! @name PWRTMG - Low Power Timing Register */ /*! @{ */ #define DDRC_PWRTMG_powerdown_to_x32_MASK (0x1FU) #define DDRC_PWRTMG_powerdown_to_x32_SHIFT (0U) /*! powerdown_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC * automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there * are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. Unit: * Multiples of 32 DFI clocks FOR PERFORMANCE ONLY. */ #define DDRC_PWRTMG_powerdown_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_PWRTMG_powerdown_to_x32_MASK) #define DDRC_PWRTMG_t_dpd_x4096_MASK (0xFF00U) #define DDRC_PWRTMG_t_dpd_x4096_SHIFT (8U) /*! t_dpd_x4096 - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as * mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is * de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 DFI * clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE * ONLY. */ #define DDRC_PWRTMG_t_dpd_x4096(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_PWRTMG_t_dpd_x4096_MASK) #define DDRC_PWRTMG_selfref_to_x32_MASK (0xFF0000U) #define DDRC_PWRTMG_selfref_to_x32_SHIFT (16U) /*! selfref_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC * automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there * are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. Unit: * Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY. */ #define DDRC_PWRTMG_selfref_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_PWRTMG_selfref_to_x32_MASK) /*! @} */ /*! @name HWLPCTL - Hardware Low Power Control Register */ /*! @{ */ #define DDRC_HWLPCTL_hw_lp_en_MASK (0x1U) #define DDRC_HWLPCTL_hw_lp_en_SHIFT (0U) /*! hw_lp_en - Enable for Hardware Low Power Interface. */ #define DDRC_HWLPCTL_hw_lp_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_en_MASK) #define DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK (0x2U) #define DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT (1U) /*! hw_lp_exit_idle_en - When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be * used to exit from the automatic clock stop, automatic power down or automatic self-refresh * modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power * Interface and/or Software (PWRCTL.selfref_sw). */ #define DDRC_HWLPCTL_hw_lp_exit_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK) #define DDRC_HWLPCTL_hw_lp_idle_x32_MASK (0xFFF0000U) #define DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT (16U) /*! hw_lp_idle_x32 - Hardware idle period. The cactive_ddrc output is driven low if the DDRC command * channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The * DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware * idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 DFI clocks. FOR * PERFORMANCE ONLY. */ #define DDRC_HWLPCTL_hw_lp_idle_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_HWLPCTL_hw_lp_idle_x32_MASK) /*! @} */ /*! @name RFSHCTL0 - Refresh Control Register 0 */ /*! @{ */ #define DDRC_RFSHCTL0_per_bank_refresh_MASK (0x4U) #define DDRC_RFSHCTL0_per_bank_refresh_SHIFT (2U) /*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is * not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 * 0b1..Per bank refresh * 0b0..All bank refresh */ #define DDRC_RFSHCTL0_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_per_bank_refresh_MASK) #define DDRC_RFSHCTL0_refresh_burst_MASK (0x1F0U) #define DDRC_RFSHCTL0_refresh_burst_SHIFT (4U) /*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to * accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to * perform a refresh is a one-time penalty that must be paid for each group of refreshes. * Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. * Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases * the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2 * refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of * DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not * per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh * feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X * mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care * must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated * due to a PHY-initiated update occurring shortly before a refresh burst was due. In this * situation, the refresh burst will be delayed until the PHY-initiated update is complete. */ #define DDRC_RFSHCTL0_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_refresh_burst_MASK) #define DDRC_RFSHCTL0_refresh_to_x32_MASK (0x1F000U) #define DDRC_RFSHCTL0_refresh_to_x32_SHIFT (12U) /*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, * but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be * performed. A speculative refresh is a refresh performed at a time when refresh would be * useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time * determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since * the last refresh, then a speculative refresh is performed. Speculative refreshes continues * successively until there are no refreshes pending or until new reads or writes are issued to the * DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks. */ #define DDRC_RFSHCTL0_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_refresh_to_x32_MASK) #define DDRC_RFSHCTL0_refresh_margin_MASK (0xF00000U) #define DDRC_RFSHCTL0_refresh_margin_SHIFT (20U) /*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or * page timer expires. A critical refresh is to be issued before this threshold is reached. It is * recommended that this not be changed from the default value, currently shown as 0x2. It must * always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, * internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled * (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to * RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks. */ #define DDRC_RFSHCTL0_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_refresh_margin_MASK) /*! @} */ /*! @name RFSHCTL1 - Refresh Control Register 1 */ /*! @{ */ #define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU) #define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U) /*! refresh_timer0_start_value_x32 - Refresh timer start for rank 0 (only present in multi-rank * configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to * proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples * of 32 DFI clock cycles. FOR PERFORMANCE ONLY. */ #define DDRC_RFSHCTL1_refresh_timer0_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK) #define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U) #define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U) /*! refresh_timer1_start_value_x32 - Refresh timer start for rank 1 (only present in multi-rank * configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to * proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples * of 32 DFI clock cycles. FOR PERFORMANCE ONLY. */ #define DDRC_RFSHCTL1_refresh_timer1_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK) /*! @} */ /*! @name RFSHCTL3 - Refresh Control Register 3 */ /*! @{ */ #define DDRC_RFSHCTL3_dis_auto_refresh_MASK (0x1U) #define DDRC_RFSHCTL3_dis_auto_refresh_SHIFT (0U) /*! dis_auto_refresh - When '1', disable auto-refresh generated by the DDRC. When auto-refresh is * disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh, * reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis_auto_refresh * transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRC. If DDR4 * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is * not supported, and this bit must be set to '0'. (DDR4 only) If FGR mode is enabled * (RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. This * register field is changeable on the fly. */ #define DDRC_RFSHCTL3_dis_auto_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_RFSHCTL3_dis_auto_refresh_MASK) #define DDRC_RFSHCTL3_refresh_update_level_MASK (0x2U) #define DDRC_RFSHCTL3_refresh_update_level_SHIFT (1U) /*! refresh_update_level - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that * the refresh register(s) have been updated. refresh_update_level must not be toggled when the * DDRC is in reset (core_ddrc_rstn = 0). The refresh register(s) are automatically updated when * exiting reset. */ #define DDRC_RFSHCTL3_refresh_update_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_update_level_SHIFT)) & DDRC_RFSHCTL3_refresh_update_level_MASK) #define DDRC_RFSHCTL3_refresh_mode_MASK (0x70U) #define DDRC_RFSHCTL3_refresh_mode_SHIFT (4U) /*! refresh_mode - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - * 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not * supported) - Everything else - reserved Note: Only Fixed 1x mode is supported if * RFSHCTL3.dis_auto_refresh = 1. Note: The on-the-fly modes are not supported in this version of the DDRC. * Note: This must be set up while the Controller is in reset or while the Controller is in * self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic * register will be supported in future version of the DDRC. Note: This register field has effect only * if a DDR4 SDRAM device is in use (MSTR.ddr4 = 1). */ #define DDRC_RFSHCTL3_refresh_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_RFSHCTL3_refresh_mode_MASK) /*! @} */ /*! @name RFSHTMG - Refresh Timing Register */ /*! @{ */ #define DDRC_RFSHTMG_t_rfc_min_MASK (0x3FFU) #define DDRC_RFSHTMG_t_rfc_min_SHIFT (0U) /*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is * operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller * is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In * LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations * is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is * equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending * on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the * appropriate value from the spec based on the 'refresh_mode' and the device density that is used. * Unit: Clocks. */ #define DDRC_RFSHTMG_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_t_rfc_min_MASK) #define DDRC_RFSHTMG_lpddr3_trefbw_en_MASK (0x8000U) #define DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT (15U) /*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when * DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 * devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW * parameter not used - 1 - tREFBW parameter used */ #define DDRC_RFSHTMG_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_lpddr3_trefbw_en_MASK) #define DDRC_RFSHTMG_t_rfc_nom_x32_MASK (0xFFF0000U) #define DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT (16U) /*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us * for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For * LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register * should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this * register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode, * program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending * on the refresh mode. The user should program the appropriate value from the spec based on the * value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be * greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or * DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed * 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode: * RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks. */ #define DDRC_RFSHTMG_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_t_rfc_nom_x32_MASK) /*! @} */ /*! @name INIT0 - SDRAM Initialization Register 0 */ /*! @{ */ #define DDRC_INIT0_pre_cke_x1024_MASK (0xFFFU) #define DDRC_INIT0_pre_cke_x1024_SHIFT (0U) /*! pre_cke_x1024 - Cycles to wait after reset before driving CKE high to start the SDRAM * initialization sequence. Unit: 1024 DFI clock cycles. DDR2 specifications typically require this to be * programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 * ms (min) When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC * spec value divided by 2, and round it up to the next integer value. For DDR3/DDR4 RDIMMs, this * should include the time needed to satisfy tSTAB */ #define DDRC_INIT0_pre_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_pre_cke_x1024_SHIFT)) & DDRC_INIT0_pre_cke_x1024_MASK) #define DDRC_INIT0_post_cke_x1024_MASK (0x3FF0000U) #define DDRC_INIT0_post_cke_x1024_SHIFT (16U) /*! post_cke_x1024 - Cycles to wait after driving CKE high to start the SDRAM initialization * sequence. Unit: 1024 DFI clock cycles. DDR2 typically requires a 400 ns delay, requiring this value * to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be * programmed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. * When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec * value divided by 2, and round it up to the next integer value. */ #define DDRC_INIT0_post_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_post_cke_x1024_SHIFT)) & DDRC_INIT0_post_cke_x1024_MASK) #define DDRC_INIT0_skip_dram_init_MASK (0xC0000000U) #define DDRC_INIT0_skip_dram_init_SHIFT (30U) /*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper * bit decides what state the controller starts up in when reset is removed - 00 - SDRAM * Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after * power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after * power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run * after power-up. * 0b00..SDRAM Initialization routine is run after power-up * 0b01..SDRAM Initialization routine is skipped after power-up * 0b10..SDRAM Initialization routine is run after power-up * 0b11..SDRAM Initialization routine is skipped after power-up */ #define DDRC_INIT0_skip_dram_init(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_skip_dram_init_SHIFT)) & DDRC_INIT0_skip_dram_init_MASK) /*! @} */ /*! @name INIT1 - SDRAM Initialization Register 1 */ /*! @{ */ #define DDRC_INIT1_pre_ocd_x32_MASK (0xFU) #define DDRC_INIT1_pre_ocd_x32_SHIFT (0U) /*! pre_ocd_x32 - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a * global timer that pulses every 32 DFI clock cycles. There is no known specific requirement for * this; it may be set to zero. */ #define DDRC_INIT1_pre_ocd_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_pre_ocd_x32_SHIFT)) & DDRC_INIT1_pre_ocd_x32_MASK) #define DDRC_INIT1_dram_rstn_x1024_MASK (0x1FF0000U) #define DDRC_INIT1_dram_rstn_x1024_SHIFT (16U) /*! dram_rstn_x1024 - Number of cycles to assert SDRAM reset signal during init sequence. This is * only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this * should be set to a minimum of 1. When the controller is operating in 1:2 frequency ratio mode, * program this to JEDEC spec value divided by 2, and round it up to the next integer value. * Unit: 1024 DFI clock cycles. */ #define DDRC_INIT1_dram_rstn_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_INIT1_dram_rstn_x1024_MASK) /*! @} */ /*! @name INIT2 - SDRAM Initialization Register 2 */ /*! @{ */ #define DDRC_INIT2_min_stable_clock_x1_MASK (0xFU) #define DDRC_INIT2_min_stable_clock_x1_SHIFT (0U) /*! min_stable_clock_x1 - Time to wait after the first CKE high, tINIT2. Present only in designs * configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the * controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by * 2, and round it up to the next integer value. Unit: DFI clock cycles. */ #define DDRC_INIT2_min_stable_clock_x1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_INIT2_min_stable_clock_x1_MASK) #define DDRC_INIT2_idle_after_reset_x32_MASK (0xFF00U) #define DDRC_INIT2_idle_after_reset_x32_SHIFT (8U) /*! idle_after_reset_x32 - Idle time after the reset command, tINIT4. Present only in designs * configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode, program * this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI * clock cycles. */ #define DDRC_INIT2_idle_after_reset_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_INIT2_idle_after_reset_x32_MASK) /*! @} */ /*! @name INIT3 - SDRAM Initialization Register 3 */ /*! @{ */ #define DDRC_INIT3_emr_MASK (0xFFFFU) #define DDRC_INIT3_emr_SHIFT (0U) /*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this * register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1 * register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by * the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - * Value to write to MR2 register */ #define DDRC_INIT3_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_emr_SHIFT)) & DDRC_INIT3_emr_MASK) #define DDRC_INIT3_mr_MASK (0xFFFF0000U) #define DDRC_INIT3_mr_SHIFT (16U) /*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The * DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to * write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register */ #define DDRC_INIT3_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_mr_SHIFT)) & DDRC_INIT3_mr_MASK) /*! @} */ /*! @name INIT4 - SDRAM Initialization Register 4 */ /*! @{ */ #define DDRC_INIT4_emr3_MASK (0xFFFFU) #define DDRC_INIT4_emr3_SHIFT (0U) /*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register * mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register */ #define DDRC_INIT4_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr3_SHIFT)) & DDRC_INIT4_emr3_MASK) #define DDRC_INIT4_emr2_MASK (0xFFFF0000U) #define DDRC_INIT4_emr2_SHIFT (16U) /*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register * LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused */ #define DDRC_INIT4_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr2_SHIFT)) & DDRC_INIT4_emr2_MASK) /*! @} */ /*! @name INIT5 - SDRAM Initialization Register 5 */ /*! @{ */ #define DDRC_INIT5_max_auto_init_x1024_MASK (0x3FFU) #define DDRC_INIT5_max_auto_init_x1024_SHIFT (0U) /*! max_auto_init_x1024 - Maximum duration of the auto initialization, tINIT5. Present only in * designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: 1024 DFI * clock cycles. */ #define DDRC_INIT5_max_auto_init_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_INIT5_max_auto_init_x1024_MASK) #define DDRC_INIT5_dev_zqinit_x32_MASK (0xFF0000U) #define DDRC_INIT5_dev_zqinit_x32_SHIFT (16U) /*! dev_zqinit_x32 - ZQ initial calibration, tZQINIT. Present only in designs configured to support * DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires * 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the controller is operating in 1:2 * frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the * next integer value. Unit: 32 DFI clock cycles. */ #define DDRC_INIT5_dev_zqinit_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_INIT5_dev_zqinit_x32_MASK) /*! @} */ /*! @name INIT6 - SDRAM Initialization Register 6 */ /*! @{ */ #define DDRC_INIT6_mr5_MASK (0xFFFFU) #define DDRC_INIT6_mr5_SHIFT (0U) /*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. */ #define DDRC_INIT6_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr5_SHIFT)) & DDRC_INIT6_mr5_MASK) #define DDRC_INIT6_mr4_MASK (0xFFFF0000U) #define DDRC_INIT6_mr4_SHIFT (16U) /*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. */ #define DDRC_INIT6_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr4_SHIFT)) & DDRC_INIT6_mr4_MASK) /*! @} */ /*! @name INIT7 - SDRAM Initialization Register 7 */ /*! @{ */ #define DDRC_INIT7_mr6_MASK (0xFFFF0000U) #define DDRC_INIT7_mr6_SHIFT (16U) /*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. */ #define DDRC_INIT7_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_mr6_SHIFT)) & DDRC_INIT7_mr6_MASK) /*! @} */ /*! @name DIMMCTL - DIMM Control Register */ /*! @{ */ #define DDRC_DIMMCTL_dimm_stagger_cs_en_MASK (0x1U) #define DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT (0U) /*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and * LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. * Even if this bit is set it does not take care of software driven MR commands (via * MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate. * 0b0..Do not stagger accesses * 0b1..(non-DDR4) Send all commands to even and odd ranks separately * 0b1..(DDR4) Send MRS commands to each ranks separately */ #define DDRC_DIMMCTL_dimm_stagger_cs_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_DIMMCTL_dimm_stagger_cs_en_MASK) #define DDRC_DIMMCTL_dimm_addr_mirr_en_MASK (0x2U) #define DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT (1U) /*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and * multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address * mirroring for odd ranks, which means that the following address, bank address and bank group * bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for * the DDR4. Setting this bit ensures that, for mode register accesses during the automatic * initialization routine, these bits are swapped within the DDRC to compensate for this * UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 * UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular * DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of * software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 * SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 * because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. * 0b0..Do not implement address mirroring * 0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any * automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring) */ #define DDRC_DIMMCTL_dimm_addr_mirr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_DIMMCTL_dimm_addr_mirr_en_MASK) #define DDRC_DIMMCTL_dimm_output_inv_en_MASK (0x4U) #define DDRC_DIMMCTL_dimm_output_inv_en_SHIFT (2U) /*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4 * RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the * following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, * A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the * DDRC during the automatic initialization routine and enabling of a particular DDR4 feature, * separate A-side and B-side mode register accesses are generated. For B-side mode register * accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It * is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect * on the address of any other memory accesses, or of software-driven mode register accesses. * 0b0..Do not implement output inversion for B-side DRAMs. * 0b1..Implement output inversion for B-side DRAMs. */ #define DDRC_DIMMCTL_dimm_output_inv_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_DIMMCTL_dimm_output_inv_en_MASK) #define DDRC_DIMMCTL_mrs_a17_en_MASK (0x8U) #define DDRC_DIMMCTL_mrs_a17_en_SHIFT (3U) /*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs * which do not have A17 are attached and the Output Inversion are enabled, this must be set to * 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on * the address of any other memory accesses, or of software-driven mode register accesses. * 0b0..Disabled * 0b1..Enabled */ #define DDRC_DIMMCTL_mrs_a17_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_DIMMCTL_mrs_a17_en_MASK) #define DDRC_DIMMCTL_mrs_bg1_en_MASK (0x10U) #define DDRC_DIMMCTL_mrs_bg1_en_SHIFT (4U) /*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs * which do not have BG1 are attached and both the CA parity and the Output Inversion are * enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: * This has no effect on the address of any other memory accesses, or of software-driven mode * register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0 * of odd ranks. * 0b0..Disabled * 0b1..Enabled */ #define DDRC_DIMMCTL_mrs_bg1_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_DIMMCTL_mrs_bg1_en_MASK) #define DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK (0x20U) #define DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U) /*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and * BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs * with x16 devices. * 0b0..BG0 and BG1 are swapped if address mirroring is enabled. * 0b1..BG0 and BG1 are NOT swapped. */ #define DDRC_DIMMCTL_dimm_dis_bg_mirroring(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK) #define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK (0x40U) #define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT (6U) /*! lrdimm_bcom_cmd_prot - Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM * commands defined in the Data Buffer specification. When using DDR4 LRDIMM, this bit must be set * to 1. Otherwise, this bit must be set to 0. */ #define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK) /*! @} */ /*! @name RANKCTL - Rank Control Register */ /*! @{ */ #define DDRC_RANKCTL_max_rank_rd_MASK (0xFU) #define DDRC_RANKCTL_max_rank_rd_SHIFT (0U) /*! max_rank_rd - Only present for multi-rank configurations. Background: Reads to the same rank can * be performed back-to-back. Reads to different ranks require additional gap dictated by the * register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to * give PHY enough time to switch the delay when changing ranks. The DDRC arbitrates for bus * access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles * (determined by the value on RANKCTL.diff_rank_rd_gap register) in which only reads from the * same rank are eligible to be scheduled. This prevents reads from other ranks from having fair * access to the data bus. This parameter represents the maximum number of reads that can be * scheduled consecutively to the same rank. After this number is reached, a delay equal to * RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be * scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This * feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on * the same rank as long as commands are available for it. Minimum programmable value is 0 (feature * disabled) and maximum programmable value is 0xF. FOR PERFORMANCE ONLY. */ #define DDRC_RANKCTL_max_rank_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_max_rank_rd_SHIFT)) & DDRC_RANKCTL_max_rank_rd_MASK) #define DDRC_RANKCTL_diff_rank_rd_gap_MASK (0xF0U) #define DDRC_RANKCTL_diff_rank_rd_gap_SHIFT (4U) /*! diff_rank_rd_gap - Only present for multi-rank configurations. Indicates the number of clocks of * gap in data responses when performing consecutive reads to different ranks. This is used to * switch the delays in the PHY to match the rank requirements. This value should consider both * PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for * value of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased * by 1. If read postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT * requirement: The value programmed in this register takes care of the ODT switch off timing requirement * when switching ranks during reads. When the controller is operating in 1:1 mode, program this * to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2 * mode, program this to the larger value divided by two and round it up to the next integer. * Note that, if using DDR4-LRDIMM, refer to TRDRD timing requirements in JEDEC DDR4 Data Buffer * (DDR4DB01) Specification. */ #define DDRC_RANKCTL_diff_rank_rd_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_rd_gap_MASK) #define DDRC_RANKCTL_diff_rank_wr_gap_MASK (0xF00U) #define DDRC_RANKCTL_diff_rank_wr_gap_SHIFT (8U) /*! diff_rank_wr_gap - Only present for multi-rank configurations. Indicates the number of clocks of * gap in data responses when performing consecutive writes to different ranks. This is used to * switch the delays in the PHY to match the rank requirements. This value should consider both * PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for * value of tphy_wrcsgap) If CRC feature is enabled, should be increased by 1. If write preamble * is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If write postamble is set to * 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this * register takes care of the ODT switch off timing requirement when switching ranks during writes. * For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 When the controller is operating in * 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the * controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to * the next integer. Note that, if using DDR4-LRDIMM, refer to TWRWR timing requirements in * JEDEC DDR4 Data Buffer (DDR4DB01) Specification. */ #define DDRC_RANKCTL_diff_rank_wr_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_wr_gap_MASK) /*! @} */ /*! @name DRAMTMG0 - SDRAM Timing Register 0 */ /*! @{ */ #define DDRC_DRAMTMG0_t_ras_min_MASK (0x3FU) #define DDRC_DRAMTMG0_t_ras_min_SHIFT (0U) /*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the * controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding * up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, * program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks */ #define DDRC_DRAMTMG0_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_t_ras_min_MASK) #define DDRC_DRAMTMG0_t_ras_max_MASK (0x7F00U) #define DDRC_DRAMTMG0_t_ras_max_SHIFT (8U) /*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the * maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. * When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2. * No rounding up. Unit: Multiples of 1024 clocks. */ #define DDRC_DRAMTMG0_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_t_ras_max_MASK) #define DDRC_DRAMTMG0_t_faw_MASK (0x3F0000U) #define DDRC_DRAMTMG0_t_faw_SHIFT (16U) /*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank * design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller * is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next * integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency * mode. Unit: Clocks */ #define DDRC_DRAMTMG0_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_faw_SHIFT)) & DDRC_DRAMTMG0_t_faw_MASK) #define DDRC_DRAMTMG0_wr2pre_MASK (0x7F000000U) #define DDRC_DRAMTMG0_wr2pre_SHIFT (24U) /*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL * + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower * frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in * the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. * - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra * cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2 * frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller * is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2 * and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it * may be necessary to adjust the value of this parameter to compensate for the extra cycle of * latency through the LRDIMM. */ #define DDRC_DRAMTMG0_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_wr2pre_SHIFT)) & DDRC_DRAMTMG0_wr2pre_MASK) /*! @} */ /*! @name DRAMTMG1 - SDRAM Timing Register 1 */ /*! @{ */ #define DDRC_DRAMTMG1_t_rc_MASK (0x7FU) #define DDRC_DRAMTMG1_t_rc_SHIFT (0U) /*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2 * frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit: * Clocks. */ #define DDRC_DRAMTMG1_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_rc_SHIFT)) & DDRC_DRAMTMG1_t_rc_MASK) #define DDRC_DRAMTMG1_rd2pre_MASK (0x3F00U) #define DDRC_DRAMTMG1_rd2pre_SHIFT (8U) /*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, * 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4) * or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: * LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 * - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, * use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode, * divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T * mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. * Unit: Clocks. */ #define DDRC_DRAMTMG1_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_rd2pre_SHIFT)) & DDRC_DRAMTMG1_rd2pre_MASK) #define DDRC_DRAMTMG1_t_xp_MASK (0x1F0000U) #define DDRC_DRAMTMG1_t_xp_SHIFT (16U) /*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be * programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used, * set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program * this to (tXP/2) and round it up to the next integer value. Units: Clocks */ #define DDRC_DRAMTMG1_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_xp_SHIFT)) & DDRC_DRAMTMG1_t_xp_MASK) /*! @} */ /*! @name DRAMTMG2 - SDRAM Timing Register 2 */ /*! @{ */ #define DDRC_DRAMTMG2_wr2rd_MASK (0x3FU) #define DDRC_DRAMTMG2_wr2rd_SHIFT (0U) /*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from * write command to read command for same bank group. In others, minimum time from write command to * read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and * global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL * = burst length. This must match the value programmed in the BL bit of the mode register to * the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes * directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes * directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. * When the controller is operating in 1:2 mode, divide the value calculated using the above * equation by 2, and round it up to next integer. */ #define DDRC_DRAMTMG2_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_wr2rd_SHIFT)) & DDRC_DRAMTMG2_wr2rd_MASK) #define DDRC_DRAMTMG2_rd2wr_MASK (0x3F00U) #define DDRC_DRAMTMG2_rd2wr_SHIFT (8U) /*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL * + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) * + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + * RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. * Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see * the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: - * WL = write latency - BL = burst length. This must match the value programmed in the BL bit of * the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write * preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to * LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated * tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the * value calculated using the above equation by 2, and round it up to next integer. Note that, * depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter * to compensate for the extra cycle of latency through the LRDIMM. */ #define DDRC_DRAMTMG2_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_rd2wr_SHIFT)) & DDRC_DRAMTMG2_rd2wr_MASK) #define DDRC_DRAMTMG2_read_latency_MASK (0x3F0000U) #define DDRC_DRAMTMG2_read_latency_SHIFT (16U) /*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be * set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust * the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When * the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the * above equation by 2, and round it up to next integer. This register field is not required for * DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in * DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks */ #define DDRC_DRAMTMG2_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_read_latency_SHIFT)) & DDRC_DRAMTMG2_read_latency_MASK) #define DDRC_DRAMTMG2_write_latency_MASK (0x3F000000U) #define DDRC_DRAMTMG2_write_latency_SHIFT (24U) /*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be * set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if * using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra * cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio * mode, divide the value calculated using the above equation by 2, and round it up to next * integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), * as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those * protocols Unit: clocks */ #define DDRC_DRAMTMG2_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_write_latency_SHIFT)) & DDRC_DRAMTMG2_write_latency_MASK) /*! @} */ /*! @name DRAMTMG3 - SDRAM Timing Register 3 */ /*! @{ */ #define DDRC_DRAMTMG3_t_mod_MASK (0x3FFU) #define DDRC_DRAMTMG3_t_mod_SHIFT (0U) /*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and * following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. * Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to * next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using * RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to * compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip. * Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller * is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if * controller is operating in 1:2 frequency ratio mode. */ #define DDRC_DRAMTMG3_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mod_SHIFT)) & DDRC_DRAMTMG3_t_mod_MASK) #define DDRC_DRAMTMG3_t_mrd_MASK (0x3F000U) #define DDRC_DRAMTMG3_t_mrd_SHIFT (12U) /*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected * SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS * command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is * operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer * value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. */ #define DDRC_DRAMTMG3_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrd_SHIFT)) & DDRC_DRAMTMG3_t_mrd_MASK) #define DDRC_DRAMTMG3_t_mrw_MASK (0x3FF00000U) #define DDRC_DRAMTMG3_t_mrw_SHIFT (20U) /*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs * configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 * typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, * this register is used for the time from a MRW/MRR to all other commands. When the controller * is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and * round it up to the next integer value. For LDPDR3, this register is used for the time from a * MRW/MRR to a MRW/MRR. */ #define DDRC_DRAMTMG3_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrw_SHIFT)) & DDRC_DRAMTMG3_t_mrw_MASK) /*! @} */ /*! @name DRAMTMG4 - SDRAM Timing Register 4 */ /*! @{ */ #define DDRC_DRAMTMG4_t_rp_MASK (0x1FU) #define DDRC_DRAMTMG4_t_rp_SHIFT (0U) /*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is * operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is * operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + * 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set * to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. */ #define DDRC_DRAMTMG4_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rp_SHIFT)) & DDRC_DRAMTMG4_t_rp_MASK) #define DDRC_DRAMTMG4_t_rrd_MASK (0xF00U) #define DDRC_DRAMTMG4_t_rrd_SHIFT (8U) /*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank * group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller * is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it * up to the next integer value. Unit: Clocks. */ #define DDRC_DRAMTMG4_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rrd_SHIFT)) & DDRC_DRAMTMG4_t_rrd_MASK) #define DDRC_DRAMTMG4_t_ccd_MASK (0xF0000U) #define DDRC_DRAMTMG4_t_ccd_SHIFT (16U) /*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank * group. Others: tCCD: This is the minimum time between two reads or two writes. When the * controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it * up to the next integer value. Unit: clocks. */ #define DDRC_DRAMTMG4_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_ccd_SHIFT)) & DDRC_DRAMTMG4_t_ccd_MASK) #define DDRC_DRAMTMG4_t_rcd_MASK (0x1F000000U) #define DDRC_DRAMTMG4_t_rcd_SHIFT (24U) /*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the * controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round * it up to the next integer value. Minimum value allowed for this register is 1, which implies * minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio * mode. Unit: Clocks. */ #define DDRC_DRAMTMG4_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rcd_SHIFT)) & DDRC_DRAMTMG4_t_rcd_MASK) /*! @} */ /*! @name DRAMTMG5 - SDRAM Timing Register 5 */ /*! @{ */ #define DDRC_DRAMTMG5_t_cke_MASK (0x1FU) #define DDRC_DRAMTMG5_t_cke_SHIFT (0U) /*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - * LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of * tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When * the controller is operating in 1:2 frequency ratio mode, program this to (value described * above)/2 and round it up to the next integer value. Unit: Clocks. */ #define DDRC_DRAMTMG5_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cke_SHIFT)) & DDRC_DRAMTMG5_t_cke_MASK) #define DDRC_DRAMTMG5_t_ckesr_MASK (0x3F00U) #define DDRC_DRAMTMG5_t_ckesr_SHIFT (8U) /*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing * in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR * - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity * latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased * by PL. When the controller is operating in 1:2 frequency ratio mode, program this to * recommended value divided by two and round it up to next integer. */ #define DDRC_DRAMTMG5_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_t_ckesr_MASK) #define DDRC_DRAMTMG5_t_cksre_MASK (0xF0000U) #define DDRC_DRAMTMG5_t_cksre_SHIFT (16U) /*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. * Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - * LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+ * PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should * be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program * this to recommended value divided by two and round it up to next integer. */ #define DDRC_DRAMTMG5_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksre_SHIFT)) & DDRC_DRAMTMG5_t_cksre_MASK) #define DDRC_DRAMTMG5_t_cksrx_MASK (0xF000000U) #define DDRC_DRAMTMG5_t_cksrx_SHIFT (24U) /*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock * before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 - * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the * controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by * two and round it up to next integer. */ #define DDRC_DRAMTMG5_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_t_cksrx_MASK) /*! @} */ /*! @name DRAMTMG6 - SDRAM Timing Register 6 */ /*! @{ */ #define DDRC_DRAMTMG6_t_ckcsx_MASK (0xFU) #define DDRC_DRAMTMG6_t_ckcsx_SHIFT (0U) /*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before * issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop * Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 * When the controller is operating in 1:2 frequency ratio mode, program this to recommended value * divided by two and round it up to next integer. This is only present for designs supporting * mDDR or LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_DRAMTMG6_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_t_ckcsx_MASK) #define DDRC_DRAMTMG6_t_ckdpdx_MASK (0xF0000U) #define DDRC_DRAMTMG6_t_ckdpdx_SHIFT (16U) /*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock * before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR: * 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, * program this to recommended value divided by two and round it up to next integer. This is only * present for designs supporting mDDR or LPDDR2 devices. */ #define DDRC_DRAMTMG6_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_t_ckdpdx_MASK) #define DDRC_DRAMTMG6_t_ckdpde_MASK (0xF000000U) #define DDRC_DRAMTMG6_t_ckdpde_SHIFT (24U) /*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock. * Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - * LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to * recommended value divided by two and round it up to next integer. This is only present for designs * supporting mDDR or LPDDR2/LPDDR3 devices. */ #define DDRC_DRAMTMG6_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_t_ckdpde_MASK) /*! @} */ /*! @name DRAMTMG7 - SDRAM Timing Register 7 */ /*! @{ */ #define DDRC_DRAMTMG7_t_ckpdx_MASK (0xFU) #define DDRC_DRAMTMG7_t_ckpdx_SHIFT (0U) /*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before * issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 - * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the * same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode, * program this to recommended value divided by two and round it up to next integer. This is only * present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_DRAMTMG7_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_t_ckpdx_MASK) #define DDRC_DRAMTMG7_t_ckpde_MASK (0xF00U) #define DDRC_DRAMTMG7_t_ckpde_SHIFT (8U) /*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock. * Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 * - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as * DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this * to recommended value divided by two and round it up to next integer. This is only present for * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_DRAMTMG7_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_t_ckpde_MASK) /*! @} */ /*! @name DRAMTMG8 - SDRAM Timing Register 8 */ /*! @{ */ #define DDRC_DRAMTMG8_t_xs_x32_MASK (0x7FU) #define DDRC_DRAMTMG8_t_xs_x32_SHIFT (0U) /*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is * operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round * up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and * DDR4 SDRAMs. */ #define DDRC_DRAMTMG8_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_x32_MASK) #define DDRC_DRAMTMG8_t_xs_dll_x32_MASK (0x7F00U) #define DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT (8U) /*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller * is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and * round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and * DDR4 SDRAMs. */ #define DDRC_DRAMTMG8_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_dll_x32_MASK) #define DDRC_DRAMTMG8_t_xs_abort_x32_MASK (0x7F0000U) #define DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT (16U) /*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self * Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. * Note: Ensure this is less than or equal to t_xs_x32. */ #define DDRC_DRAMTMG8_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_abort_x32_MASK) #define DDRC_DRAMTMG8_t_xs_fast_x32_MASK (0x7F000000U) #define DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT (24U) /*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown * mode). When the controller is operating in 1:2 frequency ratio mode, program this to the * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: * This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to * t_xs_x32. */ #define DDRC_DRAMTMG8_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_fast_x32_MASK) /*! @} */ /*! @name DRAMTMG9 - SDRAM Timing Register 9 */ /*! @{ */ #define DDRC_DRAMTMG9_wr2rd_s_MASK (0x3FU) #define DDRC_DRAMTMG9_wr2rd_s_SHIFT (0U) /*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different * bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and * global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where: * - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value * programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read * command delay for different bank group. This comes directly from the SDRAM specification. When * the controller is operating in 1:2 mode, divide the value calculated using the above equation * by 2, and round it up to next integer. */ #define DDRC_DRAMTMG9_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_wr2rd_s_MASK) #define DDRC_DRAMTMG9_t_rrd_s_MASK (0xF00U) #define DDRC_DRAMTMG9_t_rrd_s_SHIFT (8U) /*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank * group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2) * and round it up to the next integer value. Present only in designs configured to support DDR4. * Unit: Clocks. */ #define DDRC_DRAMTMG9_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_t_rrd_s_MASK) #define DDRC_DRAMTMG9_t_ccd_s_MASK (0x70000U) #define DDRC_DRAMTMG9_t_ccd_s_SHIFT (16U) /*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank * group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When * the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round * it up to the next integer value. Present only in designs configured to support DDR4. Unit: * clocks. */ #define DDRC_DRAMTMG9_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_t_ccd_s_MASK) #define DDRC_DRAMTMG9_ddr4_wr_preamble_MASK (0x40000000U) #define DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT (30U) /*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 */ #define DDRC_DRAMTMG9_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_ddr4_wr_preamble_MASK) /*! @} */ /*! @name DRAMTMG10 - SDRAM Timing Register 10 */ /*! @{ */ #define DDRC_DRAMTMG10_t_gear_hold_MASK (0x3U) #define DDRC_DRAMTMG10_t_gear_hold_SHIFT (0U) /*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in * 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer * value. Unit: Clocks */ #define DDRC_DRAMTMG10_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_t_gear_hold_MASK) #define DDRC_DRAMTMG10_t_gear_setup_MASK (0xCU) #define DDRC_DRAMTMG10_t_gear_setup_SHIFT (2U) /*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in * 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer * value. Unit: Clocks */ #define DDRC_DRAMTMG10_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_t_gear_setup_MASK) #define DDRC_DRAMTMG10_t_cmd_gear_MASK (0x1F00U) #define DDRC_DRAMTMG10_t_cmd_gear_SHIFT (8U) /*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is * defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for * this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2) * and round it up to the next integer value. Unit: Clocks */ #define DDRC_DRAMTMG10_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_t_cmd_gear_MASK) #define DDRC_DRAMTMG10_t_sync_gear_MASK (0x1F0000U) #define DDRC_DRAMTMG10_t_sync_gear_SHIFT (16U) /*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even * number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK * tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28 * When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up * to the next integer value. Unit: Clocks */ #define DDRC_DRAMTMG10_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_t_sync_gear_MASK) /*! @} */ /*! @name DRAMTMG11 - SDRAM Timing Register 11 */ /*! @{ */ #define DDRC_DRAMTMG11_t_ckmpe_MASK (0x1FU) #define DDRC_DRAMTMG11_t_ckmpe_SHIFT (0U) /*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs * configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio * mode, divide the value calculated using the above equation by 2, and round it up to next * integer. */ #define DDRC_DRAMTMG11_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_t_ckmpe_MASK) #define DDRC_DRAMTMG11_t_mpx_s_MASK (0x300U) #define DDRC_DRAMTMG11_t_mpx_s_SHIFT (8U) /*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2 * frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value. * Present only in designs configured to support DDR4. Unit: Clocks. */ #define DDRC_DRAMTMG11_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_t_mpx_s_MASK) #define DDRC_DRAMTMG11_t_mpx_lh_MASK (0x1F0000U) #define DDRC_DRAMTMG11_t_mpx_lh_SHIFT (16U) /*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the * controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present * only in designs configured to support DDR4. Unit: clocks. */ #define DDRC_DRAMTMG11_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_t_mpx_lh_MASK) #define DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK (0x7F000000U) #define DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT (24U) /*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. * When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and * round it up to the next integer value. Present only in designs configured to support DDR4. * Unit: Multiples of 32 clocks. */ #define DDRC_DRAMTMG11_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK) /*! @} */ /*! @name DRAMTMG12 - SDRAM Timing Register 12 */ /*! @{ */ #define DDRC_DRAMTMG12_t_mrd_pda_MASK (0x1FU) #define DDRC_DRAMTMG12_t_mrd_pda_SHIFT (0U) /*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the * controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up * to the next integer value. */ #define DDRC_DRAMTMG12_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_t_mrd_pda_MASK) #define DDRC_DRAMTMG12_t_ckehcmd_MASK (0xF00U) #define DDRC_DRAMTMG12_t_ckehcmd_SHIFT (8U) /*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is * operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next * integer value. */ #define DDRC_DRAMTMG12_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_t_ckehcmd_MASK) #define DDRC_DRAMTMG12_t_cmdcke_MASK (0x30000U) #define DDRC_DRAMTMG12_t_cmdcke_SHIFT (16U) /*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE * or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to * (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value. */ #define DDRC_DRAMTMG12_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_t_cmdcke_MASK) /*! @} */ /*! @name DRAMTMG13 - SDRAM Timing Register 13 */ /*! @{ */ #define DDRC_DRAMTMG13_t_ppd_MASK (0x7U) #define DDRC_DRAMTMG13_t_ppd_SHIFT (0U) /*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the * controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to * the next integer value. Unit: Clocks. */ #define DDRC_DRAMTMG13_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ppd_SHIFT)) & DDRC_DRAMTMG13_t_ppd_MASK) #define DDRC_DRAMTMG13_t_ccd_mw_MASK (0x3F0000U) #define DDRC_DRAMTMG13_t_ccd_mw_SHIFT (16U) /*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write * command for same bank. When the controller is operating in 1:2 frequency ratio mode, program * this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks. */ #define DDRC_DRAMTMG13_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_t_ccd_mw_MASK) #define DDRC_DRAMTMG13_odtloff_MASK (0x7F000000U) #define DDRC_DRAMTMG13_odtloff_SHIFT (24U) /*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When * the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round * it up to the next integer value. Unit: Clocks. */ #define DDRC_DRAMTMG13_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_odtloff_SHIFT)) & DDRC_DRAMTMG13_odtloff_MASK) /*! @} */ /*! @name DRAMTMG14 - SDRAM Timing Register 14 */ /*! @{ */ #define DDRC_DRAMTMG14_t_xsr_MASK (0xFFFU) #define DDRC_DRAMTMG14_t_xsr_SHIFT (0U) /*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2 * frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. * Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode. */ #define DDRC_DRAMTMG14_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_t_xsr_SHIFT)) & DDRC_DRAMTMG14_t_xsr_MASK) /*! @} */ /*! @name DRAMTMG15 - SDRAM Timing Register 15 */ /*! @{ */ #define DDRC_DRAMTMG15_t_stab_x32_MASK (0xFFU) #define DDRC_DRAMTMG15_t_stab_x32_SHIFT (0U) /*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 * RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the * clock must be stable for a time specified by tSTAB - in the case of input clock frequency * change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for * DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to * recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock * cycles. */ #define DDRC_DRAMTMG15_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_t_stab_x32_MASK) #define DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK (0x80000000U) #define DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT (31U) /*! en_dfi_lp_t_stab - Enable DFI tSTAB * 0b0..Disable using tSTAB when exiting DFI LP * 0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ #define DDRC_DRAMTMG15_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK) /*! @} */ /*! @name ZQCTL0 - ZQ Control Register 0 */ /*! @{ */ #define DDRC_ZQCTL0_t_zq_short_nop_MASK (0x3FFU) #define DDRC_ZQCTL0_t_zq_short_nop_SHIFT (0U) /*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles * of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. * When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and * round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or * LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_ZQCTL0_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_short_nop_MASK) #define DDRC_ZQCTL0_t_zq_long_nop_MASK (0x7FF0000U) #define DDRC_ZQCTL0_t_zq_long_nop_SHIFT (16U) /*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI * clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is * issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program * this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to * tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it * up to the next integer value. This is only present for designs supporting DDR3/DDR4 or * LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_ZQCTL0_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_long_nop_MASK) #define DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK (0x10000000U) #define DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT (28U) /*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC * configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting * MPSM mode. * 0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. * This is only present for designs supporting DDR4 devices. * 0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. */ #define DDRC_ZQCTL0_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK) #define DDRC_ZQCTL0_zq_resistor_shared_MASK (0x20000000U) #define DDRC_ZQCTL0_zq_resistor_shared_SHIFT (29U) /*! zq_resistor_shared - ZQ resistor sharing * 0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. * 0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are * sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that * commands to different ranks do not overlap. */ #define DDRC_ZQCTL0_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_zq_resistor_shared_MASK) #define DDRC_ZQCTL0_dis_srx_zqcl_MASK (0x40000000U) #define DDRC_ZQCTL0_dis_srx_zqcl_SHIFT (30U) /*! dis_srx_zqcl - Disable ZQCL/MPC * 0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting * DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. * 0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ #define DDRC_ZQCTL0_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_srx_zqcl_MASK) #define DDRC_ZQCTL0_dis_auto_zq_MASK (0x80000000U) #define DDRC_ZQCTL0_dis_auto_zq_SHIFT (31U) /*! dis_auto_zq - Disable Auto ZQCS/MPC * 0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. * 0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used * instead to issue ZQ calibration request from APB module. */ #define DDRC_ZQCTL0_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_dis_auto_zq_MASK) /*! @} */ /*! @name ZQCTL1 - ZQ Control Register 1 */ /*! @{ */ #define DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU) #define DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U) /*! t_zq_short_interval_x1024 - Average interval to wait between automatically issuing ZQCS (ZQ * calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. * Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 DFI clock cycles. This is only present for designs * supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_ZQCTL1_t_zq_short_interval_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK) #define DDRC_ZQCTL1_t_zq_reset_nop_MASK (0x3FF00000U) #define DDRC_ZQCTL1_t_zq_reset_nop_SHIFT (20U) /*! t_zq_reset_nop - tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ * calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency * ratio mode, program this to tZQReset/2 and round it up to the next integer value. This is only * present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_ZQCTL1_t_zq_reset_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_ZQCTL1_t_zq_reset_nop_MASK) /*! @} */ /*! @name ZQCTL2 - ZQ Control Register 2 */ /*! @{ */ #define DDRC_ZQCTL2_zq_reset_MASK (0x1U) #define DDRC_ZQCTL2_zq_reset_SHIFT (0U) /*! zq_reset - Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset * operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this * signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down * operating modes. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_ZQCTL2_zq_reset(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_zq_reset_SHIFT)) & DDRC_ZQCTL2_zq_reset_MASK) /*! @} */ /*! @name ZQSTAT - ZQ Status Register */ /*! @{ */ #define DDRC_ZQSTAT_zq_reset_busy_MASK (0x1U) #define DDRC_ZQSTAT_zq_reset_busy_SHIFT (0U) /*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This * signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ * Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended * not to perform ZQ Reset commands when this signal is high. * 0b0..Indicates that the SoC core can initiate a ZQ Reset operation * 0b1..Indicates that ZQ Reset operation is in progress */ #define DDRC_ZQSTAT_zq_reset_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_ZQSTAT_zq_reset_busy_MASK) /*! @} */ /*! @name DFITMG0 - DFI Timing Register 0 */ /*! @{ */ #define DDRC_DFITMG0_dfi_tphy_wrlat_MASK (0x3FU) #define DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT (0U) /*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable * (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY * specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be * necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for * the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY * clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr. */ #define DDRC_DFITMG0_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrlat_MASK) #define DDRC_DFITMG0_dfi_tphy_wrdata_MASK (0x3F00U) #define DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT (8U) /*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to * when the associated write data is driven on the dfi_wrdata signal. This corresponds to the * DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max * supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on * DFITMG0.dfi_wrdata_use_sdr. */ #define DDRC_DFITMG0_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrdata_MASK) #define DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK (0x8000U) #define DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT (15U) /*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using * HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat * is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in * DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of * HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification * for correct value. */ #define DDRC_DFITMG0_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK) #define DDRC_DFITMG0_dfi_t_rddata_en_MASK (0x7F0000U) #define DDRC_DFITMG0_dfi_t_rddata_en_SHIFT (16U) /*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the * assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds * to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it * may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to * compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or * DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr. */ #define DDRC_DFITMG0_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_dfi_t_rddata_en_MASK) #define DDRC_DFITMG0_dfi_rddata_use_sdr_MASK (0x800000U) #define DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT (23U) /*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated * using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in * DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI * clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct * value. */ #define DDRC_DFITMG0_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_rddata_use_sdr_MASK) #define DDRC_DFITMG0_dfi_t_ctrl_delay_MASK (0x1F000000U) #define DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT (24U) /*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion * of the DFI control signals that the control signals at the PHY-DRAM interface reflect the * assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing * parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it * is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms * of DFI clock. */ #define DDRC_DFITMG0_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_dfi_t_ctrl_delay_MASK) /*! @} */ /*! @name DFITMG1 - DFI Timing Register 1 */ /*! @{ */ #define DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK (0x1FU) #define DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U) /*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the * dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the * DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not * phase aligned, this timing parameter should be rounded up to the next integer value. */ #define DDRC_DFITMG1_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK) #define DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U) #define DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U) /*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the * dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM * boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, * this timing parameter should be rounded up to the next integer value. */ #define DDRC_DFITMG1_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK) #define DDRC_DFITMG1_dfi_t_wrdata_delay_MASK (0x1F0000U) #define DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT (16U) /*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en * signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. * This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for * correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI * 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be * programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 * and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: * Clocks */ #define DDRC_DFITMG1_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_dfi_t_wrdata_delay_MASK) #define DDRC_DFITMG1_dfi_t_parin_lat_MASK (0x3000000U) #define DDRC_DFITMG1_dfi_t_parin_lat_SHIFT (24U) /*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is * asserted and when the associated dfi_parity_in signal is driven. */ #define DDRC_DFITMG1_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_parin_lat_MASK) #define DDRC_DFITMG1_dfi_t_cmd_lat_MASK (0xF0000000U) #define DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT (28U) /*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is * asserted and when the associated command is driven. This field is used for CAL mode, should be * set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY * can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 */ #define DDRC_DFITMG1_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_cmd_lat_MASK) /*! @} */ /*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */ /*! @{ */ #define DDRC_DFILPCFG0_dfi_lp_en_pd_MASK (0x1U) #define DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT (0U) /*! dfi_lp_en_pd - Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled */ #define DDRC_DFILPCFG0_dfi_lp_en_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_pd_MASK) #define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK (0xF0U) #define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT (4U) /*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down * mode is entered. Determines the DFI's tlp_wakeup time: * 0b0000..16 cycles * 0b0001..32 cycles * 0b0010..64 cycles * 0b0011..128 cycles * 0b0100..256 cycles * 0b0101..512 cycles * 0b0110..1024 cycles * 0b0111..2048 cycles * 0b1000..4096 cycles * 0b1001..8192 cycles * 0b1010..16384 cycles * 0b1011..32768 cycles * 0b1100..65536 cycles * 0b1101..131072 cycles * 0b1110..262144 cycles * 0b1111..Unlimited cycles */ #define DDRC_DFILPCFG0_dfi_lp_wakeup_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK) #define DDRC_DFILPCFG0_dfi_lp_en_sr_MASK (0x100U) #define DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT (8U) /*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled * 0b0..Disabled * 0b1..Enabled */ #define DDRC_DFILPCFG0_dfi_lp_en_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_sr_MASK) #define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK (0xF000U) #define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT (12U) /*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh * mode is entered. Determines the DFI's tlp_wakeup time: * 0b0000..16 cycles * 0b0001..32 cycles * 0b0010..64 cycles * 0b0011..128 cycles * 0b0100..256 cycles * 0b0101..512 cycles * 0b0110..1024 cycles * 0b0111..2048 cycles * 0b1000..4096 cycles * 0b1001..8192 cycles * 0b1010..16384 cycles * 0b1011..32768 cycles * 0b1100..65536 cycles * 0b1101..131072 cycles * 0b1110..262144 cycles * 0b1111..Unlimited cycles */ #define DDRC_DFILPCFG0_dfi_lp_wakeup_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK) #define DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK (0x10000U) #define DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT (16U) /*! dfi_lp_en_dpd - Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - * 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 * devices. */ #define DDRC_DFILPCFG0_dfi_lp_en_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK) #define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK (0xF00000U) #define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT (20U) /*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power * Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs * supporting mDDR or LPDDR2/LPDDR3 devices. * 0b0000..16 cycles * 0b0001..32 cycles * 0b0010..64 cycles * 0b0011..128 cycles * 0b0100..256 cycles * 0b0101..512 cycles * 0b0110..1024 cycles * 0b0111..2048 cycles * 0b1000..4096 cycles * 0b1001..8192 cycles * 0b1010..16384 cycles * 0b1011..32768 cycles * 0b1100..65536 cycles * 0b1101..131072 cycles * 0b1110..262144 cycles * 0b1111..Unlimited cycles */ #define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK) #define DDRC_DFILPCFG0_dfi_tlp_resp_MASK (0x1F000000U) #define DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT (24U) /*! dfi_tlp_resp - Setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both * Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 * specification onwards, recommends using a fixed value of 7 always. */ #define DDRC_DFILPCFG0_dfi_tlp_resp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT)) & DDRC_DFILPCFG0_dfi_tlp_resp_MASK) /*! @} */ /*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */ /*! @{ */ #define DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK (0x1U) #define DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT (0U) /*! dfi_lp_en_mpsm - Enables DFI Low Power interface handshaking during Maximum Power Saving Mode * Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 * devices. */ #define DDRC_DFILPCFG1_dfi_lp_en_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK) #define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK (0xF0U) #define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT (4U) /*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum * Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: * 0b0000..16 cycles * 0b0001..32 cycles * 0b0010..64 cycles * 0b0011..128 cycles * 0b0100..256 cycles * 0b0101..512 cycles * 0b0110..1024 cycles * 0b0111..2048 cycles * 0b1000..4096 cycles * 0b1001..8192 cycles * 0b1010..16384 cycles * 0b1011..32768 cycles * 0b1100..65536 cycles * 0b1101..131072 cycles * 0b1110..262144 cycles * 0b1111..Unlimited cycles */ #define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK) /*! @} */ /*! @name DFIUPD0 - DFI Update Register 0 */ /*! @{ */ #define DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK (0x3FFU) #define DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT (0U) /*! dfi_t_ctrlup_min - Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req * signal must be asserted. The DDRC expects the PHY to respond within this time. If the PHY does * not respond, the DDRC will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest * value to assign to this variable is 0x3. */ #define DDRC_DFIUPD0_dfi_t_ctrlup_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK) #define DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK (0x3FF0000U) #define DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT (16U) /*! dfi_t_ctrlup_max - Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req * signal can assert. Lowest value to assign to this variable is 0x40. */ #define DDRC_DFIUPD0_dfi_t_ctrlup_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK) #define DDRC_DFIUPD0_ctrlupd_pre_srx_MASK (0x20000000U) #define DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT (29U) /*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1 * : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, * because no dfi_ctrlupd_req will be issued when SRX. * 0b0..send ctrlupd after SRX * 0b1..send ctrlupd before SRX */ #define DDRC_DFIUPD0_ctrlupd_pre_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT)) & DDRC_DFIUPD0_ctrlupd_pre_srx_MASK) #define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK (0x40000000U) #define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT (30U) /*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit. * 0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx. */ #define DDRC_DFIUPD0_dis_auto_ctrlupd_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK) #define DDRC_DFIUPD0_dis_auto_ctrlupd_MASK (0x80000000U) #define DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT (31U) /*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC * 0b0..DDRC issues dfi_ctrlupd_req periodically. * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req * signal using register reg_ddrc_ctrlupd. */ #define DDRC_DFIUPD0_dis_auto_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_MASK) /*! @} */ /*! @name DFIUPD1 - DFI Update Register 1 */ /*! @{ */ #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK (0xFFU) #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT (0U) /*! dfi_t_ctrlupd_interval_max_x1024 - This is the maximum amount of time between DDRC initiated DFI * update requests. This timer resets with each update request; when the timer expires * dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this * idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used * to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain * calibration over PVT, but frequent updates may impact performance. Minimum allowed value for * this field is 1. Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be * greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 DFI clock cycles */ #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK) #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK (0xFF0000U) #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT (16U) /*! dfi_t_ctrlupd_interval_min_x1024 - This is the minimum amount of time between DDRC initiated DFI * update requests (which is executed whenever the DDRC is idle). Set this number higher to * reduce the frequency of update requests, which can have a small impact on the latency of the first * read request when the DDRC is idle. Minimum allowed value for this field is 1. Unit: 1024 DFI * clock cycles */ #define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK) /*! @} */ /*! @name DFIUPD2 - DFI Update Register 2 */ /*! @{ */ #define DDRC_DFIUPD2_dfi_phyupd_en_MASK (0x80000000U) #define DDRC_DFIUPD2_dfi_phyupd_en_SHIFT (31U) /*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates: * 0b0..Disabled * 0b1..Enabled */ #define DDRC_DFIUPD2_dfi_phyupd_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD2_dfi_phyupd_en_SHIFT)) & DDRC_DFIUPD2_dfi_phyupd_en_MASK) /*! @} */ /*! @name DFIMISC - DFI Miscellaneous Control Register */ /*! @{ */ #define DDRC_DFIMISC_dfi_init_complete_en_MASK (0x1U) #define DDRC_DFIMISC_dfi_init_complete_en_SHIFT (0U) /*! dfi_init_complete_en - PHY initialization complete enable signal. When asserted the * dfi_init_complete signal can be used to trigger SDRAM initialisation */ #define DDRC_DFIMISC_dfi_init_complete_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_complete_en_SHIFT)) & DDRC_DFIMISC_dfi_init_complete_en_MASK) #define DDRC_DFIMISC_phy_dbi_mode_MASK (0x2U) #define DDRC_DFIMISC_phy_dbi_mode_SHIFT (1U) /*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4. * 0b0..DDRC implements DBI functionality. * 0b1..PHY implements DBI functionality. */ #define DDRC_DFIMISC_phy_dbi_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_phy_dbi_mode_SHIFT)) & DDRC_DFIMISC_phy_dbi_mode_MASK) #define DDRC_DFIMISC_dfi_data_cs_polarity_MASK (0x4U) #define DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT (2U) /*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. * 0b0..Signals are active low * 0b1..Signals are active high */ #define DDRC_DFIMISC_dfi_data_cs_polarity(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT)) & DDRC_DFIMISC_dfi_data_cs_polarity_MASK) #define DDRC_DFIMISC_ctl_idle_en_MASK (0x10U) #define DDRC_DFIMISC_ctl_idle_en_SHIFT (4U) /*! ctl_idle_en - Enables support of ctl_idle signal, which is non-DFI related pin specific to * certain PHYs. See signal description of ctl_idle signal for further details of ctl_idle * functionality. */ #define DDRC_DFIMISC_ctl_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_ctl_idle_en_SHIFT)) & DDRC_DFIMISC_ctl_idle_en_MASK) #define DDRC_DFIMISC_dfi_init_start_MASK (0x20U) #define DDRC_DFIMISC_dfi_init_start_SHIFT (5U) /*! dfi_init_start - PHY init start request signal.When asserted it triggers the PHY init start request */ #define DDRC_DFIMISC_dfi_init_start(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_start_SHIFT)) & DDRC_DFIMISC_dfi_init_start_MASK) #define DDRC_DFIMISC_dfi_frequency_MASK (0x1F00U) #define DDRC_DFIMISC_dfi_frequency_SHIFT (8U) /*! dfi_frequency - Indicates the operating frequency of the system. The number of supported * frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ #define DDRC_DFIMISC_dfi_frequency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_frequency_SHIFT)) & DDRC_DFIMISC_dfi_frequency_MASK) /*! @} */ /*! @name DFITMG2 - DFI Timing Register 2 */ /*! @{ */ #define DDRC_DFITMG2_dfi_tphy_wrcslat_MASK (0x3FU) #define DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT (0U) /*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the * DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds * to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. */ #define DDRC_DFITMG2_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_wrcslat_MASK) #define DDRC_DFITMG2_dfi_tphy_rdcslat_MASK (0x7F00U) #define DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT (8U) /*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI * control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds * to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. */ #define DDRC_DFITMG2_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_rdcslat_MASK) /*! @} */ /*! @name DFITMG3 - DFI Timing Register 3 */ /*! @{ */ #define DDRC_DFITMG3_dfi_t_geardown_delay_MASK (0x1FU) #define DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT (0U) /*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being * ready to receive commands. Refer to PHY specification for correct value. When the controller is * operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to * the next integer value. Unit: Clocks */ #define DDRC_DFITMG3_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_dfi_t_geardown_delay_MASK) /*! @} */ /*! @name DFISTAT - DFI Status Register */ /*! @{ */ #define DDRC_DFISTAT_dfi_init_complete_MASK (0x1U) #define DDRC_DFISTAT_dfi_init_complete_SHIFT (0U) /*! dfi_init_complete - The status flag register which announces when the DFI initialization has * been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete * flag is polled to know when the initialization is done. */ #define DDRC_DFISTAT_dfi_init_complete(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_init_complete_SHIFT)) & DDRC_DFISTAT_dfi_init_complete_MASK) #define DDRC_DFISTAT_dfi_lp_ack_MASK (0x2U) #define DDRC_DFISTAT_dfi_lp_ack_SHIFT (1U) /*! dfi_lp_ack - Stores the value of the dfi_lp_ack input to the controller. */ #define DDRC_DFISTAT_dfi_lp_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_lp_ack_SHIFT)) & DDRC_DFISTAT_dfi_lp_ack_MASK) /*! @} */ /*! @name DBICTL - DM/DBI Control Register */ /*! @{ */ #define DDRC_DBICTL_dm_en_MASK (0x1U) #define DDRC_DBICTL_dm_en_SHIFT (0U) /*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode * register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal * must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity * from this signal * 0b0..DM is disabled * 0b1..DM is enabled */ #define DDRC_DBICTL_dm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_dm_en_SHIFT)) & DDRC_DBICTL_dm_en_MASK) #define DDRC_DBICTL_wr_dbi_en_MASK (0x2U) #define DDRC_DBICTL_wr_dbi_en_SHIFT (1U) /*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11. * When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] * 0b0..Write DBI is disabled * 0b1..Write DBI is enabled. */ #define DDRC_DBICTL_wr_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_wr_dbi_en_SHIFT)) & DDRC_DBICTL_wr_dbi_en_MASK) #define DDRC_DBICTL_rd_dbi_en_MASK (0x4U) #define DDRC_DBICTL_rd_dbi_en_SHIFT (2U) /*! rd_dbi_en - Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is * enabled. This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A12. When * x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6] */ #define DDRC_DBICTL_rd_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_rd_dbi_en_SHIFT)) & DDRC_DBICTL_rd_dbi_en_MASK) /*! @} */ /*! @name ADDRMAP0 - Address Map Register 0 */ /*! @{ */ #define DDRC_ADDRMAP0_addrmap_cs_bit0_MASK (0x1FU) #define DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT (0U) /*! addrmap_cs_bit0 - Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 28, * and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base * to the value of this field. If set to 31, rank address bit 0 is set to 0. */ #define DDRC_ADDRMAP0_addrmap_cs_bit0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT)) & DDRC_ADDRMAP0_addrmap_cs_bit0_MASK) /*! @} */ /*! @name ADDRMAP1 - Address Map Register 1 */ /*! @{ */ #define DDRC_ADDRMAP1_addrmap_bank_b0_MASK (0x1FU) #define DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT (0U) /*! addrmap_bank_b0 - Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 31 * Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined * by adding the internal base to the value of this field. */ #define DDRC_ADDRMAP1_addrmap_bank_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b0_MASK) #define DDRC_ADDRMAP1_addrmap_bank_b1_MASK (0x1F00U) #define DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT (8U) /*! addrmap_bank_b1 - Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 31 * Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined * by adding the internal base to the value of this field. */ #define DDRC_ADDRMAP1_addrmap_bank_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b1_MASK) #define DDRC_ADDRMAP1_addrmap_bank_b2_MASK (0x1F0000U) #define DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT (16U) /*! addrmap_bank_b2 - Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 30 * and 31 Internal Base: 4 The selected HIF address bit is determined by adding the internal base * to the value of this field. If set to 31, bank address bit 2 is set to 0. */ #define DDRC_ADDRMAP1_addrmap_bank_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b2_MASK) /*! @} */ /*! @name ADDRMAP2 - Address Map Register 2 */ /*! @{ */ #define DDRC_ADDRMAP2_addrmap_col_b2_MASK (0xFU) #define DDRC_ADDRMAP2_addrmap_col_b2_SHIFT (0U) /*! addrmap_col_b2 - - Full bus width mode: Selects the HIF address bit used as column address bit * 2. - Half bus width mode: Selects the HIF address bit used as column address bit 3. - Quarter * bus width mode: Selects the HIF address bit used as column address bit 4. Valid Range: 0 to 7 * Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the * value of this field. Note, if DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to * program this to 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - * PCCFG.bl_exp_mode==1 and either - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 or - In LPDDR4 and * ADDRMAP1.addrmap_bank_b0==0 If DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to * 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1 * and - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus * Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to * column address bit 2. If MEMC_BURST_LENGTH=16 and Full Bus Width (MSTR.data_bus_width==00), it * is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If * MEMC_BURST_LENGTH=16 and Half Bus Width (MSTR.data_bus_width==01), it is recommended to program this to 0 * so that HIF[2] maps to column address bit 3. */ #define DDRC_ADDRMAP2_addrmap_col_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b2_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b2_MASK) #define DDRC_ADDRMAP2_addrmap_col_b3_MASK (0xF00U) #define DDRC_ADDRMAP2_addrmap_col_b3_SHIFT (8U) /*! addrmap_col_b3 - - Full bus width mode: Selects the HIF address bit used as column address bit * 3. - Half bus width mode: Selects the HIF address bit used as column address bit 4. - Quarter * bus width mode: Selects the HIF address bit used as column address bit 5. Valid Range: 0 to 7 * Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the * value of this field. Note, if DDRC_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width * (MSTR.data_bus_width=00) and BL16 (MSTR.burst_rdwr=1000), it is recommended to program this to 0. */ #define DDRC_ADDRMAP2_addrmap_col_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b3_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b3_MASK) #define DDRC_ADDRMAP2_addrmap_col_b4_MASK (0xF0000U) #define DDRC_ADDRMAP2_addrmap_col_b4_SHIFT (16U) /*! addrmap_col_b4 - - Full bus width mode: Selects the HIF address bit used as column address bit * 4. - Half bus width mode: Selects the HIF address bit used as column address bit 5. - Quarter * bus width mode: Selects the HIF address bit used as column address bit 6. Valid Range: 0 to 7, * and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base * to the value of this field. If set to 15, this column address bit is set to 0. */ #define DDRC_ADDRMAP2_addrmap_col_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b4_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b4_MASK) #define DDRC_ADDRMAP2_addrmap_col_b5_MASK (0xF000000U) #define DDRC_ADDRMAP2_addrmap_col_b5_SHIFT (24U) /*! addrmap_col_b5 - - Full bus width mode: Selects the HIF address bit used as column address bit * 5. - Half bus width mode: Selects the HIF address bit used as column address bit 6. - Quarter * bus width mode: Selects the HIF address bit used as column address bit 7 . Valid Range: 0 to 7, * and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal * base to the value of this field. If set to 15, this column address bit is set to 0. */ #define DDRC_ADDRMAP2_addrmap_col_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b5_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b5_MASK) /*! @} */ /*! @name ADDRMAP3 - Address Map Register 3 */ /*! @{ */ #define DDRC_ADDRMAP3_addrmap_col_b6_MASK (0xFU) #define DDRC_ADDRMAP3_addrmap_col_b6_SHIFT (0U) /*! addrmap_col_b6 - - Full bus width mode: Selects the HIF address bit used as column address bit * 6. - Half bus width mode: Selects the HIF address bit used as column address bit 7. - Quarter * bus width mode: Selects the HIF address bit used as column address bit 8. Valid Range: 0 to 7, * and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base * to the value of this field. If set to 15, this column address bit is set to 0. */ #define DDRC_ADDRMAP3_addrmap_col_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b6_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b6_MASK) #define DDRC_ADDRMAP3_addrmap_col_b7_MASK (0xF00U) #define DDRC_ADDRMAP3_addrmap_col_b7_SHIFT (8U) /*! addrmap_col_b7 - - Full bus width mode: Selects the HIF address bit used as column address bit * 7. - Half bus width mode: Selects the HIF address bit used as column address bit 8. - Quarter * bus width mode: Selects the HIF address bit used as column address bit 9. Valid Range: 0 to 7, * and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base * to the value of this field. If set to 15, this column address bit is set to 0. */ #define DDRC_ADDRMAP3_addrmap_col_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b7_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b7_MASK) #define DDRC_ADDRMAP3_addrmap_col_b8_MASK (0xF0000U) #define DDRC_ADDRMAP3_addrmap_col_b8_SHIFT (16U) /*! addrmap_col_b8 - - Full bus width mode: Selects the HIF address bit used as column address bit * 8. - Half bus width mode: Selects the HIF address bit used as column address bit 9. - Quarter * bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 * mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined * by adding the internal base to the value of this field. If set to 15, this column address bit * is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for * indicating auto-precharge, and hence no source address bit can be mapped to column address * bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence * column bit 10 is used. */ #define DDRC_ADDRMAP3_addrmap_col_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b8_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b8_MASK) #define DDRC_ADDRMAP3_addrmap_col_b9_MASK (0xF000000U) #define DDRC_ADDRMAP3_addrmap_col_b9_SHIFT (24U) /*! addrmap_col_b9 - - Full bus width mode: Selects the HIF address bit used as column address bit * 9. - Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in * LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as column address * bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected * HIF address bit is determined by adding the internal base to the value of this field. If set to * 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column * address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be * mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for * auto-precharge in the CA bus and hence column bit 10 is used. */ #define DDRC_ADDRMAP3_addrmap_col_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b9_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b9_MASK) /*! @} */ /*! @name ADDRMAP4 - Address Map Register 4 */ /*! @{ */ #define DDRC_ADDRMAP4_addrmap_col_b10_MASK (0xFU) #define DDRC_ADDRMAP4_addrmap_col_b10_SHIFT (0U) /*! addrmap_col_b10 - - Full bus width mode: Selects the HIF address bit used as column address bit * 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the HIF address bit used as * column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. To make it * unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF * address bit is determined by adding the internal base to the value of this field. If set to * 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column * address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be * mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge * in the CA bus and hence column bit 10 is used. */ #define DDRC_ADDRMAP4_addrmap_col_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b10_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b10_MASK) #define DDRC_ADDRMAP4_addrmap_col_b11_MASK (0xF00U) #define DDRC_ADDRMAP4_addrmap_col_b11_SHIFT (8U) /*! addrmap_col_b11 - - Full bus width mode: Selects the HIF address bit used as column address bit * 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To make it unused, this should * be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must be tied to * 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by * adding the internal base to the value of this field. If set to 15, this column address bit is * set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for * indicating auto-precharge, and hence no source address bit can be mapped to column address bit * 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column * bit 10 is used. */ #define DDRC_ADDRMAP4_addrmap_col_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b11_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b11_MASK) /*! @} */ /*! @name ADDRMAP5 - Address Map Register 5 */ /*! @{ */ #define DDRC_ADDRMAP5_addrmap_row_b0_MASK (0xFU) #define DDRC_ADDRMAP5_addrmap_row_b0_SHIFT (0U) /*! addrmap_row_b0 - Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 * Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by * adding the internal base to the value of this field. */ #define DDRC_ADDRMAP5_addrmap_row_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b0_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b0_MASK) #define DDRC_ADDRMAP5_addrmap_row_b1_MASK (0xF00U) #define DDRC_ADDRMAP5_addrmap_row_b1_SHIFT (8U) /*! addrmap_row_b1 - Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 * Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by * adding the internal base to the value of this field. */ #define DDRC_ADDRMAP5_addrmap_row_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b1_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b1_MASK) #define DDRC_ADDRMAP5_addrmap_row_b2_10_MASK (0xF0000U) #define DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT (16U) /*! addrmap_row_b2_10 - Selects the HIF address bits used as row address bits 2 to 10. Valid Range: * 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for * row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF address bit * for each of the row address bits is determined by adding the internal base to the value of this * field. When value 15 is used the values of row address bits 2 to 10 are defined by registers * ADDRMAP9, ADDRMAP10, ADDRMAP11. */ #define DDRC_ADDRMAP5_addrmap_row_b2_10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b2_10_MASK) #define DDRC_ADDRMAP5_addrmap_row_b11_MASK (0xF000000U) #define DDRC_ADDRMAP5_addrmap_row_b11_SHIFT (24U) /*! addrmap_row_b11 - Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, * and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal * base to the value of this field. If set to 15, row address bit 11 is set to 0. */ #define DDRC_ADDRMAP5_addrmap_row_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b11_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b11_MASK) /*! @} */ /*! @name ADDRMAP6 - Address Map Register 6 */ /*! @{ */ #define DDRC_ADDRMAP6_addrmap_row_b12_MASK (0xFU) #define DDRC_ADDRMAP6_addrmap_row_b12_SHIFT (0U) /*! addrmap_row_b12 - Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, * and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal * base to the value of this field. If set to 15, row address bit 12 is set to 0. */ #define DDRC_ADDRMAP6_addrmap_row_b12(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b12_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b12_MASK) #define DDRC_ADDRMAP6_addrmap_row_b13_MASK (0xF00U) #define DDRC_ADDRMAP6_addrmap_row_b13_SHIFT (8U) /*! addrmap_row_b13 - Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, * and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal * base to the value of this field. If set to 15, row address bit 13 is set to 0. */ #define DDRC_ADDRMAP6_addrmap_row_b13(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b13_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b13_MASK) #define DDRC_ADDRMAP6_addrmap_row_b14_MASK (0xF0000U) #define DDRC_ADDRMAP6_addrmap_row_b14_SHIFT (16U) /*! addrmap_row_b14 - Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, * and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal * base to the value of this field. If set to 15, row address bit 14 is set to 0. */ #define DDRC_ADDRMAP6_addrmap_row_b14(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b14_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b14_MASK) #define DDRC_ADDRMAP6_addrmap_row_b15_MASK (0xF000000U) #define DDRC_ADDRMAP6_addrmap_row_b15_SHIFT (24U) /*! addrmap_row_b15 - Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, * and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal * base to the value of this field. If set to 15, row address bit 15 is set to 0. */ #define DDRC_ADDRMAP6_addrmap_row_b15(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b15_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b15_MASK) #define DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK (0x80000000U) #define DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT (31U) /*! lpddr3_6gb_12gb - Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - * LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as * invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present only in designs * configured to support LPDDR3. */ #define DDRC_ADDRMAP6_lpddr3_6gb_12gb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT)) & DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK) /*! @} */ /*! @name ADDRMAP7 - Address Map Register 7 */ /*! @{ */ #define DDRC_ADDRMAP7_addrmap_row_b16_MASK (0xFU) #define DDRC_ADDRMAP7_addrmap_row_b16_SHIFT (0U) /*! addrmap_row_b16 - Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, * and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal * base to the value of this field. If set to 15, row address bit 16 is set to 0. */ #define DDRC_ADDRMAP7_addrmap_row_b16(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b16_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b16_MASK) #define DDRC_ADDRMAP7_addrmap_row_b17_MASK (0xF00U) #define DDRC_ADDRMAP7_addrmap_row_b17_SHIFT (8U) /*! addrmap_row_b17 - Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11, * and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal * base to the value of this field. If set to 15, row address bit 17 is set to 0. */ #define DDRC_ADDRMAP7_addrmap_row_b17(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b17_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b17_MASK) /*! @} */ /*! @name ADDRMAP8 - Address Map Register 8 */ /*! @{ */ #define DDRC_ADDRMAP8_addrmap_bg_b0_MASK (0x1FU) #define DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT (0U) /*! addrmap_bg_b0 - Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to * 31 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is * determined by adding the internal base to the value of this field. */ #define DDRC_ADDRMAP8_addrmap_bg_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b0_MASK) #define DDRC_ADDRMAP8_addrmap_bg_b1_MASK (0x3F00U) #define DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT (8U) /*! addrmap_bg_b1 - Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to * 31, and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address * bits is determined by adding the internal base to the value of this field. If set to 63, bank * group address bit 1 is set to 0. */ #define DDRC_ADDRMAP8_addrmap_bg_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b1_MASK) /*! @} */ /*! @name ADDRMAP9 - Address Map Register 9 */ /*! @{ */ #define DDRC_ADDRMAP9_addrmap_row_b2_MASK (0xFU) #define DDRC_ADDRMAP9_addrmap_row_b2_SHIFT (0U) /*! addrmap_row_b2 - Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 * Internal Base: 8 The selected HIF address bit for each of the row address bits is determined by * adding the internal base to the value of this field. This register field is used only when * ADDRMAP5.addrmap_row_b2_10 is set to value 15. */ #define DDRC_ADDRMAP9_addrmap_row_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b2_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b2_MASK) #define DDRC_ADDRMAP9_addrmap_row_b3_MASK (0xF00U) #define DDRC_ADDRMAP9_addrmap_row_b3_SHIFT (8U) /*! addrmap_row_b3 - Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 * Internal Base: 9 The selected HIF address bit for each of the row address bits is determined by * adding the internal base to the value of this field. This register field is used only when * ADDRMAP5.addrmap_row_b2_10 is set to value 15. */ #define DDRC_ADDRMAP9_addrmap_row_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b3_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b3_MASK) #define DDRC_ADDRMAP9_addrmap_row_b4_MASK (0xF0000U) #define DDRC_ADDRMAP9_addrmap_row_b4_SHIFT (16U) /*! addrmap_row_b4 - Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 * Internal Base: 10 The selected HIF address bit for each of the row address bits is determined by * adding the internal base to the value of this field. This register field is used only when * ADDRMAP5.addrmap_row_b2_10 is set to value 15. */ #define DDRC_ADDRMAP9_addrmap_row_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b4_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b4_MASK) #define DDRC_ADDRMAP9_addrmap_row_b5_MASK (0xF000000U) #define DDRC_ADDRMAP9_addrmap_row_b5_SHIFT (24U) /*! addrmap_row_b5 - Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 * Internal Base: 11 The selected HIF address bit for each of the row address bits is determined by * adding the internal base to the value of this field. This register field is used only when * ADDRMAP5.addrmap_row_b2_10 is set to value 15. */ #define DDRC_ADDRMAP9_addrmap_row_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b5_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b5_MASK) /*! @} */ /*! @name ADDRMAP10 - Address Map Register 10 */ /*! @{ */ #define DDRC_ADDRMAP10_addrmap_row_b6_MASK (0xFU) #define DDRC_ADDRMAP10_addrmap_row_b6_SHIFT (0U) /*! addrmap_row_b6 - Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 * Internal Base: 12 The selected HIF address bit for each of the row address bits is determined by * adding the internal base to the value of this field. This register field is used only when * ADDRMAP5.addrmap_row_b2_10 is set to value 15. */ #define DDRC_ADDRMAP10_addrmap_row_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b6_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b6_MASK) #define DDRC_ADDRMAP10_addrmap_row_b7_MASK (0xF00U) #define DDRC_ADDRMAP10_addrmap_row_b7_SHIFT (8U) /*! addrmap_row_b7 - Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 * Internal Base: 13 The selected HIF address bit for each of the row address bits is determined by * adding the internal base to the value of this field. This register field is used only when * ADDRMAP5.addrmap_row_b2_10 is set to value 15. */ #define DDRC_ADDRMAP10_addrmap_row_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b7_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b7_MASK) #define DDRC_ADDRMAP10_addrmap_row_b8_MASK (0xF0000U) #define DDRC_ADDRMAP10_addrmap_row_b8_SHIFT (16U) /*! addrmap_row_b8 - Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 * Internal Base: 14 The selected HIF address bit for each of the row address bits is determined by * adding the internal base to the value of this field. This register field is used only when * ADDRMAP5.addrmap_row_b2_10 is set to value 15. */ #define DDRC_ADDRMAP10_addrmap_row_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b8_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b8_MASK) #define DDRC_ADDRMAP10_addrmap_row_b9_MASK (0xF000000U) #define DDRC_ADDRMAP10_addrmap_row_b9_SHIFT (24U) /*! addrmap_row_b9 - Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 * Internal Base: 15 The selected HIF address bit for each of the row address bits is determined by * adding the internal base to the value of this field. This register field is used only when * ADDRMAP5.addrmap_row_b2_10 is set to value 15. */ #define DDRC_ADDRMAP10_addrmap_row_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b9_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b9_MASK) /*! @} */ /*! @name ADDRMAP11 - Address Map Register 11 */ /*! @{ */ #define DDRC_ADDRMAP11_addrmap_row_b10_MASK (0xFU) #define DDRC_ADDRMAP11_addrmap_row_b10_SHIFT (0U) /*! addrmap_row_b10 - Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 * Internal Base: 16 The selected HIF address bit for each of the row address bits is determined * by adding the internal base to the value of this field. This register field is used only when * ADDRMAP5.addrmap_row_b2_10 is set to value 15. */ #define DDRC_ADDRMAP11_addrmap_row_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP11_addrmap_row_b10_SHIFT)) & DDRC_ADDRMAP11_addrmap_row_b10_MASK) /*! @} */ /*! @name ODTCFG - ODT Configuration Register */ /*! @{ */ #define DDRC_ODTCFG_rd_odt_delay_MASK (0x7CU) #define DDRC_ODTCFG_rd_odt_delay_SHIFT (2U) /*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT * values associated with that command. ODT setting must remain constant for the entire time that * DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 * (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL - * CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL * mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write * preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does * not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) */ #define DDRC_ODTCFG_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_rd_odt_delay_MASK) #define DDRC_ODTCFG_rd_odt_hold_MASK (0xF00U) #define DDRC_ODTCFG_rd_odt_hold_SHIFT (8U) /*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value * is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not * DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK * write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - * RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK) */ #define DDRC_ODTCFG_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_rd_odt_hold_MASK) #define DDRC_ODTCFG_wr_odt_delay_MASK (0x1F0000U) #define DDRC_ODTCFG_wr_odt_delay_SHIFT (16U) /*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT * values associated with that command. ODT setting must remain constant for the entire time that * DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + * AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT * for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: * - WL - 1 - RU(tODTon(max)/tCK)) */ #define DDRC_ODTCFG_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_wr_odt_delay_MASK) #define DDRC_ODTCFG_wr_odt_hold_MASK (0xF000000U) #define DDRC_ODTCFG_wr_odt_hold_SHIFT (24U) /*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value * is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) * - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: * 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) * CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) */ #define DDRC_ODTCFG_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_wr_odt_hold_MASK) /*! @} */ /*! @name ODTMAP - ODT/Rank Map Register */ /*! @{ */ #define DDRC_ODTMAP_rank0_wr_odt_MASK (0x3U) #define DDRC_ODTMAP_rank0_wr_odt_SHIFT (0U) /*! rank0_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 0. Each rank * has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each * rank, set its bit to 1 to enable its ODT. */ #define DDRC_ODTMAP_rank0_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_wr_odt_SHIFT)) & DDRC_ODTMAP_rank0_wr_odt_MASK) #define DDRC_ODTMAP_rank0_rd_odt_MASK (0x30U) #define DDRC_ODTMAP_rank0_rd_odt_SHIFT (4U) /*! rank0_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 0. Each * rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each * rank, set its bit to 1 to enable its ODT. */ #define DDRC_ODTMAP_rank0_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_rd_odt_SHIFT)) & DDRC_ODTMAP_rank0_rd_odt_MASK) #define DDRC_ODTMAP_rank1_wr_odt_MASK (0x300U) #define DDRC_ODTMAP_rank1_wr_odt_SHIFT (8U) /*! rank1_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 1. Each rank * has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each * rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks */ #define DDRC_ODTMAP_rank1_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_wr_odt_SHIFT)) & DDRC_ODTMAP_rank1_wr_odt_MASK) #define DDRC_ODTMAP_rank1_rd_odt_MASK (0x3000U) #define DDRC_ODTMAP_rank1_rd_odt_SHIFT (12U) /*! rank1_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 1. Each * rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each * rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more * ranks */ #define DDRC_ODTMAP_rank1_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_rd_odt_SHIFT)) & DDRC_ODTMAP_rank1_rd_odt_MASK) /*! @} */ /*! @name SCHED - Scheduler Control Register */ /*! @{ */ #define DDRC_SCHED_force_low_pri_n_MASK (0x1U) #define DDRC_SCHED_force_low_pri_n_SHIFT (0U) /*! force_low_pri_n - Active low signal. When asserted ('0'), all incoming transactions are forced * to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read * commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all * Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. * Forcing the incoming transactions to low priority implicitly turns off Bypass path for read * commands. FOR PERFORMANCE ONLY. */ #define DDRC_SCHED_force_low_pri_n(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_force_low_pri_n_SHIFT)) & DDRC_SCHED_force_low_pri_n_MASK) #define DDRC_SCHED_prefer_write_MASK (0x2U) #define DDRC_SCHED_prefer_write_SHIFT (1U) /*! prefer_write - If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. */ #define DDRC_SCHED_prefer_write(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_prefer_write_SHIFT)) & DDRC_SCHED_prefer_write_MASK) #define DDRC_SCHED_pageclose_MASK (0x4U) #define DDRC_SCHED_pageclose_SHIFT (2U) /*! pageclose - If true, bank is kept open only while there are page hit transactions available in * the CAM to that bank. The last read or write command in the CAM with a bank and page hit will * be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and * SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued * in some cases where there is a mode switch between Write and Read or between LPR and HPR. The * Read and Write commands that are executed as part of the ECC scrub requests are also executed * without auto-precharge. If false, the bank remains open until there is a need to close it (to * open a different page, or for page timeout or refresh timeout) - also known as open page * policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF * interface (hif_cmd_autopre). The pageclose feature provids a midway between Open and Close page * policies. FOR PERFORMANCE ONLY. */ #define DDRC_SCHED_pageclose(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_pageclose_SHIFT)) & DDRC_SCHED_pageclose_MASK) #define DDRC_SCHED_lpr_num_entries_MASK (0x1F00U) #define DDRC_SCHED_lpr_num_entries_SHIFT (8U) /*! lpr_num_entries - Number of entries in the low priority transaction store is this value + 1. * (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high * priority transaction store. Setting this to maximum value allocates all entries to low * priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and * the rest to high priority transaction store. Note: In ECC configurations, the numbers of * write and low priority read credits issued is one less than in the non-ECC case. One entry each is * reserved in the write and low-priority read CAMs for storing the RMW requests arising out of * single bit error correction RMW operation. */ #define DDRC_SCHED_lpr_num_entries(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_lpr_num_entries_SHIFT)) & DDRC_SCHED_lpr_num_entries_MASK) #define DDRC_SCHED_go2critical_hysteresis_MASK (0xFF0000U) #define DDRC_SCHED_go2critical_hysteresis_SHIFT (16U) /*! go2critical_hysteresis - UNUSED */ #define DDRC_SCHED_go2critical_hysteresis(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_go2critical_hysteresis_SHIFT)) & DDRC_SCHED_go2critical_hysteresis_MASK) #define DDRC_SCHED_rdwr_idle_gap_MASK (0x7F000000U) #define DDRC_SCHED_rdwr_idle_gap_SHIFT (24U) /*! rdwr_idle_gap - When the preferred transaction store is empty for these many clock cycles, * switch to the alternate transaction store if it is non-empty. The read transaction store (both high * and low priority) is the default preferred transaction store and the write transaction store * is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal * value for this register. When set to 0x0, the transaction store switching will happen * immediately when the switching conditions become true. FOR PERFORMANCE ONLY */ #define DDRC_SCHED_rdwr_idle_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_rdwr_idle_gap_SHIFT)) & DDRC_SCHED_rdwr_idle_gap_MASK) /*! @} */ /*! @name SCHED1 - Scheduler Control Register 1 */ /*! @{ */ #define DDRC_SCHED1_pageclose_timer_MASK (0xFFU) #define DDRC_SCHED1_pageclose_timer_SHIFT (0U) /*! pageclose_timer - This field works in conjunction with SCHED.pageclose. It only has meaning if * SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be * scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes * an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for * details of when this may happen. If SCHED.pageclose==1 and pageclose_timer>0, then an * auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. * Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per * bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page * hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a * page hit. Once the timer has reached zero, an explcit precharge will be attempted to be * scheduled. */ #define DDRC_SCHED1_pageclose_timer(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED1_pageclose_timer_SHIFT)) & DDRC_SCHED1_pageclose_timer_MASK) /*! @} */ /*! @name PERFHPR1 - High Priority Read CAM Register 1 */ /*! @{ */ #define DDRC_PERFHPR1_hpr_max_starve_MASK (0xFFFFU) #define DDRC_PERFHPR1_hpr_max_starve_SHIFT (0U) /*! hpr_max_starve - Number of DFI clocks that the HPR queue can be starved before it goes critical. * The minimum valid functional value for this register is 0x1. Programming it to 0x0 will * disable the starvation functionality; during normal operation, this function should not be disabled * as it will cause excessive latencies. FOR PERFORMANCE ONLY. */ #define DDRC_PERFHPR1_hpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_max_starve_SHIFT)) & DDRC_PERFHPR1_hpr_max_starve_MASK) #define DDRC_PERFHPR1_hpr_xact_run_length_MASK (0xFF000000U) #define DDRC_PERFHPR1_hpr_xact_run_length_SHIFT (24U) /*! hpr_xact_run_length - Number of transactions that are serviced once the HPR queue goes critical * is the smaller of: - (a) This number - (b) Number of transactions available. Unit: * Transaction. FOR PERFORMANCE ONLY. */ #define DDRC_PERFHPR1_hpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_xact_run_length_SHIFT)) & DDRC_PERFHPR1_hpr_xact_run_length_MASK) /*! @} */ /*! @name PERFLPR1 - Low Priority Read CAM Register 1 */ /*! @{ */ #define DDRC_PERFLPR1_lpr_max_starve_MASK (0xFFFFU) #define DDRC_PERFLPR1_lpr_max_starve_SHIFT (0U) /*! lpr_max_starve - Number of DFI clocks that the LPR queue can be starved before it goes critical. * The minimum valid functional value for this register is 0x1. Programming it to 0x0 will * disable the starvation functionality; during normal operation, this function should not be disabled * as it will cause excessive latencies. FOR PERFORMANCE ONLY. */ #define DDRC_PERFLPR1_lpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_max_starve_SHIFT)) & DDRC_PERFLPR1_lpr_max_starve_MASK) #define DDRC_PERFLPR1_lpr_xact_run_length_MASK (0xFF000000U) #define DDRC_PERFLPR1_lpr_xact_run_length_SHIFT (24U) /*! lpr_xact_run_length - Number of transactions that are serviced once the LPR queue goes critical * is the smaller of: - (a) This number - (b) Number of transactions available. Unit: * Transaction. FOR PERFORMANCE ONLY. */ #define DDRC_PERFLPR1_lpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_xact_run_length_SHIFT)) & DDRC_PERFLPR1_lpr_xact_run_length_MASK) /*! @} */ /*! @name PERFWR1 - Write CAM Register 1 */ /*! @{ */ #define DDRC_PERFWR1_w_max_starve_MASK (0xFFFFU) #define DDRC_PERFWR1_w_max_starve_SHIFT (0U) /*! w_max_starve - Number of DFI clocks that the WR queue can be starved before it goes critical. * The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable * the starvation functionality; during normal operation, this function should not be disabled as * it will cause excessive latencies. FOR PERFORMANCE ONLY. */ #define DDRC_PERFWR1_w_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_max_starve_SHIFT)) & DDRC_PERFWR1_w_max_starve_MASK) #define DDRC_PERFWR1_w_xact_run_length_MASK (0xFF000000U) #define DDRC_PERFWR1_w_xact_run_length_SHIFT (24U) /*! w_xact_run_length - Number of transactions that are serviced once the WR queue goes critical is * the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction. * FOR PERFORMANCE ONLY. */ #define DDRC_PERFWR1_w_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_xact_run_length_SHIFT)) & DDRC_PERFWR1_w_xact_run_length_MASK) /*! @} */ /*! @name DBG0 - Debug Register 0 */ /*! @{ */ #define DDRC_DBG0_dis_wc_MASK (0x1U) #define DDRC_DBG0_dis_wc_SHIFT (0U) /*! dis_wc - When 1, disable write combine. FOR DEBUG ONLY */ #define DDRC_DBG0_dis_wc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_wc_SHIFT)) & DDRC_DBG0_dis_wc_MASK) #define DDRC_DBG0_dis_rd_bypass_MASK (0x2U) #define DDRC_DBG0_dis_rd_bypass_SHIFT (1U) /*! dis_rd_bypass - Only present in designs supporting read bypass. When 1, disable bypass path for * high priority read page hits FOR DEBUG ONLY. */ #define DDRC_DBG0_dis_rd_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_rd_bypass_SHIFT)) & DDRC_DBG0_dis_rd_bypass_MASK) #define DDRC_DBG0_dis_act_bypass_MASK (0x4U) #define DDRC_DBG0_dis_act_bypass_SHIFT (2U) /*! dis_act_bypass - Only present in designs supporting activate bypass. When 1, disable bypass path * for high priority read activates FOR DEBUG ONLY. */ #define DDRC_DBG0_dis_act_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_act_bypass_SHIFT)) & DDRC_DBG0_dis_act_bypass_MASK) #define DDRC_DBG0_dis_collision_page_opt_MASK (0x10U) #define DDRC_DBG0_dis_collision_page_opt_SHIFT (4U) /*! dis_collision_page_opt - When this is set to '0', auto-precharge is disabled for the flushed * command in a collision case. Collision cases are write followed by read to same address, read * followed by write to same address, or write followed by write to same address with DBG0.dis_wc * bit = 1 (where same address comparisons exclude the two address bits representing critical * word). FOR DEBUG ONLY. */ #define DDRC_DBG0_dis_collision_page_opt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_collision_page_opt_SHIFT)) & DDRC_DBG0_dis_collision_page_opt_MASK) /*! @} */ /*! @name DBG1 - Debug Register 1 */ /*! @{ */ #define DDRC_DBG1_dis_dq_MASK (0x1U) #define DDRC_DBG1_dis_dq_SHIFT (0U) /*! dis_dq - When 1, DDRC will not de-queue any transactions from the CAM. Bypass is also disabled. * All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this * is asserted. This bit may be used to prevent reads or writes being issued by the DDRC, which * makes it safe to modify certain register fields associated with reads and writes (see User * Guide for details). After setting this bit, it is strongly recommended to poll * DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which * affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. This bit * is intended to be switched on-the-fly. */ #define DDRC_DBG1_dis_dq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_dq_SHIFT)) & DDRC_DBG1_dis_dq_MASK) #define DDRC_DBG1_dis_hif_MASK (0x2U) #define DDRC_DBG1_dis_hif_SHIFT (1U) /*! dis_hif - When 1, DDRC asserts the HIF command signal hif_cmd_stall. DDRC will ignore the * hif_cmd_valid and all other associated request signals. This bit is intended to be switched * on-the-fly. */ #define DDRC_DBG1_dis_hif(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_hif_SHIFT)) & DDRC_DBG1_dis_hif_MASK) /*! @} */ /*! @name DBGCAM - CAM Debug Register */ /*! @{ */ #define DDRC_DBGCAM_dbg_hpr_q_depth_MASK (0x3FU) #define DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT (0U) /*! dbg_hpr_q_depth - High priority read queue depth FOR DEBUG ONLY */ #define DDRC_DBGCAM_dbg_hpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_hpr_q_depth_MASK) #define DDRC_DBGCAM_dbg_lpr_q_depth_MASK (0x3F00U) #define DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT (8U) /*! dbg_lpr_q_depth - Low priority read queue depth The last entry of Lpr queue is reserved for ECC * SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG * ONLY */ #define DDRC_DBGCAM_dbg_lpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_lpr_q_depth_MASK) #define DDRC_DBGCAM_dbg_w_q_depth_MASK (0x3F0000U) #define DDRC_DBGCAM_dbg_w_q_depth_SHIFT (16U) /*! dbg_w_q_depth - Write queue depth The last entry of WR queue is reserved for ECC SCRUB * operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY */ #define DDRC_DBGCAM_dbg_w_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_w_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_w_q_depth_MASK) #define DDRC_DBGCAM_dbg_stall_MASK (0x1000000U) #define DDRC_DBGCAM_dbg_stall_SHIFT (24U) /*! dbg_stall - Stall FOR DEBUG ONLY */ #define DDRC_DBGCAM_dbg_stall(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_SHIFT)) & DDRC_DBGCAM_dbg_stall_MASK) #define DDRC_DBGCAM_dbg_rd_q_empty_MASK (0x2000000U) #define DDRC_DBGCAM_dbg_rd_q_empty_SHIFT (25U) /*! dbg_rd_q_empty - When 1, all the Read command queues and Read data buffers inside DDRC are * empty. This register is to be used for debug purpose. An example use-case scenario: When Controller * enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have * executed all the commands in its queues and the write and read data drained. Hence this register * should be 1 at that time. FOR DEBUG ONLY */ #define DDRC_DBGCAM_dbg_rd_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_rd_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_rd_q_empty_MASK) #define DDRC_DBGCAM_dbg_wr_q_empty_MASK (0x4000000U) #define DDRC_DBGCAM_dbg_wr_q_empty_SHIFT (26U) /*! dbg_wr_q_empty - When 1, all the Write command queues and Write data buffers inside DDRC are * empty. This register is to be used for debug purpose. An example use-case scenario: When * Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have * executed all the commands in its queues and the write and read data drained. Hence this register * should be 1 at that time. FOR DEBUG ONLY */ #define DDRC_DBGCAM_dbg_wr_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_wr_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_wr_q_empty_MASK) #define DDRC_DBGCAM_rd_data_pipeline_empty_MASK (0x10000000U) #define DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT (28U) /*! rd_data_pipeline_empty - This bit indicates that the read data pipeline on the DFI interface is * empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to * ensure that all remaining commands/data have completed. */ #define DDRC_DBGCAM_rd_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT)) & DDRC_DBGCAM_rd_data_pipeline_empty_MASK) #define DDRC_DBGCAM_wr_data_pipeline_empty_MASK (0x20000000U) #define DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT (29U) /*! wr_data_pipeline_empty - This bit indicates that the write data pipeline on the DFI interface is * empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to * ensure that all remaining commands/data have completed. */ #define DDRC_DBGCAM_wr_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT)) & DDRC_DBGCAM_wr_data_pipeline_empty_MASK) #define DDRC_DBGCAM_dbg_stall_wr_MASK (0x40000000U) #define DDRC_DBGCAM_dbg_stall_wr_SHIFT (30U) /*! dbg_stall_wr - Stall for Write channel FOR DEBUG ONLY */ #define DDRC_DBGCAM_dbg_stall_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_wr_SHIFT)) & DDRC_DBGCAM_dbg_stall_wr_MASK) #define DDRC_DBGCAM_dbg_stall_rd_MASK (0x80000000U) #define DDRC_DBGCAM_dbg_stall_rd_SHIFT (31U) /*! dbg_stall_rd - Stall for Read channel FOR DEBUG ONLY */ #define DDRC_DBGCAM_dbg_stall_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_rd_SHIFT)) & DDRC_DBGCAM_dbg_stall_rd_MASK) /*! @} */ /*! @name DBGCMD - Command Debug Register */ /*! @{ */ #define DDRC_DBGCMD_rank0_refresh_MASK (0x1U) #define DDRC_DBGCMD_rank0_refresh_SHIFT (0U) /*! rank0_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank * 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When * DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent * to rank index 0. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is * recommended NOT to set this register bit if in Init or Deep power-down operating modes or * Maximum Power Saving Mode. */ #define DDRC_DBGCMD_rank0_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank0_refresh_SHIFT)) & DDRC_DBGCMD_rank0_refresh_MASK) #define DDRC_DBGCMD_rank1_refresh_MASK (0x2U) #define DDRC_DBGCMD_rank1_refresh_SHIFT (1U) /*! rank1_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank * 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When * DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent * to rank index 1. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is * recommended NOT to set this register bit if in Init or Deep power-down operating modes or * Maximum Power Saving Mode. */ #define DDRC_DBGCMD_rank1_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank1_refresh_SHIFT)) & DDRC_DBGCMD_rank1_refresh_MASK) #define DDRC_DBGCMD_zq_calib_short_MASK (0x10U) #define DDRC_DBGCMD_zq_calib_short_SHIFT (4U) /*! zq_calib_short - Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ * calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the * DDRC, the bit is automatically cleared. This operation can be performed only when * ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register * bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep * power-down operating modes and Maximum Power Saving Mode. */ #define DDRC_DBGCMD_zq_calib_short(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_zq_calib_short_SHIFT)) & DDRC_DBGCMD_zq_calib_short_MASK) #define DDRC_DBGCMD_ctrlupd_MASK (0x20U) #define DDRC_DBGCMD_ctrlupd_SHIFT (5U) /*! ctrlupd - Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the * PHY. When this request is stored in the DDRC, the bit is automatically cleared. This * operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ #define DDRC_DBGCMD_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_ctrlupd_SHIFT)) & DDRC_DBGCMD_ctrlupd_MASK) /*! @} */ /*! @name DBGSTAT - Status Debug Register */ /*! @{ */ #define DDRC_DBGSTAT_rank0_refresh_busy_MASK (0x1U) #define DDRC_DBGSTAT_rank0_refresh_busy_SHIFT (0U) /*! rank0_refresh_busy - SoC core may initiate a rank0_refresh operation (refresh operation to rank * 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh * is set to one. It goes low when the rank0_refresh operation is stored in the DDRC. It is * recommended not to perform rank0_refresh operations when this signal is high. - 0 - Indicates that * the SoC core can initiate a rank0_refresh operation - 1 - Indicates that rank0_refresh * operation has not been stored yet in the DDRC */ #define DDRC_DBGSTAT_rank0_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank0_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank0_refresh_busy_MASK) #define DDRC_DBGSTAT_rank1_refresh_busy_MASK (0x2U) #define DDRC_DBGSTAT_rank1_refresh_busy_SHIFT (1U) /*! rank1_refresh_busy - SoC core may initiate a rank1_refresh operation (refresh operation to rank * 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh * is set to one. It goes low when the rank1_refresh operation is stored in the DDRC. It is * recommended not to perform rank1_refresh operations when this signal is high. - 0 - Indicates that * the SoC core can initiate a rank1_refresh operation - 1 - Indicates that rank1_refresh * operation has not been stored yet in the DDRC */ #define DDRC_DBGSTAT_rank1_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank1_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank1_refresh_busy_MASK) #define DDRC_DBGSTAT_zq_calib_short_busy_MASK (0x10U) #define DDRC_DBGSTAT_zq_calib_short_busy_SHIFT (4U) /*! zq_calib_short_busy - SoC core may initiate a ZQCS (ZQ calibration short) operation only if this * signal is low. This signal goes high in the clock after the DDRC accepts the ZQCS request. It * goes low when the ZQCS operation is initiated in the DDRC. It is recommended not to perform * ZQCS operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ZQCS * operation - 1 - Indicates that ZQCS operation has not been initiated yet in the DDRC */ #define DDRC_DBGSTAT_zq_calib_short_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_zq_calib_short_busy_SHIFT)) & DDRC_DBGSTAT_zq_calib_short_busy_MASK) #define DDRC_DBGSTAT_ctrlupd_busy_MASK (0x20U) #define DDRC_DBGSTAT_ctrlupd_busy_SHIFT (5U) /*! ctrlupd_busy - SoC core may initiate a ctrlupd operation only if this signal is low. This signal * goes high in the clock after the DDRC accepts the ctrlupd request. It goes low when the * ctrlupd operation is initiated in the DDRC. It is recommended not to perform ctrlupd operations * when this signal is high. - 0 - Indicates that the SoC core can initiate a ctrlupd operation - 1 * - Indicates that ctrlupd operation has not been initiated yet in the DDRC */ #define DDRC_DBGSTAT_ctrlupd_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_ctrlupd_busy_SHIFT)) & DDRC_DBGSTAT_ctrlupd_busy_MASK) /*! @} */ /*! @name SWCTL - Software Register Programming Control Enable */ /*! @{ */ #define DDRC_SWCTL_sw_done_MASK (0x1U) #define DDRC_SWCTL_sw_done_SHIFT (0U) /*! sw_done - Enable quasi-dynamic register programming outside reset. Program register to 0 to * enable quasi-dynamic programming. Set back register to 1 once programming is done. */ #define DDRC_SWCTL_sw_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWCTL_sw_done_SHIFT)) & DDRC_SWCTL_sw_done_MASK) /*! @} */ /*! @name SWSTAT - Software Register Programming Control Status */ /*! @{ */ #define DDRC_SWSTAT_sw_done_ack_MASK (0x1U) #define DDRC_SWSTAT_sw_done_ack_SHIFT (0U) /*! sw_done_ack - Register programming done. This register is the echo of SWCTL.sw_done. Wait for * sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure * that the correct registers values are propagated to the destination clock domains. */ #define DDRC_SWSTAT_sw_done_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWSTAT_sw_done_ack_SHIFT)) & DDRC_SWSTAT_sw_done_ack_MASK) /*! @} */ /*! @name POISONCFG - AXI Poison Configuration Register. */ /*! @{ */ #define DDRC_POISONCFG_wr_poison_slverr_en_MASK (0x1U) #define DDRC_POISONCFG_wr_poison_slverr_en_SHIFT (0U) /*! wr_poison_slverr_en - If set to 1, enables SLVERR response for write transaction poisoning */ #define DDRC_POISONCFG_wr_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_slverr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_slverr_en_MASK) #define DDRC_POISONCFG_wr_poison_intr_en_MASK (0x10U) #define DDRC_POISONCFG_wr_poison_intr_en_SHIFT (4U) /*! wr_poison_intr_en - If set to 1, enables interrupts for write transaction poisoning */ #define DDRC_POISONCFG_wr_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_en_MASK) #define DDRC_POISONCFG_wr_poison_intr_clr_MASK (0x100U) #define DDRC_POISONCFG_wr_poison_intr_clr_SHIFT (8U) /*! wr_poison_intr_clr - Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for * correct value to propagate to core logic and clear the interrupts. */ #define DDRC_POISONCFG_wr_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_clr_MASK) #define DDRC_POISONCFG_rd_poison_slverr_en_MASK (0x10000U) #define DDRC_POISONCFG_rd_poison_slverr_en_SHIFT (16U) /*! rd_poison_slverr_en - If set to 1, enables SLVERR response for read transaction poisoning */ #define DDRC_POISONCFG_rd_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_slverr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_slverr_en_MASK) #define DDRC_POISONCFG_rd_poison_intr_en_MASK (0x100000U) #define DDRC_POISONCFG_rd_poison_intr_en_SHIFT (20U) /*! rd_poison_intr_en - If set to 1, enables interrupts for read transaction poisoning */ #define DDRC_POISONCFG_rd_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_en_MASK) #define DDRC_POISONCFG_rd_poison_intr_clr_MASK (0x1000000U) #define DDRC_POISONCFG_rd_poison_intr_clr_SHIFT (24U) /*! rd_poison_intr_clr - Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for * correct value to propagate to core logic and clear the interrupts. */ #define DDRC_POISONCFG_rd_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_clr_MASK) /*! @} */ /*! @name POISONSTAT - AXI Poison Status Register */ /*! @{ */ #define DDRC_POISONSTAT_wr_poison_intr_0_MASK (0x1U) #define DDRC_POISONSTAT_wr_poison_intr_0_SHIFT (0U) /*! wr_poison_intr_0 - Write transaction poisoning error interrupt for port 0. This register is a * APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is * poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0, and * so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB * clock. */ #define DDRC_POISONSTAT_wr_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_wr_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_wr_poison_intr_0_MASK) #define DDRC_POISONSTAT_rd_poison_intr_0_MASK (0x10000U) #define DDRC_POISONSTAT_rd_poison_intr_0_SHIFT (16U) /*! rd_poison_intr_0 - Read transaction poisoning error interrupt for port 0. This register is a APB * clock copy (double register synchronizer) of the interrupt asserted when a transaction is * poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0, and * so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ #define DDRC_POISONSTAT_rd_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_rd_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_rd_poison_intr_0_MASK) /*! @} */ /*! @name PSTAT - Port Status Register */ /*! @{ */ #define DDRC_PSTAT_rd_port_busy_0_MASK (0x1U) #define DDRC_PSTAT_rd_port_busy_0_SHIFT (0U) /*! rd_port_busy_0 - Indicates if there are outstanding reads for AXI port 0. */ #define DDRC_PSTAT_rd_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_rd_port_busy_0_SHIFT)) & DDRC_PSTAT_rd_port_busy_0_MASK) #define DDRC_PSTAT_wr_port_busy_0_MASK (0x10000U) #define DDRC_PSTAT_wr_port_busy_0_SHIFT (16U) /*! wr_port_busy_0 - Indicates if there are outstanding writes for AXI port 0. */ #define DDRC_PSTAT_wr_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_wr_port_busy_0_SHIFT)) & DDRC_PSTAT_wr_port_busy_0_MASK) /*! @} */ /*! @name PCCFG - Port Common Configuration Register */ /*! @{ */ #define DDRC_PCCFG_go2critical_en_MASK (0x1U) #define DDRC_PCCFG_go2critical_en_SHIFT (0U) /*! go2critical_en - If set to 1 (enabled), sets co_gs_go2critical_wr and * co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from * AXI master. If set to 0 (disabled), co_gs_go2critical_wr and * co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. */ #define DDRC_PCCFG_go2critical_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_go2critical_en_SHIFT)) & DDRC_PCCFG_go2critical_en_MASK) #define DDRC_PCCFG_pagematch_limit_MASK (0x10U) #define DDRC_PCCFG_pagematch_limit_SHIFT (4U) /*! pagematch_limit - Page match four limit. If set to 1, limits the number of consecutive same page * DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is * enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC * transactions. */ #define DDRC_PCCFG_pagematch_limit(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_pagematch_limit_SHIFT)) & DDRC_PCCFG_pagematch_limit_MASK) #define DDRC_PCCFG_bl_exp_mode_MASK (0x100U) #define DDRC_PCCFG_bl_exp_mode_SHIFT (8U) /*! bl_exp_mode - Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every * AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then * XPI will use half of the memory burst length as a unit. This applies to both reads and * writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in * cases where Partial Writes is enabled (DDRC_PARTIAL_WR=1), in order to avoid or minimize t_ccd_l * penalty in DDR4 and t_ccd_mw penalty in LPDDR4. Hence, bl_exp_mode=1 is only recommended if * DDR4 or LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the * following cases: - DDRC_PARTIAL_WR=0 - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01, * MEMC_BURST_LENGTH=8 and MSTR.burst_rdwr=1000 (LPDDR4 only) - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01, * MEMC_BURST_LENGTH=4 and MSTR.burst_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or * CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Data Channel * Interleave is enabled */ #define DDRC_PCCFG_bl_exp_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_bl_exp_mode_SHIFT)) & DDRC_PCCFG_bl_exp_mode_MASK) /*! @} */ /*! @name PCFGR_0 - Port n Configuration Read Register */ /*! @{ */ #define DDRC_PCFGR_0_rd_port_priority_MASK (0x3FFU) #define DDRC_PCFGR_0_rd_port_priority_SHIFT (0U) /*! rd_port_priority - Determines the initial load value of read aging counters. These counters will * be parallel loaded after reset, or after each grant to the corresponding port. The aging * counters down-count every clock cycle where the port is requesting but not granted. The higher * significant 5-bits of the read aging counter sets the priority of the read channel of a given * port. Port's priority will increase as the higher significant 5-bits of the counter starts to * decrease. When the aging counter becomes 0, the corresponding port channel will have the highest * priority level (timeout condition - Priority0). For multi-port configurations, the aging * counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are * enabled (timeout is still applicable). For single port configurations, the aging counters are * only used when they timeout (become 0) to force read-write direction switching. In this case, * external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read * priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by * command basis. Note: The two LSBs of this register field are tied internally to 2'b00. */ #define DDRC_PCFGR_0_rd_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_priority_SHIFT)) & DDRC_PCFGR_0_rd_port_priority_MASK) #define DDRC_PCFGR_0_rd_port_aging_en_MASK (0x1000U) #define DDRC_PCFGR_0_rd_port_aging_en_SHIFT (12U) /*! rd_port_aging_en - If set to 1, enables aging function for the read channel of the port. */ #define DDRC_PCFGR_0_rd_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_aging_en_SHIFT)) & DDRC_PCFGR_0_rd_port_aging_en_MASK) #define DDRC_PCFGR_0_rd_port_urgent_en_MASK (0x2000U) #define DDRC_PCFGR_0_rd_port_urgent_en_SHIFT (13U) /*! rd_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled * and arurgent is asserted by the master, that port becomes the highest priority and * co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in * PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is * independent of address handshaking (it is not associated with any particular command). */ #define DDRC_PCFGR_0_rd_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_urgent_en_SHIFT)) & DDRC_PCFGR_0_rd_port_urgent_en_MASK) #define DDRC_PCFGR_0_rd_port_pagematch_en_MASK (0x4000U) #define DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT (14U) /*! rd_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a * requesting port is granted, the port is continued to be granted if the following immediate commands are * to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit * register. */ #define DDRC_PCFGR_0_rd_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT)) & DDRC_PCFGR_0_rd_port_pagematch_en_MASK) #define DDRC_PCFGR_0_rdwr_ordered_en_MASK (0x10000U) #define DDRC_PCFGR_0_rdwr_ordered_en_SHIFT (16U) /*! rdwr_ordered_en - Enable ordered read/writes. If set to 1, preserves the ordering between read * transaction and write transaction issued to the same address, on a given port. In other words, * the controller ensures that all same address read and write commands from the application port * interface are transported to the DFI interface in the order of acceptance. This feature is * useful in cases where software coherency is desired for masters issuing back-to-back read/write * transactions without waiting for write/read responses. Note that this register has an effect * only if necessary logic is instantiated via the DDRC_RDWR_ORDERED_n parameter. */ #define DDRC_PCFGR_0_rdwr_ordered_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rdwr_ordered_en_SHIFT)) & DDRC_PCFGR_0_rdwr_ordered_en_MASK) /*! @} */ /*! @name PCFGW_0 - Port n Configuration Write Register */ /*! @{ */ #define DDRC_PCFGW_0_wr_port_priority_MASK (0x3FFU) #define DDRC_PCFGW_0_wr_port_priority_SHIFT (0U) /*! wr_port_priority - Determines the initial load value of write aging counters. These counters * will be parallel loaded after reset, or after each grant to the corresponding port. The aging * counters down-count every clock cycle where the port is requesting but not granted. The higher * significant 5-bits of the write aging counter sets the initial priority of the write channel of * a given port. Port's priority will increase as the higher significant 5-bits of the counter * starts to decrease. When the aging counter becomes 0, the corresponding port channel will have * the highest priority level. For multi-port configurations, the aging counters cannot be used to * set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is * still applicable). For single port configurations, the aging counters are only used when they * timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register * field are tied internally to 2'b00. */ #define DDRC_PCFGW_0_wr_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_priority_SHIFT)) & DDRC_PCFGW_0_wr_port_priority_MASK) #define DDRC_PCFGW_0_wr_port_aging_en_MASK (0x1000U) #define DDRC_PCFGW_0_wr_port_aging_en_SHIFT (12U) /*! wr_port_aging_en - If set to 1, enables aging function for the write channel of the port. */ #define DDRC_PCFGW_0_wr_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_aging_en_SHIFT)) & DDRC_PCFGW_0_wr_port_aging_en_MASK) #define DDRC_PCFGW_0_wr_port_urgent_en_MASK (0x2000U) #define DDRC_PCFGW_0_wr_port_urgent_en_SHIFT (13U) /*! wr_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled * and awurgent is asserted by the master, that port becomes the highest priority and * co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that * awurgent signal can be asserted anytime and as long as required which is independent of address * handshaking (it is not associated with any particular command). */ #define DDRC_PCFGW_0_wr_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_urgent_en_SHIFT)) & DDRC_PCFGW_0_wr_port_urgent_en_MASK) #define DDRC_PCFGW_0_wr_port_pagematch_en_MASK (0x4000U) #define DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT (14U) /*! wr_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a * requesting port is granted, the port is continued to be granted if the following immediate commands are * to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit * register. */ #define DDRC_PCFGW_0_wr_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT)) & DDRC_PCFGW_0_wr_port_pagematch_en_MASK) /*! @} */ /*! @name PCTRL_0 - Port n Control Register */ /*! @{ */ #define DDRC_PCTRL_0_port_en_MASK (0x1U) #define DDRC_PCTRL_0_port_en_SHIFT (0U) /*! port_en - Enables AXI port n. */ #define DDRC_PCTRL_0_port_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCTRL_0_port_en_SHIFT)) & DDRC_PCTRL_0_port_en_MASK) /*! @} */ /*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */ /*! @{ */ #define DDRC_PCFGQOS0_0_rqos_map_level1_MASK (0xFU) #define DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT (0U) /*! rqos_map_level1 - Separation level1 indicating the end of region0 mapping; start of region0 is * 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which * corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where * the higher the value corresponds to higher port priority. All of the map_level* registers must * be set to distinct values. */ #define DDRC_PCFGQOS0_0_rqos_map_level1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_level1_MASK) #define DDRC_PCFGQOS0_0_rqos_map_region0_MASK (0x30000U) #define DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT (16U) /*! rqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0: * LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address * queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support is disabled * (DDRC_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR * traffic. */ #define DDRC_PCFGQOS0_0_rqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region0_MASK) #define DDRC_PCFGQOS0_0_rqos_map_region1_MASK (0x300000U) #define DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT (20U) /*! rqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0 : * LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address * queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled * (DDRC_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR * traffic. */ #define DDRC_PCFGQOS0_0_rqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region1_MASK) /*! @} */ /*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */ /*! @{ */ #define DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK (0x7FFU) #define DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT (0U) /*! rqos_map_timeoutb - Specifies the timeout value for transactions mapped to the blue address queue. */ #define DDRC_PCFGQOS1_0_rqos_map_timeoutb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK) #define DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK (0x7FF0000U) #define DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT (16U) /*! rqos_map_timeoutr - Specifies the timeout value for transactions mapped to the red address queue. */ #define DDRC_PCFGQOS1_0_rqos_map_timeoutr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK) /*! @} */ /*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */ /*! @{ */ #define DDRC_PCFGWQOS0_0_wqos_map_level_MASK (0xFU) #define DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT (0U) /*! wqos_map_level - Separation level indicating the end of region0 mapping; start of region0 is 0. * Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos * values are used directly as port priorities, where the higher the value corresponds to higher * port priority. */ #define DDRC_PCFGWQOS0_0_wqos_map_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_level_MASK) #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) #define DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT (16U) /*! wqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0: * NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region0 is set * to 1 (VPW), VPW traffic is aliased to NPW traffic. */ #define DDRC_PCFGWQOS0_0_wqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK) #define DDRC_PCFGWQOS0_0_wqos_map_region1_MASK (0x300000U) #define DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT (20U) /*! wqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0: * NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region 1 is * set to 1 (VPW), VPW traffic is aliased to LPW traffic. */ #define DDRC_PCFGWQOS0_0_wqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region1_MASK) /*! @} */ /*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */ /*! @{ */ #define DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK (0x7FFU) #define DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT (0U) /*! wqos_map_timeout - Specifies the timeout value for write transactions. */ #define DDRC_PCFGWQOS1_0_wqos_map_timeout(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT)) & DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK) /*! @} */ /*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */ /*! @{ */ #define DDRC_DERATEEN_SHADOW_derate_enable_MASK (0x1U) #define DDRC_DERATEEN_SHADOW_derate_enable_SHIFT (0U) /*! derate_enable - Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing * parameter derating is enabled using MR4 read value. Present only in designs configured to support * LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. */ #define DDRC_DERATEEN_SHADOW_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_enable_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_enable_MASK) #define DDRC_DERATEEN_SHADOW_derate_value_MASK (0x2U) #define DDRC_DERATEEN_SHADOW_derate_value_SHIFT (1U) /*! derate_value - Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in * designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as * derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of * core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it * should be set to 0. */ #define DDRC_DERATEEN_SHADOW_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_value_MASK) #define DDRC_DERATEEN_SHADOW_derate_byte_MASK (0xF0U) #define DDRC_DERATEEN_SHADOW_derate_byte_SHIFT (4U) /*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 * Indicates which byte of the MRR data is used for derating. The maximum valid value depends on * MEMC_DRAM_TOTAL_DATA_WIDTH. */ #define DDRC_DERATEEN_SHADOW_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_byte_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_byte_MASK) #define DDRC_DERATEEN_SHADOW_rc_derate_value_MASK (0x300U) #define DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT (8U) /*! rc_derate_value - Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. * - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in designs configured to support * LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by * the core_ddrc_core_clk period, and rounding up the next integer. */ #define DDRC_DERATEEN_SHADOW_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_rc_derate_value_MASK) /*! @} */ /*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */ /*! @{ */ #define DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK (0xFFFFFFFFU) #define DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT (0U) /*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters. * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to * zero. Unit: DFI clock cycle. */ #define DDRC_DERATEINT_SHADOW_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK) /*! @} */ /*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */ /*! @{ */ #define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK (0x4U) #define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT (2U) /*! per_bank_refresh - - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows * traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should * be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support * LPDDR2/LPDDR3/LPDDR4 */ #define DDRC_RFSHCTL0_SHADOW_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK) #define DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK (0x1F0U) #define DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT (4U) /*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to * accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to * perform a refresh is a one-time penalty that must be paid for each group of refreshes. * Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. * Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases * the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2 * refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of * DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not * per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh * feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X * mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care * must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated * due to a PHY-initiated update occurring shortly before a refresh burst was due. In this * situation, the refresh burst will be delayed until the PHY-initiated update is complete. */ #define DDRC_RFSHCTL0_SHADOW_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK) #define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK (0x1F000U) #define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT (12U) /*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, * but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be * performed. A speculative refresh is a refresh performed at a time when refresh would be * useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time * determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since * the last refresh, then a speculative refresh is performed. Speculative refreshes continues * successively until there are no refreshes pending or until new reads or writes are issued to the * DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks. */ #define DDRC_RFSHCTL0_SHADOW_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK) #define DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK (0xF00000U) #define DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT (20U) /*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or * page timer expires. A critical refresh is to be issued before this threshold is reached. It is * recommended that this not be changed from the default value, currently shown as 0x2. It must * always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, * internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled * (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to * RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks. */ #define DDRC_RFSHCTL0_SHADOW_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK) /*! @} */ /*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */ /*! @{ */ #define DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK (0x3FFU) #define DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT (0U) /*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is * operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller * is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In * LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations * is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is * equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending * on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the * appropriate value from the spec based on the 'refresh_mode' and the device density that is used. * Unit: Clocks. */ #define DDRC_RFSHTMG_SHADOW_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK) #define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK (0x8000U) #define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT (15U) /*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when * DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 * devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW * parameter not used - 1 - tREFBW parameter used */ #define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK) #define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK (0xFFF0000U) #define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT (16U) /*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us * for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For * LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register * should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this * register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode, * program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending * on the refresh mode. The user should program the appropriate value from the spec based on the * value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be * greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or * DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed * 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode: * RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks. */ #define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK) /*! @} */ /*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */ /*! @{ */ #define DDRC_INIT3_SHADOW_emr_MASK (0xFFFFU) #define DDRC_INIT3_SHADOW_emr_SHIFT (0U) /*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this * register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1 * register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by * the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - * Value to write to MR2 register */ #define DDRC_INIT3_SHADOW_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_emr_SHIFT)) & DDRC_INIT3_SHADOW_emr_MASK) #define DDRC_INIT3_SHADOW_mr_MASK (0xFFFF0000U) #define DDRC_INIT3_SHADOW_mr_SHIFT (16U) /*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The * DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to * write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register */ #define DDRC_INIT3_SHADOW_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_mr_SHIFT)) & DDRC_INIT3_SHADOW_mr_MASK) /*! @} */ /*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */ /*! @{ */ #define DDRC_INIT4_SHADOW_emr3_MASK (0xFFFFU) #define DDRC_INIT4_SHADOW_emr3_SHIFT (0U) /*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register * mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register */ #define DDRC_INIT4_SHADOW_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr3_SHIFT)) & DDRC_INIT4_SHADOW_emr3_MASK) #define DDRC_INIT4_SHADOW_emr2_MASK (0xFFFF0000U) #define DDRC_INIT4_SHADOW_emr2_SHIFT (16U) /*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register * LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused */ #define DDRC_INIT4_SHADOW_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr2_SHIFT)) & DDRC_INIT4_SHADOW_emr2_MASK) /*! @} */ /*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */ /*! @{ */ #define DDRC_INIT6_SHADOW_mr5_MASK (0xFFFFU) #define DDRC_INIT6_SHADOW_mr5_SHIFT (0U) /*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. */ #define DDRC_INIT6_SHADOW_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr5_SHIFT)) & DDRC_INIT6_SHADOW_mr5_MASK) #define DDRC_INIT6_SHADOW_mr4_MASK (0xFFFF0000U) #define DDRC_INIT6_SHADOW_mr4_SHIFT (16U) /*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. */ #define DDRC_INIT6_SHADOW_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr4_SHIFT)) & DDRC_INIT6_SHADOW_mr4_MASK) /*! @} */ /*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */ /*! @{ */ #define DDRC_INIT7_SHADOW_mr6_MASK (0xFFFF0000U) #define DDRC_INIT7_SHADOW_mr6_SHIFT (16U) /*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. */ #define DDRC_INIT7_SHADOW_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_SHADOW_mr6_SHIFT)) & DDRC_INIT7_SHADOW_mr6_MASK) /*! @} */ /*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */ /*! @{ */ #define DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK (0x3FU) #define DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT (0U) /*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the * controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding * up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, * program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks */ #define DDRC_DRAMTMG0_SHADOW_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK) #define DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK (0x7F00U) #define DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT (8U) /*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the * maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. * When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2. * No rounding up. Unit: Multiples of 1024 clocks. */ #define DDRC_DRAMTMG0_SHADOW_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK) #define DDRC_DRAMTMG0_SHADOW_t_faw_MASK (0x3F0000U) #define DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT (16U) /*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank * design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller * is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next * integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency * mode. Unit: Clocks */ #define DDRC_DRAMTMG0_SHADOW_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_faw_MASK) #define DDRC_DRAMTMG0_SHADOW_wr2pre_MASK (0x7F000000U) #define DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT (24U) /*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL * + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower * frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in * the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. * - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra * cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2 * frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller * is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2 * and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it * may be necessary to adjust the value of this parameter to compensate for the extra cycle of * latency through the LRDIMM. */ #define DDRC_DRAMTMG0_SHADOW_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT)) & DDRC_DRAMTMG0_SHADOW_wr2pre_MASK) /*! @} */ /*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */ /*! @{ */ #define DDRC_DRAMTMG1_SHADOW_t_rc_MASK (0x7FU) #define DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT (0U) /*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2 * frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit: * Clocks. */ #define DDRC_DRAMTMG1_SHADOW_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_rc_MASK) #define DDRC_DRAMTMG1_SHADOW_rd2pre_MASK (0x3F00U) #define DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT (8U) /*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, * 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4) * or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: * LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 * - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, * use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode, * divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T * mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. * Unit: Clocks. */ #define DDRC_DRAMTMG1_SHADOW_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT)) & DDRC_DRAMTMG1_SHADOW_rd2pre_MASK) #define DDRC_DRAMTMG1_SHADOW_t_xp_MASK (0x1F0000U) #define DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT (16U) /*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be * programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used, * set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program * this to (tXP/2) and round it up to the next integer value. Units: Clocks */ #define DDRC_DRAMTMG1_SHADOW_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_xp_MASK) /*! @} */ /*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */ /*! @{ */ #define DDRC_DRAMTMG2_SHADOW_wr2rd_MASK (0x3FU) #define DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT (0U) /*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from * write command to read command for same bank group. In others, minimum time from write command to * read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and * global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL * = burst length. This must match the value programmed in the BL bit of the mode register to * the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes * directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes * directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. * When the controller is operating in 1:2 mode, divide the value calculated using the above * equation by 2, and round it up to next integer. */ #define DDRC_DRAMTMG2_SHADOW_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT)) & DDRC_DRAMTMG2_SHADOW_wr2rd_MASK) #define DDRC_DRAMTMG2_SHADOW_rd2wr_MASK (0x3F00U) #define DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT (8U) /*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL * + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) * + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + * RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. * Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see * the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: - * WL = write latency - BL = burst length. This must match the value programmed in the BL bit of * the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write * preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to * LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated * tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the * value calculated using the above equation by 2, and round it up to next integer. Note that, * depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter * to compensate for the extra cycle of latency through the LRDIMM. */ #define DDRC_DRAMTMG2_SHADOW_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT)) & DDRC_DRAMTMG2_SHADOW_rd2wr_MASK) #define DDRC_DRAMTMG2_SHADOW_read_latency_MASK (0x3F0000U) #define DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT (16U) /*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be * set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust * the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When * the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the * above equation by 2, and round it up to next integer. This register field is not required for * DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in * DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks */ #define DDRC_DRAMTMG2_SHADOW_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_read_latency_MASK) #define DDRC_DRAMTMG2_SHADOW_write_latency_MASK (0x3F000000U) #define DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT (24U) /*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be * set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if * using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra * cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio * mode, divide the value calculated using the above equation by 2, and round it up to next * integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), * as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those * protocols Unit: clocks */ #define DDRC_DRAMTMG2_SHADOW_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_write_latency_MASK) /*! @} */ /*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */ /*! @{ */ #define DDRC_DRAMTMG3_SHADOW_t_mod_MASK (0x3FFU) #define DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT (0U) /*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and * following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. * Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to * next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using * RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to * compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip. * Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller * is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if * controller is operating in 1:2 frequency ratio mode. */ #define DDRC_DRAMTMG3_SHADOW_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mod_MASK) #define DDRC_DRAMTMG3_SHADOW_t_mrd_MASK (0x3F000U) #define DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT (12U) /*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected * SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS * command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is * operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer * value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. */ #define DDRC_DRAMTMG3_SHADOW_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrd_MASK) #define DDRC_DRAMTMG3_SHADOW_t_mrw_MASK (0x3FF00000U) #define DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT (20U) /*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs * configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 * typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, * this register is used for the time from a MRW/MRR to all other commands. When the controller * is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and * round it up to the next integer value. For LDPDR3, this register is used for the time from a * MRW/MRR to a MRW/MRR. */ #define DDRC_DRAMTMG3_SHADOW_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrw_MASK) /*! @} */ /*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */ /*! @{ */ #define DDRC_DRAMTMG4_SHADOW_t_rp_MASK (0x1FU) #define DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT (0U) /*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is * operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is * operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + * 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set * to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. */ #define DDRC_DRAMTMG4_SHADOW_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rp_MASK) #define DDRC_DRAMTMG4_SHADOW_t_rrd_MASK (0xF00U) #define DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT (8U) /*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank * group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller * is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it * up to the next integer value. Unit: Clocks. */ #define DDRC_DRAMTMG4_SHADOW_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rrd_MASK) #define DDRC_DRAMTMG4_SHADOW_t_ccd_MASK (0xF0000U) #define DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT (16U) /*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank * group. Others: tCCD: This is the minimum time between two reads or two writes. When the * controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it * up to the next integer value. Unit: clocks. */ #define DDRC_DRAMTMG4_SHADOW_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_ccd_MASK) #define DDRC_DRAMTMG4_SHADOW_t_rcd_MASK (0x1F000000U) #define DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT (24U) /*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the * controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round * it up to the next integer value. Minimum value allowed for this register is 1, which implies * minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio * mode. Unit: Clocks. */ #define DDRC_DRAMTMG4_SHADOW_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rcd_MASK) /*! @} */ /*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */ /*! @{ */ #define DDRC_DRAMTMG5_SHADOW_t_cke_MASK (0x1FU) #define DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT (0U) /*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - * LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of * tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When * the controller is operating in 1:2 frequency ratio mode, program this to (value described * above)/2 and round it up to the next integer value. Unit: Clocks. */ #define DDRC_DRAMTMG5_SHADOW_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cke_MASK) #define DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK (0x3F00U) #define DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT (8U) /*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing * in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR * - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity * latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased * by PL. When the controller is operating in 1:2 frequency ratio mode, program this to * recommended value divided by two and round it up to next integer. */ #define DDRC_DRAMTMG5_SHADOW_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK) #define DDRC_DRAMTMG5_SHADOW_t_cksre_MASK (0xF0000U) #define DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT (16U) /*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. * Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - * LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+ * PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should * be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program * this to recommended value divided by two and round it up to next integer. */ #define DDRC_DRAMTMG5_SHADOW_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksre_MASK) #define DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK (0xF000000U) #define DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT (24U) /*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock * before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 - * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the * controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by * two and round it up to next integer. */ #define DDRC_DRAMTMG5_SHADOW_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK) /*! @} */ /*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */ /*! @{ */ #define DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK (0xFU) #define DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT (0U) /*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before * issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop * Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 * When the controller is operating in 1:2 frequency ratio mode, program this to recommended value * divided by two and round it up to next integer. This is only present for designs supporting * mDDR or LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_DRAMTMG6_SHADOW_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK) #define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK (0xF0000U) #define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT (16U) /*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock * before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR: * 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, * program this to recommended value divided by two and round it up to next integer. This is only * present for designs supporting mDDR or LPDDR2 devices. */ #define DDRC_DRAMTMG6_SHADOW_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK) #define DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK (0xF000000U) #define DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT (24U) /*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock. * Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - * LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to * recommended value divided by two and round it up to next integer. This is only present for designs * supporting mDDR or LPDDR2/LPDDR3 devices. */ #define DDRC_DRAMTMG6_SHADOW_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK) /*! @} */ /*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */ /*! @{ */ #define DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK (0xFU) #define DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT (0U) /*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before * issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 - * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the * same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode, * program this to recommended value divided by two and round it up to next integer. This is only * present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_DRAMTMG7_SHADOW_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK) #define DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK (0xF00U) #define DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT (8U) /*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock. * Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 * - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as * DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this * to recommended value divided by two and round it up to next integer. This is only present for * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_DRAMTMG7_SHADOW_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK) /*! @} */ /*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */ /*! @{ */ #define DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK (0x7FU) #define DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT (0U) /*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is * operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round * up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and * DDR4 SDRAMs. */ #define DDRC_DRAMTMG8_SHADOW_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK) #define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK (0x7F00U) #define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT (8U) /*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller * is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and * round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and * DDR4 SDRAMs. */ #define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK) #define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK (0x7F0000U) #define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT (16U) /*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self * Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. * Note: Ensure this is less than or equal to t_xs_x32. */ #define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK) #define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK (0x7F000000U) #define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT (24U) /*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown * mode). When the controller is operating in 1:2 frequency ratio mode, program this to the * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: * This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to * t_xs_x32. */ #define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK) /*! @} */ /*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */ /*! @{ */ #define DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK (0x3FU) #define DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT (0U) /*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different * bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and * global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where: * - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value * programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read * command delay for different bank group. This comes directly from the SDRAM specification. When * the controller is operating in 1:2 mode, divide the value calculated using the above equation * by 2, and round it up to next integer. */ #define DDRC_DRAMTMG9_SHADOW_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK) #define DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK (0xF00U) #define DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT (8U) /*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank * group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2) * and round it up to the next integer value. Present only in designs configured to support DDR4. * Unit: Clocks. */ #define DDRC_DRAMTMG9_SHADOW_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK) #define DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK (0x70000U) #define DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT (16U) /*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank * group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When * the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round * it up to the next integer value. Present only in designs configured to support DDR4. Unit: * clocks. */ #define DDRC_DRAMTMG9_SHADOW_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK) #define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK (0x40000000U) #define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT (30U) /*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 */ #define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK) /*! @} */ /*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */ /*! @{ */ #define DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK (0x3U) #define DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT (0U) /*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in * 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer * value. Unit: Clocks */ #define DDRC_DRAMTMG10_SHADOW_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK) #define DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK (0xCU) #define DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT (2U) /*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in * 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer * value. Unit: Clocks */ #define DDRC_DRAMTMG10_SHADOW_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK) #define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK (0x1F00U) #define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT (8U) /*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is * defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for * this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2) * and round it up to the next integer value. Unit: Clocks */ #define DDRC_DRAMTMG10_SHADOW_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK) #define DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK (0x1F0000U) #define DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT (16U) /*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even * number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK * tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28 * When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up * to the next integer value. Unit: Clocks */ #define DDRC_DRAMTMG10_SHADOW_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK) /*! @} */ /*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */ /*! @{ */ #define DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK (0x1FU) #define DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT (0U) /*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs * configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio * mode, divide the value calculated using the above equation by 2, and round it up to next * integer. */ #define DDRC_DRAMTMG11_SHADOW_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK) #define DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK (0x300U) #define DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT (8U) /*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2 * frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value. * Present only in designs configured to support DDR4. Unit: Clocks. */ #define DDRC_DRAMTMG11_SHADOW_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK) #define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK (0x1F0000U) #define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT (16U) /*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the * controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present * only in designs configured to support DDR4. Unit: clocks. */ #define DDRC_DRAMTMG11_SHADOW_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK) #define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK (0x7F000000U) #define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT (24U) /*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. * When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and * round it up to the next integer value. Present only in designs configured to support DDR4. * Unit: Multiples of 32 clocks. */ #define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK) /*! @} */ /*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */ /*! @{ */ #define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK (0x1FU) #define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT (0U) /*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the * controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up * to the next integer value. */ #define DDRC_DRAMTMG12_SHADOW_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK) #define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK (0xF00U) #define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT (8U) /*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is * operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next * integer value. */ #define DDRC_DRAMTMG12_SHADOW_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK) #define DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK (0x30000U) #define DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT (16U) /*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE * or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to * (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value. */ #define DDRC_DRAMTMG12_SHADOW_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK) /*! @} */ /*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */ /*! @{ */ #define DDRC_DRAMTMG13_SHADOW_t_ppd_MASK (0x7U) #define DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT (0U) /*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the * controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to * the next integer value. Unit: Clocks. */ #define DDRC_DRAMTMG13_SHADOW_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ppd_MASK) #define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK (0x3F0000U) #define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT (16U) /*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write * command for same bank. When the controller is operating in 1:2 frequency ratio mode, program * this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks. */ #define DDRC_DRAMTMG13_SHADOW_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK) #define DDRC_DRAMTMG13_SHADOW_odtloff_MASK (0x7F000000U) #define DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT (24U) /*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When * the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round * it up to the next integer value. Unit: Clocks. */ #define DDRC_DRAMTMG13_SHADOW_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT)) & DDRC_DRAMTMG13_SHADOW_odtloff_MASK) /*! @} */ /*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */ /*! @{ */ #define DDRC_DRAMTMG14_SHADOW_t_xsr_MASK (0xFFFU) #define DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT (0U) /*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2 * frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. * Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode. */ #define DDRC_DRAMTMG14_SHADOW_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT)) & DDRC_DRAMTMG14_SHADOW_t_xsr_MASK) /*! @} */ /*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */ /*! @{ */ #define DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK (0xFFU) #define DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT (0U) /*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 * RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the * clock must be stable for a time specified by tSTAB - in the case of input clock frequency * change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for * DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to * recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock * cycles. */ #define DDRC_DRAMTMG15_SHADOW_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK) #define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK (0x80000000U) #define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT (31U) /*! en_dfi_lp_t_stab - - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is * stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when * exiting DFI LP */ #define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK) /*! @} */ /*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */ /*! @{ */ #define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK (0x3FFU) #define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT (0U) /*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles * of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. * When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and * round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or * LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_ZQCTL0_SHADOW_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK) #define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK (0x7FF0000U) #define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT (16U) /*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI * clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is * issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program * this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to * tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it * up to the next integer value. This is only present for designs supporting DDR3/DDR4 or * LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_ZQCTL0_SHADOW_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK) #define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK (0x10000000U) #define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT (28U) /*! dis_mpsmx_zqcl - - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only * applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving * Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting * DDR4 devices. Note: Do not issue ZQCL command at Maximum Power Save Mode exit if the * DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after * exiting MPSM mode. */ #define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK) #define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK (0x20000000U) #define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT (29U) /*! zq_resistor_shared - - 1 - Denotes that ZQ resistor is shared between ranks. Means * ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 - * ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or * LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_ZQCTL0_SHADOW_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK) #define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK (0x40000000U) #define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT (30U) /*! dis_srx_zqcl - - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at * Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - * Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only * applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for * designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK) #define DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK (0x80000000U) #define DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT (31U) /*! dis_auto_zq - - 1 - Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register * DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 - * Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. */ #define DDRC_ZQCTL0_SHADOW_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK) /*! @} */ /*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */ /*! @{ */ #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK (0x3FU) #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT (0U) /*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable * (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY * specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be * necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for * the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY * clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr. */ #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK) #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK (0x3F00U) #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT (8U) /*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to * when the associated write data is driven on the dfi_wrdata signal. This corresponds to the * DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max * supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on * DFITMG0.dfi_wrdata_use_sdr. */ #define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK) #define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK (0x8000U) #define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT (15U) /*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using * HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat * is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in * DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of * HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification * for correct value. */ #define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK) #define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK (0x7F0000U) #define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT (16U) /*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the * assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds * to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it * may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to * compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or * DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr. */ #define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK) #define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK (0x800000U) #define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT (23U) /*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated * using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in * DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI * clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct * value. */ #define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK) #define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK (0x1F000000U) #define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT (24U) /*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion * of the DFI control signals that the control signals at the PHY-DRAM interface reflect the * assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing * parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it * is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms * of DFI clock. */ #define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK) /*! @} */ /*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */ /*! @{ */ #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK (0x1FU) #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT (0U) /*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the * dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the * DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not * phase aligned, this timing parameter should be rounded up to the next integer value. */ #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK) #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK (0x1F00U) #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT (8U) /*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the * dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM * boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, * this timing parameter should be rounded up to the next integer value. */ #define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK) #define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK (0x1F0000U) #define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT (16U) /*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en * signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. * This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for * correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI * 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be * programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 * and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: * Clocks */ #define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK) #define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK (0x3000000U) #define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT (24U) /*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is * asserted and when the associated dfi_parity_in signal is driven. */ #define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK) #define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK (0xF0000000U) #define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT (28U) /*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is * asserted and when the associated command is driven. This field is used for CAL mode, should be * set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY * can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 */ #define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK) /*! @} */ /*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */ /*! @{ */ #define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK (0x3FU) #define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT (0U) /*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the * DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds * to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. */ #define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK) #define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK (0x7F00U) #define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT (8U) /*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI * control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds * to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. */ #define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK) /*! @} */ /*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */ /*! @{ */ #define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK (0x1FU) #define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT (0U) /*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being * ready to receive commands. Refer to PHY specification for correct value. When the controller is * operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to * the next integer value. Unit: Clocks */ #define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK) /*! @} */ /*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */ /*! @{ */ #define DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK (0x7CU) #define DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT (2U) /*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT * values associated with that command. ODT setting must remain constant for the entire time that * DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 * (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL - * CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL * mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write * preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does * not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) */ #define DDRC_ODTCFG_SHADOW_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK) #define DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK (0xF00U) #define DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT (8U) /*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value * is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not * DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK * write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - * RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK) */ #define DDRC_ODTCFG_SHADOW_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK) #define DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK (0x1F0000U) #define DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT (16U) /*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT * values associated with that command. ODT setting must remain constant for the entire time that * DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + * AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT * for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: * - WL - 1 - RU(tODTon(max)/tCK)) */ #define DDRC_ODTCFG_SHADOW_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK) #define DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK (0xF000000U) #define DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT (24U) /*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value * is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) * - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: * 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) * CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) */ #define DDRC_ODTCFG_SHADOW_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK) /*! @} */ /*! * @} */ /* end of group DDRC_Register_Masks */ /* DDRC - Peripheral instance base addresses */ /** Peripheral DRC__DDRC base address */ #define DRC__DDRC_BASE (0x5C000000u) /** Peripheral DRC__DDRC base pointer */ #define DRC__DDRC ((DDRC_Type *)DRC__DDRC_BASE) /** Array initializer of DDRC peripheral base addresses */ #define DDRC_BASE_ADDRS { DRC__DDRC_BASE } /** Array initializer of DDRC peripheral base pointers */ #define DDRC_BASE_PTRS { DRC__DDRC } /*! * @} */ /* end of group DDRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DDRPHY Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DDRPHY_Peripheral_Access_Layer DDRPHY Peripheral Access Layer * @{ */ /** DDRPHY - Register Layout Typedef */ typedef struct { __I uint32_t RIDR; /**< Revision Identification Register, offset: 0x0 */ __IO uint32_t PIR; /**< PHY Initialization Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t PGCR0; /**< PHY General Configuration Register 0, offset: 0x10 */ __IO uint32_t PGCR1; /**< PHY General Configuration Register 1, offset: 0x14 */ __IO uint32_t PGCR2; /**< PHY General Configuration Register 2, offset: 0x18 */ __IO uint32_t PGCR3; /**< PHY General Configuration Register 3, offset: 0x1C */ __IO uint32_t PGCR4; /**< PHY General Configuration Register 4, offset: 0x20 */ __IO uint32_t PGCR5; /**< PHY General Configuration Register 5, offset: 0x24 */ __IO uint32_t PGCR6; /**< PHY General Configuration Register 6, offset: 0x28 */ __IO uint32_t PGCR7; /**< PHY General Configuration Register 7, offset: 0x2C */ __I uint32_t PGSR0; /**< PHY General Status Register 0, offset: 0x30 */ __I uint32_t PGSR1; /**< PHY General Status Register 1, offset: 0x34 */ __I uint32_t PGSR2; /**< PHY General Status Register 2, offset: 0x38 */ uint8_t RESERVED_1[4]; __IO uint32_t PTR0; /**< PHY Timing Register 0, offset: 0x40 */ __IO uint32_t PTR1; /**< PHY Timing Register 1, offset: 0x44 */ __IO uint32_t PTR2; /**< PHY Timing Register 2, offset: 0x48 */ __IO uint32_t PTR3; /**< PHY Timing Register 3, offset: 0x4C */ __IO uint32_t PTR4; /**< PHY Timing Register 4, offset: 0x50 */ __IO uint32_t PTR5; /**< PHY Timing Register 5, offset: 0x54 */ __IO uint32_t PTR6; /**< PHY Timing Register 6, offset: 0x58 */ uint8_t RESERVED_2[12]; __IO uint32_t PLLCR0; /**< PLL Control Register 0 (Type B PLL Only), offset: 0x68 */ __IO uint32_t PLLCR1; /**< PLL Control Register 1 (Type B PLL Only), offset: 0x6C */ __IO uint32_t PLLCR2; /**< PLL Control Register 2 (Type B PLL Only), offset: 0x70 */ __IO uint32_t PLLCR3; /**< PLL Control Register 3 (Type B PLL Only), offset: 0x74 */ __IO uint32_t PLLCR4; /**< PLL Control Register 4 (Type B PLL Only), offset: 0x78 */ __IO uint32_t PLLCR5; /**< PLL Control Register 5 (Type B PLL Only), offset: 0x7C */ uint8_t RESERVED_3[8]; __IO uint32_t DXCCR; /**< DATX8 Common Configuration Register, offset: 0x88 */ uint8_t RESERVED_4[4]; __IO uint32_t DSGCR; /**< DDR System General Configuration Register, offset: 0x90 */ uint8_t RESERVED_5[4]; __IO uint32_t ODTCR; /**< ODT Configuration Register, offset: 0x98 */ uint8_t RESERVED_6[4]; __IO uint32_t AACR; /**< Anti-Aging Control Register, offset: 0xA0 */ uint8_t RESERVED_7[28]; __IO uint32_t GPR0; /**< General Purpose Register 0, offset: 0xC0 */ __IO uint32_t GPR1; /**< General Purpose Register 1, offset: 0xC4 */ uint8_t RESERVED_8[56]; __IO uint32_t DCR; /**< DRAM Configuration Register, offset: 0x100 */ uint8_t RESERVED_9[12]; __IO uint32_t DTPR0; /**< DRAM Timing Parameters Register 0, offset: 0x110 */ __IO uint32_t DTPR1; /**< DRAM Timing Parameters Register 1, offset: 0x114 */ __IO uint32_t DTPR2; /**< DRAM Timing Parameters Register 2, offset: 0x118 */ __IO uint32_t DTPR3; /**< DRAM Timing Parameters Register 3, offset: 0x11C */ __IO uint32_t DTPR4; /**< DRAM Timing Parameters Register 4, offset: 0x120 */ __IO uint32_t DTPR5; /**< DRAM Timing Parameters Register 5, offset: 0x124 */ __IO uint32_t DTPR6; /**< DRAM Timing Parameters Register 6, offset: 0x128 */ uint8_t RESERVED_10[20]; __IO uint32_t RDIMMGCR0; /**< RDIMM General Configuration Register 0, offset: 0x140 */ __IO uint32_t RDIMMGCR1; /**< RDIMM General Configuration Register 1, offset: 0x144 */ __IO uint32_t RDIMMGCR2; /**< RDIMM General Configuration Register 2, offset: 0x148 */ uint8_t RESERVED_11[4]; __IO uint32_t RDIMMCR0; /**< RDIMM Control Register 0, offset: 0x150 */ __IO uint32_t RDIMMCR1; /**< RDIMM Control Register 1, offset: 0x154 */ __IO uint32_t RDIMMCR2; /**< RDIMM Control Register 2, offset: 0x158 */ __IO uint32_t RDIMMCR3; /**< RDIMM Control Register 3, offset: 0x15C */ __IO uint32_t RDIMMCR4; /**< RDIMM Control Register 4, offset: 0x160 */ uint8_t RESERVED_12[4]; __IO uint32_t SCHCR0; /**< Scheduler Command Register 0, offset: 0x168 */ __IO uint32_t SCHCR1; /**< Scheduler Command Register 1, offset: 0x16C */ uint8_t RESERVED_13[16]; __IO uint32_t MR0; /**< LPDDR4 Mode Register 0, offset: 0x180 */ __IO uint32_t MR1; /**< LPDDR4 Mode Register 1, offset: 0x184 */ __IO uint32_t MR2; /**< LPDDR4 Mode Register 2, offset: 0x188 */ __IO uint32_t MR3; /**< LPDDR4 Mode Register 3, offset: 0x18C */ __IO uint32_t MR4; /**< LPDDR4 Mode Register 4, offset: 0x190 */ __IO uint32_t MR5; /**< LPDDR4 Mode Register 5, offset: 0x194 */ __IO uint32_t MR6; /**< LPDDR4 Mode Register 6, offset: 0x198 */ __IO uint32_t MR7; /**< LPDDR4 Mode Register 7, offset: 0x19C */ uint8_t RESERVED_14[12]; __IO uint32_t MR11; /**< LPDDR4 Mode Register 11, offset: 0x1AC */ __IO uint32_t MR12; /**< LPDDR4 Mode Register 12, offset: 0x1B0 */ __IO uint32_t MR13; /**< LPDDR4 Mode Register 13, offset: 0x1B4 */ __IO uint32_t MR14; /**< LPDDR4 Mode Register 14, offset: 0x1B8 */ uint8_t RESERVED_15[28]; __IO uint32_t MR22; /**< LPDDR4 Mode Register 22, offset: 0x1D8 */ uint8_t RESERVED_16[36]; __IO uint32_t DTCR0; /**< Data Training Configuration Register 0, offset: 0x200 */ __IO uint32_t DTCR1; /**< Data Training Configuration Register 1, offset: 0x204 */ __IO uint32_t DTAR0; /**< Data Training Address Register 0, offset: 0x208 */ __IO uint32_t DTAR1; /**< Data Training Address Register 1, offset: 0x20C */ __IO uint32_t DTAR2; /**< Data Training Address Register 2, offset: 0x210 */ uint8_t RESERVED_17[4]; __IO uint32_t DTDR0; /**< Data Training Data Register 0, offset: 0x218 */ __IO uint32_t DTDR1; /**< Data Training Data Register 1, offset: 0x21C */ uint8_t RESERVED_18[16]; __I uint32_t DTEDR0; /**< Data Training Eye Data Register 0, offset: 0x230 */ __I uint32_t DTEDR1; /**< Data Training Eye Data Register 1, offset: 0x234 */ __I uint32_t DTEDR2; /**< Data Training Eye Data Register 2, offset: 0x238 */ __I uint32_t VTDR; /**< VREF Training Data Register, offset: 0x23C */ __IO uint32_t CATR0; /**< CA Training Register 0, offset: 0x240 */ __IO uint32_t CATR1; /**< CA Training Register 1, offset: 0x244 */ __IO uint32_t PGCR8; /**< PHY General Configuration Register 8, offset: 0x248 */ uint8_t RESERVED_19[4]; __IO uint32_t DQSDR0; /**< DQS Drift Register 0, offset: 0x250 */ __IO uint32_t DQSDR1; /**< DQS Drift Register 1, offset: 0x254 */ __IO uint32_t DQSDR2; /**< DQS Drift Register 2, offset: 0x258 */ uint8_t RESERVED_20[164]; __IO uint32_t DCUAR; /**< DCU Address Register, offset: 0x300 */ __IO uint32_t DCUDR; /**< DCU Data Register, offset: 0x304 */ __IO uint32_t DCURR; /**< DCU Run Register, offset: 0x308 */ __IO uint32_t DCULR; /**< DCU Loop Register, offset: 0x30C */ __IO uint32_t DCUGCR; /**< DCU General Configuration Register, offset: 0x310 */ __IO uint32_t DCUTPR; /**< DCU Timing Parameters Register, offset: 0x314 */ __I uint32_t DCUSR0; /**< DCU Status Register 0, offset: 0x318 */ __I uint32_t DCUSR1; /**< DCU Status Register 1, offset: 0x31C */ uint8_t RESERVED_21[224]; __IO uint32_t BISTRR; /**< BIST Run Register, offset: 0x400 */ __IO uint32_t BISTWCR; /**< BIST Word Count Register, offset: 0x404 */ __IO uint32_t BISTMSKR0; /**< BIST Mask Register 0, offset: 0x408 */ __IO uint32_t BISTMSKR1; /**< BIST Mask Register 1, offset: 0x40C */ __IO uint32_t BISTMSKR2; /**< BIST Mask Register 2, offset: 0x410 */ __IO uint32_t BISTLSR; /**< BIST LFSR Seed Register, offset: 0x414 */ __IO uint32_t BISTAR0; /**< BIST Address Register 0, offset: 0x418 */ __IO uint32_t BISTAR1; /**< BIST Address Register 1, offset: 0x41C */ __IO uint32_t BISTAR2; /**< BIST Address Register 2, offset: 0x420 */ __IO uint32_t BISTAR3; /**< BIST Address Register 3, offset: 0x424 */ __IO uint32_t BISTAR4; /**< BIST Address Register 4, offset: 0x428 */ __IO uint32_t BISTUDPR; /**< BIST User Data Pattern Register, offset: 0x42C */ __I uint32_t BISTGSR; /**< BIST General Status Register, offset: 0x430 */ __I uint32_t BISTWER0; /**< BIST Word Error Register 0, offset: 0x434 */ __I uint32_t BISTWER1; /**< BIST Word Error Register 1, offset: 0x438 */ __I uint32_t BISTBER0; /**< BIST Bit Error Register 0, offset: 0x43C */ __I uint32_t BISTBER1; /**< BIST Bit Error Register 1, offset: 0x440 */ __I uint32_t BISTBER2; /**< BIST Bit Error Register 2, offset: 0x444 */ __I uint32_t BISTBER3; /**< BIST Bit Error Register 3, offset: 0x448 */ __I uint32_t BISTBER4; /**< BIST Bit Error Register 4, offset: 0x44C */ __I uint32_t BISTWCSR; /**< BIST Word Count Status Register, offset: 0x450 */ __I uint32_t BISTFWR0; /**< BIST Fail Word Register 0, offset: 0x454 */ __I uint32_t BISTFWR1; /**< BIST Fail Word Register 1, offset: 0x458 */ __I uint32_t BISTFWR2; /**< BIST Fail Word Register 2, offset: 0x45C */ __I uint32_t BISTBER5; /**< BIST Bit Error Register 5, offset: 0x460 */ uint8_t RESERVED_22[120]; __IO uint32_t RANKIDR; /**< Rank ID Register, offset: 0x4DC */ __I uint32_t RIOCR0; /**< Rank I/O Configuration Register 0, offset: 0x4E0 */ __I uint32_t RIOCR1; /**< Rank I/O Configuration Register 1, offset: 0x4E4 */ __IO uint32_t RIOCR2; /**< Rank I/O Configuration Register 2, offset: 0x4E8 */ __I uint32_t RIOCR3; /**< Rank I/O Configuration Register 3, offset: 0x4EC */ __IO uint32_t RIOCR4; /**< Rank I/O Configuration Register 4, offset: 0x4F0 */ __IO uint32_t RIOCR5; /**< Rank I/O Configuration Register 5, offset: 0x4F4 */ uint8_t RESERVED_23[8]; __IO uint32_t ACIOCR0; /**< AC I/O Configuration Register 0, offset: 0x500 */ __IO uint32_t ACIOCR1; /**< AC I/O Configuration Register 1, offset: 0x504 */ __IO uint32_t ACIOCR2; /**< AC I/O Configuration Register 2, offset: 0x508 */ __IO uint32_t ACIOCR3; /**< AC I/O Configuration Register 3, offset: 0x50C */ __IO uint32_t ACIOCR4; /**< AC I/O Configuration Register 4, offset: 0x510 */ __IO uint32_t ACIOCR5; /**< AC I/O Configuration Register 5, offset: 0x514 */ uint8_t RESERVED_24[8]; __IO uint32_t IOVCR0; /**< IO VREF Control Register 0, offset: 0x520 */ __I uint32_t IOVCR1; /**< IO VREF Control Register 1, offset: 0x524 */ __IO uint32_t VTCR0; /**< VREF Training Control Register 0, offset: 0x528 */ __IO uint32_t VTCR1; /**< VREF Training Control Register 1, offset: 0x52C */ uint8_t RESERVED_25[16]; __IO uint32_t ACBDLR0; /**< AC Bit Delay Line Register 0, offset: 0x540 */ __IO uint32_t ACBDLR1; /**< AC Bit Delay Line Register 1, offset: 0x544 */ __IO uint32_t ACBDLR2; /**< AC Bit Delay Line Register 2, offset: 0x548 */ __IO uint32_t ACBDLR3; /**< AC Bit Delay Line Register 3, offset: 0x54C */ __IO uint32_t ACBDLR4; /**< AC Bit Delay Line Register 4, offset: 0x550 */ __IO uint32_t ACBDLR5; /**< AC Bit Delay Line Register 5, offset: 0x554 */ __IO uint32_t ACBDLR6; /**< AC Bit Delay Line Register 6, offset: 0x558 */ __IO uint32_t ACBDLR7; /**< AC Bit Delay Line Register 7, offset: 0x55C */ __IO uint32_t ACBDLR8; /**< AC Bit Delay Line Register 8, offset: 0x560 */ __IO uint32_t ACBDLR9; /**< AC Bit Delay Line Register 9, offset: 0x564 */ __IO uint32_t ACBDLR10; /**< AC Bit Delay Line Register 10, offset: 0x568 */ __I uint32_t ACBDLR11; /**< AC Bit Delay Line Register 11, offset: 0x56C */ __I uint32_t ACBDLR12; /**< AC Bit Delay Line Register 12, offset: 0x570 */ __I uint32_t ACBDLR13; /**< AC Bit Delay Line Register 13, offset: 0x574 */ __I uint32_t ACBDLR14; /**< AC Bit Delay Line Register 14, offset: 0x578 */ __IO uint32_t ACBDLR15; /**< AC Bit Delay Line Register 15, offset: 0x57C */ __IO uint32_t ACBDLR16; /**< AC Bit Delay Line Register 16, offset: 0x580 */ __IO uint32_t ACLCDLR; /**< AC Local Calibrated Delay Line Register, offset: 0x584 */ uint8_t RESERVED_26[24]; __IO uint32_t ACMDLR0; /**< AC Master Delay Line Register 0, offset: 0x5A0 */ __IO uint32_t ACMDLR1; /**< AC Master Delay Line Register 1, offset: 0x5A4 */ uint8_t RESERVED_27[216]; __IO uint32_t ZQCR; /**< ZQ Impedance Control Register, offset: 0x680 */ __IO uint32_t ZQ0PR0; /**< ZQ n Impedance Control Program Register 0, offset: 0x684 */ __IO uint32_t ZQ0PR1; /**< ZQ n Impedance Control Program Register 1, offset: 0x688 */ __I uint32_t ZQ0DR0; /**< ZQ n Impedance Control Data Register 0, offset: 0x68C */ __I uint32_t ZQ0DR1; /**< ZQ n Impedance Control Data Register 1, offset: 0x690 */ __IO uint32_t ZQ0OR0; /**< ZQ n Impedance Control Override Data Register 0, offset: 0x694 */ __IO uint32_t ZQ0OR1; /**< ZQ n Impedance Control Override Data Register 1, offset: 0x698 */ __I uint32_t ZQ0SR; /**< ZQ n Impedance Control Status Register, offset: 0x69C */ uint8_t RESERVED_28[4]; __IO uint32_t ZQ1PR0; /**< ZQ n Impedance Control Program Register 0, offset: 0x6A4 */ __IO uint32_t ZQ1PR1; /**< ZQ n Impedance Control Program Register 1, offset: 0x6A8 */ __I uint32_t ZQ1DR0; /**< ZQ n Impedance Control Data Register 0, offset: 0x6AC */ __I uint32_t ZQ1DR1; /**< ZQ n Impedance Control Data Register 1, offset: 0x6B0 */ __IO uint32_t ZQ1OR0; /**< ZQ n Impedance Control Override Data Register 0, offset: 0x6B4 */ __IO uint32_t ZQ1OR1; /**< ZQ n Impedance Control Override Data Register 1, offset: 0x6B8 */ __I uint32_t ZQ1SR; /**< ZQ n Impedance Control Status Register, offset: 0x6BC */ uint8_t RESERVED_29[4]; __IO uint32_t ZQ2PR0; /**< ZQ n Impedance Control Program Register 0, offset: 0x6C4 */ __IO uint32_t ZQ2PR1; /**< ZQ n Impedance Control Program Register 1, offset: 0x6C8 */ __I uint32_t ZQ2DR0; /**< ZQ n Impedance Control Data Register 0, offset: 0x6CC */ __I uint32_t ZQ2DR1; /**< ZQ n Impedance Control Data Register 1, offset: 0x6D0 */ __IO uint32_t ZQ2OR0; /**< ZQ n Impedance Control Override Data Register 0, offset: 0x6D4 */ __IO uint32_t ZQ2OR1; /**< ZQ n Impedance Control Override Data Register 1, offset: 0x6D8 */ __I uint32_t ZQ2SR; /**< ZQ n Impedance Control Status Register, offset: 0x6DC */ uint8_t RESERVED_30[4]; __I uint32_t ZQ3PR0; /**< ZQ n Impedance Control Program Register 0, offset: 0x6E4 */ __I uint32_t ZQ3PR1; /**< ZQ n Impedance Control Program Register 1, offset: 0x6E8 */ __I uint32_t ZQ3DR0; /**< ZQ n Impedance Control Data Register 0, offset: 0x6EC */ __I uint32_t ZQ3DR1; /**< ZQ n Impedance Control Data Register 1, offset: 0x6F0 */ __I uint32_t ZQ3OR0; /**< ZQ n Impedance Control Override Data Register 0, offset: 0x6F4 */ __I uint32_t ZQ3OR1; /**< ZQ n Impedance Control Override Data Register 1, offset: 0x6F8 */ __I uint32_t ZQ3SR; /**< ZQ n Impedance Control Status Register, offset: 0x6FC */ __IO uint32_t DX0GCR0; /**< DATX8 n General Configuration Register 0, offset: 0x700 */ __IO uint32_t DX0GCR1; /**< DATX8 n General Configuration Register 1, offset: 0x704 */ __IO uint32_t DX0GCR2; /**< DATX8 n General Configuration Register 2, offset: 0x708 */ __IO uint32_t DX0GCR3; /**< DATX8 n General Configuration Register 3, offset: 0x70C */ __IO uint32_t DX0GCR4; /**< DATX8 n General Configuration Register 4, offset: 0x710 */ __IO uint32_t DX0GCR5; /**< DATX8 n General Configuration Register 5, offset: 0x714 */ __IO uint32_t DX0GCR6; /**< DATX8 n General Configuration Register 6, offset: 0x718 */ __IO uint32_t DX0GCR7; /**< DATX8 n General Configuration Register 7, offset: 0x71C */ __I uint32_t DX0GCR8; /**< DATX8 n General Configuration Register 8, offset: 0x720 */ __I uint32_t DX0GCR9; /**< DATX8 n General Configuration Register 9, offset: 0x724 */ __IO uint32_t DX0DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0x728 */ __IO uint32_t DX0DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0x72C */ uint8_t RESERVED_31[16]; __IO uint32_t DX0BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0x740 */ __IO uint32_t DX0BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0x744 */ __IO uint32_t DX0BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0x748 */ uint8_t RESERVED_32[4]; __IO uint32_t DX0BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0x750 */ __IO uint32_t DX0BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0x754 */ __IO uint32_t DX0BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0x758 */ uint8_t RESERVED_33[4]; __IO uint32_t DX0BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0x760 */ __I uint32_t DX0BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0x764 */ __I uint32_t DX0BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0x768 */ __I uint32_t DX0BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0x76C */ uint8_t RESERVED_34[16]; __IO uint32_t DX0LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0x780 */ __IO uint32_t DX0LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0x784 */ __IO uint32_t DX0LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0x788 */ __IO uint32_t DX0LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0x78C */ __IO uint32_t DX0LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0x790 */ __IO uint32_t DX0LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0x794 */ uint8_t RESERVED_35[8]; __IO uint32_t DX0MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0x7A0 */ __IO uint32_t DX0MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0x7A4 */ uint8_t RESERVED_36[24]; __IO uint32_t DX0GTR0; /**< DATX8 n General Timing Register 0, offset: 0x7C0 */ uint8_t RESERVED_37[12]; __I uint32_t DX0RSR0; /**< DATX8 n Rank Status Register 0, offset: 0x7D0 */ __I uint32_t DX0RSR1; /**< DATX8 n Rank Status Register 1, offset: 0x7D4 */ __I uint32_t DX0RSR2; /**< DATX8 n Rank Status Register 2, offset: 0x7D8 */ __I uint32_t DX0RSR3; /**< DATX8 n Rank Status Register 3, offset: 0x7DC */ __I uint32_t DX0GSR0; /**< DATX8 n General Status Register 0, offset: 0x7E0 */ __I uint32_t DX0GSR1; /**< DATX8 n General Status Register 1, offset: 0x7E4 */ __I uint32_t DX0GSR2; /**< DATX8 n General Status Register 2, offset: 0x7E8 */ __I uint32_t DX0GSR3; /**< DATX8 n General Status Register 3, offset: 0x7EC */ __I uint32_t DX0GSR4; /**< DATX8 n General Status Register 4, offset: 0x7F0 */ __I uint32_t DX0GSR5; /**< DATX8 n General Status Register 5, offset: 0x7F4 */ __I uint32_t DX0GSR6; /**< DATX8 n General Status Register 6, offset: 0x7F8 */ uint8_t RESERVED_38[4]; __IO uint32_t DX1GCR0; /**< DATX8 n General Configuration Register 0, offset: 0x800 */ __IO uint32_t DX1GCR1; /**< DATX8 n General Configuration Register 1, offset: 0x804 */ __IO uint32_t DX1GCR2; /**< DATX8 n General Configuration Register 2, offset: 0x808 */ __IO uint32_t DX1GCR3; /**< DATX8 n General Configuration Register 3, offset: 0x80C */ __IO uint32_t DX1GCR4; /**< DATX8 n General Configuration Register 4, offset: 0x810 */ __IO uint32_t DX1GCR5; /**< DATX8 n General Configuration Register 5, offset: 0x814 */ __IO uint32_t DX1GCR6; /**< DATX8 n General Configuration Register 6, offset: 0x818 */ __IO uint32_t DX1GCR7; /**< DATX8 n General Configuration Register 7, offset: 0x81C */ __I uint32_t DX1GCR8; /**< DATX8 n General Configuration Register 8, offset: 0x820 */ __I uint32_t DX1GCR9; /**< DATX8 n General Configuration Register 9, offset: 0x824 */ __IO uint32_t DX1DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0x828 */ __IO uint32_t DX1DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0x82C */ uint8_t RESERVED_39[16]; __IO uint32_t DX1BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0x840 */ __IO uint32_t DX1BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0x844 */ __IO uint32_t DX1BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0x848 */ uint8_t RESERVED_40[4]; __IO uint32_t DX1BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0x850 */ __IO uint32_t DX1BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0x854 */ __IO uint32_t DX1BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0x858 */ uint8_t RESERVED_41[4]; __IO uint32_t DX1BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0x860 */ __I uint32_t DX1BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0x864 */ __I uint32_t DX1BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0x868 */ __I uint32_t DX1BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0x86C */ uint8_t RESERVED_42[16]; __IO uint32_t DX1LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0x880 */ __IO uint32_t DX1LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0x884 */ __IO uint32_t DX1LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0x888 */ __IO uint32_t DX1LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0x88C */ __IO uint32_t DX1LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0x890 */ __IO uint32_t DX1LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0x894 */ uint8_t RESERVED_43[8]; __IO uint32_t DX1MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0x8A0 */ __IO uint32_t DX1MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0x8A4 */ uint8_t RESERVED_44[24]; __IO uint32_t DX1GTR0; /**< DATX8 n General Timing Register 0, offset: 0x8C0 */ uint8_t RESERVED_45[12]; __I uint32_t DX1RSR0; /**< DATX8 n Rank Status Register 0, offset: 0x8D0 */ __I uint32_t DX1RSR1; /**< DATX8 n Rank Status Register 1, offset: 0x8D4 */ __I uint32_t DX1RSR2; /**< DATX8 n Rank Status Register 2, offset: 0x8D8 */ __I uint32_t DX1RSR3; /**< DATX8 n Rank Status Register 3, offset: 0x8DC */ __I uint32_t DX1GSR0; /**< DATX8 n General Status Register 0, offset: 0x8E0 */ __I uint32_t DX1GSR1; /**< DATX8 n General Status Register 1, offset: 0x8E4 */ __I uint32_t DX1GSR2; /**< DATX8 n General Status Register 2, offset: 0x8E8 */ __I uint32_t DX1GSR3; /**< DATX8 n General Status Register 3, offset: 0x8EC */ __I uint32_t DX1GSR4; /**< DATX8 n General Status Register 4, offset: 0x8F0 */ __I uint32_t DX1GSR5; /**< DATX8 n General Status Register 5, offset: 0x8F4 */ __I uint32_t DX1GSR6; /**< DATX8 n General Status Register 6, offset: 0x8F8 */ uint8_t RESERVED_46[4]; __IO uint32_t DX2GCR0; /**< DATX8 n General Configuration Register 0, offset: 0x900 */ __IO uint32_t DX2GCR1; /**< DATX8 n General Configuration Register 1, offset: 0x904 */ __IO uint32_t DX2GCR2; /**< DATX8 n General Configuration Register 2, offset: 0x908 */ __IO uint32_t DX2GCR3; /**< DATX8 n General Configuration Register 3, offset: 0x90C */ __IO uint32_t DX2GCR4; /**< DATX8 n General Configuration Register 4, offset: 0x910 */ __IO uint32_t DX2GCR5; /**< DATX8 n General Configuration Register 5, offset: 0x914 */ __IO uint32_t DX2GCR6; /**< DATX8 n General Configuration Register 6, offset: 0x918 */ __IO uint32_t DX2GCR7; /**< DATX8 n General Configuration Register 7, offset: 0x91C */ __I uint32_t DX2GCR8; /**< DATX8 n General Configuration Register 8, offset: 0x920 */ __I uint32_t DX2GCR9; /**< DATX8 n General Configuration Register 9, offset: 0x924 */ __IO uint32_t DX2DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0x928 */ __IO uint32_t DX2DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0x92C */ uint8_t RESERVED_47[16]; __IO uint32_t DX2BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0x940 */ __IO uint32_t DX2BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0x944 */ __IO uint32_t DX2BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0x948 */ uint8_t RESERVED_48[4]; __IO uint32_t DX2BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0x950 */ __IO uint32_t DX2BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0x954 */ __IO uint32_t DX2BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0x958 */ uint8_t RESERVED_49[4]; __IO uint32_t DX2BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0x960 */ __I uint32_t DX2BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0x964 */ __I uint32_t DX2BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0x968 */ __I uint32_t DX2BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0x96C */ uint8_t RESERVED_50[16]; __IO uint32_t DX2LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0x980 */ __IO uint32_t DX2LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0x984 */ __IO uint32_t DX2LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0x988 */ __IO uint32_t DX2LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0x98C */ __IO uint32_t DX2LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0x990 */ __IO uint32_t DX2LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0x994 */ uint8_t RESERVED_51[8]; __IO uint32_t DX2MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0x9A0 */ __IO uint32_t DX2MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0x9A4 */ uint8_t RESERVED_52[24]; __IO uint32_t DX2GTR0; /**< DATX8 n General Timing Register 0, offset: 0x9C0 */ uint8_t RESERVED_53[12]; __I uint32_t DX2RSR0; /**< DATX8 n Rank Status Register 0, offset: 0x9D0 */ __I uint32_t DX2RSR1; /**< DATX8 n Rank Status Register 1, offset: 0x9D4 */ __I uint32_t DX2RSR2; /**< DATX8 n Rank Status Register 2, offset: 0x9D8 */ __I uint32_t DX2RSR3; /**< DATX8 n Rank Status Register 3, offset: 0x9DC */ __I uint32_t DX2GSR0; /**< DATX8 n General Status Register 0, offset: 0x9E0 */ __I uint32_t DX2GSR1; /**< DATX8 n General Status Register 1, offset: 0x9E4 */ __I uint32_t DX2GSR2; /**< DATX8 n General Status Register 2, offset: 0x9E8 */ __I uint32_t DX2GSR3; /**< DATX8 n General Status Register 3, offset: 0x9EC */ __I uint32_t DX2GSR4; /**< DATX8 n General Status Register 4, offset: 0x9F0 */ __I uint32_t DX2GSR5; /**< DATX8 n General Status Register 5, offset: 0x9F4 */ __I uint32_t DX2GSR6; /**< DATX8 n General Status Register 6, offset: 0x9F8 */ uint8_t RESERVED_54[4]; __IO uint32_t DX3GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xA00 */ __IO uint32_t DX3GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xA04 */ __IO uint32_t DX3GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xA08 */ __IO uint32_t DX3GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xA0C */ __IO uint32_t DX3GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xA10 */ __IO uint32_t DX3GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xA14 */ __IO uint32_t DX3GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xA18 */ __IO uint32_t DX3GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xA1C */ __I uint32_t DX3GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xA20 */ __I uint32_t DX3GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xA24 */ __IO uint32_t DX3DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xA28 */ __IO uint32_t DX3DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xA2C */ uint8_t RESERVED_55[16]; __IO uint32_t DX3BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xA40 */ __IO uint32_t DX3BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xA44 */ __IO uint32_t DX3BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xA48 */ uint8_t RESERVED_56[4]; __IO uint32_t DX3BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xA50 */ __IO uint32_t DX3BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xA54 */ __IO uint32_t DX3BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xA58 */ uint8_t RESERVED_57[4]; __IO uint32_t DX3BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xA60 */ __I uint32_t DX3BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xA64 */ __I uint32_t DX3BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xA68 */ __I uint32_t DX3BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xA6C */ uint8_t RESERVED_58[16]; __IO uint32_t DX3LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xA80 */ __IO uint32_t DX3LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xA84 */ __IO uint32_t DX3LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xA88 */ __IO uint32_t DX3LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xA8C */ __IO uint32_t DX3LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xA90 */ __IO uint32_t DX3LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xA94 */ uint8_t RESERVED_59[8]; __IO uint32_t DX3MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xAA0 */ __IO uint32_t DX3MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xAA4 */ uint8_t RESERVED_60[24]; __IO uint32_t DX3GTR0; /**< DATX8 n General Timing Register 0, offset: 0xAC0 */ uint8_t RESERVED_61[12]; __I uint32_t DX3RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xAD0 */ __I uint32_t DX3RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xAD4 */ __I uint32_t DX3RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xAD8 */ __I uint32_t DX3RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xADC */ __I uint32_t DX3GSR0; /**< DATX8 n General Status Register 0, offset: 0xAE0 */ __I uint32_t DX3GSR1; /**< DATX8 n General Status Register 1, offset: 0xAE4 */ __I uint32_t DX3GSR2; /**< DATX8 n General Status Register 2, offset: 0xAE8 */ __I uint32_t DX3GSR3; /**< DATX8 n General Status Register 3, offset: 0xAEC */ __I uint32_t DX3GSR4; /**< DATX8 n General Status Register 4, offset: 0xAF0 */ __I uint32_t DX3GSR5; /**< DATX8 n General Status Register 5, offset: 0xAF4 */ __I uint32_t DX3GSR6; /**< DATX8 n General Status Register 6, offset: 0xAF8 */ uint8_t RESERVED_62[4]; __I uint32_t DX4GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xB00 */ __I uint32_t DX4GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xB04 */ __I uint32_t DX4GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xB08 */ __I uint32_t DX4GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xB0C */ __I uint32_t DX4GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xB10 */ __I uint32_t DX4GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xB14 */ __I uint32_t DX4GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xB18 */ __I uint32_t DX4GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xB1C */ __I uint32_t DX4GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xB20 */ __I uint32_t DX4GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xB24 */ __I uint32_t DX4DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xB28 */ __I uint32_t DX4DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xB2C */ uint8_t RESERVED_63[16]; __I uint32_t DX4BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xB40 */ __I uint32_t DX4BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xB44 */ __I uint32_t DX4BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xB48 */ uint8_t RESERVED_64[4]; __I uint32_t DX4BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xB50 */ __I uint32_t DX4BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xB54 */ __I uint32_t DX4BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xB58 */ uint8_t RESERVED_65[4]; __I uint32_t DX4BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xB60 */ __I uint32_t DX4BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xB64 */ __I uint32_t DX4BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xB68 */ __I uint32_t DX4BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xB6C */ uint8_t RESERVED_66[16]; __I uint32_t DX4LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xB80 */ __I uint32_t DX4LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xB84 */ __I uint32_t DX4LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xB88 */ __I uint32_t DX4LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xB8C */ __I uint32_t DX4LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xB90 */ __I uint32_t DX4LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xB94 */ uint8_t RESERVED_67[8]; __I uint32_t DX4MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xBA0 */ __I uint32_t DX4MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xBA4 */ uint8_t RESERVED_68[24]; __I uint32_t DX4GTR0; /**< DATX8 n General Timing Register 0, offset: 0xBC0 */ uint8_t RESERVED_69[12]; __I uint32_t DX4RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xBD0 */ __I uint32_t DX4RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xBD4 */ __I uint32_t DX4RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xBD8 */ __I uint32_t DX4RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xBDC */ __I uint32_t DX4GSR0; /**< DATX8 n General Status Register 0, offset: 0xBE0 */ __I uint32_t DX4GSR1; /**< DATX8 n General Status Register 1, offset: 0xBE4 */ __I uint32_t DX4GSR2; /**< DATX8 n General Status Register 2, offset: 0xBE8 */ __I uint32_t DX4GSR3; /**< DATX8 n General Status Register 3, offset: 0xBEC */ __I uint32_t DX4GSR4; /**< DATX8 n General Status Register 4, offset: 0xBF0 */ __I uint32_t DX4GSR5; /**< DATX8 n General Status Register 5, offset: 0xBF4 */ __I uint32_t DX4GSR6; /**< DATX8 n General Status Register 6, offset: 0xBF8 */ uint8_t RESERVED_70[4]; __I uint32_t DX5GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xC00 */ __I uint32_t DX5GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xC04 */ __I uint32_t DX5GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xC08 */ __I uint32_t DX5GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xC0C */ __I uint32_t DX5GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xC10 */ __I uint32_t DX5GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xC14 */ __I uint32_t DX5GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xC18 */ __I uint32_t DX5GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xC1C */ __I uint32_t DX5GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xC20 */ __I uint32_t DX5GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xC24 */ __I uint32_t DX5DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xC28 */ __I uint32_t DX5DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xC2C */ uint8_t RESERVED_71[16]; __I uint32_t DX5BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xC40 */ __I uint32_t DX5BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xC44 */ __I uint32_t DX5BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xC48 */ uint8_t RESERVED_72[4]; __I uint32_t DX5BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xC50 */ __I uint32_t DX5BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xC54 */ __I uint32_t DX5BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xC58 */ uint8_t RESERVED_73[4]; __I uint32_t DX5BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xC60 */ __I uint32_t DX5BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xC64 */ __I uint32_t DX5BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xC68 */ __I uint32_t DX5BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xC6C */ uint8_t RESERVED_74[16]; __I uint32_t DX5LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xC80 */ __I uint32_t DX5LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xC84 */ __I uint32_t DX5LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xC88 */ __I uint32_t DX5LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xC8C */ __I uint32_t DX5LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xC90 */ __I uint32_t DX5LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xC94 */ uint8_t RESERVED_75[8]; __I uint32_t DX5MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xCA0 */ __I uint32_t DX5MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xCA4 */ uint8_t RESERVED_76[24]; __I uint32_t DX5GTR0; /**< DATX8 n General Timing Register 0, offset: 0xCC0 */ uint8_t RESERVED_77[12]; __I uint32_t DX5RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xCD0 */ __I uint32_t DX5RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xCD4 */ __I uint32_t DX5RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xCD8 */ __I uint32_t DX5RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xCDC */ __I uint32_t DX5GSR0; /**< DATX8 n General Status Register 0, offset: 0xCE0 */ __I uint32_t DX5GSR1; /**< DATX8 n General Status Register 1, offset: 0xCE4 */ __I uint32_t DX5GSR2; /**< DATX8 n General Status Register 2, offset: 0xCE8 */ __I uint32_t DX5GSR3; /**< DATX8 n General Status Register 3, offset: 0xCEC */ __I uint32_t DX5GSR4; /**< DATX8 n General Status Register 4, offset: 0xCF0 */ __I uint32_t DX5GSR5; /**< DATX8 n General Status Register 5, offset: 0xCF4 */ __I uint32_t DX5GSR6; /**< DATX8 n General Status Register 6, offset: 0xCF8 */ uint8_t RESERVED_78[4]; __I uint32_t DX6GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xD00 */ __I uint32_t DX6GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xD04 */ __I uint32_t DX6GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xD08 */ __I uint32_t DX6GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xD0C */ __I uint32_t DX6GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xD10 */ __I uint32_t DX6GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xD14 */ __I uint32_t DX6GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xD18 */ __I uint32_t DX6GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xD1C */ __I uint32_t DX6GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xD20 */ __I uint32_t DX6GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xD24 */ __I uint32_t DX6DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xD28 */ __I uint32_t DX6DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xD2C */ uint8_t RESERVED_79[16]; __I uint32_t DX6BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xD40 */ __I uint32_t DX6BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xD44 */ __I uint32_t DX6BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xD48 */ uint8_t RESERVED_80[4]; __I uint32_t DX6BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xD50 */ __I uint32_t DX6BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xD54 */ __I uint32_t DX6BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xD58 */ uint8_t RESERVED_81[4]; __I uint32_t DX6BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xD60 */ __I uint32_t DX6BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xD64 */ __I uint32_t DX6BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xD68 */ __I uint32_t DX6BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xD6C */ uint8_t RESERVED_82[16]; __I uint32_t DX6LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xD80 */ __I uint32_t DX6LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xD84 */ __I uint32_t DX6LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xD88 */ __I uint32_t DX6LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xD8C */ __I uint32_t DX6LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xD90 */ __I uint32_t DX6LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xD94 */ uint8_t RESERVED_83[8]; __I uint32_t DX6MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xDA0 */ __I uint32_t DX6MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xDA4 */ uint8_t RESERVED_84[24]; __I uint32_t DX6GTR0; /**< DATX8 n General Timing Register 0, offset: 0xDC0 */ uint8_t RESERVED_85[12]; __I uint32_t DX6RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xDD0 */ __I uint32_t DX6RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xDD4 */ __I uint32_t DX6RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xDD8 */ __I uint32_t DX6RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xDDC */ __I uint32_t DX6GSR0; /**< DATX8 n General Status Register 0, offset: 0xDE0 */ __I uint32_t DX6GSR1; /**< DATX8 n General Status Register 1, offset: 0xDE4 */ __I uint32_t DX6GSR2; /**< DATX8 n General Status Register 2, offset: 0xDE8 */ __I uint32_t DX6GSR3; /**< DATX8 n General Status Register 3, offset: 0xDEC */ __I uint32_t DX6GSR4; /**< DATX8 n General Status Register 4, offset: 0xDF0 */ __I uint32_t DX6GSR5; /**< DATX8 n General Status Register 5, offset: 0xDF4 */ __I uint32_t DX6GSR6; /**< DATX8 n General Status Register 6, offset: 0xDF8 */ uint8_t RESERVED_86[4]; __I uint32_t DX7GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xE00 */ __I uint32_t DX7GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xE04 */ __I uint32_t DX7GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xE08 */ __I uint32_t DX7GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xE0C */ __I uint32_t DX7GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xE10 */ __I uint32_t DX7GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xE14 */ __I uint32_t DX7GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xE18 */ __I uint32_t DX7GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xE1C */ __I uint32_t DX7GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xE20 */ __I uint32_t DX7GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xE24 */ __I uint32_t DX7DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xE28 */ __I uint32_t DX7DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xE2C */ uint8_t RESERVED_87[16]; __I uint32_t DX7BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xE40 */ __I uint32_t DX7BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xE44 */ __I uint32_t DX7BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xE48 */ uint8_t RESERVED_88[4]; __I uint32_t DX7BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xE50 */ __I uint32_t DX7BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xE54 */ __I uint32_t DX7BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xE58 */ uint8_t RESERVED_89[4]; __I uint32_t DX7BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xE60 */ __I uint32_t DX7BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xE64 */ __I uint32_t DX7BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xE68 */ __I uint32_t DX7BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xE6C */ uint8_t RESERVED_90[16]; __I uint32_t DX7LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xE80 */ __I uint32_t DX7LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xE84 */ __I uint32_t DX7LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xE88 */ __I uint32_t DX7LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xE8C */ __I uint32_t DX7LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xE90 */ __I uint32_t DX7LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xE94 */ uint8_t RESERVED_91[8]; __I uint32_t DX7MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xEA0 */ __I uint32_t DX7MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xEA4 */ uint8_t RESERVED_92[24]; __I uint32_t DX7GTR0; /**< DATX8 n General Timing Register 0, offset: 0xEC0 */ uint8_t RESERVED_93[12]; __I uint32_t DX7RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xED0 */ __I uint32_t DX7RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xED4 */ __I uint32_t DX7RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xED8 */ __I uint32_t DX7RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xEDC */ __I uint32_t DX7GSR0; /**< DATX8 n General Status Register 0, offset: 0xEE0 */ __I uint32_t DX7GSR1; /**< DATX8 n General Status Register 1, offset: 0xEE4 */ __I uint32_t DX7GSR2; /**< DATX8 n General Status Register 2, offset: 0xEE8 */ __I uint32_t DX7GSR3; /**< DATX8 n General Status Register 3, offset: 0xEEC */ __I uint32_t DX7GSR4; /**< DATX8 n General Status Register 4, offset: 0xEF0 */ __I uint32_t DX7GSR5; /**< DATX8 n General Status Register 5, offset: 0xEF4 */ __I uint32_t DX7GSR6; /**< DATX8 n General Status Register 6, offset: 0xEF8 */ uint8_t RESERVED_94[4]; __I uint32_t DX8GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xF00 */ __I uint32_t DX8GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xF04 */ __I uint32_t DX8GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xF08 */ __I uint32_t DX8GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xF0C */ __I uint32_t DX8GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xF10 */ __I uint32_t DX8GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xF14 */ __I uint32_t DX8GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xF18 */ __I uint32_t DX8GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xF1C */ __I uint32_t DX8GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xF20 */ __I uint32_t DX8GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xF24 */ __I uint32_t DX8DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xF28 */ __I uint32_t DX8DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xF2C */ uint8_t RESERVED_95[16]; __I uint32_t DX8BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xF40 */ __I uint32_t DX8BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xF44 */ __I uint32_t DX8BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xF48 */ uint8_t RESERVED_96[4]; __I uint32_t DX8BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xF50 */ __I uint32_t DX8BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xF54 */ __I uint32_t DX8BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xF58 */ uint8_t RESERVED_97[4]; __I uint32_t DX8BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xF60 */ __I uint32_t DX8BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xF64 */ __I uint32_t DX8BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xF68 */ __I uint32_t DX8BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xF6C */ uint8_t RESERVED_98[16]; __I uint32_t DX8LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xF80 */ __I uint32_t DX8LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xF84 */ __I uint32_t DX8LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xF88 */ __I uint32_t DX8LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xF8C */ __I uint32_t DX8LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xF90 */ __I uint32_t DX8LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xF94 */ uint8_t RESERVED_99[8]; __I uint32_t DX8MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xFA0 */ __I uint32_t DX8MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xFA4 */ uint8_t RESERVED_100[24]; __I uint32_t DX8GTR0; /**< DATX8 n General Timing Register 0, offset: 0xFC0 */ uint8_t RESERVED_101[12]; __I uint32_t DX8RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xFD0 */ __I uint32_t DX8RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xFD4 */ __I uint32_t DX8RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xFD8 */ __I uint32_t DX8RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xFDC */ __I uint32_t DX8GSR0; /**< DATX8 n General Status Register 0, offset: 0xFE0 */ __I uint32_t DX8GSR1; /**< DATX8 n General Status Register 1, offset: 0xFE4 */ __I uint32_t DX8GSR2; /**< DATX8 n General Status Register 2, offset: 0xFE8 */ __I uint32_t DX8GSR3; /**< DATX8 n General Status Register 3, offset: 0xFEC */ __I uint32_t DX8GSR4; /**< DATX8 n General Status Register 4, offset: 0xFF0 */ __I uint32_t DX8GSR5; /**< DATX8 n General Status Register 5, offset: 0xFF4 */ __I uint32_t DX8GSR6; /**< DATX8 n General Status Register 6, offset: 0xFF8 */ uint8_t RESERVED_102[1028]; __IO uint32_t DX8SL0OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1400 */ __IO uint32_t DX8SL0PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1404 */ __IO uint32_t DX8SL0PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1408 */ __IO uint32_t DX8SL0PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x140C */ __IO uint32_t DX8SL0PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1410 */ __IO uint32_t DX8SL0PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1414 */ __IO uint32_t DX8SL0PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1418 */ __IO uint32_t DX8SL0DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x141C */ __I uint32_t DX8SL0TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x1420 */ __IO uint32_t DX8SL0DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x1424 */ __IO uint32_t DX8SL0DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x1428 */ __IO uint32_t DX8SL0DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x142C */ __IO uint32_t DX8SL0IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x1430 */ __I uint32_t DX4SL0IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1434 */ uint8_t RESERVED_103[8]; __IO uint32_t DX8SL1OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1440 */ __IO uint32_t DX8SL1PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1444 */ __IO uint32_t DX8SL1PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1448 */ __IO uint32_t DX8SL1PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x144C */ __IO uint32_t DX8SL1PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1450 */ __IO uint32_t DX8SL1PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1454 */ __IO uint32_t DX8SL1PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1458 */ __IO uint32_t DX8SL1DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x145C */ __I uint32_t DX8SL1TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x1460 */ __IO uint32_t DX8SL1DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x1464 */ __IO uint32_t DX8SL1DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x1468 */ __IO uint32_t DX8SL1DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x146C */ __IO uint32_t DX8SL1IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x1470 */ __I uint32_t DX4SL1IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1474 */ uint8_t RESERVED_104[8]; __IO uint32_t DX8SL2OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1480 */ __IO uint32_t DX8SL2PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1484 */ __IO uint32_t DX8SL2PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1488 */ __IO uint32_t DX8SL2PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x148C */ __IO uint32_t DX8SL2PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1490 */ __IO uint32_t DX8SL2PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1494 */ __IO uint32_t DX8SL2PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1498 */ __IO uint32_t DX8SL2DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x149C */ __I uint32_t DX8SL2TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x14A0 */ __IO uint32_t DX8SL2DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x14A4 */ __IO uint32_t DX8SL2DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x14A8 */ __IO uint32_t DX8SL2DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x14AC */ __IO uint32_t DX8SL2IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x14B0 */ __I uint32_t DX4SL2IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x14B4 */ uint8_t RESERVED_105[8]; __I uint32_t DX8SL3OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x14C0 */ __I uint32_t DX8SL3PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x14C4 */ __I uint32_t DX8SL3PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x14C8 */ __I uint32_t DX8SL3PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x14CC */ __I uint32_t DX8SL3PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x14D0 */ __I uint32_t DX8SL3PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x14D4 */ __I uint32_t DX8SL3PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x14D8 */ __I uint32_t DX8SL3DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x14DC */ __I uint32_t DX8SL3TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x14E0 */ __I uint32_t DX8SL3DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x14E4 */ __I uint32_t DX8SL3DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x14E8 */ __I uint32_t DX8SL3DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x14EC */ __I uint32_t DX8SL3IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x14F0 */ __I uint32_t DX4SL3IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x14F4 */ uint8_t RESERVED_106[8]; __I uint32_t DX8SL4OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1500 */ __I uint32_t DX8SL4PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1504 */ __I uint32_t DX8SL4PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1508 */ __I uint32_t DX8SL4PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x150C */ __I uint32_t DX8SL4PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1510 */ __I uint32_t DX8SL4PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1514 */ __I uint32_t DX8SL4PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1518 */ __I uint32_t DX8SL4DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x151C */ __I uint32_t DX8SL4TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x1520 */ __I uint32_t DX8SL4DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x1524 */ __I uint32_t DX8SL4DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x1528 */ __I uint32_t DX8SL4DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x152C */ __I uint32_t DX8SL4IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x1530 */ __I uint32_t DX4SL4IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1534 */ uint8_t RESERVED_107[8]; __I uint32_t DX8SL5OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1540 */ __I uint32_t DX8SL5PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1544 */ __I uint32_t DX8SL5PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1548 */ __I uint32_t DX8SL5PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x154C */ __I uint32_t DX8SL5PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1550 */ __I uint32_t DX8SL5PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1554 */ __I uint32_t DX8SL5PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1558 */ __I uint32_t DX8SL5DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x155C */ __I uint32_t DX8SL5TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x1560 */ __I uint32_t DX8SL5DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x1564 */ __I uint32_t DX8SL5DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x1568 */ __I uint32_t DX8SL5DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x156C */ __I uint32_t DX8SL5IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x1570 */ __I uint32_t DX4SL5IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1574 */ uint8_t RESERVED_108[8]; __I uint32_t DX8SL6OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1580 */ __I uint32_t DX8SL6PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1584 */ __I uint32_t DX8SL6PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1588 */ __I uint32_t DX8SL6PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x158C */ __I uint32_t DX8SL6PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1590 */ __I uint32_t DX8SL6PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1594 */ __I uint32_t DX8SL6PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1598 */ __I uint32_t DX8SL6DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x159C */ __I uint32_t DX8SL6TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x15A0 */ __I uint32_t DX8SL6DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x15A4 */ __I uint32_t DX8SL6DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x15A8 */ __I uint32_t DX8SL6DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x15AC */ __I uint32_t DX8SL6IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x15B0 */ __I uint32_t DX4SL6IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x15B4 */ uint8_t RESERVED_109[8]; __I uint32_t DX8SL7OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x15C0 */ __I uint32_t DX8SL7PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x15C4 */ __I uint32_t DX8SL7PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x15C8 */ __I uint32_t DX8SL7PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x15CC */ __I uint32_t DX8SL7PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x15D0 */ __I uint32_t DX8SL7PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x15D4 */ __I uint32_t DX8SL7PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x15D8 */ __I uint32_t DX8SL7DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x15DC */ __I uint32_t DX8SL7TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x15E0 */ __I uint32_t DX8SL7DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x15E4 */ __I uint32_t DX8SL7DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x15E8 */ __I uint32_t DX8SL7DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x15EC */ __I uint32_t DX8SL7IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x15F0 */ __I uint32_t DX4SL7IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x15F4 */ uint8_t RESERVED_110[8]; __I uint32_t DX8SL8OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1600 */ __I uint32_t DX8SL8PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1604 */ __I uint32_t DX8SL8PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1608 */ __I uint32_t DX8SL8PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x160C */ __I uint32_t DX8SL8PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1610 */ __I uint32_t DX8SL8PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1614 */ __I uint32_t DX8SL8PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1618 */ __I uint32_t DX8SL8DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x161C */ __I uint32_t DX8SL8TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x1620 */ __I uint32_t DX8SL8DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x1624 */ __I uint32_t DX8SL8DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x1628 */ __I uint32_t DX8SL8DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x162C */ __I uint32_t DX8SL8IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x1630 */ __I uint32_t DX4SL8IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1634 */ uint8_t RESERVED_111[392]; __O uint32_t DX8SLBOSC; /**< DATX8 0-8 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x17C0 */ __O uint32_t DX8SLBPLLCR0; /**< DAXT8 0-8 PLL Control Register 0, offset: 0x17C4 */ __O uint32_t DX8SLBPLLCR1; /**< DAXT8 0-8 PLL Control Register 1 (Type B PLL Only), offset: 0x17C8 */ __O uint32_t DX8SLBPLLCR2; /**< DAXT8 0-8 PLL Control Register 2 (Type B PLL Only), offset: 0x17CC */ __O uint32_t DX8SLBPLLCR3; /**< DAXT8 0-8 PLL Control Register 3 (Type B PLL Only), offset: 0x17D0 */ __O uint32_t DX8SLBPLLCR4; /**< DAXT8 0-8 PLL Control Register 4 (Type B PLL Only), offset: 0x17D4 */ __O uint32_t DX8SLBPLLCR5; /**< DAXT8 0-8 PLL Control Register 5 (Type B PLL Only), offset: 0x17D8 */ __O uint32_t DX8SLBDQSCTL; /**< DATX8 0-8 DQS Control Register, offset: 0x17DC */ __O uint32_t DX8SLBTRNCTL; /**< DATX8 0-8 Training Control Register, offset: 0x17E0 */ __O uint32_t DX8SLBDDLCTL; /**< DATX8 0-8 DDL Control Register, offset: 0x17E4 */ __O uint32_t DX8SLBDXCTL1; /**< DATX8 0-8 DX Control Register 1, offset: 0x17E8 */ __O uint32_t DX8SLBDXCTL2; /**< DATX8 0-8 DX Control Register 2, offset: 0x17EC */ __O uint32_t DX8SLBIOCR; /**< DATX8 0-8 I/O Configuration Register, offset: 0x17F0 */ __O uint32_t DX4SLBIOCR; /**< DATX4 0-8 I/O Configuration Register, offset: 0x17F4 */ } DDRPHY_Type; /* ---------------------------------------------------------------------------- -- DDRPHY Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDRPHY_Register_Masks DDRPHY Register Masks * @{ */ /*! @name RIDR - Revision Identification Register */ /*! @{ */ #define DDRPHY_RIDR_PUBMNR_MASK (0xFU) #define DDRPHY_RIDR_PUBMNR_SHIFT (0U) /*! PUBMNR - PUB Minor Revision */ #define DDRPHY_RIDR_PUBMNR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PUBMNR_SHIFT)) & DDRPHY_RIDR_PUBMNR_MASK) #define DDRPHY_RIDR_PUBMDR_MASK (0xF0U) #define DDRPHY_RIDR_PUBMDR_SHIFT (4U) /*! PUBMDR - PUB Moderate Revision */ #define DDRPHY_RIDR_PUBMDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PUBMDR_SHIFT)) & DDRPHY_RIDR_PUBMDR_MASK) #define DDRPHY_RIDR_PUBMJR_MASK (0xF00U) #define DDRPHY_RIDR_PUBMJR_SHIFT (8U) /*! PUBMJR - PUB Major Revision */ #define DDRPHY_RIDR_PUBMJR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PUBMJR_SHIFT)) & DDRPHY_RIDR_PUBMJR_MASK) #define DDRPHY_RIDR_PHYMNR_MASK (0xF000U) #define DDRPHY_RIDR_PHYMNR_SHIFT (12U) /*! PHYMNR - PHY Minor Revision */ #define DDRPHY_RIDR_PHYMNR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PHYMNR_SHIFT)) & DDRPHY_RIDR_PHYMNR_MASK) #define DDRPHY_RIDR_PHYMDR_MASK (0xF0000U) #define DDRPHY_RIDR_PHYMDR_SHIFT (16U) /*! PHYMDR - PHY Moderate Revision */ #define DDRPHY_RIDR_PHYMDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PHYMDR_SHIFT)) & DDRPHY_RIDR_PHYMDR_MASK) #define DDRPHY_RIDR_PHYMJR_MASK (0xF00000U) #define DDRPHY_RIDR_PHYMJR_SHIFT (20U) /*! PHYMJR - PHY Major Revision */ #define DDRPHY_RIDR_PHYMJR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PHYMJR_SHIFT)) & DDRPHY_RIDR_PHYMJR_MASK) #define DDRPHY_RIDR_UDRID_MASK (0xFF000000U) #define DDRPHY_RIDR_UDRID_SHIFT (24U) /*! UDRID - User-Defined Revision ID */ #define DDRPHY_RIDR_UDRID(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_UDRID_SHIFT)) & DDRPHY_RIDR_UDRID_MASK) /*! @} */ /*! @name PIR - PHY Initialization Register */ /*! @{ */ #define DDRPHY_PIR_INIT_MASK (0x1U) #define DDRPHY_PIR_INIT_SHIFT (0U) /*! INIT - Initialization Trigger */ #define DDRPHY_PIR_INIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_INIT_SHIFT)) & DDRPHY_PIR_INIT_MASK) #define DDRPHY_PIR_ZCAL_MASK (0x2U) #define DDRPHY_PIR_ZCAL_SHIFT (1U) /*! ZCAL - Impedance Calibration */ #define DDRPHY_PIR_ZCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_ZCAL_SHIFT)) & DDRPHY_PIR_ZCAL_MASK) #define DDRPHY_PIR_CA_MASK (0x4U) #define DDRPHY_PIR_CA_SHIFT (2U) /*! CA - CA Training */ #define DDRPHY_PIR_CA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_CA_SHIFT)) & DDRPHY_PIR_CA_MASK) #define DDRPHY_PIR_RESERVED_3_MASK (0x8U) #define DDRPHY_PIR_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_PIR_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RESERVED_3_SHIFT)) & DDRPHY_PIR_RESERVED_3_MASK) #define DDRPHY_PIR_PLLINIT_MASK (0x10U) #define DDRPHY_PIR_PLLINIT_SHIFT (4U) /*! PLLINIT - PLL Initialiazation */ #define DDRPHY_PIR_PLLINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_PLLINIT_SHIFT)) & DDRPHY_PIR_PLLINIT_MASK) #define DDRPHY_PIR_DCAL_MASK (0x20U) #define DDRPHY_PIR_DCAL_SHIFT (5U) /*! DCAL - Digital Delay Line (DDL) Calibration */ #define DDRPHY_PIR_DCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DCAL_SHIFT)) & DDRPHY_PIR_DCAL_MASK) #define DDRPHY_PIR_PHYRST_MASK (0x40U) #define DDRPHY_PIR_PHYRST_SHIFT (6U) /*! PHYRST - PHY Reset */ #define DDRPHY_PIR_PHYRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_PHYRST_SHIFT)) & DDRPHY_PIR_PHYRST_MASK) #define DDRPHY_PIR_DRAMRST_MASK (0x80U) #define DDRPHY_PIR_DRAMRST_SHIFT (7U) /*! DRAMRST - DRAM Reset (DDR3/DDR4/LPDDR4 Only) */ #define DDRPHY_PIR_DRAMRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DRAMRST_SHIFT)) & DDRPHY_PIR_DRAMRST_MASK) #define DDRPHY_PIR_DRAMINIT_MASK (0x100U) #define DDRPHY_PIR_DRAMINIT_SHIFT (8U) /*! DRAMINIT - DRAM Initialization */ #define DDRPHY_PIR_DRAMINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DRAMINIT_SHIFT)) & DDRPHY_PIR_DRAMINIT_MASK) #define DDRPHY_PIR_WL_MASK (0x200U) #define DDRPHY_PIR_WL_SHIFT (9U) /*! WL - Write Leveling */ #define DDRPHY_PIR_WL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WL_SHIFT)) & DDRPHY_PIR_WL_MASK) #define DDRPHY_PIR_QSGATE_MASK (0x400U) #define DDRPHY_PIR_QSGATE_SHIFT (10U) /*! QSGATE - Read DQS Gate Training */ #define DDRPHY_PIR_QSGATE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_QSGATE_SHIFT)) & DDRPHY_PIR_QSGATE_MASK) #define DDRPHY_PIR_WLADJ_MASK (0x800U) #define DDRPHY_PIR_WLADJ_SHIFT (11U) /*! WLADJ - Write Leveling Adjust */ #define DDRPHY_PIR_WLADJ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WLADJ_SHIFT)) & DDRPHY_PIR_WLADJ_MASK) #define DDRPHY_PIR_RDDSKW_MASK (0x1000U) #define DDRPHY_PIR_RDDSKW_SHIFT (12U) /*! RDDSKW - Read Data Bit Deskew */ #define DDRPHY_PIR_RDDSKW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RDDSKW_SHIFT)) & DDRPHY_PIR_RDDSKW_MASK) #define DDRPHY_PIR_WRDSKW_MASK (0x2000U) #define DDRPHY_PIR_WRDSKW_SHIFT (13U) /*! WRDSKW - Write Data Bit Deskew */ #define DDRPHY_PIR_WRDSKW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WRDSKW_SHIFT)) & DDRPHY_PIR_WRDSKW_MASK) #define DDRPHY_PIR_RDEYE_MASK (0x4000U) #define DDRPHY_PIR_RDEYE_SHIFT (14U) /*! RDEYE - Read Data Eye Training */ #define DDRPHY_PIR_RDEYE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RDEYE_SHIFT)) & DDRPHY_PIR_RDEYE_MASK) #define DDRPHY_PIR_WREYE_MASK (0x8000U) #define DDRPHY_PIR_WREYE_SHIFT (15U) /*! WREYE - Write Data Eye Training */ #define DDRPHY_PIR_WREYE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WREYE_SHIFT)) & DDRPHY_PIR_WREYE_MASK) #define DDRPHY_PIR_SRD_MASK (0x10000U) #define DDRPHY_PIR_SRD_SHIFT (16U) /*! SRD - Static Read Training */ #define DDRPHY_PIR_SRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_SRD_SHIFT)) & DDRPHY_PIR_SRD_MASK) #define DDRPHY_PIR_VREF_MASK (0x20000U) #define DDRPHY_PIR_VREF_SHIFT (17U) /*! VREF - VREF Training */ #define DDRPHY_PIR_VREF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_VREF_SHIFT)) & DDRPHY_PIR_VREF_MASK) #define DDRPHY_PIR_CTLDINIT_MASK (0x40000U) #define DDRPHY_PIR_CTLDINIT_SHIFT (18U) /*! CTLDINIT - Controller DRAM Initialization */ #define DDRPHY_PIR_CTLDINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_CTLDINIT_SHIFT)) & DDRPHY_PIR_CTLDINIT_MASK) #define DDRPHY_PIR_RDIMMINIT_MASK (0x80000U) #define DDRPHY_PIR_RDIMMINIT_SHIFT (19U) /*! RDIMMINIT - RDIMM Initialization */ #define DDRPHY_PIR_RDIMMINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RDIMMINIT_SHIFT)) & DDRPHY_PIR_RDIMMINIT_MASK) #define DDRPHY_PIR_DQS2DQ_MASK (0x100000U) #define DDRPHY_PIR_DQS2DQ_SHIFT (20U) /*! DQS2DQ - Write DQS2DQ Training */ #define DDRPHY_PIR_DQS2DQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DQS2DQ_SHIFT)) & DDRPHY_PIR_DQS2DQ_MASK) #define DDRPHY_PIR_RESERVED_28_21_MASK (0x1FE00000U) #define DDRPHY_PIR_RESERVED_28_21_SHIFT (21U) /*! RESERVED_28_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_PIR_RESERVED_28_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RESERVED_28_21_SHIFT)) & DDRPHY_PIR_RESERVED_28_21_MASK) #define DDRPHY_PIR_DCALPSE_MASK (0x20000000U) #define DDRPHY_PIR_DCALPSE_SHIFT (29U) /*! DCALPSE - Digital Delay Line (DDL) Calibration Pause */ #define DDRPHY_PIR_DCALPSE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DCALPSE_SHIFT)) & DDRPHY_PIR_DCALPSE_MASK) #define DDRPHY_PIR_ZCALBYP_MASK (0x40000000U) #define DDRPHY_PIR_ZCALBYP_SHIFT (30U) /*! ZCALBYP - Impedance Calibration Bypass */ #define DDRPHY_PIR_ZCALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_ZCALBYP_SHIFT)) & DDRPHY_PIR_ZCALBYP_MASK) #define DDRPHY_PIR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_PIR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_PIR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RESERVED_31_SHIFT)) & DDRPHY_PIR_RESERVED_31_MASK) /*! @} */ /*! @name PGCR0 - PHY General Configuration Register 0 */ /*! @{ */ #define DDRPHY_PGCR0_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_PGCR0_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR0_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_7_0_SHIFT)) & DDRPHY_PGCR0_RESERVED_7_0_MASK) #define DDRPHY_PGCR0_OSCEN_MASK (0x100U) #define DDRPHY_PGCR0_OSCEN_SHIFT (8U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_PGCR0_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_OSCEN_SHIFT)) & DDRPHY_PGCR0_OSCEN_MASK) #define DDRPHY_PGCR0_OSCDIV_MASK (0x1E00U) #define DDRPHY_PGCR0_OSCDIV_SHIFT (9U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_PGCR0_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_OSCDIV_SHIFT)) & DDRPHY_PGCR0_OSCDIV_MASK) #define DDRPHY_PGCR0_RESERVED_13_MASK (0x2000U) #define DDRPHY_PGCR0_RESERVED_13_SHIFT (13U) /*! RESERVED_13 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR0_RESERVED_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_13_SHIFT)) & DDRPHY_PGCR0_RESERVED_13_MASK) #define DDRPHY_PGCR0_DTOSEL_MASK (0x7C000U) #define DDRPHY_PGCR0_DTOSEL_SHIFT (14U) /*! DTOSEL - Digital Test Output Select */ #define DDRPHY_PGCR0_DTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_DTOSEL_SHIFT)) & DDRPHY_PGCR0_DTOSEL_MASK) #define DDRPHY_PGCR0_RESERVED_23_19_MASK (0xF80000U) #define DDRPHY_PGCR0_RESERVED_23_19_SHIFT (19U) /*! RESERVED_23_19 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR0_RESERVED_23_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_23_19_SHIFT)) & DDRPHY_PGCR0_RESERVED_23_19_MASK) #define DDRPHY_PGCR0_OSCACDL_MASK (0x3000000U) #define DDRPHY_PGCR0_OSCACDL_SHIFT (24U) /*! OSCACDL - Oscillator Mode Address/Command Delay Line Select */ #define DDRPHY_PGCR0_OSCACDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_OSCACDL_SHIFT)) & DDRPHY_PGCR0_OSCACDL_MASK) #define DDRPHY_PGCR0_PHYFRST_MASK (0x4000000U) #define DDRPHY_PGCR0_PHYFRST_SHIFT (26U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_PGCR0_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_PHYFRST_SHIFT)) & DDRPHY_PGCR0_PHYFRST_MASK) #define DDRPHY_PGCR0_RESERVED_30_27_MASK (0x78000000U) #define DDRPHY_PGCR0_RESERVED_30_27_SHIFT (27U) /*! RESERVED_30_27 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR0_RESERVED_30_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_30_27_SHIFT)) & DDRPHY_PGCR0_RESERVED_30_27_MASK) #define DDRPHY_PGCR0_ADCP_MASK (0x80000000U) #define DDRPHY_PGCR0_ADCP_SHIFT (31U) /*! ADCP - Address Copy */ #define DDRPHY_PGCR0_ADCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_ADCP_SHIFT)) & DDRPHY_PGCR0_ADCP_MASK) /*! @} */ /*! @name PGCR1 - PHY General Configuration Register 1 */ /*! @{ */ #define DDRPHY_PGCR1_DTOMODE_MASK (0x1U) #define DDRPHY_PGCR1_DTOMODE_SHIFT (0U) /*! DTOMODE - Digital Test Output Mode */ #define DDRPHY_PGCR1_DTOMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DTOMODE_SHIFT)) & DDRPHY_PGCR1_DTOMODE_MASK) #define DDRPHY_PGCR1_WLMODE_MASK (0x2U) #define DDRPHY_PGCR1_WLMODE_SHIFT (1U) /*! WLMODE - Write Leveling (Software) Mode */ #define DDRPHY_PGCR1_WLMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_WLMODE_SHIFT)) & DDRPHY_PGCR1_WLMODE_MASK) #define DDRPHY_PGCR1_WLSTEP_MASK (0x4U) #define DDRPHY_PGCR1_WLSTEP_SHIFT (2U) /*! WLSTEP - Write Leveling Step */ #define DDRPHY_PGCR1_WLSTEP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_WLSTEP_SHIFT)) & DDRPHY_PGCR1_WLSTEP_MASK) #define DDRPHY_PGCR1_AC_CKOUT_DIFF_MASK (0x8U) #define DDRPHY_PGCR1_AC_CKOUT_DIFF_SHIFT (3U) /*! AC_CKOUT_DIFF - Selects PDIFF cell for CK generation */ #define DDRPHY_PGCR1_AC_CKOUT_DIFF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_AC_CKOUT_DIFF_SHIFT)) & DDRPHY_PGCR1_AC_CKOUT_DIFF_MASK) #define DDRPHY_PGCR1_DX_DQSOUT_DIFF_MASK (0x10U) #define DDRPHY_PGCR1_DX_DQSOUT_DIFF_SHIFT (4U) /*! DX_DQSOUT_DIFF - Selects PDIFF cell for DQS generation */ #define DDRPHY_PGCR1_DX_DQSOUT_DIFF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DX_DQSOUT_DIFF_SHIFT)) & DDRPHY_PGCR1_DX_DQSOUT_DIFF_MASK) #define DDRPHY_PGCR1_CAST_MASK (0x20U) #define DDRPHY_PGCR1_CAST_SHIFT (5U) /*! CAST - CA Software Training. */ #define DDRPHY_PGCR1_CAST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_CAST_SHIFT)) & DDRPHY_PGCR1_CAST_MASK) #define DDRPHY_PGCR1_PUBMODE_MASK (0x40U) #define DDRPHY_PGCR1_PUBMODE_SHIFT (6U) /*! PUBMODE - Enables, if set, the PUB to control the interface to the PHY and SDRAM. */ #define DDRPHY_PGCR1_PUBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_PUBMODE_SHIFT)) & DDRPHY_PGCR1_PUBMODE_MASK) #define DDRPHY_PGCR1_RESERVED_8_7_MASK (0x180U) #define DDRPHY_PGCR1_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR1_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_RESERVED_8_7_SHIFT)) & DDRPHY_PGCR1_RESERVED_8_7_MASK) #define DDRPHY_PGCR1_MDLEN_MASK (0x200U) #define DDRPHY_PGCR1_MDLEN_SHIFT (9U) /*! MDLEN - Master Delay Line Enable */ #define DDRPHY_PGCR1_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_MDLEN_SHIFT)) & DDRPHY_PGCR1_MDLEN_MASK) #define DDRPHY_PGCR1_LPFEN_MASK (0x400U) #define DDRPHY_PGCR1_LPFEN_SHIFT (10U) /*! LPFEN - Low-Pass Filter Enable */ #define DDRPHY_PGCR1_LPFEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LPFEN_SHIFT)) & DDRPHY_PGCR1_LPFEN_MASK) #define DDRPHY_PGCR1_LPFDEPTH_MASK (0x1800U) #define DDRPHY_PGCR1_LPFDEPTH_SHIFT (11U) /*! LPFDEPTH - Low-Pass Filter Depth */ #define DDRPHY_PGCR1_LPFDEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LPFDEPTH_SHIFT)) & DDRPHY_PGCR1_LPFDEPTH_MASK) #define DDRPHY_PGCR1_FDEPTH_MASK (0x6000U) #define DDRPHY_PGCR1_FDEPTH_SHIFT (13U) /*! FDEPTH - Filter Depth */ #define DDRPHY_PGCR1_FDEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_FDEPTH_SHIFT)) & DDRPHY_PGCR1_FDEPTH_MASK) #define DDRPHY_PGCR1_DUALCHN_MASK (0x8000U) #define DDRPHY_PGCR1_DUALCHN_SHIFT (15U) /*! DUALCHN - Dual Channel Configuration */ #define DDRPHY_PGCR1_DUALCHN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DUALCHN_SHIFT)) & DDRPHY_PGCR1_DUALCHN_MASK) #define DDRPHY_PGCR1_ACPDDC_MASK (0x10000U) #define DDRPHY_PGCR1_ACPDDC_SHIFT (16U) /*! ACPDDC - AC Power-Down with Dual Channels */ #define DDRPHY_PGCR1_ACPDDC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_ACPDDC_SHIFT)) & DDRPHY_PGCR1_ACPDDC_MASK) #define DDRPHY_PGCR1_DISDIC_MASK (0x20000U) #define DDRPHY_PGCR1_DISDIC_SHIFT (17U) /*! DISDIC - Enable/Disable control for dfi_init_complete. */ #define DDRPHY_PGCR1_DISDIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DISDIC_SHIFT)) & DDRPHY_PGCR1_DISDIC_MASK) #define DDRPHY_PGCR1_UPDMSTRC0_MASK (0x40000U) #define DDRPHY_PGCR1_UPDMSTRC0_SHIFT (18U) /*! UPDMSTRC0 - DFI Update Master Channel 0 */ #define DDRPHY_PGCR1_UPDMSTRC0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_UPDMSTRC0_SHIFT)) & DDRPHY_PGCR1_UPDMSTRC0_MASK) #define DDRPHY_PGCR1_RESERVED_19_MASK (0x80000U) #define DDRPHY_PGCR1_RESERVED_19_SHIFT (19U) /*! RESERVED_19 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR1_RESERVED_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_RESERVED_19_SHIFT)) & DDRPHY_PGCR1_RESERVED_19_MASK) #define DDRPHY_PGCR1_LRDIMMST_MASK (0x100000U) #define DDRPHY_PGCR1_LRDIMMST_SHIFT (20U) /*! LRDIMMST - LRDIMM Software Training */ #define DDRPHY_PGCR1_LRDIMMST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LRDIMMST_SHIFT)) & DDRPHY_PGCR1_LRDIMMST_MASK) #define DDRPHY_PGCR1_ACVLDDLY_MASK (0xE00000U) #define DDRPHY_PGCR1_ACVLDDLY_SHIFT (21U) /*! ACVLDDLY - AC Loopback Valid Delay */ #define DDRPHY_PGCR1_ACVLDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_ACVLDDLY_SHIFT)) & DDRPHY_PGCR1_ACVLDDLY_MASK) #define DDRPHY_PGCR1_ACVLDTRN_MASK (0x1000000U) #define DDRPHY_PGCR1_ACVLDTRN_SHIFT (24U) /*! ACVLDTRN - AC Loopback Valid Train */ #define DDRPHY_PGCR1_ACVLDTRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_ACVLDTRN_SHIFT)) & DDRPHY_PGCR1_ACVLDTRN_MASK) #define DDRPHY_PGCR1_PHYHRST_MASK (0x2000000U) #define DDRPHY_PGCR1_PHYHRST_SHIFT (25U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_PGCR1_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_PHYHRST_SHIFT)) & DDRPHY_PGCR1_PHYHRST_MASK) #define DDRPHY_PGCR1_DLTMODE_MASK (0x4000000U) #define DDRPHY_PGCR1_DLTMODE_SHIFT (26U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_PGCR1_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DLTMODE_SHIFT)) & DDRPHY_PGCR1_DLTMODE_MASK) #define DDRPHY_PGCR1_DLTST_MASK (0x8000000U) #define DDRPHY_PGCR1_DLTST_SHIFT (27U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_PGCR1_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DLTST_SHIFT)) & DDRPHY_PGCR1_DLTST_MASK) #define DDRPHY_PGCR1_LBGSDQS_MASK (0x10000000U) #define DDRPHY_PGCR1_LBGSDQS_SHIFT (28U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value (equivalent to one CK period) */ #define DDRPHY_PGCR1_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LBGSDQS_SHIFT)) & DDRPHY_PGCR1_LBGSDQS_MASK) #define DDRPHY_PGCR1_RESERVED_30_29_MASK (0x60000000U) #define DDRPHY_PGCR1_RESERVED_30_29_SHIFT (29U) /*! RESERVED_30_29 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR1_RESERVED_30_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_RESERVED_30_29_SHIFT)) & DDRPHY_PGCR1_RESERVED_30_29_MASK) #define DDRPHY_PGCR1_LBMODE_MASK (0x80000000U) #define DDRPHY_PGCR1_LBMODE_SHIFT (31U) /*! LBMODE - Loopback Mode */ #define DDRPHY_PGCR1_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LBMODE_SHIFT)) & DDRPHY_PGCR1_LBMODE_MASK) /*! @} */ /*! @name PGCR2 - PHY General Configuration Register 2 */ /*! @{ */ #define DDRPHY_PGCR2_tREFPRD_MASK (0x3FFFFU) #define DDRPHY_PGCR2_tREFPRD_SHIFT (0U) /*! tREFPRD - Refresh Period */ #define DDRPHY_PGCR2_tREFPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_tREFPRD_SHIFT)) & DDRPHY_PGCR2_tREFPRD_MASK) #define DDRPHY_PGCR2_PLLFSMBYP_MASK (0x40000U) #define DDRPHY_PGCR2_PLLFSMBYP_SHIFT (18U) /*! PLLFSMBYP - PLL FSM Bypass */ #define DDRPHY_PGCR2_PLLFSMBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_PLLFSMBYP_SHIFT)) & DDRPHY_PGCR2_PLLFSMBYP_MASK) #define DDRPHY_PGCR2_INITFSMBYP_MASK (0x80000U) #define DDRPHY_PGCR2_INITFSMBYP_SHIFT (19U) /*! INITFSMBYP - Initialization Bypass */ #define DDRPHY_PGCR2_INITFSMBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_INITFSMBYP_SHIFT)) & DDRPHY_PGCR2_INITFSMBYP_MASK) #define DDRPHY_PGCR2_DTPMXTMR_MASK (0xFF00000U) #define DDRPHY_PGCR2_DTPMXTMR_SHIFT (20U) /*! DTPMXTMR - Data Training PUB Mode Exit Timer */ #define DDRPHY_PGCR2_DTPMXTMR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_DTPMXTMR_SHIFT)) & DDRPHY_PGCR2_DTPMXTMR_MASK) #define DDRPHY_PGCR2_ICPC_MASK (0x10000000U) #define DDRPHY_PGCR2_ICPC_SHIFT (28U) /*! ICPC - Initialization Complete Pin Configuration */ #define DDRPHY_PGCR2_ICPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_ICPC_SHIFT)) & DDRPHY_PGCR2_ICPC_MASK) #define DDRPHY_PGCR2_CLRPERR_MASK (0x20000000U) #define DDRPHY_PGCR2_CLRPERR_SHIFT (29U) /*! CLRPERR - Clear Parity Error */ #define DDRPHY_PGCR2_CLRPERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_CLRPERR_SHIFT)) & DDRPHY_PGCR2_CLRPERR_MASK) #define DDRPHY_PGCR2_CLRZCAL_MASK (0x40000000U) #define DDRPHY_PGCR2_CLRZCAL_SHIFT (30U) /*! CLRZCAL - Clear Impedance Calibration */ #define DDRPHY_PGCR2_CLRZCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_CLRZCAL_SHIFT)) & DDRPHY_PGCR2_CLRZCAL_MASK) #define DDRPHY_PGCR2_CLRTSTAT_MASK (0x80000000U) #define DDRPHY_PGCR2_CLRTSTAT_SHIFT (31U) /*! CLRTSTAT - Clear Training Status Registers */ #define DDRPHY_PGCR2_CLRTSTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_CLRTSTAT_SHIFT)) & DDRPHY_PGCR2_CLRTSTAT_MASK) /*! @} */ /*! @name PGCR3 - PHY General Configuration Register 3 */ /*! @{ */ #define DDRPHY_PGCR3_CLKLEVEL_MASK (0x3U) #define DDRPHY_PGCR3_CLKLEVEL_SHIFT (0U) /*! CLKLEVEL - Clock Level when Clock Gating */ #define DDRPHY_PGCR3_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_CLKLEVEL_SHIFT)) & DDRPHY_PGCR3_CLKLEVEL_MASK) #define DDRPHY_PGCR3_DISRST_MASK (0x4U) #define DDRPHY_PGCR3_DISRST_SHIFT (2U) /*! DISRST - Read FIFO Reset Disable */ #define DDRPHY_PGCR3_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_DISRST_SHIFT)) & DDRPHY_PGCR3_DISRST_MASK) #define DDRPHY_PGCR3_RDMODE_MASK (0x18U) #define DDRPHY_PGCR3_RDMODE_SHIFT (3U) /*! RDMODE - AC Receive FIFO Read Mode */ #define DDRPHY_PGCR3_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_RDMODE_SHIFT)) & DDRPHY_PGCR3_RDMODE_MASK) #define DDRPHY_PGCR3_IOLB_MASK (0x20U) #define DDRPHY_PGCR3_IOLB_SHIFT (5U) /*! IOLB - IO Loop-Back Select */ #define DDRPHY_PGCR3_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_IOLB_SHIFT)) & DDRPHY_PGCR3_IOLB_MASK) #define DDRPHY_PGCR3_DDLBYPMODE_MASK (0xC0U) #define DDRPHY_PGCR3_DDLBYPMODE_SHIFT (6U) /*! DDLBYPMODE - Controls DDL Bypass Modes */ #define DDRPHY_PGCR3_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_DDLBYPMODE_SHIFT)) & DDRPHY_PGCR3_DDLBYPMODE_MASK) #define DDRPHY_PGCR3_RESERVED_8_MASK (0x100U) #define DDRPHY_PGCR3_RESERVED_8_SHIFT (8U) /*! RESERVED_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_PGCR3_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_RESERVED_8_SHIFT)) & DDRPHY_PGCR3_RESERVED_8_MASK) #define DDRPHY_PGCR3_GATEACCTLCLK_MASK (0x600U) #define DDRPHY_PGCR3_GATEACCTLCLK_SHIFT (9U) /*! GATEACCTLCLK - Enable Clock Gating for AC [0] ctl_clk */ #define DDRPHY_PGCR3_GATEACCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_GATEACCTLCLK_SHIFT)) & DDRPHY_PGCR3_GATEACCTLCLK_MASK) #define DDRPHY_PGCR3_GATEACDDRCLK_MASK (0x1800U) #define DDRPHY_PGCR3_GATEACDDRCLK_SHIFT (11U) /*! GATEACDDRCLK - Enable Clock Gating for AC [0] ddr_clk */ #define DDRPHY_PGCR3_GATEACDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_GATEACDDRCLK_SHIFT)) & DDRPHY_PGCR3_GATEACDDRCLK_MASK) #define DDRPHY_PGCR3_GATEACRDCLK_MASK (0x6000U) #define DDRPHY_PGCR3_GATEACRDCLK_SHIFT (13U) /*! GATEACRDCLK - Enable Clock Gating for AC [0] ctl_rd_clk */ #define DDRPHY_PGCR3_GATEACRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_GATEACRDCLK_SHIFT)) & DDRPHY_PGCR3_GATEACRDCLK_MASK) #define DDRPHY_PGCR3_RESERVED_15_MASK (0x8000U) #define DDRPHY_PGCR3_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_PGCR3_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_RESERVED_15_SHIFT)) & DDRPHY_PGCR3_RESERVED_15_MASK) #define DDRPHY_PGCR3_CKEN_MASK (0xFF0000U) #define DDRPHY_PGCR3_CKEN_SHIFT (16U) /*! CKEN - CK Enable */ #define DDRPHY_PGCR3_CKEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_CKEN_SHIFT)) & DDRPHY_PGCR3_CKEN_MASK) #define DDRPHY_PGCR3_CKNEN_MASK (0xFF000000U) #define DDRPHY_PGCR3_CKNEN_SHIFT (24U) /*! CKNEN - CKN Enable */ #define DDRPHY_PGCR3_CKNEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_CKNEN_SHIFT)) & DDRPHY_PGCR3_CKNEN_MASK) /*! @} */ /*! @name PGCR4 - PHY General Configuration Register 4 */ /*! @{ */ #define DDRPHY_PGCR4_LPIOPD_MASK (0x1U) #define DDRPHY_PGCR4_LPIOPD_SHIFT (0U) /*! LPIOPD - AC Low Power IO Power Down */ #define DDRPHY_PGCR4_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_LPIOPD_SHIFT)) & DDRPHY_PGCR4_LPIOPD_MASK) #define DDRPHY_PGCR4_LPPLLPD_MASK (0x2U) #define DDRPHY_PGCR4_LPPLLPD_SHIFT (1U) /*! LPPLLPD - AC Low Power PLL Power Down */ #define DDRPHY_PGCR4_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_LPPLLPD_SHIFT)) & DDRPHY_PGCR4_LPPLLPD_MASK) #define DDRPHY_PGCR4_RESERVED_3_2_MASK (0xCU) #define DDRPHY_PGCR4_RESERVED_3_2_SHIFT (2U) /*! RESERVED_3_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_PGCR4_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RESERVED_3_2_SHIFT)) & DDRPHY_PGCR4_RESERVED_3_2_MASK) #define DDRPHY_PGCR4_LPWAKEUP_THRSH_MASK (0xF0U) #define DDRPHY_PGCR4_LPWAKEUP_THRSH_SHIFT (4U) /*! LPWAKEUP_THRSH - AC Low Power Wakeup Threshold */ #define DDRPHY_PGCR4_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_PGCR4_LPWAKEUP_THRSH_MASK) #define DDRPHY_PGCR4_DCALSVAL_MASK (0x1FF00U) #define DDRPHY_PGCR4_DCALSVAL_SHIFT (8U) /*! DCALSVAL - DDL Calibration Starting Value */ #define DDRPHY_PGCR4_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_DCALSVAL_SHIFT)) & DDRPHY_PGCR4_DCALSVAL_MASK) #define DDRPHY_PGCR4_DCALTYPE_MASK (0x20000U) #define DDRPHY_PGCR4_DCALTYPE_SHIFT (17U) /*! DCALTYPE - DDL Calibration Type */ #define DDRPHY_PGCR4_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_DCALTYPE_SHIFT)) & DDRPHY_PGCR4_DCALTYPE_MASK) #define DDRPHY_PGCR4_RESERVED_18_MASK (0x40000U) #define DDRPHY_PGCR4_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Return zeroes on reads. */ #define DDRPHY_PGCR4_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RESERVED_18_SHIFT)) & DDRPHY_PGCR4_RESERVED_18_MASK) #define DDRPHY_PGCR4_WRRMODE_MASK (0x80000U) #define DDRPHY_PGCR4_WRRMODE_SHIFT (19U) /*! WRRMODE - AC Macro Write Path Rise-to-Rise Mode */ #define DDRPHY_PGCR4_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_WRRMODE_SHIFT)) & DDRPHY_PGCR4_WRRMODE_MASK) #define DDRPHY_PGCR4_RRRMODE_MASK (0x100000U) #define DDRPHY_PGCR4_RRRMODE_SHIFT (20U) /*! RRRMODE - AC Macro Read Path Rise-to-Rise Mode */ #define DDRPHY_PGCR4_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RRRMODE_SHIFT)) & DDRPHY_PGCR4_RRRMODE_MASK) #define DDRPHY_PGCR4_PDRDDLBYP_MASK (0x200000U) #define DDRPHY_PGCR4_PDRDDLBYP_SHIFT (21U) /*! PDRDDLBYP - AC PDR DDL Bypass */ #define DDRPHY_PGCR4_PDRDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_PDRDDLBYP_SHIFT)) & DDRPHY_PGCR4_PDRDDLBYP_MASK) #define DDRPHY_PGCR4_TEDDLBYP_MASK (0x400000U) #define DDRPHY_PGCR4_TEDDLBYP_SHIFT (22U) /*! TEDDLBYP - AC ODT DDL Bypass */ #define DDRPHY_PGCR4_TEDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_TEDDLBYP_SHIFT)) & DDRPHY_PGCR4_TEDDLBYP_MASK) #define DDRPHY_PGCR4_OEDDLBYP_MASK (0x800000U) #define DDRPHY_PGCR4_OEDDLBYP_SHIFT (23U) /*! OEDDLBYP - AC OE DDL Bypass */ #define DDRPHY_PGCR4_OEDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_OEDDLBYP_SHIFT)) & DDRPHY_PGCR4_OEDDLBYP_MASK) #define DDRPHY_PGCR4_ACDDLBYP_MASK (0x1F000000U) #define DDRPHY_PGCR4_ACDDLBYP_SHIFT (24U) /*! ACDDLBYP - AC DDL Bypass */ #define DDRPHY_PGCR4_ACDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_ACDDLBYP_SHIFT)) & DDRPHY_PGCR4_ACDDLBYP_MASK) #define DDRPHY_PGCR4_ACDDLLD_MASK (0x20000000U) #define DDRPHY_PGCR4_ACDDLLD_SHIFT (29U) /*! ACDDLLD - AC DDL Delay Select Dymainc Load */ #define DDRPHY_PGCR4_ACDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_ACDDLLD_SHIFT)) & DDRPHY_PGCR4_ACDDLLD_MASK) #define DDRPHY_PGCR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_PGCR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_PGCR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RESERVED_31_30_SHIFT)) & DDRPHY_PGCR4_RESERVED_31_30_MASK) /*! @} */ /*! @name PGCR5 - PHY General Configuration Register 5 */ /*! @{ */ #define DDRPHY_PGCR5_DDLPGRW_MASK (0x1U) #define DDRPHY_PGCR5_DDLPGRW_SHIFT (0U) /*! DDLPGRW - DDL Page Read Write select */ #define DDRPHY_PGCR5_DDLPGRW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DDLPGRW_SHIFT)) & DDRPHY_PGCR5_DDLPGRW_MASK) #define DDRPHY_PGCR5_DDLPGACT_MASK (0x2U) #define DDRPHY_PGCR5_DDLPGACT_SHIFT (1U) /*! DDLPGACT - DDL Page Read Write select */ #define DDRPHY_PGCR5_DDLPGACT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DDLPGACT_SHIFT)) & DDRPHY_PGCR5_DDLPGACT_MASK) #define DDRPHY_PGCR5_DXREFISELRANGE_MASK (0x4U) #define DDRPHY_PGCR5_DXREFISELRANGE_SHIFT (2U) /*! DXREFISELRANGE - Internal VREF generator REFSEL ragne select */ #define DDRPHY_PGCR5_DXREFISELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DXREFISELRANGE_SHIFT)) & DDRPHY_PGCR5_DXREFISELRANGE_MASK) #define DDRPHY_PGCR5_RESERVED_3_MASK (0x8U) #define DDRPHY_PGCR5_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_PGCR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_RESERVED_3_SHIFT)) & DDRPHY_PGCR5_RESERVED_3_MASK) #define DDRPHY_PGCR5_VREF_RBCTRL_MASK (0xF0U) #define DDRPHY_PGCR5_VREF_RBCTRL_SHIFT (4U) /*! VREF_RBCTRL - Receiver bias core side control */ #define DDRPHY_PGCR5_VREF_RBCTRL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_VREF_RBCTRL_SHIFT)) & DDRPHY_PGCR5_VREF_RBCTRL_MASK) #define DDRPHY_PGCR5_DISCNPERIOD_MASK (0xFF00U) #define DDRPHY_PGCR5_DISCNPERIOD_SHIFT (8U) /*! DISCNPERIOD - DFI Disconnect Time Period */ #define DDRPHY_PGCR5_DISCNPERIOD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DISCNPERIOD_SHIFT)) & DDRPHY_PGCR5_DISCNPERIOD_MASK) #define DDRPHY_PGCR5_FRQAT_MASK (0xFF0000U) #define DDRPHY_PGCR5_FRQAT_SHIFT (16U) /*! FRQAT - Frequency A Ratio Term */ #define DDRPHY_PGCR5_FRQAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_FRQAT_SHIFT)) & DDRPHY_PGCR5_FRQAT_MASK) #define DDRPHY_PGCR5_FRQBT_MASK (0xFF000000U) #define DDRPHY_PGCR5_FRQBT_SHIFT (24U) /*! FRQBT - Frequency B Ratio Term */ #define DDRPHY_PGCR5_FRQBT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_FRQBT_SHIFT)) & DDRPHY_PGCR5_FRQBT_MASK) /*! @} */ /*! @name PGCR6 - PHY General Configuration Register 6 */ /*! @{ */ #define DDRPHY_PGCR6_INHVT_MASK (0x1U) #define DDRPHY_PGCR6_INHVT_SHIFT (0U) /*! INHVT - VT Calculation Inhibit */ #define DDRPHY_PGCR6_INHVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_INHVT_SHIFT)) & DDRPHY_PGCR6_INHVT_MASK) #define DDRPHY_PGCR6_FVT_MASK (0x2U) #define DDRPHY_PGCR6_FVT_SHIFT (1U) /*! FVT - Forced VT Compensation Trigger */ #define DDRPHY_PGCR6_FVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_FVT_SHIFT)) & DDRPHY_PGCR6_FVT_MASK) #define DDRPHY_PGCR6_RESERVED_7_2_MASK (0xFCU) #define DDRPHY_PGCR6_RESERVED_7_2_SHIFT (2U) /*! RESERVED_7_2 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR6_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_RESERVED_7_2_SHIFT)) & DDRPHY_PGCR6_RESERVED_7_2_MASK) #define DDRPHY_PGCR6_CKBVT_MASK (0x100U) #define DDRPHY_PGCR6_CKBVT_SHIFT (8U) /*! CKBVT - CK Bit Delay VT Compensation */ #define DDRPHY_PGCR6_CKBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_CKBVT_SHIFT)) & DDRPHY_PGCR6_CKBVT_MASK) #define DDRPHY_PGCR6_CSNBVT_MASK (0x200U) #define DDRPHY_PGCR6_CSNBVT_SHIFT (9U) /*! CSNBVT - CSN Bit Delay VT Compensation */ #define DDRPHY_PGCR6_CSNBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_CSNBVT_SHIFT)) & DDRPHY_PGCR6_CSNBVT_MASK) #define DDRPHY_PGCR6_CKEBVT_MASK (0x400U) #define DDRPHY_PGCR6_CKEBVT_SHIFT (10U) /*! CKEBVT - CKE Bit Delay VT Compensation */ #define DDRPHY_PGCR6_CKEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_CKEBVT_SHIFT)) & DDRPHY_PGCR6_CKEBVT_MASK) #define DDRPHY_PGCR6_ODTBVT_MASK (0x800U) #define DDRPHY_PGCR6_ODTBVT_SHIFT (11U) /*! ODTBVT - ODT Bit Delay VT Compensation */ #define DDRPHY_PGCR6_ODTBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_ODTBVT_SHIFT)) & DDRPHY_PGCR6_ODTBVT_MASK) #define DDRPHY_PGCR6_ACBVT_MASK (0x1000U) #define DDRPHY_PGCR6_ACBVT_SHIFT (12U) /*! ACBVT - Address/Command Bit Delay VT Compensation */ #define DDRPHY_PGCR6_ACBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_ACBVT_SHIFT)) & DDRPHY_PGCR6_ACBVT_MASK) #define DDRPHY_PGCR6_ACDLVT_MASK (0x2000U) #define DDRPHY_PGCR6_ACDLVT_SHIFT (13U) /*! ACDLVT - AC Address/Command Delay LCDL VT Compensation */ #define DDRPHY_PGCR6_ACDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_ACDLVT_SHIFT)) & DDRPHY_PGCR6_ACDLVT_MASK) #define DDRPHY_PGCR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_PGCR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_RESERVED_15_14_SHIFT)) & DDRPHY_PGCR6_RESERVED_15_14_MASK) #define DDRPHY_PGCR6_DLDLMT_MASK (0xFF0000U) #define DDRPHY_PGCR6_DLDLMT_SHIFT (16U) /*! DLDLMT - Delay Line VT Drift Limit */ #define DDRPHY_PGCR6_DLDLMT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_DLDLMT_SHIFT)) & DDRPHY_PGCR6_DLDLMT_MASK) #define DDRPHY_PGCR6_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_PGCR6_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_RESERVED_31_24_SHIFT)) & DDRPHY_PGCR6_RESERVED_31_24_MASK) /*! @} */ /*! @name PGCR7 - PHY General Configuration Register 7 */ /*! @{ */ #define DDRPHY_PGCR7_ACTMODE_MASK (0x1U) #define DDRPHY_PGCR7_ACTMODE_SHIFT (0U) /*! ACTMODE - AC Test Mode */ #define DDRPHY_PGCR7_ACTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACTMODE_SHIFT)) & DDRPHY_PGCR7_ACTMODE_MASK) #define DDRPHY_PGCR7_ACDTOSEL_MASK (0x2U) #define DDRPHY_PGCR7_ACDTOSEL_SHIFT (1U) /*! ACDTOSEL - AC Digital Test Output Select */ #define DDRPHY_PGCR7_ACDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACDTOSEL_SHIFT)) & DDRPHY_PGCR7_ACDTOSEL_MASK) #define DDRPHY_PGCR7_ACRSVD_2_MASK (0x4U) #define DDRPHY_PGCR7_ACRSVD_2_SHIFT (2U) /*! ACRSVD_2 - This bit is reserved for future AC special PHY modes but the register is already * connected to existing (unused) AC phy_mode bits. */ #define DDRPHY_PGCR7_ACRSVD_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACRSVD_2_SHIFT)) & DDRPHY_PGCR7_ACRSVD_2_MASK) #define DDRPHY_PGCR7_ACDLDT_MASK (0x8U) #define DDRPHY_PGCR7_ACDLDT_SHIFT (3U) /*! ACDLDT - AC DDL Load Type */ #define DDRPHY_PGCR7_ACDLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACDLDT_SHIFT)) & DDRPHY_PGCR7_ACDLDT_MASK) #define DDRPHY_PGCR7_ACRCLKMD_MASK (0x10U) #define DDRPHY_PGCR7_ACRCLKMD_SHIFT (4U) /*! ACRCLKMD - AC Read Clock Mode */ #define DDRPHY_PGCR7_ACRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACRCLKMD_SHIFT)) & DDRPHY_PGCR7_ACRCLKMD_MASK) #define DDRPHY_PGCR7_ACCALCLK_MASK (0x20U) #define DDRPHY_PGCR7_ACCALCLK_SHIFT (5U) /*! ACCALCLK - AC Calibration Clock Select */ #define DDRPHY_PGCR7_ACCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACCALCLK_SHIFT)) & DDRPHY_PGCR7_ACCALCLK_MASK) #define DDRPHY_PGCR7_ACRSVD_7_6_MASK (0xC0U) #define DDRPHY_PGCR7_ACRSVD_7_6_SHIFT (6U) /*! ACRSVD_7_6 - These bits are reserved for future AC special PHY modes but the registers are * already connected to existing (unused) AC phy_mode bits. */ #define DDRPHY_PGCR7_ACRSVD_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACRSVD_7_6_SHIFT)) & DDRPHY_PGCR7_ACRSVD_7_6_MASK) #define DDRPHY_PGCR7_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_PGCR7_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGCR7_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_RESERVED_31_8_SHIFT)) & DDRPHY_PGCR7_RESERVED_31_8_MASK) /*! @} */ /*! @name PGSR0 - PHY General Status Register 0 */ /*! @{ */ #define DDRPHY_PGSR0_IDONE_MASK (0x1U) #define DDRPHY_PGSR0_IDONE_SHIFT (0U) /*! IDONE - Initialization Done */ #define DDRPHY_PGSR0_IDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_IDONE_SHIFT)) & DDRPHY_PGSR0_IDONE_MASK) #define DDRPHY_PGSR0_PLDONE_MASK (0x2U) #define DDRPHY_PGSR0_PLDONE_SHIFT (1U) /*! PLDONE - PLL Lock Done */ #define DDRPHY_PGSR0_PLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_PLDONE_SHIFT)) & DDRPHY_PGSR0_PLDONE_MASK) #define DDRPHY_PGSR0_DCDONE_MASK (0x4U) #define DDRPHY_PGSR0_DCDONE_SHIFT (2U) /*! DCDONE - Digital Delay Line (DDL) Calibration Done */ #define DDRPHY_PGSR0_DCDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DCDONE_SHIFT)) & DDRPHY_PGSR0_DCDONE_MASK) #define DDRPHY_PGSR0_ZCDONE_MASK (0x8U) #define DDRPHY_PGSR0_ZCDONE_SHIFT (3U) /*! ZCDONE - Impedance Calibration Done */ #define DDRPHY_PGSR0_ZCDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_ZCDONE_SHIFT)) & DDRPHY_PGSR0_ZCDONE_MASK) #define DDRPHY_PGSR0_DIDONE_MASK (0x10U) #define DDRPHY_PGSR0_DIDONE_SHIFT (4U) /*! DIDONE - DRAM Initialization Done */ #define DDRPHY_PGSR0_DIDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DIDONE_SHIFT)) & DDRPHY_PGSR0_DIDONE_MASK) #define DDRPHY_PGSR0_WLDONE_MASK (0x20U) #define DDRPHY_PGSR0_WLDONE_SHIFT (5U) /*! WLDONE - Write Leveling Done */ #define DDRPHY_PGSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLDONE_SHIFT)) & DDRPHY_PGSR0_WLDONE_MASK) #define DDRPHY_PGSR0_QSGDONE_MASK (0x40U) #define DDRPHY_PGSR0_QSGDONE_SHIFT (6U) /*! QSGDONE - DQS Gate Training Done */ #define DDRPHY_PGSR0_QSGDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_QSGDONE_SHIFT)) & DDRPHY_PGSR0_QSGDONE_MASK) #define DDRPHY_PGSR0_WLADONE_MASK (0x80U) #define DDRPHY_PGSR0_WLADONE_SHIFT (7U) /*! WLADONE - Write Leveling Adjustment Done */ #define DDRPHY_PGSR0_WLADONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLADONE_SHIFT)) & DDRPHY_PGSR0_WLADONE_MASK) #define DDRPHY_PGSR0_RDDONE_MASK (0x100U) #define DDRPHY_PGSR0_RDDONE_SHIFT (8U) /*! RDDONE - Read Bit Deskew Done */ #define DDRPHY_PGSR0_RDDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_RDDONE_SHIFT)) & DDRPHY_PGSR0_RDDONE_MASK) #define DDRPHY_PGSR0_WDDONE_MASK (0x200U) #define DDRPHY_PGSR0_WDDONE_SHIFT (9U) /*! WDDONE - Write Bit Deskew Done */ #define DDRPHY_PGSR0_WDDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WDDONE_SHIFT)) & DDRPHY_PGSR0_WDDONE_MASK) #define DDRPHY_PGSR0_REDONE_MASK (0x400U) #define DDRPHY_PGSR0_REDONE_SHIFT (10U) /*! REDONE - Read Eye Training Done */ #define DDRPHY_PGSR0_REDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_REDONE_SHIFT)) & DDRPHY_PGSR0_REDONE_MASK) #define DDRPHY_PGSR0_WEDONE_MASK (0x800U) #define DDRPHY_PGSR0_WEDONE_SHIFT (11U) /*! WEDONE - Write Eye Training Done */ #define DDRPHY_PGSR0_WEDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WEDONE_SHIFT)) & DDRPHY_PGSR0_WEDONE_MASK) #define DDRPHY_PGSR0_CADONE_MASK (0x1000U) #define DDRPHY_PGSR0_CADONE_SHIFT (12U) /*! CADONE - CA Training Done */ #define DDRPHY_PGSR0_CADONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_CADONE_SHIFT)) & DDRPHY_PGSR0_CADONE_MASK) #define DDRPHY_PGSR0_SRDDONE_MASK (0x2000U) #define DDRPHY_PGSR0_SRDDONE_SHIFT (13U) /*! SRDDONE - Static Read Done */ #define DDRPHY_PGSR0_SRDDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_SRDDONE_SHIFT)) & DDRPHY_PGSR0_SRDDONE_MASK) #define DDRPHY_PGSR0_VDONE_MASK (0x4000U) #define DDRPHY_PGSR0_VDONE_SHIFT (14U) /*! VDONE - VREF Training Done */ #define DDRPHY_PGSR0_VDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_VDONE_SHIFT)) & DDRPHY_PGSR0_VDONE_MASK) #define DDRPHY_PGSR0_DQS2DQDONE_MASK (0x8000U) #define DDRPHY_PGSR0_DQS2DQDONE_SHIFT (15U) /*! DQS2DQDONE - Write DQS2DQ Training Done */ #define DDRPHY_PGSR0_DQS2DQDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DQS2DQDONE_SHIFT)) & DDRPHY_PGSR0_DQS2DQDONE_MASK) #define DDRPHY_PGSR0_RESERVED_17_16_MASK (0x30000U) #define DDRPHY_PGSR0_RESERVED_17_16_SHIFT (16U) /*! RESERVED_17_16 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGSR0_RESERVED_17_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_RESERVED_17_16_SHIFT)) & DDRPHY_PGSR0_RESERVED_17_16_MASK) #define DDRPHY_PGSR0_DQS2DQERR_MASK (0x40000U) #define DDRPHY_PGSR0_DQS2DQERR_SHIFT (18U) /*! DQS2DQERR - Write DQS2DQ Training Error */ #define DDRPHY_PGSR0_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DQS2DQERR_SHIFT)) & DDRPHY_PGSR0_DQS2DQERR_MASK) #define DDRPHY_PGSR0_VERR_MASK (0x80000U) #define DDRPHY_PGSR0_VERR_SHIFT (19U) /*! VERR - VREF Training Error */ #define DDRPHY_PGSR0_VERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_VERR_SHIFT)) & DDRPHY_PGSR0_VERR_MASK) #define DDRPHY_PGSR0_ZCERR_MASK (0x100000U) #define DDRPHY_PGSR0_ZCERR_SHIFT (20U) /*! ZCERR - Impedance Calibration Error */ #define DDRPHY_PGSR0_ZCERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_ZCERR_SHIFT)) & DDRPHY_PGSR0_ZCERR_MASK) #define DDRPHY_PGSR0_WLERR_MASK (0x200000U) #define DDRPHY_PGSR0_WLERR_SHIFT (21U) /*! WLERR - Write Leveling Error */ #define DDRPHY_PGSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLERR_SHIFT)) & DDRPHY_PGSR0_WLERR_MASK) #define DDRPHY_PGSR0_QSGERR_MASK (0x400000U) #define DDRPHY_PGSR0_QSGERR_SHIFT (22U) /*! QSGERR - DQS Gate Training Error */ #define DDRPHY_PGSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_QSGERR_SHIFT)) & DDRPHY_PGSR0_QSGERR_MASK) #define DDRPHY_PGSR0_WLAERR_MASK (0x800000U) #define DDRPHY_PGSR0_WLAERR_SHIFT (23U) /*! WLAERR - Write Leveling Adjustment Error */ #define DDRPHY_PGSR0_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLAERR_SHIFT)) & DDRPHY_PGSR0_WLAERR_MASK) #define DDRPHY_PGSR0_RDERR_MASK (0x1000000U) #define DDRPHY_PGSR0_RDERR_SHIFT (24U) /*! RDERR - Read Bit Deskew Error */ #define DDRPHY_PGSR0_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_RDERR_SHIFT)) & DDRPHY_PGSR0_RDERR_MASK) #define DDRPHY_PGSR0_WDERR_MASK (0x2000000U) #define DDRPHY_PGSR0_WDERR_SHIFT (25U) /*! WDERR - Write Bit Deskew Error */ #define DDRPHY_PGSR0_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WDERR_SHIFT)) & DDRPHY_PGSR0_WDERR_MASK) #define DDRPHY_PGSR0_REERR_MASK (0x4000000U) #define DDRPHY_PGSR0_REERR_SHIFT (26U) /*! REERR - Read Eye Training Error */ #define DDRPHY_PGSR0_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_REERR_SHIFT)) & DDRPHY_PGSR0_REERR_MASK) #define DDRPHY_PGSR0_WEERR_MASK (0x8000000U) #define DDRPHY_PGSR0_WEERR_SHIFT (27U) /*! WEERR - Write Eye Training Error */ #define DDRPHY_PGSR0_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WEERR_SHIFT)) & DDRPHY_PGSR0_WEERR_MASK) #define DDRPHY_PGSR0_CAERR_MASK (0x10000000U) #define DDRPHY_PGSR0_CAERR_SHIFT (28U) /*! CAERR - CA Training Error */ #define DDRPHY_PGSR0_CAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_CAERR_SHIFT)) & DDRPHY_PGSR0_CAERR_MASK) #define DDRPHY_PGSR0_CAWRN_MASK (0x20000000U) #define DDRPHY_PGSR0_CAWRN_SHIFT (29U) /*! CAWRN - CA Training Warning */ #define DDRPHY_PGSR0_CAWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_CAWRN_SHIFT)) & DDRPHY_PGSR0_CAWRN_MASK) #define DDRPHY_PGSR0_SRDERR_MASK (0x40000000U) #define DDRPHY_PGSR0_SRDERR_SHIFT (30U) /*! SRDERR - Static Read Error */ #define DDRPHY_PGSR0_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_SRDERR_SHIFT)) & DDRPHY_PGSR0_SRDERR_MASK) #define DDRPHY_PGSR0_APLOCK_MASK (0x80000000U) #define DDRPHY_PGSR0_APLOCK_SHIFT (31U) /*! APLOCK - AC PLL Lock */ #define DDRPHY_PGSR0_APLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_APLOCK_SHIFT)) & DDRPHY_PGSR0_APLOCK_MASK) /*! @} */ /*! @name PGSR1 - PHY General Status Register 1 */ /*! @{ */ #define DDRPHY_PGSR1_DLTDONE_MASK (0x1U) #define DDRPHY_PGSR1_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done for AC macro 0 */ #define DDRPHY_PGSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_DLTDONE_SHIFT)) & DDRPHY_PGSR1_DLTDONE_MASK) #define DDRPHY_PGSR1_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_PGSR1_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code for AC macro 0 */ #define DDRPHY_PGSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_DLTCODE_SHIFT)) & DDRPHY_PGSR1_DLTCODE_MASK) #define DDRPHY_PGSR1_RESERVED_29_25_MASK (0x3E000000U) #define DDRPHY_PGSR1_RESERVED_29_25_SHIFT (25U) /*! RESERVED_29_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGSR1_RESERVED_29_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_RESERVED_29_25_SHIFT)) & DDRPHY_PGSR1_RESERVED_29_25_MASK) #define DDRPHY_PGSR1_VTSTOP_MASK (0x40000000U) #define DDRPHY_PGSR1_VTSTOP_SHIFT (30U) /*! VTSTOP - VT Stop */ #define DDRPHY_PGSR1_VTSTOP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_VTSTOP_SHIFT)) & DDRPHY_PGSR1_VTSTOP_MASK) #define DDRPHY_PGSR1_PARERR_MASK (0x80000000U) #define DDRPHY_PGSR1_PARERR_SHIFT (31U) /*! PARERR - RDIMM Parity Error */ #define DDRPHY_PGSR1_PARERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_PARERR_SHIFT)) & DDRPHY_PGSR1_PARERR_MASK) /*! @} */ /*! @name PGSR2 - PHY General Status Register 2 */ /*! @{ */ #define DDRPHY_PGSR2_DLTDONE_MASK (0x1U) #define DDRPHY_PGSR2_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done for AC macro 1 */ #define DDRPHY_PGSR2_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR2_DLTDONE_SHIFT)) & DDRPHY_PGSR2_DLTDONE_MASK) #define DDRPHY_PGSR2_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_PGSR2_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code for AC macro 1 */ #define DDRPHY_PGSR2_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR2_DLTCODE_SHIFT)) & DDRPHY_PGSR2_DLTCODE_MASK) #define DDRPHY_PGSR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_PGSR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PGSR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR2_RESERVED_31_25_SHIFT)) & DDRPHY_PGSR2_RESERVED_31_25_MASK) /*! @} */ /*! @name PTR0 - PHY Timing Register 0 */ /*! @{ */ #define DDRPHY_PTR0_tPHYRST_MASK (0x3FU) #define DDRPHY_PTR0_tPHYRST_SHIFT (0U) /*! tPHYRST - PHY Reset Time */ #define DDRPHY_PTR0_tPHYRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR0_tPHYRST_SHIFT)) & DDRPHY_PTR0_tPHYRST_MASK) #define DDRPHY_PTR0_tPLLGS_MASK (0x1FFFC0U) #define DDRPHY_PTR0_tPLLGS_SHIFT (6U) /*! tPLLGS - PLL Gear Shift Time */ #define DDRPHY_PTR0_tPLLGS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR0_tPLLGS_SHIFT)) & DDRPHY_PTR0_tPLLGS_MASK) #define DDRPHY_PTR0_tPLLPD_MASK (0xFFE00000U) #define DDRPHY_PTR0_tPLLPD_SHIFT (21U) /*! tPLLPD - PLL Power-Down Time */ #define DDRPHY_PTR0_tPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR0_tPLLPD_SHIFT)) & DDRPHY_PTR0_tPLLPD_MASK) /*! @} */ /*! @name PTR1 - PHY Timing Register 1 */ /*! @{ */ #define DDRPHY_PTR1_tPLLRST_MASK (0x1FFFU) #define DDRPHY_PTR1_tPLLRST_SHIFT (0U) /*! tPLLRST - PLL Reset Time */ #define DDRPHY_PTR1_tPLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR1_tPLLRST_SHIFT)) & DDRPHY_PTR1_tPLLRST_MASK) #define DDRPHY_PTR1_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_PTR1_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Returns zeroes on reads. */ #define DDRPHY_PTR1_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR1_RESERVED_15_13_SHIFT)) & DDRPHY_PTR1_RESERVED_15_13_MASK) #define DDRPHY_PTR1_tPLLLOCK_MASK (0xFFFF0000U) #define DDRPHY_PTR1_tPLLLOCK_SHIFT (16U) /*! tPLLLOCK - PLL Lock Time */ #define DDRPHY_PTR1_tPLLLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR1_tPLLLOCK_SHIFT)) & DDRPHY_PTR1_tPLLLOCK_MASK) /*! @} */ /*! @name PTR2 - PHY Timing Register 2 */ /*! @{ */ #define DDRPHY_PTR2_tCALON_MASK (0x1FU) #define DDRPHY_PTR2_tCALON_SHIFT (0U) /*! tCALON - Calibration On Time */ #define DDRPHY_PTR2_tCALON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tCALON_SHIFT)) & DDRPHY_PTR2_tCALON_MASK) #define DDRPHY_PTR2_tCALS_MASK (0x3E0U) #define DDRPHY_PTR2_tCALS_SHIFT (5U) /*! tCALS - Calibration Setup Time */ #define DDRPHY_PTR2_tCALS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tCALS_SHIFT)) & DDRPHY_PTR2_tCALS_MASK) #define DDRPHY_PTR2_tCALH_MASK (0x7C00U) #define DDRPHY_PTR2_tCALH_SHIFT (10U) /*! tCALH - Calibration Hold Time */ #define DDRPHY_PTR2_tCALH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tCALH_SHIFT)) & DDRPHY_PTR2_tCALH_MASK) #define DDRPHY_PTR2_tWLDLYS_MASK (0xF8000U) #define DDRPHY_PTR2_tWLDLYS_SHIFT (15U) /*! tWLDLYS - Write Leveling Delay Settling Time */ #define DDRPHY_PTR2_tWLDLYS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tWLDLYS_SHIFT)) & DDRPHY_PTR2_tWLDLYS_MASK) #define DDRPHY_PTR2_RESERVED_31_20_MASK (0xFFF00000U) #define DDRPHY_PTR2_RESERVED_31_20_SHIFT (20U) /*! RESERVED_31_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_PTR2_RESERVED_31_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_RESERVED_31_20_SHIFT)) & DDRPHY_PTR2_RESERVED_31_20_MASK) /*! @} */ /*! @name PTR3 - PHY Timing Register 3 */ /*! @{ */ #define DDRPHY_PTR3_tDINIT0_MASK (0x7FFFFFU) #define DDRPHY_PTR3_tDINIT0_SHIFT (0U) /*! tDINIT0 - DRAM Initialization Time 0 */ #define DDRPHY_PTR3_tDINIT0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR3_tDINIT0_SHIFT)) & DDRPHY_PTR3_tDINIT0_MASK) #define DDRPHY_PTR3_RESERVED_31_23_MASK (0xFF800000U) #define DDRPHY_PTR3_RESERVED_31_23_SHIFT (23U) /*! RESERVED_31_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_PTR3_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR3_RESERVED_31_23_SHIFT)) & DDRPHY_PTR3_RESERVED_31_23_MASK) /*! @} */ /*! @name PTR4 - PHY Timing Register 4 */ /*! @{ */ #define DDRPHY_PTR4_tDINIT1_MASK (0x1FFFU) #define DDRPHY_PTR4_tDINIT1_SHIFT (0U) /*! tDINIT1 - DRAM Initialization Time 1 */ #define DDRPHY_PTR4_tDINIT1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR4_tDINIT1_SHIFT)) & DDRPHY_PTR4_tDINIT1_MASK) #define DDRPHY_PTR4_RESERVED_31_13_MASK (0xFFFFE000U) #define DDRPHY_PTR4_RESERVED_31_13_SHIFT (13U) /*! RESERVED_31_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_PTR4_RESERVED_31_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR4_RESERVED_31_13_SHIFT)) & DDRPHY_PTR4_RESERVED_31_13_MASK) /*! @} */ /*! @name PTR5 - PHY Timing Register 5 */ /*! @{ */ #define DDRPHY_PTR5_tDINIT2_MASK (0x7FFFFU) #define DDRPHY_PTR5_tDINIT2_SHIFT (0U) /*! tDINIT2 - DRAM Initialization Time 1 */ #define DDRPHY_PTR5_tDINIT2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR5_tDINIT2_SHIFT)) & DDRPHY_PTR5_tDINIT2_MASK) #define DDRPHY_PTR5_RESERVED_31_19_MASK (0xFFF80000U) #define DDRPHY_PTR5_RESERVED_31_19_SHIFT (19U) /*! RESERVED_31_19 - Reserved. Return zeroes on reads. */ #define DDRPHY_PTR5_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR5_RESERVED_31_19_SHIFT)) & DDRPHY_PTR5_RESERVED_31_19_MASK) /*! @} */ /*! @name PTR6 - PHY Timing Register 6 */ /*! @{ */ #define DDRPHY_PTR6_tDINIT3_MASK (0xFFFU) #define DDRPHY_PTR6_tDINIT3_SHIFT (0U) /*! tDINIT3 - DRAM Initialization Time 3 */ #define DDRPHY_PTR6_tDINIT3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_tDINIT3_SHIFT)) & DDRPHY_PTR6_tDINIT3_MASK) #define DDRPHY_PTR6_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_PTR6_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_PTR6_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_RESERVED_19_12_SHIFT)) & DDRPHY_PTR6_RESERVED_19_12_MASK) #define DDRPHY_PTR6_tDINIT4_MASK (0x7F00000U) #define DDRPHY_PTR6_tDINIT4_SHIFT (20U) /*! tDINIT4 - DRAM Initialization Time 4 */ #define DDRPHY_PTR6_tDINIT4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_tDINIT4_SHIFT)) & DDRPHY_PTR6_tDINIT4_MASK) #define DDRPHY_PTR6_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_PTR6_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_PTR6_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_RESERVED_31_27_SHIFT)) & DDRPHY_PTR6_RESERVED_31_27_MASK) /*! @} */ /*! @name PLLCR0 - PLL Control Register 0 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_PLLCR0_DTC_MASK (0xFU) #define DDRPHY_PLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_DTC_SHIFT)) & DDRPHY_PLLCR0_DTC_MASK) #define DDRPHY_PLLCR0_ATC_MASK (0xF0U) #define DDRPHY_PLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_ATC_SHIFT)) & DDRPHY_PLLCR0_ATC_MASK) #define DDRPHY_PLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_PLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable */ #define DDRPHY_PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_ATOEN_SHIFT)) & DDRPHY_PLLCR0_ATOEN_MASK) #define DDRPHY_PLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_PLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_PLLCR0_RESERVED_11_9_MASK) #define DDRPHY_PLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_PLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_GSHIFT_SHIFT)) & DDRPHY_PLLCR0_GSHIFT_MASK) #define DDRPHY_PLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_PLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_CPIC_SHIFT)) & DDRPHY_PLLCR0_CPIC_MASK) #define DDRPHY_PLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_PLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_CPPC_SHIFT)) & DDRPHY_PLLCR0_CPPC_MASK) #define DDRPHY_PLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_PLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_RLOCKM_SHIFT)) & DDRPHY_PLLCR0_RLOCKM_MASK) #define DDRPHY_PLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_PLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_FRQSEL_SHIFT)) & DDRPHY_PLLCR0_FRQSEL_MASK) #define DDRPHY_PLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_PLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_RSTOPM_SHIFT)) & DDRPHY_PLLCR0_RSTOPM_MASK) #define DDRPHY_PLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_PLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_PLLPD_SHIFT)) & DDRPHY_PLLCR0_PLLPD_MASK) #define DDRPHY_PLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_PLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_PLLRST_SHIFT)) & DDRPHY_PLLCR0_PLLRST_MASK) #define DDRPHY_PLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_PLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_PLLBYP_SHIFT)) & DDRPHY_PLLCR0_PLLBYP_MASK) /*! @} */ /*! @name PLLCR1 - PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_PLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_PLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_LOCKDS_SHIFT)) & DDRPHY_PLLCR1_LOCKDS_MASK) #define DDRPHY_PLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_PLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_LOCKCS_SHIFT)) & DDRPHY_PLLCR1_LOCKCS_MASK) #define DDRPHY_PLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_PLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_LOCKPS_SHIFT)) & DDRPHY_PLLCR1_LOCKPS_MASK) #define DDRPHY_PLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_PLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_BYPVDD_SHIFT)) & DDRPHY_PLLCR1_BYPVDD_MASK) #define DDRPHY_PLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_PLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_PLLCR1_BYPVREGDIG_MASK) #define DDRPHY_PLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_PLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_PLLCR1_BYPVREGCP_MASK) #define DDRPHY_PLLCR1_RESERVED_15_6_MASK (0xFFC0U) #define DDRPHY_PLLCR1_RESERVED_15_6_SHIFT (6U) /*! RESERVED_15_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_PLLCR1_RESERVED_15_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_RESERVED_15_6_SHIFT)) & DDRPHY_PLLCR1_RESERVED_15_6_MASK) #define DDRPHY_PLLCR1_PLLPROG_MASK (0xFFFF0000U) #define DDRPHY_PLLCR1_PLLPROG_SHIFT (16U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_PLLPROG_SHIFT)) & DDRPHY_PLLCR1_PLLPROG_MASK) /*! @} */ /*! @name PLLCR2 - PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_PLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_PLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name PLLCR3 - PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_PLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_PLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name PLLCR4 - PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_PLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_PLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name PLLCR5 - PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_PLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_PLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_PLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_PLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_PLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DXCCR - DATX8 Common Configuration Register */ /*! @{ */ #define DDRPHY_DXCCR_RESERVED_2_0_MASK (0x7U) #define DDRPHY_DXCCR_RESERVED_2_0_SHIFT (0U) /*! RESERVED_2_0 - Reserved. Return zeroes on reads */ #define DDRPHY_DXCCR_RESERVED_2_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RESERVED_2_0_SHIFT)) & DDRPHY_DXCCR_RESERVED_2_0_MASK) #define DDRPHY_DXCCR_DQS2DQMPER_MASK (0x78U) #define DDRPHY_DXCCR_DQS2DQMPER_SHIFT (3U) /*! DQS2DQMPER - Write DQS2DQ Training Measurement Period */ #define DDRPHY_DXCCR_DQS2DQMPER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_DQS2DQMPER_SHIFT)) & DDRPHY_DXCCR_DQS2DQMPER_MASK) #define DDRPHY_DXCCR_RESERVED_28_7_MASK (0x1FFFFF80U) #define DDRPHY_DXCCR_RESERVED_28_7_SHIFT (7U) /*! RESERVED_28_7 - Reserved. Return zeroes on reads */ #define DDRPHY_DXCCR_RESERVED_28_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RESERVED_28_7_SHIFT)) & DDRPHY_DXCCR_RESERVED_28_7_MASK) #define DDRPHY_DXCCR_RKLOOP_MASK (0x20000000U) #define DDRPHY_DXCCR_RKLOOP_SHIFT (29U) /*! RKLOOP - Rank looping (per-rank eye centering) enable */ #define DDRPHY_DXCCR_RKLOOP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RKLOOP_SHIFT)) & DDRPHY_DXCCR_RKLOOP_MASK) #define DDRPHY_DXCCR_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DXCCR_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads */ #define DDRPHY_DXCCR_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RESERVED_31_30_SHIFT)) & DDRPHY_DXCCR_RESERVED_31_30_MASK) /*! @} */ /*! @name DSGCR - DDR System General Configuration Register */ /*! @{ */ #define DDRPHY_DSGCR_PUREN_MASK (0x1U) #define DDRPHY_DSGCR_PUREN_SHIFT (0U) /*! PUREN - PHY Update Request Enable */ #define DDRPHY_DSGCR_PUREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_PUREN_SHIFT)) & DDRPHY_DSGCR_PUREN_MASK) #define DDRPHY_DSGCR_MREN_MASK (0x2U) #define DDRPHY_DSGCR_MREN_SHIFT (1U) /*! MREN - Master Request Enable */ #define DDRPHY_DSGCR_MREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_MREN_SHIFT)) & DDRPHY_DSGCR_MREN_MASK) #define DDRPHY_DSGCR_CTLZUEN_MASK (0x4U) #define DDRPHY_DSGCR_CTLZUEN_SHIFT (2U) /*! CTLZUEN - Controller Impedance Update Enable */ #define DDRPHY_DSGCR_CTLZUEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_CTLZUEN_SHIFT)) & DDRPHY_DSGCR_CTLZUEN_MASK) #define DDRPHY_DSGCR_MSTRVER_MASK (0x8U) #define DDRPHY_DSGCR_MSTRVER_SHIFT (3U) /*! MSTRVER - Master Version */ #define DDRPHY_DSGCR_MSTRVER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_MSTRVER_SHIFT)) & DDRPHY_DSGCR_MSTRVER_MASK) #define DDRPHY_DSGCR_RESERVED_4_MASK (0x10U) #define DDRPHY_DSGCR_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads */ #define DDRPHY_DSGCR_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_4_SHIFT)) & DDRPHY_DSGCR_RESERVED_4_MASK) #define DDRPHY_DSGCR_CUAEN_MASK (0x20U) #define DDRPHY_DSGCR_CUAEN_SHIFT (5U) /*! CUAEN - Controller Update Acknowledge Enable */ #define DDRPHY_DSGCR_CUAEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_CUAEN_SHIFT)) & DDRPHY_DSGCR_CUAEN_MASK) #define DDRPHY_DSGCR_PUAD_MASK (0xFC0U) #define DDRPHY_DSGCR_PUAD_SHIFT (6U) /*! PUAD - PHY Update Acknowledge Delay */ #define DDRPHY_DSGCR_PUAD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_PUAD_SHIFT)) & DDRPHY_DSGCR_PUAD_MASK) #define DDRPHY_DSGCR_DTOODT_MASK (0x1000U) #define DDRPHY_DSGCR_DTOODT_SHIFT (12U) /*! DTOODT - DTO On-Die Termination */ #define DDRPHY_DSGCR_DTOODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOODT_SHIFT)) & DDRPHY_DSGCR_DTOODT_MASK) #define DDRPHY_DSGCR_RESERVED_13_MASK (0x2000U) #define DDRPHY_DSGCR_RESERVED_13_SHIFT (13U) /*! RESERVED_13 - Reserved. Return zeroes on reads */ #define DDRPHY_DSGCR_RESERVED_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_13_SHIFT)) & DDRPHY_DSGCR_RESERVED_13_MASK) #define DDRPHY_DSGCR_DTOPDR_MASK (0x4000U) #define DDRPHY_DSGCR_DTOPDR_SHIFT (14U) /*! DTOPDR - DTO Power Down Receiver */ #define DDRPHY_DSGCR_DTOPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOPDR_SHIFT)) & DDRPHY_DSGCR_DTOPDR_MASK) #define DDRPHY_DSGCR_DTOIOM_MASK (0x8000U) #define DDRPHY_DSGCR_DTOIOM_SHIFT (15U) /*! DTOIOM - DTO I/O Mode */ #define DDRPHY_DSGCR_DTOIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOIOM_SHIFT)) & DDRPHY_DSGCR_DTOIOM_MASK) #define DDRPHY_DSGCR_DTOOE_MASK (0x10000U) #define DDRPHY_DSGCR_DTOOE_SHIFT (16U) /*! DTOOE - DTO Output Enable */ #define DDRPHY_DSGCR_DTOOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOOE_SHIFT)) & DDRPHY_DSGCR_DTOOE_MASK) #define DDRPHY_DSGCR_ATOAE_MASK (0x20000U) #define DDRPHY_DSGCR_ATOAE_SHIFT (17U) /*! ATOAE - ATO Analog Test Enable */ #define DDRPHY_DSGCR_ATOAE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_ATOAE_SHIFT)) & DDRPHY_DSGCR_ATOAE_MASK) #define DDRPHY_DSGCR_RESERVED_18_MASK (0x40000U) #define DDRPHY_DSGCR_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Return zeroes on reads. */ #define DDRPHY_DSGCR_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_18_SHIFT)) & DDRPHY_DSGCR_RESERVED_18_MASK) #define DDRPHY_DSGCR_SDRMODE_MASK (0x180000U) #define DDRPHY_DSGCR_SDRMODE_SHIFT (19U) /*! SDRMODE - Single Data Rate Mode */ #define DDRPHY_DSGCR_SDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_SDRMODE_SHIFT)) & DDRPHY_DSGCR_SDRMODE_MASK) #define DDRPHY_DSGCR_RSTOE_MASK (0x200000U) #define DDRPHY_DSGCR_RSTOE_SHIFT (21U) /*! RSTOE - SDRAM Reset Output Enable */ #define DDRPHY_DSGCR_RSTOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RSTOE_SHIFT)) & DDRPHY_DSGCR_RSTOE_MASK) #define DDRPHY_DSGCR_RESERVED_22_MASK (0x400000U) #define DDRPHY_DSGCR_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DSGCR_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_22_SHIFT)) & DDRPHY_DSGCR_RESERVED_22_MASK) #define DDRPHY_DSGCR_PHYZUEN_MASK (0x800000U) #define DDRPHY_DSGCR_PHYZUEN_SHIFT (23U) /*! PHYZUEN - PHY Impedance Update Enable */ #define DDRPHY_DSGCR_PHYZUEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_PHYZUEN_SHIFT)) & DDRPHY_DSGCR_PHYZUEN_MASK) #define DDRPHY_DSGCR_RDBICL_MASK (0x7000000U) #define DDRPHY_DSGCR_RDBICL_SHIFT (24U) /*! RDBICL - When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value. */ #define DDRPHY_DSGCR_RDBICL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RDBICL_SHIFT)) & DDRPHY_DSGCR_RDBICL_MASK) #define DDRPHY_DSGCR_RDBICLSEL_MASK (0x8000000U) #define DDRPHY_DSGCR_RDBICLSEL_SHIFT (27U) /*! RDBICLSEL - When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, * calculation will use RDBICL, otherwise use default calculation. */ #define DDRPHY_DSGCR_RDBICLSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RDBICLSEL_SHIFT)) & DDRPHY_DSGCR_RDBICLSEL_MASK) #define DDRPHY_DSGCR_RESERVED_31_28_MASK (0xF0000000U) #define DDRPHY_DSGCR_RESERVED_31_28_SHIFT (28U) /*! RESERVED_31_28 - Reserved. Return zeroes on reads. */ #define DDRPHY_DSGCR_RESERVED_31_28(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_31_28_SHIFT)) & DDRPHY_DSGCR_RESERVED_31_28_MASK) /*! @} */ /*! @name ODTCR - ODT Configuration Register */ /*! @{ */ #define DDRPHY_ODTCR_RDODT_MASK (0x1U) #define DDRPHY_ODTCR_RDODT_SHIFT (0U) /*! RDODT - Read ODT. */ #define DDRPHY_ODTCR_RDODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RDODT_SHIFT)) & DDRPHY_ODTCR_RDODT_MASK) #define DDRPHY_ODTCR_RDODT_RSVD_MASK (0xFFEU) #define DDRPHY_ODTCR_RDODT_RSVD_SHIFT (1U) /*! RDODT_RSVD - Reserved. Return zeroes on reads. */ #define DDRPHY_ODTCR_RDODT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RDODT_RSVD_SHIFT)) & DDRPHY_ODTCR_RDODT_RSVD_MASK) #define DDRPHY_ODTCR_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_ODTCR_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_ODTCR_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RESERVED_15_12_SHIFT)) & DDRPHY_ODTCR_RESERVED_15_12_MASK) #define DDRPHY_ODTCR_WRODT_MASK (0x10000U) #define DDRPHY_ODTCR_WRODT_SHIFT (16U) /*! WRODT - Write ODT. */ #define DDRPHY_ODTCR_WRODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_WRODT_SHIFT)) & DDRPHY_ODTCR_WRODT_MASK) #define DDRPHY_ODTCR_WRODT_RSVD_MASK (0xFFE0000U) #define DDRPHY_ODTCR_WRODT_RSVD_SHIFT (17U) /*! WRODT_RSVD - Reserved. Return zeroes on reads. */ #define DDRPHY_ODTCR_WRODT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_WRODT_RSVD_SHIFT)) & DDRPHY_ODTCR_WRODT_RSVD_MASK) #define DDRPHY_ODTCR_RESERVED_31_28_MASK (0xF0000000U) #define DDRPHY_ODTCR_RESERVED_31_28_SHIFT (28U) /*! RESERVED_31_28 - Reserved. Return zeroes on reads. */ #define DDRPHY_ODTCR_RESERVED_31_28(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RESERVED_31_28_SHIFT)) & DDRPHY_ODTCR_RESERVED_31_28_MASK) /*! @} */ /*! @name AACR - Anti-Aging Control Register */ /*! @{ */ #define DDRPHY_AACR_AATR_MASK (0x3FFFFFFFU) #define DDRPHY_AACR_AATR_SHIFT (0U) /*! AATR - Anti-Aging Toggle Rate */ #define DDRPHY_AACR_AATR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_AACR_AATR_SHIFT)) & DDRPHY_AACR_AATR_MASK) #define DDRPHY_AACR_AAENC_MASK (0x40000000U) #define DDRPHY_AACR_AAENC_SHIFT (30U) /*! AAENC - Anti-Aging Enable Control */ #define DDRPHY_AACR_AAENC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_AACR_AAENC_SHIFT)) & DDRPHY_AACR_AAENC_MASK) #define DDRPHY_AACR_AAOENC_MASK (0x80000000U) #define DDRPHY_AACR_AAOENC_SHIFT (31U) /*! AAOENC - Anti-Aging PAD Output Enable Control */ #define DDRPHY_AACR_AAOENC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_AACR_AAOENC_SHIFT)) & DDRPHY_AACR_AAOENC_MASK) /*! @} */ /*! @name GPR0 - General Purpose Register 0 */ /*! @{ */ #define DDRPHY_GPR0_GPR0_MASK (0xFFFFFFFFU) #define DDRPHY_GPR0_GPR0_SHIFT (0U) /*! GPR0 - General Purpose Register 0 */ #define DDRPHY_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_GPR0_GPR0_SHIFT)) & DDRPHY_GPR0_GPR0_MASK) /*! @} */ /*! @name GPR1 - General Purpose Register 1 */ /*! @{ */ #define DDRPHY_GPR1_GPR1_MASK (0xFFFFFFFFU) #define DDRPHY_GPR1_GPR1_SHIFT (0U) /*! GPR1 - General Purpose Register 1 */ #define DDRPHY_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_GPR1_GPR1_SHIFT)) & DDRPHY_GPR1_GPR1_MASK) /*! @} */ /*! @name DCR - DRAM Configuration Register */ /*! @{ */ #define DDRPHY_DCR_DDRMD_MASK (0x7U) #define DDRPHY_DCR_DDRMD_SHIFT (0U) /*! DDRMD - DDR Mode */ #define DDRPHY_DCR_DDRMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDRMD_SHIFT)) & DDRPHY_DCR_DDRMD_MASK) #define DDRPHY_DCR_DDR8BNK_MASK (0x8U) #define DDRPHY_DCR_DDR8BNK_SHIFT (3U) /*! DDR8BNK - DDR 8-Bank */ #define DDRPHY_DCR_DDR8BNK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDR8BNK_SHIFT)) & DDRPHY_DCR_DDR8BNK_MASK) #define DDRPHY_DCR_PDQ_MASK (0x70U) #define DDRPHY_DCR_PDQ_SHIFT (4U) /*! PDQ - Primary DQ (DDR3 Only) */ #define DDRPHY_DCR_PDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_PDQ_SHIFT)) & DDRPHY_DCR_PDQ_MASK) #define DDRPHY_DCR_MPRDQ_MASK (0x80U) #define DDRPHY_DCR_MPRDQ_SHIFT (7U) /*! MPRDQ - Multi-Purpose Register (MPR) DQ (DDR3 Only) */ #define DDRPHY_DCR_MPRDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_MPRDQ_SHIFT)) & DDRPHY_DCR_MPRDQ_MASK) #define DDRPHY_DCR_DDRTYPE_MASK (0x300U) #define DDRPHY_DCR_DDRTYPE_SHIFT (8U) /*! DDRTYPE - DDR Type */ #define DDRPHY_DCR_DDRTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDRTYPE_SHIFT)) & DDRPHY_DCR_DDRTYPE_MASK) #define DDRPHY_DCR_BYTEMASK_MASK (0x3FC00U) #define DDRPHY_DCR_BYTEMASK_SHIFT (10U) /*! BYTEMASK - Byte Mask */ #define DDRPHY_DCR_BYTEMASK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_BYTEMASK_SHIFT)) & DDRPHY_DCR_BYTEMASK_MASK) #define DDRPHY_DCR_RESERVED_26_18_MASK (0x7FC0000U) #define DDRPHY_DCR_RESERVED_26_18_SHIFT (18U) /*! RESERVED_26_18 - Reserved. Return zeroes on reads. */ #define DDRPHY_DCR_RESERVED_26_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_RESERVED_26_18_SHIFT)) & DDRPHY_DCR_RESERVED_26_18_MASK) #define DDRPHY_DCR_NOSRA_MASK (0x8000000U) #define DDRPHY_DCR_NOSRA_SHIFT (27U) /*! NOSRA - No Simultaneous Rank Access */ #define DDRPHY_DCR_NOSRA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_NOSRA_SHIFT)) & DDRPHY_DCR_NOSRA_MASK) #define DDRPHY_DCR_DDR2T_MASK (0x10000000U) #define DDRPHY_DCR_DDR2T_SHIFT (28U) /*! DDR2T - DDR 2T Timing */ #define DDRPHY_DCR_DDR2T(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDR2T_SHIFT)) & DDRPHY_DCR_DDR2T_MASK) #define DDRPHY_DCR_UDIMM_MASK (0x20000000U) #define DDRPHY_DCR_UDIMM_SHIFT (29U) /*! UDIMM - Un-buffered DIMM Address Mirroring */ #define DDRPHY_DCR_UDIMM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_UDIMM_SHIFT)) & DDRPHY_DCR_UDIMM_MASK) #define DDRPHY_DCR_UBG_MASK (0x40000000U) #define DDRPHY_DCR_UBG_SHIFT (30U) /*! UBG - Un-used Bank Group */ #define DDRPHY_DCR_UBG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_UBG_SHIFT)) & DDRPHY_DCR_UBG_MASK) #define DDRPHY_DCR_GEARDN_MASK (0x80000000U) #define DDRPHY_DCR_GEARDN_SHIFT (31U) /*! GEARDN - DDR4 Gear Down Timing. */ #define DDRPHY_DCR_GEARDN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_GEARDN_SHIFT)) & DDRPHY_DCR_GEARDN_MASK) /*! @} */ /*! @name DTPR0 - DRAM Timing Parameters Register 0 */ /*! @{ */ #define DDRPHY_DTPR0_tRTP_MASK (0x1FU) #define DDRPHY_DTPR0_tRTP_SHIFT (0U) /*! tRTP - Internal read to precharge command delay */ #define DDRPHY_DTPR0_tRTP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRTP_SHIFT)) & DDRPHY_DTPR0_tRTP_MASK) #define DDRPHY_DTPR0_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DTPR0_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR0_RESERVED_7_5_MASK) #define DDRPHY_DTPR0_tRP_MASK (0x7F00U) #define DDRPHY_DTPR0_tRP_SHIFT (8U) /*! tRP - Precharge command period */ #define DDRPHY_DTPR0_tRP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRP_SHIFT)) & DDRPHY_DTPR0_tRP_MASK) #define DDRPHY_DTPR0_RESERVED_15_MASK (0x8000U) #define DDRPHY_DTPR0_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR0_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_15_SHIFT)) & DDRPHY_DTPR0_RESERVED_15_MASK) #define DDRPHY_DTPR0_tRAS_MASK (0x7F0000U) #define DDRPHY_DTPR0_tRAS_SHIFT (16U) /*! tRAS - Activate to precharge command delay */ #define DDRPHY_DTPR0_tRAS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRAS_SHIFT)) & DDRPHY_DTPR0_tRAS_MASK) #define DDRPHY_DTPR0_RESERVED_23_MASK (0x800000U) #define DDRPHY_DTPR0_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR0_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_23_SHIFT)) & DDRPHY_DTPR0_RESERVED_23_MASK) #define DDRPHY_DTPR0_tRRD_MASK (0x1F000000U) #define DDRPHY_DTPR0_tRRD_SHIFT (24U) /*! tRRD - Activate to activate command delay (different banks) */ #define DDRPHY_DTPR0_tRRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRRD_SHIFT)) & DDRPHY_DTPR0_tRRD_MASK) #define DDRPHY_DTPR0_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DTPR0_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR0_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_31_29_SHIFT)) & DDRPHY_DTPR0_RESERVED_31_29_MASK) /*! @} */ /*! @name DTPR1 - DRAM Timing Parameters Register 1 */ /*! @{ */ #define DDRPHY_DTPR1_tMRD_MASK (0x1FU) #define DDRPHY_DTPR1_tMRD_SHIFT (0U) /*! tMRD - Load mode cycle time */ #define DDRPHY_DTPR1_tMRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tMRD_SHIFT)) & DDRPHY_DTPR1_tMRD_MASK) #define DDRPHY_DTPR1_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DTPR1_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR1_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR1_RESERVED_7_5_MASK) #define DDRPHY_DTPR1_tMOD_MASK (0x700U) #define DDRPHY_DTPR1_tMOD_SHIFT (8U) /*! tMOD - Load mode update delay (DDR4 and DDR3 only) */ #define DDRPHY_DTPR1_tMOD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tMOD_SHIFT)) & DDRPHY_DTPR1_tMOD_MASK) #define DDRPHY_DTPR1_RESERVED_15_11_MASK (0xF800U) #define DDRPHY_DTPR1_RESERVED_15_11_SHIFT (11U) /*! RESERVED_15_11 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR1_RESERVED_15_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_15_11_SHIFT)) & DDRPHY_DTPR1_RESERVED_15_11_MASK) #define DDRPHY_DTPR1_tFAW_MASK (0x7F0000U) #define DDRPHY_DTPR1_tFAW_SHIFT (16U) /*! tFAW - 4-bank activate period */ #define DDRPHY_DTPR1_tFAW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tFAW_SHIFT)) & DDRPHY_DTPR1_tFAW_MASK) #define DDRPHY_DTPR1_RESERVED_23_MASK (0x800000U) #define DDRPHY_DTPR1_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR1_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_23_SHIFT)) & DDRPHY_DTPR1_RESERVED_23_MASK) #define DDRPHY_DTPR1_tWLMRD_MASK (0x7F000000U) #define DDRPHY_DTPR1_tWLMRD_SHIFT (24U) /*! tWLMRD - Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. */ #define DDRPHY_DTPR1_tWLMRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tWLMRD_SHIFT)) & DDRPHY_DTPR1_tWLMRD_MASK) #define DDRPHY_DTPR1_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DTPR1_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR1_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_31_SHIFT)) & DDRPHY_DTPR1_RESERVED_31_MASK) /*! @} */ /*! @name DTPR2 - DRAM Timing Parameters Register 2 */ /*! @{ */ #define DDRPHY_DTPR2_tXS_MASK (0x3FFU) #define DDRPHY_DTPR2_tXS_SHIFT (0U) /*! tXS - Self refresh exit delay */ #define DDRPHY_DTPR2_tXS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tXS_SHIFT)) & DDRPHY_DTPR2_tXS_MASK) #define DDRPHY_DTPR2_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_DTPR2_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR2_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_RESERVED_15_10_SHIFT)) & DDRPHY_DTPR2_RESERVED_15_10_MASK) #define DDRPHY_DTPR2_tCKE_MASK (0xF0000U) #define DDRPHY_DTPR2_tCKE_SHIFT (16U) /*! tCKE - CKE minimum pulse width */ #define DDRPHY_DTPR2_tCKE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tCKE_SHIFT)) & DDRPHY_DTPR2_tCKE_MASK) #define DDRPHY_DTPR2_tCMDCKE_MASK (0xF00000U) #define DDRPHY_DTPR2_tCMDCKE_SHIFT (20U) /*! tCMDCKE - Delay from Valid command to CKE Input low (LPDDR4 mode only) */ #define DDRPHY_DTPR2_tCMDCKE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tCMDCKE_SHIFT)) & DDRPHY_DTPR2_tCMDCKE_MASK) #define DDRPHY_DTPR2_tRTODT_MASK (0x1000000U) #define DDRPHY_DTPR2_tRTODT_SHIFT (24U) /*! tRTODT - Read to ODT delay (DDR3 only) */ #define DDRPHY_DTPR2_tRTODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tRTODT_SHIFT)) & DDRPHY_DTPR2_tRTODT_MASK) #define DDRPHY_DTPR2_RESERVED_27_25_MASK (0xE000000U) #define DDRPHY_DTPR2_RESERVED_27_25_SHIFT (25U) /*! RESERVED_27_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR2_RESERVED_27_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_RESERVED_27_25_SHIFT)) & DDRPHY_DTPR2_RESERVED_27_25_MASK) #define DDRPHY_DTPR2_tRTW_MASK (0x10000000U) #define DDRPHY_DTPR2_tRTW_SHIFT (28U) /*! tRTW - Read to Write command delay. Valid values are */ #define DDRPHY_DTPR2_tRTW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tRTW_SHIFT)) & DDRPHY_DTPR2_tRTW_MASK) #define DDRPHY_DTPR2_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DTPR2_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR2_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_RESERVED_31_29_SHIFT)) & DDRPHY_DTPR2_RESERVED_31_29_MASK) /*! @} */ /*! @name DTPR3 - DRAM Timing Parameters Register 3 */ /*! @{ */ #define DDRPHY_DTPR3_TDQSCK_MASK (0x7U) #define DDRPHY_DTPR3_TDQSCK_SHIFT (0U) /*! TDQSCK - DQS output access time from CK/CK# (LPDDR2/3 only) */ #define DDRPHY_DTPR3_TDQSCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_TDQSCK_SHIFT)) & DDRPHY_DTPR3_TDQSCK_MASK) #define DDRPHY_DTPR3_RESERVED_7_3_MASK (0xF8U) #define DDRPHY_DTPR3_RESERVED_7_3_SHIFT (3U) /*! RESERVED_7_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR3_RESERVED_7_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_RESERVED_7_3_SHIFT)) & DDRPHY_DTPR3_RESERVED_7_3_MASK) #define DDRPHY_DTPR3_tDQSCKmax_MASK (0xF00U) #define DDRPHY_DTPR3_tDQSCKmax_SHIFT (8U) /*! tDQSCKmax - Maximum DQS output access time from CK/CK# (LPDDR2/3 only) */ #define DDRPHY_DTPR3_tDQSCKmax(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tDQSCKmax_SHIFT)) & DDRPHY_DTPR3_tDQSCKmax_MASK) #define DDRPHY_DTPR3_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_DTPR3_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR3_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_RESERVED_15_12_SHIFT)) & DDRPHY_DTPR3_RESERVED_15_12_MASK) #define DDRPHY_DTPR3_tDLLK_MASK (0x3FF0000U) #define DDRPHY_DTPR3_tDLLK_SHIFT (16U) /*! tDLLK - DLL locking time */ #define DDRPHY_DTPR3_tDLLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tDLLK_SHIFT)) & DDRPHY_DTPR3_tDLLK_MASK) #define DDRPHY_DTPR3_tCCD_MASK (0x1C000000U) #define DDRPHY_DTPR3_tCCD_SHIFT (26U) /*! tCCD - Read to read and write to write command delay */ #define DDRPHY_DTPR3_tCCD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tCCD_SHIFT)) & DDRPHY_DTPR3_tCCD_MASK) #define DDRPHY_DTPR3_tOFDx_MASK (0xE0000000U) #define DDRPHY_DTPR3_tOFDx_SHIFT (29U) /*! tOFDx - ODT turn-off delay extension */ #define DDRPHY_DTPR3_tOFDx(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tOFDx_SHIFT)) & DDRPHY_DTPR3_tOFDx_MASK) /*! @} */ /*! @name DTPR4 - DRAM Timing Parameters Register 4 */ /*! @{ */ #define DDRPHY_DTPR4_tXP_MASK (0x1FU) #define DDRPHY_DTPR4_tXP_SHIFT (0U) /*! tXP - Power down exit delay */ #define DDRPHY_DTPR4_tXP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tXP_SHIFT)) & DDRPHY_DTPR4_tXP_MASK) #define DDRPHY_DTPR4_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DTPR4_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR4_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR4_RESERVED_7_5_MASK) #define DDRPHY_DTPR4_tWLO_MASK (0x3F00U) #define DDRPHY_DTPR4_tWLO_SHIFT (8U) /*! tWLO - Write leveling output delay */ #define DDRPHY_DTPR4_tWLO(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tWLO_SHIFT)) & DDRPHY_DTPR4_tWLO_MASK) #define DDRPHY_DTPR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DTPR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_15_14_SHIFT)) & DDRPHY_DTPR4_RESERVED_15_14_MASK) #define DDRPHY_DTPR4_tRFC_MASK (0x3FF0000U) #define DDRPHY_DTPR4_tRFC_SHIFT (16U) /*! tRFC - Refresh-to-Refresh */ #define DDRPHY_DTPR4_tRFC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tRFC_SHIFT)) & DDRPHY_DTPR4_tRFC_MASK) #define DDRPHY_DTPR4_RESERVED_27_26_MASK (0xC000000U) #define DDRPHY_DTPR4_RESERVED_27_26_SHIFT (26U) /*! RESERVED_27_26 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR4_RESERVED_27_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_27_26_SHIFT)) & DDRPHY_DTPR4_RESERVED_27_26_MASK) #define DDRPHY_DTPR4_tAOND_tAOFD_MASK (0x30000000U) #define DDRPHY_DTPR4_tAOND_tAOFD_SHIFT (28U) /*! tAOND_tAOFD - ODT turn-on/turn-off delays (DDR2 only) */ #define DDRPHY_DTPR4_tAOND_tAOFD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tAOND_tAOFD_SHIFT)) & DDRPHY_DTPR4_tAOND_tAOFD_MASK) #define DDRPHY_DTPR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DTPR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_31_30_SHIFT)) & DDRPHY_DTPR4_RESERVED_31_30_MASK) /*! @} */ /*! @name DTPR5 - DRAM Timing Parameters Register 5 */ /*! @{ */ #define DDRPHY_DTPR5_tWTR_MASK (0x1FU) #define DDRPHY_DTPR5_tWTR_SHIFT (0U) /*! tWTR - Internal write to read command delay */ #define DDRPHY_DTPR5_tWTR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_tWTR_SHIFT)) & DDRPHY_DTPR5_tWTR_MASK) #define DDRPHY_DTPR5_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DTPR5_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR5_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR5_RESERVED_7_5_MASK) #define DDRPHY_DTPR5_tRCD_MASK (0x7F00U) #define DDRPHY_DTPR5_tRCD_SHIFT (8U) /*! tRCD - Activate to read or write delay */ #define DDRPHY_DTPR5_tRCD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_tRCD_SHIFT)) & DDRPHY_DTPR5_tRCD_MASK) #define DDRPHY_DTPR5_RESERVED_15_MASK (0x8000U) #define DDRPHY_DTPR5_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_RESERVED_15_SHIFT)) & DDRPHY_DTPR5_RESERVED_15_MASK) #define DDRPHY_DTPR5_tRC_MASK (0xFF0000U) #define DDRPHY_DTPR5_tRC_SHIFT (16U) /*! tRC - Activate to activate command delay (same bank) */ #define DDRPHY_DTPR5_tRC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_tRC_SHIFT)) & DDRPHY_DTPR5_tRC_MASK) #define DDRPHY_DTPR5_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DTPR5_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR5_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_RESERVED_31_24_SHIFT)) & DDRPHY_DTPR5_RESERVED_31_24_MASK) /*! @} */ /*! @name DTPR6 - DRAM Timing Parameters Register 6 */ /*! @{ */ #define DDRPHY_DTPR6_PUBRL_MASK (0x3FU) #define DDRPHY_DTPR6_PUBRL_SHIFT (0U) /*! PUBRL - Read Latency */ #define DDRPHY_DTPR6_PUBRL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBRL_SHIFT)) & DDRPHY_DTPR6_PUBRL_MASK) #define DDRPHY_DTPR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DTPR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_RESERVED_7_6_SHIFT)) & DDRPHY_DTPR6_RESERVED_7_6_MASK) #define DDRPHY_DTPR6_PUBWL_MASK (0x3F00U) #define DDRPHY_DTPR6_PUBWL_SHIFT (8U) /*! PUBWL - Write Latency */ #define DDRPHY_DTPR6_PUBWL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBWL_SHIFT)) & DDRPHY_DTPR6_PUBWL_MASK) #define DDRPHY_DTPR6_RESERVED_29_14_MASK (0x3FFFC000U) #define DDRPHY_DTPR6_RESERVED_29_14_SHIFT (14U) /*! RESERVED_29_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTPR6_RESERVED_29_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_RESERVED_29_14_SHIFT)) & DDRPHY_DTPR6_RESERVED_29_14_MASK) #define DDRPHY_DTPR6_PUBRLEN_MASK (0x40000000U) #define DDRPHY_DTPR6_PUBRLEN_SHIFT (30U) /*! PUBRLEN - PUB Read Latency Enable */ #define DDRPHY_DTPR6_PUBRLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBRLEN_SHIFT)) & DDRPHY_DTPR6_PUBRLEN_MASK) #define DDRPHY_DTPR6_PUBWLEN_MASK (0x80000000U) #define DDRPHY_DTPR6_PUBWLEN_SHIFT (31U) /*! PUBWLEN - PUB Write Latency Enable */ #define DDRPHY_DTPR6_PUBWLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBWLEN_SHIFT)) & DDRPHY_DTPR6_PUBWLEN_MASK) /*! @} */ /*! @name RDIMMGCR0 - RDIMM General Configuration Register 0 */ /*! @{ */ #define DDRPHY_RDIMMGCR0_RDIMM_MASK (0x1U) #define DDRPHY_RDIMMGCR0_RDIMM_SHIFT (0U) /*! RDIMM - Registered DIMM */ #define DDRPHY_RDIMMGCR0_RDIMM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RDIMM_SHIFT)) & DDRPHY_RDIMMGCR0_RDIMM_MASK) #define DDRPHY_RDIMMGCR0_ERRNOREG_MASK (0x2U) #define DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT (1U) /*! ERRNOREG - Parity Error No Registering */ #define DDRPHY_RDIMMGCR0_ERRNOREG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT)) & DDRPHY_RDIMMGCR0_ERRNOREG_MASK) #define DDRPHY_RDIMMGCR0_SOPERR_MASK (0x4U) #define DDRPHY_RDIMMGCR0_SOPERR_SHIFT (2U) /*! SOPERR - Stop on Parity Error */ #define DDRPHY_RDIMMGCR0_SOPERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_SOPERR_SHIFT)) & DDRPHY_RDIMMGCR0_SOPERR_MASK) #define DDRPHY_RDIMMGCR0_RESERVED_3_MASK (0x8U) #define DDRPHY_RDIMMGCR0_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR0_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_3_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_3_MASK) #define DDRPHY_RDIMMGCR0_RNKMRREN_MASK (0x10U) #define DDRPHY_RDIMMGCR0_RNKMRREN_SHIFT (4U) /*! RNKMRREN - Rank Mirror Enable. */ #define DDRPHY_RDIMMGCR0_RNKMRREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RNKMRREN_SHIFT)) & DDRPHY_RDIMMGCR0_RNKMRREN_MASK) #define DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_MASK (0xE0U) #define DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT (5U) /*! RNKMRREN_RSVD - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR0_RNKMRREN_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT)) & DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_MASK) #define DDRPHY_RDIMMGCR0_RESERVED_16_8_MASK (0x1FF00U) #define DDRPHY_RDIMMGCR0_RESERVED_16_8_SHIFT (8U) /*! RESERVED_16_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR0_RESERVED_16_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_16_8_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_16_8_MASK) #define DDRPHY_RDIMMGCR0_PARINIOM_MASK (0x20000U) #define DDRPHY_RDIMMGCR0_PARINIOM_SHIFT (17U) /*! PARINIOM - PAR_IN I/O Mode */ #define DDRPHY_RDIMMGCR0_PARINIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_PARINIOM_SHIFT)) & DDRPHY_RDIMMGCR0_PARINIOM_MASK) #define DDRPHY_RDIMMGCR0_LRDIMM_MASK (0x40000U) #define DDRPHY_RDIMMGCR0_LRDIMM_SHIFT (18U) /*! LRDIMM - Load Reduced DIMM */ #define DDRPHY_RDIMMGCR0_LRDIMM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_LRDIMM_SHIFT)) & DDRPHY_RDIMMGCR0_LRDIMM_MASK) #define DDRPHY_RDIMMGCR0_ERROUTODT_MASK (0x80000U) #define DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT (19U) /*! ERROUTODT - ERROUT# On-Die Termination */ #define DDRPHY_RDIMMGCR0_ERROUTODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTODT_MASK) #define DDRPHY_RDIMMGCR0_RESERVED_20_MASK (0x100000U) #define DDRPHY_RDIMMGCR0_RESERVED_20_SHIFT (20U) /*! RESERVED_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR0_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_20_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_20_MASK) #define DDRPHY_RDIMMGCR0_ERROUTPDR_MASK (0x200000U) #define DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT (21U) /*! ERROUTPDR - ERROUT# Power Down Receiver */ #define DDRPHY_RDIMMGCR0_ERROUTPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTPDR_MASK) #define DDRPHY_RDIMMGCR0_ERROUTIOM_MASK (0x400000U) #define DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT (22U) /*! ERROUTIOM - ERROUT# I/O Mode */ #define DDRPHY_RDIMMGCR0_ERROUTIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTIOM_MASK) #define DDRPHY_RDIMMGCR0_ERROUTOE_MASK (0x800000U) #define DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT (23U) /*! ERROUTOE - ERROUT# Output Enable */ #define DDRPHY_RDIMMGCR0_ERROUTOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTOE_MASK) #define DDRPHY_RDIMMGCR0_RESERVED_26_24_MASK (0x7000000U) #define DDRPHY_RDIMMGCR0_RESERVED_26_24_SHIFT (24U) /*! RESERVED_26_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR0_RESERVED_26_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_26_24_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_26_24_MASK) #define DDRPHY_RDIMMGCR0_RDIMMIOM_MASK (0x8000000U) #define DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT (27U) /*! RDIMMIOM - RDIMM Outputs I/O Mode */ #define DDRPHY_RDIMMGCR0_RDIMMIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT)) & DDRPHY_RDIMMGCR0_RDIMMIOM_MASK) #define DDRPHY_RDIMMGCR0_RESERVED_29_28_MASK (0x30000000U) #define DDRPHY_RDIMMGCR0_RESERVED_29_28_SHIFT (28U) /*! RESERVED_29_28 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR0_RESERVED_29_28(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_29_28_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_29_28_MASK) #define DDRPHY_RDIMMGCR0_QCSEN_MASK (0x40000000U) #define DDRPHY_RDIMMGCR0_QCSEN_SHIFT (30U) /*! QCSEN - RDMIMM Quad CS Enable */ #define DDRPHY_RDIMMGCR0_QCSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_QCSEN_SHIFT)) & DDRPHY_RDIMMGCR0_QCSEN_MASK) #define DDRPHY_RDIMMGCR0_RESERVED_31_MASK (0x80000000U) #define DDRPHY_RDIMMGCR0_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_31_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_31_MASK) /*! @} */ /*! @name RDIMMGCR1 - RDIMM General Configuration Register 1 */ /*! @{ */ #define DDRPHY_RDIMMGCR1_tBCSTAB_MASK (0x3FFFU) #define DDRPHY_RDIMMGCR1_tBCSTAB_SHIFT (0U) /*! tBCSTAB - Stabilization time */ #define DDRPHY_RDIMMGCR1_tBCSTAB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCSTAB_SHIFT)) & DDRPHY_RDIMMGCR1_tBCSTAB_MASK) #define DDRPHY_RDIMMGCR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_RDIMMGCR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_15_14_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_15_14_MASK) #define DDRPHY_RDIMMGCR1_tBCMRD_MASK (0x70000U) #define DDRPHY_RDIMMGCR1_tBCMRD_SHIFT (16U) /*! tBCMRD - Command word to command word programming delay */ #define DDRPHY_RDIMMGCR1_tBCMRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCMRD_SHIFT)) & DDRPHY_RDIMMGCR1_tBCMRD_MASK) #define DDRPHY_RDIMMGCR1_RESERVED_19_MASK (0x80000U) #define DDRPHY_RDIMMGCR1_RESERVED_19_SHIFT (19U) /*! RESERVED_19 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR1_RESERVED_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_19_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_19_MASK) #define DDRPHY_RDIMMGCR1_tBCMRD_L_MASK (0x700000U) #define DDRPHY_RDIMMGCR1_tBCMRD_L_SHIFT (20U) /*! tBCMRD_L - Command word to command word programming delay */ #define DDRPHY_RDIMMGCR1_tBCMRD_L(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCMRD_L_SHIFT)) & DDRPHY_RDIMMGCR1_tBCMRD_L_MASK) #define DDRPHY_RDIMMGCR1_RESERVED_23_MASK (0x800000U) #define DDRPHY_RDIMMGCR1_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR1_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_23_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_23_MASK) #define DDRPHY_RDIMMGCR1_tBCMRD_L2_MASK (0x7000000U) #define DDRPHY_RDIMMGCR1_tBCMRD_L2_SHIFT (24U) /*! tBCMRD_L2 - Command word to command word programming delay */ #define DDRPHY_RDIMMGCR1_tBCMRD_L2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCMRD_L2_SHIFT)) & DDRPHY_RDIMMGCR1_tBCMRD_L2_MASK) #define DDRPHY_RDIMMGCR1_RESERVED_27_MASK (0x8000000U) #define DDRPHY_RDIMMGCR1_RESERVED_27_SHIFT (27U) /*! RESERVED_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR1_RESERVED_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_27_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_27_MASK) #define DDRPHY_RDIMMGCR1_A17BID_MASK (0x10000000U) #define DDRPHY_RDIMMGCR1_A17BID_SHIFT (28U) /*! A17BID - Address [17] B-side Inversion Disable */ #define DDRPHY_RDIMMGCR1_A17BID(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_A17BID_SHIFT)) & DDRPHY_RDIMMGCR1_A17BID_MASK) #define DDRPHY_RDIMMGCR1_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_RDIMMGCR1_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Reserved. Return zeroes on reads. */ #define DDRPHY_RDIMMGCR1_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_31_29_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_31_29_MASK) /*! @} */ /*! @name RDIMMGCR2 - RDIMM General Configuration Register 2 */ /*! @{ */ #define DDRPHY_RDIMMGCR2_CRINIT_MASK (0xFFFFFFFFU) #define DDRPHY_RDIMMGCR2_CRINIT_SHIFT (0U) /*! CRINIT - Control Registers Initialization Enable */ #define DDRPHY_RDIMMGCR2_CRINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR2_CRINIT_SHIFT)) & DDRPHY_RDIMMGCR2_CRINIT_MASK) /*! @} */ /*! @name RDIMMCR0 - RDIMM Control Register 0 */ /*! @{ */ #define DDRPHY_RDIMMCR0_RC0_MASK (0xFU) #define DDRPHY_RDIMMCR0_RC0_SHIFT (0U) /*! RC0 - DDR4/DDR3 Control Word 0 (Global Features Control Word) */ #define DDRPHY_RDIMMCR0_RC0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC0_SHIFT)) & DDRPHY_RDIMMCR0_RC0_MASK) #define DDRPHY_RDIMMCR0_RC1_MASK (0xF0U) #define DDRPHY_RDIMMCR0_RC1_SHIFT (4U) /*! RC1 - DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) */ #define DDRPHY_RDIMMCR0_RC1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC1_SHIFT)) & DDRPHY_RDIMMCR0_RC1_MASK) #define DDRPHY_RDIMMCR0_RC2_MASK (0xF00U) #define DDRPHY_RDIMMCR0_RC2_SHIFT (8U) /*! RC2 - DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word) */ #define DDRPHY_RDIMMCR0_RC2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC2_SHIFT)) & DDRPHY_RDIMMCR0_RC2_MASK) #define DDRPHY_RDIMMCR0_RC3_MASK (0xF000U) #define DDRPHY_RDIMMCR0_RC3_SHIFT (12U) /*! RC3 - DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control * Word 3 (Command/Address Signals Driver Characteristrics Control Word) */ #define DDRPHY_RDIMMCR0_RC3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC3_SHIFT)) & DDRPHY_RDIMMCR0_RC3_MASK) #define DDRPHY_RDIMMCR0_RC4_MASK (0xF0000U) #define DDRPHY_RDIMMCR0_RC4_SHIFT (16U) /*! RC4 - DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 * Control Word 4 (Control Signals Driver Characteristics Control Word) */ #define DDRPHY_RDIMMCR0_RC4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC4_SHIFT)) & DDRPHY_RDIMMCR0_RC4_MASK) #define DDRPHY_RDIMMCR0_RC5_MASK (0xF00000U) #define DDRPHY_RDIMMCR0_RC5_SHIFT (20U) /*! RC5 - DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) */ #define DDRPHY_RDIMMCR0_RC5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC5_SHIFT)) & DDRPHY_RDIMMCR0_RC5_MASK) #define DDRPHY_RDIMMCR0_RC6_MASK (0xF000000U) #define DDRPHY_RDIMMCR0_RC6_SHIFT (24U) /*! RC6 - DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved */ #define DDRPHY_RDIMMCR0_RC6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC6_SHIFT)) & DDRPHY_RDIMMCR0_RC6_MASK) #define DDRPHY_RDIMMCR0_RC7_MASK (0xF0000000U) #define DDRPHY_RDIMMCR0_RC7_SHIFT (28U) /*! RC7 - DDR4/DDR3 Control Word 7 */ #define DDRPHY_RDIMMCR0_RC7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC7_SHIFT)) & DDRPHY_RDIMMCR0_RC7_MASK) /*! @} */ /*! @name RDIMMCR1 - RDIMM Control Register 1 */ /*! @{ */ #define DDRPHY_RDIMMCR1_RC8_MASK (0xFU) #define DDRPHY_RDIMMCR1_RC8_SHIFT (0U) /*! RC8 - DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 * (Additional Input Bus Termination Setting Control Word) */ #define DDRPHY_RDIMMCR1_RC8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC8_SHIFT)) & DDRPHY_RDIMMCR1_RC8_MASK) #define DDRPHY_RDIMMCR1_RC9_MASK (0xF0U) #define DDRPHY_RDIMMCR1_RC9_SHIFT (4U) /*! RC9 - DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) */ #define DDRPHY_RDIMMCR1_RC9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC9_SHIFT)) & DDRPHY_RDIMMCR1_RC9_MASK) #define DDRPHY_RDIMMCR1_RC10_MASK (0xF00U) #define DDRPHY_RDIMMCR1_RC10_SHIFT (8U) /*! RC10 - DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) */ #define DDRPHY_RDIMMCR1_RC10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC10_SHIFT)) & DDRPHY_RDIMMCR1_RC10_MASK) #define DDRPHY_RDIMMCR1_RC11_MASK (0xF000U) #define DDRPHY_RDIMMCR1_RC11_SHIFT (12U) /*! RC11 - DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 * Control Word 11 (Operation Voltage VDD Control Word) */ #define DDRPHY_RDIMMCR1_RC11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC11_SHIFT)) & DDRPHY_RDIMMCR1_RC11_MASK) #define DDRPHY_RDIMMCR1_RC12_MASK (0xF0000U) #define DDRPHY_RDIMMCR1_RC12_SHIFT (16U) /*! RC12 - DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved */ #define DDRPHY_RDIMMCR1_RC12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC12_SHIFT)) & DDRPHY_RDIMMCR1_RC12_MASK) #define DDRPHY_RDIMMCR1_RC13_MASK (0xF00000U) #define DDRPHY_RDIMMCR1_RC13_SHIFT (20U) /*! RC13 - DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved */ #define DDRPHY_RDIMMCR1_RC13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC13_SHIFT)) & DDRPHY_RDIMMCR1_RC13_MASK) #define DDRPHY_RDIMMCR1_RC14_MASK (0xF000000U) #define DDRPHY_RDIMMCR1_RC14_SHIFT (24U) /*! RC14 - DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved */ #define DDRPHY_RDIMMCR1_RC14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC14_SHIFT)) & DDRPHY_RDIMMCR1_RC14_MASK) #define DDRPHY_RDIMMCR1_RC15_MASK (0xF0000000U) #define DDRPHY_RDIMMCR1_RC15_SHIFT (28U) /*! RC15 - Control Word 15 */ #define DDRPHY_RDIMMCR1_RC15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC15_SHIFT)) & DDRPHY_RDIMMCR1_RC15_MASK) /*! @} */ /*! @name RDIMMCR2 - RDIMM Control Register 2 */ /*! @{ */ #define DDRPHY_RDIMMCR2_RC1X_MASK (0xFFU) #define DDRPHY_RDIMMCR2_RC1X_SHIFT (0U) /*! RC1X - Control Word RC1X */ #define DDRPHY_RDIMMCR2_RC1X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC1X_SHIFT)) & DDRPHY_RDIMMCR2_RC1X_MASK) #define DDRPHY_RDIMMCR2_RC2X_MASK (0xFF00U) #define DDRPHY_RDIMMCR2_RC2X_SHIFT (8U) /*! RC2X - Control Word RC2X */ #define DDRPHY_RDIMMCR2_RC2X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC2X_SHIFT)) & DDRPHY_RDIMMCR2_RC2X_MASK) #define DDRPHY_RDIMMCR2_RC3X_MASK (0xFF0000U) #define DDRPHY_RDIMMCR2_RC3X_SHIFT (16U) /*! RC3X - Control Word RC3X */ #define DDRPHY_RDIMMCR2_RC3X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC3X_SHIFT)) & DDRPHY_RDIMMCR2_RC3X_MASK) #define DDRPHY_RDIMMCR2_RC4X_MASK (0xFF000000U) #define DDRPHY_RDIMMCR2_RC4X_SHIFT (24U) /*! RC4X - Control Word RC4X */ #define DDRPHY_RDIMMCR2_RC4X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC4X_SHIFT)) & DDRPHY_RDIMMCR2_RC4X_MASK) /*! @} */ /*! @name RDIMMCR3 - RDIMM Control Register 3 */ /*! @{ */ #define DDRPHY_RDIMMCR3_RC5X_MASK (0xFFU) #define DDRPHY_RDIMMCR3_RC5X_SHIFT (0U) /*! RC5X - Control Word RC5X */ #define DDRPHY_RDIMMCR3_RC5X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC5X_SHIFT)) & DDRPHY_RDIMMCR3_RC5X_MASK) #define DDRPHY_RDIMMCR3_RC6X_MASK (0xFF00U) #define DDRPHY_RDIMMCR3_RC6X_SHIFT (8U) /*! RC6X - Control Word RC6X */ #define DDRPHY_RDIMMCR3_RC6X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC6X_SHIFT)) & DDRPHY_RDIMMCR3_RC6X_MASK) #define DDRPHY_RDIMMCR3_RC7X_MASK (0xFF0000U) #define DDRPHY_RDIMMCR3_RC7X_SHIFT (16U) /*! RC7X - Control Word RC7X */ #define DDRPHY_RDIMMCR3_RC7X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC7X_SHIFT)) & DDRPHY_RDIMMCR3_RC7X_MASK) #define DDRPHY_RDIMMCR3_RC8X_MASK (0xFF000000U) #define DDRPHY_RDIMMCR3_RC8X_SHIFT (24U) /*! RC8X - Control Word RC8X */ #define DDRPHY_RDIMMCR3_RC8X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC8X_SHIFT)) & DDRPHY_RDIMMCR3_RC8X_MASK) /*! @} */ /*! @name RDIMMCR4 - RDIMM Control Register 4 */ /*! @{ */ #define DDRPHY_RDIMMCR4_RC9X_MASK (0xFFU) #define DDRPHY_RDIMMCR4_RC9X_SHIFT (0U) /*! RC9X - Control Word RC9X */ #define DDRPHY_RDIMMCR4_RC9X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RC9X_SHIFT)) & DDRPHY_RDIMMCR4_RC9X_MASK) #define DDRPHY_RDIMMCR4_RCAX_MASK (0xFF00U) #define DDRPHY_RDIMMCR4_RCAX_SHIFT (8U) /*! RCAX - Control Word RC10X */ #define DDRPHY_RDIMMCR4_RCAX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RCAX_SHIFT)) & DDRPHY_RDIMMCR4_RCAX_MASK) #define DDRPHY_RDIMMCR4_RCBX_MASK (0xFF0000U) #define DDRPHY_RDIMMCR4_RCBX_SHIFT (16U) /*! RCBX - Control Word RC11X */ #define DDRPHY_RDIMMCR4_RCBX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RCBX_SHIFT)) & DDRPHY_RDIMMCR4_RCBX_MASK) #define DDRPHY_RDIMMCR4_RCXX_MASK (0xFF000000U) #define DDRPHY_RDIMMCR4_RCXX_SHIFT (24U) /*! RCXX - Reserved for future use. */ #define DDRPHY_RDIMMCR4_RCXX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RCXX_SHIFT)) & DDRPHY_RDIMMCR4_RCXX_MASK) /*! @} */ /*! @name SCHCR0 - Scheduler Command Register 0 */ /*! @{ */ #define DDRPHY_SCHCR0_SCHTRIG_MASK (0xFU) #define DDRPHY_SCHCR0_SCHTRIG_SHIFT (0U) /*! SCHTRIG - Mode Register Command Trigger */ #define DDRPHY_SCHCR0_SCHTRIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_SCHTRIG_SHIFT)) & DDRPHY_SCHCR0_SCHTRIG_MASK) #define DDRPHY_SCHCR0_CMD_MASK (0xF0U) #define DDRPHY_SCHCR0_CMD_SHIFT (4U) /*! CMD - Specifies the Command to be issued */ #define DDRPHY_SCHCR0_CMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_CMD_SHIFT)) & DDRPHY_SCHCR0_CMD_MASK) #define DDRPHY_SCHCR0_SP_CMD_MASK (0xF00U) #define DDRPHY_SCHCR0_SP_CMD_SHIFT (8U) /*! SP_CMD - Special Command codes */ #define DDRPHY_SCHCR0_SP_CMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_SP_CMD_SHIFT)) & DDRPHY_SCHCR0_SP_CMD_MASK) #define DDRPHY_SCHCR0_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_SCHCR0_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_SCHCR0_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_RESERVED_15_12_SHIFT)) & DDRPHY_SCHCR0_RESERVED_15_12_MASK) #define DDRPHY_SCHCR0_SCHDQV_MASK (0x1FF0000U) #define DDRPHY_SCHCR0_SCHDQV_SHIFT (16U) /*! SCHDQV - Scheduler Command DQ Value */ #define DDRPHY_SCHCR0_SCHDQV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_SCHDQV_SHIFT)) & DDRPHY_SCHCR0_SCHDQV_MASK) #define DDRPHY_SCHCR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_SCHCR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_SCHCR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_RESERVED_31_25_SHIFT)) & DDRPHY_SCHCR0_RESERVED_31_25_MASK) /*! @} */ /*! @name SCHCR1 - Scheduler Command Register 1 */ /*! @{ */ #define DDRPHY_SCHCR1_RESERVED_1_0_MASK (0x3U) #define DDRPHY_SCHCR1_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_SCHCR1_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_RESERVED_1_0_SHIFT)) & DDRPHY_SCHCR1_RESERVED_1_0_MASK) #define DDRPHY_SCHCR1_ALLRANK_MASK (0x4U) #define DDRPHY_SCHCR1_ALLRANK_SHIFT (2U) /*! ALLRANK - All Ranks enabled */ #define DDRPHY_SCHCR1_ALLRANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_ALLRANK_SHIFT)) & DDRPHY_SCHCR1_ALLRANK_MASK) #define DDRPHY_SCHCR1_RESERVED_3_MASK (0x8U) #define DDRPHY_SCHCR1_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_SCHCR1_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_RESERVED_3_SHIFT)) & DDRPHY_SCHCR1_RESERVED_3_MASK) #define DDRPHY_SCHCR1_SCBK_MASK (0x30U) #define DDRPHY_SCHCR1_SCBK_SHIFT (4U) /*! SCBK - Scheduler Command Bank Address */ #define DDRPHY_SCHCR1_SCBK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCBK_SHIFT)) & DDRPHY_SCHCR1_SCBK_MASK) #define DDRPHY_SCHCR1_SCBG_MASK (0xC0U) #define DDRPHY_SCHCR1_SCBG_SHIFT (6U) /*! SCBG - Scheduler Command Bank Group */ #define DDRPHY_SCHCR1_SCBG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCBG_SHIFT)) & DDRPHY_SCHCR1_SCBG_MASK) #define DDRPHY_SCHCR1_SCADDR_MASK (0xFFFFF00U) #define DDRPHY_SCHCR1_SCADDR_SHIFT (8U) /*! SCADDR - Scheduler Command Address Specifies the value to be driven on the address bus. */ #define DDRPHY_SCHCR1_SCADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCADDR_SHIFT)) & DDRPHY_SCHCR1_SCADDR_MASK) #define DDRPHY_SCHCR1_SCRNK_MASK (0xF0000000U) #define DDRPHY_SCHCR1_SCRNK_SHIFT (28U) /*! SCRNK - Scheduler Rank Address */ #define DDRPHY_SCHCR1_SCRNK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCRNK_SHIFT)) & DDRPHY_SCHCR1_SCRNK_MASK) /*! @} */ /*! @name MR0 - LPDDR4 Mode Register 0 */ /*! @{ */ #define DDRPHY_MR0_RSVD_2_0_MASK (0x7U) #define DDRPHY_MR0_RSVD_2_0_SHIFT (0U) /*! RSVD_2_0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR0_RSVD_2_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RSVD_2_0_SHIFT)) & DDRPHY_MR0_RSVD_2_0_MASK) #define DDRPHY_MR0_RZQI_MASK (0x18U) #define DDRPHY_MR0_RZQI_SHIFT (3U) /*! RZQI - Built-in Self-Test for RZQ */ #define DDRPHY_MR0_RZQI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RZQI_SHIFT)) & DDRPHY_MR0_RZQI_MASK) #define DDRPHY_MR0_RSVD_6_5_MASK (0x60U) #define DDRPHY_MR0_RSVD_6_5_SHIFT (5U) /*! RSVD_6_5 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR0_RSVD_6_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RSVD_6_5_SHIFT)) & DDRPHY_MR0_RSVD_6_5_MASK) #define DDRPHY_MR0_CATR_MASK (0x80U) #define DDRPHY_MR0_CATR_SHIFT (7U) /*! CATR - CA Terminating Rank */ #define DDRPHY_MR0_CATR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_CATR_SHIFT)) & DDRPHY_MR0_CATR_MASK) #define DDRPHY_MR0_RSVD_15_8_MASK (0xFF00U) #define DDRPHY_MR0_RSVD_15_8_SHIFT (8U) /*! RSVD_15_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR0_RSVD_15_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RSVD_15_8_SHIFT)) & DDRPHY_MR0_RSVD_15_8_MASK) #define DDRPHY_MR0_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_MR0_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RESERVED_31_16_SHIFT)) & DDRPHY_MR0_RESERVED_31_16_MASK) /*! @} */ /*! @name MR1 - LPDDR4 Mode Register 1 */ /*! @{ */ #define DDRPHY_MR1_BL_MASK (0x3U) #define DDRPHY_MR1_BL_SHIFT (0U) /*! BL - Burst Length */ #define DDRPHY_MR1_BL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_BL_SHIFT)) & DDRPHY_MR1_BL_MASK) #define DDRPHY_MR1_WRPRE_MASK (0x4U) #define DDRPHY_MR1_WRPRE_SHIFT (2U) /*! WRPRE - Write Preamble Length */ #define DDRPHY_MR1_WRPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_WRPRE_SHIFT)) & DDRPHY_MR1_WRPRE_MASK) #define DDRPHY_MR1_RDPRE_MASK (0x8U) #define DDRPHY_MR1_RDPRE_SHIFT (3U) /*! RDPRE - Read Preamble Length */ #define DDRPHY_MR1_RDPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RDPRE_SHIFT)) & DDRPHY_MR1_RDPRE_MASK) #define DDRPHY_MR1_nWR_MASK (0x70U) #define DDRPHY_MR1_nWR_SHIFT (4U) /*! nWR - Write-recovery for auto-precharge command */ #define DDRPHY_MR1_nWR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_nWR_SHIFT)) & DDRPHY_MR1_nWR_MASK) #define DDRPHY_MR1_RDPST_MASK (0x80U) #define DDRPHY_MR1_RDPST_SHIFT (7U) /*! RDPST - Read Postamble Length */ #define DDRPHY_MR1_RDPST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RDPST_SHIFT)) & DDRPHY_MR1_RDPST_MASK) #define DDRPHY_MR1_RSVD_MASK (0xFF00U) #define DDRPHY_MR1_RSVD_SHIFT (8U) /*! RSVD - Reserved. Return zeroes on reads. */ #define DDRPHY_MR1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RSVD_SHIFT)) & DDRPHY_MR1_RSVD_MASK) #define DDRPHY_MR1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_MR1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RESERVED_31_16_SHIFT)) & DDRPHY_MR1_RESERVED_31_16_MASK) /*! @} */ /*! @name MR2 - LPDDR4 Mode Register 2 */ /*! @{ */ #define DDRPHY_MR2_RL_MASK (0x7U) #define DDRPHY_MR2_RL_SHIFT (0U) /*! RL - Read Latency */ #define DDRPHY_MR2_RL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_RL_SHIFT)) & DDRPHY_MR2_RL_MASK) #define DDRPHY_MR2_WL_MASK (0x38U) #define DDRPHY_MR2_WL_SHIFT (3U) /*! WL - Write Latency */ #define DDRPHY_MR2_WL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_WL_SHIFT)) & DDRPHY_MR2_WL_MASK) #define DDRPHY_MR2_WLS_MASK (0x40U) #define DDRPHY_MR2_WLS_SHIFT (6U) /*! WLS - Write Latency Set */ #define DDRPHY_MR2_WLS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_WLS_SHIFT)) & DDRPHY_MR2_WLS_MASK) #define DDRPHY_MR2_WRL_MASK (0x80U) #define DDRPHY_MR2_WRL_SHIFT (7U) /*! WRL - Write Leveling */ #define DDRPHY_MR2_WRL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_WRL_SHIFT)) & DDRPHY_MR2_WRL_MASK) #define DDRPHY_MR2_RSVD_MASK (0xFF00U) #define DDRPHY_MR2_RSVD_SHIFT (8U) /*! RSVD - Reserved. Return zeroes on reads. */ #define DDRPHY_MR2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_RSVD_SHIFT)) & DDRPHY_MR2_RSVD_MASK) #define DDRPHY_MR2_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_MR2_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_RESERVED_31_16_SHIFT)) & DDRPHY_MR2_RESERVED_31_16_MASK) /*! @} */ /*! @name MR3 - LPDDR4 Mode Register 3 */ /*! @{ */ #define DDRPHY_MR3_PUCAL_MASK (0x1U) #define DDRPHY_MR3_PUCAL_SHIFT (0U) /*! PUCAL - Pull-up Calibration Point */ #define DDRPHY_MR3_PUCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_PUCAL_SHIFT)) & DDRPHY_MR3_PUCAL_MASK) #define DDRPHY_MR3_WRPST_MASK (0x2U) #define DDRPHY_MR3_WRPST_SHIFT (1U) /*! WRPST - Write Postamble Length */ #define DDRPHY_MR3_WRPST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_WRPST_SHIFT)) & DDRPHY_MR3_WRPST_MASK) #define DDRPHY_MR3_RSVD_MASK (0x4U) #define DDRPHY_MR3_RSVD_SHIFT (2U) /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR3_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_RSVD_SHIFT)) & DDRPHY_MR3_RSVD_MASK) #define DDRPHY_MR3_PDDS_MASK (0x38U) #define DDRPHY_MR3_PDDS_SHIFT (3U) /*! PDDS - Pull-down Drive Strength */ #define DDRPHY_MR3_PDDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_PDDS_SHIFT)) & DDRPHY_MR3_PDDS_MASK) #define DDRPHY_MR3_DBIRD_MASK (0x40U) #define DDRPHY_MR3_DBIRD_SHIFT (6U) /*! DBIRD - DBI-Read Enable */ #define DDRPHY_MR3_DBIRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_DBIRD_SHIFT)) & DDRPHY_MR3_DBIRD_MASK) #define DDRPHY_MR3_DBIWR_MASK (0x80U) #define DDRPHY_MR3_DBIWR_SHIFT (7U) /*! DBIWR - DBI-Write Enable */ #define DDRPHY_MR3_DBIWR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_DBIWR_SHIFT)) & DDRPHY_MR3_DBIWR_MASK) #define DDRPHY_MR3_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_MR3_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR3_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_RESERVED_31_8_SHIFT)) & DDRPHY_MR3_RESERVED_31_8_MASK) /*! @} */ /*! @name MR4 - LPDDR4 Mode Register 4 */ /*! @{ */ #define DDRPHY_MR4_RSVD_MASK (0xFFU) #define DDRPHY_MR4_RSVD_SHIFT (0U) /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR4_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR4_RSVD_SHIFT)) & DDRPHY_MR4_RSVD_MASK) #define DDRPHY_MR4_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_MR4_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR4_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR4_RESERVED_31_8_SHIFT)) & DDRPHY_MR4_RESERVED_31_8_MASK) /*! @} */ /*! @name MR5 - LPDDR4 Mode Register 5 */ /*! @{ */ #define DDRPHY_MR5_RSVD_MASK (0xFFU) #define DDRPHY_MR5_RSVD_SHIFT (0U) /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR5_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR5_RSVD_SHIFT)) & DDRPHY_MR5_RSVD_MASK) #define DDRPHY_MR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_MR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR5_RESERVED_31_8_SHIFT)) & DDRPHY_MR5_RESERVED_31_8_MASK) /*! @} */ /*! @name MR6 - LPDDR4 Mode Register 6 */ /*! @{ */ #define DDRPHY_MR6_RSVD_MASK (0xFFU) #define DDRPHY_MR6_RSVD_SHIFT (0U) /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR6_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR6_RSVD_SHIFT)) & DDRPHY_MR6_RSVD_MASK) #define DDRPHY_MR6_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_MR6_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR6_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR6_RESERVED_31_8_SHIFT)) & DDRPHY_MR6_RESERVED_31_8_MASK) /*! @} */ /*! @name MR7 - LPDDR4 Mode Register 7 */ /*! @{ */ #define DDRPHY_MR7_RSVD_MASK (0xFFU) #define DDRPHY_MR7_RSVD_SHIFT (0U) /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR7_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR7_RSVD_SHIFT)) & DDRPHY_MR7_RSVD_MASK) #define DDRPHY_MR7_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_MR7_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR7_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR7_RESERVED_31_8_SHIFT)) & DDRPHY_MR7_RESERVED_31_8_MASK) /*! @} */ /*! @name MR11 - LPDDR4 Mode Register 11 */ /*! @{ */ #define DDRPHY_MR11_DQODT_MASK (0x7U) #define DDRPHY_MR11_DQODT_SHIFT (0U) /*! DQODT - DQ Bus Receiver On-Die-Termination */ #define DDRPHY_MR11_DQODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_DQODT_SHIFT)) & DDRPHY_MR11_DQODT_MASK) #define DDRPHY_MR11_RSVD_3_MASK (0x8U) #define DDRPHY_MR11_RSVD_3_SHIFT (3U) /*! RSVD_3 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR11_RSVD_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RSVD_3_SHIFT)) & DDRPHY_MR11_RSVD_3_MASK) #define DDRPHY_MR11_CAODT_MASK (0x70U) #define DDRPHY_MR11_CAODT_SHIFT (4U) /*! CAODT - CA Bus Receiver On-Die-Termination */ #define DDRPHY_MR11_CAODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_CAODT_SHIFT)) & DDRPHY_MR11_CAODT_MASK) #define DDRPHY_MR11_RSVD_7_MASK (0x80U) #define DDRPHY_MR11_RSVD_7_SHIFT (7U) /*! RSVD_7 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR11_RSVD_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RSVD_7_SHIFT)) & DDRPHY_MR11_RSVD_7_MASK) #define DDRPHY_MR11_RSVD_15_8_MASK (0xFF00U) #define DDRPHY_MR11_RSVD_15_8_SHIFT (8U) /*! RSVD_15_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR11_RSVD_15_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RSVD_15_8_SHIFT)) & DDRPHY_MR11_RSVD_15_8_MASK) #define DDRPHY_MR11_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_MR11_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR11_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RESERVED_31_16_SHIFT)) & DDRPHY_MR11_RESERVED_31_16_MASK) /*! @} */ /*! @name MR12 - LPDDR4 Mode Register 12 */ /*! @{ */ #define DDRPHY_MR12_VREF_CA_MASK (0x3FU) #define DDRPHY_MR12_VREF_CA_SHIFT (0U) /*! VREF_CA - Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. */ #define DDRPHY_MR12_VREF_CA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_VREF_CA_SHIFT)) & DDRPHY_MR12_VREF_CA_MASK) #define DDRPHY_MR12_VR_CA_MASK (0x40U) #define DDRPHY_MR12_VR_CA_SHIFT (6U) /*! VR_CA - VREF_CA Range Select. */ #define DDRPHY_MR12_VR_CA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_VR_CA_SHIFT)) & DDRPHY_MR12_VR_CA_MASK) #define DDRPHY_MR12_RSVD_MASK (0x80U) #define DDRPHY_MR12_RSVD_SHIFT (7U) /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR12_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_RSVD_SHIFT)) & DDRPHY_MR12_RSVD_MASK) #define DDRPHY_MR12_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_MR12_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR12_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_RESERVED_31_8_SHIFT)) & DDRPHY_MR12_RESERVED_31_8_MASK) /*! @} */ /*! @name MR13 - LPDDR4 Mode Register 13 */ /*! @{ */ #define DDRPHY_MR13_CBT_MASK (0x1U) #define DDRPHY_MR13_CBT_SHIFT (0U) /*! CBT - Command Bus Training */ #define DDRPHY_MR13_CBT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_CBT_SHIFT)) & DDRPHY_MR13_CBT_MASK) #define DDRPHY_MR13_RPT_MASK (0x2U) #define DDRPHY_MR13_RPT_SHIFT (1U) /*! RPT - Read Preamble Training Mode */ #define DDRPHY_MR13_RPT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_RPT_SHIFT)) & DDRPHY_MR13_RPT_MASK) #define DDRPHY_MR13_VRO_MASK (0x4U) #define DDRPHY_MR13_VRO_SHIFT (2U) /*! VRO - VREF Output */ #define DDRPHY_MR13_VRO(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_VRO_SHIFT)) & DDRPHY_MR13_VRO_MASK) #define DDRPHY_MR13_VRCG_MASK (0x8U) #define DDRPHY_MR13_VRCG_SHIFT (3U) /*! VRCG - VREF Current Generator */ #define DDRPHY_MR13_VRCG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_VRCG_SHIFT)) & DDRPHY_MR13_VRCG_MASK) #define DDRPHY_MR13_RRO_MASK (0x10U) #define DDRPHY_MR13_RRO_SHIFT (4U) /*! RRO - Refresh Rate Option */ #define DDRPHY_MR13_RRO(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_RRO_SHIFT)) & DDRPHY_MR13_RRO_MASK) #define DDRPHY_MR13_DMD_MASK (0x20U) #define DDRPHY_MR13_DMD_SHIFT (5U) /*! DMD - Data Mask Enable */ #define DDRPHY_MR13_DMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_DMD_SHIFT)) & DDRPHY_MR13_DMD_MASK) #define DDRPHY_MR13_FSPWR_MASK (0x40U) #define DDRPHY_MR13_FSPWR_SHIFT (6U) /*! FSPWR - Frequency Set Point Write Enable */ #define DDRPHY_MR13_FSPWR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_FSPWR_SHIFT)) & DDRPHY_MR13_FSPWR_MASK) #define DDRPHY_MR13_FSPOP_MASK (0x80U) #define DDRPHY_MR13_FSPOP_SHIFT (7U) /*! FSPOP - Frequency Set Point Operation Mode */ #define DDRPHY_MR13_FSPOP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_FSPOP_SHIFT)) & DDRPHY_MR13_FSPOP_MASK) #define DDRPHY_MR13_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_MR13_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR13_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_RESERVED_31_8_SHIFT)) & DDRPHY_MR13_RESERVED_31_8_MASK) /*! @} */ /*! @name MR14 - LPDDR4 Mode Register 14 */ /*! @{ */ #define DDRPHY_MR14_VREF_DQ_MASK (0x3FU) #define DDRPHY_MR14_VREF_DQ_SHIFT (0U) /*! VREF_DQ - Reserved. Return zeroes on reads. */ #define DDRPHY_MR14_VREF_DQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_VREF_DQ_SHIFT)) & DDRPHY_MR14_VREF_DQ_MASK) #define DDRPHY_MR14_VR_DQ_MASK (0x40U) #define DDRPHY_MR14_VR_DQ_SHIFT (6U) /*! VR_DQ - VREFDQ Range Selects. */ #define DDRPHY_MR14_VR_DQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_VR_DQ_SHIFT)) & DDRPHY_MR14_VR_DQ_MASK) #define DDRPHY_MR14_RSVD_MASK (0x80U) #define DDRPHY_MR14_RSVD_SHIFT (7U) /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR14_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_RSVD_SHIFT)) & DDRPHY_MR14_RSVD_MASK) #define DDRPHY_MR14_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_MR14_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR14_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_RESERVED_31_8_SHIFT)) & DDRPHY_MR14_RESERVED_31_8_MASK) /*! @} */ /*! @name MR22 - LPDDR4 Mode Register 22 */ /*! @{ */ #define DDRPHY_MR22_CODT_MASK (0x7U) #define DDRPHY_MR22_CODT_SHIFT (0U) /*! CODT - Controller ODT value for VOH calibration. */ #define DDRPHY_MR22_CODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_CODT_SHIFT)) & DDRPHY_MR22_CODT_MASK) #define DDRPHY_MR22_ODTE_CK_MASK (0x8U) #define DDRPHY_MR22_ODTE_CK_SHIFT (3U) /*! ODTE_CK - ODT CK override. */ #define DDRPHY_MR22_ODTE_CK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_ODTE_CK_SHIFT)) & DDRPHY_MR22_ODTE_CK_MASK) #define DDRPHY_MR22_ODTE_CS_MASK (0x10U) #define DDRPHY_MR22_ODTE_CS_SHIFT (4U) /*! ODTE_CS - ODT CS override. */ #define DDRPHY_MR22_ODTE_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_ODTE_CS_SHIFT)) & DDRPHY_MR22_ODTE_CS_MASK) #define DDRPHY_MR22_ODTD_CA_MASK (0x20U) #define DDRPHY_MR22_ODTD_CA_SHIFT (5U) /*! ODTD_CA - CA ODT termination disable. */ #define DDRPHY_MR22_ODTD_CA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_ODTD_CA_SHIFT)) & DDRPHY_MR22_ODTD_CA_MASK) #define DDRPHY_MR22_RSVD_MASK (0xC0U) #define DDRPHY_MR22_RSVD_SHIFT (6U) /*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. */ #define DDRPHY_MR22_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_RSVD_SHIFT)) & DDRPHY_MR22_RSVD_MASK) #define DDRPHY_MR22_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_MR22_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_MR22_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_RESERVED_31_8_SHIFT)) & DDRPHY_MR22_RESERVED_31_8_MASK) /*! @} */ /*! @name DTCR0 - Data Training Configuration Register 0 */ /*! @{ */ #define DDRPHY_DTCR0_DTRPTN_MASK (0xFU) #define DDRPHY_DTCR0_DTRPTN_SHIFT (0U) /*! DTRPTN - Data Training Repeat Number */ #define DDRPHY_DTCR0_DTRPTN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTRPTN_SHIFT)) & DDRPHY_DTCR0_DTRPTN_MASK) #define DDRPHY_DTCR0_MPCWEYE_MASK (0x10U) #define DDRPHY_DTCR0_MPCWEYE_SHIFT (4U) /*! MPCWEYE - WEYE Training using MPC FIFO Commands */ #define DDRPHY_DTCR0_MPCWEYE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_MPCWEYE_SHIFT)) & DDRPHY_DTCR0_MPCWEYE_MASK) #define DDRPHY_DTCR0_RESERVED_5_MASK (0x20U) #define DDRPHY_DTCR0_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTCR0_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RESERVED_5_SHIFT)) & DDRPHY_DTCR0_RESERVED_5_MASK) #define DDRPHY_DTCR0_DTMPR_MASK (0x40U) #define DDRPHY_DTCR0_DTMPR_SHIFT (6U) /*! DTMPR - Data Training Using MPR */ #define DDRPHY_DTCR0_DTMPR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTMPR_SHIFT)) & DDRPHY_DTCR0_DTMPR_MASK) #define DDRPHY_DTCR0_DTCMPD_MASK (0x80U) #define DDRPHY_DTCR0_DTCMPD_SHIFT (7U) /*! DTCMPD - Data Training Compare Data */ #define DDRPHY_DTCR0_DTCMPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTCMPD_SHIFT)) & DDRPHY_DTCR0_DTCMPD_MASK) #define DDRPHY_DTCR0_RFSHEN_MASK (0xF00U) #define DDRPHY_DTCR0_RFSHEN_SHIFT (8U) /*! RFSHEN - Refreshes Issued During Entry to Training */ #define DDRPHY_DTCR0_RFSHEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RFSHEN_SHIFT)) & DDRPHY_DTCR0_RFSHEN_MASK) #define DDRPHY_DTCR0_DTWBDDM_MASK (0x1000U) #define DDRPHY_DTCR0_DTWBDDM_SHIFT (12U) /*! DTWBDDM - Data Training Write Bit Deskew Data Mask */ #define DDRPHY_DTCR0_DTWBDDM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTWBDDM_SHIFT)) & DDRPHY_DTCR0_DTWBDDM_MASK) #define DDRPHY_DTCR0_DTBDC_MASK (0x2000U) #define DDRPHY_DTCR0_DTBDC_SHIFT (13U) /*! DTBDC - Data Training Bit Deskew Centering */ #define DDRPHY_DTCR0_DTBDC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTBDC_SHIFT)) & DDRPHY_DTCR0_DTBDC_MASK) #define DDRPHY_DTCR0_DTRDBITR_MASK (0xC000U) #define DDRPHY_DTCR0_DTRDBITR_SHIFT (14U) /*! DTRDBITR - Data Training read DBI deskewing configuration */ #define DDRPHY_DTCR0_DTRDBITR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTRDBITR_SHIFT)) & DDRPHY_DTCR0_DTRDBITR_MASK) #define DDRPHY_DTCR0_DTDBS_MASK (0xF0000U) #define DDRPHY_DTCR0_DTDBS_SHIFT (16U) /*! DTDBS - Data Training Debug Byte Select */ #define DDRPHY_DTCR0_DTDBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDBS_SHIFT)) & DDRPHY_DTCR0_DTDBS_MASK) #define DDRPHY_DTCR0_DTDEN_MASK (0x100000U) #define DDRPHY_DTCR0_DTDEN_SHIFT (20U) /*! DTDEN - Data Training Debug Enable */ #define DDRPHY_DTCR0_DTDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDEN_SHIFT)) & DDRPHY_DTCR0_DTDEN_MASK) #define DDRPHY_DTCR0_DTDSTP_MASK (0x200000U) #define DDRPHY_DTCR0_DTDSTP_SHIFT (21U) /*! DTDSTP - Data Training Debug Step */ #define DDRPHY_DTCR0_DTDSTP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDSTP_SHIFT)) & DDRPHY_DTCR0_DTDSTP_MASK) #define DDRPHY_DTCR0_DTEXD_MASK (0x400000U) #define DDRPHY_DTCR0_DTEXD_SHIFT (22U) /*! DTEXD - Data Training Extended Write DQS */ #define DDRPHY_DTCR0_DTEXD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTEXD_SHIFT)) & DDRPHY_DTCR0_DTEXD_MASK) #define DDRPHY_DTCR0_DTEXG_MASK (0x800000U) #define DDRPHY_DTCR0_DTEXG_SHIFT (23U) /*! DTEXG - Data Training with Early/Extended Gate */ #define DDRPHY_DTCR0_DTEXG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTEXG_SHIFT)) & DDRPHY_DTCR0_DTEXG_MASK) #define DDRPHY_DTCR0_DTDRS_MASK (0x3000000U) #define DDRPHY_DTCR0_DTDRS_SHIFT (24U) /*! DTDRS - Data Training Debug Rank Select */ #define DDRPHY_DTCR0_DTDRS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDRS_SHIFT)) & DDRPHY_DTCR0_DTDRS_MASK) #define DDRPHY_DTCR0_RESERVED_27_26_MASK (0xC000000U) #define DDRPHY_DTCR0_RESERVED_27_26_SHIFT (26U) /*! RESERVED_27_26 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTCR0_RESERVED_27_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RESERVED_27_26_SHIFT)) & DDRPHY_DTCR0_RESERVED_27_26_MASK) #define DDRPHY_DTCR0_RFSHDT_MASK (0xF0000000U) #define DDRPHY_DTCR0_RFSHDT_SHIFT (28U) /*! RFSHDT - Refresh During Training */ #define DDRPHY_DTCR0_RFSHDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RFSHDT_SHIFT)) & DDRPHY_DTCR0_RFSHDT_MASK) /*! @} */ /*! @name DTCR1 - Data Training Configuration Register 1 */ /*! @{ */ #define DDRPHY_DTCR1_BSTEN_MASK (0x1U) #define DDRPHY_DTCR1_BSTEN_SHIFT (0U) /*! BSTEN - Basic Gate Training Enable */ #define DDRPHY_DTCR1_BSTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_BSTEN_SHIFT)) & DDRPHY_DTCR1_BSTEN_MASK) #define DDRPHY_DTCR1_RDLVLEN_MASK (0x2U) #define DDRPHY_DTCR1_RDLVLEN_SHIFT (1U) /*! RDLVLEN - Read Leveling Enable */ #define DDRPHY_DTCR1_RDLVLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDLVLEN_SHIFT)) & DDRPHY_DTCR1_RDLVLEN_MASK) #define DDRPHY_DTCR1_RDPRMVL_TRN_MASK (0x4U) #define DDRPHY_DTCR1_RDPRMVL_TRN_SHIFT (2U) /*! RDPRMVL_TRN - Read Preamble Training enable */ #define DDRPHY_DTCR1_RDPRMVL_TRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDPRMVL_TRN_SHIFT)) & DDRPHY_DTCR1_RDPRMVL_TRN_MASK) #define DDRPHY_DTCR1_RESERVED_3_MASK (0x8U) #define DDRPHY_DTCR1_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTCR1_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_3_SHIFT)) & DDRPHY_DTCR1_RESERVED_3_MASK) #define DDRPHY_DTCR1_RDLVLGS_MASK (0x70U) #define DDRPHY_DTCR1_RDLVLGS_SHIFT (4U) /*! RDLVLGS - Read Leveling Gate Shift */ #define DDRPHY_DTCR1_RDLVLGS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDLVLGS_SHIFT)) & DDRPHY_DTCR1_RDLVLGS_MASK) #define DDRPHY_DTCR1_RESERVED_7_MASK (0x80U) #define DDRPHY_DTCR1_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTCR1_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_7_SHIFT)) & DDRPHY_DTCR1_RESERVED_7_MASK) #define DDRPHY_DTCR1_RDLVLGDIFF_MASK (0x700U) #define DDRPHY_DTCR1_RDLVLGDIFF_SHIFT (8U) /*! RDLVLGDIFF - Read Leveling Gate Sampling Difference */ #define DDRPHY_DTCR1_RDLVLGDIFF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDLVLGDIFF_SHIFT)) & DDRPHY_DTCR1_RDLVLGDIFF_MASK) #define DDRPHY_DTCR1_RESERVED_11_MASK (0x800U) #define DDRPHY_DTCR1_RESERVED_11_SHIFT (11U) /*! RESERVED_11 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTCR1_RESERVED_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_11_SHIFT)) & DDRPHY_DTCR1_RESERVED_11_MASK) #define DDRPHY_DTCR1_DTRANK_MASK (0x3000U) #define DDRPHY_DTCR1_DTRANK_SHIFT (12U) /*! DTRANK - Data Training Rank */ #define DDRPHY_DTCR1_DTRANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_DTRANK_SHIFT)) & DDRPHY_DTCR1_DTRANK_MASK) #define DDRPHY_DTCR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DTCR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTCR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_15_14_SHIFT)) & DDRPHY_DTCR1_RESERVED_15_14_MASK) #define DDRPHY_DTCR1_RANKEN_MASK (0x10000U) #define DDRPHY_DTCR1_RANKEN_SHIFT (16U) /*! RANKEN - Rank Enable. */ #define DDRPHY_DTCR1_RANKEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RANKEN_SHIFT)) & DDRPHY_DTCR1_RANKEN_MASK) #define DDRPHY_DTCR1_RANKEN_RSVD_MASK (0xFFFE0000U) #define DDRPHY_DTCR1_RANKEN_RSVD_SHIFT (17U) /*! RANKEN_RSVD - Rank Enable. */ #define DDRPHY_DTCR1_RANKEN_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RANKEN_RSVD_SHIFT)) & DDRPHY_DTCR1_RANKEN_RSVD_MASK) /*! @} */ /*! @name DTAR0 - Data Training Address Register 0 */ /*! @{ */ #define DDRPHY_DTAR0_DTROW_MASK (0x3FFFFU) #define DDRPHY_DTAR0_DTROW_SHIFT (0U) /*! DTROW - Data Training Row Address */ #define DDRPHY_DTAR0_DTROW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_DTROW_SHIFT)) & DDRPHY_DTAR0_DTROW_MASK) #define DDRPHY_DTAR0_RESERVED_19_18_MASK (0xC0000U) #define DDRPHY_DTAR0_RESERVED_19_18_SHIFT (18U) /*! RESERVED_19_18 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTAR0_RESERVED_19_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_RESERVED_19_18_SHIFT)) & DDRPHY_DTAR0_RESERVED_19_18_MASK) #define DDRPHY_DTAR0_DTBGBK0_MASK (0xF00000U) #define DDRPHY_DTAR0_DTBGBK0_SHIFT (20U) /*! DTBGBK0 - Data Training Bank Group and Bank Address */ #define DDRPHY_DTAR0_DTBGBK0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_DTBGBK0_SHIFT)) & DDRPHY_DTAR0_DTBGBK0_MASK) #define DDRPHY_DTAR0_DTBGBK1_MASK (0xF000000U) #define DDRPHY_DTAR0_DTBGBK1_SHIFT (24U) /*! DTBGBK1 - Data Training Bank Group and Bank Address */ #define DDRPHY_DTAR0_DTBGBK1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_DTBGBK1_SHIFT)) & DDRPHY_DTAR0_DTBGBK1_MASK) #define DDRPHY_DTAR0_MPRLOC_MASK (0x30000000U) #define DDRPHY_DTAR0_MPRLOC_SHIFT (28U) /*! MPRLOC - Multi-Purpose Register (MPR) Location */ #define DDRPHY_DTAR0_MPRLOC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_MPRLOC_SHIFT)) & DDRPHY_DTAR0_MPRLOC_MASK) #define DDRPHY_DTAR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DTAR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTAR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_RESERVED_31_30_SHIFT)) & DDRPHY_DTAR0_RESERVED_31_30_MASK) /*! @} */ /*! @name DTAR1 - Data Training Address Register 1 */ /*! @{ */ #define DDRPHY_DTAR1_DTCOL0_MASK (0x1FFU) #define DDRPHY_DTAR1_DTCOL0_SHIFT (0U) /*! DTCOL0 - Data Training Column Address */ #define DDRPHY_DTAR1_DTCOL0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_DTCOL0_SHIFT)) & DDRPHY_DTAR1_DTCOL0_MASK) #define DDRPHY_DTAR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DTAR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTAR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_RESERVED_15_9_SHIFT)) & DDRPHY_DTAR1_RESERVED_15_9_MASK) #define DDRPHY_DTAR1_DTCOL1_MASK (0x1FF0000U) #define DDRPHY_DTAR1_DTCOL1_SHIFT (16U) /*! DTCOL1 - Data Training Column Address */ #define DDRPHY_DTAR1_DTCOL1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_DTCOL1_SHIFT)) & DDRPHY_DTAR1_DTCOL1_MASK) #define DDRPHY_DTAR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DTAR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTAR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_RESERVED_31_25_SHIFT)) & DDRPHY_DTAR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DTAR2 - Data Training Address Register 2 */ /*! @{ */ #define DDRPHY_DTAR2_DTCOL2_MASK (0x1FFU) #define DDRPHY_DTAR2_DTCOL2_SHIFT (0U) /*! DTCOL2 - Data Training Column Address */ #define DDRPHY_DTAR2_DTCOL2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_DTCOL2_SHIFT)) & DDRPHY_DTAR2_DTCOL2_MASK) #define DDRPHY_DTAR2_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DTAR2_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTAR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_RESERVED_15_9_SHIFT)) & DDRPHY_DTAR2_RESERVED_15_9_MASK) #define DDRPHY_DTAR2_DTCOL3_MASK (0x1FF0000U) #define DDRPHY_DTAR2_DTCOL3_SHIFT (16U) /*! DTCOL3 - Data Training Column Address */ #define DDRPHY_DTAR2_DTCOL3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_DTCOL3_SHIFT)) & DDRPHY_DTAR2_DTCOL3_MASK) #define DDRPHY_DTAR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DTAR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DTAR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_RESERVED_31_25_SHIFT)) & DDRPHY_DTAR2_RESERVED_31_25_MASK) /*! @} */ /*! @name DTDR0 - Data Training Data Register 0 */ /*! @{ */ #define DDRPHY_DTDR0_DTBYTE0_MASK (0xFFU) #define DDRPHY_DTDR0_DTBYTE0_SHIFT (0U) /*! DTBYTE0 - Data Training Data */ #define DDRPHY_DTDR0_DTBYTE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE0_SHIFT)) & DDRPHY_DTDR0_DTBYTE0_MASK) #define DDRPHY_DTDR0_DTBYTE1_MASK (0xFF00U) #define DDRPHY_DTDR0_DTBYTE1_SHIFT (8U) /*! DTBYTE1 - Data Training Data */ #define DDRPHY_DTDR0_DTBYTE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE1_SHIFT)) & DDRPHY_DTDR0_DTBYTE1_MASK) #define DDRPHY_DTDR0_DTBYTE2_MASK (0xFF0000U) #define DDRPHY_DTDR0_DTBYTE2_SHIFT (16U) /*! DTBYTE2 - Data Training Data */ #define DDRPHY_DTDR0_DTBYTE2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE2_SHIFT)) & DDRPHY_DTDR0_DTBYTE2_MASK) #define DDRPHY_DTDR0_DTBYTE3_MASK (0xFF000000U) #define DDRPHY_DTDR0_DTBYTE3_SHIFT (24U) /*! DTBYTE3 - Data Training Data */ #define DDRPHY_DTDR0_DTBYTE3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE3_SHIFT)) & DDRPHY_DTDR0_DTBYTE3_MASK) /*! @} */ /*! @name DTDR1 - Data Training Data Register 1 */ /*! @{ */ #define DDRPHY_DTDR1_DTBYTE4_MASK (0xFFU) #define DDRPHY_DTDR1_DTBYTE4_SHIFT (0U) /*! DTBYTE4 - Data Training Data */ #define DDRPHY_DTDR1_DTBYTE4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE4_SHIFT)) & DDRPHY_DTDR1_DTBYTE4_MASK) #define DDRPHY_DTDR1_DTBYTE5_MASK (0xFF00U) #define DDRPHY_DTDR1_DTBYTE5_SHIFT (8U) /*! DTBYTE5 - Data Training Data */ #define DDRPHY_DTDR1_DTBYTE5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE5_SHIFT)) & DDRPHY_DTDR1_DTBYTE5_MASK) #define DDRPHY_DTDR1_DTBYTE6_MASK (0xFF0000U) #define DDRPHY_DTDR1_DTBYTE6_SHIFT (16U) /*! DTBYTE6 - Data Training Data */ #define DDRPHY_DTDR1_DTBYTE6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE6_SHIFT)) & DDRPHY_DTDR1_DTBYTE6_MASK) #define DDRPHY_DTDR1_DTBYTE7_MASK (0xFF000000U) #define DDRPHY_DTDR1_DTBYTE7_SHIFT (24U) /*! DTBYTE7 - Data Training Data */ #define DDRPHY_DTDR1_DTBYTE7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE7_SHIFT)) & DDRPHY_DTDR1_DTBYTE7_MASK) /*! @} */ /*! @name DTEDR0 - Data Training Eye Data Register 0 */ /*! @{ */ #define DDRPHY_DTEDR0_WDQLMN_MASK (0x1FFU) #define DDRPHY_DTEDR0_WDQLMN_SHIFT (0U) /*! WDQLMN - Data Training WDQ LCDL Minimum. */ #define DDRPHY_DTEDR0_WDQLMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQLMN_SHIFT)) & DDRPHY_DTEDR0_WDQLMN_MASK) #define DDRPHY_DTEDR0_WDQLMX_MASK (0x3FE00U) #define DDRPHY_DTEDR0_WDQLMX_SHIFT (9U) /*! WDQLMX - Data Training WDQ LCDL Maximum. */ #define DDRPHY_DTEDR0_WDQLMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQLMX_SHIFT)) & DDRPHY_DTEDR0_WDQLMX_MASK) #define DDRPHY_DTEDR0_WDQBMN_MASK (0xFC0000U) #define DDRPHY_DTEDR0_WDQBMN_SHIFT (18U) /*! WDQBMN - Data Training Write BDL Shift Minimum. */ #define DDRPHY_DTEDR0_WDQBMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQBMN_SHIFT)) & DDRPHY_DTEDR0_WDQBMN_MASK) #define DDRPHY_DTEDR0_WDQBMX_MASK (0xFF000000U) #define DDRPHY_DTEDR0_WDQBMX_SHIFT (24U) /*! WDQBMX - Data Training Write BDL Shift Maximum. */ #define DDRPHY_DTEDR0_WDQBMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQBMX_SHIFT)) & DDRPHY_DTEDR0_WDQBMX_MASK) /*! @} */ /*! @name DTEDR1 - Data Training Eye Data Register 1 */ /*! @{ */ #define DDRPHY_DTEDR1_RDQSLMN_MASK (0x1FFU) #define DDRPHY_DTEDR1_RDQSLMN_SHIFT (0U) /*! RDQSLMN - Data Training RDQS LCDL Minimum. */ #define DDRPHY_DTEDR1_RDQSLMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSLMN_SHIFT)) & DDRPHY_DTEDR1_RDQSLMN_MASK) #define DDRPHY_DTEDR1_RDQSLMX_MASK (0x3FE00U) #define DDRPHY_DTEDR1_RDQSLMX_SHIFT (9U) /*! RDQSLMX - Data Training RDQS LCDL Maximum. */ #define DDRPHY_DTEDR1_RDQSLMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSLMX_SHIFT)) & DDRPHY_DTEDR1_RDQSLMX_MASK) #define DDRPHY_DTEDR1_RDQSBMN_MASK (0xFC0000U) #define DDRPHY_DTEDR1_RDQSBMN_SHIFT (18U) /*! RDQSBMN - Data Training Read BDL Shift Minimum. */ #define DDRPHY_DTEDR1_RDQSBMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSBMN_SHIFT)) & DDRPHY_DTEDR1_RDQSBMN_MASK) #define DDRPHY_DTEDR1_RDQSBMX_MASK (0xFF000000U) #define DDRPHY_DTEDR1_RDQSBMX_SHIFT (24U) /*! RDQSBMX - Data Training Read BDL Shift Maximum. */ #define DDRPHY_DTEDR1_RDQSBMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSBMX_SHIFT)) & DDRPHY_DTEDR1_RDQSBMX_MASK) /*! @} */ /*! @name DTEDR2 - Data Training Eye Data Register 2 */ /*! @{ */ #define DDRPHY_DTEDR2_RDQSNLMN_MASK (0x1FFU) #define DDRPHY_DTEDR2_RDQSNLMN_SHIFT (0U) /*! RDQSNLMN - Data Training RDQSN LCDL Minimum. */ #define DDRPHY_DTEDR2_RDQSNLMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNLMN_SHIFT)) & DDRPHY_DTEDR2_RDQSNLMN_MASK) #define DDRPHY_DTEDR2_RDQSNLMX_MASK (0x3FE00U) #define DDRPHY_DTEDR2_RDQSNLMX_SHIFT (9U) /*! RDQSNLMX - Data Training RDQSN LCDL Maximum. */ #define DDRPHY_DTEDR2_RDQSNLMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNLMX_SHIFT)) & DDRPHY_DTEDR2_RDQSNLMX_MASK) #define DDRPHY_DTEDR2_RDQSNBMN_MASK (0xFC0000U) #define DDRPHY_DTEDR2_RDQSNBMN_SHIFT (18U) /*! RDQSNBMN - Data Training Read BDL Shift Minimum. */ #define DDRPHY_DTEDR2_RDQSNBMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNBMN_SHIFT)) & DDRPHY_DTEDR2_RDQSNBMN_MASK) #define DDRPHY_DTEDR2_RDQSNBMX_MASK (0xFF000000U) #define DDRPHY_DTEDR2_RDQSNBMX_SHIFT (24U) /*! RDQSNBMX - Data Training Read BDL Shift Maximum. */ #define DDRPHY_DTEDR2_RDQSNBMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNBMX_SHIFT)) & DDRPHY_DTEDR2_RDQSNBMX_MASK) /*! @} */ /*! @name VTDR - VREF Training Data Register */ /*! @{ */ #define DDRPHY_VTDR_DVREFMN_MASK (0x3FU) #define DDRPHY_VTDR_DVREFMN_SHIFT (0U) /*! DVREFMN - DRAM DQ VREF Minimum. */ #define DDRPHY_VTDR_DVREFMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_DVREFMN_SHIFT)) & DDRPHY_VTDR_DVREFMN_MASK) #define DDRPHY_VTDR_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_VTDR_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeroes on reads. */ #define DDRPHY_VTDR_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_7_6_SHIFT)) & DDRPHY_VTDR_RESERVED_7_6_MASK) #define DDRPHY_VTDR_DVREFMX_MASK (0x3F00U) #define DDRPHY_VTDR_DVREFMX_SHIFT (8U) /*! DVREFMX - DRAM DQ VREF Maximum. */ #define DDRPHY_VTDR_DVREFMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_DVREFMX_SHIFT)) & DDRPHY_VTDR_DVREFMX_MASK) #define DDRPHY_VTDR_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_VTDR_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeroes on reads. */ #define DDRPHY_VTDR_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_15_14_SHIFT)) & DDRPHY_VTDR_RESERVED_15_14_MASK) #define DDRPHY_VTDR_HVREFMN_MASK (0x7F0000U) #define DDRPHY_VTDR_HVREFMN_SHIFT (16U) /*! HVREFMN - DRAM DQ VREF Minimum. */ #define DDRPHY_VTDR_HVREFMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_HVREFMN_SHIFT)) & DDRPHY_VTDR_HVREFMN_MASK) #define DDRPHY_VTDR_RESERVED_23_MASK (0x800000U) #define DDRPHY_VTDR_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Returns zeroes on reads. */ #define DDRPHY_VTDR_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_23_SHIFT)) & DDRPHY_VTDR_RESERVED_23_MASK) #define DDRPHY_VTDR_HVREFMX_MASK (0x7F000000U) #define DDRPHY_VTDR_HVREFMX_SHIFT (24U) /*! HVREFMX - DRAM DQ VREF Maximum. */ #define DDRPHY_VTDR_HVREFMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_HVREFMX_SHIFT)) & DDRPHY_VTDR_HVREFMX_MASK) #define DDRPHY_VTDR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_VTDR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeroes on reads. */ #define DDRPHY_VTDR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_31_SHIFT)) & DDRPHY_VTDR_RESERVED_31_MASK) /*! @} */ /*! @name CATR0 - CA Training Register 0 */ /*! @{ */ #define DDRPHY_CATR0_CA1BYTE0_MASK (0xFU) #define DDRPHY_CATR0_CA1BYTE0_SHIFT (0U) /*! CA1BYTE0 - CA_1 Response Byte Lane 0 */ #define DDRPHY_CATR0_CA1BYTE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CA1BYTE0_SHIFT)) & DDRPHY_CATR0_CA1BYTE0_MASK) #define DDRPHY_CATR0_CA1BYTE1_MASK (0xF0U) #define DDRPHY_CATR0_CA1BYTE1_SHIFT (4U) /*! CA1BYTE1 - CA_1 Response Byte Lane 1 */ #define DDRPHY_CATR0_CA1BYTE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CA1BYTE1_SHIFT)) & DDRPHY_CATR0_CA1BYTE1_MASK) #define DDRPHY_CATR0_CAADR_MASK (0x1F00U) #define DDRPHY_CATR0_CAADR_SHIFT (8U) /*! CAADR - Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA * response after Calibration command has been sent to the memory */ #define DDRPHY_CATR0_CAADR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CAADR_SHIFT)) & DDRPHY_CATR0_CAADR_MASK) #define DDRPHY_CATR0_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_CATR0_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_CATR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_RESERVED_15_13_SHIFT)) & DDRPHY_CATR0_RESERVED_15_13_MASK) #define DDRPHY_CATR0_CACD_MASK (0x1F0000U) #define DDRPHY_CATR0_CACD_SHIFT (16U) /*! CACD - Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command */ #define DDRPHY_CATR0_CACD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CACD_SHIFT)) & DDRPHY_CATR0_CACD_MASK) #define DDRPHY_CATR0_RESERVED_31_21_MASK (0xFFE00000U) #define DDRPHY_CATR0_RESERVED_31_21_SHIFT (21U) /*! RESERVED_31_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_CATR0_RESERVED_31_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_RESERVED_31_21_SHIFT)) & DDRPHY_CATR0_RESERVED_31_21_MASK) /*! @} */ /*! @name CATR1 - CA Training Register 1 */ /*! @{ */ #define DDRPHY_CATR1_CAENT_MASK (0xFU) #define DDRPHY_CATR1_CAENT_SHIFT (0U) /*! CAENT - Minimum time (in terms of number of dram clocks) for first CA calibration command after CKE is low */ #define DDRPHY_CATR1_CAENT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CAENT_SHIFT)) & DDRPHY_CATR1_CAENT_MASK) #define DDRPHY_CATR1_CAEXT_MASK (0xF0U) #define DDRPHY_CATR1_CAEXT_SHIFT (4U) /*! CAEXT - Minimum time (in terms of number of dram clocks) for CA calibration exit command after CKE is high */ #define DDRPHY_CATR1_CAEXT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CAEXT_SHIFT)) & DDRPHY_CATR1_CAEXT_MASK) #define DDRPHY_CATR1_CACKEL_MASK (0xF00U) #define DDRPHY_CATR1_CACKEL_SHIFT (8U) /*! CACKEL - Minimum time (in terms of number of dram clocks) for CKE going low after CA calibration mode is programmed */ #define DDRPHY_CATR1_CACKEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CACKEL_SHIFT)) & DDRPHY_CATR1_CACKEL_MASK) #define DDRPHY_CATR1_CACKEH_MASK (0xF000U) #define DDRPHY_CATR1_CACKEH_SHIFT (12U) /*! CACKEH - Minimum time (in terms of number of dram clocks) for CKE high after last CA calibration response is driven by memory */ #define DDRPHY_CATR1_CACKEH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CACKEH_SHIFT)) & DDRPHY_CATR1_CACKEH_MASK) #define DDRPHY_CATR1_CAMRZ_MASK (0xF0000U) #define DDRPHY_CATR1_CAMRZ_SHIFT (16U) /*! CAMRZ - Minimum time (in terms of number of dram clocks) for DRAM DQ going tristate after MRW CA exit calibration command */ #define DDRPHY_CATR1_CAMRZ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CAMRZ_SHIFT)) & DDRPHY_CATR1_CAMRZ_MASK) #define DDRPHY_CATR1_CA0BYTE0_MASK (0xF00000U) #define DDRPHY_CATR1_CA0BYTE0_SHIFT (20U) /*! CA0BYTE0 - CA_0 Response Byte Lane 0 */ #define DDRPHY_CATR1_CA0BYTE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CA0BYTE0_SHIFT)) & DDRPHY_CATR1_CA0BYTE0_MASK) #define DDRPHY_CATR1_CA0BYTE1_MASK (0xF000000U) #define DDRPHY_CATR1_CA0BYTE1_SHIFT (24U) /*! CA0BYTE1 - CA_0 Response Byte Lane 1 */ #define DDRPHY_CATR1_CA0BYTE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CA0BYTE1_SHIFT)) & DDRPHY_CATR1_CA0BYTE1_MASK) #define DDRPHY_CATR1_RESERVED_31_28_MASK (0xF0000000U) #define DDRPHY_CATR1_RESERVED_31_28_SHIFT (28U) /*! RESERVED_31_28 - Reserved. Return zeroes on reads. */ #define DDRPHY_CATR1_RESERVED_31_28(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_RESERVED_31_28_SHIFT)) & DDRPHY_CATR1_RESERVED_31_28_MASK) /*! @} */ /*! @name PGCR8 - PHY General Configuration Register 8 */ /*! @{ */ #define DDRPHY_PGCR8_BSWAPMSB_MASK (0x1FFU) #define DDRPHY_PGCR8_BSWAPMSB_SHIFT (0U) /*! BSWAPMSB - When a bit is set, it indicates that the corresponding PHY byte lane is connected to * MSByte of the LPDDR4 DRAM 16 bit instance it is connected to. */ #define DDRPHY_PGCR8_BSWAPMSB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_BSWAPMSB_SHIFT)) & DDRPHY_PGCR8_BSWAPMSB_MASK) #define DDRPHY_PGCR8_RESERVED_13_9_MASK (0x3E00U) #define DDRPHY_PGCR8_RESERVED_13_9_SHIFT (9U) /*! RESERVED_13_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_PGCR8_RESERVED_13_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_RESERVED_13_9_SHIFT)) & DDRPHY_PGCR8_RESERVED_13_9_MASK) #define DDRPHY_PGCR8_INC_DQS2DQ_EN_MASK (0x4000U) #define DDRPHY_PGCR8_INC_DQS2DQ_EN_SHIFT (14U) /*! INC_DQS2DQ_EN - Incremental DQS2DQ Training */ #define DDRPHY_PGCR8_INC_DQS2DQ_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_EN_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_EN_MASK) #define DDRPHY_PGCR8_INC_DQS2DQ_MODE_MASK (0x8000U) #define DDRPHY_PGCR8_INC_DQS2DQ_MODE_SHIFT (15U) /*! INC_DQS2DQ_MODE - Self Incremental DQS2DQ Training */ #define DDRPHY_PGCR8_INC_DQS2DQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_MODE_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_MODE_MASK) #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_MASK (0x10000U) #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_SHIFT (16U) /*! INC_DQS2DQ_RANKEN - Rank Enable */ #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_MASK) #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_MASK (0xE0000U) #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_SHIFT (17U) /*! INC_DQS2DQ_RANKEN_RSVD - Rank Enable */ #define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_MASK) #define DDRPHY_PGCR8_INC_DQS2DQ_CM_MASK (0xFF00000U) #define DDRPHY_PGCR8_INC_DQS2DQ_CM_SHIFT (20U) /*! INC_DQS2DQ_CM - Counter Cycle Multiplier */ #define DDRPHY_PGCR8_INC_DQS2DQ_CM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_CM_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_CM_MASK) #define DDRPHY_PGCR8_INC_DQS2DQ_CF_MASK (0xF0000000U) #define DDRPHY_PGCR8_INC_DQS2DQ_CF_SHIFT (28U) /*! INC_DQS2DQ_CF - Counter Cycles Factor */ #define DDRPHY_PGCR8_INC_DQS2DQ_CF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_CF_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_CF_MASK) /*! @} */ /*! @name DQSDR0 - DQS Drift Register 0 */ /*! @{ */ #define DDRPHY_DQSDR0_DFTDTEN_MASK (0x1U) #define DDRPHY_DQSDR0_DFTDTEN_SHIFT (0U) /*! DFTDTEN - DQS Drift Detection Enable */ #define DDRPHY_DQSDR0_DFTDTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDTEN_SHIFT)) & DDRPHY_DQSDR0_DFTDTEN_MASK) #define DDRPHY_DQSDR0_DFTDTMODE_MASK (0x2U) #define DDRPHY_DQSDR0_DFTDTMODE_SHIFT (1U) /*! DFTDTMODE - DQS Drift Detection Mode */ #define DDRPHY_DQSDR0_DFTDTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDTMODE_SHIFT)) & DDRPHY_DQSDR0_DFTDTMODE_MASK) #define DDRPHY_DQSDR0_DFTUPMODE_MASK (0xCU) #define DDRPHY_DQSDR0_DFTUPMODE_SHIFT (2U) /*! DFTUPMODE - DQS Drift Update Mode */ #define DDRPHY_DQSDR0_DFTUPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTUPMODE_SHIFT)) & DDRPHY_DQSDR0_DFTUPMODE_MASK) #define DDRPHY_DQSDR0_DFTGPULSE_MASK (0xF0U) #define DDRPHY_DQSDR0_DFTGPULSE_SHIFT (4U) /*! DFTGPULSE - Gate Pulse Enable */ #define DDRPHY_DQSDR0_DFTGPULSE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTGPULSE_SHIFT)) & DDRPHY_DQSDR0_DFTGPULSE_MASK) #define DDRPHY_DQSDR0_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DQSDR0_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DQSDR0_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_RESERVED_11_8_SHIFT)) & DDRPHY_DQSDR0_RESERVED_11_8_MASK) #define DDRPHY_DQSDR0_DFTIDLRD_MASK (0xF000U) #define DDRPHY_DQSDR0_DFTIDLRD_SHIFT (12U) /*! DFTIDLRD - Drift Idle Reads */ #define DDRPHY_DQSDR0_DFTIDLRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTIDLRD_SHIFT)) & DDRPHY_DQSDR0_DFTIDLRD_MASK) #define DDRPHY_DQSDR0_DFTB2BRD_MASK (0xF0000U) #define DDRPHY_DQSDR0_DFTB2BRD_SHIFT (16U) /*! DFTB2BRD - Drift Back-to-Back Reads */ #define DDRPHY_DQSDR0_DFTB2BRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTB2BRD_SHIFT)) & DDRPHY_DQSDR0_DFTB2BRD_MASK) #define DDRPHY_DQSDR0_DFTRDSPC_MASK (0x300000U) #define DDRPHY_DQSDR0_DFTRDSPC_SHIFT (20U) /*! DFTRDSPC - Drift Read Spacing */ #define DDRPHY_DQSDR0_DFTRDSPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTRDSPC_SHIFT)) & DDRPHY_DQSDR0_DFTRDSPC_MASK) #define DDRPHY_DQSDR0_RESERVED_25_22_MASK (0x3C00000U) #define DDRPHY_DQSDR0_RESERVED_25_22_SHIFT (22U) /*! RESERVED_25_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DQSDR0_RESERVED_25_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_RESERVED_25_22_SHIFT)) & DDRPHY_DQSDR0_RESERVED_25_22_MASK) #define DDRPHY_DQSDR0_DFTDDLUP_MASK (0x4000000U) #define DDRPHY_DQSDR0_DFTDDLUP_SHIFT (26U) /*! DFTDDLUP - Drift DDL Update */ #define DDRPHY_DQSDR0_DFTDDLUP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDDLUP_SHIFT)) & DDRPHY_DQSDR0_DFTDDLUP_MASK) #define DDRPHY_DQSDR0_DFTZQUP_MASK (0x8000000U) #define DDRPHY_DQSDR0_DFTZQUP_SHIFT (27U) /*! DFTZQUP - Drift Impedance Update */ #define DDRPHY_DQSDR0_DFTZQUP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTZQUP_SHIFT)) & DDRPHY_DQSDR0_DFTZQUP_MASK) #define DDRPHY_DQSDR0_DFTDLY_MASK (0xF0000000U) #define DDRPHY_DQSDR0_DFTDLY_SHIFT (28U) /*! DFTDLY - Number of delay taps by which the DQS gate LCDL will be updated when DQS drift is detected */ #define DDRPHY_DQSDR0_DFTDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDLY_SHIFT)) & DDRPHY_DQSDR0_DFTDLY_MASK) /*! @} */ /*! @name DQSDR1 - DQS Drift Register 1 */ /*! @{ */ #define DDRPHY_DQSDR1_DFTRDIDLC_MASK (0xFFU) #define DDRPHY_DQSDR1_DFTRDIDLC_SHIFT (0U) /*! DFTRDIDLC - Drift Idle Read Cycles */ #define DDRPHY_DQSDR1_DFTRDIDLC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDIDLC_SHIFT)) & DDRPHY_DQSDR1_DFTRDIDLC_MASK) #define DDRPHY_DQSDR1_DFTRDB2BC_MASK (0xFF00U) #define DDRPHY_DQSDR1_DFTRDB2BC_SHIFT (8U) /*! DFTRDB2BC - Drift Back-to-Back Read Cycles */ #define DDRPHY_DQSDR1_DFTRDB2BC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDB2BC_SHIFT)) & DDRPHY_DQSDR1_DFTRDB2BC_MASK) #define DDRPHY_DQSDR1_DFTRDIDLF_MASK (0xF0000U) #define DDRPHY_DQSDR1_DFTRDIDLF_SHIFT (16U) /*! DFTRDIDLF - Drift Idle Read Cycles Factor */ #define DDRPHY_DQSDR1_DFTRDIDLF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDIDLF_SHIFT)) & DDRPHY_DQSDR1_DFTRDIDLF_MASK) #define DDRPHY_DQSDR1_DFTRDB2BF_MASK (0xF00000U) #define DDRPHY_DQSDR1_DFTRDB2BF_SHIFT (20U) /*! DFTRDB2BF - Drift Back-to-Back Read Cycles Factor */ #define DDRPHY_DQSDR1_DFTRDB2BF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDB2BF_SHIFT)) & DDRPHY_DQSDR1_DFTRDB2BF_MASK) #define DDRPHY_DQSDR1_DFTUPDACKC_MASK (0x1F000000U) #define DDRPHY_DQSDR1_DFTUPDACKC_SHIFT (24U) /*! DFTUPDACKC - Drift DFI Update ACK to DQS Drift FSM issuing IDLE Read Cycles */ #define DDRPHY_DQSDR1_DFTUPDACKC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTUPDACKC_SHIFT)) & DDRPHY_DQSDR1_DFTUPDACKC_MASK) #define DDRPHY_DQSDR1_DFTUPDACKF_MASK (0xE0000000U) #define DDRPHY_DQSDR1_DFTUPDACKF_SHIFT (29U) /*! DFTUPDACKF - Drift DFI Update Request ACK to DQS Drift FSM issing IDLE REad Cycles Factor */ #define DDRPHY_DQSDR1_DFTUPDACKF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTUPDACKF_SHIFT)) & DDRPHY_DQSDR1_DFTUPDACKF_MASK) /*! @} */ /*! @name DQSDR2 - DQS Drift Register 2 */ /*! @{ */ #define DDRPHY_DQSDR2_DFTMNTPRD_MASK (0xFFFFU) #define DDRPHY_DQSDR2_DFTMNTPRD_SHIFT (0U) /*! DFTMNTPRD - Drift Monitor Period */ #define DDRPHY_DQSDR2_DFTMNTPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR2_DFTMNTPRD_SHIFT)) & DDRPHY_DQSDR2_DFTMNTPRD_MASK) #define DDRPHY_DQSDR2_DFTTHRSH_MASK (0xFF0000U) #define DDRPHY_DQSDR2_DFTTHRSH_SHIFT (16U) /*! DFTTHRSH - Drift Threshold */ #define DDRPHY_DQSDR2_DFTTHRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR2_DFTTHRSH_SHIFT)) & DDRPHY_DQSDR2_DFTTHRSH_MASK) #define DDRPHY_DQSDR2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DQSDR2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DQSDR2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR2_RESERVED_31_24_SHIFT)) & DDRPHY_DQSDR2_RESERVED_31_24_MASK) /*! @} */ /*! @name DCUAR - DCU Address Register */ /*! @{ */ #define DDRPHY_DCUAR_CWADDR_W_MASK (0xFU) #define DDRPHY_DCUAR_CWADDR_W_SHIFT (0U) /*! CWADDR_W - Cache Word Address */ #define DDRPHY_DCUAR_CWADDR_W(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CWADDR_W_SHIFT)) & DDRPHY_DCUAR_CWADDR_W_MASK) #define DDRPHY_DCUAR_CSADDR_W_MASK (0xF0U) #define DDRPHY_DCUAR_CSADDR_W_SHIFT (4U) /*! CSADDR_W - Cache Slice Address */ #define DDRPHY_DCUAR_CSADDR_W(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CSADDR_W_SHIFT)) & DDRPHY_DCUAR_CSADDR_W_MASK) #define DDRPHY_DCUAR_CSEL_MASK (0x300U) #define DDRPHY_DCUAR_CSEL_SHIFT (8U) /*! CSEL - Cache Select */ #define DDRPHY_DCUAR_CSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CSEL_SHIFT)) & DDRPHY_DCUAR_CSEL_MASK) #define DDRPHY_DCUAR_INCA_MASK (0x400U) #define DDRPHY_DCUAR_INCA_SHIFT (10U) /*! INCA - Increment Address */ #define DDRPHY_DCUAR_INCA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_INCA_SHIFT)) & DDRPHY_DCUAR_INCA_MASK) #define DDRPHY_DCUAR_ATYPE_MASK (0x800U) #define DDRPHY_DCUAR_ATYPE_SHIFT (11U) /*! ATYPE - Access Type */ #define DDRPHY_DCUAR_ATYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_ATYPE_SHIFT)) & DDRPHY_DCUAR_ATYPE_MASK) #define DDRPHY_DCUAR_CWADDR_R_MASK (0xF000U) #define DDRPHY_DCUAR_CWADDR_R_SHIFT (12U) /*! CWADDR_R - Cache Word Address */ #define DDRPHY_DCUAR_CWADDR_R(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CWADDR_R_SHIFT)) & DDRPHY_DCUAR_CWADDR_R_MASK) #define DDRPHY_DCUAR_CSADDR_R_MASK (0xF0000U) #define DDRPHY_DCUAR_CSADDR_R_SHIFT (16U) /*! CSADDR_R - Cache Slice Address */ #define DDRPHY_DCUAR_CSADDR_R(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CSADDR_R_SHIFT)) & DDRPHY_DCUAR_CSADDR_R_MASK) #define DDRPHY_DCUAR_RESERVED_31_20_MASK (0xFFF00000U) #define DDRPHY_DCUAR_RESERVED_31_20_SHIFT (20U) /*! RESERVED_31_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DCUAR_RESERVED_31_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_RESERVED_31_20_SHIFT)) & DDRPHY_DCUAR_RESERVED_31_20_MASK) /*! @} */ /*! @name DCUDR - DCU Data Register */ /*! @{ */ #define DDRPHY_DCUDR_CDATA_MASK (0xFFFFFFFFU) #define DDRPHY_DCUDR_CDATA_SHIFT (0U) /*! CDATA - Cache Data */ #define DDRPHY_DCUDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUDR_CDATA_SHIFT)) & DDRPHY_DCUDR_CDATA_MASK) /*! @} */ /*! @name DCURR - DCU Run Register */ /*! @{ */ #define DDRPHY_DCURR_DINST_MASK (0xFU) #define DDRPHY_DCURR_DINST_SHIFT (0U) /*! DINST - DCU Instruction */ #define DDRPHY_DCURR_DINST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_DINST_SHIFT)) & DDRPHY_DCURR_DINST_MASK) #define DDRPHY_DCURR_SADDR_MASK (0xF0U) #define DDRPHY_DCURR_SADDR_SHIFT (4U) /*! SADDR - Start Address */ #define DDRPHY_DCURR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_SADDR_SHIFT)) & DDRPHY_DCURR_SADDR_MASK) #define DDRPHY_DCURR_EADDR_MASK (0xF00U) #define DDRPHY_DCURR_EADDR_SHIFT (8U) /*! EADDR - End Address */ #define DDRPHY_DCURR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_EADDR_SHIFT)) & DDRPHY_DCURR_EADDR_MASK) #define DDRPHY_DCURR_NFAIL_MASK (0xFF000U) #define DDRPHY_DCURR_NFAIL_SHIFT (12U) /*! NFAIL - Number of Failures */ #define DDRPHY_DCURR_NFAIL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_NFAIL_SHIFT)) & DDRPHY_DCURR_NFAIL_MASK) #define DDRPHY_DCURR_SONF_MASK (0x100000U) #define DDRPHY_DCURR_SONF_SHIFT (20U) /*! SONF - Stop On Nth Fail */ #define DDRPHY_DCURR_SONF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_SONF_SHIFT)) & DDRPHY_DCURR_SONF_MASK) #define DDRPHY_DCURR_SCOF_MASK (0x200000U) #define DDRPHY_DCURR_SCOF_SHIFT (21U) /*! SCOF - Stop Capture On Full */ #define DDRPHY_DCURR_SCOF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_SCOF_SHIFT)) & DDRPHY_DCURR_SCOF_MASK) #define DDRPHY_DCURR_RCEN_MASK (0x400000U) #define DDRPHY_DCURR_RCEN_SHIFT (22U) /*! RCEN - Read Capture Enable */ #define DDRPHY_DCURR_RCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_RCEN_SHIFT)) & DDRPHY_DCURR_RCEN_MASK) #define DDRPHY_DCURR_XCEN_MASK (0x800000U) #define DDRPHY_DCURR_XCEN_SHIFT (23U) /*! XCEN - Expected Compare Enable */ #define DDRPHY_DCURR_XCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_XCEN_SHIFT)) & DDRPHY_DCURR_XCEN_MASK) #define DDRPHY_DCURR_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DCURR_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DCURR_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_RESERVED_31_24_SHIFT)) & DDRPHY_DCURR_RESERVED_31_24_MASK) /*! @} */ /*! @name DCULR - DCU Loop Register */ /*! @{ */ #define DDRPHY_DCULR_LSADDR_MASK (0xFU) #define DDRPHY_DCULR_LSADDR_SHIFT (0U) /*! LSADDR - Loop Start Address */ #define DDRPHY_DCULR_LSADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LSADDR_SHIFT)) & DDRPHY_DCULR_LSADDR_MASK) #define DDRPHY_DCULR_LEADDR_MASK (0xF0U) #define DDRPHY_DCULR_LEADDR_SHIFT (4U) /*! LEADDR - Loop End Address */ #define DDRPHY_DCULR_LEADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LEADDR_SHIFT)) & DDRPHY_DCULR_LEADDR_MASK) #define DDRPHY_DCULR_LCNT_MASK (0xFF00U) #define DDRPHY_DCULR_LCNT_SHIFT (8U) /*! LCNT - Loop Count */ #define DDRPHY_DCULR_LCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LCNT_SHIFT)) & DDRPHY_DCULR_LCNT_MASK) #define DDRPHY_DCULR_LINF_MASK (0x10000U) #define DDRPHY_DCULR_LINF_SHIFT (16U) /*! LINF - Loop Infinite */ #define DDRPHY_DCULR_LINF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LINF_SHIFT)) & DDRPHY_DCULR_LINF_MASK) #define DDRPHY_DCULR_IDA_MASK (0x20000U) #define DDRPHY_DCULR_IDA_SHIFT (17U) /*! IDA - Increment DRAM Address */ #define DDRPHY_DCULR_IDA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_IDA_SHIFT)) & DDRPHY_DCULR_IDA_MASK) #define DDRPHY_DCULR_RESERVED_27_18_MASK (0xFFC0000U) #define DDRPHY_DCULR_RESERVED_27_18_SHIFT (18U) /*! RESERVED_27_18 - Reserved. Return zeroes on reads. */ #define DDRPHY_DCULR_RESERVED_27_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_RESERVED_27_18_SHIFT)) & DDRPHY_DCULR_RESERVED_27_18_MASK) #define DDRPHY_DCULR_XLEADDR_MASK (0xF0000000U) #define DDRPHY_DCULR_XLEADDR_SHIFT (28U) /*! XLEADDR - Expected Data Loop End Address */ #define DDRPHY_DCULR_XLEADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_XLEADDR_SHIFT)) & DDRPHY_DCULR_XLEADDR_MASK) /*! @} */ /*! @name DCUGCR - DCU General Configuration Register */ /*! @{ */ #define DDRPHY_DCUGCR_RCSW_MASK (0xFFFFU) #define DDRPHY_DCUGCR_RCSW_SHIFT (0U) /*! RCSW - Read Capture Start Word */ #define DDRPHY_DCUGCR_RCSW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUGCR_RCSW_SHIFT)) & DDRPHY_DCUGCR_RCSW_MASK) #define DDRPHY_DCUGCR_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DCUGCR_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DCUGCR_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUGCR_RESERVED_31_16_SHIFT)) & DDRPHY_DCUGCR_RESERVED_31_16_MASK) /*! @} */ /*! @name DCUTPR - DCU Timing Parameters Register */ /*! @{ */ #define DDRPHY_DCUTPR_tDCUT0_MASK (0xFFU) #define DDRPHY_DCUTPR_tDCUT0_SHIFT (0U) /*! tDCUT0 - DCU Generic Timing Parameter 0 */ #define DDRPHY_DCUTPR_tDCUT0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUTPR_tDCUT0_SHIFT)) & DDRPHY_DCUTPR_tDCUT0_MASK) #define DDRPHY_DCUTPR_tDCUT1_MASK (0xFF00U) #define DDRPHY_DCUTPR_tDCUT1_SHIFT (8U) /*! tDCUT1 - DCU Generic Timing Parameter 1 */ #define DDRPHY_DCUTPR_tDCUT1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUTPR_tDCUT1_SHIFT)) & DDRPHY_DCUTPR_tDCUT1_MASK) #define DDRPHY_DCUTPR_tDCUT2_MASK (0xFFFF0000U) #define DDRPHY_DCUTPR_tDCUT2_SHIFT (16U) /*! tDCUT2 - DCU Generic Timing Parameter 2 */ #define DDRPHY_DCUTPR_tDCUT2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUTPR_tDCUT2_SHIFT)) & DDRPHY_DCUTPR_tDCUT2_MASK) /*! @} */ /*! @name DCUSR0 - DCU Status Register 0 */ /*! @{ */ #define DDRPHY_DCUSR0_RDONE_MASK (0x1U) #define DDRPHY_DCUSR0_RDONE_SHIFT (0U) /*! RDONE - Run Done */ #define DDRPHY_DCUSR0_RDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_RDONE_SHIFT)) & DDRPHY_DCUSR0_RDONE_MASK) #define DDRPHY_DCUSR0_CFAIL_MASK (0x2U) #define DDRPHY_DCUSR0_CFAIL_SHIFT (1U) /*! CFAIL - Capture Fail */ #define DDRPHY_DCUSR0_CFAIL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_CFAIL_SHIFT)) & DDRPHY_DCUSR0_CFAIL_MASK) #define DDRPHY_DCUSR0_CFULL_MASK (0x4U) #define DDRPHY_DCUSR0_CFULL_SHIFT (2U) /*! CFULL - Capture Full */ #define DDRPHY_DCUSR0_CFULL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_CFULL_SHIFT)) & DDRPHY_DCUSR0_CFULL_MASK) #define DDRPHY_DCUSR0_RESERVED_31_3_MASK (0xFFFFFFF8U) #define DDRPHY_DCUSR0_RESERVED_31_3_SHIFT (3U) /*! RESERVED_31_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DCUSR0_RESERVED_31_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_RESERVED_31_3_SHIFT)) & DDRPHY_DCUSR0_RESERVED_31_3_MASK) /*! @} */ /*! @name DCUSR1 - DCU Status Register 1 */ /*! @{ */ #define DDRPHY_DCUSR1_RDCNT_MASK (0xFFFFU) #define DDRPHY_DCUSR1_RDCNT_SHIFT (0U) /*! RDCNT - Read Count */ #define DDRPHY_DCUSR1_RDCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR1_RDCNT_SHIFT)) & DDRPHY_DCUSR1_RDCNT_MASK) #define DDRPHY_DCUSR1_FLCNT_MASK (0xFF0000U) #define DDRPHY_DCUSR1_FLCNT_SHIFT (16U) /*! FLCNT - Fail Count */ #define DDRPHY_DCUSR1_FLCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR1_FLCNT_SHIFT)) & DDRPHY_DCUSR1_FLCNT_MASK) #define DDRPHY_DCUSR1_LPCNT_MASK (0xFF000000U) #define DDRPHY_DCUSR1_LPCNT_SHIFT (24U) /*! LPCNT - Loop Count */ #define DDRPHY_DCUSR1_LPCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR1_LPCNT_SHIFT)) & DDRPHY_DCUSR1_LPCNT_MASK) /*! @} */ /*! @name BISTRR - BIST Run Register */ /*! @{ */ #define DDRPHY_BISTRR_BINST_MASK (0x7U) #define DDRPHY_BISTRR_BINST_SHIFT (0U) /*! BINST - BIST Instruction */ #define DDRPHY_BISTRR_BINST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BINST_SHIFT)) & DDRPHY_BISTRR_BINST_MASK) #define DDRPHY_BISTRR_BMODE_MASK (0x8U) #define DDRPHY_BISTRR_BMODE_SHIFT (3U) /*! BMODE - BIST Mode */ #define DDRPHY_BISTRR_BMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BMODE_SHIFT)) & DDRPHY_BISTRR_BMODE_MASK) #define DDRPHY_BISTRR_BINF_MASK (0x10U) #define DDRPHY_BISTRR_BINF_SHIFT (4U) /*! BINF - BIST Infinite Run */ #define DDRPHY_BISTRR_BINF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BINF_SHIFT)) & DDRPHY_BISTRR_BINF_MASK) #define DDRPHY_BISTRR_NFAIL_MASK (0x1FE0U) #define DDRPHY_BISTRR_NFAIL_SHIFT (5U) /*! NFAIL - Number of Failures */ #define DDRPHY_BISTRR_NFAIL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_NFAIL_SHIFT)) & DDRPHY_BISTRR_NFAIL_MASK) #define DDRPHY_BISTRR_BSONF_MASK (0x2000U) #define DDRPHY_BISTRR_BSONF_SHIFT (13U) /*! BSONF - BIST Stop On Nth Fail */ #define DDRPHY_BISTRR_BSONF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BSONF_SHIFT)) & DDRPHY_BISTRR_BSONF_MASK) #define DDRPHY_BISTRR_BDXEN_MASK (0x4000U) #define DDRPHY_BISTRR_BDXEN_SHIFT (14U) /*! BDXEN - BIST DATX8 Enable */ #define DDRPHY_BISTRR_BDXEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDXEN_SHIFT)) & DDRPHY_BISTRR_BDXEN_MASK) #define DDRPHY_BISTRR_BACEN_MASK (0x8000U) #define DDRPHY_BISTRR_BACEN_SHIFT (15U) /*! BACEN - BIST AC Enable */ #define DDRPHY_BISTRR_BACEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BACEN_SHIFT)) & DDRPHY_BISTRR_BACEN_MASK) #define DDRPHY_BISTRR_BDMEN_MASK (0x10000U) #define DDRPHY_BISTRR_BDMEN_SHIFT (16U) /*! BDMEN - BIST Data Mask Enable */ #define DDRPHY_BISTRR_BDMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDMEN_SHIFT)) & DDRPHY_BISTRR_BDMEN_MASK) #define DDRPHY_BISTRR_BDXDPAT_MASK (0x60000U) #define DDRPHY_BISTRR_BDXDPAT_SHIFT (17U) /*! BDXDPAT - BIST Data Pattern */ #define DDRPHY_BISTRR_BDXDPAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDXDPAT_SHIFT)) & DDRPHY_BISTRR_BDXDPAT_MASK) #define DDRPHY_BISTRR_BDXSEL_MASK (0x780000U) #define DDRPHY_BISTRR_BDXSEL_SHIFT (19U) /*! BDXSEL - BIST DATX8 Select */ #define DDRPHY_BISTRR_BDXSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDXSEL_SHIFT)) & DDRPHY_BISTRR_BDXSEL_MASK) #define DDRPHY_BISTRR_BCKSEL_MASK (0x1800000U) #define DDRPHY_BISTRR_BCKSEL_SHIFT (23U) /*! BCKSEL - BIST CK Select */ #define DDRPHY_BISTRR_BCKSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BCKSEL_SHIFT)) & DDRPHY_BISTRR_BCKSEL_MASK) #define DDRPHY_BISTRR_BCCSEL_MASK (0x2000000U) #define DDRPHY_BISTRR_BCCSEL_SHIFT (25U) /*! BCCSEL - BIST Clock Cycle Select */ #define DDRPHY_BISTRR_BCCSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BCCSEL_SHIFT)) & DDRPHY_BISTRR_BCCSEL_MASK) #define DDRPHY_BISTRR_BACDPAT_MASK (0xC000000U) #define DDRPHY_BISTRR_BACDPAT_SHIFT (26U) /*! BACDPAT - BIST AC Data Pattern */ #define DDRPHY_BISTRR_BACDPAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BACDPAT_SHIFT)) & DDRPHY_BISTRR_BACDPAT_MASK) #define DDRPHY_BISTRR_BSOMA_MASK (0x10000000U) #define DDRPHY_BISTRR_BSOMA_SHIFT (28U) /*! BSOMA - BIST Stop on Maximum Address */ #define DDRPHY_BISTRR_BSOMA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BSOMA_SHIFT)) & DDRPHY_BISTRR_BSOMA_MASK) #define DDRPHY_BISTRR_BPRBST_MASK (0x20000000U) #define DDRPHY_BISTRR_BPRBST_SHIFT (29U) /*! BPRBST - BIST PRBS Type. */ #define DDRPHY_BISTRR_BPRBST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BPRBST_SHIFT)) & DDRPHY_BISTRR_BPRBST_MASK) #define DDRPHY_BISTRR_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_BISTRR_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTRR_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_RESERVED_31_30_SHIFT)) & DDRPHY_BISTRR_RESERVED_31_30_MASK) /*! @} */ /*! @name BISTWCR - BIST Word Count Register */ /*! @{ */ #define DDRPHY_BISTWCR_BDXWCNT_MASK (0xFFFFU) #define DDRPHY_BISTWCR_BDXWCNT_SHIFT (0U) /*! BDXWCNT - BIST DX Word Count */ #define DDRPHY_BISTWCR_BDXWCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCR_BDXWCNT_SHIFT)) & DDRPHY_BISTWCR_BDXWCNT_MASK) #define DDRPHY_BISTWCR_BACWCNT_MASK (0xFFFF0000U) #define DDRPHY_BISTWCR_BACWCNT_SHIFT (16U) /*! BACWCNT - BIST AC Word Count */ #define DDRPHY_BISTWCR_BACWCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCR_BACWCNT_SHIFT)) & DDRPHY_BISTWCR_BACWCNT_MASK) /*! @} */ /*! @name BISTMSKR0 - BIST Mask Register 0 */ /*! @{ */ #define DDRPHY_BISTMSKR0_AMSK_MASK (0x3FFFFU) #define DDRPHY_BISTMSKR0_AMSK_SHIFT (0U) /*! AMSK - Mask bit for each of the up to 16 address bits. */ #define DDRPHY_BISTMSKR0_AMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_AMSK_SHIFT)) & DDRPHY_BISTMSKR0_AMSK_MASK) #define DDRPHY_BISTMSKR0_RESERVED_18_MASK (0x40000U) #define DDRPHY_BISTMSKR0_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Return zeros on reads. */ #define DDRPHY_BISTMSKR0_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_RESERVED_18_SHIFT)) & DDRPHY_BISTMSKR0_RESERVED_18_MASK) #define DDRPHY_BISTMSKR0_ACTMSK_MASK (0x80000U) #define DDRPHY_BISTMSKR0_ACTMSK_SHIFT (19U) /*! ACTMSK - Mask bit for the RAS. */ #define DDRPHY_BISTMSKR0_ACTMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_ACTMSK_SHIFT)) & DDRPHY_BISTMSKR0_ACTMSK_MASK) #define DDRPHY_BISTMSKR0_CSMSK_MASK (0x100000U) #define DDRPHY_BISTMSKR0_CSMSK_SHIFT (20U) /*! CSMSK - Mask bit for each of the up to 12 CS_N bits. */ #define DDRPHY_BISTMSKR0_CSMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_CSMSK_SHIFT)) & DDRPHY_BISTMSKR0_CSMSK_MASK) #define DDRPHY_BISTMSKR0_CSMSK_RSVD_MASK (0xFFE00000U) #define DDRPHY_BISTMSKR0_CSMSK_RSVD_SHIFT (21U) /*! CSMSK_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTMSKR0_CSMSK_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_CSMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR0_CSMSK_RSVD_MASK) /*! @} */ /*! @name BISTMSKR1 - BIST Mask Register 1 */ /*! @{ */ #define DDRPHY_BISTMSKR1_RESERVED_3_0_MASK (0xFU) #define DDRPHY_BISTMSKR1_RESERVED_3_0_SHIFT (0U) /*! RESERVED_3_0 - Reserved. Return zeros on reads. */ #define DDRPHY_BISTMSKR1_RESERVED_3_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_RESERVED_3_0_SHIFT)) & DDRPHY_BISTMSKR1_RESERVED_3_0_MASK) #define DDRPHY_BISTMSKR1_BAMSK_MASK (0xF0U) #define DDRPHY_BISTMSKR1_BAMSK_SHIFT (4U) /*! BAMSK - Mask bit for each of the up to 4 bank address bits. */ #define DDRPHY_BISTMSKR1_BAMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_BAMSK_SHIFT)) & DDRPHY_BISTMSKR1_BAMSK_MASK) #define DDRPHY_BISTMSKR1_CKEMSK_MASK (0x100U) #define DDRPHY_BISTMSKR1_CKEMSK_SHIFT (8U) /*! CKEMSK - Mask bit for each of the up to 8 CKE bits. */ #define DDRPHY_BISTMSKR1_CKEMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CKEMSK_SHIFT)) & DDRPHY_BISTMSKR1_CKEMSK_MASK) #define DDRPHY_BISTMSKR1_CKEMSK_RSVD_MASK (0xFE00U) #define DDRPHY_BISTMSKR1_CKEMSK_RSVD_SHIFT (9U) /*! CKEMSK_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTMSKR1_CKEMSK_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CKEMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR1_CKEMSK_RSVD_MASK) #define DDRPHY_BISTMSKR1_ODTMSK_MASK (0x10000U) #define DDRPHY_BISTMSKR1_ODTMSK_SHIFT (16U) /*! ODTMSK - Mask bit for each of the up to 8 ODT bits. */ #define DDRPHY_BISTMSKR1_ODTMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_ODTMSK_SHIFT)) & DDRPHY_BISTMSKR1_ODTMSK_MASK) #define DDRPHY_BISTMSKR1_ODTMSK_RSVD_MASK (0xFE0000U) #define DDRPHY_BISTMSKR1_ODTMSK_RSVD_SHIFT (17U) /*! ODTMSK_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTMSKR1_ODTMSK_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_ODTMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR1_ODTMSK_RSVD_MASK) #define DDRPHY_BISTMSKR1_CIDMSK_MASK (0x1000000U) #define DDRPHY_BISTMSKR1_CIDMSK_SHIFT (24U) /*! CIDMSK - Mask bits for each of the up to 3 Chip IP bits. */ #define DDRPHY_BISTMSKR1_CIDMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CIDMSK_SHIFT)) & DDRPHY_BISTMSKR1_CIDMSK_MASK) #define DDRPHY_BISTMSKR1_CIDMSK_RSVD_MASK (0x6000000U) #define DDRPHY_BISTMSKR1_CIDMSK_RSVD_SHIFT (25U) /*! CIDMSK_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTMSKR1_CIDMSK_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CIDMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR1_CIDMSK_RSVD_MASK) #define DDRPHY_BISTMSKR1_PARINMSK_MASK (0x8000000U) #define DDRPHY_BISTMSKR1_PARINMSK_SHIFT (27U) /*! PARINMSK - Mask bit for the PAR_IN. */ #define DDRPHY_BISTMSKR1_PARINMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_PARINMSK_SHIFT)) & DDRPHY_BISTMSKR1_PARINMSK_MASK) #define DDRPHY_BISTMSKR1_DMMSK_MASK (0xF0000000U) #define DDRPHY_BISTMSKR1_DMMSK_SHIFT (28U) /*! DMMSK - Mask bit for the data mask (DM) bit. */ #define DDRPHY_BISTMSKR1_DMMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_DMMSK_SHIFT)) & DDRPHY_BISTMSKR1_DMMSK_MASK) /*! @} */ /*! @name BISTMSKR2 - BIST Mask Register 2 */ /*! @{ */ #define DDRPHY_BISTMSKR2_DQMSK_MASK (0xFFFFFFFFU) #define DDRPHY_BISTMSKR2_DQMSK_SHIFT (0U) /*! DQMSK - Mask bit for each of the 8 data (DQ) bits */ #define DDRPHY_BISTMSKR2_DQMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR2_DQMSK_SHIFT)) & DDRPHY_BISTMSKR2_DQMSK_MASK) /*! @} */ /*! @name BISTLSR - BIST LFSR Seed Register */ /*! @{ */ #define DDRPHY_BISTLSR_SEED_MASK (0xFFFFFFFFU) #define DDRPHY_BISTLSR_SEED_SHIFT (0U) /*! SEED - LFSR seed for pseudo-random BIST patterns */ #define DDRPHY_BISTLSR_SEED(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTLSR_SEED_SHIFT)) & DDRPHY_BISTLSR_SEED_MASK) /*! @} */ /*! @name BISTAR0 - BIST Address Register 0 */ /*! @{ */ #define DDRPHY_BISTAR0_BCOL_MASK (0xFFFU) #define DDRPHY_BISTAR0_BCOL_SHIFT (0U) /*! BCOL - BIST Column Address */ #define DDRPHY_BISTAR0_BCOL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR0_BCOL_SHIFT)) & DDRPHY_BISTAR0_BCOL_MASK) #define DDRPHY_BISTAR0_RESERVED_27_12_MASK (0xFFFF000U) #define DDRPHY_BISTAR0_RESERVED_27_12_SHIFT (12U) /*! RESERVED_27_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTAR0_RESERVED_27_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR0_RESERVED_27_12_SHIFT)) & DDRPHY_BISTAR0_RESERVED_27_12_MASK) #define DDRPHY_BISTAR0_BBANK_MASK (0xF0000000U) #define DDRPHY_BISTAR0_BBANK_SHIFT (28U) /*! BBANK - BIST Bank Address */ #define DDRPHY_BISTAR0_BBANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR0_BBANK_SHIFT)) & DDRPHY_BISTAR0_BBANK_MASK) /*! @} */ /*! @name BISTAR1 - BIST Address Register 1 */ /*! @{ */ #define DDRPHY_BISTAR1_BRANK_MASK (0xFU) #define DDRPHY_BISTAR1_BRANK_SHIFT (0U) /*! BRANK - BIST Rank */ #define DDRPHY_BISTAR1_BRANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_BRANK_SHIFT)) & DDRPHY_BISTAR1_BRANK_MASK) #define DDRPHY_BISTAR1_BAINC_MASK (0xFFF0U) #define DDRPHY_BISTAR1_BAINC_SHIFT (4U) /*! BAINC - BIST Address Increment */ #define DDRPHY_BISTAR1_BAINC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_BAINC_SHIFT)) & DDRPHY_BISTAR1_BAINC_MASK) #define DDRPHY_BISTAR1_BMRANK_MASK (0xF0000U) #define DDRPHY_BISTAR1_BMRANK_SHIFT (16U) /*! BMRANK - BIST Maximum Rank */ #define DDRPHY_BISTAR1_BMRANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_BMRANK_SHIFT)) & DDRPHY_BISTAR1_BMRANK_MASK) #define DDRPHY_BISTAR1_RESERVED_31_20_MASK (0xFFF00000U) #define DDRPHY_BISTAR1_RESERVED_31_20_SHIFT (20U) /*! RESERVED_31_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTAR1_RESERVED_31_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_RESERVED_31_20_SHIFT)) & DDRPHY_BISTAR1_RESERVED_31_20_MASK) /*! @} */ /*! @name BISTAR2 - BIST Address Register 2 */ /*! @{ */ #define DDRPHY_BISTAR2_BMCOL_MASK (0xFFFU) #define DDRPHY_BISTAR2_BMCOL_SHIFT (0U) /*! BMCOL - BIST Maximum Column Address */ #define DDRPHY_BISTAR2_BMCOL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR2_BMCOL_SHIFT)) & DDRPHY_BISTAR2_BMCOL_MASK) #define DDRPHY_BISTAR2_RESERVED_27_12_MASK (0xFFFF000U) #define DDRPHY_BISTAR2_RESERVED_27_12_SHIFT (12U) /*! RESERVED_27_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTAR2_RESERVED_27_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR2_RESERVED_27_12_SHIFT)) & DDRPHY_BISTAR2_RESERVED_27_12_MASK) #define DDRPHY_BISTAR2_BMBANK_MASK (0xF0000000U) #define DDRPHY_BISTAR2_BMBANK_SHIFT (28U) /*! BMBANK - BIST Maximum Bank Address */ #define DDRPHY_BISTAR2_BMBANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR2_BMBANK_SHIFT)) & DDRPHY_BISTAR2_BMBANK_MASK) /*! @} */ /*! @name BISTAR3 - BIST Address Register 3 */ /*! @{ */ #define DDRPHY_BISTAR3_BROW_MASK (0x3FFFFU) #define DDRPHY_BISTAR3_BROW_SHIFT (0U) /*! BROW - BIST Row Address */ #define DDRPHY_BISTAR3_BROW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR3_BROW_SHIFT)) & DDRPHY_BISTAR3_BROW_MASK) #define DDRPHY_BISTAR3_RESERVED_31_18_MASK (0xFFFC0000U) #define DDRPHY_BISTAR3_RESERVED_31_18_SHIFT (18U) /*! RESERVED_31_18 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTAR3_RESERVED_31_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR3_RESERVED_31_18_SHIFT)) & DDRPHY_BISTAR3_RESERVED_31_18_MASK) /*! @} */ /*! @name BISTAR4 - BIST Address Register 4 */ /*! @{ */ #define DDRPHY_BISTAR4_BMROW_MASK (0x3FFFFU) #define DDRPHY_BISTAR4_BMROW_SHIFT (0U) /*! BMROW - BIST Maximum Row Address */ #define DDRPHY_BISTAR4_BMROW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR4_BMROW_SHIFT)) & DDRPHY_BISTAR4_BMROW_MASK) #define DDRPHY_BISTAR4_RESERVED_31_18_MASK (0xFFFC0000U) #define DDRPHY_BISTAR4_RESERVED_31_18_SHIFT (18U) /*! RESERVED_31_18 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTAR4_RESERVED_31_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR4_RESERVED_31_18_SHIFT)) & DDRPHY_BISTAR4_RESERVED_31_18_MASK) /*! @} */ /*! @name BISTUDPR - BIST User Data Pattern Register */ /*! @{ */ #define DDRPHY_BISTUDPR_BUDP0_MASK (0xFFFFU) #define DDRPHY_BISTUDPR_BUDP0_SHIFT (0U) /*! BUDP0 - BIST User Data Pattern 0 */ #define DDRPHY_BISTUDPR_BUDP0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTUDPR_BUDP0_SHIFT)) & DDRPHY_BISTUDPR_BUDP0_MASK) #define DDRPHY_BISTUDPR_BUDP1_MASK (0xFFFF0000U) #define DDRPHY_BISTUDPR_BUDP1_SHIFT (16U) /*! BUDP1 - BIST User Data Pattern 1 */ #define DDRPHY_BISTUDPR_BUDP1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTUDPR_BUDP1_SHIFT)) & DDRPHY_BISTUDPR_BUDP1_MASK) /*! @} */ /*! @name BISTGSR - BIST General Status Register */ /*! @{ */ #define DDRPHY_BISTGSR_BDONE_MASK (0x1U) #define DDRPHY_BISTGSR_BDONE_SHIFT (0U) /*! BDONE - BIST Done */ #define DDRPHY_BISTGSR_BDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_BDONE_SHIFT)) & DDRPHY_BISTGSR_BDONE_MASK) #define DDRPHY_BISTGSR_BACERR_MASK (0x2U) #define DDRPHY_BISTGSR_BACERR_SHIFT (1U) /*! BACERR - BIST Address/Command Error */ #define DDRPHY_BISTGSR_BACERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_BACERR_SHIFT)) & DDRPHY_BISTGSR_BACERR_MASK) #define DDRPHY_BISTGSR_BDXERR_MASK (0x7FCU) #define DDRPHY_BISTGSR_BDXERR_SHIFT (2U) /*! BDXERR - BIST Data Error */ #define DDRPHY_BISTGSR_BDXERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_BDXERR_SHIFT)) & DDRPHY_BISTGSR_BDXERR_MASK) #define DDRPHY_BISTGSR_RESERVED_11_MASK (0x800U) #define DDRPHY_BISTGSR_RESERVED_11_SHIFT (11U) /*! RESERVED_11 - Reserved. Return zeros on reads. */ #define DDRPHY_BISTGSR_RESERVED_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RESERVED_11_SHIFT)) & DDRPHY_BISTGSR_RESERVED_11_MASK) #define DDRPHY_BISTGSR_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_BISTGSR_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTGSR_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RESERVED_19_12_SHIFT)) & DDRPHY_BISTGSR_RESERVED_19_12_MASK) #define DDRPHY_BISTGSR_DMBER_MASK (0xFF00000U) #define DDRPHY_BISTGSR_DMBER_SHIFT (20U) /*! DMBER - DM Bit Error */ #define DDRPHY_BISTGSR_DMBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_DMBER_SHIFT)) & DDRPHY_BISTGSR_DMBER_MASK) #define DDRPHY_BISTGSR_RASBER_MASK (0x30000000U) #define DDRPHY_BISTGSR_RASBER_SHIFT (28U) /*! RASBER - RAS_n/ACT_n Bit Error */ #define DDRPHY_BISTGSR_RASBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RASBER_SHIFT)) & DDRPHY_BISTGSR_RASBER_MASK) #define DDRPHY_BISTGSR_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_BISTGSR_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTGSR_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RESERVED_31_30_SHIFT)) & DDRPHY_BISTGSR_RESERVED_31_30_MASK) /*! @} */ /*! @name BISTWER0 - BIST Word Error Register 0 */ /*! @{ */ #define DDRPHY_BISTWER0_ACWER_MASK (0x3FFFFU) #define DDRPHY_BISTWER0_ACWER_SHIFT (0U) /*! ACWER - Address/Command Word Error */ #define DDRPHY_BISTWER0_ACWER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER0_ACWER_SHIFT)) & DDRPHY_BISTWER0_ACWER_MASK) #define DDRPHY_BISTWER0_RESERVED_31_18_MASK (0xFFFC0000U) #define DDRPHY_BISTWER0_RESERVED_31_18_SHIFT (18U) /*! RESERVED_31_18 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTWER0_RESERVED_31_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER0_RESERVED_31_18_SHIFT)) & DDRPHY_BISTWER0_RESERVED_31_18_MASK) /*! @} */ /*! @name BISTWER1 - BIST Word Error Register 1 */ /*! @{ */ #define DDRPHY_BISTWER1_DXWER_MASK (0xFFFFU) #define DDRPHY_BISTWER1_DXWER_SHIFT (0U) /*! DXWER - Byte Word Error */ #define DDRPHY_BISTWER1_DXWER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER1_DXWER_SHIFT)) & DDRPHY_BISTWER1_DXWER_MASK) #define DDRPHY_BISTWER1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_BISTWER1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTWER1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER1_RESERVED_31_16_SHIFT)) & DDRPHY_BISTWER1_RESERVED_31_16_MASK) /*! @} */ /*! @name BISTBER0 - BIST Bit Error Register 0 */ /*! @{ */ #define DDRPHY_BISTBER0_ABER_MASK (0xFFFFFFFFU) #define DDRPHY_BISTBER0_ABER_SHIFT (0U) /*! ABER - Address Bit Error */ #define DDRPHY_BISTBER0_ABER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER0_ABER_SHIFT)) & DDRPHY_BISTBER0_ABER_MASK) /*! @} */ /*! @name BISTBER1 - BIST Bit Error Register 1 */ /*! @{ */ #define DDRPHY_BISTBER1_BABER_MASK (0xFFU) #define DDRPHY_BISTBER1_BABER_SHIFT (0U) /*! BABER - Bank Address Bit Error */ #define DDRPHY_BISTBER1_BABER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER1_BABER_SHIFT)) & DDRPHY_BISTBER1_BABER_MASK) #define DDRPHY_BISTBER1_CSBER_MASK (0x300U) #define DDRPHY_BISTBER1_CSBER_SHIFT (8U) /*! CSBER - CS_N Bit Error. */ #define DDRPHY_BISTBER1_CSBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER1_CSBER_SHIFT)) & DDRPHY_BISTBER1_CSBER_MASK) #define DDRPHY_BISTBER1_CSBER_RSVD_MASK (0xFFFFFC00U) #define DDRPHY_BISTBER1_CSBER_RSVD_SHIFT (10U) /*! CSBER_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTBER1_CSBER_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER1_CSBER_RSVD_SHIFT)) & DDRPHY_BISTBER1_CSBER_RSVD_MASK) /*! @} */ /*! @name BISTBER2 - BIST Bit Error Register 2 */ /*! @{ */ #define DDRPHY_BISTBER2_DQBER0_MASK (0xFFFFFFFFU) #define DDRPHY_BISTBER2_DQBER0_SHIFT (0U) /*! DQBER0 - Data Bit Error */ #define DDRPHY_BISTBER2_DQBER0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER2_DQBER0_SHIFT)) & DDRPHY_BISTBER2_DQBER0_MASK) /*! @} */ /*! @name BISTBER3 - BIST Bit Error Register 3 */ /*! @{ */ #define DDRPHY_BISTBER3_DQBER1_MASK (0xFFFFFFFFU) #define DDRPHY_BISTBER3_DQBER1_SHIFT (0U) /*! DQBER1 - Data Bit Error */ #define DDRPHY_BISTBER3_DQBER1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER3_DQBER1_SHIFT)) & DDRPHY_BISTBER3_DQBER1_MASK) /*! @} */ /*! @name BISTBER4 - BIST Bit Error Register 4 */ /*! @{ */ #define DDRPHY_BISTBER4_ABER_MASK (0xFU) #define DDRPHY_BISTBER4_ABER_SHIFT (0U) /*! ABER - Address Bit Error */ #define DDRPHY_BISTBER4_ABER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_ABER_SHIFT)) & DDRPHY_BISTBER4_ABER_MASK) #define DDRPHY_BISTBER4_RESERVED_7_4_MASK (0xF0U) #define DDRPHY_BISTBER4_RESERVED_7_4_SHIFT (4U) /*! RESERVED_7_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTBER4_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_RESERVED_7_4_SHIFT)) & DDRPHY_BISTBER4_RESERVED_7_4_MASK) #define DDRPHY_BISTBER4_CIDBER_MASK (0x300U) #define DDRPHY_BISTBER4_CIDBER_SHIFT (8U) /*! CIDBER - Chip ID Bit Error. */ #define DDRPHY_BISTBER4_CIDBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_CIDBER_SHIFT)) & DDRPHY_BISTBER4_CIDBER_MASK) #define DDRPHY_BISTBER4_CIDBER_RSVD_MASK (0x3C00U) #define DDRPHY_BISTBER4_CIDBER_RSVD_SHIFT (10U) /*! CIDBER_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTBER4_CIDBER_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_CIDBER_RSVD_SHIFT)) & DDRPHY_BISTBER4_CIDBER_RSVD_MASK) #define DDRPHY_BISTBER4_RESERVED_31_14_MASK (0xFFFFC000U) #define DDRPHY_BISTBER4_RESERVED_31_14_SHIFT (14U) /*! RESERVED_31_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTBER4_RESERVED_31_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_RESERVED_31_14_SHIFT)) & DDRPHY_BISTBER4_RESERVED_31_14_MASK) /*! @} */ /*! @name BISTWCSR - BIST Word Count Status Register */ /*! @{ */ #define DDRPHY_BISTWCSR_ACWCNT_MASK (0xFFFFU) #define DDRPHY_BISTWCSR_ACWCNT_SHIFT (0U) /*! ACWCNT - Address/Command Word Count */ #define DDRPHY_BISTWCSR_ACWCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCSR_ACWCNT_SHIFT)) & DDRPHY_BISTWCSR_ACWCNT_MASK) #define DDRPHY_BISTWCSR_DXWCNT_MASK (0xFFFF0000U) #define DDRPHY_BISTWCSR_DXWCNT_SHIFT (16U) /*! DXWCNT - Byte Word Count */ #define DDRPHY_BISTWCSR_DXWCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCSR_DXWCNT_SHIFT)) & DDRPHY_BISTWCSR_DXWCNT_MASK) /*! @} */ /*! @name BISTFWR0 - BIST Fail Word Register 0 */ /*! @{ */ #define DDRPHY_BISTFWR0_AWEBS_MASK (0x3FFFFU) #define DDRPHY_BISTFWR0_AWEBS_SHIFT (0U) /*! AWEBS - Bit status during a word error for each of the up to 16 address bits */ #define DDRPHY_BISTFWR0_AWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_AWEBS_SHIFT)) & DDRPHY_BISTFWR0_AWEBS_MASK) #define DDRPHY_BISTFWR0_ACTWEBS_MASK (0x40000U) #define DDRPHY_BISTFWR0_ACTWEBS_SHIFT (18U) /*! ACTWEBS - Bit status during a word error for the RAS. */ #define DDRPHY_BISTFWR0_ACTWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_ACTWEBS_SHIFT)) & DDRPHY_BISTFWR0_ACTWEBS_MASK) #define DDRPHY_BISTFWR0_RESERVED_19_MASK (0x80000U) #define DDRPHY_BISTFWR0_RESERVED_19_SHIFT (19U) /*! RESERVED_19 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTFWR0_RESERVED_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_RESERVED_19_SHIFT)) & DDRPHY_BISTFWR0_RESERVED_19_MASK) #define DDRPHY_BISTFWR0_CSWEBS_MASK (0x100000U) #define DDRPHY_BISTFWR0_CSWEBS_SHIFT (20U) /*! CSWEBS - Bit status during a word error for each of the up to 12 CS# bits. */ #define DDRPHY_BISTFWR0_CSWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_CSWEBS_SHIFT)) & DDRPHY_BISTFWR0_CSWEBS_MASK) #define DDRPHY_BISTFWR0_CSWEBS_RSVD_MASK (0xFFE00000U) #define DDRPHY_BISTFWR0_CSWEBS_RSVD_SHIFT (21U) /*! CSWEBS_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTFWR0_CSWEBS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_CSWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR0_CSWEBS_RSVD_MASK) /*! @} */ /*! @name BISTFWR1 - BIST Fail Word Register 1 */ /*! @{ */ #define DDRPHY_BISTFWR1_CKEWEBS_MASK (0x1U) #define DDRPHY_BISTFWR1_CKEWEBS_SHIFT (0U) /*! CKEWEBS - Bit status during a word error for each of the up to 8 CKE bits. */ #define DDRPHY_BISTFWR1_CKEWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CKEWEBS_SHIFT)) & DDRPHY_BISTFWR1_CKEWEBS_MASK) #define DDRPHY_BISTFWR1_CKEWEBS_RSVD_MASK (0xFEU) #define DDRPHY_BISTFWR1_CKEWEBS_RSVD_SHIFT (1U) /*! CKEWEBS_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTFWR1_CKEWEBS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CKEWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR1_CKEWEBS_RSVD_MASK) #define DDRPHY_BISTFWR1_ODTWEBS_MASK (0x100U) #define DDRPHY_BISTFWR1_ODTWEBS_SHIFT (8U) /*! ODTWEBS - Bit status during a word error for each of the up to 8 ODT bits. */ #define DDRPHY_BISTFWR1_ODTWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_ODTWEBS_SHIFT)) & DDRPHY_BISTFWR1_ODTWEBS_MASK) #define DDRPHY_BISTFWR1_ODTWEBS_RSVD_MASK (0xFE00U) #define DDRPHY_BISTFWR1_ODTWEBS_RSVD_SHIFT (9U) /*! ODTWEBS_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTFWR1_ODTWEBS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_ODTWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR1_ODTWEBS_RSVD_MASK) #define DDRPHY_BISTFWR1_BAWEBS_MASK (0xF0000U) #define DDRPHY_BISTFWR1_BAWEBS_SHIFT (16U) /*! BAWEBS - Bit status during a word error for each of the bank address bits */ #define DDRPHY_BISTFWR1_BAWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_BAWEBS_SHIFT)) & DDRPHY_BISTFWR1_BAWEBS_MASK) #define DDRPHY_BISTFWR1_CIDWEBS_MASK (0x100000U) #define DDRPHY_BISTFWR1_CIDWEBS_SHIFT (20U) /*! CIDWEBS - Bit status during a word error for each of the up to 3 chip ID bits. */ #define DDRPHY_BISTFWR1_CIDWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CIDWEBS_SHIFT)) & DDRPHY_BISTFWR1_CIDWEBS_MASK) #define DDRPHY_BISTFWR1_CIDWEBS_RSVD_MASK (0x600000U) #define DDRPHY_BISTFWR1_CIDWEBS_RSVD_SHIFT (21U) /*! CIDWEBS_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTFWR1_CIDWEBS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CIDWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR1_CIDWEBS_RSVD_MASK) #define DDRPHY_BISTFWR1_RESERVED_23_22_MASK (0x800000U) #define DDRPHY_BISTFWR1_RESERVED_23_22_SHIFT (23U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTFWR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_RESERVED_23_22_SHIFT)) & DDRPHY_BISTFWR1_RESERVED_23_22_MASK) #define DDRPHY_BISTFWR1_RESERVED_27_24_MASK (0xF000000U) #define DDRPHY_BISTFWR1_RESERVED_27_24_SHIFT (24U) /*! RESERVED_27_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_BISTFWR1_RESERVED_27_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_RESERVED_27_24_SHIFT)) & DDRPHY_BISTFWR1_RESERVED_27_24_MASK) #define DDRPHY_BISTFWR1_DMWEBS_MASK (0xF0000000U) #define DDRPHY_BISTFWR1_DMWEBS_SHIFT (28U) /*! DMWEBS - Bit status during a word error for the data mask (DM) bit */ #define DDRPHY_BISTFWR1_DMWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_DMWEBS_SHIFT)) & DDRPHY_BISTFWR1_DMWEBS_MASK) /*! @} */ /*! @name BISTFWR2 - BIST Fail Word Register 2 */ /*! @{ */ #define DDRPHY_BISTFWR2_DQWEBS_MASK (0xFFFFFFFFU) #define DDRPHY_BISTFWR2_DQWEBS_SHIFT (0U) /*! DQWEBS - Bit status during a word error for each of the 8 data (DQ) bits */ #define DDRPHY_BISTFWR2_DQWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR2_DQWEBS_SHIFT)) & DDRPHY_BISTFWR2_DQWEBS_MASK) /*! @} */ /*! @name BISTBER5 - BIST Bit Error Register 5 */ /*! @{ */ #define DDRPHY_BISTBER5_CKEBER_MASK (0x3U) #define DDRPHY_BISTBER5_CKEBER_SHIFT (0U) /*! CKEBER - CKE Bit Error. */ #define DDRPHY_BISTBER5_CKEBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_CKEBER_SHIFT)) & DDRPHY_BISTBER5_CKEBER_MASK) #define DDRPHY_BISTBER5_CKEBER_RSVD_MASK (0xFFFCU) #define DDRPHY_BISTBER5_CKEBER_RSVD_SHIFT (2U) /*! CKEBER_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTBER5_CKEBER_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_CKEBER_RSVD_SHIFT)) & DDRPHY_BISTBER5_CKEBER_RSVD_MASK) #define DDRPHY_BISTBER5_ODTBER_MASK (0x30000U) #define DDRPHY_BISTBER5_ODTBER_SHIFT (16U) /*! ODTBER - ODT Bit Error. */ #define DDRPHY_BISTBER5_ODTBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_ODTBER_SHIFT)) & DDRPHY_BISTBER5_ODTBER_MASK) #define DDRPHY_BISTBER5_ODTBER_RSVD_MASK (0xFFFC0000U) #define DDRPHY_BISTBER5_ODTBER_RSVD_SHIFT (18U) /*! ODTBER_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_BISTBER5_ODTBER_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_ODTBER_RSVD_SHIFT)) & DDRPHY_BISTBER5_ODTBER_RSVD_MASK) /*! @} */ /*! @name RANKIDR - Rank ID Register */ /*! @{ */ #define DDRPHY_RANKIDR_RANKWID_MASK (0xFU) #define DDRPHY_RANKIDR_RANKWID_SHIFT (0U) /*! RANKWID - Rank Write ID */ #define DDRPHY_RANKIDR_RANKWID(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RANKWID_SHIFT)) & DDRPHY_RANKIDR_RANKWID_MASK) #define DDRPHY_RANKIDR_RESERVED_15_4_MASK (0xFFF0U) #define DDRPHY_RANKIDR_RESERVED_15_4_SHIFT (4U) /*! RESERVED_15_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_RANKIDR_RESERVED_15_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RESERVED_15_4_SHIFT)) & DDRPHY_RANKIDR_RESERVED_15_4_MASK) #define DDRPHY_RANKIDR_RANKRID_MASK (0xF0000U) #define DDRPHY_RANKIDR_RANKRID_SHIFT (16U) /*! RANKRID - Rank Read ID */ #define DDRPHY_RANKIDR_RANKRID(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RANKRID_SHIFT)) & DDRPHY_RANKIDR_RANKRID_MASK) #define DDRPHY_RANKIDR_RESERVED_31_20_MASK (0xFFF00000U) #define DDRPHY_RANKIDR_RESERVED_31_20_SHIFT (20U) /*! RESERVED_31_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_RANKIDR_RESERVED_31_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RESERVED_31_20_SHIFT)) & DDRPHY_RANKIDR_RESERVED_31_20_MASK) /*! @} */ /*! @name RIOCR0 - Rank I/O Configuration Register 0 */ /*! @{ */ #define DDRPHY_RIOCR0_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_RIOCR0_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_RIOCR0_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR0_RESERVED_31_0_SHIFT)) & DDRPHY_RIOCR0_RESERVED_31_0_MASK) /*! @} */ /*! @name RIOCR1 - Rank I/O Configuration Register 1 */ /*! @{ */ #define DDRPHY_RIOCR1_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_RIOCR1_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_RIOCR1_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR1_RESERVED_31_0_SHIFT)) & DDRPHY_RIOCR1_RESERVED_31_0_MASK) /*! @} */ /*! @name RIOCR2 - Rank I/O Configuration Register 2 */ /*! @{ */ #define DDRPHY_RIOCR2_CSOEMODE_MASK (0x3U) #define DDRPHY_RIOCR2_CSOEMODE_SHIFT (0U) /*! CSOEMODE - SDRAM CS_n Output Enable (OE) Mode Selection. */ #define DDRPHY_RIOCR2_CSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_CSOEMODE_SHIFT)) & DDRPHY_RIOCR2_CSOEMODE_MASK) #define DDRPHY_RIOCR2_CSOEMODE_RSVD_MASK (0xFFFFFCU) #define DDRPHY_RIOCR2_CSOEMODE_RSVD_SHIFT (2U) /*! CSOEMODE_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_RIOCR2_CSOEMODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_CSOEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR2_CSOEMODE_RSVD_MASK) #define DDRPHY_RIOCR2_COEMODE_MASK (0x3000000U) #define DDRPHY_RIOCR2_COEMODE_SHIFT (24U) /*! COEMODE - SDRAM C Output Enable (OE) Mode Selection. */ #define DDRPHY_RIOCR2_COEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_COEMODE_SHIFT)) & DDRPHY_RIOCR2_COEMODE_MASK) #define DDRPHY_RIOCR2_COEMODE_RSVD_MASK (0x3C000000U) #define DDRPHY_RIOCR2_COEMODE_RSVD_SHIFT (26U) /*! COEMODE_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_RIOCR2_COEMODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_COEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR2_COEMODE_RSVD_MASK) #define DDRPHY_RIOCR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_RIOCR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_RIOCR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_RESERVED_31_30_SHIFT)) & DDRPHY_RIOCR2_RESERVED_31_30_MASK) /*! @} */ /*! @name RIOCR3 - Rank I/O Configuration Register 3 */ /*! @{ */ #define DDRPHY_RIOCR3_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_RIOCR3_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_RIOCR3_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR3_RESERVED_31_0_SHIFT)) & DDRPHY_RIOCR3_RESERVED_31_0_MASK) /*! @} */ /*! @name RIOCR4 - Rank I/O Configuration Register 4 */ /*! @{ */ #define DDRPHY_RIOCR4_CKEOEMODE_MASK (0x3U) #define DDRPHY_RIOCR4_CKEOEMODE_SHIFT (0U) /*! CKEOEMODE - SDRAM CKE Output Enable (OE) Mode Selection. */ #define DDRPHY_RIOCR4_CKEOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR4_CKEOEMODE_SHIFT)) & DDRPHY_RIOCR4_CKEOEMODE_MASK) #define DDRPHY_RIOCR4_CKEOEMODE_RSVD_MASK (0xFFFCU) #define DDRPHY_RIOCR4_CKEOEMODE_RSVD_SHIFT (2U) /*! CKEOEMODE_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_RIOCR4_CKEOEMODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR4_CKEOEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR4_CKEOEMODE_RSVD_MASK) #define DDRPHY_RIOCR4_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_RIOCR4_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_RIOCR4_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR4_RESERVED_31_16_SHIFT)) & DDRPHY_RIOCR4_RESERVED_31_16_MASK) /*! @} */ /*! @name RIOCR5 - Rank I/O Configuration Register 5 */ /*! @{ */ #define DDRPHY_RIOCR5_ODTOEMODE_MASK (0x3U) #define DDRPHY_RIOCR5_ODTOEMODE_SHIFT (0U) /*! ODTOEMODE - SDRAM On-die Termination Output Enable (OE) Mode Selection. */ #define DDRPHY_RIOCR5_ODTOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR5_ODTOEMODE_SHIFT)) & DDRPHY_RIOCR5_ODTOEMODE_MASK) #define DDRPHY_RIOCR5_ODTOEMODE_RSVD_MASK (0xFFFCU) #define DDRPHY_RIOCR5_ODTOEMODE_RSVD_SHIFT (2U) /*! ODTOEMODE_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_RIOCR5_ODTOEMODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR5_ODTOEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR5_ODTOEMODE_RSVD_MASK) #define DDRPHY_RIOCR5_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_RIOCR5_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_RIOCR5_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR5_RESERVED_31_16_SHIFT)) & DDRPHY_RIOCR5_RESERVED_31_16_MASK) /*! @} */ /*! @name ACIOCR0 - AC I/O Configuration Register 0 */ /*! @{ */ #define DDRPHY_ACIOCR0_ACRANKCLKSEL_MASK (0x1U) #define DDRPHY_ACIOCR0_ACRANKCLKSEL_SHIFT (0U) /*! ACRANKCLKSEL - Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. */ #define DDRPHY_ACIOCR0_ACRANKCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACRANKCLKSEL_SHIFT)) & DDRPHY_ACIOCR0_ACRANKCLKSEL_MASK) #define DDRPHY_ACIOCR0_RESERVED_1_MASK (0x2U) #define DDRPHY_ACIOCR0_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACIOCR0_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_1_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_1_MASK) #define DDRPHY_ACIOCR0_ACODTMODE_MASK (0xCU) #define DDRPHY_ACIOCR0_ACODTMODE_SHIFT (2U) /*! ACODTMODE - AC On-die Termination Mode */ #define DDRPHY_ACIOCR0_ACODTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACODTMODE_SHIFT)) & DDRPHY_ACIOCR0_ACODTMODE_MASK) #define DDRPHY_ACIOCR0_ACPDRMODE_MASK (0x30U) #define DDRPHY_ACIOCR0_ACPDRMODE_SHIFT (4U) /*! ACPDRMODE - AC Power Down Receiver Mode */ #define DDRPHY_ACIOCR0_ACPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACPDRMODE_SHIFT)) & DDRPHY_ACIOCR0_ACPDRMODE_MASK) #define DDRPHY_ACIOCR0_CKDCC_MASK (0x3C0U) #define DDRPHY_ACIOCR0_CKDCC_SHIFT (6U) /*! CKDCC - CK Duty Cycle Correction */ #define DDRPHY_ACIOCR0_CKDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_CKDCC_SHIFT)) & DDRPHY_ACIOCR0_CKDCC_MASK) #define DDRPHY_ACIOCR0_ACPNUMSEL_MASK (0xC00U) #define DDRPHY_ACIOCR0_ACPNUMSEL_SHIFT (10U) /*! ACPNUMSEL - Address/Command custom pin mapping configuration */ #define DDRPHY_ACIOCR0_ACPNUMSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACPNUMSEL_SHIFT)) & DDRPHY_ACIOCR0_ACPNUMSEL_MASK) #define DDRPHY_ACIOCR0_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_ACIOCR0_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACIOCR0_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_15_12_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_15_12_MASK) #define DDRPHY_ACIOCR0_ESR_MASK (0xFF0000U) #define DDRPHY_ACIOCR0_ESR_SHIFT (16U) /*! ESR - Decoupling Capacitance ESR Control in D5M I/O ring */ #define DDRPHY_ACIOCR0_ESR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ESR_SHIFT)) & DDRPHY_ACIOCR0_ESR_MASK) #define DDRPHY_ACIOCR0_RESERVED_25_24_MASK (0x3000000U) #define DDRPHY_ACIOCR0_RESERVED_25_24_SHIFT (24U) /*! RESERVED_25_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACIOCR0_RESERVED_25_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_25_24_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_25_24_MASK) #define DDRPHY_ACIOCR0_RSTODT_MASK (0x4000000U) #define DDRPHY_ACIOCR0_RSTODT_SHIFT (26U) /*! RSTODT - SDRAM Reset On-Die Termination */ #define DDRPHY_ACIOCR0_RSTODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RSTODT_SHIFT)) & DDRPHY_ACIOCR0_RSTODT_MASK) #define DDRPHY_ACIOCR0_RESERVED_27_MASK (0x8000000U) #define DDRPHY_ACIOCR0_RESERVED_27_SHIFT (27U) /*! RESERVED_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACIOCR0_RESERVED_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_27_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_27_MASK) #define DDRPHY_ACIOCR0_RSTPDR_MASK (0x10000000U) #define DDRPHY_ACIOCR0_RSTPDR_SHIFT (28U) /*! RSTPDR - SDRAM Reset Power Down Receiver */ #define DDRPHY_ACIOCR0_RSTPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RSTPDR_SHIFT)) & DDRPHY_ACIOCR0_RSTPDR_MASK) #define DDRPHY_ACIOCR0_RSTIOM_MASK (0x20000000U) #define DDRPHY_ACIOCR0_RSTIOM_SHIFT (29U) /*! RSTIOM - SDRAM Reset I/O Mode */ #define DDRPHY_ACIOCR0_RSTIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RSTIOM_SHIFT)) & DDRPHY_ACIOCR0_RSTIOM_MASK) #define DDRPHY_ACIOCR0_ACSR_MASK (0xC0000000U) #define DDRPHY_ACIOCR0_ACSR_SHIFT (30U) /*! ACSR - Address/Command Slew Rate (D3F I/O Only) */ #define DDRPHY_ACIOCR0_ACSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACSR_SHIFT)) & DDRPHY_ACIOCR0_ACSR_MASK) /*! @} */ /*! @name ACIOCR1 - AC I/O Configuration Register 1 */ /*! @{ */ #define DDRPHY_ACIOCR1_AOEMODE_MASK (0xFFFFFFFFU) #define DDRPHY_ACIOCR1_AOEMODE_SHIFT (0U) /*! AOEMODE - SDRAM Address Output Enable (OE) Mode Selection */ #define DDRPHY_ACIOCR1_AOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR1_AOEMODE_SHIFT)) & DDRPHY_ACIOCR1_AOEMODE_MASK) /*! @} */ /*! @name ACIOCR2 - AC I/O Configuration Register 2 */ /*! @{ */ #define DDRPHY_ACIOCR2_ACCLKGATE0_MASK (0xFFFFFFU) #define DDRPHY_ACIOCR2_ACCLKGATE0_SHIFT (0U) /*! ACCLKGATE0 - Clock gating for AC D slices [23:0] */ #define DDRPHY_ACIOCR2_ACCLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACCLKGATE0_MASK) #define DDRPHY_ACIOCR2_CKCLKGATE0_MASK (0x3000000U) #define DDRPHY_ACIOCR2_CKCLKGATE0_SHIFT (24U) /*! CKCLKGATE0 - Clock gating for CK D slices [1:0] */ #define DDRPHY_ACIOCR2_CKCLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_CKCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_CKCLKGATE0_MASK) #define DDRPHY_ACIOCR2_CKNCLKGATE0_MASK (0xC000000U) #define DDRPHY_ACIOCR2_CKNCLKGATE0_SHIFT (26U) /*! CKNCLKGATE0 - Clock gating for CK# D slices [1:0] */ #define DDRPHY_ACIOCR2_CKNCLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_CKNCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_CKNCLKGATE0_MASK) #define DDRPHY_ACIOCR2_ACTECLKGATE0_MASK (0x10000000U) #define DDRPHY_ACIOCR2_ACTECLKGATE0_SHIFT (28U) /*! ACTECLKGATE0 - Clock gating for Termination Enable D slices [0] */ #define DDRPHY_ACIOCR2_ACTECLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACTECLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACTECLKGATE0_MASK) #define DDRPHY_ACIOCR2_ACPDRCLKGATE0_MASK (0x20000000U) #define DDRPHY_ACIOCR2_ACPDRCLKGATE0_SHIFT (29U) /*! ACPDRCLKGATE0 - Clock gating for Power Down Receiver D slices [0] */ #define DDRPHY_ACIOCR2_ACPDRCLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACPDRCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACPDRCLKGATE0_MASK) #define DDRPHY_ACIOCR2_ACOECLKGATE0_MASK (0x40000000U) #define DDRPHY_ACIOCR2_ACOECLKGATE0_SHIFT (30U) /*! ACOECLKGATE0 - Clock gating for Output Enable D slices [0] */ #define DDRPHY_ACIOCR2_ACOECLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACOECLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACOECLKGATE0_MASK) #define DDRPHY_ACIOCR2_CLKGENCLKGATE_MASK (0x80000000U) #define DDRPHY_ACIOCR2_CLKGENCLKGATE_SHIFT (31U) /*! CLKGENCLKGATE - Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice */ #define DDRPHY_ACIOCR2_CLKGENCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_CLKGENCLKGATE_SHIFT)) & DDRPHY_ACIOCR2_CLKGENCLKGATE_MASK) /*! @} */ /*! @name ACIOCR3 - AC I/O Configuration Register 3 */ /*! @{ */ #define DDRPHY_ACIOCR3_CKOEMODE_MASK (0xFU) #define DDRPHY_ACIOCR3_CKOEMODE_SHIFT (0U) /*! CKOEMODE - SDRAM CK Output Enable (OE) Mode Selection. */ #define DDRPHY_ACIOCR3_CKOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_CKOEMODE_SHIFT)) & DDRPHY_ACIOCR3_CKOEMODE_MASK) #define DDRPHY_ACIOCR3_CKOEMODE_RSVD_MASK (0xF0U) #define DDRPHY_ACIOCR3_CKOEMODE_RSVD_SHIFT (4U) /*! CKOEMODE_RSVD - Reserved. Return zeros on reads. */ #define DDRPHY_ACIOCR3_CKOEMODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_CKOEMODE_RSVD_SHIFT)) & DDRPHY_ACIOCR3_CKOEMODE_RSVD_MASK) #define DDRPHY_ACIOCR3_RESERVED_15_8_MASK (0xFF00U) #define DDRPHY_ACIOCR3_RESERVED_15_8_SHIFT (8U) /*! RESERVED_15_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACIOCR3_RESERVED_15_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_RESERVED_15_8_SHIFT)) & DDRPHY_ACIOCR3_RESERVED_15_8_MASK) #define DDRPHY_ACIOCR3_ACTOEMODE_MASK (0x30000U) #define DDRPHY_ACIOCR3_ACTOEMODE_SHIFT (16U) /*! ACTOEMODE - SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) */ #define DDRPHY_ACIOCR3_ACTOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_ACTOEMODE_SHIFT)) & DDRPHY_ACIOCR3_ACTOEMODE_MASK) #define DDRPHY_ACIOCR3_A16OEMODE_MASK (0xC0000U) #define DDRPHY_ACIOCR3_A16OEMODE_SHIFT (18U) /*! A16OEMODE - SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection */ #define DDRPHY_ACIOCR3_A16OEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_A16OEMODE_SHIFT)) & DDRPHY_ACIOCR3_A16OEMODE_MASK) #define DDRPHY_ACIOCR3_A17OEMODE_MASK (0x300000U) #define DDRPHY_ACIOCR3_A17OEMODE_SHIFT (20U) /*! A17OEMODE - SDRAM A[17] Output Enable (OE) Mode Selection */ #define DDRPHY_ACIOCR3_A17OEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_A17OEMODE_SHIFT)) & DDRPHY_ACIOCR3_A17OEMODE_MASK) #define DDRPHY_ACIOCR3_BAOEMODE_MASK (0x3C00000U) #define DDRPHY_ACIOCR3_BAOEMODE_SHIFT (22U) /*! BAOEMODE - SDRAM Bank Address Output Enable (OE) Mode Selection */ #define DDRPHY_ACIOCR3_BAOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_BAOEMODE_SHIFT)) & DDRPHY_ACIOCR3_BAOEMODE_MASK) #define DDRPHY_ACIOCR3_BGOEMODE_MASK (0x3C000000U) #define DDRPHY_ACIOCR3_BGOEMODE_SHIFT (26U) /*! BGOEMODE - SDRAM Bank Group Output Enable (OE) Mode Selection */ #define DDRPHY_ACIOCR3_BGOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_BGOEMODE_SHIFT)) & DDRPHY_ACIOCR3_BGOEMODE_MASK) #define DDRPHY_ACIOCR3_PAROEMODE_MASK (0xC0000000U) #define DDRPHY_ACIOCR3_PAROEMODE_SHIFT (30U) /*! PAROEMODE - SDRAM Parity Output Enable (OE) Mode Selection */ #define DDRPHY_ACIOCR3_PAROEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_PAROEMODE_SHIFT)) & DDRPHY_ACIOCR3_PAROEMODE_MASK) /*! @} */ /*! @name ACIOCR4 - AC I/O Configuration Register 4 */ /*! @{ */ #define DDRPHY_ACIOCR4_ACCLKGATE1_MASK (0xFFFFFFU) #define DDRPHY_ACIOCR4_ACCLKGATE1_SHIFT (0U) /*! ACCLKGATE1 - Clock gating for AC D slices [47:24] */ #define DDRPHY_ACIOCR4_ACCLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACCLKGATE1_MASK) #define DDRPHY_ACIOCR4_CKCLKGATE1_MASK (0x3000000U) #define DDRPHY_ACIOCR4_CKCLKGATE1_SHIFT (24U) /*! CKCLKGATE1 - Clock gating for CK D slices [3:2] */ #define DDRPHY_ACIOCR4_CKCLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_CKCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_CKCLKGATE1_MASK) #define DDRPHY_ACIOCR4_CKNCLKGATE1_MASK (0xC000000U) #define DDRPHY_ACIOCR4_CKNCLKGATE1_SHIFT (26U) /*! CKNCLKGATE1 - Clock gating for CK# D slices [3:2] */ #define DDRPHY_ACIOCR4_CKNCLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_CKNCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_CKNCLKGATE1_MASK) #define DDRPHY_ACIOCR4_ACTECLKGATE1_MASK (0x10000000U) #define DDRPHY_ACIOCR4_ACTECLKGATE1_SHIFT (28U) /*! ACTECLKGATE1 - Clock gating for Termination Enable D slices [1] */ #define DDRPHY_ACIOCR4_ACTECLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACTECLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACTECLKGATE1_MASK) #define DDRPHY_ACIOCR4_ACPDRCLKGATE1_MASK (0x20000000U) #define DDRPHY_ACIOCR4_ACPDRCLKGATE1_SHIFT (29U) /*! ACPDRCLKGATE1 - Clock gating for Power Down Receiver D slices [1] */ #define DDRPHY_ACIOCR4_ACPDRCLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACPDRCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACPDRCLKGATE1_MASK) #define DDRPHY_ACIOCR4_ACOECLKGATE1_MASK (0x40000000U) #define DDRPHY_ACIOCR4_ACOECLKGATE1_SHIFT (30U) /*! ACOECLKGATE1 - Clock gating for Output Enable D slices [1] */ #define DDRPHY_ACIOCR4_ACOECLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACOECLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACOECLKGATE1_MASK) #define DDRPHY_ACIOCR4_LBCLKGATE_MASK (0x80000000U) #define DDRPHY_ACIOCR4_LBCLKGATE_SHIFT (31U) /*! LBCLKGATE - Clock gating for AC LB slices and loopback read valid slices */ #define DDRPHY_ACIOCR4_LBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_LBCLKGATE_SHIFT)) & DDRPHY_ACIOCR4_LBCLKGATE_MASK) /*! @} */ /*! @name ACIOCR5 - AC I/O Configuration Register 5 */ /*! @{ */ #define DDRPHY_ACIOCR5_ACRXM_MASK (0x7FFU) #define DDRPHY_ACIOCR5_ACRXM_SHIFT (0U) /*! ACRXM - AC IO Receiver Mode */ #define DDRPHY_ACIOCR5_ACRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACRXM_SHIFT)) & DDRPHY_ACIOCR5_ACRXM_MASK) #define DDRPHY_ACIOCR5_ACTXM_MASK (0x3FF800U) #define DDRPHY_ACIOCR5_ACTXM_SHIFT (11U) /*! ACTXM - AC IO Transmitter Mode */ #define DDRPHY_ACIOCR5_ACTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACTXM_SHIFT)) & DDRPHY_ACIOCR5_ACTXM_MASK) #define DDRPHY_ACIOCR5_ACXIOM_MASK (0x1C00000U) #define DDRPHY_ACIOCR5_ACXIOM_SHIFT (22U) /*! ACXIOM - AC IO Mode */ #define DDRPHY_ACIOCR5_ACXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACXIOM_SHIFT)) & DDRPHY_ACIOCR5_ACXIOM_MASK) #define DDRPHY_ACIOCR5_ACVREFIOM_MASK (0xE000000U) #define DDRPHY_ACIOCR5_ACVREFIOM_SHIFT (25U) /*! ACVREFIOM - IOM bits for PVREF and PVREFE cells in AC IO ring */ #define DDRPHY_ACIOCR5_ACVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACVREFIOM_SHIFT)) & DDRPHY_ACIOCR5_ACVREFIOM_MASK) #define DDRPHY_ACIOCR5_RESERVED_31_28_MASK (0xF0000000U) #define DDRPHY_ACIOCR5_RESERVED_31_28_SHIFT (28U) /*! RESERVED_31_28 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACIOCR5_RESERVED_31_28(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_RESERVED_31_28_SHIFT)) & DDRPHY_ACIOCR5_RESERVED_31_28_MASK) /*! @} */ /*! @name IOVCR0 - IO VREF Control Register 0 */ /*! @{ */ #define DDRPHY_IOVCR0_ACVREFISEL_MASK (0x7FU) #define DDRPHY_IOVCR0_ACVREFISEL_SHIFT (0U) /*! ACVREFISEL - REFSEL Control for internal AC IOs */ #define DDRPHY_IOVCR0_ACVREFISEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACVREFISEL_SHIFT)) & DDRPHY_IOVCR0_ACVREFISEL_MASK) #define DDRPHY_IOVCR0_ACVREFISELRANGE_MASK (0x80U) #define DDRPHY_IOVCR0_ACVREFISELRANGE_SHIFT (7U) /*! ACVREFISELRANGE - Internal VREF generator REFSEL ragne select */ #define DDRPHY_IOVCR0_ACVREFISELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACVREFISELRANGE_SHIFT)) & DDRPHY_IOVCR0_ACVREFISELRANGE_MASK) #define DDRPHY_IOVCR0_ACREFSSEL_MASK (0x7F00U) #define DDRPHY_IOVCR0_ACREFSSEL_SHIFT (8U) /*! ACREFSSEL - Address/command lane Single-End VREF Select */ #define DDRPHY_IOVCR0_ACREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFSSEL_SHIFT)) & DDRPHY_IOVCR0_ACREFSSEL_MASK) #define DDRPHY_IOVCR0_ACREFSSELRANGE_MASK (0x8000U) #define DDRPHY_IOVCR0_ACREFSSELRANGE_SHIFT (15U) /*! ACREFSSELRANGE - Single ended VREF generator REFSEL range select */ #define DDRPHY_IOVCR0_ACREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFSSELRANGE_SHIFT)) & DDRPHY_IOVCR0_ACREFSSELRANGE_MASK) #define DDRPHY_IOVCR0_ACREFESEL_MASK (0x7F0000U) #define DDRPHY_IOVCR0_ACREFESEL_SHIFT (16U) /*! ACREFESEL - Address/command lane External VREF Select */ #define DDRPHY_IOVCR0_ACREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFESEL_SHIFT)) & DDRPHY_IOVCR0_ACREFESEL_MASK) #define DDRPHY_IOVCR0_ACREFESELRANGE_MASK (0x800000U) #define DDRPHY_IOVCR0_ACREFESELRANGE_SHIFT (23U) /*! ACREFESELRANGE - External VREF generato REFSEL range select */ #define DDRPHY_IOVCR0_ACREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFESELRANGE_SHIFT)) & DDRPHY_IOVCR0_ACREFESELRANGE_MASK) #define DDRPHY_IOVCR0_ACREFIEN_MASK (0x1000000U) #define DDRPHY_IOVCR0_ACREFIEN_SHIFT (24U) /*! ACREFIEN - Address/command lane Internal VREF Enable */ #define DDRPHY_IOVCR0_ACREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFIEN_SHIFT)) & DDRPHY_IOVCR0_ACREFIEN_MASK) #define DDRPHY_IOVCR0_ACREFSEN_MASK (0x2000000U) #define DDRPHY_IOVCR0_ACREFSEN_SHIFT (25U) /*! ACREFSEN - Address/command lane Single-End VREF Enable */ #define DDRPHY_IOVCR0_ACREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFSEN_SHIFT)) & DDRPHY_IOVCR0_ACREFSEN_MASK) #define DDRPHY_IOVCR0_ACREFEEN_MASK (0xC000000U) #define DDRPHY_IOVCR0_ACREFEEN_SHIFT (26U) /*! ACREFEEN - Address/command lane Internal VREF Enable */ #define DDRPHY_IOVCR0_ACREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFEEN_SHIFT)) & DDRPHY_IOVCR0_ACREFEEN_MASK) #define DDRPHY_IOVCR0_ACREFPEN_MASK (0x10000000U) #define DDRPHY_IOVCR0_ACREFPEN_SHIFT (28U) /*! ACREFPEN - Address/command lane VREF Pad Enable */ #define DDRPHY_IOVCR0_ACREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFPEN_SHIFT)) & DDRPHY_IOVCR0_ACREFPEN_MASK) #define DDRPHY_IOVCR0_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_IOVCR0_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Reserved. Return zeroes on reads. */ #define DDRPHY_IOVCR0_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_RESERVED_31_29_SHIFT)) & DDRPHY_IOVCR0_RESERVED_31_29_MASK) /*! @} */ /*! @name IOVCR1 - IO VREF Control Register 1 */ /*! @{ */ #define DDRPHY_IOVCR1_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_IOVCR1_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_IOVCR1_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR1_RESERVED_31_0_SHIFT)) & DDRPHY_IOVCR1_RESERVED_31_0_MASK) /*! @} */ /*! @name VTCR0 - VREF Training Control Register 0 */ /*! @{ */ #define DDRPHY_VTCR0_DVINIT_MASK (0x3FU) #define DDRPHY_VTCR0_DVINIT_SHIFT (0U) /*! DVINIT - Initial DRAM DQ VREF value used during DRAM VREF training */ #define DDRPHY_VTCR0_DVINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVINIT_SHIFT)) & DDRPHY_VTCR0_DVINIT_MASK) #define DDRPHY_VTCR0_DVMIN_MASK (0xFC0U) #define DDRPHY_VTCR0_DVMIN_SHIFT (6U) /*! DVMIN - Minimum VREF limit value used during DRAM VREF training */ #define DDRPHY_VTCR0_DVMIN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVMIN_SHIFT)) & DDRPHY_VTCR0_DVMIN_MASK) #define DDRPHY_VTCR0_DVMAX_MASK (0x3F000U) #define DDRPHY_VTCR0_DVMAX_SHIFT (12U) /*! DVMAX - Maximum VREF limit value used during DRAM VREF training */ #define DDRPHY_VTCR0_DVMAX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVMAX_SHIFT)) & DDRPHY_VTCR0_DVMAX_MASK) #define DDRPHY_VTCR0_DVSS_MASK (0x3C0000U) #define DDRPHY_VTCR0_DVSS_SHIFT (18U) /*! DVSS - DRAM DQ VREF step size used during DRAM VREF training */ #define DDRPHY_VTCR0_DVSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVSS_SHIFT)) & DDRPHY_VTCR0_DVSS_MASK) #define DDRPHY_VTCR0_VWCR_MASK (0x3C00000U) #define DDRPHY_VTCR0_VWCR_SHIFT (22U) /*! VWCR - VREF Word Count */ #define DDRPHY_VTCR0_VWCR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_VWCR_SHIFT)) & DDRPHY_VTCR0_VWCR_MASK) #define DDRPHY_VTCR0_RESERVED_26_MASK (0x4000000U) #define DDRPHY_VTCR0_RESERVED_26_SHIFT (26U) /*! RESERVED_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_VTCR0_RESERVED_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_RESERVED_26_SHIFT)) & DDRPHY_VTCR0_RESERVED_26_MASK) #define DDRPHY_VTCR0_PDAEN_MASK (0x8000000U) #define DDRPHY_VTCR0_PDAEN_SHIFT (27U) /*! PDAEN - Per Device Addressability Enable */ #define DDRPHY_VTCR0_PDAEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_PDAEN_SHIFT)) & DDRPHY_VTCR0_PDAEN_MASK) #define DDRPHY_VTCR0_DVEN_MASK (0x10000000U) #define DDRPHY_VTCR0_DVEN_SHIFT (28U) /*! DVEN - DRM DQ VREF training Enable */ #define DDRPHY_VTCR0_DVEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVEN_SHIFT)) & DDRPHY_VTCR0_DVEN_MASK) #define DDRPHY_VTCR0_tVREF_MASK (0xE0000000U) #define DDRPHY_VTCR0_tVREF_SHIFT (29U) /*! tVREF - Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training */ #define DDRPHY_VTCR0_tVREF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_tVREF_SHIFT)) & DDRPHY_VTCR0_tVREF_MASK) /*! @} */ /*! @name VTCR1 - VREF Training Control Register 1 */ /*! @{ */ #define DDRPHY_VTCR1_HVIO_MASK (0x1U) #define DDRPHY_VTCR1_HVIO_SHIFT (0U) /*! HVIO - Host IO Type Control */ #define DDRPHY_VTCR1_HVIO(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVIO_SHIFT)) & DDRPHY_VTCR1_HVIO_MASK) #define DDRPHY_VTCR1_HVEN_MASK (0x2U) #define DDRPHY_VTCR1_HVEN_SHIFT (1U) /*! HVEN - HOST (IO) internal VREF training Enable */ #define DDRPHY_VTCR1_HVEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVEN_SHIFT)) & DDRPHY_VTCR1_HVEN_MASK) #define DDRPHY_VTCR1_ENUM_MASK (0x4U) #define DDRPHY_VTCR1_ENUM_SHIFT (2U) /*! ENUM - Number of LCDL Eye points for which VREF training is repeated */ #define DDRPHY_VTCR1_ENUM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_ENUM_SHIFT)) & DDRPHY_VTCR1_ENUM_MASK) #define DDRPHY_VTCR1_EOFF_MASK (0x18U) #define DDRPHY_VTCR1_EOFF_SHIFT (3U) /*! EOFF - Eye LCDL Offset value for VREF training */ #define DDRPHY_VTCR1_EOFF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_EOFF_SHIFT)) & DDRPHY_VTCR1_EOFF_MASK) #define DDRPHY_VTCR1_tVREFIO_MASK (0xE0U) #define DDRPHY_VTCR1_tVREFIO_SHIFT (5U) /*! tVREFIO - Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training */ #define DDRPHY_VTCR1_tVREFIO(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_tVREFIO_SHIFT)) & DDRPHY_VTCR1_tVREFIO_MASK) #define DDRPHY_VTCR1_SHREN_MASK (0x100U) #define DDRPHY_VTCR1_SHREN_SHIFT (8U) /*! SHREN - Static Host Vref Rank Enable */ #define DDRPHY_VTCR1_SHREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_SHREN_SHIFT)) & DDRPHY_VTCR1_SHREN_MASK) #define DDRPHY_VTCR1_SHRNK_MASK (0x600U) #define DDRPHY_VTCR1_SHRNK_SHIFT (9U) /*! SHRNK - Static Host Vref Rank Value */ #define DDRPHY_VTCR1_SHRNK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_SHRNK_SHIFT)) & DDRPHY_VTCR1_SHRNK_MASK) #define DDRPHY_VTCR1_RESERVED_11_MASK (0x800U) #define DDRPHY_VTCR1_RESERVED_11_SHIFT (11U) /*! RESERVED_11 - Reserved. Returns zeroes on reads. */ #define DDRPHY_VTCR1_RESERVED_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_11_SHIFT)) & DDRPHY_VTCR1_RESERVED_11_MASK) #define DDRPHY_VTCR1_HVMIN_MASK (0x7F000U) #define DDRPHY_VTCR1_HVMIN_SHIFT (12U) /*! HVMIN - Minimum VREF limit value used during DRAM VREF training. */ #define DDRPHY_VTCR1_HVMIN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVMIN_SHIFT)) & DDRPHY_VTCR1_HVMIN_MASK) #define DDRPHY_VTCR1_RESERVED_19_MASK (0x80000U) #define DDRPHY_VTCR1_RESERVED_19_SHIFT (19U) /*! RESERVED_19 - Reserved. Returns zeroes on reads. */ #define DDRPHY_VTCR1_RESERVED_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_19_SHIFT)) & DDRPHY_VTCR1_RESERVED_19_MASK) #define DDRPHY_VTCR1_HVMAX_MASK (0x7F00000U) #define DDRPHY_VTCR1_HVMAX_SHIFT (20U) /*! HVMAX - Maximum VREF limit value used during DRAM VREF training. */ #define DDRPHY_VTCR1_HVMAX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVMAX_SHIFT)) & DDRPHY_VTCR1_HVMAX_MASK) #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) #define DDRPHY_VTCR1_RESERVED_27_SHIFT (27U) /*! RESERVED_27 - Reserved. Returns zeroes on reads. */ #define DDRPHY_VTCR1_RESERVED_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK) #define DDRPHY_VTCR1_HVSS_MASK (0xF0000000U) #define DDRPHY_VTCR1_HVSS_SHIFT (28U) /*! HVSS - Host VREF step size used during VREF training. The register value of N indicates step size of (N+1) */ #define DDRPHY_VTCR1_HVSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVSS_SHIFT)) & DDRPHY_VTCR1_HVSS_MASK) /*! @} */ /*! @name ACBDLR0 - AC Bit Delay Line Register 0 */ /*! @{ */ #define DDRPHY_ACBDLR0_CK0BD_MASK (0x3FU) #define DDRPHY_ACBDLR0_CK0BD_SHIFT (0U) /*! CK0BD - CK0 Bit Delay */ #define DDRPHY_ACBDLR0_CK0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK0BD_SHIFT)) & DDRPHY_ACBDLR0_CK0BD_MASK) #define DDRPHY_ACBDLR0_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR0_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR0_CK1BD_MASK (0x3F00U) #define DDRPHY_ACBDLR0_CK1BD_SHIFT (8U) /*! CK1BD - CK1 Bit Delay */ #define DDRPHY_ACBDLR0_CK1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK1BD_SHIFT)) & DDRPHY_ACBDLR0_CK1BD_MASK) #define DDRPHY_ACBDLR0_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR0_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR0_CK2BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR0_CK2BD_SHIFT (16U) /*! CK2BD - CK2 Bit Delay */ #define DDRPHY_ACBDLR0_CK2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK2BD_SHIFT)) & DDRPHY_ACBDLR0_CK2BD_MASK) #define DDRPHY_ACBDLR0_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR0_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR0_CK3BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR0_CK3BD_SHIFT (24U) /*! CK3BD - CK3 Bit Delay */ #define DDRPHY_ACBDLR0_CK3BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK3BD_SHIFT)) & DDRPHY_ACBDLR0_CK3BD_MASK) #define DDRPHY_ACBDLR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR1 - AC Bit Delay Line Register 1 */ /*! @{ */ #define DDRPHY_ACBDLR1_ACTBD_MASK (0x3FU) #define DDRPHY_ACBDLR1_ACTBD_SHIFT (0U) /*! ACTBD - Delay select for the BDL on ACTN. */ #define DDRPHY_ACBDLR1_ACTBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_ACTBD_SHIFT)) & DDRPHY_ACBDLR1_ACTBD_MASK) #define DDRPHY_ACBDLR1_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR1_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR1_A17BD_MASK (0x3F00U) #define DDRPHY_ACBDLR1_A17BD_SHIFT (8U) /*! A17BD - Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS. */ #define DDRPHY_ACBDLR1_A17BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_A17BD_SHIFT)) & DDRPHY_ACBDLR1_A17BD_MASK) #define DDRPHY_ACBDLR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR1_A16BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR1_A16BD_SHIFT (16U) /*! A16BD - Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE. */ #define DDRPHY_ACBDLR1_A16BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_A16BD_SHIFT)) & DDRPHY_ACBDLR1_A16BD_MASK) #define DDRPHY_ACBDLR1_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR1_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR1_PARBD_MASK (0x3F000000U) #define DDRPHY_ACBDLR1_PARBD_SHIFT (24U) /*! PARBD - Delay select for the BDL on Parity. */ #define DDRPHY_ACBDLR1_PARBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_PARBD_SHIFT)) & DDRPHY_ACBDLR1_PARBD_MASK) #define DDRPHY_ACBDLR1_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR1_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR2 - AC Bit Delay Line Register 2 */ /*! @{ */ #define DDRPHY_ACBDLR2_BA0BD_MASK (0x3FU) #define DDRPHY_ACBDLR2_BA0BD_SHIFT (0U) /*! BA0BD - Delay select for the BDL on BA[0]. */ #define DDRPHY_ACBDLR2_BA0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BA0BD_SHIFT)) & DDRPHY_ACBDLR2_BA0BD_MASK) #define DDRPHY_ACBDLR2_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR2_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR2_BA1BD_MASK (0x3F00U) #define DDRPHY_ACBDLR2_BA1BD_SHIFT (8U) /*! BA1BD - Delay select for the BDL on BA[1]. */ #define DDRPHY_ACBDLR2_BA1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BA1BD_SHIFT)) & DDRPHY_ACBDLR2_BA1BD_MASK) #define DDRPHY_ACBDLR2_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR2_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reser.ved Return zeroes on reads. */ #define DDRPHY_ACBDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR2_BG0BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR2_BG0BD_SHIFT (16U) /*! BG0BD - Delay select for the BDL on BG[0]. */ #define DDRPHY_ACBDLR2_BG0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BG0BD_SHIFT)) & DDRPHY_ACBDLR2_BG0BD_MASK) #define DDRPHY_ACBDLR2_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR2_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR2_BG1BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR2_BG1BD_SHIFT (24U) /*! BG1BD - Delay select for the BDL on BG[1]. */ #define DDRPHY_ACBDLR2_BG1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BG1BD_SHIFT)) & DDRPHY_ACBDLR2_BG1BD_MASK) #define DDRPHY_ACBDLR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR3 - AC Bit Delay Line Register 3 */ /*! @{ */ #define DDRPHY_ACBDLR3_CS0BD_MASK (0x3FU) #define DDRPHY_ACBDLR3_CS0BD_SHIFT (0U) /*! CS0BD - Delay select for the BDL on CS[0]. */ #define DDRPHY_ACBDLR3_CS0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS0BD_SHIFT)) & DDRPHY_ACBDLR3_CS0BD_MASK) #define DDRPHY_ACBDLR3_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR3_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR3_CS1BD_MASK (0x3F00U) #define DDRPHY_ACBDLR3_CS1BD_SHIFT (8U) /*! CS1BD - Delay select for the BDL on CS[1]. */ #define DDRPHY_ACBDLR3_CS1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS1BD_SHIFT)) & DDRPHY_ACBDLR3_CS1BD_MASK) #define DDRPHY_ACBDLR3_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR3_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR3_CS2BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR3_CS2BD_SHIFT (16U) /*! CS2BD - Delay select for the BDL on CS[2]. */ #define DDRPHY_ACBDLR3_CS2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS2BD_SHIFT)) & DDRPHY_ACBDLR3_CS2BD_MASK) #define DDRPHY_ACBDLR3_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR3_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR3_CS3BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR3_CS3BD_SHIFT (24U) /*! CS3BD - Delay select for the BDL on CS[3]. */ #define DDRPHY_ACBDLR3_CS3BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS3BD_SHIFT)) & DDRPHY_ACBDLR3_CS3BD_MASK) #define DDRPHY_ACBDLR3_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR3_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR4 - AC Bit Delay Line Register 4 */ /*! @{ */ #define DDRPHY_ACBDLR4_ODT0BD_MASK (0x3FU) #define DDRPHY_ACBDLR4_ODT0BD_SHIFT (0U) /*! ODT0BD - Delay select for the BDL on ODT[0]. */ #define DDRPHY_ACBDLR4_ODT0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT0BD_SHIFT)) & DDRPHY_ACBDLR4_ODT0BD_MASK) #define DDRPHY_ACBDLR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR4_ODT1BD_MASK (0x3F00U) #define DDRPHY_ACBDLR4_ODT1BD_SHIFT (8U) /*! ODT1BD - Delay select for the BDL on ODT[1]. */ #define DDRPHY_ACBDLR4_ODT1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT1BD_SHIFT)) & DDRPHY_ACBDLR4_ODT1BD_MASK) #define DDRPHY_ACBDLR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR4_ODT2BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR4_ODT2BD_SHIFT (16U) /*! ODT2BD - Delay select for the BDL on ODT[2]. */ #define DDRPHY_ACBDLR4_ODT2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT2BD_SHIFT)) & DDRPHY_ACBDLR4_ODT2BD_MASK) #define DDRPHY_ACBDLR4_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR4_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR4_ODT3BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR4_ODT3BD_SHIFT (24U) /*! ODT3BD - Delay select for the BDL on ODT[3]. */ #define DDRPHY_ACBDLR4_ODT3BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT3BD_SHIFT)) & DDRPHY_ACBDLR4_ODT3BD_MASK) #define DDRPHY_ACBDLR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR5 - AC Bit Delay Line Register 5 */ /*! @{ */ #define DDRPHY_ACBDLR5_CKE0BD_MASK (0x3FU) #define DDRPHY_ACBDLR5_CKE0BD_SHIFT (0U) /*! CKE0BD - Delay select for the BDL on CKE[0]. */ #define DDRPHY_ACBDLR5_CKE0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE0BD_SHIFT)) & DDRPHY_ACBDLR5_CKE0BD_MASK) #define DDRPHY_ACBDLR5_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR5_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR5_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR5_CKE1BD_MASK (0x3F00U) #define DDRPHY_ACBDLR5_CKE1BD_SHIFT (8U) /*! CKE1BD - Delay select for the BDL on CKE[1]. */ #define DDRPHY_ACBDLR5_CKE1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE1BD_SHIFT)) & DDRPHY_ACBDLR5_CKE1BD_MASK) #define DDRPHY_ACBDLR5_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR5_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR5_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR5_CKE2BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR5_CKE2BD_SHIFT (16U) /*! CKE2BD - Delay select for the BDL on CKE[2]. */ #define DDRPHY_ACBDLR5_CKE2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE2BD_SHIFT)) & DDRPHY_ACBDLR5_CKE2BD_MASK) #define DDRPHY_ACBDLR5_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR5_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR5_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR5_CKE3BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR5_CKE3BD_SHIFT (24U) /*! CKE3BD - Delay select for the BDL on CKE[3]. */ #define DDRPHY_ACBDLR5_CKE3BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE3BD_SHIFT)) & DDRPHY_ACBDLR5_CKE3BD_MASK) #define DDRPHY_ACBDLR5_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR5_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR5_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR6 - AC Bit Delay Line Register 6 */ /*! @{ */ #define DDRPHY_ACBDLR6_A00BD_MASK (0x3FU) #define DDRPHY_ACBDLR6_A00BD_SHIFT (0U) /*! A00BD - Delay select for the BDL on Address A[0]. */ #define DDRPHY_ACBDLR6_A00BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A00BD_SHIFT)) & DDRPHY_ACBDLR6_A00BD_MASK) #define DDRPHY_ACBDLR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR6_A01BD_MASK (0x3F00U) #define DDRPHY_ACBDLR6_A01BD_SHIFT (8U) /*! A01BD - Delay select for the BDL on Address A[1]. */ #define DDRPHY_ACBDLR6_A01BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A01BD_SHIFT)) & DDRPHY_ACBDLR6_A01BD_MASK) #define DDRPHY_ACBDLR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR6_A02BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR6_A02BD_SHIFT (16U) /*! A02BD - Delay select for the BDL on Address A[2]. */ #define DDRPHY_ACBDLR6_A02BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A02BD_SHIFT)) & DDRPHY_ACBDLR6_A02BD_MASK) #define DDRPHY_ACBDLR6_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR6_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR6_A03BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR6_A03BD_SHIFT (24U) /*! A03BD - Delay select for the BDL on Address A[3]. */ #define DDRPHY_ACBDLR6_A03BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A03BD_SHIFT)) & DDRPHY_ACBDLR6_A03BD_MASK) #define DDRPHY_ACBDLR6_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR6_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR7 - AC Bit Delay Line Register 7 */ /*! @{ */ #define DDRPHY_ACBDLR7_A04BD_MASK (0x3FU) #define DDRPHY_ACBDLR7_A04BD_SHIFT (0U) /*! A04BD - Delay select for the BDL on Address A[4]. */ #define DDRPHY_ACBDLR7_A04BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A04BD_SHIFT)) & DDRPHY_ACBDLR7_A04BD_MASK) #define DDRPHY_ACBDLR7_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR7_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR7_A05BD_MASK (0x3F00U) #define DDRPHY_ACBDLR7_A05BD_SHIFT (8U) /*! A05BD - Delay select for the BDL on Address A[5]. */ #define DDRPHY_ACBDLR7_A05BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A05BD_SHIFT)) & DDRPHY_ACBDLR7_A05BD_MASK) #define DDRPHY_ACBDLR7_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR7_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR7_A06BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR7_A06BD_SHIFT (16U) /*! A06BD - Delay select for the BDL on Address A[6]. */ #define DDRPHY_ACBDLR7_A06BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A06BD_SHIFT)) & DDRPHY_ACBDLR7_A06BD_MASK) #define DDRPHY_ACBDLR7_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR7_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR7_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR7_A07BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR7_A07BD_SHIFT (24U) /*! A07BD - Delay select for the BDL on Address A[7]. */ #define DDRPHY_ACBDLR7_A07BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A07BD_SHIFT)) & DDRPHY_ACBDLR7_A07BD_MASK) #define DDRPHY_ACBDLR7_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR7_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR7_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR8 - AC Bit Delay Line Register 8 */ /*! @{ */ #define DDRPHY_ACBDLR8_A08BD_MASK (0x3FU) #define DDRPHY_ACBDLR8_A08BD_SHIFT (0U) /*! A08BD - Delay select for the BDL on Address A[8]. */ #define DDRPHY_ACBDLR8_A08BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A08BD_SHIFT)) & DDRPHY_ACBDLR8_A08BD_MASK) #define DDRPHY_ACBDLR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR8_A09BD_MASK (0x3F00U) #define DDRPHY_ACBDLR8_A09BD_SHIFT (8U) /*! A09BD - Delay select for the BDL on Address A[9]. */ #define DDRPHY_ACBDLR8_A09BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A09BD_SHIFT)) & DDRPHY_ACBDLR8_A09BD_MASK) #define DDRPHY_ACBDLR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR8_A10BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR8_A10BD_SHIFT (16U) /*! A10BD - Delay select for the BDL on Address A[10]. */ #define DDRPHY_ACBDLR8_A10BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A10BD_SHIFT)) & DDRPHY_ACBDLR8_A10BD_MASK) #define DDRPHY_ACBDLR8_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR8_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR8_A11BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR8_A11BD_SHIFT (24U) /*! A11BD - Delay select for the BDL on Address A[11]. */ #define DDRPHY_ACBDLR8_A11BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A11BD_SHIFT)) & DDRPHY_ACBDLR8_A11BD_MASK) #define DDRPHY_ACBDLR8_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR8_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR9 - AC Bit Delay Line Register 9 */ /*! @{ */ #define DDRPHY_ACBDLR9_A12BD_MASK (0x3FU) #define DDRPHY_ACBDLR9_A12BD_SHIFT (0U) /*! A12BD - Delay select for the BDL on Address A[12]. */ #define DDRPHY_ACBDLR9_A12BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A12BD_SHIFT)) & DDRPHY_ACBDLR9_A12BD_MASK) #define DDRPHY_ACBDLR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR9_A13BD_MASK (0x3F00U) #define DDRPHY_ACBDLR9_A13BD_SHIFT (8U) /*! A13BD - Delay select for the BDL on Address A[13]. */ #define DDRPHY_ACBDLR9_A13BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A13BD_SHIFT)) & DDRPHY_ACBDLR9_A13BD_MASK) #define DDRPHY_ACBDLR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR9_A14BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR9_A14BD_SHIFT (16U) /*! A14BD - Delay select for the BDL on Address A[14]. */ #define DDRPHY_ACBDLR9_A14BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A14BD_SHIFT)) & DDRPHY_ACBDLR9_A14BD_MASK) #define DDRPHY_ACBDLR9_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR9_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR9_A15BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR9_A15BD_SHIFT (24U) /*! A15BD - Delay select for the BDL on Address A[15]. */ #define DDRPHY_ACBDLR9_A15BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A15BD_SHIFT)) & DDRPHY_ACBDLR9_A15BD_MASK) #define DDRPHY_ACBDLR9_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR9_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR10 - AC Bit Delay Line Register 10 */ /*! @{ */ #define DDRPHY_ACBDLR10_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_ACBDLR10_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR10_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_7_0_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_7_0_MASK) #define DDRPHY_ACBDLR10_CID0BD_MASK (0x3F00U) #define DDRPHY_ACBDLR10_CID0BD_SHIFT (8U) /*! CID0BD - Delay select for the BDL on Chip ID CID[0] */ #define DDRPHY_ACBDLR10_CID0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_CID0BD_SHIFT)) & DDRPHY_ACBDLR10_CID0BD_MASK) #define DDRPHY_ACBDLR10_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR10_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR10_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR10_CID1BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR10_CID1BD_SHIFT (16U) /*! CID1BD - Delay select for the BDL on Chip ID CID[1] */ #define DDRPHY_ACBDLR10_CID1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_CID1BD_SHIFT)) & DDRPHY_ACBDLR10_CID1BD_MASK) #define DDRPHY_ACBDLR10_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR10_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR10_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR10_CID2BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR10_CID2BD_SHIFT (24U) /*! CID2BD - Delay select for the BDL on Chip ID CID[2] */ #define DDRPHY_ACBDLR10_CID2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_CID2BD_SHIFT)) & DDRPHY_ACBDLR10_CID2BD_MASK) #define DDRPHY_ACBDLR10_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR10_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR10_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR11 - AC Bit Delay Line Register 11 */ /*! @{ */ #define DDRPHY_ACBDLR11_CS4BD_MASK (0x3FU) #define DDRPHY_ACBDLR11_CS4BD_SHIFT (0U) /*! CS4BD - Delay select for the BDL on CS[4] */ #define DDRPHY_ACBDLR11_CS4BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS4BD_SHIFT)) & DDRPHY_ACBDLR11_CS4BD_MASK) #define DDRPHY_ACBDLR11_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR11_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR11_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR11_CS5BD_MASK (0x3F00U) #define DDRPHY_ACBDLR11_CS5BD_SHIFT (8U) /*! CS5BD - Delay select for the BDL on CS[5] */ #define DDRPHY_ACBDLR11_CS5BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS5BD_SHIFT)) & DDRPHY_ACBDLR11_CS5BD_MASK) #define DDRPHY_ACBDLR11_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR11_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR11_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR11_CS6BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR11_CS6BD_SHIFT (16U) /*! CS6BD - Delay select for the BDL on CS[6] */ #define DDRPHY_ACBDLR11_CS6BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS6BD_SHIFT)) & DDRPHY_ACBDLR11_CS6BD_MASK) #define DDRPHY_ACBDLR11_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR11_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR11_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR11_CS7BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR11_CS7BD_SHIFT (24U) /*! CS7BD - Delay select for the BDL on CS[7] */ #define DDRPHY_ACBDLR11_CS7BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS7BD_SHIFT)) & DDRPHY_ACBDLR11_CS7BD_MASK) #define DDRPHY_ACBDLR11_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR11_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR11_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR12 - AC Bit Delay Line Register 12 */ /*! @{ */ #define DDRPHY_ACBDLR12_CS8BD_MASK (0x3FU) #define DDRPHY_ACBDLR12_CS8BD_SHIFT (0U) /*! CS8BD - Delay select for the BDL on CS[8] */ #define DDRPHY_ACBDLR12_CS8BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS8BD_SHIFT)) & DDRPHY_ACBDLR12_CS8BD_MASK) #define DDRPHY_ACBDLR12_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR12_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR12_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR12_CS9BD_MASK (0x3F00U) #define DDRPHY_ACBDLR12_CS9BD_SHIFT (8U) /*! CS9BD - Delay select for the BDL on CS[9] */ #define DDRPHY_ACBDLR12_CS9BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS9BD_SHIFT)) & DDRPHY_ACBDLR12_CS9BD_MASK) #define DDRPHY_ACBDLR12_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR12_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR12_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR12_CS10BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR12_CS10BD_SHIFT (16U) /*! CS10BD - Delay select for the BDL on CS[10] */ #define DDRPHY_ACBDLR12_CS10BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS10BD_SHIFT)) & DDRPHY_ACBDLR12_CS10BD_MASK) #define DDRPHY_ACBDLR12_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR12_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR12_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR12_CS11BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR12_CS11BD_SHIFT (24U) /*! CS11BD - Delay select for the BDL on CS[11] */ #define DDRPHY_ACBDLR12_CS11BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS11BD_SHIFT)) & DDRPHY_ACBDLR12_CS11BD_MASK) #define DDRPHY_ACBDLR12_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR12_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR12_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR13 - AC Bit Delay Line Register 13 */ /*! @{ */ #define DDRPHY_ACBDLR13_ODT4BD_MASK (0x3FU) #define DDRPHY_ACBDLR13_ODT4BD_SHIFT (0U) /*! ODT4BD - Delay select for the BDL on ODT[4] */ #define DDRPHY_ACBDLR13_ODT4BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT4BD_SHIFT)) & DDRPHY_ACBDLR13_ODT4BD_MASK) #define DDRPHY_ACBDLR13_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR13_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR13_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR13_ODT5BD_MASK (0x3F00U) #define DDRPHY_ACBDLR13_ODT5BD_SHIFT (8U) /*! ODT5BD - Delay select for the BDL on ODT[5] */ #define DDRPHY_ACBDLR13_ODT5BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT5BD_SHIFT)) & DDRPHY_ACBDLR13_ODT5BD_MASK) #define DDRPHY_ACBDLR13_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR13_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR13_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR13_ODT6BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR13_ODT6BD_SHIFT (16U) /*! ODT6BD - Delay select for the BDL on ODT[6] */ #define DDRPHY_ACBDLR13_ODT6BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT6BD_SHIFT)) & DDRPHY_ACBDLR13_ODT6BD_MASK) #define DDRPHY_ACBDLR13_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR13_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR13_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR13_ODT7BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR13_ODT7BD_SHIFT (24U) /*! ODT7BD - Delay select for the BDL on ODT[7] */ #define DDRPHY_ACBDLR13_ODT7BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT7BD_SHIFT)) & DDRPHY_ACBDLR13_ODT7BD_MASK) #define DDRPHY_ACBDLR13_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR13_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR13_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR14 - AC Bit Delay Line Register 14 */ /*! @{ */ #define DDRPHY_ACBDLR14_CKE4BD_MASK (0x3FU) #define DDRPHY_ACBDLR14_CKE4BD_SHIFT (0U) /*! CKE4BD - Delay select for the BDL on CKE[4] */ #define DDRPHY_ACBDLR14_CKE4BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE4BD_SHIFT)) & DDRPHY_ACBDLR14_CKE4BD_MASK) #define DDRPHY_ACBDLR14_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR14_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR14_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR14_CKE5BD_MASK (0x3F00U) #define DDRPHY_ACBDLR14_CKE5BD_SHIFT (8U) /*! CKE5BD - Delay select for the BDL on CKE[5] */ #define DDRPHY_ACBDLR14_CKE5BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE5BD_SHIFT)) & DDRPHY_ACBDLR14_CKE5BD_MASK) #define DDRPHY_ACBDLR14_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR14_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR14_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR14_CKE6BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR14_CKE6BD_SHIFT (16U) /*! CKE6BD - Delay select for the BDL on CKE[6] */ #define DDRPHY_ACBDLR14_CKE6BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE6BD_SHIFT)) & DDRPHY_ACBDLR14_CKE6BD_MASK) #define DDRPHY_ACBDLR14_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR14_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR14_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR14_CKE7BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR14_CKE7BD_SHIFT (24U) /*! CKE7BD - Delay select for the BDL on CKE[7] */ #define DDRPHY_ACBDLR14_CKE7BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE7BD_SHIFT)) & DDRPHY_ACBDLR14_CKE7BD_MASK) #define DDRPHY_ACBDLR14_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR14_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR14_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_31_30_MASK) /*! @} */ /*! @name ACBDLR15 - AC Bit Delay Line Register 15 */ /*! @{ */ #define DDRPHY_ACBDLR15_PDRBD_MASK (0x3FU) #define DDRPHY_ACBDLR15_PDRBD_SHIFT (0U) /*! PDRBD - Delay select for the BDL on PDR */ #define DDRPHY_ACBDLR15_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_PDRBD_SHIFT)) & DDRPHY_ACBDLR15_PDRBD_MASK) #define DDRPHY_ACBDLR15_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR15_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR15_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR15_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR15_TEBD_MASK (0x3F00U) #define DDRPHY_ACBDLR15_TEBD_SHIFT (8U) /*! TEBD - Delay select for the BDL on TE */ #define DDRPHY_ACBDLR15_TEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_TEBD_SHIFT)) & DDRPHY_ACBDLR15_TEBD_MASK) #define DDRPHY_ACBDLR15_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR15_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR15_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR15_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR15_OEBD_MASK (0x3F0000U) #define DDRPHY_ACBDLR15_OEBD_SHIFT (16U) /*! OEBD - Delay select for the BDL on OE */ #define DDRPHY_ACBDLR15_OEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_OEBD_SHIFT)) & DDRPHY_ACBDLR15_OEBD_MASK) #define DDRPHY_ACBDLR15_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_ACBDLR15_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR15_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_RESERVED_31_22_SHIFT)) & DDRPHY_ACBDLR15_RESERVED_31_22_MASK) /*! @} */ /*! @name ACBDLR16 - AC Bit Delay Line Register 16 */ /*! @{ */ #define DDRPHY_ACBDLR16_CKN0BD_MASK (0x3FU) #define DDRPHY_ACBDLR16_CKN0BD_SHIFT (0U) /*! CKN0BD - Delay select for the BDL on CKN[0] */ #define DDRPHY_ACBDLR16_CKN0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN0BD_SHIFT)) & DDRPHY_ACBDLR16_CKN0BD_MASK) #define DDRPHY_ACBDLR16_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_ACBDLR16_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR16_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_7_6_MASK) #define DDRPHY_ACBDLR16_CKN1BD_MASK (0x3F00U) #define DDRPHY_ACBDLR16_CKN1BD_SHIFT (8U) /*! CKN1BD - Delay select for the BDL on CKN[1] */ #define DDRPHY_ACBDLR16_CKN1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN1BD_SHIFT)) & DDRPHY_ACBDLR16_CKN1BD_MASK) #define DDRPHY_ACBDLR16_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_ACBDLR16_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR16_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_15_14_MASK) #define DDRPHY_ACBDLR16_CKN2BD_MASK (0x3F0000U) #define DDRPHY_ACBDLR16_CKN2BD_SHIFT (16U) /*! CKN2BD - Delay select for the BDL on CKN[2] */ #define DDRPHY_ACBDLR16_CKN2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN2BD_SHIFT)) & DDRPHY_ACBDLR16_CKN2BD_MASK) #define DDRPHY_ACBDLR16_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_ACBDLR16_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR16_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_23_22_MASK) #define DDRPHY_ACBDLR16_CKN3BD_MASK (0x3F000000U) #define DDRPHY_ACBDLR16_CKN3BD_SHIFT (24U) /*! CKN3BD - Delay select for the BDL on CKN[3] */ #define DDRPHY_ACBDLR16_CKN3BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN3BD_SHIFT)) & DDRPHY_ACBDLR16_CKN3BD_MASK) #define DDRPHY_ACBDLR16_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_ACBDLR16_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACBDLR16_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_31_30_MASK) /*! @} */ /*! @name ACLCDLR - AC Local Calibrated Delay Line Register */ /*! @{ */ #define DDRPHY_ACLCDLR_ACD_MASK (0x1FFU) #define DDRPHY_ACLCDLR_ACD_SHIFT (0U) /*! ACD - Address/Command Delay for AC Macro 0 */ #define DDRPHY_ACLCDLR_ACD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_ACD_SHIFT)) & DDRPHY_ACLCDLR_ACD_MASK) #define DDRPHY_ACLCDLR_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_ACLCDLR_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACLCDLR_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_RESERVED_15_9_SHIFT)) & DDRPHY_ACLCDLR_RESERVED_15_9_MASK) #define DDRPHY_ACLCDLR_ACD1_MASK (0x1FF0000U) #define DDRPHY_ACLCDLR_ACD1_SHIFT (16U) /*! ACD1 - Address/Command Delay for AC Macro 1 */ #define DDRPHY_ACLCDLR_ACD1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_ACD1_SHIFT)) & DDRPHY_ACLCDLR_ACD1_MASK) #define DDRPHY_ACLCDLR_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_ACLCDLR_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACLCDLR_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_RESERVED_31_25_SHIFT)) & DDRPHY_ACLCDLR_RESERVED_31_25_MASK) /*! @} */ /*! @name ACMDLR0 - AC Master Delay Line Register 0 */ /*! @{ */ #define DDRPHY_ACMDLR0_IPRD_MASK (0x1FFU) #define DDRPHY_ACMDLR0_IPRD_SHIFT (0U) /*! IPRD - Initial Period */ #define DDRPHY_ACMDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_IPRD_SHIFT)) & DDRPHY_ACMDLR0_IPRD_MASK) #define DDRPHY_ACMDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_ACMDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACMDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_ACMDLR0_RESERVED_15_9_MASK) #define DDRPHY_ACMDLR0_TPRD_MASK (0x1FF0000U) #define DDRPHY_ACMDLR0_TPRD_SHIFT (16U) /*! TPRD - Target Period */ #define DDRPHY_ACMDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_TPRD_SHIFT)) & DDRPHY_ACMDLR0_TPRD_MASK) #define DDRPHY_ACMDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_ACMDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACMDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_ACMDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name ACMDLR1 - AC Master Delay Line Register 1 */ /*! @{ */ #define DDRPHY_ACMDLR1_MDLD_MASK (0x1FFU) #define DDRPHY_ACMDLR1_MDLD_SHIFT (0U) /*! MDLD - MDL Delay for AC Macro 0 */ #define DDRPHY_ACMDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_MDLD_SHIFT)) & DDRPHY_ACMDLR1_MDLD_MASK) #define DDRPHY_ACMDLR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_ACMDLR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACMDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_ACMDLR1_RESERVED_15_9_MASK) #define DDRPHY_ACMDLR1_MDLD1_MASK (0x1FF0000U) #define DDRPHY_ACMDLR1_MDLD1_SHIFT (16U) /*! MDLD1 - MDL Delay for AC Macro 1 */ #define DDRPHY_ACMDLR1_MDLD1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_MDLD1_SHIFT)) & DDRPHY_ACMDLR1_MDLD1_MASK) #define DDRPHY_ACMDLR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_ACMDLR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_ACMDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_ACMDLR1_RESERVED_31_25_MASK) /*! @} */ /*! @name ZQCR - ZQ Impedance Control Register */ /*! @{ */ #define DDRPHY_ZQCR_ZQPD_MASK (0x1U) #define DDRPHY_ZQCR_ZQPD_SHIFT (0U) /*! ZQPD - ZQ Power Down */ #define DDRPHY_ZQCR_ZQPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQPD_SHIFT)) & DDRPHY_ZQCR_ZQPD_MASK) #define DDRPHY_ZQCR_ZCALT_MASK (0x2U) #define DDRPHY_ZQCR_ZCALT_SHIFT (1U) /*! ZCALT - ZQ Calibration Type */ #define DDRPHY_ZQCR_ZCALT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZCALT_SHIFT)) & DDRPHY_ZQCR_ZCALT_MASK) #define DDRPHY_ZQCR_AVGMAX_MASK (0xCU) #define DDRPHY_ZQCR_AVGMAX_SHIFT (2U) /*! AVGMAX - Maximum number of averaging rounds to be used by averaging algorithm */ #define DDRPHY_ZQCR_AVGMAX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_AVGMAX_SHIFT)) & DDRPHY_ZQCR_AVGMAX_MASK) #define DDRPHY_ZQCR_AVGEN_MASK (0x10U) #define DDRPHY_ZQCR_AVGEN_SHIFT (4U) /*! AVGEN - Averaging algorithm enable, if set, enables averaging algorithm */ #define DDRPHY_ZQCR_AVGEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_AVGEN_SHIFT)) & DDRPHY_ZQCR_AVGEN_MASK) #define DDRPHY_ZQCR_IODLMT_MASK (0xE0U) #define DDRPHY_ZQCR_IODLMT_SHIFT (5U) /*! IODLMT - IO VT Drift Limit */ #define DDRPHY_ZQCR_IODLMT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_IODLMT_SHIFT)) & DDRPHY_ZQCR_IODLMT_MASK) #define DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK (0x100U) #define DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT (8U) /*! FORCE_ZCAL_VT_UPDATE - Force ZCAL VT update */ #define DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT)) & DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK) #define DDRPHY_ZQCR_ODT_MODE_MASK (0x600U) #define DDRPHY_ZQCR_ODT_MODE_SHIFT (9U) /*! ODT_MODE - Choice of termination mode */ #define DDRPHY_ZQCR_ODT_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ODT_MODE_SHIFT)) & DDRPHY_ZQCR_ODT_MODE_MASK) #define DDRPHY_ZQCR_ZQREFIEN_MASK (0x800U) #define DDRPHY_ZQCR_ZQREFIEN_SHIFT (11U) /*! ZQREFIEN - ZQ Internal VREF Enable */ #define DDRPHY_ZQCR_ZQREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQREFIEN_SHIFT)) & DDRPHY_ZQCR_ZQREFIEN_MASK) #define DDRPHY_ZQCR_ZQREFPEN_MASK (0x1000U) #define DDRPHY_ZQCR_ZQREFPEN_SHIFT (12U) /*! ZQREFPEN - ZQ VREF Pad Enable */ #define DDRPHY_ZQCR_ZQREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQREFPEN_SHIFT)) & DDRPHY_ZQCR_ZQREFPEN_MASK) #define DDRPHY_ZQCR_PGWAIT_FRQA_MASK (0x7E000U) #define DDRPHY_ZQCR_PGWAIT_FRQA_SHIFT (13U) /*! PGWAIT_FRQA - Programmable Wait for Frequency A */ #define DDRPHY_ZQCR_PGWAIT_FRQA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_PGWAIT_FRQA_SHIFT)) & DDRPHY_ZQCR_PGWAIT_FRQA_MASK) #define DDRPHY_ZQCR_PGWAIT_FRQB_MASK (0x1F80000U) #define DDRPHY_ZQCR_PGWAIT_FRQB_SHIFT (19U) /*! PGWAIT_FRQB - Programmable Wait for Frequency B */ #define DDRPHY_ZQCR_PGWAIT_FRQB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_PGWAIT_FRQB_SHIFT)) & DDRPHY_ZQCR_PGWAIT_FRQB_MASK) #define DDRPHY_ZQCR_ZQREFISELRANGE_MASK (0x2000000U) #define DDRPHY_ZQCR_ZQREFISELRANGE_SHIFT (25U) /*! ZQREFISELRANGE - ZQ VREF Range */ #define DDRPHY_ZQCR_ZQREFISELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQREFISELRANGE_SHIFT)) & DDRPHY_ZQCR_ZQREFISELRANGE_MASK) #define DDRPHY_ZQCR_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQCR_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeroes on reads. */ #define DDRPHY_ZQCR_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_RESERVED_31_26_SHIFT)) & DDRPHY_ZQCR_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ0PR0 - ZQ n Impedance Control Program Register 0 */ /*! @{ */ #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK (0xFU) #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT (0U) /*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) */ #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK) #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK (0xF0U) #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT (4U) /*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) */ #define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK) #define DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_MASK (0xF00U) #define DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT (8U) /*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio */ #define DDRPHY_ZQ0PR0_ZPROG_HOST_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_MASK) #define DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK (0xF000U) #define DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT (12U) /*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio */ #define DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK) #define DDRPHY_ZQ0PR0_PU_DRV_ADJUST_MASK (0x70000U) #define DDRPHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT (16U) /*! PU_DRV_ADJUST - Pullup drive strength adjustment */ #define DDRPHY_ZQ0PR0_PU_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ0PR0_PU_DRV_ADJUST_MASK) #define DDRPHY_ZQ0PR0_PD_DRV_ADJUST_MASK (0x380000U) #define DDRPHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT (19U) /*! PD_DRV_ADJUST - Pulldown drive strength adjustment */ #define DDRPHY_ZQ0PR0_PD_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ0PR0_PD_DRV_ADJUST_MASK) #define DDRPHY_ZQ0PR0_ODT_ADJUST_MASK (0x1C00000U) #define DDRPHY_ZQ0PR0_ODT_ADJUST_SHIFT (22U) /*! ODT_ADJUST - Termination adjustment */ #define DDRPHY_ZQ0PR0_ODT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ0PR0_ODT_ADJUST_MASK) #define DDRPHY_ZQ0PR0_ZLE_MODE_MASK (0x6000000U) #define DDRPHY_ZQ0PR0_ZLE_MODE_SHIFT (25U) /*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB */ #define DDRPHY_ZQ0PR0_ZLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ0PR0_ZLE_MODE_MASK) #define DDRPHY_ZQ0PR0_ZSEGBYP_MASK (0x8000000U) #define DDRPHY_ZQ0PR0_ZSEGBYP_SHIFT (27U) /*! ZSEGBYP - Calibration segment bypass */ #define DDRPHY_ZQ0PR0_ZSEGBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ0PR0_ZSEGBYP_MASK) #define DDRPHY_ZQ0PR0_PU_ODT_ZDEN_MASK (0x10000000U) #define DDRPHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT (28U) /*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable */ #define DDRPHY_ZQ0PR0_PU_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PU_ODT_ZDEN_MASK) #define DDRPHY_ZQ0PR0_PD_ODT_ZDEN_MASK (0x20000000U) #define DDRPHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT (29U) /*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable */ #define DDRPHY_ZQ0PR0_PD_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PD_ODT_ZDEN_MASK) #define DDRPHY_ZQ0PR0_PU_DRV_ZDEN_MASK (0x40000000U) #define DDRPHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT (30U) /*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable */ #define DDRPHY_ZQ0PR0_PU_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PU_DRV_ZDEN_MASK) #define DDRPHY_ZQ0PR0_PD_DRV_ZDEN_MASK (0x80000000U) #define DDRPHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT (31U) /*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable */ #define DDRPHY_ZQ0PR0_PD_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PD_DRV_ZDEN_MASK) /*! @} */ /*! @name ZQ0PR1 - ZQ n Impedance Control Program Register 1 */ /*! @{ */ #define DDRPHY_ZQ0PR1_PD_REFSEL_MASK (0x7FU) #define DDRPHY_ZQ0PR1_PD_REFSEL_SHIFT (0U) /*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell */ #define DDRPHY_ZQ0PR1_PD_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ0PR1_PD_REFSEL_MASK) #define DDRPHY_ZQ0PR1_RESERVED_7_MASK (0x80U) #define DDRPHY_ZQ0PR1_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0PR1_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ0PR1_RESERVED_7_MASK) #define DDRPHY_ZQ0PR1_PU_REFSEL_MASK (0x7F00U) #define DDRPHY_ZQ0PR1_PU_REFSEL_SHIFT (8U) /*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell */ #define DDRPHY_ZQ0PR1_PU_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ0PR1_PU_REFSEL_MASK) #define DDRPHY_ZQ0PR1_RESERVED_31_15_MASK (0xFFFF8000U) #define DDRPHY_ZQ0PR1_RESERVED_31_15_SHIFT (15U) /*! RESERVED_31_15 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0PR1_RESERVED_31_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ0PR1_RESERVED_31_15_MASK) /*! @} */ /*! @name ZQ0DR0 - ZQ n Impedance Control Data Register 0 */ /*! @{ */ #define DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_MASK (0x3FFU) #define DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_SHIFT (0U) /*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result */ #define DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_MASK) #define DDRPHY_ZQ0DR0_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ0DR0_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0DR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0DR0_RESERVED_15_10_MASK) #define DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_MASK (0x3FF0000U) #define DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_SHIFT (16U) /*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result */ #define DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_MASK) #define DDRPHY_ZQ0DR0_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ0DR0_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0DR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0DR0_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ0DR1 - ZQ n Impedance Control Data Register 1 */ /*! @{ */ #define DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_MASK (0x3FFU) #define DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_SHIFT (0U) /*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result */ #define DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_MASK) #define DDRPHY_ZQ0DR1_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ0DR1_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0DR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0DR1_RESERVED_15_10_MASK) #define DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_MASK (0x3FF0000U) #define DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_SHIFT (16U) /*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result */ #define DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_MASK) #define DDRPHY_ZQ0DR1_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ0DR1_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0DR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0DR1_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ0OR0 - ZQ n Impedance Control Override Data Register 0 */ /*! @{ */ #define DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK (0x3FFU) #define DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT (0U) /*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance */ #define DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK) #define DDRPHY_ZQ0OR0_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ0OR0_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0OR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0OR0_RESERVED_15_10_MASK) #define DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK (0x3FF0000U) #define DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT (16U) /*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance */ #define DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK) #define DDRPHY_ZQ0OR0_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ0OR0_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0OR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0OR0_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ0OR1 - ZQ n Impedance Control Override Data Register 1 */ /*! @{ */ #define DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK (0x3FFU) #define DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT (0U) /*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination */ #define DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK) #define DDRPHY_ZQ0OR1_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ0OR1_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0OR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0OR1_RESERVED_15_10_MASK) #define DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK (0x3FF0000U) #define DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT (16U) /*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination */ #define DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK) #define DDRPHY_ZQ0OR1_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ0OR1_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0OR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0OR1_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ0SR - ZQ n Impedance Control Status Register */ /*! @{ */ #define DDRPHY_ZQ0SR_ZPD_MASK (0x3U) #define DDRPHY_ZQ0SR_ZPD_SHIFT (0U) /*! ZPD - Output impedance pull-down calibration status */ #define DDRPHY_ZQ0SR_ZPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZPD_SHIFT)) & DDRPHY_ZQ0SR_ZPD_MASK) #define DDRPHY_ZQ0SR_ZPU_MASK (0xCU) #define DDRPHY_ZQ0SR_ZPU_SHIFT (2U) /*! ZPU - Output impedance pull-up calibration status */ #define DDRPHY_ZQ0SR_ZPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZPU_SHIFT)) & DDRPHY_ZQ0SR_ZPU_MASK) #define DDRPHY_ZQ0SR_OPD_MASK (0x30U) #define DDRPHY_ZQ0SR_OPD_SHIFT (4U) /*! OPD - On-die termination (ODT) pull-down calibration status */ #define DDRPHY_ZQ0SR_OPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_OPD_SHIFT)) & DDRPHY_ZQ0SR_OPD_MASK) #define DDRPHY_ZQ0SR_OPU_MASK (0xC0U) #define DDRPHY_ZQ0SR_OPU_SHIFT (6U) /*! OPU - On-die termination (ODT) pull-up calibration status */ #define DDRPHY_ZQ0SR_OPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_OPU_SHIFT)) & DDRPHY_ZQ0SR_OPU_MASK) #define DDRPHY_ZQ0SR_ZERR_MASK (0x100U) #define DDRPHY_ZQ0SR_ZERR_SHIFT (8U) /*! ZERR - Impedance Calibration Error */ #define DDRPHY_ZQ0SR_ZERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZERR_SHIFT)) & DDRPHY_ZQ0SR_ZERR_MASK) #define DDRPHY_ZQ0SR_ZDONE_MASK (0x200U) #define DDRPHY_ZQ0SR_ZDONE_SHIFT (9U) /*! ZDONE - Impedance Calibration Done */ #define DDRPHY_ZQ0SR_ZDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZDONE_SHIFT)) & DDRPHY_ZQ0SR_ZDONE_MASK) #define DDRPHY_ZQ0SR_PU_DRV_SAT_MASK (0x400U) #define DDRPHY_ZQ0SR_PU_DRV_SAT_SHIFT (10U) /*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ0SR_PU_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ0SR_PU_DRV_SAT_MASK) #define DDRPHY_ZQ0SR_PD_DRV_SAT_MASK (0x800U) #define DDRPHY_ZQ0SR_PD_DRV_SAT_SHIFT (11U) /*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ0SR_PD_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ0SR_PD_DRV_SAT_MASK) #define DDRPHY_ZQ0SR_PU_ODT_SAT_MASK (0x1000U) #define DDRPHY_ZQ0SR_PU_ODT_SAT_SHIFT (12U) /*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ0SR_PU_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ0SR_PU_ODT_SAT_MASK) #define DDRPHY_ZQ0SR_PD_ODT_SAT_MASK (0x2000U) #define DDRPHY_ZQ0SR_PD_ODT_SAT_SHIFT (13U) /*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ0SR_PD_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ0SR_PD_ODT_SAT_MASK) #define DDRPHY_ZQ0SR_RESERVED_31_14_MASK (0xFFFFC000U) #define DDRPHY_ZQ0SR_RESERVED_31_14_SHIFT (14U) /*! RESERVED_31_14 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ0SR_RESERVED_31_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ0SR_RESERVED_31_14_MASK) /*! @} */ /*! @name ZQ1PR0 - ZQ n Impedance Control Program Register 0 */ /*! @{ */ #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK (0xFU) #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT (0U) /*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) */ #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK) #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK (0xF0U) #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT (4U) /*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) */ #define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK) #define DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_MASK (0xF00U) #define DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT (8U) /*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio */ #define DDRPHY_ZQ1PR0_ZPROG_HOST_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_MASK) #define DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK (0xF000U) #define DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT (12U) /*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio */ #define DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK) #define DDRPHY_ZQ1PR0_PU_DRV_ADJUST_MASK (0x70000U) #define DDRPHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT (16U) /*! PU_DRV_ADJUST - Pullup drive strength adjustment */ #define DDRPHY_ZQ1PR0_PU_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ1PR0_PU_DRV_ADJUST_MASK) #define DDRPHY_ZQ1PR0_PD_DRV_ADJUST_MASK (0x380000U) #define DDRPHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT (19U) /*! PD_DRV_ADJUST - Pulldown drive strength adjustment */ #define DDRPHY_ZQ1PR0_PD_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ1PR0_PD_DRV_ADJUST_MASK) #define DDRPHY_ZQ1PR0_ODT_ADJUST_MASK (0x1C00000U) #define DDRPHY_ZQ1PR0_ODT_ADJUST_SHIFT (22U) /*! ODT_ADJUST - Termination adjustment */ #define DDRPHY_ZQ1PR0_ODT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ1PR0_ODT_ADJUST_MASK) #define DDRPHY_ZQ1PR0_ZLE_MODE_MASK (0x6000000U) #define DDRPHY_ZQ1PR0_ZLE_MODE_SHIFT (25U) /*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB */ #define DDRPHY_ZQ1PR0_ZLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ1PR0_ZLE_MODE_MASK) #define DDRPHY_ZQ1PR0_ZSEGBYP_MASK (0x8000000U) #define DDRPHY_ZQ1PR0_ZSEGBYP_SHIFT (27U) /*! ZSEGBYP - Calibration segment bypass */ #define DDRPHY_ZQ1PR0_ZSEGBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ1PR0_ZSEGBYP_MASK) #define DDRPHY_ZQ1PR0_PU_ODT_ZDEN_MASK (0x10000000U) #define DDRPHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT (28U) /*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable */ #define DDRPHY_ZQ1PR0_PU_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PU_ODT_ZDEN_MASK) #define DDRPHY_ZQ1PR0_PD_ODT_ZDEN_MASK (0x20000000U) #define DDRPHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT (29U) /*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable */ #define DDRPHY_ZQ1PR0_PD_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PD_ODT_ZDEN_MASK) #define DDRPHY_ZQ1PR0_PU_DRV_ZDEN_MASK (0x40000000U) #define DDRPHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT (30U) /*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable */ #define DDRPHY_ZQ1PR0_PU_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PU_DRV_ZDEN_MASK) #define DDRPHY_ZQ1PR0_PD_DRV_ZDEN_MASK (0x80000000U) #define DDRPHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT (31U) /*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable */ #define DDRPHY_ZQ1PR0_PD_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PD_DRV_ZDEN_MASK) /*! @} */ /*! @name ZQ1PR1 - ZQ n Impedance Control Program Register 1 */ /*! @{ */ #define DDRPHY_ZQ1PR1_PD_REFSEL_MASK (0x7FU) #define DDRPHY_ZQ1PR1_PD_REFSEL_SHIFT (0U) /*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell */ #define DDRPHY_ZQ1PR1_PD_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ1PR1_PD_REFSEL_MASK) #define DDRPHY_ZQ1PR1_RESERVED_7_MASK (0x80U) #define DDRPHY_ZQ1PR1_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1PR1_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ1PR1_RESERVED_7_MASK) #define DDRPHY_ZQ1PR1_PU_REFSEL_MASK (0x7F00U) #define DDRPHY_ZQ1PR1_PU_REFSEL_SHIFT (8U) /*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell */ #define DDRPHY_ZQ1PR1_PU_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ1PR1_PU_REFSEL_MASK) #define DDRPHY_ZQ1PR1_RESERVED_31_15_MASK (0xFFFF8000U) #define DDRPHY_ZQ1PR1_RESERVED_31_15_SHIFT (15U) /*! RESERVED_31_15 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1PR1_RESERVED_31_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ1PR1_RESERVED_31_15_MASK) /*! @} */ /*! @name ZQ1DR0 - ZQ n Impedance Control Data Register 0 */ /*! @{ */ #define DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_MASK (0x3FFU) #define DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_SHIFT (0U) /*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result */ #define DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_MASK) #define DDRPHY_ZQ1DR0_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ1DR0_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1DR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1DR0_RESERVED_15_10_MASK) #define DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_MASK (0x3FF0000U) #define DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_SHIFT (16U) /*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result */ #define DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_MASK) #define DDRPHY_ZQ1DR0_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ1DR0_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1DR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1DR0_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ1DR1 - ZQ n Impedance Control Data Register 1 */ /*! @{ */ #define DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_MASK (0x3FFU) #define DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_SHIFT (0U) /*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result */ #define DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_MASK) #define DDRPHY_ZQ1DR1_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ1DR1_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1DR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1DR1_RESERVED_15_10_MASK) #define DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_MASK (0x3FF0000U) #define DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_SHIFT (16U) /*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result */ #define DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_MASK) #define DDRPHY_ZQ1DR1_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ1DR1_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1DR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1DR1_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ1OR0 - ZQ n Impedance Control Override Data Register 0 */ /*! @{ */ #define DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_MASK (0x3FFU) #define DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_SHIFT (0U) /*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance */ #define DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_MASK) #define DDRPHY_ZQ1OR0_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ1OR0_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1OR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1OR0_RESERVED_15_10_MASK) #define DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_MASK (0x3FF0000U) #define DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_SHIFT (16U) /*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance */ #define DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_MASK) #define DDRPHY_ZQ1OR0_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ1OR0_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1OR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1OR0_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ1OR1 - ZQ n Impedance Control Override Data Register 1 */ /*! @{ */ #define DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_MASK (0x3FFU) #define DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_SHIFT (0U) /*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination */ #define DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_MASK) #define DDRPHY_ZQ1OR1_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ1OR1_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1OR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1OR1_RESERVED_15_10_MASK) #define DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_MASK (0x3FF0000U) #define DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_SHIFT (16U) /*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination */ #define DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_MASK) #define DDRPHY_ZQ1OR1_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ1OR1_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1OR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1OR1_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ1SR - ZQ n Impedance Control Status Register */ /*! @{ */ #define DDRPHY_ZQ1SR_ZPD_MASK (0x3U) #define DDRPHY_ZQ1SR_ZPD_SHIFT (0U) /*! ZPD - Output impedance pull-down calibration status */ #define DDRPHY_ZQ1SR_ZPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZPD_SHIFT)) & DDRPHY_ZQ1SR_ZPD_MASK) #define DDRPHY_ZQ1SR_ZPU_MASK (0xCU) #define DDRPHY_ZQ1SR_ZPU_SHIFT (2U) /*! ZPU - Output impedance pull-up calibration status */ #define DDRPHY_ZQ1SR_ZPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZPU_SHIFT)) & DDRPHY_ZQ1SR_ZPU_MASK) #define DDRPHY_ZQ1SR_OPD_MASK (0x30U) #define DDRPHY_ZQ1SR_OPD_SHIFT (4U) /*! OPD - On-die termination (ODT) pull-down calibration status */ #define DDRPHY_ZQ1SR_OPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_OPD_SHIFT)) & DDRPHY_ZQ1SR_OPD_MASK) #define DDRPHY_ZQ1SR_OPU_MASK (0xC0U) #define DDRPHY_ZQ1SR_OPU_SHIFT (6U) /*! OPU - On-die termination (ODT) pull-up calibration status */ #define DDRPHY_ZQ1SR_OPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_OPU_SHIFT)) & DDRPHY_ZQ1SR_OPU_MASK) #define DDRPHY_ZQ1SR_ZERR_MASK (0x100U) #define DDRPHY_ZQ1SR_ZERR_SHIFT (8U) /*! ZERR - Impedance Calibration Error */ #define DDRPHY_ZQ1SR_ZERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZERR_SHIFT)) & DDRPHY_ZQ1SR_ZERR_MASK) #define DDRPHY_ZQ1SR_ZDONE_MASK (0x200U) #define DDRPHY_ZQ1SR_ZDONE_SHIFT (9U) /*! ZDONE - Impedance Calibration Done */ #define DDRPHY_ZQ1SR_ZDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZDONE_SHIFT)) & DDRPHY_ZQ1SR_ZDONE_MASK) #define DDRPHY_ZQ1SR_PU_DRV_SAT_MASK (0x400U) #define DDRPHY_ZQ1SR_PU_DRV_SAT_SHIFT (10U) /*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ1SR_PU_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ1SR_PU_DRV_SAT_MASK) #define DDRPHY_ZQ1SR_PD_DRV_SAT_MASK (0x800U) #define DDRPHY_ZQ1SR_PD_DRV_SAT_SHIFT (11U) /*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ1SR_PD_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ1SR_PD_DRV_SAT_MASK) #define DDRPHY_ZQ1SR_PU_ODT_SAT_MASK (0x1000U) #define DDRPHY_ZQ1SR_PU_ODT_SAT_SHIFT (12U) /*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ1SR_PU_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ1SR_PU_ODT_SAT_MASK) #define DDRPHY_ZQ1SR_PD_ODT_SAT_MASK (0x2000U) #define DDRPHY_ZQ1SR_PD_ODT_SAT_SHIFT (13U) /*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ1SR_PD_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ1SR_PD_ODT_SAT_MASK) #define DDRPHY_ZQ1SR_RESERVED_31_14_MASK (0xFFFFC000U) #define DDRPHY_ZQ1SR_RESERVED_31_14_SHIFT (14U) /*! RESERVED_31_14 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ1SR_RESERVED_31_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ1SR_RESERVED_31_14_MASK) /*! @} */ /*! @name ZQ2PR0 - ZQ n Impedance Control Program Register 0 */ /*! @{ */ #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_MASK (0xFU) #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_SHIFT (0U) /*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) */ #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_MASK) #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_MASK (0xF0U) #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_SHIFT (4U) /*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) */ #define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_MASK) #define DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_MASK (0xF00U) #define DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_SHIFT (8U) /*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio */ #define DDRPHY_ZQ2PR0_ZPROG_HOST_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_MASK) #define DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_MASK (0xF000U) #define DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_SHIFT (12U) /*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio */ #define DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_MASK) #define DDRPHY_ZQ2PR0_PU_DRV_ADJUST_MASK (0x70000U) #define DDRPHY_ZQ2PR0_PU_DRV_ADJUST_SHIFT (16U) /*! PU_DRV_ADJUST - Pullup drive strength adjustment */ #define DDRPHY_ZQ2PR0_PU_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ2PR0_PU_DRV_ADJUST_MASK) #define DDRPHY_ZQ2PR0_PD_DRV_ADJUST_MASK (0x380000U) #define DDRPHY_ZQ2PR0_PD_DRV_ADJUST_SHIFT (19U) /*! PD_DRV_ADJUST - Pulldown drive strength adjustment */ #define DDRPHY_ZQ2PR0_PD_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ2PR0_PD_DRV_ADJUST_MASK) #define DDRPHY_ZQ2PR0_ODT_ADJUST_MASK (0x1C00000U) #define DDRPHY_ZQ2PR0_ODT_ADJUST_SHIFT (22U) /*! ODT_ADJUST - Termination adjustment */ #define DDRPHY_ZQ2PR0_ODT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ2PR0_ODT_ADJUST_MASK) #define DDRPHY_ZQ2PR0_ZLE_MODE_MASK (0x6000000U) #define DDRPHY_ZQ2PR0_ZLE_MODE_SHIFT (25U) /*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB */ #define DDRPHY_ZQ2PR0_ZLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ2PR0_ZLE_MODE_MASK) #define DDRPHY_ZQ2PR0_ZSEGBYP_MASK (0x8000000U) #define DDRPHY_ZQ2PR0_ZSEGBYP_SHIFT (27U) /*! ZSEGBYP - Calibration segment bypass */ #define DDRPHY_ZQ2PR0_ZSEGBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ2PR0_ZSEGBYP_MASK) #define DDRPHY_ZQ2PR0_PU_ODT_ZDEN_MASK (0x10000000U) #define DDRPHY_ZQ2PR0_PU_ODT_ZDEN_SHIFT (28U) /*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable */ #define DDRPHY_ZQ2PR0_PU_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PU_ODT_ZDEN_MASK) #define DDRPHY_ZQ2PR0_PD_ODT_ZDEN_MASK (0x20000000U) #define DDRPHY_ZQ2PR0_PD_ODT_ZDEN_SHIFT (29U) /*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable */ #define DDRPHY_ZQ2PR0_PD_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PD_ODT_ZDEN_MASK) #define DDRPHY_ZQ2PR0_PU_DRV_ZDEN_MASK (0x40000000U) #define DDRPHY_ZQ2PR0_PU_DRV_ZDEN_SHIFT (30U) /*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable */ #define DDRPHY_ZQ2PR0_PU_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PU_DRV_ZDEN_MASK) #define DDRPHY_ZQ2PR0_PD_DRV_ZDEN_MASK (0x80000000U) #define DDRPHY_ZQ2PR0_PD_DRV_ZDEN_SHIFT (31U) /*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable */ #define DDRPHY_ZQ2PR0_PD_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PD_DRV_ZDEN_MASK) /*! @} */ /*! @name ZQ2PR1 - ZQ n Impedance Control Program Register 1 */ /*! @{ */ #define DDRPHY_ZQ2PR1_PD_REFSEL_MASK (0x7FU) #define DDRPHY_ZQ2PR1_PD_REFSEL_SHIFT (0U) /*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell */ #define DDRPHY_ZQ2PR1_PD_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ2PR1_PD_REFSEL_MASK) #define DDRPHY_ZQ2PR1_RESERVED_7_MASK (0x80U) #define DDRPHY_ZQ2PR1_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2PR1_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ2PR1_RESERVED_7_MASK) #define DDRPHY_ZQ2PR1_PU_REFSEL_MASK (0x7F00U) #define DDRPHY_ZQ2PR1_PU_REFSEL_SHIFT (8U) /*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell */ #define DDRPHY_ZQ2PR1_PU_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ2PR1_PU_REFSEL_MASK) #define DDRPHY_ZQ2PR1_RESERVED_31_15_MASK (0xFFFF8000U) #define DDRPHY_ZQ2PR1_RESERVED_31_15_SHIFT (15U) /*! RESERVED_31_15 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2PR1_RESERVED_31_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ2PR1_RESERVED_31_15_MASK) /*! @} */ /*! @name ZQ2DR0 - ZQ n Impedance Control Data Register 0 */ /*! @{ */ #define DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_MASK (0x3FFU) #define DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_SHIFT (0U) /*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result */ #define DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_MASK) #define DDRPHY_ZQ2DR0_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ2DR0_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2DR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2DR0_RESERVED_15_10_MASK) #define DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_MASK (0x3FF0000U) #define DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_SHIFT (16U) /*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result */ #define DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_MASK) #define DDRPHY_ZQ2DR0_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ2DR0_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2DR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2DR0_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ2DR1 - ZQ n Impedance Control Data Register 1 */ /*! @{ */ #define DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_MASK (0x3FFU) #define DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_SHIFT (0U) /*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result */ #define DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_MASK) #define DDRPHY_ZQ2DR1_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ2DR1_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2DR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2DR1_RESERVED_15_10_MASK) #define DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_MASK (0x3FF0000U) #define DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_SHIFT (16U) /*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result */ #define DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_MASK) #define DDRPHY_ZQ2DR1_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ2DR1_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2DR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2DR1_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ2OR0 - ZQ n Impedance Control Override Data Register 0 */ /*! @{ */ #define DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_MASK (0x3FFU) #define DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_SHIFT (0U) /*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance */ #define DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_MASK) #define DDRPHY_ZQ2OR0_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ2OR0_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2OR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2OR0_RESERVED_15_10_MASK) #define DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_MASK (0x3FF0000U) #define DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_SHIFT (16U) /*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance */ #define DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_MASK) #define DDRPHY_ZQ2OR0_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ2OR0_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2OR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2OR0_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ2OR1 - ZQ n Impedance Control Override Data Register 1 */ /*! @{ */ #define DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_MASK (0x3FFU) #define DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_SHIFT (0U) /*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination */ #define DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_MASK) #define DDRPHY_ZQ2OR1_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ2OR1_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2OR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2OR1_RESERVED_15_10_MASK) #define DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_MASK (0x3FF0000U) #define DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_SHIFT (16U) /*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination */ #define DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_MASK) #define DDRPHY_ZQ2OR1_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ2OR1_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2OR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2OR1_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ2SR - ZQ n Impedance Control Status Register */ /*! @{ */ #define DDRPHY_ZQ2SR_ZPD_MASK (0x3U) #define DDRPHY_ZQ2SR_ZPD_SHIFT (0U) /*! ZPD - Output impedance pull-down calibration status */ #define DDRPHY_ZQ2SR_ZPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZPD_SHIFT)) & DDRPHY_ZQ2SR_ZPD_MASK) #define DDRPHY_ZQ2SR_ZPU_MASK (0xCU) #define DDRPHY_ZQ2SR_ZPU_SHIFT (2U) /*! ZPU - Output impedance pull-up calibration status */ #define DDRPHY_ZQ2SR_ZPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZPU_SHIFT)) & DDRPHY_ZQ2SR_ZPU_MASK) #define DDRPHY_ZQ2SR_OPD_MASK (0x30U) #define DDRPHY_ZQ2SR_OPD_SHIFT (4U) /*! OPD - On-die termination (ODT) pull-down calibration status */ #define DDRPHY_ZQ2SR_OPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_OPD_SHIFT)) & DDRPHY_ZQ2SR_OPD_MASK) #define DDRPHY_ZQ2SR_OPU_MASK (0xC0U) #define DDRPHY_ZQ2SR_OPU_SHIFT (6U) /*! OPU - On-die termination (ODT) pull-up calibration status */ #define DDRPHY_ZQ2SR_OPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_OPU_SHIFT)) & DDRPHY_ZQ2SR_OPU_MASK) #define DDRPHY_ZQ2SR_ZERR_MASK (0x100U) #define DDRPHY_ZQ2SR_ZERR_SHIFT (8U) /*! ZERR - Impedance Calibration Error */ #define DDRPHY_ZQ2SR_ZERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZERR_SHIFT)) & DDRPHY_ZQ2SR_ZERR_MASK) #define DDRPHY_ZQ2SR_ZDONE_MASK (0x200U) #define DDRPHY_ZQ2SR_ZDONE_SHIFT (9U) /*! ZDONE - Impedance Calibration Done */ #define DDRPHY_ZQ2SR_ZDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZDONE_SHIFT)) & DDRPHY_ZQ2SR_ZDONE_MASK) #define DDRPHY_ZQ2SR_PU_DRV_SAT_MASK (0x400U) #define DDRPHY_ZQ2SR_PU_DRV_SAT_SHIFT (10U) /*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ2SR_PU_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ2SR_PU_DRV_SAT_MASK) #define DDRPHY_ZQ2SR_PD_DRV_SAT_MASK (0x800U) #define DDRPHY_ZQ2SR_PD_DRV_SAT_SHIFT (11U) /*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ2SR_PD_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ2SR_PD_DRV_SAT_MASK) #define DDRPHY_ZQ2SR_PU_ODT_SAT_MASK (0x1000U) #define DDRPHY_ZQ2SR_PU_ODT_SAT_SHIFT (12U) /*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ2SR_PU_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ2SR_PU_ODT_SAT_MASK) #define DDRPHY_ZQ2SR_PD_ODT_SAT_MASK (0x2000U) #define DDRPHY_ZQ2SR_PD_ODT_SAT_SHIFT (13U) /*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ2SR_PD_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ2SR_PD_ODT_SAT_MASK) #define DDRPHY_ZQ2SR_RESERVED_31_14_MASK (0xFFFFC000U) #define DDRPHY_ZQ2SR_RESERVED_31_14_SHIFT (14U) /*! RESERVED_31_14 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ2SR_RESERVED_31_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ2SR_RESERVED_31_14_MASK) /*! @} */ /*! @name ZQ3PR0 - ZQ n Impedance Control Program Register 0 */ /*! @{ */ #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_MASK (0xFU) #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_SHIFT (0U) /*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) */ #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_MASK) #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_MASK (0xF0U) #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_SHIFT (4U) /*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) */ #define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_MASK) #define DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_MASK (0xF00U) #define DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_SHIFT (8U) /*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio */ #define DDRPHY_ZQ3PR0_ZPROG_HOST_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_MASK) #define DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_MASK (0xF000U) #define DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_SHIFT (12U) /*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio */ #define DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_MASK) #define DDRPHY_ZQ3PR0_PU_DRV_ADJUST_MASK (0x70000U) #define DDRPHY_ZQ3PR0_PU_DRV_ADJUST_SHIFT (16U) /*! PU_DRV_ADJUST - Pullup drive strength adjustment */ #define DDRPHY_ZQ3PR0_PU_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ3PR0_PU_DRV_ADJUST_MASK) #define DDRPHY_ZQ3PR0_PD_DRV_ADJUST_MASK (0x380000U) #define DDRPHY_ZQ3PR0_PD_DRV_ADJUST_SHIFT (19U) /*! PD_DRV_ADJUST - Pulldown drive strength adjustment */ #define DDRPHY_ZQ3PR0_PD_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ3PR0_PD_DRV_ADJUST_MASK) #define DDRPHY_ZQ3PR0_ODT_ADJUST_MASK (0x1C00000U) #define DDRPHY_ZQ3PR0_ODT_ADJUST_SHIFT (22U) /*! ODT_ADJUST - Termination adjustment */ #define DDRPHY_ZQ3PR0_ODT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ3PR0_ODT_ADJUST_MASK) #define DDRPHY_ZQ3PR0_ZLE_MODE_MASK (0x6000000U) #define DDRPHY_ZQ3PR0_ZLE_MODE_SHIFT (25U) /*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB */ #define DDRPHY_ZQ3PR0_ZLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ3PR0_ZLE_MODE_MASK) #define DDRPHY_ZQ3PR0_ZSEGBYP_MASK (0x8000000U) #define DDRPHY_ZQ3PR0_ZSEGBYP_SHIFT (27U) /*! ZSEGBYP - Calibration segment bypass */ #define DDRPHY_ZQ3PR0_ZSEGBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ3PR0_ZSEGBYP_MASK) #define DDRPHY_ZQ3PR0_PU_ODT_ZDEN_MASK (0x10000000U) #define DDRPHY_ZQ3PR0_PU_ODT_ZDEN_SHIFT (28U) /*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable */ #define DDRPHY_ZQ3PR0_PU_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PU_ODT_ZDEN_MASK) #define DDRPHY_ZQ3PR0_PD_ODT_ZDEN_MASK (0x20000000U) #define DDRPHY_ZQ3PR0_PD_ODT_ZDEN_SHIFT (29U) /*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable */ #define DDRPHY_ZQ3PR0_PD_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PD_ODT_ZDEN_MASK) #define DDRPHY_ZQ3PR0_PU_DRV_ZDEN_MASK (0x40000000U) #define DDRPHY_ZQ3PR0_PU_DRV_ZDEN_SHIFT (30U) /*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable */ #define DDRPHY_ZQ3PR0_PU_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PU_DRV_ZDEN_MASK) #define DDRPHY_ZQ3PR0_PD_DRV_ZDEN_MASK (0x80000000U) #define DDRPHY_ZQ3PR0_PD_DRV_ZDEN_SHIFT (31U) /*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable */ #define DDRPHY_ZQ3PR0_PD_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PD_DRV_ZDEN_MASK) /*! @} */ /*! @name ZQ3PR1 - ZQ n Impedance Control Program Register 1 */ /*! @{ */ #define DDRPHY_ZQ3PR1_PD_REFSEL_MASK (0x7FU) #define DDRPHY_ZQ3PR1_PD_REFSEL_SHIFT (0U) /*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell */ #define DDRPHY_ZQ3PR1_PD_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ3PR1_PD_REFSEL_MASK) #define DDRPHY_ZQ3PR1_RESERVED_7_MASK (0x80U) #define DDRPHY_ZQ3PR1_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3PR1_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ3PR1_RESERVED_7_MASK) #define DDRPHY_ZQ3PR1_PU_REFSEL_MASK (0x7F00U) #define DDRPHY_ZQ3PR1_PU_REFSEL_SHIFT (8U) /*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell */ #define DDRPHY_ZQ3PR1_PU_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ3PR1_PU_REFSEL_MASK) #define DDRPHY_ZQ3PR1_RESERVED_31_15_MASK (0xFFFF8000U) #define DDRPHY_ZQ3PR1_RESERVED_31_15_SHIFT (15U) /*! RESERVED_31_15 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3PR1_RESERVED_31_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ3PR1_RESERVED_31_15_MASK) /*! @} */ /*! @name ZQ3DR0 - ZQ n Impedance Control Data Register 0 */ /*! @{ */ #define DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_MASK (0x3FFU) #define DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_SHIFT (0U) /*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result */ #define DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_MASK) #define DDRPHY_ZQ3DR0_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ3DR0_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3DR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3DR0_RESERVED_15_10_MASK) #define DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_MASK (0x3FF0000U) #define DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_SHIFT (16U) /*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result */ #define DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_MASK) #define DDRPHY_ZQ3DR0_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ3DR0_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3DR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3DR0_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ3DR1 - ZQ n Impedance Control Data Register 1 */ /*! @{ */ #define DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_MASK (0x3FFU) #define DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_SHIFT (0U) /*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result */ #define DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_MASK) #define DDRPHY_ZQ3DR1_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ3DR1_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3DR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3DR1_RESERVED_15_10_MASK) #define DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_MASK (0x3FF0000U) #define DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_SHIFT (16U) /*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result */ #define DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_MASK) #define DDRPHY_ZQ3DR1_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ3DR1_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3DR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3DR1_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ3OR0 - ZQ n Impedance Control Override Data Register 0 */ /*! @{ */ #define DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_MASK (0x3FFU) #define DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_SHIFT (0U) /*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance */ #define DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_MASK) #define DDRPHY_ZQ3OR0_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ3OR0_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3OR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3OR0_RESERVED_15_10_MASK) #define DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_MASK (0x3FF0000U) #define DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_SHIFT (16U) /*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance */ #define DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_MASK) #define DDRPHY_ZQ3OR0_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ3OR0_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3OR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3OR0_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ3OR1 - ZQ n Impedance Control Override Data Register 1 */ /*! @{ */ #define DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_MASK (0x3FFU) #define DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_SHIFT (0U) /*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination */ #define DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_MASK) #define DDRPHY_ZQ3OR1_RESERVED_15_10_MASK (0xFC00U) #define DDRPHY_ZQ3OR1_RESERVED_15_10_SHIFT (10U) /*! RESERVED_15_10 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3OR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3OR1_RESERVED_15_10_MASK) #define DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_MASK (0x3FF0000U) #define DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_SHIFT (16U) /*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination */ #define DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_MASK) #define DDRPHY_ZQ3OR1_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_ZQ3OR1_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3OR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3OR1_RESERVED_31_26_MASK) /*! @} */ /*! @name ZQ3SR - ZQ n Impedance Control Status Register */ /*! @{ */ #define DDRPHY_ZQ3SR_ZPD_MASK (0x3U) #define DDRPHY_ZQ3SR_ZPD_SHIFT (0U) /*! ZPD - Output impedance pull-down calibration status */ #define DDRPHY_ZQ3SR_ZPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZPD_SHIFT)) & DDRPHY_ZQ3SR_ZPD_MASK) #define DDRPHY_ZQ3SR_ZPU_MASK (0xCU) #define DDRPHY_ZQ3SR_ZPU_SHIFT (2U) /*! ZPU - Output impedance pull-up calibration status */ #define DDRPHY_ZQ3SR_ZPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZPU_SHIFT)) & DDRPHY_ZQ3SR_ZPU_MASK) #define DDRPHY_ZQ3SR_OPD_MASK (0x30U) #define DDRPHY_ZQ3SR_OPD_SHIFT (4U) /*! OPD - On-die termination (ODT) pull-down calibration status */ #define DDRPHY_ZQ3SR_OPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_OPD_SHIFT)) & DDRPHY_ZQ3SR_OPD_MASK) #define DDRPHY_ZQ3SR_OPU_MASK (0xC0U) #define DDRPHY_ZQ3SR_OPU_SHIFT (6U) /*! OPU - On-die termination (ODT) pull-up calibration status */ #define DDRPHY_ZQ3SR_OPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_OPU_SHIFT)) & DDRPHY_ZQ3SR_OPU_MASK) #define DDRPHY_ZQ3SR_ZERR_MASK (0x100U) #define DDRPHY_ZQ3SR_ZERR_SHIFT (8U) /*! ZERR - Impedance Calibration Error */ #define DDRPHY_ZQ3SR_ZERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZERR_SHIFT)) & DDRPHY_ZQ3SR_ZERR_MASK) #define DDRPHY_ZQ3SR_ZDONE_MASK (0x200U) #define DDRPHY_ZQ3SR_ZDONE_SHIFT (9U) /*! ZDONE - Impedance Calibration Done */ #define DDRPHY_ZQ3SR_ZDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZDONE_SHIFT)) & DDRPHY_ZQ3SR_ZDONE_MASK) #define DDRPHY_ZQ3SR_PU_DRV_SAT_MASK (0x400U) #define DDRPHY_ZQ3SR_PU_DRV_SAT_SHIFT (10U) /*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ3SR_PU_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ3SR_PU_DRV_SAT_MASK) #define DDRPHY_ZQ3SR_PD_DRV_SAT_MASK (0x800U) #define DDRPHY_ZQ3SR_PD_DRV_SAT_SHIFT (11U) /*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ3SR_PD_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ3SR_PD_DRV_SAT_MASK) #define DDRPHY_ZQ3SR_PU_ODT_SAT_MASK (0x1000U) #define DDRPHY_ZQ3SR_PU_ODT_SAT_SHIFT (12U) /*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ3SR_PU_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ3SR_PU_ODT_SAT_MASK) #define DDRPHY_ZQ3SR_PD_ODT_SAT_MASK (0x2000U) #define DDRPHY_ZQ3SR_PD_ODT_SAT_SHIFT (13U) /*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register */ #define DDRPHY_ZQ3SR_PD_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ3SR_PD_ODT_SAT_MASK) #define DDRPHY_ZQ3SR_RESERVED_31_14_MASK (0xFFFFC000U) #define DDRPHY_ZQ3SR_RESERVED_31_14_SHIFT (14U) /*! RESERVED_31_14 - Reserved. Return zeros on reads. */ #define DDRPHY_ZQ3SR_RESERVED_31_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ3SR_RESERVED_31_14_MASK) /*! @} */ /*! @name DX0GCR0 - DATX8 n General Configuration Register 0 */ /*! @{ */ #define DDRPHY_DX0GCR0_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX0GCR0_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX0GCR0_RESERVED_1_0_MASK) #define DDRPHY_DX0GCR0_DQSGOE_MASK (0x4U) #define DDRPHY_DX0GCR0_DQSGOE_SHIFT (2U) /*! DQSGOE - DQSG Output Enable */ #define DDRPHY_DX0GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSGOE_SHIFT)) & DDRPHY_DX0GCR0_DQSGOE_MASK) #define DDRPHY_DX0GCR0_DQSGODT_MASK (0x8U) #define DDRPHY_DX0GCR0_DQSGODT_SHIFT (3U) /*! DQSGODT - DQSG On-Die Termination */ #define DDRPHY_DX0GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSGODT_SHIFT)) & DDRPHY_DX0GCR0_DQSGODT_MASK) #define DDRPHY_DX0GCR0_RESERVED_4_MASK (0x10U) #define DDRPHY_DX0GCR0_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX0GCR0_RESERVED_4_MASK) #define DDRPHY_DX0GCR0_DQSGPDR_MASK (0x20U) #define DDRPHY_DX0GCR0_DQSGPDR_SHIFT (5U) /*! DQSGPDR - DQSG Power Down Receiver */ #define DDRPHY_DX0GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX0GCR0_DQSGPDR_MASK) #define DDRPHY_DX0GCR0_DQSRPD_MASK (0x40U) #define DDRPHY_DX0GCR0_DQSRPD_SHIFT (6U) /*! DQSRPD - DQSR Power Down */ #define DDRPHY_DX0GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSRPD_SHIFT)) & DDRPHY_DX0GCR0_DQSRPD_MASK) #define DDRPHY_DX0GCR0_CPDRSHFT_MASK (0x180U) #define DDRPHY_DX0GCR0_CPDRSHFT_SHIFT (7U) /*! CPDRSHFT - Configurable PDR Phase Shift */ #define DDRPHY_DX0GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX0GCR0_CPDRSHFT_MASK) #define DDRPHY_DX0GCR0_RTTOH_MASK (0x600U) #define DDRPHY_DX0GCR0_RTTOH_SHIFT (9U) /*! RTTOH - RTT Output Hold */ #define DDRPHY_DX0GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RTTOH_SHIFT)) & DDRPHY_DX0GCR0_RTTOH_MASK) #define DDRPHY_DX0GCR0_RTTOAL_MASK (0x800U) #define DDRPHY_DX0GCR0_RTTOAL_SHIFT (11U) /*! RTTOAL - RTT On Additive Latency */ #define DDRPHY_DX0GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RTTOAL_SHIFT)) & DDRPHY_DX0GCR0_RTTOAL_MASK) #define DDRPHY_DX0GCR0_DQSSEPDR_MASK (0x1000U) #define DDRPHY_DX0GCR0_DQSSEPDR_SHIFT (12U) /*! DQSSEPDR - DQSSE Power Down Receiver */ #define DDRPHY_DX0GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX0GCR0_DQSSEPDR_MASK) #define DDRPHY_DX0GCR0_DQSNSEPDR_MASK (0x2000U) #define DDRPHY_DX0GCR0_DQSNSEPDR_SHIFT (13U) /*! DQSNSEPDR - DQSNSE Power Down Receiver */ #define DDRPHY_DX0GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX0GCR0_DQSNSEPDR_MASK) #define DDRPHY_DX0GCR0_RESERVED_19_14_MASK (0xFC000U) #define DDRPHY_DX0GCR0_RESERVED_19_14_SHIFT (14U) /*! RESERVED_19_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX0GCR0_RESERVED_19_14_MASK) #define DDRPHY_DX0GCR0_RDDLY_MASK (0xF00000U) #define DDRPHY_DX0GCR0_RDDLY_SHIFT (20U) /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY */ #define DDRPHY_DX0GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RDDLY_SHIFT)) & DDRPHY_DX0GCR0_RDDLY_MASK) #define DDRPHY_DX0GCR0_DQSDCC_MASK (0xF000000U) #define DDRPHY_DX0GCR0_DQSDCC_SHIFT (24U) /*! DQSDCC - DQS Duty Cycle Correction */ #define DDRPHY_DX0GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSDCC_SHIFT)) & DDRPHY_DX0GCR0_DQSDCC_MASK) #define DDRPHY_DX0GCR0_CODTSHFT_MASK (0x30000000U) #define DDRPHY_DX0GCR0_CODTSHFT_SHIFT (28U) /*! CODTSHFT - Configurable ODT(TE) Phase Shift */ #define DDRPHY_DX0GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX0GCR0_CODTSHFT_MASK) #define DDRPHY_DX0GCR0_MDLEN_MASK (0x40000000U) #define DDRPHY_DX0GCR0_MDLEN_SHIFT (30U) /*! MDLEN - Master Delay Line Enable */ #define DDRPHY_DX0GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_MDLEN_SHIFT)) & DDRPHY_DX0GCR0_MDLEN_MASK) #define DDRPHY_DX0GCR0_CALBYP_MASK (0x80000000U) #define DDRPHY_DX0GCR0_CALBYP_SHIFT (31U) /*! CALBYP - Calibration Bypass */ #define DDRPHY_DX0GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_CALBYP_SHIFT)) & DDRPHY_DX0GCR0_CALBYP_MASK) /*! @} */ /*! @name DX0GCR1 - DATX8 n General Configuration Register 1 */ /*! @{ */ #define DDRPHY_DX0GCR1_DQEN_MASK (0xFFU) #define DDRPHY_DX0GCR1_DQEN_SHIFT (0U) /*! DQEN - Enables DQ corresponding to each bit in a byte */ #define DDRPHY_DX0GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DQEN_SHIFT)) & DDRPHY_DX0GCR1_DQEN_MASK) #define DDRPHY_DX0GCR1_DMEN_MASK (0x100U) #define DDRPHY_DX0GCR1_DMEN_SHIFT (8U) /*! DMEN - Enables DM pin in a byte lane */ #define DDRPHY_DX0GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DMEN_SHIFT)) & DDRPHY_DX0GCR1_DMEN_MASK) #define DDRPHY_DX0GCR1_DSEN_MASK (0x200U) #define DDRPHY_DX0GCR1_DSEN_SHIFT (9U) /*! DSEN - Enables Write Data strobe in a byte lane */ #define DDRPHY_DX0GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DSEN_SHIFT)) & DDRPHY_DX0GCR1_DSEN_MASK) #define DDRPHY_DX0GCR1_TEEN_MASK (0x400U) #define DDRPHY_DX0GCR1_TEEN_SHIFT (10U) /*! TEEN - Enables ODT/TE in a byte lane */ #define DDRPHY_DX0GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_TEEN_SHIFT)) & DDRPHY_DX0GCR1_TEEN_MASK) #define DDRPHY_DX0GCR1_PDREN_MASK (0x800U) #define DDRPHY_DX0GCR1_PDREN_SHIFT (11U) /*! PDREN - Enables PDR in a byte lane */ #define DDRPHY_DX0GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_PDREN_SHIFT)) & DDRPHY_DX0GCR1_PDREN_MASK) #define DDRPHY_DX0GCR1_OEEN_MASK (0x1000U) #define DDRPHY_DX0GCR1_OEEN_SHIFT (12U) /*! OEEN - Enables Read Data Strobe in a byte lane */ #define DDRPHY_DX0GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_OEEN_SHIFT)) & DDRPHY_DX0GCR1_OEEN_MASK) #define DDRPHY_DX0GCR1_QSSEL_MASK (0x2000U) #define DDRPHY_DX0GCR1_QSSEL_SHIFT (13U) /*! QSSEL - Select the delayed or non-delayed read data strobe */ #define DDRPHY_DX0GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_QSSEL_SHIFT)) & DDRPHY_DX0GCR1_QSSEL_MASK) #define DDRPHY_DX0GCR1_QSNSEL_MASK (0x4000U) #define DDRPHY_DX0GCR1_QSNSEL_SHIFT (14U) /*! QSNSEL - Select the delayed or non-delayed read data strobe # */ #define DDRPHY_DX0GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_QSNSEL_SHIFT)) & DDRPHY_DX0GCR1_QSNSEL_MASK) #define DDRPHY_DX0GCR1_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX0GCR1_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX0GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX0GCR1_RESERVED_15_MASK) #define DDRPHY_DX0GCR1_DXPDRMODE_MASK (0xFFFF0000U) #define DDRPHY_DX0GCR1_DXPDRMODE_SHIFT (16U) /*! DXPDRMODE - Enables the PDR mode for DQ[7:0] */ #define DDRPHY_DX0GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX0GCR1_DXPDRMODE_MASK) /*! @} */ /*! @name DX0GCR2 - DATX8 n General Configuration Register 2 */ /*! @{ */ #define DDRPHY_DX0GCR2_DXTEMODE_MASK (0xFFFFU) #define DDRPHY_DX0GCR2_DXTEMODE_SHIFT (0U) /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0] */ #define DDRPHY_DX0GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX0GCR2_DXTEMODE_MASK) #define DDRPHY_DX0GCR2_DXOEMODE_MASK (0xFFFF0000U) #define DDRPHY_DX0GCR2_DXOEMODE_SHIFT (16U) /*! DXOEMODE - Enables the OE mode values for DQ[7:0] */ #define DDRPHY_DX0GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX0GCR2_DXOEMODE_MASK) /*! @} */ /*! @name DX0GCR3 - DATX8 n General Configuration Register 3 */ /*! @{ */ #define DDRPHY_DX0GCR3_WDMBVT_MASK (0x1U) #define DDRPHY_DX0GCR3_WDMBVT_SHIFT (0U) /*! WDMBVT - Write Data Mask BDL VT Compensation */ #define DDRPHY_DX0GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDMBVT_SHIFT)) & DDRPHY_DX0GCR3_WDMBVT_MASK) #define DDRPHY_DX0GCR3_RDMBVT_MASK (0x2U) #define DDRPHY_DX0GCR3_RDMBVT_SHIFT (1U) /*! RDMBVT - Read Data Mask BDL VT Compensation */ #define DDRPHY_DX0GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RDMBVT_SHIFT)) & DDRPHY_DX0GCR3_RDMBVT_MASK) #define DDRPHY_DX0GCR3_DSPDRMODE_MASK (0xCU) #define DDRPHY_DX0GCR3_DSPDRMODE_SHIFT (2U) /*! DSPDRMODE - Enables the PDR mode values for DQS. */ #define DDRPHY_DX0GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX0GCR3_DSPDRMODE_MASK) #define DDRPHY_DX0GCR3_DSTEMODE_MASK (0x30U) #define DDRPHY_DX0GCR3_DSTEMODE_SHIFT (4U) /*! DSTEMODE - Enables the TE mode values for DQS. */ #define DDRPHY_DX0GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSTEMODE_MASK) #define DDRPHY_DX0GCR3_DSOEMODE_MASK (0xC0U) #define DDRPHY_DX0GCR3_DSOEMODE_SHIFT (6U) /*! DSOEMODE - Enables the OE mode values for DQS. */ #define DDRPHY_DX0GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSOEMODE_MASK) #define DDRPHY_DX0GCR3_WDSBVT_MASK (0x100U) #define DDRPHY_DX0GCR3_WDSBVT_SHIFT (8U) /*! WDSBVT - Write Data Strobe BDL VT Compensation */ #define DDRPHY_DX0GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDSBVT_SHIFT)) & DDRPHY_DX0GCR3_WDSBVT_MASK) #define DDRPHY_DX0GCR3_RESERVED_9_MASK (0x200U) #define DDRPHY_DX0GCR3_RESERVED_9_SHIFT (9U) /*! RESERVED_9 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX0GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX0GCR3_RESERVED_9_MASK) #define DDRPHY_DX0GCR3_DMPDRMODE_MASK (0xC00U) #define DDRPHY_DX0GCR3_DMPDRMODE_SHIFT (10U) /*! DMPDRMODE - Enables the PDR mode values for DM. */ #define DDRPHY_DX0GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX0GCR3_DMPDRMODE_MASK) #define DDRPHY_DX0GCR3_DMTEMODE_MASK (0x3000U) #define DDRPHY_DX0GCR3_DMTEMODE_SHIFT (12U) /*! DMTEMODE - Enables the TE mode values for DM. */ #define DDRPHY_DX0GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX0GCR3_DMTEMODE_MASK) #define DDRPHY_DX0GCR3_DMOEMODE_MASK (0xC000U) #define DDRPHY_DX0GCR3_DMOEMODE_SHIFT (14U) /*! DMOEMODE - Enables the OE mode values for DM. */ #define DDRPHY_DX0GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX0GCR3_DMOEMODE_MASK) #define DDRPHY_DX0GCR3_DSNPDRMODE_MASK (0x30000U) #define DDRPHY_DX0GCR3_DSNPDRMODE_SHIFT (16U) /*! DSNPDRMODE - Enables the PDR mode for DQS */ #define DDRPHY_DX0GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX0GCR3_DSNPDRMODE_MASK) #define DDRPHY_DX0GCR3_DSNTEMODE_MASK (0xC0000U) #define DDRPHY_DX0GCR3_DSNTEMODE_SHIFT (18U) /*! DSNTEMODE - Enables the TE mode for DQS */ #define DDRPHY_DX0GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSNTEMODE_MASK) #define DDRPHY_DX0GCR3_DSNOEMODE_MASK (0x300000U) #define DDRPHY_DX0GCR3_DSNOEMODE_SHIFT (20U) /*! DSNOEMODE - Enables the OE mode for DQs */ #define DDRPHY_DX0GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSNOEMODE_MASK) #define DDRPHY_DX0GCR3_PDRBVT_MASK (0x400000U) #define DDRPHY_DX0GCR3_PDRBVT_SHIFT (22U) /*! PDRBVT - Power Down Receiver BDL VT Compensation */ #define DDRPHY_DX0GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_PDRBVT_SHIFT)) & DDRPHY_DX0GCR3_PDRBVT_MASK) #define DDRPHY_DX0GCR3_RGSLVT_MASK (0x800000U) #define DDRPHY_DX0GCR3_RGSLVT_SHIFT (23U) /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation */ #define DDRPHY_DX0GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RGSLVT_SHIFT)) & DDRPHY_DX0GCR3_RGSLVT_MASK) #define DDRPHY_DX0GCR3_WLLVT_MASK (0x1000000U) #define DDRPHY_DX0GCR3_WLLVT_SHIFT (24U) /*! WLLVT - Write Leveling LCDL Delay VT Compensation */ #define DDRPHY_DX0GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WLLVT_SHIFT)) & DDRPHY_DX0GCR3_WLLVT_MASK) #define DDRPHY_DX0GCR3_WDLVT_MASK (0x2000000U) #define DDRPHY_DX0GCR3_WDLVT_SHIFT (25U) /*! WDLVT - Write DQ LCDL Delay VT Compensation */ #define DDRPHY_DX0GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDLVT_SHIFT)) & DDRPHY_DX0GCR3_WDLVT_MASK) #define DDRPHY_DX0GCR3_RDLVT_MASK (0x4000000U) #define DDRPHY_DX0GCR3_RDLVT_SHIFT (26U) /*! RDLVT - Read DQS LCDL Delay VT Compensation */ #define DDRPHY_DX0GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RDLVT_SHIFT)) & DDRPHY_DX0GCR3_RDLVT_MASK) #define DDRPHY_DX0GCR3_RGLVT_MASK (0x8000000U) #define DDRPHY_DX0GCR3_RGLVT_SHIFT (27U) /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation */ #define DDRPHY_DX0GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RGLVT_SHIFT)) & DDRPHY_DX0GCR3_RGLVT_MASK) #define DDRPHY_DX0GCR3_WDBVT_MASK (0x10000000U) #define DDRPHY_DX0GCR3_WDBVT_SHIFT (28U) /*! WDBVT - Write Data BDL VT Compensation */ #define DDRPHY_DX0GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDBVT_SHIFT)) & DDRPHY_DX0GCR3_WDBVT_MASK) #define DDRPHY_DX0GCR3_RDBVT_MASK (0x20000000U) #define DDRPHY_DX0GCR3_RDBVT_SHIFT (29U) /*! RDBVT - Read Data BDL VT Compensation */ #define DDRPHY_DX0GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RDBVT_SHIFT)) & DDRPHY_DX0GCR3_RDBVT_MASK) #define DDRPHY_DX0GCR3_TEBVT_MASK (0x40000000U) #define DDRPHY_DX0GCR3_TEBVT_SHIFT (30U) /*! TEBVT - Termination Enable BDL VT Compensation */ #define DDRPHY_DX0GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_TEBVT_SHIFT)) & DDRPHY_DX0GCR3_TEBVT_MASK) #define DDRPHY_DX0GCR3_OEBVT_MASK (0x80000000U) #define DDRPHY_DX0GCR3_OEBVT_SHIFT (31U) /*! OEBVT - Output Enable BDL VT Compensation */ #define DDRPHY_DX0GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_OEBVT_SHIFT)) & DDRPHY_DX0GCR3_OEBVT_MASK) /*! @} */ /*! @name DX0GCR4 - DATX8 n General Configuration Register 4 */ /*! @{ */ #define DDRPHY_DX0GCR4_DXREFIMON_MASK (0x3U) #define DDRPHY_DX0GCR4_DXREFIMON_SHIFT (0U) /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX0GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX0GCR4_DXREFIMON_MASK) #define DDRPHY_DX0GCR4_DXREFIEN_MASK (0x3CU) #define DDRPHY_DX0GCR4_DXREFIEN_SHIFT (2U) /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX0GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFIEN_MASK) #define DDRPHY_DX0GCR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0GCR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX0GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR4_RESERVED_7_6_MASK) #define DDRPHY_DX0GCR4_DXREFSSEL_MASK (0x7F00U) #define DDRPHY_DX0GCR4_DXREFSSEL_SHIFT (8U) /*! DXREFSSEL - Byte Lane Single-End VREF Select */ #define DDRPHY_DX0GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX0GCR4_DXREFSSEL_MASK) #define DDRPHY_DX0GCR4_DXREFSSELRANGE_MASK (0x8000U) #define DDRPHY_DX0GCR4_DXREFSSELRANGE_SHIFT (15U) /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select */ #define DDRPHY_DX0GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX0GCR4_DXREFSSELRANGE_MASK) #define DDRPHY_DX0GCR4_DXREFESEL_MASK (0x7F0000U) #define DDRPHY_DX0GCR4_DXREFESEL_SHIFT (16U) /*! DXREFESEL - Byte Lane External VREF Select */ #define DDRPHY_DX0GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX0GCR4_DXREFESEL_MASK) #define DDRPHY_DX0GCR4_DXREFESELRANGE_MASK (0x800000U) #define DDRPHY_DX0GCR4_DXREFESELRANGE_SHIFT (23U) /*! DXREFESELRANGE - External VREF generator REFSEL range select */ #define DDRPHY_DX0GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX0GCR4_DXREFESELRANGE_MASK) #define DDRPHY_DX0GCR4_RESERVED_24_MASK (0x1000000U) #define DDRPHY_DX0GCR4_RESERVED_24_SHIFT (24U) /*! RESERVED_24 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX0GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX0GCR4_RESERVED_24_MASK) #define DDRPHY_DX0GCR4_DXREFSEN_MASK (0x2000000U) #define DDRPHY_DX0GCR4_DXREFSEN_SHIFT (25U) /*! DXREFSEN - Byte Lane Single-End VREF Enable */ #define DDRPHY_DX0GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFSEN_MASK) #define DDRPHY_DX0GCR4_DXREFEEN_MASK (0xC000000U) #define DDRPHY_DX0GCR4_DXREFEEN_SHIFT (26U) /*! DXREFEEN - Byte Lane Internal VREF Enable */ #define DDRPHY_DX0GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFEEN_MASK) #define DDRPHY_DX0GCR4_DXREFPEN_MASK (0x10000000U) #define DDRPHY_DX0GCR4_DXREFPEN_SHIFT (28U) /*! DXREFPEN - Byte Lane VREF Pad Enable */ #define DDRPHY_DX0GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFPEN_MASK) #define DDRPHY_DX0GCR4_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DX0GCR4_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs) */ #define DDRPHY_DX0GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX0GCR4_RESERVED_31_29_MASK) /*! @} */ /*! @name DX0GCR5 - DATX8 n General Configuration Register 5 */ /*! @{ */ #define DDRPHY_DX0GCR5_DXREFISELR0_MASK (0x7FU) #define DDRPHY_DX0GCR5_DXREFISELR0_SHIFT (0U) /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0 */ #define DDRPHY_DX0GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR0_MASK) #define DDRPHY_DX0GCR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX0GCR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX0GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_7_MASK) #define DDRPHY_DX0GCR5_DXREFISELR1_MASK (0x7F00U) #define DDRPHY_DX0GCR5_DXREFISELR1_SHIFT (8U) /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1 */ #define DDRPHY_DX0GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR1_MASK) #define DDRPHY_DX0GCR5_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX0GCR5_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX0GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_15_MASK) #define DDRPHY_DX0GCR5_DXREFISELR2_MASK (0x7F0000U) #define DDRPHY_DX0GCR5_DXREFISELR2_SHIFT (16U) /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2 */ #define DDRPHY_DX0GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR2_MASK) #define DDRPHY_DX0GCR5_RESERVED_23_MASK (0x800000U) #define DDRPHY_DX0GCR5_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX0GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_23_MASK) #define DDRPHY_DX0GCR5_DXREFISELR3_MASK (0x7F000000U) #define DDRPHY_DX0GCR5_DXREFISELR3_SHIFT (24U) /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3 */ #define DDRPHY_DX0GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR3_MASK) #define DDRPHY_DX0GCR5_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX0GCR5_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX0GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_31_MASK) /*! @} */ /*! @name DX0GCR6 - DATX8 n General Configuration Register 6 */ /*! @{ */ #define DDRPHY_DX0GCR6_DXDQVREFR0_MASK (0x3FU) #define DDRPHY_DX0GCR6_DXDQVREFR0_SHIFT (0U) /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0 */ #define DDRPHY_DX0GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR0_MASK) #define DDRPHY_DX0GCR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0GCR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX0GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_7_6_MASK) #define DDRPHY_DX0GCR6_DXDQVREFR1_MASK (0x3F00U) #define DDRPHY_DX0GCR6_DXDQVREFR1_SHIFT (8U) /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1 */ #define DDRPHY_DX0GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR1_MASK) #define DDRPHY_DX0GCR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0GCR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX0GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_15_14_MASK) #define DDRPHY_DX0GCR6_DXDQVREFR2_MASK (0x3F0000U) #define DDRPHY_DX0GCR6_DXDQVREFR2_SHIFT (16U) /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2 */ #define DDRPHY_DX0GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR2_MASK) #define DDRPHY_DX0GCR6_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX0GCR6_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX0GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_23_22_MASK) #define DDRPHY_DX0GCR6_DXDQVREFR3_MASK (0x3F000000U) #define DDRPHY_DX0GCR6_DXDQVREFR3_SHIFT (24U) /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3 */ #define DDRPHY_DX0GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR3_MASK) #define DDRPHY_DX0GCR6_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX0GCR6_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX0GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_31_30_MASK) /*! @} */ /*! @name DX0GCR7 - DATX8 n General Configuration Register 7 */ /*! @{ */ #define DDRPHY_DX0GCR7_DCALSVAL_MASK (0x1FFU) #define DDRPHY_DX0GCR7_DCALSVAL_SHIFT (0U) /*! DCALSVAL - DDL Calibration Starting Value */ #define DDRPHY_DX0GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX0GCR7_DCALSVAL_MASK) #define DDRPHY_DX0GCR7_DCALTYPE_MASK (0x200U) #define DDRPHY_DX0GCR7_DCALTYPE_SHIFT (9U) /*! DCALTYPE - DDL Calibration Type */ #define DDRPHY_DX0GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX0GCR7_DCALTYPE_MASK) #define DDRPHY_DX0GCR7_RESERVED_17_10_MASK (0x3FC00U) #define DDRPHY_DX0GCR7_RESERVED_17_10_SHIFT (10U) /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX0GCR7_RESERVED_17_10_MASK) #define DDRPHY_DX0GCR7_RESERVED_18_MASK (0x40000U) #define DDRPHY_DX0GCR7_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX0GCR7_RESERVED_18_MASK) #define DDRPHY_DX0GCR7_RESERVED_31_19_MASK (0xFFF80000U) #define DDRPHY_DX0GCR7_RESERVED_31_19_SHIFT (19U) /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX0GCR7_RESERVED_31_19_MASK) /*! @} */ /*! @name DX0GCR8 - DATX8 n General Configuration Register 8 */ /*! @{ */ #define DDRPHY_DX0GCR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX0GCR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_5_0_MASK) #define DDRPHY_DX0GCR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0GCR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_7_6_MASK) #define DDRPHY_DX0GCR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX0GCR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_13_8_MASK) #define DDRPHY_DX0GCR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0GCR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_15_14_MASK) #define DDRPHY_DX0GCR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX0GCR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_21_16_MASK) #define DDRPHY_DX0GCR8_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX0GCR8_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_23_22_MASK) #define DDRPHY_DX0GCR8_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX0GCR8_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_29_24_MASK) #define DDRPHY_DX0GCR8_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX0GCR8_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_31_30_MASK) /*! @} */ /*! @name DX0GCR9 - DATX8 n General Configuration Register 9 */ /*! @{ */ #define DDRPHY_DX0GCR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX0GCR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_5_0_MASK) #define DDRPHY_DX0GCR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0GCR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_7_6_MASK) #define DDRPHY_DX0GCR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX0GCR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_13_8_MASK) #define DDRPHY_DX0GCR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0GCR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_15_14_MASK) #define DDRPHY_DX0GCR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX0GCR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_21_16_MASK) #define DDRPHY_DX0GCR9_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX0GCR9_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_23_22_MASK) #define DDRPHY_DX0GCR9_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX0GCR9_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_29_24_MASK) #define DDRPHY_DX0GCR9_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX0GCR9_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_31_30_MASK) /*! @} */ /*! @name DX0DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */ /*! @{ */ #define DDRPHY_DX0DQMAP0_DQ0MAP_MASK (0xFU) #define DDRPHY_DX0DQMAP0_DQ0MAP_SHIFT (0U) /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index */ #define DDRPHY_DX0DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ0MAP_MASK) #define DDRPHY_DX0DQMAP0_DQ1MAP_MASK (0xF0U) #define DDRPHY_DX0DQMAP0_DQ1MAP_SHIFT (4U) /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index */ #define DDRPHY_DX0DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ1MAP_MASK) #define DDRPHY_DX0DQMAP0_DQ2MAP_MASK (0xF00U) #define DDRPHY_DX0DQMAP0_DQ2MAP_SHIFT (8U) /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index */ #define DDRPHY_DX0DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ2MAP_MASK) #define DDRPHY_DX0DQMAP0_DQ3MAP_MASK (0xF000U) #define DDRPHY_DX0DQMAP0_DQ3MAP_SHIFT (12U) /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index */ #define DDRPHY_DX0DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ3MAP_MASK) #define DDRPHY_DX0DQMAP0_DQ4MAP_MASK (0xF0000U) #define DDRPHY_DX0DQMAP0_DQ4MAP_SHIFT (16U) /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index */ #define DDRPHY_DX0DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ4MAP_MASK) #define DDRPHY_DX0DQMAP0_RESERVED_30_20_MASK (0x7FF00000U) #define DDRPHY_DX0DQMAP0_RESERVED_30_20_SHIFT (20U) /*! RESERVED_30_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX0DQMAP0_RESERVED_30_20_MASK) #define DDRPHY_DX0DQMAP0_MAPOK_MASK (0x80000000U) #define DDRPHY_DX0DQMAP0_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX0DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX0DQMAP0_MAPOK_MASK) /*! @} */ /*! @name DX0DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */ /*! @{ */ #define DDRPHY_DX0DQMAP1_DQ5MAP_MASK (0xFU) #define DDRPHY_DX0DQMAP1_DQ5MAP_SHIFT (0U) /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index */ #define DDRPHY_DX0DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX0DQMAP1_DQ5MAP_MASK) #define DDRPHY_DX0DQMAP1_DQ6MAP_MASK (0xF0U) #define DDRPHY_DX0DQMAP1_DQ6MAP_SHIFT (4U) /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index */ #define DDRPHY_DX0DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX0DQMAP1_DQ6MAP_MASK) #define DDRPHY_DX0DQMAP1_DQ7MAP_MASK (0xF00U) #define DDRPHY_DX0DQMAP1_DQ7MAP_SHIFT (8U) /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index */ #define DDRPHY_DX0DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX0DQMAP1_DQ7MAP_MASK) #define DDRPHY_DX0DQMAP1_DMMAP_MASK (0xF000U) #define DDRPHY_DX0DQMAP1_DMMAP_SHIFT (12U) /*! DMMAP - DM bit DATX8 slice mapping index */ #define DDRPHY_DX0DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX0DQMAP1_DMMAP_MASK) #define DDRPHY_DX0DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U) #define DDRPHY_DX0DQMAP1_RESERVED_30_16_SHIFT (16U) /*! RESERVED_30_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX0DQMAP1_RESERVED_30_16_MASK) #define DDRPHY_DX0DQMAP1_MAPOK_MASK (0x80000000U) #define DDRPHY_DX0DQMAP1_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX0DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX0DQMAP1_MAPOK_MASK) /*! @} */ /*! @name DX0BDLR0 - DATX8 n Bit Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX0BDLR0_DQ0WBD_MASK (0x3FU) #define DDRPHY_DX0BDLR0_DQ0WBD_SHIFT (0U) /*! DQ0WBD - DQ0 Write Bit Delay */ #define DDRPHY_DX0BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ0WBD_MASK) #define DDRPHY_DX0BDLR0_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0BDLR0_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_7_6_MASK) #define DDRPHY_DX0BDLR0_DQ1WBD_MASK (0x3F00U) #define DDRPHY_DX0BDLR0_DQ1WBD_SHIFT (8U) /*! DQ1WBD - DQ1 Write Bit Delay */ #define DDRPHY_DX0BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ1WBD_MASK) #define DDRPHY_DX0BDLR0_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0BDLR0_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_15_14_MASK) #define DDRPHY_DX0BDLR0_DQ2WBD_MASK (0x3F0000U) #define DDRPHY_DX0BDLR0_DQ2WBD_SHIFT (16U) /*! DQ2WBD - DQ2 Write Bit Delay */ #define DDRPHY_DX0BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ2WBD_MASK) #define DDRPHY_DX0BDLR0_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX0BDLR0_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_23_22_MASK) #define DDRPHY_DX0BDLR0_DQ3WBD_MASK (0x3F000000U) #define DDRPHY_DX0BDLR0_DQ3WBD_SHIFT (24U) /*! DQ3WBD - DQ3 Write Bit Delay */ #define DDRPHY_DX0BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ3WBD_MASK) #define DDRPHY_DX0BDLR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX0BDLR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_31_30_MASK) /*! @} */ /*! @name DX0BDLR1 - DATX8 n Bit Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX0BDLR1_DQ4WBD_MASK (0x3FU) #define DDRPHY_DX0BDLR1_DQ4WBD_SHIFT (0U) /*! DQ4WBD - DQ4 Write Bit Delay */ #define DDRPHY_DX0BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ4WBD_MASK) #define DDRPHY_DX0BDLR1_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0BDLR1_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_7_6_MASK) #define DDRPHY_DX0BDLR1_DQ5WBD_MASK (0x3F00U) #define DDRPHY_DX0BDLR1_DQ5WBD_SHIFT (8U) /*! DQ5WBD - DQ5 Write Bit Delay */ #define DDRPHY_DX0BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ5WBD_MASK) #define DDRPHY_DX0BDLR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0BDLR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_15_14_MASK) #define DDRPHY_DX0BDLR1_DQ6WBD_MASK (0x3F0000U) #define DDRPHY_DX0BDLR1_DQ6WBD_SHIFT (16U) /*! DQ6WBD - DQ6 Write Bit Delay */ #define DDRPHY_DX0BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ6WBD_MASK) #define DDRPHY_DX0BDLR1_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX0BDLR1_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_23_22_MASK) #define DDRPHY_DX0BDLR1_DQ7WBD_MASK (0x3F000000U) #define DDRPHY_DX0BDLR1_DQ7WBD_SHIFT (24U) /*! DQ7WBD - DQ7 Write Bit Delay */ #define DDRPHY_DX0BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ7WBD_MASK) #define DDRPHY_DX0BDLR1_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX0BDLR1_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_31_30_MASK) /*! @} */ /*! @name DX0BDLR2 - DATX8 n Bit Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX0BDLR2_DMWBD_MASK (0x3FU) #define DDRPHY_DX0BDLR2_DMWBD_SHIFT (0U) /*! DMWBD - DM Write Bit Delay */ #define DDRPHY_DX0BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DMWBD_SHIFT)) & DDRPHY_DX0BDLR2_DMWBD_MASK) #define DDRPHY_DX0BDLR2_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0BDLR2_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_7_6_MASK) #define DDRPHY_DX0BDLR2_DSWBD_MASK (0x3F00U) #define DDRPHY_DX0BDLR2_DSWBD_SHIFT (8U) /*! DSWBD - DQS Write Bit Delay */ #define DDRPHY_DX0BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DSWBD_SHIFT)) & DDRPHY_DX0BDLR2_DSWBD_MASK) #define DDRPHY_DX0BDLR2_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0BDLR2_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_15_14_MASK) #define DDRPHY_DX0BDLR2_DSOEBD_MASK (0x3F0000U) #define DDRPHY_DX0BDLR2_DSOEBD_SHIFT (16U) /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay */ #define DDRPHY_DX0BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX0BDLR2_DSOEBD_MASK) #define DDRPHY_DX0BDLR2_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX0BDLR2_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_23_22_MASK) #define DDRPHY_DX0BDLR2_DSNWBD_MASK (0x3F000000U) #define DDRPHY_DX0BDLR2_DSNWBD_SHIFT (24U) /*! DSNWBD - DQSN Write Bit Delay */ #define DDRPHY_DX0BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX0BDLR2_DSNWBD_MASK) #define DDRPHY_DX0BDLR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX0BDLR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_31_30_MASK) /*! @} */ /*! @name DX0BDLR3 - DATX8 n Bit Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX0BDLR3_DQ0RBD_MASK (0x3FU) #define DDRPHY_DX0BDLR3_DQ0RBD_SHIFT (0U) /*! DQ0RBD - DQ0 Read Bit Delay */ #define DDRPHY_DX0BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ0RBD_MASK) #define DDRPHY_DX0BDLR3_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0BDLR3_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_7_6_MASK) #define DDRPHY_DX0BDLR3_DQ1RBD_MASK (0x3F00U) #define DDRPHY_DX0BDLR3_DQ1RBD_SHIFT (8U) /*! DQ1RBD - DQ1 Read Bit Delay */ #define DDRPHY_DX0BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ1RBD_MASK) #define DDRPHY_DX0BDLR3_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0BDLR3_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_15_14_MASK) #define DDRPHY_DX0BDLR3_DQ2RBD_MASK (0x3F0000U) #define DDRPHY_DX0BDLR3_DQ2RBD_SHIFT (16U) /*! DQ2RBD - DQ2 Read Bit Delay */ #define DDRPHY_DX0BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ2RBD_MASK) #define DDRPHY_DX0BDLR3_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX0BDLR3_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_23_22_MASK) #define DDRPHY_DX0BDLR3_DQ3RBD_MASK (0x3F000000U) #define DDRPHY_DX0BDLR3_DQ3RBD_SHIFT (24U) /*! DQ3RBD - DQ3 Read Bit Delay */ #define DDRPHY_DX0BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ3RBD_MASK) #define DDRPHY_DX0BDLR3_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX0BDLR3_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_31_30_MASK) /*! @} */ /*! @name DX0BDLR4 - DATX8 n Bit Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX0BDLR4_DQ4RBD_MASK (0x3FU) #define DDRPHY_DX0BDLR4_DQ4RBD_SHIFT (0U) /*! DQ4RBD - DQ4 Read Bit Delay */ #define DDRPHY_DX0BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ4RBD_MASK) #define DDRPHY_DX0BDLR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0BDLR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_7_6_MASK) #define DDRPHY_DX0BDLR4_DQ5RBD_MASK (0x3F00U) #define DDRPHY_DX0BDLR4_DQ5RBD_SHIFT (8U) /*! DQ5RBD - DQ5 Read Bit Delay */ #define DDRPHY_DX0BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ5RBD_MASK) #define DDRPHY_DX0BDLR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0BDLR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_15_14_MASK) #define DDRPHY_DX0BDLR4_DQ6RBD_MASK (0x3F0000U) #define DDRPHY_DX0BDLR4_DQ6RBD_SHIFT (16U) /*! DQ6RBD - DQ6 Read Bit Delay */ #define DDRPHY_DX0BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ6RBD_MASK) #define DDRPHY_DX0BDLR4_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX0BDLR4_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_23_22_MASK) #define DDRPHY_DX0BDLR4_DQ7RBD_MASK (0x3F000000U) #define DDRPHY_DX0BDLR4_DQ7RBD_SHIFT (24U) /*! DQ7RBD - DQ7 Read Bit Delay */ #define DDRPHY_DX0BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ7RBD_MASK) #define DDRPHY_DX0BDLR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX0BDLR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_31_30_MASK) /*! @} */ /*! @name DX0BDLR5 - DATX8 n Bit Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX0BDLR5_DMRBD_MASK (0x3FU) #define DDRPHY_DX0BDLR5_DMRBD_SHIFT (0U) /*! DMRBD - DM Read Bit Delay */ #define DDRPHY_DX0BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR5_DMRBD_SHIFT)) & DDRPHY_DX0BDLR5_DMRBD_MASK) #define DDRPHY_DX0BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U) #define DDRPHY_DX0BDLR5_RESERVED_31_6_SHIFT (6U) /*! RESERVED_31_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX0BDLR5_RESERVED_31_6_MASK) /*! @} */ /*! @name DX0BDLR6 - DATX8 n Bit Delay Line Register 6 */ /*! @{ */ #define DDRPHY_DX0BDLR6_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_DX0BDLR6_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX0BDLR6_RESERVED_7_0_MASK) #define DDRPHY_DX0BDLR6_PDRBD_MASK (0x3F00U) #define DDRPHY_DX0BDLR6_PDRBD_SHIFT (8U) /*! PDRBD - Power down receiver Bit Delay */ #define DDRPHY_DX0BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_PDRBD_SHIFT)) & DDRPHY_DX0BDLR6_PDRBD_MASK) #define DDRPHY_DX0BDLR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0BDLR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR6_RESERVED_15_14_MASK) #define DDRPHY_DX0BDLR6_TERBD_MASK (0x3F0000U) #define DDRPHY_DX0BDLR6_TERBD_SHIFT (16U) /*! TERBD - Termination Enable Bit Delay */ #define DDRPHY_DX0BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_TERBD_SHIFT)) & DDRPHY_DX0BDLR6_TERBD_MASK) #define DDRPHY_DX0BDLR6_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX0BDLR6_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR6_RESERVED_31_22_MASK) /*! @} */ /*! @name DX0BDLR7 - DATX8 n Bit Delay Line Register 7 */ /*! @{ */ #define DDRPHY_DX0BDLR7_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX0BDLR7_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_5_0_MASK) #define DDRPHY_DX0BDLR7_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0BDLR7_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_7_6_MASK) #define DDRPHY_DX0BDLR7_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX0BDLR7_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_13_8_MASK) #define DDRPHY_DX0BDLR7_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0BDLR7_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_15_14_MASK) #define DDRPHY_DX0BDLR7_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX0BDLR7_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_21_16_MASK) #define DDRPHY_DX0BDLR7_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX0BDLR7_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_31_22_MASK) /*! @} */ /*! @name DX0BDLR8 - DATX8 n Bit Delay Line Register 8 */ /*! @{ */ #define DDRPHY_DX0BDLR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX0BDLR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_5_0_MASK) #define DDRPHY_DX0BDLR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0BDLR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_7_6_MASK) #define DDRPHY_DX0BDLR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX0BDLR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_13_8_MASK) #define DDRPHY_DX0BDLR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0BDLR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_15_14_MASK) #define DDRPHY_DX0BDLR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX0BDLR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_21_16_MASK) #define DDRPHY_DX0BDLR8_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX0BDLR8_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_31_22_MASK) /*! @} */ /*! @name DX0BDLR9 - DATX8 n Bit Delay Line Register 9 */ /*! @{ */ #define DDRPHY_DX0BDLR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX0BDLR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_5_0_MASK) #define DDRPHY_DX0BDLR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX0BDLR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_7_6_MASK) #define DDRPHY_DX0BDLR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX0BDLR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_13_8_MASK) #define DDRPHY_DX0BDLR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX0BDLR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_15_14_MASK) #define DDRPHY_DX0BDLR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX0BDLR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_21_16_MASK) #define DDRPHY_DX0BDLR9_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX0BDLR9_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_31_22_MASK) /*! @} */ /*! @name DX0LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX0LCDLR0_WLD_MASK (0x1FFU) #define DDRPHY_DX0LCDLR0_WLD_SHIFT (0U) /*! WLD - Write Leveling Delay */ #define DDRPHY_DX0LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_WLD_SHIFT)) & DDRPHY_DX0LCDLR0_WLD_MASK) #define DDRPHY_DX0LCDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX0LCDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX0LCDLR0_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX0LCDLR0_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR0_RESERVED_24_16_MASK) #define DDRPHY_DX0LCDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX0LCDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX0LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX0LCDLR1_WDQD_MASK (0x1FFU) #define DDRPHY_DX0LCDLR1_WDQD_SHIFT (0U) /*! WDQD - Write Data Delay */ #define DDRPHY_DX0LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_WDQD_SHIFT)) & DDRPHY_DX0LCDLR1_WDQD_MASK) #define DDRPHY_DX0LCDLR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX0LCDLR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR1_RESERVED_15_9_MASK) #define DDRPHY_DX0LCDLR1_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX0LCDLR1_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR1_RESERVED_24_16_MASK) #define DDRPHY_DX0LCDLR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX0LCDLR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX0LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX0LCDLR2_DQSGD_MASK (0x1FFU) #define DDRPHY_DX0LCDLR2_DQSGD_SHIFT (0U) /*! DQSGD - Read DQS Gating Delay */ #define DDRPHY_DX0LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX0LCDLR2_DQSGD_MASK) #define DDRPHY_DX0LCDLR2_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX0LCDLR2_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR2_RESERVED_15_9_MASK) #define DDRPHY_DX0LCDLR2_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX0LCDLR2_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR2_RESERVED_24_16_MASK) #define DDRPHY_DX0LCDLR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX0LCDLR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR2_RESERVED_31_25_MASK) /*! @} */ /*! @name DX0LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX0LCDLR3_RDQSD_MASK (0x1FFU) #define DDRPHY_DX0LCDLR3_RDQSD_SHIFT (0U) /*! RDQSD - Read DQS Delay */ #define DDRPHY_DX0LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX0LCDLR3_RDQSD_MASK) #define DDRPHY_DX0LCDLR3_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX0LCDLR3_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR3_RESERVED_15_9_MASK) #define DDRPHY_DX0LCDLR3_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX0LCDLR3_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR3_RESERVED_24_16_MASK) #define DDRPHY_DX0LCDLR3_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX0LCDLR3_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR3_RESERVED_31_25_MASK) /*! @} */ /*! @name DX0LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX0LCDLR4_RDQSND_MASK (0x1FFU) #define DDRPHY_DX0LCDLR4_RDQSND_SHIFT (0U) /*! RDQSND - Read DQSN Delay */ #define DDRPHY_DX0LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX0LCDLR4_RDQSND_MASK) #define DDRPHY_DX0LCDLR4_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX0LCDLR4_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR4_RESERVED_15_9_MASK) #define DDRPHY_DX0LCDLR4_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX0LCDLR4_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR4_RESERVED_24_16_MASK) #define DDRPHY_DX0LCDLR4_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX0LCDLR4_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR4_RESERVED_31_25_MASK) /*! @} */ /*! @name DX0LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX0LCDLR5_DQSGSD_MASK (0x1FFU) #define DDRPHY_DX0LCDLR5_DQSGSD_SHIFT (0U) /*! DQSGSD - DQS Gating Status Delay */ #define DDRPHY_DX0LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX0LCDLR5_DQSGSD_MASK) #define DDRPHY_DX0LCDLR5_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX0LCDLR5_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR5_RESERVED_15_9_MASK) #define DDRPHY_DX0LCDLR5_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX0LCDLR5_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR5_RESERVED_24_16_MASK) #define DDRPHY_DX0LCDLR5_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX0LCDLR5_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR5_RESERVED_31_25_MASK) /*! @} */ /*! @name DX0MDLR0 - DATX8 n Master Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX0MDLR0_IPRD_MASK (0x1FFU) #define DDRPHY_DX0MDLR0_IPRD_SHIFT (0U) /*! IPRD - Initial Period */ #define DDRPHY_DX0MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_IPRD_SHIFT)) & DDRPHY_DX0MDLR0_IPRD_MASK) #define DDRPHY_DX0MDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX0MDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX0MDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX0MDLR0_TPRD_MASK (0x1FF0000U) #define DDRPHY_DX0MDLR0_TPRD_SHIFT (16U) /*! TPRD - Target Period */ #define DDRPHY_DX0MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_TPRD_SHIFT)) & DDRPHY_DX0MDLR0_TPRD_MASK) #define DDRPHY_DX0MDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX0MDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX0MDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX0MDLR1 - DATX8 n Master Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX0MDLR1_MDLD_MASK (0x1FFU) #define DDRPHY_DX0MDLR1_MDLD_SHIFT (0U) /*! MDLD - MDL Delay */ #define DDRPHY_DX0MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR1_MDLD_SHIFT)) & DDRPHY_DX0MDLR1_MDLD_MASK) #define DDRPHY_DX0MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U) #define DDRPHY_DX0MDLR1_RESERVED_31_9_SHIFT (9U) /*! RESERVED_31_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX0MDLR1_RESERVED_31_9_MASK) /*! @} */ /*! @name DX0GTR0 - DATX8 n General Timing Register 0 */ /*! @{ */ #define DDRPHY_DX0GTR0_DGSL_MASK (0x1FU) #define DDRPHY_DX0GTR0_DGSL_SHIFT (0U) /*! DGSL - DQS Gating System Latency */ #define DDRPHY_DX0GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_DGSL_SHIFT)) & DDRPHY_DX0GTR0_DGSL_MASK) #define DDRPHY_DX0GTR0_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DX0GTR0_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_7_5_MASK) #define DDRPHY_DX0GTR0_RESERVED_12_8_MASK (0x1F00U) #define DDRPHY_DX0GTR0_RESERVED_12_8_SHIFT (8U) /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_12_8_MASK) #define DDRPHY_DX0GTR0_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_DX0GTR0_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_15_13_MASK) #define DDRPHY_DX0GTR0_WLSL_MASK (0xF0000U) #define DDRPHY_DX0GTR0_WLSL_SHIFT (16U) /*! WLSL - Write Leveling System Latency */ #define DDRPHY_DX0GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_WLSL_SHIFT)) & DDRPHY_DX0GTR0_WLSL_MASK) #define DDRPHY_DX0GTR0_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX0GTR0_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX0GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_23_20_MASK) #define DDRPHY_DX0GTR0_WDQSL_MASK (0x7000000U) #define DDRPHY_DX0GTR0_WDQSL_SHIFT (24U) /*! WDQSL - DQ Write Path Latency Pipeline */ #define DDRPHY_DX0GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_WDQSL_SHIFT)) & DDRPHY_DX0GTR0_WDQSL_MASK) #define DDRPHY_DX0GTR0_RESERVED_31_24_MASK (0xF8000000U) #define DDRPHY_DX0GTR0_RESERVED_31_24_SHIFT (27U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_31_24_MASK) /*! @} */ /*! @name DX0RSR0 - DATX8 n Rank Status Register 0 */ /*! @{ */ #define DDRPHY_DX0RSR0_QSGERR_MASK (0xFFFFU) #define DDRPHY_DX0RSR0_QSGERR_SHIFT (0U) /*! QSGERR - DQS Gate Training Error */ #define DDRPHY_DX0RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR0_QSGERR_SHIFT)) & DDRPHY_DX0RSR0_QSGERR_MASK) #define DDRPHY_DX0RSR0_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX0RSR0_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR0_RESERVED_31_16_MASK) /*! @} */ /*! @name DX0RSR1 - DATX8 n Rank Status Register 1 */ /*! @{ */ #define DDRPHY_DX0RSR1_RDLVLERR_MASK (0xFFFFU) #define DDRPHY_DX0RSR1_RDLVLERR_SHIFT (0U) /*! RDLVLERR - Read Leveling Error */ #define DDRPHY_DX0RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX0RSR1_RDLVLERR_MASK) #define DDRPHY_DX0RSR1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX0RSR1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR1_RESERVED_31_16_MASK) /*! @} */ /*! @name DX0RSR2 - DATX8 n Rank Status Register 2 */ /*! @{ */ #define DDRPHY_DX0RSR2_WLAWN_MASK (0xFFFFU) #define DDRPHY_DX0RSR2_WLAWN_SHIFT (0U) /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning */ #define DDRPHY_DX0RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR2_WLAWN_SHIFT)) & DDRPHY_DX0RSR2_WLAWN_MASK) #define DDRPHY_DX0RSR2_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX0RSR2_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR2_RESERVED_31_16_MASK) /*! @} */ /*! @name DX0RSR3 - DATX8 n Rank Status Register 3 */ /*! @{ */ #define DDRPHY_DX0RSR3_WLAERR_MASK (0xFFFFU) #define DDRPHY_DX0RSR3_WLAERR_SHIFT (0U) /*! WLAERR - Write Leveling Adjustment Error */ #define DDRPHY_DX0RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR3_WLAERR_SHIFT)) & DDRPHY_DX0RSR3_WLAERR_MASK) #define DDRPHY_DX0RSR3_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX0RSR3_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR3_RESERVED_31_16_MASK) /*! @} */ /*! @name DX0GSR0 - DATX8 n General Status Register 0 */ /*! @{ */ #define DDRPHY_DX0GSR0_WDQCAL_MASK (0x1U) #define DDRPHY_DX0GSR0_WDQCAL_SHIFT (0U) /*! WDQCAL - Write DQ Calibration */ #define DDRPHY_DX0GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WDQCAL_SHIFT)) & DDRPHY_DX0GSR0_WDQCAL_MASK) #define DDRPHY_DX0GSR0_RDQSCAL_MASK (0x2U) #define DDRPHY_DX0GSR0_RDQSCAL_SHIFT (1U) /*! RDQSCAL - Read DQS Calibration */ #define DDRPHY_DX0GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX0GSR0_RDQSCAL_MASK) #define DDRPHY_DX0GSR0_RDQSNCAL_MASK (0x4U) #define DDRPHY_DX0GSR0_RDQSNCAL_SHIFT (2U) /*! RDQSNCAL - Read DQS# Calibration */ #define DDRPHY_DX0GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX0GSR0_RDQSNCAL_MASK) #define DDRPHY_DX0GSR0_GDQSCAL_MASK (0x8U) #define DDRPHY_DX0GSR0_GDQSCAL_SHIFT (3U) /*! GDQSCAL - Read DQS gating Calibration */ #define DDRPHY_DX0GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX0GSR0_GDQSCAL_MASK) #define DDRPHY_DX0GSR0_WLCAL_MASK (0x10U) #define DDRPHY_DX0GSR0_WLCAL_SHIFT (4U) /*! WLCAL - Write Leveling Calibration */ #define DDRPHY_DX0GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLCAL_SHIFT)) & DDRPHY_DX0GSR0_WLCAL_MASK) #define DDRPHY_DX0GSR0_WLDONE_MASK (0x20U) #define DDRPHY_DX0GSR0_WLDONE_SHIFT (5U) /*! WLDONE - Write Leveling Done */ #define DDRPHY_DX0GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLDONE_SHIFT)) & DDRPHY_DX0GSR0_WLDONE_MASK) #define DDRPHY_DX0GSR0_WLERR_MASK (0x40U) #define DDRPHY_DX0GSR0_WLERR_SHIFT (6U) /*! WLERR - Write Leveling Error */ #define DDRPHY_DX0GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLERR_SHIFT)) & DDRPHY_DX0GSR0_WLERR_MASK) #define DDRPHY_DX0GSR0_WLPRD_MASK (0xFF80U) #define DDRPHY_DX0GSR0_WLPRD_SHIFT (7U) /*! WLPRD - Write Leveling Period */ #define DDRPHY_DX0GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLPRD_SHIFT)) & DDRPHY_DX0GSR0_WLPRD_MASK) #define DDRPHY_DX0GSR0_DPLOCK_MASK (0x10000U) #define DDRPHY_DX0GSR0_DPLOCK_SHIFT (16U) /*! DPLOCK - DATX8 PLL Lock */ #define DDRPHY_DX0GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_DPLOCK_SHIFT)) & DDRPHY_DX0GSR0_DPLOCK_MASK) #define DDRPHY_DX0GSR0_GDQSPRD_MASK (0x3FE0000U) #define DDRPHY_DX0GSR0_GDQSPRD_SHIFT (17U) /*! GDQSPRD - Read DQS gating Period */ #define DDRPHY_DX0GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX0GSR0_GDQSPRD_MASK) #define DDRPHY_DX0GSR0_RESERVED_29_26_MASK (0x3C000000U) #define DDRPHY_DX0GSR0_RESERVED_29_26_SHIFT (26U) /*! RESERVED_29_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX0GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX0GSR0_RESERVED_29_26_MASK) #define DDRPHY_DX0GSR0_WLDQ_MASK (0x40000000U) #define DDRPHY_DX0GSR0_WLDQ_SHIFT (30U) /*! WLDQ - Write Leveling DQ Status */ #define DDRPHY_DX0GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLDQ_SHIFT)) & DDRPHY_DX0GSR0_WLDQ_MASK) #define DDRPHY_DX0GSR0_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX0GSR0_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX0GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX0GSR0_RESERVED_31_MASK) /*! @} */ /*! @name DX0GSR1 - DATX8 n General Status Register 1 */ /*! @{ */ #define DDRPHY_DX0GSR1_DLTDONE_MASK (0x1U) #define DDRPHY_DX0GSR1_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done */ #define DDRPHY_DX0GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR1_DLTDONE_SHIFT)) & DDRPHY_DX0GSR1_DLTDONE_MASK) #define DDRPHY_DX0GSR1_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_DX0GSR1_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code */ #define DDRPHY_DX0GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR1_DLTCODE_SHIFT)) & DDRPHY_DX0GSR1_DLTCODE_MASK) #define DDRPHY_DX0GSR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX0GSR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX0GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX0GSR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX0GSR2 - DATX8 n General Status Register 2 */ /*! @{ */ #define DDRPHY_DX0GSR2_RDERR_MASK (0x1U) #define DDRPHY_DX0GSR2_RDERR_SHIFT (0U) /*! RDERR - Read Bit Deskew Error */ #define DDRPHY_DX0GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_RDERR_SHIFT)) & DDRPHY_DX0GSR2_RDERR_MASK) #define DDRPHY_DX0GSR2_RDWN_MASK (0x2U) #define DDRPHY_DX0GSR2_RDWN_SHIFT (1U) /*! RDWN - Read Bit Deskew Warning */ #define DDRPHY_DX0GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_RDWN_SHIFT)) & DDRPHY_DX0GSR2_RDWN_MASK) #define DDRPHY_DX0GSR2_WDERR_MASK (0x4U) #define DDRPHY_DX0GSR2_WDERR_SHIFT (2U) /*! WDERR - Write Bit Deskew Error */ #define DDRPHY_DX0GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WDERR_SHIFT)) & DDRPHY_DX0GSR2_WDERR_MASK) #define DDRPHY_DX0GSR2_WDWN_MASK (0x8U) #define DDRPHY_DX0GSR2_WDWN_SHIFT (3U) /*! WDWN - Write Bit Deskew Warning */ #define DDRPHY_DX0GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WDWN_SHIFT)) & DDRPHY_DX0GSR2_WDWN_MASK) #define DDRPHY_DX0GSR2_REERR_MASK (0x10U) #define DDRPHY_DX0GSR2_REERR_SHIFT (4U) /*! REERR - Read Eye Centering Error */ #define DDRPHY_DX0GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_REERR_SHIFT)) & DDRPHY_DX0GSR2_REERR_MASK) #define DDRPHY_DX0GSR2_REWN_MASK (0x20U) #define DDRPHY_DX0GSR2_REWN_SHIFT (5U) /*! REWN - Read Eye Centering Warning */ #define DDRPHY_DX0GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_REWN_SHIFT)) & DDRPHY_DX0GSR2_REWN_MASK) #define DDRPHY_DX0GSR2_WEERR_MASK (0x40U) #define DDRPHY_DX0GSR2_WEERR_SHIFT (6U) /*! WEERR - Write Eye Centering Error */ #define DDRPHY_DX0GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WEERR_SHIFT)) & DDRPHY_DX0GSR2_WEERR_MASK) #define DDRPHY_DX0GSR2_WEWN_MASK (0x80U) #define DDRPHY_DX0GSR2_WEWN_SHIFT (7U) /*! WEWN - Write Eye Centering Warning */ #define DDRPHY_DX0GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WEWN_SHIFT)) & DDRPHY_DX0GSR2_WEWN_MASK) #define DDRPHY_DX0GSR2_ESTAT_MASK (0xF00U) #define DDRPHY_DX0GSR2_ESTAT_SHIFT (8U) /*! ESTAT - Error Status */ #define DDRPHY_DX0GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_ESTAT_SHIFT)) & DDRPHY_DX0GSR2_ESTAT_MASK) #define DDRPHY_DX0GSR2_DQS2DQERR_MASK (0xFF000U) #define DDRPHY_DX0GSR2_DQS2DQERR_SHIFT (12U) /*! DQS2DQERR - Write DQS2DQ Training Error */ #define DDRPHY_DX0GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX0GSR2_DQS2DQERR_MASK) #define DDRPHY_DX0GSR2_SRDERR_MASK (0x100000U) #define DDRPHY_DX0GSR2_SRDERR_SHIFT (20U) /*! SRDERR - Static Read Error */ #define DDRPHY_DX0GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_SRDERR_SHIFT)) & DDRPHY_DX0GSR2_SRDERR_MASK) #define DDRPHY_DX0GSR2_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX0GSR2_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX0GSR2_RESERVED_21_MASK) #define DDRPHY_DX0GSR2_GSDQSCAL_MASK (0x400000U) #define DDRPHY_DX0GSR2_GSDQSCAL_SHIFT (22U) /*! GSDQSCAL - Read DQS Gating Status Calibration */ #define DDRPHY_DX0GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX0GSR2_GSDQSCAL_MASK) #define DDRPHY_DX0GSR2_GSDQSPRD_MASK (0xFF800000U) #define DDRPHY_DX0GSR2_GSDQSPRD_SHIFT (23U) /*! GSDQSPRD - Read DQS gating Status Period */ #define DDRPHY_DX0GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX0GSR2_GSDQSPRD_MASK) /*! @} */ /*! @name DX0GSR3 - DATX8 n General Status Register 3 */ /*! @{ */ #define DDRPHY_DX0GSR3_SRDPC_MASK (0x3U) #define DDRPHY_DX0GSR3_SRDPC_SHIFT (0U) /*! SRDPC - Static Read Delay Pass Count */ #define DDRPHY_DX0GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_SRDPC_SHIFT)) & DDRPHY_DX0GSR3_SRDPC_MASK) #define DDRPHY_DX0GSR3_RESERVED_7_2_MASK (0xFCU) #define DDRPHY_DX0GSR3_RESERVED_7_2_SHIFT (2U) /*! RESERVED_7_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX0GSR3_RESERVED_7_2_MASK) #define DDRPHY_DX0GSR3_HVERR_MASK (0xF00U) #define DDRPHY_DX0GSR3_HVERR_SHIFT (8U) /*! HVERR - Host VREF Training Error */ #define DDRPHY_DX0GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_HVERR_SHIFT)) & DDRPHY_DX0GSR3_HVERR_MASK) #define DDRPHY_DX0GSR3_HVWRN_MASK (0xF000U) #define DDRPHY_DX0GSR3_HVWRN_SHIFT (12U) /*! HVWRN - Host VREF Training Warning */ #define DDRPHY_DX0GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_HVWRN_SHIFT)) & DDRPHY_DX0GSR3_HVWRN_MASK) #define DDRPHY_DX0GSR3_DVERR_MASK (0xF0000U) #define DDRPHY_DX0GSR3_DVERR_SHIFT (16U) /*! DVERR - DRAM VREF Training Error */ #define DDRPHY_DX0GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_DVERR_SHIFT)) & DDRPHY_DX0GSR3_DVERR_MASK) #define DDRPHY_DX0GSR3_DVWRN_MASK (0xF00000U) #define DDRPHY_DX0GSR3_DVWRN_SHIFT (20U) /*! DVWRN - DRAM VREF Training Warning */ #define DDRPHY_DX0GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_DVWRN_SHIFT)) & DDRPHY_DX0GSR3_DVWRN_MASK) #define DDRPHY_DX0GSR3_ESTAT_MASK (0x7000000U) #define DDRPHY_DX0GSR3_ESTAT_SHIFT (24U) /*! ESTAT - VREF Training Error Status Code */ #define DDRPHY_DX0GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_ESTAT_SHIFT)) & DDRPHY_DX0GSR3_ESTAT_MASK) #define DDRPHY_DX0GSR3_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX0GSR3_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX0GSR3_RESERVED_31_27_MASK) /*! @} */ /*! @name DX0GSR4 - DATX8 n General Status Register 4 */ /*! @{ */ #define DDRPHY_DX0GSR4_RESERVED_0_MASK (0x1U) #define DDRPHY_DX0GSR4_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_0_MASK) #define DDRPHY_DX0GSR4_RESERVED_1_MASK (0x2U) #define DDRPHY_DX0GSR4_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_1_MASK) #define DDRPHY_DX0GSR4_RESERVED_2_MASK (0x4U) #define DDRPHY_DX0GSR4_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_2_MASK) #define DDRPHY_DX0GSR4_RESERVED_3_MASK (0x8U) #define DDRPHY_DX0GSR4_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_3_MASK) #define DDRPHY_DX0GSR4_RESERVED_4_MASK (0x10U) #define DDRPHY_DX0GSR4_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_4_MASK) #define DDRPHY_DX0GSR4_RESERVED_5_MASK (0x20U) #define DDRPHY_DX0GSR4_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_5_MASK) #define DDRPHY_DX0GSR4_RESERVED_6_MASK (0x40U) #define DDRPHY_DX0GSR4_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_6_MASK) #define DDRPHY_DX0GSR4_RESERVED_15_7_MASK (0xFF80U) #define DDRPHY_DX0GSR4_RESERVED_15_7_SHIFT (7U) /*! RESERVED_15_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_15_7_MASK) #define DDRPHY_DX0GSR4_RESERVED_16_MASK (0x10000U) #define DDRPHY_DX0GSR4_RESERVED_16_SHIFT (16U) /*! RESERVED_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_16_MASK) #define DDRPHY_DX0GSR4_RESERVED_25_17_MASK (0x3FE0000U) #define DDRPHY_DX0GSR4_RESERVED_25_17_SHIFT (17U) /*! RESERVED_25_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_25_17_MASK) #define DDRPHY_DX0GSR4_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_DX0GSR4_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX0GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_31_26_MASK) /*! @} */ /*! @name DX0GSR5 - DATX8 n General Status Register 5 */ /*! @{ */ #define DDRPHY_DX0GSR5_RESERVED_0_MASK (0x1U) #define DDRPHY_DX0GSR5_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_0_MASK) #define DDRPHY_DX0GSR5_RESERVED_1_MASK (0x2U) #define DDRPHY_DX0GSR5_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_1_MASK) #define DDRPHY_DX0GSR5_RESERVED_2_MASK (0x4U) #define DDRPHY_DX0GSR5_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_2_MASK) #define DDRPHY_DX0GSR5_RESERVED_3_MASK (0x8U) #define DDRPHY_DX0GSR5_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_3_MASK) #define DDRPHY_DX0GSR5_RESERVED_4_MASK (0x10U) #define DDRPHY_DX0GSR5_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_4_MASK) #define DDRPHY_DX0GSR5_RESERVED_5_MASK (0x20U) #define DDRPHY_DX0GSR5_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_5_MASK) #define DDRPHY_DX0GSR5_RESERVED_6_MASK (0x40U) #define DDRPHY_DX0GSR5_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_6_MASK) #define DDRPHY_DX0GSR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX0GSR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_7_MASK) #define DDRPHY_DX0GSR5_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX0GSR5_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_11_8_MASK) #define DDRPHY_DX0GSR5_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_DX0GSR5_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_19_12_MASK) #define DDRPHY_DX0GSR5_RESERVED_20_MASK (0x100000U) #define DDRPHY_DX0GSR5_RESERVED_20_SHIFT (20U) /*! RESERVED_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_20_MASK) #define DDRPHY_DX0GSR5_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX0GSR5_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_21_MASK) #define DDRPHY_DX0GSR5_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX0GSR5_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_22_MASK) #define DDRPHY_DX0GSR5_RESERVED_31_23_MASK (0xFF800000U) #define DDRPHY_DX0GSR5_RESERVED_31_23_SHIFT (23U) /*! RESERVED_31_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_31_23_MASK) /*! @} */ /*! @name DX0GSR6 - DATX8 n General Status Register 6 */ /*! @{ */ #define DDRPHY_DX0GSR6_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX0GSR6_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_1_0_MASK) #define DDRPHY_DX0GSR6_RESERVED_3_2_MASK (0xCU) #define DDRPHY_DX0GSR6_RESERVED_3_2_SHIFT (2U) /*! RESERVED_3_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_3_2_MASK) #define DDRPHY_DX0GSR6_RESERVED_7_4_MASK (0xF0U) #define DDRPHY_DX0GSR6_RESERVED_7_4_SHIFT (4U) /*! RESERVED_7_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_7_4_MASK) #define DDRPHY_DX0GSR6_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX0GSR6_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_11_8_MASK) #define DDRPHY_DX0GSR6_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_DX0GSR6_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_15_12_MASK) #define DDRPHY_DX0GSR6_RESERVED_19_15_MASK (0xF0000U) #define DDRPHY_DX0GSR6_RESERVED_19_15_SHIFT (16U) /*! RESERVED_19_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_19_15_MASK) #define DDRPHY_DX0GSR6_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX0GSR6_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_23_20_MASK) #define DDRPHY_DX0GSR6_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX0GSR6_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX0GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_31_24_MASK) /*! @} */ /*! @name DX1GCR0 - DATX8 n General Configuration Register 0 */ /*! @{ */ #define DDRPHY_DX1GCR0_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX1GCR0_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX1GCR0_RESERVED_1_0_MASK) #define DDRPHY_DX1GCR0_DQSGOE_MASK (0x4U) #define DDRPHY_DX1GCR0_DQSGOE_SHIFT (2U) /*! DQSGOE - DQSG Output Enable */ #define DDRPHY_DX1GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSGOE_SHIFT)) & DDRPHY_DX1GCR0_DQSGOE_MASK) #define DDRPHY_DX1GCR0_DQSGODT_MASK (0x8U) #define DDRPHY_DX1GCR0_DQSGODT_SHIFT (3U) /*! DQSGODT - DQSG On-Die Termination */ #define DDRPHY_DX1GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSGODT_SHIFT)) & DDRPHY_DX1GCR0_DQSGODT_MASK) #define DDRPHY_DX1GCR0_RESERVED_4_MASK (0x10U) #define DDRPHY_DX1GCR0_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX1GCR0_RESERVED_4_MASK) #define DDRPHY_DX1GCR0_DQSGPDR_MASK (0x20U) #define DDRPHY_DX1GCR0_DQSGPDR_SHIFT (5U) /*! DQSGPDR - DQSG Power Down Receiver */ #define DDRPHY_DX1GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX1GCR0_DQSGPDR_MASK) #define DDRPHY_DX1GCR0_DQSRPD_MASK (0x40U) #define DDRPHY_DX1GCR0_DQSRPD_SHIFT (6U) /*! DQSRPD - DQSR Power Down */ #define DDRPHY_DX1GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSRPD_SHIFT)) & DDRPHY_DX1GCR0_DQSRPD_MASK) #define DDRPHY_DX1GCR0_CPDRSHFT_MASK (0x180U) #define DDRPHY_DX1GCR0_CPDRSHFT_SHIFT (7U) /*! CPDRSHFT - Configurable PDR Phase Shift */ #define DDRPHY_DX1GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX1GCR0_CPDRSHFT_MASK) #define DDRPHY_DX1GCR0_RTTOH_MASK (0x600U) #define DDRPHY_DX1GCR0_RTTOH_SHIFT (9U) /*! RTTOH - RTT Output Hold */ #define DDRPHY_DX1GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RTTOH_SHIFT)) & DDRPHY_DX1GCR0_RTTOH_MASK) #define DDRPHY_DX1GCR0_RTTOAL_MASK (0x800U) #define DDRPHY_DX1GCR0_RTTOAL_SHIFT (11U) /*! RTTOAL - RTT On Additive Latency */ #define DDRPHY_DX1GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RTTOAL_SHIFT)) & DDRPHY_DX1GCR0_RTTOAL_MASK) #define DDRPHY_DX1GCR0_DQSSEPDR_MASK (0x1000U) #define DDRPHY_DX1GCR0_DQSSEPDR_SHIFT (12U) /*! DQSSEPDR - DQSSE Power Down Receiver */ #define DDRPHY_DX1GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX1GCR0_DQSSEPDR_MASK) #define DDRPHY_DX1GCR0_DQSNSEPDR_MASK (0x2000U) #define DDRPHY_DX1GCR0_DQSNSEPDR_SHIFT (13U) /*! DQSNSEPDR - DQSNSE Power Down Receiver */ #define DDRPHY_DX1GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX1GCR0_DQSNSEPDR_MASK) #define DDRPHY_DX1GCR0_RESERVED_19_14_MASK (0xFC000U) #define DDRPHY_DX1GCR0_RESERVED_19_14_SHIFT (14U) /*! RESERVED_19_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX1GCR0_RESERVED_19_14_MASK) #define DDRPHY_DX1GCR0_RDDLY_MASK (0xF00000U) #define DDRPHY_DX1GCR0_RDDLY_SHIFT (20U) /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY */ #define DDRPHY_DX1GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RDDLY_SHIFT)) & DDRPHY_DX1GCR0_RDDLY_MASK) #define DDRPHY_DX1GCR0_DQSDCC_MASK (0xF000000U) #define DDRPHY_DX1GCR0_DQSDCC_SHIFT (24U) /*! DQSDCC - DQS Duty Cycle Correction */ #define DDRPHY_DX1GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSDCC_SHIFT)) & DDRPHY_DX1GCR0_DQSDCC_MASK) #define DDRPHY_DX1GCR0_CODTSHFT_MASK (0x30000000U) #define DDRPHY_DX1GCR0_CODTSHFT_SHIFT (28U) /*! CODTSHFT - Configurable ODT(TE) Phase Shift */ #define DDRPHY_DX1GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX1GCR0_CODTSHFT_MASK) #define DDRPHY_DX1GCR0_MDLEN_MASK (0x40000000U) #define DDRPHY_DX1GCR0_MDLEN_SHIFT (30U) /*! MDLEN - Master Delay Line Enable */ #define DDRPHY_DX1GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_MDLEN_SHIFT)) & DDRPHY_DX1GCR0_MDLEN_MASK) #define DDRPHY_DX1GCR0_CALBYP_MASK (0x80000000U) #define DDRPHY_DX1GCR0_CALBYP_SHIFT (31U) /*! CALBYP - Calibration Bypass */ #define DDRPHY_DX1GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_CALBYP_SHIFT)) & DDRPHY_DX1GCR0_CALBYP_MASK) /*! @} */ /*! @name DX1GCR1 - DATX8 n General Configuration Register 1 */ /*! @{ */ #define DDRPHY_DX1GCR1_DQEN_MASK (0xFFU) #define DDRPHY_DX1GCR1_DQEN_SHIFT (0U) /*! DQEN - Enables DQ corresponding to each bit in a byte */ #define DDRPHY_DX1GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DQEN_SHIFT)) & DDRPHY_DX1GCR1_DQEN_MASK) #define DDRPHY_DX1GCR1_DMEN_MASK (0x100U) #define DDRPHY_DX1GCR1_DMEN_SHIFT (8U) /*! DMEN - Enables DM pin in a byte lane */ #define DDRPHY_DX1GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DMEN_SHIFT)) & DDRPHY_DX1GCR1_DMEN_MASK) #define DDRPHY_DX1GCR1_DSEN_MASK (0x200U) #define DDRPHY_DX1GCR1_DSEN_SHIFT (9U) /*! DSEN - Enables Write Data strobe in a byte lane */ #define DDRPHY_DX1GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DSEN_SHIFT)) & DDRPHY_DX1GCR1_DSEN_MASK) #define DDRPHY_DX1GCR1_TEEN_MASK (0x400U) #define DDRPHY_DX1GCR1_TEEN_SHIFT (10U) /*! TEEN - Enables ODT/TE in a byte lane */ #define DDRPHY_DX1GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_TEEN_SHIFT)) & DDRPHY_DX1GCR1_TEEN_MASK) #define DDRPHY_DX1GCR1_PDREN_MASK (0x800U) #define DDRPHY_DX1GCR1_PDREN_SHIFT (11U) /*! PDREN - Enables PDR in a byte lane */ #define DDRPHY_DX1GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_PDREN_SHIFT)) & DDRPHY_DX1GCR1_PDREN_MASK) #define DDRPHY_DX1GCR1_OEEN_MASK (0x1000U) #define DDRPHY_DX1GCR1_OEEN_SHIFT (12U) /*! OEEN - Enables Read Data Strobe in a byte lane */ #define DDRPHY_DX1GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_OEEN_SHIFT)) & DDRPHY_DX1GCR1_OEEN_MASK) #define DDRPHY_DX1GCR1_QSSEL_MASK (0x2000U) #define DDRPHY_DX1GCR1_QSSEL_SHIFT (13U) /*! QSSEL - Select the delayed or non-delayed read data strobe */ #define DDRPHY_DX1GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_QSSEL_SHIFT)) & DDRPHY_DX1GCR1_QSSEL_MASK) #define DDRPHY_DX1GCR1_QSNSEL_MASK (0x4000U) #define DDRPHY_DX1GCR1_QSNSEL_SHIFT (14U) /*! QSNSEL - Select the delayed or non-delayed read data strobe # */ #define DDRPHY_DX1GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_QSNSEL_SHIFT)) & DDRPHY_DX1GCR1_QSNSEL_MASK) #define DDRPHY_DX1GCR1_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX1GCR1_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX1GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX1GCR1_RESERVED_15_MASK) #define DDRPHY_DX1GCR1_DXPDRMODE_MASK (0xFFFF0000U) #define DDRPHY_DX1GCR1_DXPDRMODE_SHIFT (16U) /*! DXPDRMODE - Enables the PDR mode for DQ[7:0] */ #define DDRPHY_DX1GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX1GCR1_DXPDRMODE_MASK) /*! @} */ /*! @name DX1GCR2 - DATX8 n General Configuration Register 2 */ /*! @{ */ #define DDRPHY_DX1GCR2_DXTEMODE_MASK (0xFFFFU) #define DDRPHY_DX1GCR2_DXTEMODE_SHIFT (0U) /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0] */ #define DDRPHY_DX1GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX1GCR2_DXTEMODE_MASK) #define DDRPHY_DX1GCR2_DXOEMODE_MASK (0xFFFF0000U) #define DDRPHY_DX1GCR2_DXOEMODE_SHIFT (16U) /*! DXOEMODE - Enables the OE mode values for DQ[7:0] */ #define DDRPHY_DX1GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX1GCR2_DXOEMODE_MASK) /*! @} */ /*! @name DX1GCR3 - DATX8 n General Configuration Register 3 */ /*! @{ */ #define DDRPHY_DX1GCR3_WDMBVT_MASK (0x1U) #define DDRPHY_DX1GCR3_WDMBVT_SHIFT (0U) /*! WDMBVT - Write Data Mask BDL VT Compensation */ #define DDRPHY_DX1GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDMBVT_SHIFT)) & DDRPHY_DX1GCR3_WDMBVT_MASK) #define DDRPHY_DX1GCR3_RDMBVT_MASK (0x2U) #define DDRPHY_DX1GCR3_RDMBVT_SHIFT (1U) /*! RDMBVT - Read Data Mask BDL VT Compensation */ #define DDRPHY_DX1GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RDMBVT_SHIFT)) & DDRPHY_DX1GCR3_RDMBVT_MASK) #define DDRPHY_DX1GCR3_DSPDRMODE_MASK (0xCU) #define DDRPHY_DX1GCR3_DSPDRMODE_SHIFT (2U) /*! DSPDRMODE - Enables the PDR mode values for DQS. */ #define DDRPHY_DX1GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX1GCR3_DSPDRMODE_MASK) #define DDRPHY_DX1GCR3_DSTEMODE_MASK (0x30U) #define DDRPHY_DX1GCR3_DSTEMODE_SHIFT (4U) /*! DSTEMODE - Enables the TE mode values for DQS. */ #define DDRPHY_DX1GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSTEMODE_MASK) #define DDRPHY_DX1GCR3_DSOEMODE_MASK (0xC0U) #define DDRPHY_DX1GCR3_DSOEMODE_SHIFT (6U) /*! DSOEMODE - Enables the OE mode values for DQS. */ #define DDRPHY_DX1GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSOEMODE_MASK) #define DDRPHY_DX1GCR3_WDSBVT_MASK (0x100U) #define DDRPHY_DX1GCR3_WDSBVT_SHIFT (8U) /*! WDSBVT - Write Data Strobe BDL VT Compensation */ #define DDRPHY_DX1GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDSBVT_SHIFT)) & DDRPHY_DX1GCR3_WDSBVT_MASK) #define DDRPHY_DX1GCR3_RESERVED_9_MASK (0x200U) #define DDRPHY_DX1GCR3_RESERVED_9_SHIFT (9U) /*! RESERVED_9 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX1GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX1GCR3_RESERVED_9_MASK) #define DDRPHY_DX1GCR3_DMPDRMODE_MASK (0xC00U) #define DDRPHY_DX1GCR3_DMPDRMODE_SHIFT (10U) /*! DMPDRMODE - Enables the PDR mode values for DM. */ #define DDRPHY_DX1GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX1GCR3_DMPDRMODE_MASK) #define DDRPHY_DX1GCR3_DMTEMODE_MASK (0x3000U) #define DDRPHY_DX1GCR3_DMTEMODE_SHIFT (12U) /*! DMTEMODE - Enables the TE mode values for DM. */ #define DDRPHY_DX1GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX1GCR3_DMTEMODE_MASK) #define DDRPHY_DX1GCR3_DMOEMODE_MASK (0xC000U) #define DDRPHY_DX1GCR3_DMOEMODE_SHIFT (14U) /*! DMOEMODE - Enables the OE mode values for DM. */ #define DDRPHY_DX1GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX1GCR3_DMOEMODE_MASK) #define DDRPHY_DX1GCR3_DSNPDRMODE_MASK (0x30000U) #define DDRPHY_DX1GCR3_DSNPDRMODE_SHIFT (16U) /*! DSNPDRMODE - Enables the PDR mode for DQS */ #define DDRPHY_DX1GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX1GCR3_DSNPDRMODE_MASK) #define DDRPHY_DX1GCR3_DSNTEMODE_MASK (0xC0000U) #define DDRPHY_DX1GCR3_DSNTEMODE_SHIFT (18U) /*! DSNTEMODE - Enables the TE mode for DQS */ #define DDRPHY_DX1GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSNTEMODE_MASK) #define DDRPHY_DX1GCR3_DSNOEMODE_MASK (0x300000U) #define DDRPHY_DX1GCR3_DSNOEMODE_SHIFT (20U) /*! DSNOEMODE - Enables the OE mode for DQs */ #define DDRPHY_DX1GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSNOEMODE_MASK) #define DDRPHY_DX1GCR3_PDRBVT_MASK (0x400000U) #define DDRPHY_DX1GCR3_PDRBVT_SHIFT (22U) /*! PDRBVT - Power Down Receiver BDL VT Compensation */ #define DDRPHY_DX1GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_PDRBVT_SHIFT)) & DDRPHY_DX1GCR3_PDRBVT_MASK) #define DDRPHY_DX1GCR3_RGSLVT_MASK (0x800000U) #define DDRPHY_DX1GCR3_RGSLVT_SHIFT (23U) /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation */ #define DDRPHY_DX1GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RGSLVT_SHIFT)) & DDRPHY_DX1GCR3_RGSLVT_MASK) #define DDRPHY_DX1GCR3_WLLVT_MASK (0x1000000U) #define DDRPHY_DX1GCR3_WLLVT_SHIFT (24U) /*! WLLVT - Write Leveling LCDL Delay VT Compensation */ #define DDRPHY_DX1GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WLLVT_SHIFT)) & DDRPHY_DX1GCR3_WLLVT_MASK) #define DDRPHY_DX1GCR3_WDLVT_MASK (0x2000000U) #define DDRPHY_DX1GCR3_WDLVT_SHIFT (25U) /*! WDLVT - Write DQ LCDL Delay VT Compensation */ #define DDRPHY_DX1GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDLVT_SHIFT)) & DDRPHY_DX1GCR3_WDLVT_MASK) #define DDRPHY_DX1GCR3_RDLVT_MASK (0x4000000U) #define DDRPHY_DX1GCR3_RDLVT_SHIFT (26U) /*! RDLVT - Read DQS LCDL Delay VT Compensation */ #define DDRPHY_DX1GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RDLVT_SHIFT)) & DDRPHY_DX1GCR3_RDLVT_MASK) #define DDRPHY_DX1GCR3_RGLVT_MASK (0x8000000U) #define DDRPHY_DX1GCR3_RGLVT_SHIFT (27U) /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation */ #define DDRPHY_DX1GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RGLVT_SHIFT)) & DDRPHY_DX1GCR3_RGLVT_MASK) #define DDRPHY_DX1GCR3_WDBVT_MASK (0x10000000U) #define DDRPHY_DX1GCR3_WDBVT_SHIFT (28U) /*! WDBVT - Write Data BDL VT Compensation */ #define DDRPHY_DX1GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDBVT_SHIFT)) & DDRPHY_DX1GCR3_WDBVT_MASK) #define DDRPHY_DX1GCR3_RDBVT_MASK (0x20000000U) #define DDRPHY_DX1GCR3_RDBVT_SHIFT (29U) /*! RDBVT - Read Data BDL VT Compensation */ #define DDRPHY_DX1GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RDBVT_SHIFT)) & DDRPHY_DX1GCR3_RDBVT_MASK) #define DDRPHY_DX1GCR3_TEBVT_MASK (0x40000000U) #define DDRPHY_DX1GCR3_TEBVT_SHIFT (30U) /*! TEBVT - Termination Enable BDL VT Compensation */ #define DDRPHY_DX1GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_TEBVT_SHIFT)) & DDRPHY_DX1GCR3_TEBVT_MASK) #define DDRPHY_DX1GCR3_OEBVT_MASK (0x80000000U) #define DDRPHY_DX1GCR3_OEBVT_SHIFT (31U) /*! OEBVT - Output Enable BDL VT Compensation */ #define DDRPHY_DX1GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_OEBVT_SHIFT)) & DDRPHY_DX1GCR3_OEBVT_MASK) /*! @} */ /*! @name DX1GCR4 - DATX8 n General Configuration Register 4 */ /*! @{ */ #define DDRPHY_DX1GCR4_DXREFIMON_MASK (0x3U) #define DDRPHY_DX1GCR4_DXREFIMON_SHIFT (0U) /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX1GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX1GCR4_DXREFIMON_MASK) #define DDRPHY_DX1GCR4_DXREFIEN_MASK (0x3CU) #define DDRPHY_DX1GCR4_DXREFIEN_SHIFT (2U) /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX1GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFIEN_MASK) #define DDRPHY_DX1GCR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1GCR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX1GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR4_RESERVED_7_6_MASK) #define DDRPHY_DX1GCR4_DXREFSSEL_MASK (0x7F00U) #define DDRPHY_DX1GCR4_DXREFSSEL_SHIFT (8U) /*! DXREFSSEL - Byte Lane Single-End VREF Select */ #define DDRPHY_DX1GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX1GCR4_DXREFSSEL_MASK) #define DDRPHY_DX1GCR4_DXREFSSELRANGE_MASK (0x8000U) #define DDRPHY_DX1GCR4_DXREFSSELRANGE_SHIFT (15U) /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select */ #define DDRPHY_DX1GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX1GCR4_DXREFSSELRANGE_MASK) #define DDRPHY_DX1GCR4_DXREFESEL_MASK (0x7F0000U) #define DDRPHY_DX1GCR4_DXREFESEL_SHIFT (16U) /*! DXREFESEL - Byte Lane External VREF Select */ #define DDRPHY_DX1GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX1GCR4_DXREFESEL_MASK) #define DDRPHY_DX1GCR4_DXREFESELRANGE_MASK (0x800000U) #define DDRPHY_DX1GCR4_DXREFESELRANGE_SHIFT (23U) /*! DXREFESELRANGE - External VREF generator REFSEL range select */ #define DDRPHY_DX1GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX1GCR4_DXREFESELRANGE_MASK) #define DDRPHY_DX1GCR4_RESERVED_24_MASK (0x1000000U) #define DDRPHY_DX1GCR4_RESERVED_24_SHIFT (24U) /*! RESERVED_24 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX1GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX1GCR4_RESERVED_24_MASK) #define DDRPHY_DX1GCR4_DXREFSEN_MASK (0x2000000U) #define DDRPHY_DX1GCR4_DXREFSEN_SHIFT (25U) /*! DXREFSEN - Byte Lane Single-End VREF Enable */ #define DDRPHY_DX1GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFSEN_MASK) #define DDRPHY_DX1GCR4_DXREFEEN_MASK (0xC000000U) #define DDRPHY_DX1GCR4_DXREFEEN_SHIFT (26U) /*! DXREFEEN - Byte Lane Internal VREF Enable */ #define DDRPHY_DX1GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFEEN_MASK) #define DDRPHY_DX1GCR4_DXREFPEN_MASK (0x10000000U) #define DDRPHY_DX1GCR4_DXREFPEN_SHIFT (28U) /*! DXREFPEN - Byte Lane VREF Pad Enable */ #define DDRPHY_DX1GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFPEN_MASK) #define DDRPHY_DX1GCR4_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DX1GCR4_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs) */ #define DDRPHY_DX1GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX1GCR4_RESERVED_31_29_MASK) /*! @} */ /*! @name DX1GCR5 - DATX8 n General Configuration Register 5 */ /*! @{ */ #define DDRPHY_DX1GCR5_DXREFISELR0_MASK (0x7FU) #define DDRPHY_DX1GCR5_DXREFISELR0_SHIFT (0U) /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0 */ #define DDRPHY_DX1GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR0_MASK) #define DDRPHY_DX1GCR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX1GCR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX1GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_7_MASK) #define DDRPHY_DX1GCR5_DXREFISELR1_MASK (0x7F00U) #define DDRPHY_DX1GCR5_DXREFISELR1_SHIFT (8U) /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1 */ #define DDRPHY_DX1GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR1_MASK) #define DDRPHY_DX1GCR5_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX1GCR5_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX1GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_15_MASK) #define DDRPHY_DX1GCR5_DXREFISELR2_MASK (0x7F0000U) #define DDRPHY_DX1GCR5_DXREFISELR2_SHIFT (16U) /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2 */ #define DDRPHY_DX1GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR2_MASK) #define DDRPHY_DX1GCR5_RESERVED_23_MASK (0x800000U) #define DDRPHY_DX1GCR5_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX1GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_23_MASK) #define DDRPHY_DX1GCR5_DXREFISELR3_MASK (0x7F000000U) #define DDRPHY_DX1GCR5_DXREFISELR3_SHIFT (24U) /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3 */ #define DDRPHY_DX1GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR3_MASK) #define DDRPHY_DX1GCR5_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX1GCR5_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX1GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_31_MASK) /*! @} */ /*! @name DX1GCR6 - DATX8 n General Configuration Register 6 */ /*! @{ */ #define DDRPHY_DX1GCR6_DXDQVREFR0_MASK (0x3FU) #define DDRPHY_DX1GCR6_DXDQVREFR0_SHIFT (0U) /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0 */ #define DDRPHY_DX1GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR0_MASK) #define DDRPHY_DX1GCR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1GCR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX1GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_7_6_MASK) #define DDRPHY_DX1GCR6_DXDQVREFR1_MASK (0x3F00U) #define DDRPHY_DX1GCR6_DXDQVREFR1_SHIFT (8U) /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1 */ #define DDRPHY_DX1GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR1_MASK) #define DDRPHY_DX1GCR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1GCR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX1GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_15_14_MASK) #define DDRPHY_DX1GCR6_DXDQVREFR2_MASK (0x3F0000U) #define DDRPHY_DX1GCR6_DXDQVREFR2_SHIFT (16U) /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2 */ #define DDRPHY_DX1GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR2_MASK) #define DDRPHY_DX1GCR6_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX1GCR6_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX1GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_23_22_MASK) #define DDRPHY_DX1GCR6_DXDQVREFR3_MASK (0x3F000000U) #define DDRPHY_DX1GCR6_DXDQVREFR3_SHIFT (24U) /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3 */ #define DDRPHY_DX1GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR3_MASK) #define DDRPHY_DX1GCR6_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX1GCR6_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX1GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_31_30_MASK) /*! @} */ /*! @name DX1GCR7 - DATX8 n General Configuration Register 7 */ /*! @{ */ #define DDRPHY_DX1GCR7_DCALSVAL_MASK (0x1FFU) #define DDRPHY_DX1GCR7_DCALSVAL_SHIFT (0U) /*! DCALSVAL - DDL Calibration Starting Value */ #define DDRPHY_DX1GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX1GCR7_DCALSVAL_MASK) #define DDRPHY_DX1GCR7_DCALTYPE_MASK (0x200U) #define DDRPHY_DX1GCR7_DCALTYPE_SHIFT (9U) /*! DCALTYPE - DDL Calibration Type */ #define DDRPHY_DX1GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX1GCR7_DCALTYPE_MASK) #define DDRPHY_DX1GCR7_RESERVED_17_10_MASK (0x3FC00U) #define DDRPHY_DX1GCR7_RESERVED_17_10_SHIFT (10U) /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX1GCR7_RESERVED_17_10_MASK) #define DDRPHY_DX1GCR7_RESERVED_18_MASK (0x40000U) #define DDRPHY_DX1GCR7_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX1GCR7_RESERVED_18_MASK) #define DDRPHY_DX1GCR7_RESERVED_31_19_MASK (0xFFF80000U) #define DDRPHY_DX1GCR7_RESERVED_31_19_SHIFT (19U) /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX1GCR7_RESERVED_31_19_MASK) /*! @} */ /*! @name DX1GCR8 - DATX8 n General Configuration Register 8 */ /*! @{ */ #define DDRPHY_DX1GCR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX1GCR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_5_0_MASK) #define DDRPHY_DX1GCR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1GCR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_7_6_MASK) #define DDRPHY_DX1GCR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX1GCR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_13_8_MASK) #define DDRPHY_DX1GCR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1GCR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_15_14_MASK) #define DDRPHY_DX1GCR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX1GCR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_21_16_MASK) #define DDRPHY_DX1GCR8_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX1GCR8_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_23_22_MASK) #define DDRPHY_DX1GCR8_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX1GCR8_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_29_24_MASK) #define DDRPHY_DX1GCR8_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX1GCR8_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_31_30_MASK) /*! @} */ /*! @name DX1GCR9 - DATX8 n General Configuration Register 9 */ /*! @{ */ #define DDRPHY_DX1GCR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX1GCR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_5_0_MASK) #define DDRPHY_DX1GCR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1GCR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_7_6_MASK) #define DDRPHY_DX1GCR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX1GCR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_13_8_MASK) #define DDRPHY_DX1GCR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1GCR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_15_14_MASK) #define DDRPHY_DX1GCR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX1GCR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_21_16_MASK) #define DDRPHY_DX1GCR9_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX1GCR9_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_23_22_MASK) #define DDRPHY_DX1GCR9_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX1GCR9_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_29_24_MASK) #define DDRPHY_DX1GCR9_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX1GCR9_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_31_30_MASK) /*! @} */ /*! @name DX1DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */ /*! @{ */ #define DDRPHY_DX1DQMAP0_DQ0MAP_MASK (0xFU) #define DDRPHY_DX1DQMAP0_DQ0MAP_SHIFT (0U) /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index */ #define DDRPHY_DX1DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ0MAP_MASK) #define DDRPHY_DX1DQMAP0_DQ1MAP_MASK (0xF0U) #define DDRPHY_DX1DQMAP0_DQ1MAP_SHIFT (4U) /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index */ #define DDRPHY_DX1DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ1MAP_MASK) #define DDRPHY_DX1DQMAP0_DQ2MAP_MASK (0xF00U) #define DDRPHY_DX1DQMAP0_DQ2MAP_SHIFT (8U) /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index */ #define DDRPHY_DX1DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ2MAP_MASK) #define DDRPHY_DX1DQMAP0_DQ3MAP_MASK (0xF000U) #define DDRPHY_DX1DQMAP0_DQ3MAP_SHIFT (12U) /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index */ #define DDRPHY_DX1DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ3MAP_MASK) #define DDRPHY_DX1DQMAP0_DQ4MAP_MASK (0xF0000U) #define DDRPHY_DX1DQMAP0_DQ4MAP_SHIFT (16U) /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index */ #define DDRPHY_DX1DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ4MAP_MASK) #define DDRPHY_DX1DQMAP0_RESERVED_30_20_MASK (0x7FF00000U) #define DDRPHY_DX1DQMAP0_RESERVED_30_20_SHIFT (20U) /*! RESERVED_30_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX1DQMAP0_RESERVED_30_20_MASK) #define DDRPHY_DX1DQMAP0_MAPOK_MASK (0x80000000U) #define DDRPHY_DX1DQMAP0_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX1DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX1DQMAP0_MAPOK_MASK) /*! @} */ /*! @name DX1DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */ /*! @{ */ #define DDRPHY_DX1DQMAP1_DQ5MAP_MASK (0xFU) #define DDRPHY_DX1DQMAP1_DQ5MAP_SHIFT (0U) /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index */ #define DDRPHY_DX1DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX1DQMAP1_DQ5MAP_MASK) #define DDRPHY_DX1DQMAP1_DQ6MAP_MASK (0xF0U) #define DDRPHY_DX1DQMAP1_DQ6MAP_SHIFT (4U) /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index */ #define DDRPHY_DX1DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX1DQMAP1_DQ6MAP_MASK) #define DDRPHY_DX1DQMAP1_DQ7MAP_MASK (0xF00U) #define DDRPHY_DX1DQMAP1_DQ7MAP_SHIFT (8U) /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index */ #define DDRPHY_DX1DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX1DQMAP1_DQ7MAP_MASK) #define DDRPHY_DX1DQMAP1_DMMAP_MASK (0xF000U) #define DDRPHY_DX1DQMAP1_DMMAP_SHIFT (12U) /*! DMMAP - DM bit DATX8 slice mapping index */ #define DDRPHY_DX1DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX1DQMAP1_DMMAP_MASK) #define DDRPHY_DX1DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U) #define DDRPHY_DX1DQMAP1_RESERVED_30_16_SHIFT (16U) /*! RESERVED_30_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX1DQMAP1_RESERVED_30_16_MASK) #define DDRPHY_DX1DQMAP1_MAPOK_MASK (0x80000000U) #define DDRPHY_DX1DQMAP1_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX1DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX1DQMAP1_MAPOK_MASK) /*! @} */ /*! @name DX1BDLR0 - DATX8 n Bit Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX1BDLR0_DQ0WBD_MASK (0x3FU) #define DDRPHY_DX1BDLR0_DQ0WBD_SHIFT (0U) /*! DQ0WBD - DQ0 Write Bit Delay */ #define DDRPHY_DX1BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ0WBD_MASK) #define DDRPHY_DX1BDLR0_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1BDLR0_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_7_6_MASK) #define DDRPHY_DX1BDLR0_DQ1WBD_MASK (0x3F00U) #define DDRPHY_DX1BDLR0_DQ1WBD_SHIFT (8U) /*! DQ1WBD - DQ1 Write Bit Delay */ #define DDRPHY_DX1BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ1WBD_MASK) #define DDRPHY_DX1BDLR0_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1BDLR0_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_15_14_MASK) #define DDRPHY_DX1BDLR0_DQ2WBD_MASK (0x3F0000U) #define DDRPHY_DX1BDLR0_DQ2WBD_SHIFT (16U) /*! DQ2WBD - DQ2 Write Bit Delay */ #define DDRPHY_DX1BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ2WBD_MASK) #define DDRPHY_DX1BDLR0_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX1BDLR0_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_23_22_MASK) #define DDRPHY_DX1BDLR0_DQ3WBD_MASK (0x3F000000U) #define DDRPHY_DX1BDLR0_DQ3WBD_SHIFT (24U) /*! DQ3WBD - DQ3 Write Bit Delay */ #define DDRPHY_DX1BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ3WBD_MASK) #define DDRPHY_DX1BDLR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX1BDLR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_31_30_MASK) /*! @} */ /*! @name DX1BDLR1 - DATX8 n Bit Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX1BDLR1_DQ4WBD_MASK (0x3FU) #define DDRPHY_DX1BDLR1_DQ4WBD_SHIFT (0U) /*! DQ4WBD - DQ4 Write Bit Delay */ #define DDRPHY_DX1BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ4WBD_MASK) #define DDRPHY_DX1BDLR1_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1BDLR1_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_7_6_MASK) #define DDRPHY_DX1BDLR1_DQ5WBD_MASK (0x3F00U) #define DDRPHY_DX1BDLR1_DQ5WBD_SHIFT (8U) /*! DQ5WBD - DQ5 Write Bit Delay */ #define DDRPHY_DX1BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ5WBD_MASK) #define DDRPHY_DX1BDLR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1BDLR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_15_14_MASK) #define DDRPHY_DX1BDLR1_DQ6WBD_MASK (0x3F0000U) #define DDRPHY_DX1BDLR1_DQ6WBD_SHIFT (16U) /*! DQ6WBD - DQ6 Write Bit Delay */ #define DDRPHY_DX1BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ6WBD_MASK) #define DDRPHY_DX1BDLR1_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX1BDLR1_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_23_22_MASK) #define DDRPHY_DX1BDLR1_DQ7WBD_MASK (0x3F000000U) #define DDRPHY_DX1BDLR1_DQ7WBD_SHIFT (24U) /*! DQ7WBD - DQ7 Write Bit Delay */ #define DDRPHY_DX1BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ7WBD_MASK) #define DDRPHY_DX1BDLR1_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX1BDLR1_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_31_30_MASK) /*! @} */ /*! @name DX1BDLR2 - DATX8 n Bit Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX1BDLR2_DMWBD_MASK (0x3FU) #define DDRPHY_DX1BDLR2_DMWBD_SHIFT (0U) /*! DMWBD - DM Write Bit Delay */ #define DDRPHY_DX1BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DMWBD_SHIFT)) & DDRPHY_DX1BDLR2_DMWBD_MASK) #define DDRPHY_DX1BDLR2_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1BDLR2_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_7_6_MASK) #define DDRPHY_DX1BDLR2_DSWBD_MASK (0x3F00U) #define DDRPHY_DX1BDLR2_DSWBD_SHIFT (8U) /*! DSWBD - DQS Write Bit Delay */ #define DDRPHY_DX1BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DSWBD_SHIFT)) & DDRPHY_DX1BDLR2_DSWBD_MASK) #define DDRPHY_DX1BDLR2_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1BDLR2_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_15_14_MASK) #define DDRPHY_DX1BDLR2_DSOEBD_MASK (0x3F0000U) #define DDRPHY_DX1BDLR2_DSOEBD_SHIFT (16U) /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay */ #define DDRPHY_DX1BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX1BDLR2_DSOEBD_MASK) #define DDRPHY_DX1BDLR2_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX1BDLR2_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_23_22_MASK) #define DDRPHY_DX1BDLR2_DSNWBD_MASK (0x3F000000U) #define DDRPHY_DX1BDLR2_DSNWBD_SHIFT (24U) /*! DSNWBD - DQSN Write Bit Delay */ #define DDRPHY_DX1BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX1BDLR2_DSNWBD_MASK) #define DDRPHY_DX1BDLR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX1BDLR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_31_30_MASK) /*! @} */ /*! @name DX1BDLR3 - DATX8 n Bit Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX1BDLR3_DQ0RBD_MASK (0x3FU) #define DDRPHY_DX1BDLR3_DQ0RBD_SHIFT (0U) /*! DQ0RBD - DQ0 Read Bit Delay */ #define DDRPHY_DX1BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ0RBD_MASK) #define DDRPHY_DX1BDLR3_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1BDLR3_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_7_6_MASK) #define DDRPHY_DX1BDLR3_DQ1RBD_MASK (0x3F00U) #define DDRPHY_DX1BDLR3_DQ1RBD_SHIFT (8U) /*! DQ1RBD - DQ1 Read Bit Delay */ #define DDRPHY_DX1BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ1RBD_MASK) #define DDRPHY_DX1BDLR3_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1BDLR3_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_15_14_MASK) #define DDRPHY_DX1BDLR3_DQ2RBD_MASK (0x3F0000U) #define DDRPHY_DX1BDLR3_DQ2RBD_SHIFT (16U) /*! DQ2RBD - DQ2 Read Bit Delay */ #define DDRPHY_DX1BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ2RBD_MASK) #define DDRPHY_DX1BDLR3_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX1BDLR3_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_23_22_MASK) #define DDRPHY_DX1BDLR3_DQ3RBD_MASK (0x3F000000U) #define DDRPHY_DX1BDLR3_DQ3RBD_SHIFT (24U) /*! DQ3RBD - DQ3 Read Bit Delay */ #define DDRPHY_DX1BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ3RBD_MASK) #define DDRPHY_DX1BDLR3_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX1BDLR3_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_31_30_MASK) /*! @} */ /*! @name DX1BDLR4 - DATX8 n Bit Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX1BDLR4_DQ4RBD_MASK (0x3FU) #define DDRPHY_DX1BDLR4_DQ4RBD_SHIFT (0U) /*! DQ4RBD - DQ4 Read Bit Delay */ #define DDRPHY_DX1BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ4RBD_MASK) #define DDRPHY_DX1BDLR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1BDLR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_7_6_MASK) #define DDRPHY_DX1BDLR4_DQ5RBD_MASK (0x3F00U) #define DDRPHY_DX1BDLR4_DQ5RBD_SHIFT (8U) /*! DQ5RBD - DQ5 Read Bit Delay */ #define DDRPHY_DX1BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ5RBD_MASK) #define DDRPHY_DX1BDLR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1BDLR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_15_14_MASK) #define DDRPHY_DX1BDLR4_DQ6RBD_MASK (0x3F0000U) #define DDRPHY_DX1BDLR4_DQ6RBD_SHIFT (16U) /*! DQ6RBD - DQ6 Read Bit Delay */ #define DDRPHY_DX1BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ6RBD_MASK) #define DDRPHY_DX1BDLR4_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX1BDLR4_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_23_22_MASK) #define DDRPHY_DX1BDLR4_DQ7RBD_MASK (0x3F000000U) #define DDRPHY_DX1BDLR4_DQ7RBD_SHIFT (24U) /*! DQ7RBD - DQ7 Read Bit Delay */ #define DDRPHY_DX1BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ7RBD_MASK) #define DDRPHY_DX1BDLR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX1BDLR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_31_30_MASK) /*! @} */ /*! @name DX1BDLR5 - DATX8 n Bit Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX1BDLR5_DMRBD_MASK (0x3FU) #define DDRPHY_DX1BDLR5_DMRBD_SHIFT (0U) /*! DMRBD - DM Read Bit Delay */ #define DDRPHY_DX1BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR5_DMRBD_SHIFT)) & DDRPHY_DX1BDLR5_DMRBD_MASK) #define DDRPHY_DX1BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U) #define DDRPHY_DX1BDLR5_RESERVED_31_6_SHIFT (6U) /*! RESERVED_31_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX1BDLR5_RESERVED_31_6_MASK) /*! @} */ /*! @name DX1BDLR6 - DATX8 n Bit Delay Line Register 6 */ /*! @{ */ #define DDRPHY_DX1BDLR6_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_DX1BDLR6_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX1BDLR6_RESERVED_7_0_MASK) #define DDRPHY_DX1BDLR6_PDRBD_MASK (0x3F00U) #define DDRPHY_DX1BDLR6_PDRBD_SHIFT (8U) /*! PDRBD - Power down receiver Bit Delay */ #define DDRPHY_DX1BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_PDRBD_SHIFT)) & DDRPHY_DX1BDLR6_PDRBD_MASK) #define DDRPHY_DX1BDLR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1BDLR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR6_RESERVED_15_14_MASK) #define DDRPHY_DX1BDLR6_TERBD_MASK (0x3F0000U) #define DDRPHY_DX1BDLR6_TERBD_SHIFT (16U) /*! TERBD - Termination Enable Bit Delay */ #define DDRPHY_DX1BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_TERBD_SHIFT)) & DDRPHY_DX1BDLR6_TERBD_MASK) #define DDRPHY_DX1BDLR6_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX1BDLR6_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR6_RESERVED_31_22_MASK) /*! @} */ /*! @name DX1BDLR7 - DATX8 n Bit Delay Line Register 7 */ /*! @{ */ #define DDRPHY_DX1BDLR7_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX1BDLR7_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_5_0_MASK) #define DDRPHY_DX1BDLR7_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1BDLR7_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_7_6_MASK) #define DDRPHY_DX1BDLR7_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX1BDLR7_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_13_8_MASK) #define DDRPHY_DX1BDLR7_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1BDLR7_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_15_14_MASK) #define DDRPHY_DX1BDLR7_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX1BDLR7_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_21_16_MASK) #define DDRPHY_DX1BDLR7_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX1BDLR7_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_31_22_MASK) /*! @} */ /*! @name DX1BDLR8 - DATX8 n Bit Delay Line Register 8 */ /*! @{ */ #define DDRPHY_DX1BDLR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX1BDLR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_5_0_MASK) #define DDRPHY_DX1BDLR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1BDLR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_7_6_MASK) #define DDRPHY_DX1BDLR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX1BDLR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_13_8_MASK) #define DDRPHY_DX1BDLR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1BDLR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_15_14_MASK) #define DDRPHY_DX1BDLR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX1BDLR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_21_16_MASK) #define DDRPHY_DX1BDLR8_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX1BDLR8_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_31_22_MASK) /*! @} */ /*! @name DX1BDLR9 - DATX8 n Bit Delay Line Register 9 */ /*! @{ */ #define DDRPHY_DX1BDLR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX1BDLR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_5_0_MASK) #define DDRPHY_DX1BDLR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX1BDLR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_7_6_MASK) #define DDRPHY_DX1BDLR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX1BDLR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_13_8_MASK) #define DDRPHY_DX1BDLR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX1BDLR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_15_14_MASK) #define DDRPHY_DX1BDLR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX1BDLR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_21_16_MASK) #define DDRPHY_DX1BDLR9_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX1BDLR9_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_31_22_MASK) /*! @} */ /*! @name DX1LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX1LCDLR0_WLD_MASK (0x1FFU) #define DDRPHY_DX1LCDLR0_WLD_SHIFT (0U) /*! WLD - Write Leveling Delay */ #define DDRPHY_DX1LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_WLD_SHIFT)) & DDRPHY_DX1LCDLR0_WLD_MASK) #define DDRPHY_DX1LCDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX1LCDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX1LCDLR0_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX1LCDLR0_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR0_RESERVED_24_16_MASK) #define DDRPHY_DX1LCDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX1LCDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX1LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX1LCDLR1_WDQD_MASK (0x1FFU) #define DDRPHY_DX1LCDLR1_WDQD_SHIFT (0U) /*! WDQD - Write Data Delay */ #define DDRPHY_DX1LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_WDQD_SHIFT)) & DDRPHY_DX1LCDLR1_WDQD_MASK) #define DDRPHY_DX1LCDLR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX1LCDLR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR1_RESERVED_15_9_MASK) #define DDRPHY_DX1LCDLR1_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX1LCDLR1_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR1_RESERVED_24_16_MASK) #define DDRPHY_DX1LCDLR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX1LCDLR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX1LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX1LCDLR2_DQSGD_MASK (0x1FFU) #define DDRPHY_DX1LCDLR2_DQSGD_SHIFT (0U) /*! DQSGD - Read DQS Gating Delay */ #define DDRPHY_DX1LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX1LCDLR2_DQSGD_MASK) #define DDRPHY_DX1LCDLR2_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX1LCDLR2_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR2_RESERVED_15_9_MASK) #define DDRPHY_DX1LCDLR2_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX1LCDLR2_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR2_RESERVED_24_16_MASK) #define DDRPHY_DX1LCDLR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX1LCDLR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR2_RESERVED_31_25_MASK) /*! @} */ /*! @name DX1LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX1LCDLR3_RDQSD_MASK (0x1FFU) #define DDRPHY_DX1LCDLR3_RDQSD_SHIFT (0U) /*! RDQSD - Read DQS Delay */ #define DDRPHY_DX1LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX1LCDLR3_RDQSD_MASK) #define DDRPHY_DX1LCDLR3_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX1LCDLR3_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR3_RESERVED_15_9_MASK) #define DDRPHY_DX1LCDLR3_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX1LCDLR3_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR3_RESERVED_24_16_MASK) #define DDRPHY_DX1LCDLR3_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX1LCDLR3_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR3_RESERVED_31_25_MASK) /*! @} */ /*! @name DX1LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX1LCDLR4_RDQSND_MASK (0x1FFU) #define DDRPHY_DX1LCDLR4_RDQSND_SHIFT (0U) /*! RDQSND - Read DQSN Delay */ #define DDRPHY_DX1LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX1LCDLR4_RDQSND_MASK) #define DDRPHY_DX1LCDLR4_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX1LCDLR4_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR4_RESERVED_15_9_MASK) #define DDRPHY_DX1LCDLR4_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX1LCDLR4_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR4_RESERVED_24_16_MASK) #define DDRPHY_DX1LCDLR4_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX1LCDLR4_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR4_RESERVED_31_25_MASK) /*! @} */ /*! @name DX1LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX1LCDLR5_DQSGSD_MASK (0x1FFU) #define DDRPHY_DX1LCDLR5_DQSGSD_SHIFT (0U) /*! DQSGSD - DQS Gating Status Delay */ #define DDRPHY_DX1LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX1LCDLR5_DQSGSD_MASK) #define DDRPHY_DX1LCDLR5_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX1LCDLR5_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR5_RESERVED_15_9_MASK) #define DDRPHY_DX1LCDLR5_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX1LCDLR5_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR5_RESERVED_24_16_MASK) #define DDRPHY_DX1LCDLR5_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX1LCDLR5_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR5_RESERVED_31_25_MASK) /*! @} */ /*! @name DX1MDLR0 - DATX8 n Master Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX1MDLR0_IPRD_MASK (0x1FFU) #define DDRPHY_DX1MDLR0_IPRD_SHIFT (0U) /*! IPRD - Initial Period */ #define DDRPHY_DX1MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_IPRD_SHIFT)) & DDRPHY_DX1MDLR0_IPRD_MASK) #define DDRPHY_DX1MDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX1MDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX1MDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX1MDLR0_TPRD_MASK (0x1FF0000U) #define DDRPHY_DX1MDLR0_TPRD_SHIFT (16U) /*! TPRD - Target Period */ #define DDRPHY_DX1MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_TPRD_SHIFT)) & DDRPHY_DX1MDLR0_TPRD_MASK) #define DDRPHY_DX1MDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX1MDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX1MDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX1MDLR1 - DATX8 n Master Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX1MDLR1_MDLD_MASK (0x1FFU) #define DDRPHY_DX1MDLR1_MDLD_SHIFT (0U) /*! MDLD - MDL Delay */ #define DDRPHY_DX1MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR1_MDLD_SHIFT)) & DDRPHY_DX1MDLR1_MDLD_MASK) #define DDRPHY_DX1MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U) #define DDRPHY_DX1MDLR1_RESERVED_31_9_SHIFT (9U) /*! RESERVED_31_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX1MDLR1_RESERVED_31_9_MASK) /*! @} */ /*! @name DX1GTR0 - DATX8 n General Timing Register 0 */ /*! @{ */ #define DDRPHY_DX1GTR0_DGSL_MASK (0x1FU) #define DDRPHY_DX1GTR0_DGSL_SHIFT (0U) /*! DGSL - DQS Gating System Latency */ #define DDRPHY_DX1GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_DGSL_SHIFT)) & DDRPHY_DX1GTR0_DGSL_MASK) #define DDRPHY_DX1GTR0_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DX1GTR0_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_7_5_MASK) #define DDRPHY_DX1GTR0_RESERVED_12_8_MASK (0x1F00U) #define DDRPHY_DX1GTR0_RESERVED_12_8_SHIFT (8U) /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_12_8_MASK) #define DDRPHY_DX1GTR0_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_DX1GTR0_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_15_13_MASK) #define DDRPHY_DX1GTR0_WLSL_MASK (0xF0000U) #define DDRPHY_DX1GTR0_WLSL_SHIFT (16U) /*! WLSL - Write Leveling System Latency */ #define DDRPHY_DX1GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_WLSL_SHIFT)) & DDRPHY_DX1GTR0_WLSL_MASK) #define DDRPHY_DX1GTR0_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX1GTR0_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX1GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_23_20_MASK) #define DDRPHY_DX1GTR0_WDQSL_MASK (0x7000000U) #define DDRPHY_DX1GTR0_WDQSL_SHIFT (24U) /*! WDQSL - DQ Write Path Latency Pipeline */ #define DDRPHY_DX1GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_WDQSL_SHIFT)) & DDRPHY_DX1GTR0_WDQSL_MASK) #define DDRPHY_DX1GTR0_RESERVED_31_24_MASK (0xF8000000U) #define DDRPHY_DX1GTR0_RESERVED_31_24_SHIFT (27U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_31_24_MASK) /*! @} */ /*! @name DX1RSR0 - DATX8 n Rank Status Register 0 */ /*! @{ */ #define DDRPHY_DX1RSR0_QSGERR_MASK (0xFFFFU) #define DDRPHY_DX1RSR0_QSGERR_SHIFT (0U) /*! QSGERR - DQS Gate Training Error */ #define DDRPHY_DX1RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR0_QSGERR_SHIFT)) & DDRPHY_DX1RSR0_QSGERR_MASK) #define DDRPHY_DX1RSR0_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX1RSR0_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR0_RESERVED_31_16_MASK) /*! @} */ /*! @name DX1RSR1 - DATX8 n Rank Status Register 1 */ /*! @{ */ #define DDRPHY_DX1RSR1_RDLVLERR_MASK (0xFFFFU) #define DDRPHY_DX1RSR1_RDLVLERR_SHIFT (0U) /*! RDLVLERR - Read Leveling Error */ #define DDRPHY_DX1RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX1RSR1_RDLVLERR_MASK) #define DDRPHY_DX1RSR1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX1RSR1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR1_RESERVED_31_16_MASK) /*! @} */ /*! @name DX1RSR2 - DATX8 n Rank Status Register 2 */ /*! @{ */ #define DDRPHY_DX1RSR2_WLAWN_MASK (0xFFFFU) #define DDRPHY_DX1RSR2_WLAWN_SHIFT (0U) /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning */ #define DDRPHY_DX1RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR2_WLAWN_SHIFT)) & DDRPHY_DX1RSR2_WLAWN_MASK) #define DDRPHY_DX1RSR2_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX1RSR2_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR2_RESERVED_31_16_MASK) /*! @} */ /*! @name DX1RSR3 - DATX8 n Rank Status Register 3 */ /*! @{ */ #define DDRPHY_DX1RSR3_WLAERR_MASK (0xFFFFU) #define DDRPHY_DX1RSR3_WLAERR_SHIFT (0U) /*! WLAERR - Write Leveling Adjustment Error */ #define DDRPHY_DX1RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR3_WLAERR_SHIFT)) & DDRPHY_DX1RSR3_WLAERR_MASK) #define DDRPHY_DX1RSR3_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX1RSR3_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR3_RESERVED_31_16_MASK) /*! @} */ /*! @name DX1GSR0 - DATX8 n General Status Register 0 */ /*! @{ */ #define DDRPHY_DX1GSR0_WDQCAL_MASK (0x1U) #define DDRPHY_DX1GSR0_WDQCAL_SHIFT (0U) /*! WDQCAL - Write DQ Calibration */ #define DDRPHY_DX1GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WDQCAL_SHIFT)) & DDRPHY_DX1GSR0_WDQCAL_MASK) #define DDRPHY_DX1GSR0_RDQSCAL_MASK (0x2U) #define DDRPHY_DX1GSR0_RDQSCAL_SHIFT (1U) /*! RDQSCAL - Read DQS Calibration */ #define DDRPHY_DX1GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX1GSR0_RDQSCAL_MASK) #define DDRPHY_DX1GSR0_RDQSNCAL_MASK (0x4U) #define DDRPHY_DX1GSR0_RDQSNCAL_SHIFT (2U) /*! RDQSNCAL - Read DQS# Calibration */ #define DDRPHY_DX1GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX1GSR0_RDQSNCAL_MASK) #define DDRPHY_DX1GSR0_GDQSCAL_MASK (0x8U) #define DDRPHY_DX1GSR0_GDQSCAL_SHIFT (3U) /*! GDQSCAL - Read DQS gating Calibration */ #define DDRPHY_DX1GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX1GSR0_GDQSCAL_MASK) #define DDRPHY_DX1GSR0_WLCAL_MASK (0x10U) #define DDRPHY_DX1GSR0_WLCAL_SHIFT (4U) /*! WLCAL - Write Leveling Calibration */ #define DDRPHY_DX1GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLCAL_SHIFT)) & DDRPHY_DX1GSR0_WLCAL_MASK) #define DDRPHY_DX1GSR0_WLDONE_MASK (0x20U) #define DDRPHY_DX1GSR0_WLDONE_SHIFT (5U) /*! WLDONE - Write Leveling Done */ #define DDRPHY_DX1GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLDONE_SHIFT)) & DDRPHY_DX1GSR0_WLDONE_MASK) #define DDRPHY_DX1GSR0_WLERR_MASK (0x40U) #define DDRPHY_DX1GSR0_WLERR_SHIFT (6U) /*! WLERR - Write Leveling Error */ #define DDRPHY_DX1GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLERR_SHIFT)) & DDRPHY_DX1GSR0_WLERR_MASK) #define DDRPHY_DX1GSR0_WLPRD_MASK (0xFF80U) #define DDRPHY_DX1GSR0_WLPRD_SHIFT (7U) /*! WLPRD - Write Leveling Period */ #define DDRPHY_DX1GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLPRD_SHIFT)) & DDRPHY_DX1GSR0_WLPRD_MASK) #define DDRPHY_DX1GSR0_DPLOCK_MASK (0x10000U) #define DDRPHY_DX1GSR0_DPLOCK_SHIFT (16U) /*! DPLOCK - DATX8 PLL Lock */ #define DDRPHY_DX1GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_DPLOCK_SHIFT)) & DDRPHY_DX1GSR0_DPLOCK_MASK) #define DDRPHY_DX1GSR0_GDQSPRD_MASK (0x3FE0000U) #define DDRPHY_DX1GSR0_GDQSPRD_SHIFT (17U) /*! GDQSPRD - Read DQS gating Period */ #define DDRPHY_DX1GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX1GSR0_GDQSPRD_MASK) #define DDRPHY_DX1GSR0_RESERVED_29_26_MASK (0x3C000000U) #define DDRPHY_DX1GSR0_RESERVED_29_26_SHIFT (26U) /*! RESERVED_29_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX1GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX1GSR0_RESERVED_29_26_MASK) #define DDRPHY_DX1GSR0_WLDQ_MASK (0x40000000U) #define DDRPHY_DX1GSR0_WLDQ_SHIFT (30U) /*! WLDQ - Write Leveling DQ Status */ #define DDRPHY_DX1GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLDQ_SHIFT)) & DDRPHY_DX1GSR0_WLDQ_MASK) #define DDRPHY_DX1GSR0_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX1GSR0_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX1GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX1GSR0_RESERVED_31_MASK) /*! @} */ /*! @name DX1GSR1 - DATX8 n General Status Register 1 */ /*! @{ */ #define DDRPHY_DX1GSR1_DLTDONE_MASK (0x1U) #define DDRPHY_DX1GSR1_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done */ #define DDRPHY_DX1GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR1_DLTDONE_SHIFT)) & DDRPHY_DX1GSR1_DLTDONE_MASK) #define DDRPHY_DX1GSR1_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_DX1GSR1_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code */ #define DDRPHY_DX1GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR1_DLTCODE_SHIFT)) & DDRPHY_DX1GSR1_DLTCODE_MASK) #define DDRPHY_DX1GSR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX1GSR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX1GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX1GSR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX1GSR2 - DATX8 n General Status Register 2 */ /*! @{ */ #define DDRPHY_DX1GSR2_RDERR_MASK (0x1U) #define DDRPHY_DX1GSR2_RDERR_SHIFT (0U) /*! RDERR - Read Bit Deskew Error */ #define DDRPHY_DX1GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_RDERR_SHIFT)) & DDRPHY_DX1GSR2_RDERR_MASK) #define DDRPHY_DX1GSR2_RDWN_MASK (0x2U) #define DDRPHY_DX1GSR2_RDWN_SHIFT (1U) /*! RDWN - Read Bit Deskew Warning */ #define DDRPHY_DX1GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_RDWN_SHIFT)) & DDRPHY_DX1GSR2_RDWN_MASK) #define DDRPHY_DX1GSR2_WDERR_MASK (0x4U) #define DDRPHY_DX1GSR2_WDERR_SHIFT (2U) /*! WDERR - Write Bit Deskew Error */ #define DDRPHY_DX1GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WDERR_SHIFT)) & DDRPHY_DX1GSR2_WDERR_MASK) #define DDRPHY_DX1GSR2_WDWN_MASK (0x8U) #define DDRPHY_DX1GSR2_WDWN_SHIFT (3U) /*! WDWN - Write Bit Deskew Warning */ #define DDRPHY_DX1GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WDWN_SHIFT)) & DDRPHY_DX1GSR2_WDWN_MASK) #define DDRPHY_DX1GSR2_REERR_MASK (0x10U) #define DDRPHY_DX1GSR2_REERR_SHIFT (4U) /*! REERR - Read Eye Centering Error */ #define DDRPHY_DX1GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_REERR_SHIFT)) & DDRPHY_DX1GSR2_REERR_MASK) #define DDRPHY_DX1GSR2_REWN_MASK (0x20U) #define DDRPHY_DX1GSR2_REWN_SHIFT (5U) /*! REWN - Read Eye Centering Warning */ #define DDRPHY_DX1GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_REWN_SHIFT)) & DDRPHY_DX1GSR2_REWN_MASK) #define DDRPHY_DX1GSR2_WEERR_MASK (0x40U) #define DDRPHY_DX1GSR2_WEERR_SHIFT (6U) /*! WEERR - Write Eye Centering Error */ #define DDRPHY_DX1GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WEERR_SHIFT)) & DDRPHY_DX1GSR2_WEERR_MASK) #define DDRPHY_DX1GSR2_WEWN_MASK (0x80U) #define DDRPHY_DX1GSR2_WEWN_SHIFT (7U) /*! WEWN - Write Eye Centering Warning */ #define DDRPHY_DX1GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WEWN_SHIFT)) & DDRPHY_DX1GSR2_WEWN_MASK) #define DDRPHY_DX1GSR2_ESTAT_MASK (0xF00U) #define DDRPHY_DX1GSR2_ESTAT_SHIFT (8U) /*! ESTAT - Error Status */ #define DDRPHY_DX1GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_ESTAT_SHIFT)) & DDRPHY_DX1GSR2_ESTAT_MASK) #define DDRPHY_DX1GSR2_DQS2DQERR_MASK (0xFF000U) #define DDRPHY_DX1GSR2_DQS2DQERR_SHIFT (12U) /*! DQS2DQERR - Write DQS2DQ Training Error */ #define DDRPHY_DX1GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX1GSR2_DQS2DQERR_MASK) #define DDRPHY_DX1GSR2_SRDERR_MASK (0x100000U) #define DDRPHY_DX1GSR2_SRDERR_SHIFT (20U) /*! SRDERR - Static Read Error */ #define DDRPHY_DX1GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_SRDERR_SHIFT)) & DDRPHY_DX1GSR2_SRDERR_MASK) #define DDRPHY_DX1GSR2_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX1GSR2_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX1GSR2_RESERVED_21_MASK) #define DDRPHY_DX1GSR2_GSDQSCAL_MASK (0x400000U) #define DDRPHY_DX1GSR2_GSDQSCAL_SHIFT (22U) /*! GSDQSCAL - Read DQS Gating Status Calibration */ #define DDRPHY_DX1GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX1GSR2_GSDQSCAL_MASK) #define DDRPHY_DX1GSR2_GSDQSPRD_MASK (0xFF800000U) #define DDRPHY_DX1GSR2_GSDQSPRD_SHIFT (23U) /*! GSDQSPRD - Read DQS gating Status Period */ #define DDRPHY_DX1GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX1GSR2_GSDQSPRD_MASK) /*! @} */ /*! @name DX1GSR3 - DATX8 n General Status Register 3 */ /*! @{ */ #define DDRPHY_DX1GSR3_SRDPC_MASK (0x3U) #define DDRPHY_DX1GSR3_SRDPC_SHIFT (0U) /*! SRDPC - Static Read Delay Pass Count */ #define DDRPHY_DX1GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_SRDPC_SHIFT)) & DDRPHY_DX1GSR3_SRDPC_MASK) #define DDRPHY_DX1GSR3_RESERVED_7_2_MASK (0xFCU) #define DDRPHY_DX1GSR3_RESERVED_7_2_SHIFT (2U) /*! RESERVED_7_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX1GSR3_RESERVED_7_2_MASK) #define DDRPHY_DX1GSR3_HVERR_MASK (0xF00U) #define DDRPHY_DX1GSR3_HVERR_SHIFT (8U) /*! HVERR - Host VREF Training Error */ #define DDRPHY_DX1GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_HVERR_SHIFT)) & DDRPHY_DX1GSR3_HVERR_MASK) #define DDRPHY_DX1GSR3_HVWRN_MASK (0xF000U) #define DDRPHY_DX1GSR3_HVWRN_SHIFT (12U) /*! HVWRN - Host VREF Training Warning */ #define DDRPHY_DX1GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_HVWRN_SHIFT)) & DDRPHY_DX1GSR3_HVWRN_MASK) #define DDRPHY_DX1GSR3_DVERR_MASK (0xF0000U) #define DDRPHY_DX1GSR3_DVERR_SHIFT (16U) /*! DVERR - DRAM VREF Training Error */ #define DDRPHY_DX1GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_DVERR_SHIFT)) & DDRPHY_DX1GSR3_DVERR_MASK) #define DDRPHY_DX1GSR3_DVWRN_MASK (0xF00000U) #define DDRPHY_DX1GSR3_DVWRN_SHIFT (20U) /*! DVWRN - DRAM VREF Training Warning */ #define DDRPHY_DX1GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_DVWRN_SHIFT)) & DDRPHY_DX1GSR3_DVWRN_MASK) #define DDRPHY_DX1GSR3_ESTAT_MASK (0x7000000U) #define DDRPHY_DX1GSR3_ESTAT_SHIFT (24U) /*! ESTAT - VREF Training Error Status Code */ #define DDRPHY_DX1GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_ESTAT_SHIFT)) & DDRPHY_DX1GSR3_ESTAT_MASK) #define DDRPHY_DX1GSR3_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX1GSR3_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX1GSR3_RESERVED_31_27_MASK) /*! @} */ /*! @name DX1GSR4 - DATX8 n General Status Register 4 */ /*! @{ */ #define DDRPHY_DX1GSR4_RESERVED_0_MASK (0x1U) #define DDRPHY_DX1GSR4_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_0_MASK) #define DDRPHY_DX1GSR4_RESERVED_1_MASK (0x2U) #define DDRPHY_DX1GSR4_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_1_MASK) #define DDRPHY_DX1GSR4_RESERVED_2_MASK (0x4U) #define DDRPHY_DX1GSR4_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_2_MASK) #define DDRPHY_DX1GSR4_RESERVED_3_MASK (0x8U) #define DDRPHY_DX1GSR4_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_3_MASK) #define DDRPHY_DX1GSR4_RESERVED_4_MASK (0x10U) #define DDRPHY_DX1GSR4_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_4_MASK) #define DDRPHY_DX1GSR4_RESERVED_5_MASK (0x20U) #define DDRPHY_DX1GSR4_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_5_MASK) #define DDRPHY_DX1GSR4_RESERVED_6_MASK (0x40U) #define DDRPHY_DX1GSR4_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_6_MASK) #define DDRPHY_DX1GSR4_RESERVED_15_7_MASK (0xFF80U) #define DDRPHY_DX1GSR4_RESERVED_15_7_SHIFT (7U) /*! RESERVED_15_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_15_7_MASK) #define DDRPHY_DX1GSR4_RESERVED_16_MASK (0x10000U) #define DDRPHY_DX1GSR4_RESERVED_16_SHIFT (16U) /*! RESERVED_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_16_MASK) #define DDRPHY_DX1GSR4_RESERVED_25_17_MASK (0x3FE0000U) #define DDRPHY_DX1GSR4_RESERVED_25_17_SHIFT (17U) /*! RESERVED_25_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_25_17_MASK) #define DDRPHY_DX1GSR4_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_DX1GSR4_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX1GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_31_26_MASK) /*! @} */ /*! @name DX1GSR5 - DATX8 n General Status Register 5 */ /*! @{ */ #define DDRPHY_DX1GSR5_RESERVED_0_MASK (0x1U) #define DDRPHY_DX1GSR5_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_0_MASK) #define DDRPHY_DX1GSR5_RESERVED_1_MASK (0x2U) #define DDRPHY_DX1GSR5_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_1_MASK) #define DDRPHY_DX1GSR5_RESERVED_2_MASK (0x4U) #define DDRPHY_DX1GSR5_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_2_MASK) #define DDRPHY_DX1GSR5_RESERVED_3_MASK (0x8U) #define DDRPHY_DX1GSR5_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_3_MASK) #define DDRPHY_DX1GSR5_RESERVED_4_MASK (0x10U) #define DDRPHY_DX1GSR5_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_4_MASK) #define DDRPHY_DX1GSR5_RESERVED_5_MASK (0x20U) #define DDRPHY_DX1GSR5_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_5_MASK) #define DDRPHY_DX1GSR5_RESERVED_6_MASK (0x40U) #define DDRPHY_DX1GSR5_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_6_MASK) #define DDRPHY_DX1GSR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX1GSR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_7_MASK) #define DDRPHY_DX1GSR5_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX1GSR5_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_11_8_MASK) #define DDRPHY_DX1GSR5_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_DX1GSR5_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_19_12_MASK) #define DDRPHY_DX1GSR5_RESERVED_20_MASK (0x100000U) #define DDRPHY_DX1GSR5_RESERVED_20_SHIFT (20U) /*! RESERVED_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_20_MASK) #define DDRPHY_DX1GSR5_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX1GSR5_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_21_MASK) #define DDRPHY_DX1GSR5_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX1GSR5_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_22_MASK) #define DDRPHY_DX1GSR5_RESERVED_31_23_MASK (0xFF800000U) #define DDRPHY_DX1GSR5_RESERVED_31_23_SHIFT (23U) /*! RESERVED_31_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_31_23_MASK) /*! @} */ /*! @name DX1GSR6 - DATX8 n General Status Register 6 */ /*! @{ */ #define DDRPHY_DX1GSR6_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX1GSR6_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_1_0_MASK) #define DDRPHY_DX1GSR6_RESERVED_3_2_MASK (0xCU) #define DDRPHY_DX1GSR6_RESERVED_3_2_SHIFT (2U) /*! RESERVED_3_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_3_2_MASK) #define DDRPHY_DX1GSR6_RESERVED_7_4_MASK (0xF0U) #define DDRPHY_DX1GSR6_RESERVED_7_4_SHIFT (4U) /*! RESERVED_7_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_7_4_MASK) #define DDRPHY_DX1GSR6_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX1GSR6_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_11_8_MASK) #define DDRPHY_DX1GSR6_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_DX1GSR6_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_15_12_MASK) #define DDRPHY_DX1GSR6_RESERVED_19_15_MASK (0xF0000U) #define DDRPHY_DX1GSR6_RESERVED_19_15_SHIFT (16U) /*! RESERVED_19_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_19_15_MASK) #define DDRPHY_DX1GSR6_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX1GSR6_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_23_20_MASK) #define DDRPHY_DX1GSR6_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX1GSR6_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX1GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_31_24_MASK) /*! @} */ /*! @name DX2GCR0 - DATX8 n General Configuration Register 0 */ /*! @{ */ #define DDRPHY_DX2GCR0_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX2GCR0_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX2GCR0_RESERVED_1_0_MASK) #define DDRPHY_DX2GCR0_DQSGOE_MASK (0x4U) #define DDRPHY_DX2GCR0_DQSGOE_SHIFT (2U) /*! DQSGOE - DQSG Output Enable */ #define DDRPHY_DX2GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSGOE_SHIFT)) & DDRPHY_DX2GCR0_DQSGOE_MASK) #define DDRPHY_DX2GCR0_DQSGODT_MASK (0x8U) #define DDRPHY_DX2GCR0_DQSGODT_SHIFT (3U) /*! DQSGODT - DQSG On-Die Termination */ #define DDRPHY_DX2GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSGODT_SHIFT)) & DDRPHY_DX2GCR0_DQSGODT_MASK) #define DDRPHY_DX2GCR0_RESERVED_4_MASK (0x10U) #define DDRPHY_DX2GCR0_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX2GCR0_RESERVED_4_MASK) #define DDRPHY_DX2GCR0_DQSGPDR_MASK (0x20U) #define DDRPHY_DX2GCR0_DQSGPDR_SHIFT (5U) /*! DQSGPDR - DQSG Power Down Receiver */ #define DDRPHY_DX2GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX2GCR0_DQSGPDR_MASK) #define DDRPHY_DX2GCR0_DQSRPD_MASK (0x40U) #define DDRPHY_DX2GCR0_DQSRPD_SHIFT (6U) /*! DQSRPD - DQSR Power Down */ #define DDRPHY_DX2GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSRPD_SHIFT)) & DDRPHY_DX2GCR0_DQSRPD_MASK) #define DDRPHY_DX2GCR0_CPDRSHFT_MASK (0x180U) #define DDRPHY_DX2GCR0_CPDRSHFT_SHIFT (7U) /*! CPDRSHFT - Configurable PDR Phase Shift */ #define DDRPHY_DX2GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX2GCR0_CPDRSHFT_MASK) #define DDRPHY_DX2GCR0_RTTOH_MASK (0x600U) #define DDRPHY_DX2GCR0_RTTOH_SHIFT (9U) /*! RTTOH - RTT Output Hold */ #define DDRPHY_DX2GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RTTOH_SHIFT)) & DDRPHY_DX2GCR0_RTTOH_MASK) #define DDRPHY_DX2GCR0_RTTOAL_MASK (0x800U) #define DDRPHY_DX2GCR0_RTTOAL_SHIFT (11U) /*! RTTOAL - RTT On Additive Latency */ #define DDRPHY_DX2GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RTTOAL_SHIFT)) & DDRPHY_DX2GCR0_RTTOAL_MASK) #define DDRPHY_DX2GCR0_DQSSEPDR_MASK (0x1000U) #define DDRPHY_DX2GCR0_DQSSEPDR_SHIFT (12U) /*! DQSSEPDR - DQSSE Power Down Receiver */ #define DDRPHY_DX2GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX2GCR0_DQSSEPDR_MASK) #define DDRPHY_DX2GCR0_DQSNSEPDR_MASK (0x2000U) #define DDRPHY_DX2GCR0_DQSNSEPDR_SHIFT (13U) /*! DQSNSEPDR - DQSNSE Power Down Receiver */ #define DDRPHY_DX2GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX2GCR0_DQSNSEPDR_MASK) #define DDRPHY_DX2GCR0_RESERVED_19_14_MASK (0xFC000U) #define DDRPHY_DX2GCR0_RESERVED_19_14_SHIFT (14U) /*! RESERVED_19_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX2GCR0_RESERVED_19_14_MASK) #define DDRPHY_DX2GCR0_RDDLY_MASK (0xF00000U) #define DDRPHY_DX2GCR0_RDDLY_SHIFT (20U) /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY */ #define DDRPHY_DX2GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RDDLY_SHIFT)) & DDRPHY_DX2GCR0_RDDLY_MASK) #define DDRPHY_DX2GCR0_DQSDCC_MASK (0xF000000U) #define DDRPHY_DX2GCR0_DQSDCC_SHIFT (24U) /*! DQSDCC - DQS Duty Cycle Correction */ #define DDRPHY_DX2GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSDCC_SHIFT)) & DDRPHY_DX2GCR0_DQSDCC_MASK) #define DDRPHY_DX2GCR0_CODTSHFT_MASK (0x30000000U) #define DDRPHY_DX2GCR0_CODTSHFT_SHIFT (28U) /*! CODTSHFT - Configurable ODT(TE) Phase Shift */ #define DDRPHY_DX2GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX2GCR0_CODTSHFT_MASK) #define DDRPHY_DX2GCR0_MDLEN_MASK (0x40000000U) #define DDRPHY_DX2GCR0_MDLEN_SHIFT (30U) /*! MDLEN - Master Delay Line Enable */ #define DDRPHY_DX2GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_MDLEN_SHIFT)) & DDRPHY_DX2GCR0_MDLEN_MASK) #define DDRPHY_DX2GCR0_CALBYP_MASK (0x80000000U) #define DDRPHY_DX2GCR0_CALBYP_SHIFT (31U) /*! CALBYP - Calibration Bypass */ #define DDRPHY_DX2GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_CALBYP_SHIFT)) & DDRPHY_DX2GCR0_CALBYP_MASK) /*! @} */ /*! @name DX2GCR1 - DATX8 n General Configuration Register 1 */ /*! @{ */ #define DDRPHY_DX2GCR1_DQEN_MASK (0xFFU) #define DDRPHY_DX2GCR1_DQEN_SHIFT (0U) /*! DQEN - Enables DQ corresponding to each bit in a byte */ #define DDRPHY_DX2GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DQEN_SHIFT)) & DDRPHY_DX2GCR1_DQEN_MASK) #define DDRPHY_DX2GCR1_DMEN_MASK (0x100U) #define DDRPHY_DX2GCR1_DMEN_SHIFT (8U) /*! DMEN - Enables DM pin in a byte lane */ #define DDRPHY_DX2GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DMEN_SHIFT)) & DDRPHY_DX2GCR1_DMEN_MASK) #define DDRPHY_DX2GCR1_DSEN_MASK (0x200U) #define DDRPHY_DX2GCR1_DSEN_SHIFT (9U) /*! DSEN - Enables Write Data strobe in a byte lane */ #define DDRPHY_DX2GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DSEN_SHIFT)) & DDRPHY_DX2GCR1_DSEN_MASK) #define DDRPHY_DX2GCR1_TEEN_MASK (0x400U) #define DDRPHY_DX2GCR1_TEEN_SHIFT (10U) /*! TEEN - Enables ODT/TE in a byte lane */ #define DDRPHY_DX2GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_TEEN_SHIFT)) & DDRPHY_DX2GCR1_TEEN_MASK) #define DDRPHY_DX2GCR1_PDREN_MASK (0x800U) #define DDRPHY_DX2GCR1_PDREN_SHIFT (11U) /*! PDREN - Enables PDR in a byte lane */ #define DDRPHY_DX2GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_PDREN_SHIFT)) & DDRPHY_DX2GCR1_PDREN_MASK) #define DDRPHY_DX2GCR1_OEEN_MASK (0x1000U) #define DDRPHY_DX2GCR1_OEEN_SHIFT (12U) /*! OEEN - Enables Read Data Strobe in a byte lane */ #define DDRPHY_DX2GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_OEEN_SHIFT)) & DDRPHY_DX2GCR1_OEEN_MASK) #define DDRPHY_DX2GCR1_QSSEL_MASK (0x2000U) #define DDRPHY_DX2GCR1_QSSEL_SHIFT (13U) /*! QSSEL - Select the delayed or non-delayed read data strobe */ #define DDRPHY_DX2GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_QSSEL_SHIFT)) & DDRPHY_DX2GCR1_QSSEL_MASK) #define DDRPHY_DX2GCR1_QSNSEL_MASK (0x4000U) #define DDRPHY_DX2GCR1_QSNSEL_SHIFT (14U) /*! QSNSEL - Select the delayed or non-delayed read data strobe # */ #define DDRPHY_DX2GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_QSNSEL_SHIFT)) & DDRPHY_DX2GCR1_QSNSEL_MASK) #define DDRPHY_DX2GCR1_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX2GCR1_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX2GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX2GCR1_RESERVED_15_MASK) #define DDRPHY_DX2GCR1_DXPDRMODE_MASK (0xFFFF0000U) #define DDRPHY_DX2GCR1_DXPDRMODE_SHIFT (16U) /*! DXPDRMODE - Enables the PDR mode for DQ[7:0] */ #define DDRPHY_DX2GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX2GCR1_DXPDRMODE_MASK) /*! @} */ /*! @name DX2GCR2 - DATX8 n General Configuration Register 2 */ /*! @{ */ #define DDRPHY_DX2GCR2_DXTEMODE_MASK (0xFFFFU) #define DDRPHY_DX2GCR2_DXTEMODE_SHIFT (0U) /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0] */ #define DDRPHY_DX2GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX2GCR2_DXTEMODE_MASK) #define DDRPHY_DX2GCR2_DXOEMODE_MASK (0xFFFF0000U) #define DDRPHY_DX2GCR2_DXOEMODE_SHIFT (16U) /*! DXOEMODE - Enables the OE mode values for DQ[7:0] */ #define DDRPHY_DX2GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX2GCR2_DXOEMODE_MASK) /*! @} */ /*! @name DX2GCR3 - DATX8 n General Configuration Register 3 */ /*! @{ */ #define DDRPHY_DX2GCR3_WDMBVT_MASK (0x1U) #define DDRPHY_DX2GCR3_WDMBVT_SHIFT (0U) /*! WDMBVT - Write Data Mask BDL VT Compensation */ #define DDRPHY_DX2GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDMBVT_SHIFT)) & DDRPHY_DX2GCR3_WDMBVT_MASK) #define DDRPHY_DX2GCR3_RDMBVT_MASK (0x2U) #define DDRPHY_DX2GCR3_RDMBVT_SHIFT (1U) /*! RDMBVT - Read Data Mask BDL VT Compensation */ #define DDRPHY_DX2GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RDMBVT_SHIFT)) & DDRPHY_DX2GCR3_RDMBVT_MASK) #define DDRPHY_DX2GCR3_DSPDRMODE_MASK (0xCU) #define DDRPHY_DX2GCR3_DSPDRMODE_SHIFT (2U) /*! DSPDRMODE - Enables the PDR mode values for DQS. */ #define DDRPHY_DX2GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX2GCR3_DSPDRMODE_MASK) #define DDRPHY_DX2GCR3_DSTEMODE_MASK (0x30U) #define DDRPHY_DX2GCR3_DSTEMODE_SHIFT (4U) /*! DSTEMODE - Enables the TE mode values for DQS. */ #define DDRPHY_DX2GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSTEMODE_MASK) #define DDRPHY_DX2GCR3_DSOEMODE_MASK (0xC0U) #define DDRPHY_DX2GCR3_DSOEMODE_SHIFT (6U) /*! DSOEMODE - Enables the OE mode values for DQS. */ #define DDRPHY_DX2GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSOEMODE_MASK) #define DDRPHY_DX2GCR3_WDSBVT_MASK (0x100U) #define DDRPHY_DX2GCR3_WDSBVT_SHIFT (8U) /*! WDSBVT - Write Data Strobe BDL VT Compensation */ #define DDRPHY_DX2GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDSBVT_SHIFT)) & DDRPHY_DX2GCR3_WDSBVT_MASK) #define DDRPHY_DX2GCR3_RESERVED_9_MASK (0x200U) #define DDRPHY_DX2GCR3_RESERVED_9_SHIFT (9U) /*! RESERVED_9 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX2GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX2GCR3_RESERVED_9_MASK) #define DDRPHY_DX2GCR3_DMPDRMODE_MASK (0xC00U) #define DDRPHY_DX2GCR3_DMPDRMODE_SHIFT (10U) /*! DMPDRMODE - Enables the PDR mode values for DM. */ #define DDRPHY_DX2GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX2GCR3_DMPDRMODE_MASK) #define DDRPHY_DX2GCR3_DMTEMODE_MASK (0x3000U) #define DDRPHY_DX2GCR3_DMTEMODE_SHIFT (12U) /*! DMTEMODE - Enables the TE mode values for DM. */ #define DDRPHY_DX2GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX2GCR3_DMTEMODE_MASK) #define DDRPHY_DX2GCR3_DMOEMODE_MASK (0xC000U) #define DDRPHY_DX2GCR3_DMOEMODE_SHIFT (14U) /*! DMOEMODE - Enables the OE mode values for DM. */ #define DDRPHY_DX2GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX2GCR3_DMOEMODE_MASK) #define DDRPHY_DX2GCR3_DSNPDRMODE_MASK (0x30000U) #define DDRPHY_DX2GCR3_DSNPDRMODE_SHIFT (16U) /*! DSNPDRMODE - Enables the PDR mode for DQS */ #define DDRPHY_DX2GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX2GCR3_DSNPDRMODE_MASK) #define DDRPHY_DX2GCR3_DSNTEMODE_MASK (0xC0000U) #define DDRPHY_DX2GCR3_DSNTEMODE_SHIFT (18U) /*! DSNTEMODE - Enables the TE mode for DQS */ #define DDRPHY_DX2GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSNTEMODE_MASK) #define DDRPHY_DX2GCR3_DSNOEMODE_MASK (0x300000U) #define DDRPHY_DX2GCR3_DSNOEMODE_SHIFT (20U) /*! DSNOEMODE - Enables the OE mode for DQs */ #define DDRPHY_DX2GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSNOEMODE_MASK) #define DDRPHY_DX2GCR3_PDRBVT_MASK (0x400000U) #define DDRPHY_DX2GCR3_PDRBVT_SHIFT (22U) /*! PDRBVT - Power Down Receiver BDL VT Compensation */ #define DDRPHY_DX2GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_PDRBVT_SHIFT)) & DDRPHY_DX2GCR3_PDRBVT_MASK) #define DDRPHY_DX2GCR3_RGSLVT_MASK (0x800000U) #define DDRPHY_DX2GCR3_RGSLVT_SHIFT (23U) /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation */ #define DDRPHY_DX2GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RGSLVT_SHIFT)) & DDRPHY_DX2GCR3_RGSLVT_MASK) #define DDRPHY_DX2GCR3_WLLVT_MASK (0x1000000U) #define DDRPHY_DX2GCR3_WLLVT_SHIFT (24U) /*! WLLVT - Write Leveling LCDL Delay VT Compensation */ #define DDRPHY_DX2GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WLLVT_SHIFT)) & DDRPHY_DX2GCR3_WLLVT_MASK) #define DDRPHY_DX2GCR3_WDLVT_MASK (0x2000000U) #define DDRPHY_DX2GCR3_WDLVT_SHIFT (25U) /*! WDLVT - Write DQ LCDL Delay VT Compensation */ #define DDRPHY_DX2GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDLVT_SHIFT)) & DDRPHY_DX2GCR3_WDLVT_MASK) #define DDRPHY_DX2GCR3_RDLVT_MASK (0x4000000U) #define DDRPHY_DX2GCR3_RDLVT_SHIFT (26U) /*! RDLVT - Read DQS LCDL Delay VT Compensation */ #define DDRPHY_DX2GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RDLVT_SHIFT)) & DDRPHY_DX2GCR3_RDLVT_MASK) #define DDRPHY_DX2GCR3_RGLVT_MASK (0x8000000U) #define DDRPHY_DX2GCR3_RGLVT_SHIFT (27U) /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation */ #define DDRPHY_DX2GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RGLVT_SHIFT)) & DDRPHY_DX2GCR3_RGLVT_MASK) #define DDRPHY_DX2GCR3_WDBVT_MASK (0x10000000U) #define DDRPHY_DX2GCR3_WDBVT_SHIFT (28U) /*! WDBVT - Write Data BDL VT Compensation */ #define DDRPHY_DX2GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDBVT_SHIFT)) & DDRPHY_DX2GCR3_WDBVT_MASK) #define DDRPHY_DX2GCR3_RDBVT_MASK (0x20000000U) #define DDRPHY_DX2GCR3_RDBVT_SHIFT (29U) /*! RDBVT - Read Data BDL VT Compensation */ #define DDRPHY_DX2GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RDBVT_SHIFT)) & DDRPHY_DX2GCR3_RDBVT_MASK) #define DDRPHY_DX2GCR3_TEBVT_MASK (0x40000000U) #define DDRPHY_DX2GCR3_TEBVT_SHIFT (30U) /*! TEBVT - Termination Enable BDL VT Compensation */ #define DDRPHY_DX2GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_TEBVT_SHIFT)) & DDRPHY_DX2GCR3_TEBVT_MASK) #define DDRPHY_DX2GCR3_OEBVT_MASK (0x80000000U) #define DDRPHY_DX2GCR3_OEBVT_SHIFT (31U) /*! OEBVT - Output Enable BDL VT Compensation */ #define DDRPHY_DX2GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_OEBVT_SHIFT)) & DDRPHY_DX2GCR3_OEBVT_MASK) /*! @} */ /*! @name DX2GCR4 - DATX8 n General Configuration Register 4 */ /*! @{ */ #define DDRPHY_DX2GCR4_DXREFIMON_MASK (0x3U) #define DDRPHY_DX2GCR4_DXREFIMON_SHIFT (0U) /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX2GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX2GCR4_DXREFIMON_MASK) #define DDRPHY_DX2GCR4_DXREFIEN_MASK (0x3CU) #define DDRPHY_DX2GCR4_DXREFIEN_SHIFT (2U) /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX2GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFIEN_MASK) #define DDRPHY_DX2GCR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2GCR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX2GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR4_RESERVED_7_6_MASK) #define DDRPHY_DX2GCR4_DXREFSSEL_MASK (0x7F00U) #define DDRPHY_DX2GCR4_DXREFSSEL_SHIFT (8U) /*! DXREFSSEL - Byte Lane Single-End VREF Select */ #define DDRPHY_DX2GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX2GCR4_DXREFSSEL_MASK) #define DDRPHY_DX2GCR4_DXREFSSELRANGE_MASK (0x8000U) #define DDRPHY_DX2GCR4_DXREFSSELRANGE_SHIFT (15U) /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select */ #define DDRPHY_DX2GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX2GCR4_DXREFSSELRANGE_MASK) #define DDRPHY_DX2GCR4_DXREFESEL_MASK (0x7F0000U) #define DDRPHY_DX2GCR4_DXREFESEL_SHIFT (16U) /*! DXREFESEL - Byte Lane External VREF Select */ #define DDRPHY_DX2GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX2GCR4_DXREFESEL_MASK) #define DDRPHY_DX2GCR4_DXREFESELRANGE_MASK (0x800000U) #define DDRPHY_DX2GCR4_DXREFESELRANGE_SHIFT (23U) /*! DXREFESELRANGE - External VREF generator REFSEL range select */ #define DDRPHY_DX2GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX2GCR4_DXREFESELRANGE_MASK) #define DDRPHY_DX2GCR4_RESERVED_24_MASK (0x1000000U) #define DDRPHY_DX2GCR4_RESERVED_24_SHIFT (24U) /*! RESERVED_24 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX2GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX2GCR4_RESERVED_24_MASK) #define DDRPHY_DX2GCR4_DXREFSEN_MASK (0x2000000U) #define DDRPHY_DX2GCR4_DXREFSEN_SHIFT (25U) /*! DXREFSEN - Byte Lane Single-End VREF Enable */ #define DDRPHY_DX2GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFSEN_MASK) #define DDRPHY_DX2GCR4_DXREFEEN_MASK (0xC000000U) #define DDRPHY_DX2GCR4_DXREFEEN_SHIFT (26U) /*! DXREFEEN - Byte Lane Internal VREF Enable */ #define DDRPHY_DX2GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFEEN_MASK) #define DDRPHY_DX2GCR4_DXREFPEN_MASK (0x10000000U) #define DDRPHY_DX2GCR4_DXREFPEN_SHIFT (28U) /*! DXREFPEN - Byte Lane VREF Pad Enable */ #define DDRPHY_DX2GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFPEN_MASK) #define DDRPHY_DX2GCR4_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DX2GCR4_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs) */ #define DDRPHY_DX2GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX2GCR4_RESERVED_31_29_MASK) /*! @} */ /*! @name DX2GCR5 - DATX8 n General Configuration Register 5 */ /*! @{ */ #define DDRPHY_DX2GCR5_DXREFISELR0_MASK (0x7FU) #define DDRPHY_DX2GCR5_DXREFISELR0_SHIFT (0U) /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0 */ #define DDRPHY_DX2GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR0_MASK) #define DDRPHY_DX2GCR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX2GCR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX2GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_7_MASK) #define DDRPHY_DX2GCR5_DXREFISELR1_MASK (0x7F00U) #define DDRPHY_DX2GCR5_DXREFISELR1_SHIFT (8U) /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1 */ #define DDRPHY_DX2GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR1_MASK) #define DDRPHY_DX2GCR5_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX2GCR5_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX2GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_15_MASK) #define DDRPHY_DX2GCR5_DXREFISELR2_MASK (0x7F0000U) #define DDRPHY_DX2GCR5_DXREFISELR2_SHIFT (16U) /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2 */ #define DDRPHY_DX2GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR2_MASK) #define DDRPHY_DX2GCR5_RESERVED_23_MASK (0x800000U) #define DDRPHY_DX2GCR5_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX2GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_23_MASK) #define DDRPHY_DX2GCR5_DXREFISELR3_MASK (0x7F000000U) #define DDRPHY_DX2GCR5_DXREFISELR3_SHIFT (24U) /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3 */ #define DDRPHY_DX2GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR3_MASK) #define DDRPHY_DX2GCR5_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX2GCR5_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX2GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_31_MASK) /*! @} */ /*! @name DX2GCR6 - DATX8 n General Configuration Register 6 */ /*! @{ */ #define DDRPHY_DX2GCR6_DXDQVREFR0_MASK (0x3FU) #define DDRPHY_DX2GCR6_DXDQVREFR0_SHIFT (0U) /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0 */ #define DDRPHY_DX2GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR0_MASK) #define DDRPHY_DX2GCR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2GCR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX2GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_7_6_MASK) #define DDRPHY_DX2GCR6_DXDQVREFR1_MASK (0x3F00U) #define DDRPHY_DX2GCR6_DXDQVREFR1_SHIFT (8U) /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1 */ #define DDRPHY_DX2GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR1_MASK) #define DDRPHY_DX2GCR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2GCR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX2GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_15_14_MASK) #define DDRPHY_DX2GCR6_DXDQVREFR2_MASK (0x3F0000U) #define DDRPHY_DX2GCR6_DXDQVREFR2_SHIFT (16U) /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2 */ #define DDRPHY_DX2GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR2_MASK) #define DDRPHY_DX2GCR6_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX2GCR6_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX2GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_23_22_MASK) #define DDRPHY_DX2GCR6_DXDQVREFR3_MASK (0x3F000000U) #define DDRPHY_DX2GCR6_DXDQVREFR3_SHIFT (24U) /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3 */ #define DDRPHY_DX2GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR3_MASK) #define DDRPHY_DX2GCR6_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX2GCR6_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX2GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_31_30_MASK) /*! @} */ /*! @name DX2GCR7 - DATX8 n General Configuration Register 7 */ /*! @{ */ #define DDRPHY_DX2GCR7_DCALSVAL_MASK (0x1FFU) #define DDRPHY_DX2GCR7_DCALSVAL_SHIFT (0U) /*! DCALSVAL - DDL Calibration Starting Value */ #define DDRPHY_DX2GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX2GCR7_DCALSVAL_MASK) #define DDRPHY_DX2GCR7_DCALTYPE_MASK (0x200U) #define DDRPHY_DX2GCR7_DCALTYPE_SHIFT (9U) /*! DCALTYPE - DDL Calibration Type */ #define DDRPHY_DX2GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX2GCR7_DCALTYPE_MASK) #define DDRPHY_DX2GCR7_RESERVED_17_10_MASK (0x3FC00U) #define DDRPHY_DX2GCR7_RESERVED_17_10_SHIFT (10U) /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX2GCR7_RESERVED_17_10_MASK) #define DDRPHY_DX2GCR7_RESERVED_18_MASK (0x40000U) #define DDRPHY_DX2GCR7_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX2GCR7_RESERVED_18_MASK) #define DDRPHY_DX2GCR7_RESERVED_31_19_MASK (0xFFF80000U) #define DDRPHY_DX2GCR7_RESERVED_31_19_SHIFT (19U) /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX2GCR7_RESERVED_31_19_MASK) /*! @} */ /*! @name DX2GCR8 - DATX8 n General Configuration Register 8 */ /*! @{ */ #define DDRPHY_DX2GCR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX2GCR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_5_0_MASK) #define DDRPHY_DX2GCR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2GCR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_7_6_MASK) #define DDRPHY_DX2GCR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX2GCR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_13_8_MASK) #define DDRPHY_DX2GCR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2GCR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_15_14_MASK) #define DDRPHY_DX2GCR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX2GCR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_21_16_MASK) #define DDRPHY_DX2GCR8_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX2GCR8_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_23_22_MASK) #define DDRPHY_DX2GCR8_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX2GCR8_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_29_24_MASK) #define DDRPHY_DX2GCR8_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX2GCR8_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_31_30_MASK) /*! @} */ /*! @name DX2GCR9 - DATX8 n General Configuration Register 9 */ /*! @{ */ #define DDRPHY_DX2GCR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX2GCR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_5_0_MASK) #define DDRPHY_DX2GCR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2GCR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_7_6_MASK) #define DDRPHY_DX2GCR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX2GCR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_13_8_MASK) #define DDRPHY_DX2GCR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2GCR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_15_14_MASK) #define DDRPHY_DX2GCR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX2GCR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_21_16_MASK) #define DDRPHY_DX2GCR9_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX2GCR9_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_23_22_MASK) #define DDRPHY_DX2GCR9_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX2GCR9_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_29_24_MASK) #define DDRPHY_DX2GCR9_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX2GCR9_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_31_30_MASK) /*! @} */ /*! @name DX2DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */ /*! @{ */ #define DDRPHY_DX2DQMAP0_DQ0MAP_MASK (0xFU) #define DDRPHY_DX2DQMAP0_DQ0MAP_SHIFT (0U) /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index */ #define DDRPHY_DX2DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ0MAP_MASK) #define DDRPHY_DX2DQMAP0_DQ1MAP_MASK (0xF0U) #define DDRPHY_DX2DQMAP0_DQ1MAP_SHIFT (4U) /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index */ #define DDRPHY_DX2DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ1MAP_MASK) #define DDRPHY_DX2DQMAP0_DQ2MAP_MASK (0xF00U) #define DDRPHY_DX2DQMAP0_DQ2MAP_SHIFT (8U) /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index */ #define DDRPHY_DX2DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ2MAP_MASK) #define DDRPHY_DX2DQMAP0_DQ3MAP_MASK (0xF000U) #define DDRPHY_DX2DQMAP0_DQ3MAP_SHIFT (12U) /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index */ #define DDRPHY_DX2DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ3MAP_MASK) #define DDRPHY_DX2DQMAP0_DQ4MAP_MASK (0xF0000U) #define DDRPHY_DX2DQMAP0_DQ4MAP_SHIFT (16U) /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index */ #define DDRPHY_DX2DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ4MAP_MASK) #define DDRPHY_DX2DQMAP0_RESERVED_30_20_MASK (0x7FF00000U) #define DDRPHY_DX2DQMAP0_RESERVED_30_20_SHIFT (20U) /*! RESERVED_30_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX2DQMAP0_RESERVED_30_20_MASK) #define DDRPHY_DX2DQMAP0_MAPOK_MASK (0x80000000U) #define DDRPHY_DX2DQMAP0_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX2DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX2DQMAP0_MAPOK_MASK) /*! @} */ /*! @name DX2DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */ /*! @{ */ #define DDRPHY_DX2DQMAP1_DQ5MAP_MASK (0xFU) #define DDRPHY_DX2DQMAP1_DQ5MAP_SHIFT (0U) /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index */ #define DDRPHY_DX2DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX2DQMAP1_DQ5MAP_MASK) #define DDRPHY_DX2DQMAP1_DQ6MAP_MASK (0xF0U) #define DDRPHY_DX2DQMAP1_DQ6MAP_SHIFT (4U) /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index */ #define DDRPHY_DX2DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX2DQMAP1_DQ6MAP_MASK) #define DDRPHY_DX2DQMAP1_DQ7MAP_MASK (0xF00U) #define DDRPHY_DX2DQMAP1_DQ7MAP_SHIFT (8U) /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index */ #define DDRPHY_DX2DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX2DQMAP1_DQ7MAP_MASK) #define DDRPHY_DX2DQMAP1_DMMAP_MASK (0xF000U) #define DDRPHY_DX2DQMAP1_DMMAP_SHIFT (12U) /*! DMMAP - DM bit DATX8 slice mapping index */ #define DDRPHY_DX2DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX2DQMAP1_DMMAP_MASK) #define DDRPHY_DX2DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U) #define DDRPHY_DX2DQMAP1_RESERVED_30_16_SHIFT (16U) /*! RESERVED_30_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX2DQMAP1_RESERVED_30_16_MASK) #define DDRPHY_DX2DQMAP1_MAPOK_MASK (0x80000000U) #define DDRPHY_DX2DQMAP1_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX2DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX2DQMAP1_MAPOK_MASK) /*! @} */ /*! @name DX2BDLR0 - DATX8 n Bit Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX2BDLR0_DQ0WBD_MASK (0x3FU) #define DDRPHY_DX2BDLR0_DQ0WBD_SHIFT (0U) /*! DQ0WBD - DQ0 Write Bit Delay */ #define DDRPHY_DX2BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ0WBD_MASK) #define DDRPHY_DX2BDLR0_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2BDLR0_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_7_6_MASK) #define DDRPHY_DX2BDLR0_DQ1WBD_MASK (0x3F00U) #define DDRPHY_DX2BDLR0_DQ1WBD_SHIFT (8U) /*! DQ1WBD - DQ1 Write Bit Delay */ #define DDRPHY_DX2BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ1WBD_MASK) #define DDRPHY_DX2BDLR0_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2BDLR0_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_15_14_MASK) #define DDRPHY_DX2BDLR0_DQ2WBD_MASK (0x3F0000U) #define DDRPHY_DX2BDLR0_DQ2WBD_SHIFT (16U) /*! DQ2WBD - DQ2 Write Bit Delay */ #define DDRPHY_DX2BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ2WBD_MASK) #define DDRPHY_DX2BDLR0_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX2BDLR0_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_23_22_MASK) #define DDRPHY_DX2BDLR0_DQ3WBD_MASK (0x3F000000U) #define DDRPHY_DX2BDLR0_DQ3WBD_SHIFT (24U) /*! DQ3WBD - DQ3 Write Bit Delay */ #define DDRPHY_DX2BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ3WBD_MASK) #define DDRPHY_DX2BDLR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX2BDLR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_31_30_MASK) /*! @} */ /*! @name DX2BDLR1 - DATX8 n Bit Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX2BDLR1_DQ4WBD_MASK (0x3FU) #define DDRPHY_DX2BDLR1_DQ4WBD_SHIFT (0U) /*! DQ4WBD - DQ4 Write Bit Delay */ #define DDRPHY_DX2BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ4WBD_MASK) #define DDRPHY_DX2BDLR1_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2BDLR1_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_7_6_MASK) #define DDRPHY_DX2BDLR1_DQ5WBD_MASK (0x3F00U) #define DDRPHY_DX2BDLR1_DQ5WBD_SHIFT (8U) /*! DQ5WBD - DQ5 Write Bit Delay */ #define DDRPHY_DX2BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ5WBD_MASK) #define DDRPHY_DX2BDLR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2BDLR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_15_14_MASK) #define DDRPHY_DX2BDLR1_DQ6WBD_MASK (0x3F0000U) #define DDRPHY_DX2BDLR1_DQ6WBD_SHIFT (16U) /*! DQ6WBD - DQ6 Write Bit Delay */ #define DDRPHY_DX2BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ6WBD_MASK) #define DDRPHY_DX2BDLR1_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX2BDLR1_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_23_22_MASK) #define DDRPHY_DX2BDLR1_DQ7WBD_MASK (0x3F000000U) #define DDRPHY_DX2BDLR1_DQ7WBD_SHIFT (24U) /*! DQ7WBD - DQ7 Write Bit Delay */ #define DDRPHY_DX2BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ7WBD_MASK) #define DDRPHY_DX2BDLR1_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX2BDLR1_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_31_30_MASK) /*! @} */ /*! @name DX2BDLR2 - DATX8 n Bit Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX2BDLR2_DMWBD_MASK (0x3FU) #define DDRPHY_DX2BDLR2_DMWBD_SHIFT (0U) /*! DMWBD - DM Write Bit Delay */ #define DDRPHY_DX2BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DMWBD_SHIFT)) & DDRPHY_DX2BDLR2_DMWBD_MASK) #define DDRPHY_DX2BDLR2_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2BDLR2_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_7_6_MASK) #define DDRPHY_DX2BDLR2_DSWBD_MASK (0x3F00U) #define DDRPHY_DX2BDLR2_DSWBD_SHIFT (8U) /*! DSWBD - DQS Write Bit Delay */ #define DDRPHY_DX2BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DSWBD_SHIFT)) & DDRPHY_DX2BDLR2_DSWBD_MASK) #define DDRPHY_DX2BDLR2_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2BDLR2_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_15_14_MASK) #define DDRPHY_DX2BDLR2_DSOEBD_MASK (0x3F0000U) #define DDRPHY_DX2BDLR2_DSOEBD_SHIFT (16U) /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay */ #define DDRPHY_DX2BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX2BDLR2_DSOEBD_MASK) #define DDRPHY_DX2BDLR2_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX2BDLR2_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_23_22_MASK) #define DDRPHY_DX2BDLR2_DSNWBD_MASK (0x3F000000U) #define DDRPHY_DX2BDLR2_DSNWBD_SHIFT (24U) /*! DSNWBD - DQSN Write Bit Delay */ #define DDRPHY_DX2BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX2BDLR2_DSNWBD_MASK) #define DDRPHY_DX2BDLR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX2BDLR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_31_30_MASK) /*! @} */ /*! @name DX2BDLR3 - DATX8 n Bit Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX2BDLR3_DQ0RBD_MASK (0x3FU) #define DDRPHY_DX2BDLR3_DQ0RBD_SHIFT (0U) /*! DQ0RBD - DQ0 Read Bit Delay */ #define DDRPHY_DX2BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ0RBD_MASK) #define DDRPHY_DX2BDLR3_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2BDLR3_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_7_6_MASK) #define DDRPHY_DX2BDLR3_DQ1RBD_MASK (0x3F00U) #define DDRPHY_DX2BDLR3_DQ1RBD_SHIFT (8U) /*! DQ1RBD - DQ1 Read Bit Delay */ #define DDRPHY_DX2BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ1RBD_MASK) #define DDRPHY_DX2BDLR3_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2BDLR3_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_15_14_MASK) #define DDRPHY_DX2BDLR3_DQ2RBD_MASK (0x3F0000U) #define DDRPHY_DX2BDLR3_DQ2RBD_SHIFT (16U) /*! DQ2RBD - DQ2 Read Bit Delay */ #define DDRPHY_DX2BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ2RBD_MASK) #define DDRPHY_DX2BDLR3_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX2BDLR3_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_23_22_MASK) #define DDRPHY_DX2BDLR3_DQ3RBD_MASK (0x3F000000U) #define DDRPHY_DX2BDLR3_DQ3RBD_SHIFT (24U) /*! DQ3RBD - DQ3 Read Bit Delay */ #define DDRPHY_DX2BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ3RBD_MASK) #define DDRPHY_DX2BDLR3_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX2BDLR3_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_31_30_MASK) /*! @} */ /*! @name DX2BDLR4 - DATX8 n Bit Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX2BDLR4_DQ4RBD_MASK (0x3FU) #define DDRPHY_DX2BDLR4_DQ4RBD_SHIFT (0U) /*! DQ4RBD - DQ4 Read Bit Delay */ #define DDRPHY_DX2BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ4RBD_MASK) #define DDRPHY_DX2BDLR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2BDLR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_7_6_MASK) #define DDRPHY_DX2BDLR4_DQ5RBD_MASK (0x3F00U) #define DDRPHY_DX2BDLR4_DQ5RBD_SHIFT (8U) /*! DQ5RBD - DQ5 Read Bit Delay */ #define DDRPHY_DX2BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ5RBD_MASK) #define DDRPHY_DX2BDLR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2BDLR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_15_14_MASK) #define DDRPHY_DX2BDLR4_DQ6RBD_MASK (0x3F0000U) #define DDRPHY_DX2BDLR4_DQ6RBD_SHIFT (16U) /*! DQ6RBD - DQ6 Read Bit Delay */ #define DDRPHY_DX2BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ6RBD_MASK) #define DDRPHY_DX2BDLR4_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX2BDLR4_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_23_22_MASK) #define DDRPHY_DX2BDLR4_DQ7RBD_MASK (0x3F000000U) #define DDRPHY_DX2BDLR4_DQ7RBD_SHIFT (24U) /*! DQ7RBD - DQ7 Read Bit Delay */ #define DDRPHY_DX2BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ7RBD_MASK) #define DDRPHY_DX2BDLR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX2BDLR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_31_30_MASK) /*! @} */ /*! @name DX2BDLR5 - DATX8 n Bit Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX2BDLR5_DMRBD_MASK (0x3FU) #define DDRPHY_DX2BDLR5_DMRBD_SHIFT (0U) /*! DMRBD - DM Read Bit Delay */ #define DDRPHY_DX2BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR5_DMRBD_SHIFT)) & DDRPHY_DX2BDLR5_DMRBD_MASK) #define DDRPHY_DX2BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U) #define DDRPHY_DX2BDLR5_RESERVED_31_6_SHIFT (6U) /*! RESERVED_31_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX2BDLR5_RESERVED_31_6_MASK) /*! @} */ /*! @name DX2BDLR6 - DATX8 n Bit Delay Line Register 6 */ /*! @{ */ #define DDRPHY_DX2BDLR6_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_DX2BDLR6_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX2BDLR6_RESERVED_7_0_MASK) #define DDRPHY_DX2BDLR6_PDRBD_MASK (0x3F00U) #define DDRPHY_DX2BDLR6_PDRBD_SHIFT (8U) /*! PDRBD - Power down receiver Bit Delay */ #define DDRPHY_DX2BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_PDRBD_SHIFT)) & DDRPHY_DX2BDLR6_PDRBD_MASK) #define DDRPHY_DX2BDLR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2BDLR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR6_RESERVED_15_14_MASK) #define DDRPHY_DX2BDLR6_TERBD_MASK (0x3F0000U) #define DDRPHY_DX2BDLR6_TERBD_SHIFT (16U) /*! TERBD - Termination Enable Bit Delay */ #define DDRPHY_DX2BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_TERBD_SHIFT)) & DDRPHY_DX2BDLR6_TERBD_MASK) #define DDRPHY_DX2BDLR6_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX2BDLR6_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR6_RESERVED_31_22_MASK) /*! @} */ /*! @name DX2BDLR7 - DATX8 n Bit Delay Line Register 7 */ /*! @{ */ #define DDRPHY_DX2BDLR7_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX2BDLR7_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_5_0_MASK) #define DDRPHY_DX2BDLR7_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2BDLR7_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_7_6_MASK) #define DDRPHY_DX2BDLR7_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX2BDLR7_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_13_8_MASK) #define DDRPHY_DX2BDLR7_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2BDLR7_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_15_14_MASK) #define DDRPHY_DX2BDLR7_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX2BDLR7_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_21_16_MASK) #define DDRPHY_DX2BDLR7_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX2BDLR7_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_31_22_MASK) /*! @} */ /*! @name DX2BDLR8 - DATX8 n Bit Delay Line Register 8 */ /*! @{ */ #define DDRPHY_DX2BDLR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX2BDLR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_5_0_MASK) #define DDRPHY_DX2BDLR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2BDLR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_7_6_MASK) #define DDRPHY_DX2BDLR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX2BDLR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_13_8_MASK) #define DDRPHY_DX2BDLR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2BDLR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_15_14_MASK) #define DDRPHY_DX2BDLR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX2BDLR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_21_16_MASK) #define DDRPHY_DX2BDLR8_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX2BDLR8_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_31_22_MASK) /*! @} */ /*! @name DX2BDLR9 - DATX8 n Bit Delay Line Register 9 */ /*! @{ */ #define DDRPHY_DX2BDLR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX2BDLR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_5_0_MASK) #define DDRPHY_DX2BDLR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX2BDLR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_7_6_MASK) #define DDRPHY_DX2BDLR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX2BDLR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_13_8_MASK) #define DDRPHY_DX2BDLR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX2BDLR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_15_14_MASK) #define DDRPHY_DX2BDLR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX2BDLR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_21_16_MASK) #define DDRPHY_DX2BDLR9_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX2BDLR9_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_31_22_MASK) /*! @} */ /*! @name DX2LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX2LCDLR0_WLD_MASK (0x1FFU) #define DDRPHY_DX2LCDLR0_WLD_SHIFT (0U) /*! WLD - Write Leveling Delay */ #define DDRPHY_DX2LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_WLD_SHIFT)) & DDRPHY_DX2LCDLR0_WLD_MASK) #define DDRPHY_DX2LCDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX2LCDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX2LCDLR0_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX2LCDLR0_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR0_RESERVED_24_16_MASK) #define DDRPHY_DX2LCDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX2LCDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX2LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX2LCDLR1_WDQD_MASK (0x1FFU) #define DDRPHY_DX2LCDLR1_WDQD_SHIFT (0U) /*! WDQD - Write Data Delay */ #define DDRPHY_DX2LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_WDQD_SHIFT)) & DDRPHY_DX2LCDLR1_WDQD_MASK) #define DDRPHY_DX2LCDLR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX2LCDLR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR1_RESERVED_15_9_MASK) #define DDRPHY_DX2LCDLR1_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX2LCDLR1_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR1_RESERVED_24_16_MASK) #define DDRPHY_DX2LCDLR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX2LCDLR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX2LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX2LCDLR2_DQSGD_MASK (0x1FFU) #define DDRPHY_DX2LCDLR2_DQSGD_SHIFT (0U) /*! DQSGD - Read DQS Gating Delay */ #define DDRPHY_DX2LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX2LCDLR2_DQSGD_MASK) #define DDRPHY_DX2LCDLR2_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX2LCDLR2_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR2_RESERVED_15_9_MASK) #define DDRPHY_DX2LCDLR2_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX2LCDLR2_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR2_RESERVED_24_16_MASK) #define DDRPHY_DX2LCDLR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX2LCDLR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR2_RESERVED_31_25_MASK) /*! @} */ /*! @name DX2LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX2LCDLR3_RDQSD_MASK (0x1FFU) #define DDRPHY_DX2LCDLR3_RDQSD_SHIFT (0U) /*! RDQSD - Read DQS Delay */ #define DDRPHY_DX2LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX2LCDLR3_RDQSD_MASK) #define DDRPHY_DX2LCDLR3_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX2LCDLR3_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR3_RESERVED_15_9_MASK) #define DDRPHY_DX2LCDLR3_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX2LCDLR3_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR3_RESERVED_24_16_MASK) #define DDRPHY_DX2LCDLR3_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX2LCDLR3_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR3_RESERVED_31_25_MASK) /*! @} */ /*! @name DX2LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX2LCDLR4_RDQSND_MASK (0x1FFU) #define DDRPHY_DX2LCDLR4_RDQSND_SHIFT (0U) /*! RDQSND - Read DQSN Delay */ #define DDRPHY_DX2LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX2LCDLR4_RDQSND_MASK) #define DDRPHY_DX2LCDLR4_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX2LCDLR4_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR4_RESERVED_15_9_MASK) #define DDRPHY_DX2LCDLR4_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX2LCDLR4_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR4_RESERVED_24_16_MASK) #define DDRPHY_DX2LCDLR4_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX2LCDLR4_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR4_RESERVED_31_25_MASK) /*! @} */ /*! @name DX2LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX2LCDLR5_DQSGSD_MASK (0x1FFU) #define DDRPHY_DX2LCDLR5_DQSGSD_SHIFT (0U) /*! DQSGSD - DQS Gating Status Delay */ #define DDRPHY_DX2LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX2LCDLR5_DQSGSD_MASK) #define DDRPHY_DX2LCDLR5_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX2LCDLR5_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR5_RESERVED_15_9_MASK) #define DDRPHY_DX2LCDLR5_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX2LCDLR5_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR5_RESERVED_24_16_MASK) #define DDRPHY_DX2LCDLR5_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX2LCDLR5_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR5_RESERVED_31_25_MASK) /*! @} */ /*! @name DX2MDLR0 - DATX8 n Master Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX2MDLR0_IPRD_MASK (0x1FFU) #define DDRPHY_DX2MDLR0_IPRD_SHIFT (0U) /*! IPRD - Initial Period */ #define DDRPHY_DX2MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_IPRD_SHIFT)) & DDRPHY_DX2MDLR0_IPRD_MASK) #define DDRPHY_DX2MDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX2MDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX2MDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX2MDLR0_TPRD_MASK (0x1FF0000U) #define DDRPHY_DX2MDLR0_TPRD_SHIFT (16U) /*! TPRD - Target Period */ #define DDRPHY_DX2MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_TPRD_SHIFT)) & DDRPHY_DX2MDLR0_TPRD_MASK) #define DDRPHY_DX2MDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX2MDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX2MDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX2MDLR1 - DATX8 n Master Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX2MDLR1_MDLD_MASK (0x1FFU) #define DDRPHY_DX2MDLR1_MDLD_SHIFT (0U) /*! MDLD - MDL Delay */ #define DDRPHY_DX2MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR1_MDLD_SHIFT)) & DDRPHY_DX2MDLR1_MDLD_MASK) #define DDRPHY_DX2MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U) #define DDRPHY_DX2MDLR1_RESERVED_31_9_SHIFT (9U) /*! RESERVED_31_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX2MDLR1_RESERVED_31_9_MASK) /*! @} */ /*! @name DX2GTR0 - DATX8 n General Timing Register 0 */ /*! @{ */ #define DDRPHY_DX2GTR0_DGSL_MASK (0x1FU) #define DDRPHY_DX2GTR0_DGSL_SHIFT (0U) /*! DGSL - DQS Gating System Latency */ #define DDRPHY_DX2GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_DGSL_SHIFT)) & DDRPHY_DX2GTR0_DGSL_MASK) #define DDRPHY_DX2GTR0_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DX2GTR0_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_7_5_MASK) #define DDRPHY_DX2GTR0_RESERVED_12_8_MASK (0x1F00U) #define DDRPHY_DX2GTR0_RESERVED_12_8_SHIFT (8U) /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_12_8_MASK) #define DDRPHY_DX2GTR0_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_DX2GTR0_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_15_13_MASK) #define DDRPHY_DX2GTR0_WLSL_MASK (0xF0000U) #define DDRPHY_DX2GTR0_WLSL_SHIFT (16U) /*! WLSL - Write Leveling System Latency */ #define DDRPHY_DX2GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_WLSL_SHIFT)) & DDRPHY_DX2GTR0_WLSL_MASK) #define DDRPHY_DX2GTR0_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX2GTR0_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX2GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_23_20_MASK) #define DDRPHY_DX2GTR0_WDQSL_MASK (0x7000000U) #define DDRPHY_DX2GTR0_WDQSL_SHIFT (24U) /*! WDQSL - DQ Write Path Latency Pipeline */ #define DDRPHY_DX2GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_WDQSL_SHIFT)) & DDRPHY_DX2GTR0_WDQSL_MASK) #define DDRPHY_DX2GTR0_RESERVED_31_24_MASK (0xF8000000U) #define DDRPHY_DX2GTR0_RESERVED_31_24_SHIFT (27U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_31_24_MASK) /*! @} */ /*! @name DX2RSR0 - DATX8 n Rank Status Register 0 */ /*! @{ */ #define DDRPHY_DX2RSR0_QSGERR_MASK (0xFFFFU) #define DDRPHY_DX2RSR0_QSGERR_SHIFT (0U) /*! QSGERR - DQS Gate Training Error */ #define DDRPHY_DX2RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR0_QSGERR_SHIFT)) & DDRPHY_DX2RSR0_QSGERR_MASK) #define DDRPHY_DX2RSR0_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX2RSR0_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR0_RESERVED_31_16_MASK) /*! @} */ /*! @name DX2RSR1 - DATX8 n Rank Status Register 1 */ /*! @{ */ #define DDRPHY_DX2RSR1_RDLVLERR_MASK (0xFFFFU) #define DDRPHY_DX2RSR1_RDLVLERR_SHIFT (0U) /*! RDLVLERR - Read Leveling Error */ #define DDRPHY_DX2RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX2RSR1_RDLVLERR_MASK) #define DDRPHY_DX2RSR1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX2RSR1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR1_RESERVED_31_16_MASK) /*! @} */ /*! @name DX2RSR2 - DATX8 n Rank Status Register 2 */ /*! @{ */ #define DDRPHY_DX2RSR2_WLAWN_MASK (0xFFFFU) #define DDRPHY_DX2RSR2_WLAWN_SHIFT (0U) /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning */ #define DDRPHY_DX2RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR2_WLAWN_SHIFT)) & DDRPHY_DX2RSR2_WLAWN_MASK) #define DDRPHY_DX2RSR2_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX2RSR2_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR2_RESERVED_31_16_MASK) /*! @} */ /*! @name DX2RSR3 - DATX8 n Rank Status Register 3 */ /*! @{ */ #define DDRPHY_DX2RSR3_WLAERR_MASK (0xFFFFU) #define DDRPHY_DX2RSR3_WLAERR_SHIFT (0U) /*! WLAERR - Write Leveling Adjustment Error */ #define DDRPHY_DX2RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR3_WLAERR_SHIFT)) & DDRPHY_DX2RSR3_WLAERR_MASK) #define DDRPHY_DX2RSR3_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX2RSR3_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR3_RESERVED_31_16_MASK) /*! @} */ /*! @name DX2GSR0 - DATX8 n General Status Register 0 */ /*! @{ */ #define DDRPHY_DX2GSR0_WDQCAL_MASK (0x1U) #define DDRPHY_DX2GSR0_WDQCAL_SHIFT (0U) /*! WDQCAL - Write DQ Calibration */ #define DDRPHY_DX2GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WDQCAL_SHIFT)) & DDRPHY_DX2GSR0_WDQCAL_MASK) #define DDRPHY_DX2GSR0_RDQSCAL_MASK (0x2U) #define DDRPHY_DX2GSR0_RDQSCAL_SHIFT (1U) /*! RDQSCAL - Read DQS Calibration */ #define DDRPHY_DX2GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX2GSR0_RDQSCAL_MASK) #define DDRPHY_DX2GSR0_RDQSNCAL_MASK (0x4U) #define DDRPHY_DX2GSR0_RDQSNCAL_SHIFT (2U) /*! RDQSNCAL - Read DQS# Calibration */ #define DDRPHY_DX2GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX2GSR0_RDQSNCAL_MASK) #define DDRPHY_DX2GSR0_GDQSCAL_MASK (0x8U) #define DDRPHY_DX2GSR0_GDQSCAL_SHIFT (3U) /*! GDQSCAL - Read DQS gating Calibration */ #define DDRPHY_DX2GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX2GSR0_GDQSCAL_MASK) #define DDRPHY_DX2GSR0_WLCAL_MASK (0x10U) #define DDRPHY_DX2GSR0_WLCAL_SHIFT (4U) /*! WLCAL - Write Leveling Calibration */ #define DDRPHY_DX2GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLCAL_SHIFT)) & DDRPHY_DX2GSR0_WLCAL_MASK) #define DDRPHY_DX2GSR0_WLDONE_MASK (0x20U) #define DDRPHY_DX2GSR0_WLDONE_SHIFT (5U) /*! WLDONE - Write Leveling Done */ #define DDRPHY_DX2GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLDONE_SHIFT)) & DDRPHY_DX2GSR0_WLDONE_MASK) #define DDRPHY_DX2GSR0_WLERR_MASK (0x40U) #define DDRPHY_DX2GSR0_WLERR_SHIFT (6U) /*! WLERR - Write Leveling Error */ #define DDRPHY_DX2GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLERR_SHIFT)) & DDRPHY_DX2GSR0_WLERR_MASK) #define DDRPHY_DX2GSR0_WLPRD_MASK (0xFF80U) #define DDRPHY_DX2GSR0_WLPRD_SHIFT (7U) /*! WLPRD - Write Leveling Period */ #define DDRPHY_DX2GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLPRD_SHIFT)) & DDRPHY_DX2GSR0_WLPRD_MASK) #define DDRPHY_DX2GSR0_DPLOCK_MASK (0x10000U) #define DDRPHY_DX2GSR0_DPLOCK_SHIFT (16U) /*! DPLOCK - DATX8 PLL Lock */ #define DDRPHY_DX2GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_DPLOCK_SHIFT)) & DDRPHY_DX2GSR0_DPLOCK_MASK) #define DDRPHY_DX2GSR0_GDQSPRD_MASK (0x3FE0000U) #define DDRPHY_DX2GSR0_GDQSPRD_SHIFT (17U) /*! GDQSPRD - Read DQS gating Period */ #define DDRPHY_DX2GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX2GSR0_GDQSPRD_MASK) #define DDRPHY_DX2GSR0_RESERVED_29_26_MASK (0x3C000000U) #define DDRPHY_DX2GSR0_RESERVED_29_26_SHIFT (26U) /*! RESERVED_29_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX2GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX2GSR0_RESERVED_29_26_MASK) #define DDRPHY_DX2GSR0_WLDQ_MASK (0x40000000U) #define DDRPHY_DX2GSR0_WLDQ_SHIFT (30U) /*! WLDQ - Write Leveling DQ Status */ #define DDRPHY_DX2GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLDQ_SHIFT)) & DDRPHY_DX2GSR0_WLDQ_MASK) #define DDRPHY_DX2GSR0_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX2GSR0_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX2GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX2GSR0_RESERVED_31_MASK) /*! @} */ /*! @name DX2GSR1 - DATX8 n General Status Register 1 */ /*! @{ */ #define DDRPHY_DX2GSR1_DLTDONE_MASK (0x1U) #define DDRPHY_DX2GSR1_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done */ #define DDRPHY_DX2GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR1_DLTDONE_SHIFT)) & DDRPHY_DX2GSR1_DLTDONE_MASK) #define DDRPHY_DX2GSR1_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_DX2GSR1_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code */ #define DDRPHY_DX2GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR1_DLTCODE_SHIFT)) & DDRPHY_DX2GSR1_DLTCODE_MASK) #define DDRPHY_DX2GSR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX2GSR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX2GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX2GSR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX2GSR2 - DATX8 n General Status Register 2 */ /*! @{ */ #define DDRPHY_DX2GSR2_RDERR_MASK (0x1U) #define DDRPHY_DX2GSR2_RDERR_SHIFT (0U) /*! RDERR - Read Bit Deskew Error */ #define DDRPHY_DX2GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_RDERR_SHIFT)) & DDRPHY_DX2GSR2_RDERR_MASK) #define DDRPHY_DX2GSR2_RDWN_MASK (0x2U) #define DDRPHY_DX2GSR2_RDWN_SHIFT (1U) /*! RDWN - Read Bit Deskew Warning */ #define DDRPHY_DX2GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_RDWN_SHIFT)) & DDRPHY_DX2GSR2_RDWN_MASK) #define DDRPHY_DX2GSR2_WDERR_MASK (0x4U) #define DDRPHY_DX2GSR2_WDERR_SHIFT (2U) /*! WDERR - Write Bit Deskew Error */ #define DDRPHY_DX2GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WDERR_SHIFT)) & DDRPHY_DX2GSR2_WDERR_MASK) #define DDRPHY_DX2GSR2_WDWN_MASK (0x8U) #define DDRPHY_DX2GSR2_WDWN_SHIFT (3U) /*! WDWN - Write Bit Deskew Warning */ #define DDRPHY_DX2GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WDWN_SHIFT)) & DDRPHY_DX2GSR2_WDWN_MASK) #define DDRPHY_DX2GSR2_REERR_MASK (0x10U) #define DDRPHY_DX2GSR2_REERR_SHIFT (4U) /*! REERR - Read Eye Centering Error */ #define DDRPHY_DX2GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_REERR_SHIFT)) & DDRPHY_DX2GSR2_REERR_MASK) #define DDRPHY_DX2GSR2_REWN_MASK (0x20U) #define DDRPHY_DX2GSR2_REWN_SHIFT (5U) /*! REWN - Read Eye Centering Warning */ #define DDRPHY_DX2GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_REWN_SHIFT)) & DDRPHY_DX2GSR2_REWN_MASK) #define DDRPHY_DX2GSR2_WEERR_MASK (0x40U) #define DDRPHY_DX2GSR2_WEERR_SHIFT (6U) /*! WEERR - Write Eye Centering Error */ #define DDRPHY_DX2GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WEERR_SHIFT)) & DDRPHY_DX2GSR2_WEERR_MASK) #define DDRPHY_DX2GSR2_WEWN_MASK (0x80U) #define DDRPHY_DX2GSR2_WEWN_SHIFT (7U) /*! WEWN - Write Eye Centering Warning */ #define DDRPHY_DX2GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WEWN_SHIFT)) & DDRPHY_DX2GSR2_WEWN_MASK) #define DDRPHY_DX2GSR2_ESTAT_MASK (0xF00U) #define DDRPHY_DX2GSR2_ESTAT_SHIFT (8U) /*! ESTAT - Error Status */ #define DDRPHY_DX2GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_ESTAT_SHIFT)) & DDRPHY_DX2GSR2_ESTAT_MASK) #define DDRPHY_DX2GSR2_DQS2DQERR_MASK (0xFF000U) #define DDRPHY_DX2GSR2_DQS2DQERR_SHIFT (12U) /*! DQS2DQERR - Write DQS2DQ Training Error */ #define DDRPHY_DX2GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX2GSR2_DQS2DQERR_MASK) #define DDRPHY_DX2GSR2_SRDERR_MASK (0x100000U) #define DDRPHY_DX2GSR2_SRDERR_SHIFT (20U) /*! SRDERR - Static Read Error */ #define DDRPHY_DX2GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_SRDERR_SHIFT)) & DDRPHY_DX2GSR2_SRDERR_MASK) #define DDRPHY_DX2GSR2_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX2GSR2_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX2GSR2_RESERVED_21_MASK) #define DDRPHY_DX2GSR2_GSDQSCAL_MASK (0x400000U) #define DDRPHY_DX2GSR2_GSDQSCAL_SHIFT (22U) /*! GSDQSCAL - Read DQS Gating Status Calibration */ #define DDRPHY_DX2GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX2GSR2_GSDQSCAL_MASK) #define DDRPHY_DX2GSR2_GSDQSPRD_MASK (0xFF800000U) #define DDRPHY_DX2GSR2_GSDQSPRD_SHIFT (23U) /*! GSDQSPRD - Read DQS gating Status Period */ #define DDRPHY_DX2GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX2GSR2_GSDQSPRD_MASK) /*! @} */ /*! @name DX2GSR3 - DATX8 n General Status Register 3 */ /*! @{ */ #define DDRPHY_DX2GSR3_SRDPC_MASK (0x3U) #define DDRPHY_DX2GSR3_SRDPC_SHIFT (0U) /*! SRDPC - Static Read Delay Pass Count */ #define DDRPHY_DX2GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_SRDPC_SHIFT)) & DDRPHY_DX2GSR3_SRDPC_MASK) #define DDRPHY_DX2GSR3_RESERVED_7_2_MASK (0xFCU) #define DDRPHY_DX2GSR3_RESERVED_7_2_SHIFT (2U) /*! RESERVED_7_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX2GSR3_RESERVED_7_2_MASK) #define DDRPHY_DX2GSR3_HVERR_MASK (0xF00U) #define DDRPHY_DX2GSR3_HVERR_SHIFT (8U) /*! HVERR - Host VREF Training Error */ #define DDRPHY_DX2GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_HVERR_SHIFT)) & DDRPHY_DX2GSR3_HVERR_MASK) #define DDRPHY_DX2GSR3_HVWRN_MASK (0xF000U) #define DDRPHY_DX2GSR3_HVWRN_SHIFT (12U) /*! HVWRN - Host VREF Training Warning */ #define DDRPHY_DX2GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_HVWRN_SHIFT)) & DDRPHY_DX2GSR3_HVWRN_MASK) #define DDRPHY_DX2GSR3_DVERR_MASK (0xF0000U) #define DDRPHY_DX2GSR3_DVERR_SHIFT (16U) /*! DVERR - DRAM VREF Training Error */ #define DDRPHY_DX2GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_DVERR_SHIFT)) & DDRPHY_DX2GSR3_DVERR_MASK) #define DDRPHY_DX2GSR3_DVWRN_MASK (0xF00000U) #define DDRPHY_DX2GSR3_DVWRN_SHIFT (20U) /*! DVWRN - DRAM VREF Training Warning */ #define DDRPHY_DX2GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_DVWRN_SHIFT)) & DDRPHY_DX2GSR3_DVWRN_MASK) #define DDRPHY_DX2GSR3_ESTAT_MASK (0x7000000U) #define DDRPHY_DX2GSR3_ESTAT_SHIFT (24U) /*! ESTAT - VREF Training Error Status Code */ #define DDRPHY_DX2GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_ESTAT_SHIFT)) & DDRPHY_DX2GSR3_ESTAT_MASK) #define DDRPHY_DX2GSR3_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX2GSR3_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX2GSR3_RESERVED_31_27_MASK) /*! @} */ /*! @name DX2GSR4 - DATX8 n General Status Register 4 */ /*! @{ */ #define DDRPHY_DX2GSR4_RESERVED_0_MASK (0x1U) #define DDRPHY_DX2GSR4_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_0_MASK) #define DDRPHY_DX2GSR4_RESERVED_1_MASK (0x2U) #define DDRPHY_DX2GSR4_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_1_MASK) #define DDRPHY_DX2GSR4_RESERVED_2_MASK (0x4U) #define DDRPHY_DX2GSR4_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_2_MASK) #define DDRPHY_DX2GSR4_RESERVED_3_MASK (0x8U) #define DDRPHY_DX2GSR4_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_3_MASK) #define DDRPHY_DX2GSR4_RESERVED_4_MASK (0x10U) #define DDRPHY_DX2GSR4_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_4_MASK) #define DDRPHY_DX2GSR4_RESERVED_5_MASK (0x20U) #define DDRPHY_DX2GSR4_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_5_MASK) #define DDRPHY_DX2GSR4_RESERVED_6_MASK (0x40U) #define DDRPHY_DX2GSR4_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_6_MASK) #define DDRPHY_DX2GSR4_RESERVED_15_7_MASK (0xFF80U) #define DDRPHY_DX2GSR4_RESERVED_15_7_SHIFT (7U) /*! RESERVED_15_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_15_7_MASK) #define DDRPHY_DX2GSR4_RESERVED_16_MASK (0x10000U) #define DDRPHY_DX2GSR4_RESERVED_16_SHIFT (16U) /*! RESERVED_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_16_MASK) #define DDRPHY_DX2GSR4_RESERVED_25_17_MASK (0x3FE0000U) #define DDRPHY_DX2GSR4_RESERVED_25_17_SHIFT (17U) /*! RESERVED_25_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_25_17_MASK) #define DDRPHY_DX2GSR4_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_DX2GSR4_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX2GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_31_26_MASK) /*! @} */ /*! @name DX2GSR5 - DATX8 n General Status Register 5 */ /*! @{ */ #define DDRPHY_DX2GSR5_RESERVED_0_MASK (0x1U) #define DDRPHY_DX2GSR5_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_0_MASK) #define DDRPHY_DX2GSR5_RESERVED_1_MASK (0x2U) #define DDRPHY_DX2GSR5_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_1_MASK) #define DDRPHY_DX2GSR5_RESERVED_2_MASK (0x4U) #define DDRPHY_DX2GSR5_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_2_MASK) #define DDRPHY_DX2GSR5_RESERVED_3_MASK (0x8U) #define DDRPHY_DX2GSR5_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_3_MASK) #define DDRPHY_DX2GSR5_RESERVED_4_MASK (0x10U) #define DDRPHY_DX2GSR5_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_4_MASK) #define DDRPHY_DX2GSR5_RESERVED_5_MASK (0x20U) #define DDRPHY_DX2GSR5_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_5_MASK) #define DDRPHY_DX2GSR5_RESERVED_6_MASK (0x40U) #define DDRPHY_DX2GSR5_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_6_MASK) #define DDRPHY_DX2GSR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX2GSR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_7_MASK) #define DDRPHY_DX2GSR5_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX2GSR5_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_11_8_MASK) #define DDRPHY_DX2GSR5_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_DX2GSR5_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_19_12_MASK) #define DDRPHY_DX2GSR5_RESERVED_20_MASK (0x100000U) #define DDRPHY_DX2GSR5_RESERVED_20_SHIFT (20U) /*! RESERVED_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_20_MASK) #define DDRPHY_DX2GSR5_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX2GSR5_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_21_MASK) #define DDRPHY_DX2GSR5_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX2GSR5_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_22_MASK) #define DDRPHY_DX2GSR5_RESERVED_31_23_MASK (0xFF800000U) #define DDRPHY_DX2GSR5_RESERVED_31_23_SHIFT (23U) /*! RESERVED_31_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_31_23_MASK) /*! @} */ /*! @name DX2GSR6 - DATX8 n General Status Register 6 */ /*! @{ */ #define DDRPHY_DX2GSR6_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX2GSR6_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_1_0_MASK) #define DDRPHY_DX2GSR6_RESERVED_3_2_MASK (0xCU) #define DDRPHY_DX2GSR6_RESERVED_3_2_SHIFT (2U) /*! RESERVED_3_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_3_2_MASK) #define DDRPHY_DX2GSR6_RESERVED_7_4_MASK (0xF0U) #define DDRPHY_DX2GSR6_RESERVED_7_4_SHIFT (4U) /*! RESERVED_7_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_7_4_MASK) #define DDRPHY_DX2GSR6_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX2GSR6_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_11_8_MASK) #define DDRPHY_DX2GSR6_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_DX2GSR6_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_15_12_MASK) #define DDRPHY_DX2GSR6_RESERVED_19_15_MASK (0xF0000U) #define DDRPHY_DX2GSR6_RESERVED_19_15_SHIFT (16U) /*! RESERVED_19_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_19_15_MASK) #define DDRPHY_DX2GSR6_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX2GSR6_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_23_20_MASK) #define DDRPHY_DX2GSR6_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX2GSR6_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX2GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_31_24_MASK) /*! @} */ /*! @name DX3GCR0 - DATX8 n General Configuration Register 0 */ /*! @{ */ #define DDRPHY_DX3GCR0_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX3GCR0_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX3GCR0_RESERVED_1_0_MASK) #define DDRPHY_DX3GCR0_DQSGOE_MASK (0x4U) #define DDRPHY_DX3GCR0_DQSGOE_SHIFT (2U) /*! DQSGOE - DQSG Output Enable */ #define DDRPHY_DX3GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSGOE_SHIFT)) & DDRPHY_DX3GCR0_DQSGOE_MASK) #define DDRPHY_DX3GCR0_DQSGODT_MASK (0x8U) #define DDRPHY_DX3GCR0_DQSGODT_SHIFT (3U) /*! DQSGODT - DQSG On-Die Termination */ #define DDRPHY_DX3GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSGODT_SHIFT)) & DDRPHY_DX3GCR0_DQSGODT_MASK) #define DDRPHY_DX3GCR0_RESERVED_4_MASK (0x10U) #define DDRPHY_DX3GCR0_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX3GCR0_RESERVED_4_MASK) #define DDRPHY_DX3GCR0_DQSGPDR_MASK (0x20U) #define DDRPHY_DX3GCR0_DQSGPDR_SHIFT (5U) /*! DQSGPDR - DQSG Power Down Receiver */ #define DDRPHY_DX3GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX3GCR0_DQSGPDR_MASK) #define DDRPHY_DX3GCR0_DQSRPD_MASK (0x40U) #define DDRPHY_DX3GCR0_DQSRPD_SHIFT (6U) /*! DQSRPD - DQSR Power Down */ #define DDRPHY_DX3GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSRPD_SHIFT)) & DDRPHY_DX3GCR0_DQSRPD_MASK) #define DDRPHY_DX3GCR0_CPDRSHFT_MASK (0x180U) #define DDRPHY_DX3GCR0_CPDRSHFT_SHIFT (7U) /*! CPDRSHFT - Configurable PDR Phase Shift */ #define DDRPHY_DX3GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX3GCR0_CPDRSHFT_MASK) #define DDRPHY_DX3GCR0_RTTOH_MASK (0x600U) #define DDRPHY_DX3GCR0_RTTOH_SHIFT (9U) /*! RTTOH - RTT Output Hold */ #define DDRPHY_DX3GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RTTOH_SHIFT)) & DDRPHY_DX3GCR0_RTTOH_MASK) #define DDRPHY_DX3GCR0_RTTOAL_MASK (0x800U) #define DDRPHY_DX3GCR0_RTTOAL_SHIFT (11U) /*! RTTOAL - RTT On Additive Latency */ #define DDRPHY_DX3GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RTTOAL_SHIFT)) & DDRPHY_DX3GCR0_RTTOAL_MASK) #define DDRPHY_DX3GCR0_DQSSEPDR_MASK (0x1000U) #define DDRPHY_DX3GCR0_DQSSEPDR_SHIFT (12U) /*! DQSSEPDR - DQSSE Power Down Receiver */ #define DDRPHY_DX3GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX3GCR0_DQSSEPDR_MASK) #define DDRPHY_DX3GCR0_DQSNSEPDR_MASK (0x2000U) #define DDRPHY_DX3GCR0_DQSNSEPDR_SHIFT (13U) /*! DQSNSEPDR - DQSNSE Power Down Receiver */ #define DDRPHY_DX3GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX3GCR0_DQSNSEPDR_MASK) #define DDRPHY_DX3GCR0_RESERVED_19_14_MASK (0xFC000U) #define DDRPHY_DX3GCR0_RESERVED_19_14_SHIFT (14U) /*! RESERVED_19_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX3GCR0_RESERVED_19_14_MASK) #define DDRPHY_DX3GCR0_RDDLY_MASK (0xF00000U) #define DDRPHY_DX3GCR0_RDDLY_SHIFT (20U) /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY */ #define DDRPHY_DX3GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RDDLY_SHIFT)) & DDRPHY_DX3GCR0_RDDLY_MASK) #define DDRPHY_DX3GCR0_DQSDCC_MASK (0xF000000U) #define DDRPHY_DX3GCR0_DQSDCC_SHIFT (24U) /*! DQSDCC - DQS Duty Cycle Correction */ #define DDRPHY_DX3GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSDCC_SHIFT)) & DDRPHY_DX3GCR0_DQSDCC_MASK) #define DDRPHY_DX3GCR0_CODTSHFT_MASK (0x30000000U) #define DDRPHY_DX3GCR0_CODTSHFT_SHIFT (28U) /*! CODTSHFT - Configurable ODT(TE) Phase Shift */ #define DDRPHY_DX3GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX3GCR0_CODTSHFT_MASK) #define DDRPHY_DX3GCR0_MDLEN_MASK (0x40000000U) #define DDRPHY_DX3GCR0_MDLEN_SHIFT (30U) /*! MDLEN - Master Delay Line Enable */ #define DDRPHY_DX3GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_MDLEN_SHIFT)) & DDRPHY_DX3GCR0_MDLEN_MASK) #define DDRPHY_DX3GCR0_CALBYP_MASK (0x80000000U) #define DDRPHY_DX3GCR0_CALBYP_SHIFT (31U) /*! CALBYP - Calibration Bypass */ #define DDRPHY_DX3GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_CALBYP_SHIFT)) & DDRPHY_DX3GCR0_CALBYP_MASK) /*! @} */ /*! @name DX3GCR1 - DATX8 n General Configuration Register 1 */ /*! @{ */ #define DDRPHY_DX3GCR1_DQEN_MASK (0xFFU) #define DDRPHY_DX3GCR1_DQEN_SHIFT (0U) /*! DQEN - Enables DQ corresponding to each bit in a byte */ #define DDRPHY_DX3GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DQEN_SHIFT)) & DDRPHY_DX3GCR1_DQEN_MASK) #define DDRPHY_DX3GCR1_DMEN_MASK (0x100U) #define DDRPHY_DX3GCR1_DMEN_SHIFT (8U) /*! DMEN - Enables DM pin in a byte lane */ #define DDRPHY_DX3GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DMEN_SHIFT)) & DDRPHY_DX3GCR1_DMEN_MASK) #define DDRPHY_DX3GCR1_DSEN_MASK (0x200U) #define DDRPHY_DX3GCR1_DSEN_SHIFT (9U) /*! DSEN - Enables Write Data strobe in a byte lane */ #define DDRPHY_DX3GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DSEN_SHIFT)) & DDRPHY_DX3GCR1_DSEN_MASK) #define DDRPHY_DX3GCR1_TEEN_MASK (0x400U) #define DDRPHY_DX3GCR1_TEEN_SHIFT (10U) /*! TEEN - Enables ODT/TE in a byte lane */ #define DDRPHY_DX3GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_TEEN_SHIFT)) & DDRPHY_DX3GCR1_TEEN_MASK) #define DDRPHY_DX3GCR1_PDREN_MASK (0x800U) #define DDRPHY_DX3GCR1_PDREN_SHIFT (11U) /*! PDREN - Enables PDR in a byte lane */ #define DDRPHY_DX3GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_PDREN_SHIFT)) & DDRPHY_DX3GCR1_PDREN_MASK) #define DDRPHY_DX3GCR1_OEEN_MASK (0x1000U) #define DDRPHY_DX3GCR1_OEEN_SHIFT (12U) /*! OEEN - Enables Read Data Strobe in a byte lane */ #define DDRPHY_DX3GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_OEEN_SHIFT)) & DDRPHY_DX3GCR1_OEEN_MASK) #define DDRPHY_DX3GCR1_QSSEL_MASK (0x2000U) #define DDRPHY_DX3GCR1_QSSEL_SHIFT (13U) /*! QSSEL - Select the delayed or non-delayed read data strobe */ #define DDRPHY_DX3GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_QSSEL_SHIFT)) & DDRPHY_DX3GCR1_QSSEL_MASK) #define DDRPHY_DX3GCR1_QSNSEL_MASK (0x4000U) #define DDRPHY_DX3GCR1_QSNSEL_SHIFT (14U) /*! QSNSEL - Select the delayed or non-delayed read data strobe # */ #define DDRPHY_DX3GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_QSNSEL_SHIFT)) & DDRPHY_DX3GCR1_QSNSEL_MASK) #define DDRPHY_DX3GCR1_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX3GCR1_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX3GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX3GCR1_RESERVED_15_MASK) #define DDRPHY_DX3GCR1_DXPDRMODE_MASK (0xFFFF0000U) #define DDRPHY_DX3GCR1_DXPDRMODE_SHIFT (16U) /*! DXPDRMODE - Enables the PDR mode for DQ[7:0] */ #define DDRPHY_DX3GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX3GCR1_DXPDRMODE_MASK) /*! @} */ /*! @name DX3GCR2 - DATX8 n General Configuration Register 2 */ /*! @{ */ #define DDRPHY_DX3GCR2_DXTEMODE_MASK (0xFFFFU) #define DDRPHY_DX3GCR2_DXTEMODE_SHIFT (0U) /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0] */ #define DDRPHY_DX3GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX3GCR2_DXTEMODE_MASK) #define DDRPHY_DX3GCR2_DXOEMODE_MASK (0xFFFF0000U) #define DDRPHY_DX3GCR2_DXOEMODE_SHIFT (16U) /*! DXOEMODE - Enables the OE mode values for DQ[7:0] */ #define DDRPHY_DX3GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX3GCR2_DXOEMODE_MASK) /*! @} */ /*! @name DX3GCR3 - DATX8 n General Configuration Register 3 */ /*! @{ */ #define DDRPHY_DX3GCR3_WDMBVT_MASK (0x1U) #define DDRPHY_DX3GCR3_WDMBVT_SHIFT (0U) /*! WDMBVT - Write Data Mask BDL VT Compensation */ #define DDRPHY_DX3GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDMBVT_SHIFT)) & DDRPHY_DX3GCR3_WDMBVT_MASK) #define DDRPHY_DX3GCR3_RDMBVT_MASK (0x2U) #define DDRPHY_DX3GCR3_RDMBVT_SHIFT (1U) /*! RDMBVT - Read Data Mask BDL VT Compensation */ #define DDRPHY_DX3GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RDMBVT_SHIFT)) & DDRPHY_DX3GCR3_RDMBVT_MASK) #define DDRPHY_DX3GCR3_DSPDRMODE_MASK (0xCU) #define DDRPHY_DX3GCR3_DSPDRMODE_SHIFT (2U) /*! DSPDRMODE - Enables the PDR mode values for DQS. */ #define DDRPHY_DX3GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX3GCR3_DSPDRMODE_MASK) #define DDRPHY_DX3GCR3_DSTEMODE_MASK (0x30U) #define DDRPHY_DX3GCR3_DSTEMODE_SHIFT (4U) /*! DSTEMODE - Enables the TE mode values for DQS. */ #define DDRPHY_DX3GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSTEMODE_MASK) #define DDRPHY_DX3GCR3_DSOEMODE_MASK (0xC0U) #define DDRPHY_DX3GCR3_DSOEMODE_SHIFT (6U) /*! DSOEMODE - Enables the OE mode values for DQS. */ #define DDRPHY_DX3GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSOEMODE_MASK) #define DDRPHY_DX3GCR3_WDSBVT_MASK (0x100U) #define DDRPHY_DX3GCR3_WDSBVT_SHIFT (8U) /*! WDSBVT - Write Data Strobe BDL VT Compensation */ #define DDRPHY_DX3GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDSBVT_SHIFT)) & DDRPHY_DX3GCR3_WDSBVT_MASK) #define DDRPHY_DX3GCR3_RESERVED_9_MASK (0x200U) #define DDRPHY_DX3GCR3_RESERVED_9_SHIFT (9U) /*! RESERVED_9 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX3GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX3GCR3_RESERVED_9_MASK) #define DDRPHY_DX3GCR3_DMPDRMODE_MASK (0xC00U) #define DDRPHY_DX3GCR3_DMPDRMODE_SHIFT (10U) /*! DMPDRMODE - Enables the PDR mode values for DM. */ #define DDRPHY_DX3GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX3GCR3_DMPDRMODE_MASK) #define DDRPHY_DX3GCR3_DMTEMODE_MASK (0x3000U) #define DDRPHY_DX3GCR3_DMTEMODE_SHIFT (12U) /*! DMTEMODE - Enables the TE mode values for DM. */ #define DDRPHY_DX3GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX3GCR3_DMTEMODE_MASK) #define DDRPHY_DX3GCR3_DMOEMODE_MASK (0xC000U) #define DDRPHY_DX3GCR3_DMOEMODE_SHIFT (14U) /*! DMOEMODE - Enables the OE mode values for DM. */ #define DDRPHY_DX3GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX3GCR3_DMOEMODE_MASK) #define DDRPHY_DX3GCR3_DSNPDRMODE_MASK (0x30000U) #define DDRPHY_DX3GCR3_DSNPDRMODE_SHIFT (16U) /*! DSNPDRMODE - Enables the PDR mode for DQS */ #define DDRPHY_DX3GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX3GCR3_DSNPDRMODE_MASK) #define DDRPHY_DX3GCR3_DSNTEMODE_MASK (0xC0000U) #define DDRPHY_DX3GCR3_DSNTEMODE_SHIFT (18U) /*! DSNTEMODE - Enables the TE mode for DQS */ #define DDRPHY_DX3GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSNTEMODE_MASK) #define DDRPHY_DX3GCR3_DSNOEMODE_MASK (0x300000U) #define DDRPHY_DX3GCR3_DSNOEMODE_SHIFT (20U) /*! DSNOEMODE - Enables the OE mode for DQs */ #define DDRPHY_DX3GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSNOEMODE_MASK) #define DDRPHY_DX3GCR3_PDRBVT_MASK (0x400000U) #define DDRPHY_DX3GCR3_PDRBVT_SHIFT (22U) /*! PDRBVT - Power Down Receiver BDL VT Compensation */ #define DDRPHY_DX3GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_PDRBVT_SHIFT)) & DDRPHY_DX3GCR3_PDRBVT_MASK) #define DDRPHY_DX3GCR3_RGSLVT_MASK (0x800000U) #define DDRPHY_DX3GCR3_RGSLVT_SHIFT (23U) /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation */ #define DDRPHY_DX3GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RGSLVT_SHIFT)) & DDRPHY_DX3GCR3_RGSLVT_MASK) #define DDRPHY_DX3GCR3_WLLVT_MASK (0x1000000U) #define DDRPHY_DX3GCR3_WLLVT_SHIFT (24U) /*! WLLVT - Write Leveling LCDL Delay VT Compensation */ #define DDRPHY_DX3GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WLLVT_SHIFT)) & DDRPHY_DX3GCR3_WLLVT_MASK) #define DDRPHY_DX3GCR3_WDLVT_MASK (0x2000000U) #define DDRPHY_DX3GCR3_WDLVT_SHIFT (25U) /*! WDLVT - Write DQ LCDL Delay VT Compensation */ #define DDRPHY_DX3GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDLVT_SHIFT)) & DDRPHY_DX3GCR3_WDLVT_MASK) #define DDRPHY_DX3GCR3_RDLVT_MASK (0x4000000U) #define DDRPHY_DX3GCR3_RDLVT_SHIFT (26U) /*! RDLVT - Read DQS LCDL Delay VT Compensation */ #define DDRPHY_DX3GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RDLVT_SHIFT)) & DDRPHY_DX3GCR3_RDLVT_MASK) #define DDRPHY_DX3GCR3_RGLVT_MASK (0x8000000U) #define DDRPHY_DX3GCR3_RGLVT_SHIFT (27U) /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation */ #define DDRPHY_DX3GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RGLVT_SHIFT)) & DDRPHY_DX3GCR3_RGLVT_MASK) #define DDRPHY_DX3GCR3_WDBVT_MASK (0x10000000U) #define DDRPHY_DX3GCR3_WDBVT_SHIFT (28U) /*! WDBVT - Write Data BDL VT Compensation */ #define DDRPHY_DX3GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDBVT_SHIFT)) & DDRPHY_DX3GCR3_WDBVT_MASK) #define DDRPHY_DX3GCR3_RDBVT_MASK (0x20000000U) #define DDRPHY_DX3GCR3_RDBVT_SHIFT (29U) /*! RDBVT - Read Data BDL VT Compensation */ #define DDRPHY_DX3GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RDBVT_SHIFT)) & DDRPHY_DX3GCR3_RDBVT_MASK) #define DDRPHY_DX3GCR3_TEBVT_MASK (0x40000000U) #define DDRPHY_DX3GCR3_TEBVT_SHIFT (30U) /*! TEBVT - Termination Enable BDL VT Compensation */ #define DDRPHY_DX3GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_TEBVT_SHIFT)) & DDRPHY_DX3GCR3_TEBVT_MASK) #define DDRPHY_DX3GCR3_OEBVT_MASK (0x80000000U) #define DDRPHY_DX3GCR3_OEBVT_SHIFT (31U) /*! OEBVT - Output Enable BDL VT Compensation */ #define DDRPHY_DX3GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_OEBVT_SHIFT)) & DDRPHY_DX3GCR3_OEBVT_MASK) /*! @} */ /*! @name DX3GCR4 - DATX8 n General Configuration Register 4 */ /*! @{ */ #define DDRPHY_DX3GCR4_DXREFIMON_MASK (0x3U) #define DDRPHY_DX3GCR4_DXREFIMON_SHIFT (0U) /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX3GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX3GCR4_DXREFIMON_MASK) #define DDRPHY_DX3GCR4_DXREFIEN_MASK (0x3CU) #define DDRPHY_DX3GCR4_DXREFIEN_SHIFT (2U) /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX3GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFIEN_MASK) #define DDRPHY_DX3GCR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3GCR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX3GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR4_RESERVED_7_6_MASK) #define DDRPHY_DX3GCR4_DXREFSSEL_MASK (0x7F00U) #define DDRPHY_DX3GCR4_DXREFSSEL_SHIFT (8U) /*! DXREFSSEL - Byte Lane Single-End VREF Select */ #define DDRPHY_DX3GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX3GCR4_DXREFSSEL_MASK) #define DDRPHY_DX3GCR4_DXREFSSELRANGE_MASK (0x8000U) #define DDRPHY_DX3GCR4_DXREFSSELRANGE_SHIFT (15U) /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select */ #define DDRPHY_DX3GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX3GCR4_DXREFSSELRANGE_MASK) #define DDRPHY_DX3GCR4_DXREFESEL_MASK (0x7F0000U) #define DDRPHY_DX3GCR4_DXREFESEL_SHIFT (16U) /*! DXREFESEL - Byte Lane External VREF Select */ #define DDRPHY_DX3GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX3GCR4_DXREFESEL_MASK) #define DDRPHY_DX3GCR4_DXREFESELRANGE_MASK (0x800000U) #define DDRPHY_DX3GCR4_DXREFESELRANGE_SHIFT (23U) /*! DXREFESELRANGE - External VREF generator REFSEL range select */ #define DDRPHY_DX3GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX3GCR4_DXREFESELRANGE_MASK) #define DDRPHY_DX3GCR4_RESERVED_24_MASK (0x1000000U) #define DDRPHY_DX3GCR4_RESERVED_24_SHIFT (24U) /*! RESERVED_24 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX3GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX3GCR4_RESERVED_24_MASK) #define DDRPHY_DX3GCR4_DXREFSEN_MASK (0x2000000U) #define DDRPHY_DX3GCR4_DXREFSEN_SHIFT (25U) /*! DXREFSEN - Byte Lane Single-End VREF Enable */ #define DDRPHY_DX3GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFSEN_MASK) #define DDRPHY_DX3GCR4_DXREFEEN_MASK (0xC000000U) #define DDRPHY_DX3GCR4_DXREFEEN_SHIFT (26U) /*! DXREFEEN - Byte Lane Internal VREF Enable */ #define DDRPHY_DX3GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFEEN_MASK) #define DDRPHY_DX3GCR4_DXREFPEN_MASK (0x10000000U) #define DDRPHY_DX3GCR4_DXREFPEN_SHIFT (28U) /*! DXREFPEN - Byte Lane VREF Pad Enable */ #define DDRPHY_DX3GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFPEN_MASK) #define DDRPHY_DX3GCR4_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DX3GCR4_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs) */ #define DDRPHY_DX3GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX3GCR4_RESERVED_31_29_MASK) /*! @} */ /*! @name DX3GCR5 - DATX8 n General Configuration Register 5 */ /*! @{ */ #define DDRPHY_DX3GCR5_DXREFISELR0_MASK (0x7FU) #define DDRPHY_DX3GCR5_DXREFISELR0_SHIFT (0U) /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0 */ #define DDRPHY_DX3GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR0_MASK) #define DDRPHY_DX3GCR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX3GCR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX3GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_7_MASK) #define DDRPHY_DX3GCR5_DXREFISELR1_MASK (0x7F00U) #define DDRPHY_DX3GCR5_DXREFISELR1_SHIFT (8U) /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1 */ #define DDRPHY_DX3GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR1_MASK) #define DDRPHY_DX3GCR5_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX3GCR5_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX3GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_15_MASK) #define DDRPHY_DX3GCR5_DXREFISELR2_MASK (0x7F0000U) #define DDRPHY_DX3GCR5_DXREFISELR2_SHIFT (16U) /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2 */ #define DDRPHY_DX3GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR2_MASK) #define DDRPHY_DX3GCR5_RESERVED_23_MASK (0x800000U) #define DDRPHY_DX3GCR5_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX3GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_23_MASK) #define DDRPHY_DX3GCR5_DXREFISELR3_MASK (0x7F000000U) #define DDRPHY_DX3GCR5_DXREFISELR3_SHIFT (24U) /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3 */ #define DDRPHY_DX3GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR3_MASK) #define DDRPHY_DX3GCR5_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX3GCR5_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX3GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_31_MASK) /*! @} */ /*! @name DX3GCR6 - DATX8 n General Configuration Register 6 */ /*! @{ */ #define DDRPHY_DX3GCR6_DXDQVREFR0_MASK (0x3FU) #define DDRPHY_DX3GCR6_DXDQVREFR0_SHIFT (0U) /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0 */ #define DDRPHY_DX3GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR0_MASK) #define DDRPHY_DX3GCR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3GCR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX3GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_7_6_MASK) #define DDRPHY_DX3GCR6_DXDQVREFR1_MASK (0x3F00U) #define DDRPHY_DX3GCR6_DXDQVREFR1_SHIFT (8U) /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1 */ #define DDRPHY_DX3GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR1_MASK) #define DDRPHY_DX3GCR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3GCR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX3GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_15_14_MASK) #define DDRPHY_DX3GCR6_DXDQVREFR2_MASK (0x3F0000U) #define DDRPHY_DX3GCR6_DXDQVREFR2_SHIFT (16U) /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2 */ #define DDRPHY_DX3GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR2_MASK) #define DDRPHY_DX3GCR6_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX3GCR6_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX3GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_23_22_MASK) #define DDRPHY_DX3GCR6_DXDQVREFR3_MASK (0x3F000000U) #define DDRPHY_DX3GCR6_DXDQVREFR3_SHIFT (24U) /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3 */ #define DDRPHY_DX3GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR3_MASK) #define DDRPHY_DX3GCR6_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX3GCR6_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX3GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_31_30_MASK) /*! @} */ /*! @name DX3GCR7 - DATX8 n General Configuration Register 7 */ /*! @{ */ #define DDRPHY_DX3GCR7_DCALSVAL_MASK (0x1FFU) #define DDRPHY_DX3GCR7_DCALSVAL_SHIFT (0U) /*! DCALSVAL - DDL Calibration Starting Value */ #define DDRPHY_DX3GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX3GCR7_DCALSVAL_MASK) #define DDRPHY_DX3GCR7_DCALTYPE_MASK (0x200U) #define DDRPHY_DX3GCR7_DCALTYPE_SHIFT (9U) /*! DCALTYPE - DDL Calibration Type */ #define DDRPHY_DX3GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX3GCR7_DCALTYPE_MASK) #define DDRPHY_DX3GCR7_RESERVED_17_10_MASK (0x3FC00U) #define DDRPHY_DX3GCR7_RESERVED_17_10_SHIFT (10U) /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX3GCR7_RESERVED_17_10_MASK) #define DDRPHY_DX3GCR7_RESERVED_18_MASK (0x40000U) #define DDRPHY_DX3GCR7_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX3GCR7_RESERVED_18_MASK) #define DDRPHY_DX3GCR7_RESERVED_31_19_MASK (0xFFF80000U) #define DDRPHY_DX3GCR7_RESERVED_31_19_SHIFT (19U) /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX3GCR7_RESERVED_31_19_MASK) /*! @} */ /*! @name DX3GCR8 - DATX8 n General Configuration Register 8 */ /*! @{ */ #define DDRPHY_DX3GCR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX3GCR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_5_0_MASK) #define DDRPHY_DX3GCR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3GCR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_7_6_MASK) #define DDRPHY_DX3GCR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX3GCR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_13_8_MASK) #define DDRPHY_DX3GCR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3GCR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_15_14_MASK) #define DDRPHY_DX3GCR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX3GCR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_21_16_MASK) #define DDRPHY_DX3GCR8_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX3GCR8_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_23_22_MASK) #define DDRPHY_DX3GCR8_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX3GCR8_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_29_24_MASK) #define DDRPHY_DX3GCR8_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX3GCR8_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_31_30_MASK) /*! @} */ /*! @name DX3GCR9 - DATX8 n General Configuration Register 9 */ /*! @{ */ #define DDRPHY_DX3GCR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX3GCR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_5_0_MASK) #define DDRPHY_DX3GCR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3GCR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_7_6_MASK) #define DDRPHY_DX3GCR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX3GCR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_13_8_MASK) #define DDRPHY_DX3GCR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3GCR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_15_14_MASK) #define DDRPHY_DX3GCR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX3GCR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_21_16_MASK) #define DDRPHY_DX3GCR9_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX3GCR9_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_23_22_MASK) #define DDRPHY_DX3GCR9_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX3GCR9_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_29_24_MASK) #define DDRPHY_DX3GCR9_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX3GCR9_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_31_30_MASK) /*! @} */ /*! @name DX3DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */ /*! @{ */ #define DDRPHY_DX3DQMAP0_DQ0MAP_MASK (0xFU) #define DDRPHY_DX3DQMAP0_DQ0MAP_SHIFT (0U) /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index */ #define DDRPHY_DX3DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ0MAP_MASK) #define DDRPHY_DX3DQMAP0_DQ1MAP_MASK (0xF0U) #define DDRPHY_DX3DQMAP0_DQ1MAP_SHIFT (4U) /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index */ #define DDRPHY_DX3DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ1MAP_MASK) #define DDRPHY_DX3DQMAP0_DQ2MAP_MASK (0xF00U) #define DDRPHY_DX3DQMAP0_DQ2MAP_SHIFT (8U) /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index */ #define DDRPHY_DX3DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ2MAP_MASK) #define DDRPHY_DX3DQMAP0_DQ3MAP_MASK (0xF000U) #define DDRPHY_DX3DQMAP0_DQ3MAP_SHIFT (12U) /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index */ #define DDRPHY_DX3DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ3MAP_MASK) #define DDRPHY_DX3DQMAP0_DQ4MAP_MASK (0xF0000U) #define DDRPHY_DX3DQMAP0_DQ4MAP_SHIFT (16U) /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index */ #define DDRPHY_DX3DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ4MAP_MASK) #define DDRPHY_DX3DQMAP0_RESERVED_30_20_MASK (0x7FF00000U) #define DDRPHY_DX3DQMAP0_RESERVED_30_20_SHIFT (20U) /*! RESERVED_30_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX3DQMAP0_RESERVED_30_20_MASK) #define DDRPHY_DX3DQMAP0_MAPOK_MASK (0x80000000U) #define DDRPHY_DX3DQMAP0_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX3DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX3DQMAP0_MAPOK_MASK) /*! @} */ /*! @name DX3DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */ /*! @{ */ #define DDRPHY_DX3DQMAP1_DQ5MAP_MASK (0xFU) #define DDRPHY_DX3DQMAP1_DQ5MAP_SHIFT (0U) /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index */ #define DDRPHY_DX3DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX3DQMAP1_DQ5MAP_MASK) #define DDRPHY_DX3DQMAP1_DQ6MAP_MASK (0xF0U) #define DDRPHY_DX3DQMAP1_DQ6MAP_SHIFT (4U) /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index */ #define DDRPHY_DX3DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX3DQMAP1_DQ6MAP_MASK) #define DDRPHY_DX3DQMAP1_DQ7MAP_MASK (0xF00U) #define DDRPHY_DX3DQMAP1_DQ7MAP_SHIFT (8U) /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index */ #define DDRPHY_DX3DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX3DQMAP1_DQ7MAP_MASK) #define DDRPHY_DX3DQMAP1_DMMAP_MASK (0xF000U) #define DDRPHY_DX3DQMAP1_DMMAP_SHIFT (12U) /*! DMMAP - DM bit DATX8 slice mapping index */ #define DDRPHY_DX3DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX3DQMAP1_DMMAP_MASK) #define DDRPHY_DX3DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U) #define DDRPHY_DX3DQMAP1_RESERVED_30_16_SHIFT (16U) /*! RESERVED_30_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX3DQMAP1_RESERVED_30_16_MASK) #define DDRPHY_DX3DQMAP1_MAPOK_MASK (0x80000000U) #define DDRPHY_DX3DQMAP1_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX3DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX3DQMAP1_MAPOK_MASK) /*! @} */ /*! @name DX3BDLR0 - DATX8 n Bit Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX3BDLR0_DQ0WBD_MASK (0x3FU) #define DDRPHY_DX3BDLR0_DQ0WBD_SHIFT (0U) /*! DQ0WBD - DQ0 Write Bit Delay */ #define DDRPHY_DX3BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ0WBD_MASK) #define DDRPHY_DX3BDLR0_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3BDLR0_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_7_6_MASK) #define DDRPHY_DX3BDLR0_DQ1WBD_MASK (0x3F00U) #define DDRPHY_DX3BDLR0_DQ1WBD_SHIFT (8U) /*! DQ1WBD - DQ1 Write Bit Delay */ #define DDRPHY_DX3BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ1WBD_MASK) #define DDRPHY_DX3BDLR0_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3BDLR0_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_15_14_MASK) #define DDRPHY_DX3BDLR0_DQ2WBD_MASK (0x3F0000U) #define DDRPHY_DX3BDLR0_DQ2WBD_SHIFT (16U) /*! DQ2WBD - DQ2 Write Bit Delay */ #define DDRPHY_DX3BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ2WBD_MASK) #define DDRPHY_DX3BDLR0_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX3BDLR0_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_23_22_MASK) #define DDRPHY_DX3BDLR0_DQ3WBD_MASK (0x3F000000U) #define DDRPHY_DX3BDLR0_DQ3WBD_SHIFT (24U) /*! DQ3WBD - DQ3 Write Bit Delay */ #define DDRPHY_DX3BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ3WBD_MASK) #define DDRPHY_DX3BDLR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX3BDLR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_31_30_MASK) /*! @} */ /*! @name DX3BDLR1 - DATX8 n Bit Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX3BDLR1_DQ4WBD_MASK (0x3FU) #define DDRPHY_DX3BDLR1_DQ4WBD_SHIFT (0U) /*! DQ4WBD - DQ4 Write Bit Delay */ #define DDRPHY_DX3BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ4WBD_MASK) #define DDRPHY_DX3BDLR1_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3BDLR1_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_7_6_MASK) #define DDRPHY_DX3BDLR1_DQ5WBD_MASK (0x3F00U) #define DDRPHY_DX3BDLR1_DQ5WBD_SHIFT (8U) /*! DQ5WBD - DQ5 Write Bit Delay */ #define DDRPHY_DX3BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ5WBD_MASK) #define DDRPHY_DX3BDLR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3BDLR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_15_14_MASK) #define DDRPHY_DX3BDLR1_DQ6WBD_MASK (0x3F0000U) #define DDRPHY_DX3BDLR1_DQ6WBD_SHIFT (16U) /*! DQ6WBD - DQ6 Write Bit Delay */ #define DDRPHY_DX3BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ6WBD_MASK) #define DDRPHY_DX3BDLR1_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX3BDLR1_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_23_22_MASK) #define DDRPHY_DX3BDLR1_DQ7WBD_MASK (0x3F000000U) #define DDRPHY_DX3BDLR1_DQ7WBD_SHIFT (24U) /*! DQ7WBD - DQ7 Write Bit Delay */ #define DDRPHY_DX3BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ7WBD_MASK) #define DDRPHY_DX3BDLR1_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX3BDLR1_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_31_30_MASK) /*! @} */ /*! @name DX3BDLR2 - DATX8 n Bit Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX3BDLR2_DMWBD_MASK (0x3FU) #define DDRPHY_DX3BDLR2_DMWBD_SHIFT (0U) /*! DMWBD - DM Write Bit Delay */ #define DDRPHY_DX3BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DMWBD_SHIFT)) & DDRPHY_DX3BDLR2_DMWBD_MASK) #define DDRPHY_DX3BDLR2_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3BDLR2_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_7_6_MASK) #define DDRPHY_DX3BDLR2_DSWBD_MASK (0x3F00U) #define DDRPHY_DX3BDLR2_DSWBD_SHIFT (8U) /*! DSWBD - DQS Write Bit Delay */ #define DDRPHY_DX3BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DSWBD_SHIFT)) & DDRPHY_DX3BDLR2_DSWBD_MASK) #define DDRPHY_DX3BDLR2_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3BDLR2_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_15_14_MASK) #define DDRPHY_DX3BDLR2_DSOEBD_MASK (0x3F0000U) #define DDRPHY_DX3BDLR2_DSOEBD_SHIFT (16U) /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay */ #define DDRPHY_DX3BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX3BDLR2_DSOEBD_MASK) #define DDRPHY_DX3BDLR2_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX3BDLR2_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_23_22_MASK) #define DDRPHY_DX3BDLR2_DSNWBD_MASK (0x3F000000U) #define DDRPHY_DX3BDLR2_DSNWBD_SHIFT (24U) /*! DSNWBD - DQSN Write Bit Delay */ #define DDRPHY_DX3BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX3BDLR2_DSNWBD_MASK) #define DDRPHY_DX3BDLR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX3BDLR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_31_30_MASK) /*! @} */ /*! @name DX3BDLR3 - DATX8 n Bit Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX3BDLR3_DQ0RBD_MASK (0x3FU) #define DDRPHY_DX3BDLR3_DQ0RBD_SHIFT (0U) /*! DQ0RBD - DQ0 Read Bit Delay */ #define DDRPHY_DX3BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ0RBD_MASK) #define DDRPHY_DX3BDLR3_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3BDLR3_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_7_6_MASK) #define DDRPHY_DX3BDLR3_DQ1RBD_MASK (0x3F00U) #define DDRPHY_DX3BDLR3_DQ1RBD_SHIFT (8U) /*! DQ1RBD - DQ1 Read Bit Delay */ #define DDRPHY_DX3BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ1RBD_MASK) #define DDRPHY_DX3BDLR3_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3BDLR3_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_15_14_MASK) #define DDRPHY_DX3BDLR3_DQ2RBD_MASK (0x3F0000U) #define DDRPHY_DX3BDLR3_DQ2RBD_SHIFT (16U) /*! DQ2RBD - DQ2 Read Bit Delay */ #define DDRPHY_DX3BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ2RBD_MASK) #define DDRPHY_DX3BDLR3_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX3BDLR3_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_23_22_MASK) #define DDRPHY_DX3BDLR3_DQ3RBD_MASK (0x3F000000U) #define DDRPHY_DX3BDLR3_DQ3RBD_SHIFT (24U) /*! DQ3RBD - DQ3 Read Bit Delay */ #define DDRPHY_DX3BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ3RBD_MASK) #define DDRPHY_DX3BDLR3_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX3BDLR3_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_31_30_MASK) /*! @} */ /*! @name DX3BDLR4 - DATX8 n Bit Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX3BDLR4_DQ4RBD_MASK (0x3FU) #define DDRPHY_DX3BDLR4_DQ4RBD_SHIFT (0U) /*! DQ4RBD - DQ4 Read Bit Delay */ #define DDRPHY_DX3BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ4RBD_MASK) #define DDRPHY_DX3BDLR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3BDLR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_7_6_MASK) #define DDRPHY_DX3BDLR4_DQ5RBD_MASK (0x3F00U) #define DDRPHY_DX3BDLR4_DQ5RBD_SHIFT (8U) /*! DQ5RBD - DQ5 Read Bit Delay */ #define DDRPHY_DX3BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ5RBD_MASK) #define DDRPHY_DX3BDLR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3BDLR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_15_14_MASK) #define DDRPHY_DX3BDLR4_DQ6RBD_MASK (0x3F0000U) #define DDRPHY_DX3BDLR4_DQ6RBD_SHIFT (16U) /*! DQ6RBD - DQ6 Read Bit Delay */ #define DDRPHY_DX3BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ6RBD_MASK) #define DDRPHY_DX3BDLR4_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX3BDLR4_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_23_22_MASK) #define DDRPHY_DX3BDLR4_DQ7RBD_MASK (0x3F000000U) #define DDRPHY_DX3BDLR4_DQ7RBD_SHIFT (24U) /*! DQ7RBD - DQ7 Read Bit Delay */ #define DDRPHY_DX3BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ7RBD_MASK) #define DDRPHY_DX3BDLR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX3BDLR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_31_30_MASK) /*! @} */ /*! @name DX3BDLR5 - DATX8 n Bit Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX3BDLR5_DMRBD_MASK (0x3FU) #define DDRPHY_DX3BDLR5_DMRBD_SHIFT (0U) /*! DMRBD - DM Read Bit Delay */ #define DDRPHY_DX3BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR5_DMRBD_SHIFT)) & DDRPHY_DX3BDLR5_DMRBD_MASK) #define DDRPHY_DX3BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U) #define DDRPHY_DX3BDLR5_RESERVED_31_6_SHIFT (6U) /*! RESERVED_31_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX3BDLR5_RESERVED_31_6_MASK) /*! @} */ /*! @name DX3BDLR6 - DATX8 n Bit Delay Line Register 6 */ /*! @{ */ #define DDRPHY_DX3BDLR6_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_DX3BDLR6_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX3BDLR6_RESERVED_7_0_MASK) #define DDRPHY_DX3BDLR6_PDRBD_MASK (0x3F00U) #define DDRPHY_DX3BDLR6_PDRBD_SHIFT (8U) /*! PDRBD - Power down receiver Bit Delay */ #define DDRPHY_DX3BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_PDRBD_SHIFT)) & DDRPHY_DX3BDLR6_PDRBD_MASK) #define DDRPHY_DX3BDLR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3BDLR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR6_RESERVED_15_14_MASK) #define DDRPHY_DX3BDLR6_TERBD_MASK (0x3F0000U) #define DDRPHY_DX3BDLR6_TERBD_SHIFT (16U) /*! TERBD - Termination Enable Bit Delay */ #define DDRPHY_DX3BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_TERBD_SHIFT)) & DDRPHY_DX3BDLR6_TERBD_MASK) #define DDRPHY_DX3BDLR6_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX3BDLR6_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR6_RESERVED_31_22_MASK) /*! @} */ /*! @name DX3BDLR7 - DATX8 n Bit Delay Line Register 7 */ /*! @{ */ #define DDRPHY_DX3BDLR7_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX3BDLR7_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_5_0_MASK) #define DDRPHY_DX3BDLR7_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3BDLR7_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_7_6_MASK) #define DDRPHY_DX3BDLR7_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX3BDLR7_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_13_8_MASK) #define DDRPHY_DX3BDLR7_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3BDLR7_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_15_14_MASK) #define DDRPHY_DX3BDLR7_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX3BDLR7_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_21_16_MASK) #define DDRPHY_DX3BDLR7_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX3BDLR7_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_31_22_MASK) /*! @} */ /*! @name DX3BDLR8 - DATX8 n Bit Delay Line Register 8 */ /*! @{ */ #define DDRPHY_DX3BDLR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX3BDLR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_5_0_MASK) #define DDRPHY_DX3BDLR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3BDLR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_7_6_MASK) #define DDRPHY_DX3BDLR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX3BDLR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_13_8_MASK) #define DDRPHY_DX3BDLR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3BDLR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_15_14_MASK) #define DDRPHY_DX3BDLR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX3BDLR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_21_16_MASK) #define DDRPHY_DX3BDLR8_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX3BDLR8_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_31_22_MASK) /*! @} */ /*! @name DX3BDLR9 - DATX8 n Bit Delay Line Register 9 */ /*! @{ */ #define DDRPHY_DX3BDLR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX3BDLR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_5_0_MASK) #define DDRPHY_DX3BDLR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX3BDLR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_7_6_MASK) #define DDRPHY_DX3BDLR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX3BDLR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_13_8_MASK) #define DDRPHY_DX3BDLR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX3BDLR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_15_14_MASK) #define DDRPHY_DX3BDLR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX3BDLR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_21_16_MASK) #define DDRPHY_DX3BDLR9_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX3BDLR9_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_31_22_MASK) /*! @} */ /*! @name DX3LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX3LCDLR0_WLD_MASK (0x1FFU) #define DDRPHY_DX3LCDLR0_WLD_SHIFT (0U) /*! WLD - Write Leveling Delay */ #define DDRPHY_DX3LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_WLD_SHIFT)) & DDRPHY_DX3LCDLR0_WLD_MASK) #define DDRPHY_DX3LCDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX3LCDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX3LCDLR0_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX3LCDLR0_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR0_RESERVED_24_16_MASK) #define DDRPHY_DX3LCDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX3LCDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX3LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX3LCDLR1_WDQD_MASK (0x1FFU) #define DDRPHY_DX3LCDLR1_WDQD_SHIFT (0U) /*! WDQD - Write Data Delay */ #define DDRPHY_DX3LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_WDQD_SHIFT)) & DDRPHY_DX3LCDLR1_WDQD_MASK) #define DDRPHY_DX3LCDLR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX3LCDLR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR1_RESERVED_15_9_MASK) #define DDRPHY_DX3LCDLR1_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX3LCDLR1_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR1_RESERVED_24_16_MASK) #define DDRPHY_DX3LCDLR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX3LCDLR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX3LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX3LCDLR2_DQSGD_MASK (0x1FFU) #define DDRPHY_DX3LCDLR2_DQSGD_SHIFT (0U) /*! DQSGD - Read DQS Gating Delay */ #define DDRPHY_DX3LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX3LCDLR2_DQSGD_MASK) #define DDRPHY_DX3LCDLR2_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX3LCDLR2_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR2_RESERVED_15_9_MASK) #define DDRPHY_DX3LCDLR2_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX3LCDLR2_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR2_RESERVED_24_16_MASK) #define DDRPHY_DX3LCDLR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX3LCDLR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR2_RESERVED_31_25_MASK) /*! @} */ /*! @name DX3LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX3LCDLR3_RDQSD_MASK (0x1FFU) #define DDRPHY_DX3LCDLR3_RDQSD_SHIFT (0U) /*! RDQSD - Read DQS Delay */ #define DDRPHY_DX3LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX3LCDLR3_RDQSD_MASK) #define DDRPHY_DX3LCDLR3_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX3LCDLR3_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR3_RESERVED_15_9_MASK) #define DDRPHY_DX3LCDLR3_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX3LCDLR3_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR3_RESERVED_24_16_MASK) #define DDRPHY_DX3LCDLR3_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX3LCDLR3_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR3_RESERVED_31_25_MASK) /*! @} */ /*! @name DX3LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX3LCDLR4_RDQSND_MASK (0x1FFU) #define DDRPHY_DX3LCDLR4_RDQSND_SHIFT (0U) /*! RDQSND - Read DQSN Delay */ #define DDRPHY_DX3LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX3LCDLR4_RDQSND_MASK) #define DDRPHY_DX3LCDLR4_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX3LCDLR4_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR4_RESERVED_15_9_MASK) #define DDRPHY_DX3LCDLR4_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX3LCDLR4_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR4_RESERVED_24_16_MASK) #define DDRPHY_DX3LCDLR4_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX3LCDLR4_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR4_RESERVED_31_25_MASK) /*! @} */ /*! @name DX3LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX3LCDLR5_DQSGSD_MASK (0x1FFU) #define DDRPHY_DX3LCDLR5_DQSGSD_SHIFT (0U) /*! DQSGSD - DQS Gating Status Delay */ #define DDRPHY_DX3LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX3LCDLR5_DQSGSD_MASK) #define DDRPHY_DX3LCDLR5_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX3LCDLR5_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR5_RESERVED_15_9_MASK) #define DDRPHY_DX3LCDLR5_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX3LCDLR5_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR5_RESERVED_24_16_MASK) #define DDRPHY_DX3LCDLR5_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX3LCDLR5_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR5_RESERVED_31_25_MASK) /*! @} */ /*! @name DX3MDLR0 - DATX8 n Master Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX3MDLR0_IPRD_MASK (0x1FFU) #define DDRPHY_DX3MDLR0_IPRD_SHIFT (0U) /*! IPRD - Initial Period */ #define DDRPHY_DX3MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_IPRD_SHIFT)) & DDRPHY_DX3MDLR0_IPRD_MASK) #define DDRPHY_DX3MDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX3MDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX3MDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX3MDLR0_TPRD_MASK (0x1FF0000U) #define DDRPHY_DX3MDLR0_TPRD_SHIFT (16U) /*! TPRD - Target Period */ #define DDRPHY_DX3MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_TPRD_SHIFT)) & DDRPHY_DX3MDLR0_TPRD_MASK) #define DDRPHY_DX3MDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX3MDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX3MDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX3MDLR1 - DATX8 n Master Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX3MDLR1_MDLD_MASK (0x1FFU) #define DDRPHY_DX3MDLR1_MDLD_SHIFT (0U) /*! MDLD - MDL Delay */ #define DDRPHY_DX3MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR1_MDLD_SHIFT)) & DDRPHY_DX3MDLR1_MDLD_MASK) #define DDRPHY_DX3MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U) #define DDRPHY_DX3MDLR1_RESERVED_31_9_SHIFT (9U) /*! RESERVED_31_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX3MDLR1_RESERVED_31_9_MASK) /*! @} */ /*! @name DX3GTR0 - DATX8 n General Timing Register 0 */ /*! @{ */ #define DDRPHY_DX3GTR0_DGSL_MASK (0x1FU) #define DDRPHY_DX3GTR0_DGSL_SHIFT (0U) /*! DGSL - DQS Gating System Latency */ #define DDRPHY_DX3GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_DGSL_SHIFT)) & DDRPHY_DX3GTR0_DGSL_MASK) #define DDRPHY_DX3GTR0_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DX3GTR0_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_7_5_MASK) #define DDRPHY_DX3GTR0_RESERVED_12_8_MASK (0x1F00U) #define DDRPHY_DX3GTR0_RESERVED_12_8_SHIFT (8U) /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_12_8_MASK) #define DDRPHY_DX3GTR0_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_DX3GTR0_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_15_13_MASK) #define DDRPHY_DX3GTR0_WLSL_MASK (0xF0000U) #define DDRPHY_DX3GTR0_WLSL_SHIFT (16U) /*! WLSL - Write Leveling System Latency */ #define DDRPHY_DX3GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_WLSL_SHIFT)) & DDRPHY_DX3GTR0_WLSL_MASK) #define DDRPHY_DX3GTR0_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX3GTR0_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX3GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_23_20_MASK) #define DDRPHY_DX3GTR0_WDQSL_MASK (0x7000000U) #define DDRPHY_DX3GTR0_WDQSL_SHIFT (24U) /*! WDQSL - DQ Write Path Latency Pipeline */ #define DDRPHY_DX3GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_WDQSL_SHIFT)) & DDRPHY_DX3GTR0_WDQSL_MASK) #define DDRPHY_DX3GTR0_RESERVED_31_24_MASK (0xF8000000U) #define DDRPHY_DX3GTR0_RESERVED_31_24_SHIFT (27U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_31_24_MASK) /*! @} */ /*! @name DX3RSR0 - DATX8 n Rank Status Register 0 */ /*! @{ */ #define DDRPHY_DX3RSR0_QSGERR_MASK (0xFFFFU) #define DDRPHY_DX3RSR0_QSGERR_SHIFT (0U) /*! QSGERR - DQS Gate Training Error */ #define DDRPHY_DX3RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR0_QSGERR_SHIFT)) & DDRPHY_DX3RSR0_QSGERR_MASK) #define DDRPHY_DX3RSR0_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX3RSR0_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR0_RESERVED_31_16_MASK) /*! @} */ /*! @name DX3RSR1 - DATX8 n Rank Status Register 1 */ /*! @{ */ #define DDRPHY_DX3RSR1_RDLVLERR_MASK (0xFFFFU) #define DDRPHY_DX3RSR1_RDLVLERR_SHIFT (0U) /*! RDLVLERR - Read Leveling Error */ #define DDRPHY_DX3RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX3RSR1_RDLVLERR_MASK) #define DDRPHY_DX3RSR1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX3RSR1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR1_RESERVED_31_16_MASK) /*! @} */ /*! @name DX3RSR2 - DATX8 n Rank Status Register 2 */ /*! @{ */ #define DDRPHY_DX3RSR2_WLAWN_MASK (0xFFFFU) #define DDRPHY_DX3RSR2_WLAWN_SHIFT (0U) /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning */ #define DDRPHY_DX3RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR2_WLAWN_SHIFT)) & DDRPHY_DX3RSR2_WLAWN_MASK) #define DDRPHY_DX3RSR2_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX3RSR2_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR2_RESERVED_31_16_MASK) /*! @} */ /*! @name DX3RSR3 - DATX8 n Rank Status Register 3 */ /*! @{ */ #define DDRPHY_DX3RSR3_WLAERR_MASK (0xFFFFU) #define DDRPHY_DX3RSR3_WLAERR_SHIFT (0U) /*! WLAERR - Write Leveling Adjustment Error */ #define DDRPHY_DX3RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR3_WLAERR_SHIFT)) & DDRPHY_DX3RSR3_WLAERR_MASK) #define DDRPHY_DX3RSR3_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX3RSR3_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR3_RESERVED_31_16_MASK) /*! @} */ /*! @name DX3GSR0 - DATX8 n General Status Register 0 */ /*! @{ */ #define DDRPHY_DX3GSR0_WDQCAL_MASK (0x1U) #define DDRPHY_DX3GSR0_WDQCAL_SHIFT (0U) /*! WDQCAL - Write DQ Calibration */ #define DDRPHY_DX3GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WDQCAL_SHIFT)) & DDRPHY_DX3GSR0_WDQCAL_MASK) #define DDRPHY_DX3GSR0_RDQSCAL_MASK (0x2U) #define DDRPHY_DX3GSR0_RDQSCAL_SHIFT (1U) /*! RDQSCAL - Read DQS Calibration */ #define DDRPHY_DX3GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX3GSR0_RDQSCAL_MASK) #define DDRPHY_DX3GSR0_RDQSNCAL_MASK (0x4U) #define DDRPHY_DX3GSR0_RDQSNCAL_SHIFT (2U) /*! RDQSNCAL - Read DQS# Calibration */ #define DDRPHY_DX3GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX3GSR0_RDQSNCAL_MASK) #define DDRPHY_DX3GSR0_GDQSCAL_MASK (0x8U) #define DDRPHY_DX3GSR0_GDQSCAL_SHIFT (3U) /*! GDQSCAL - Read DQS gating Calibration */ #define DDRPHY_DX3GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX3GSR0_GDQSCAL_MASK) #define DDRPHY_DX3GSR0_WLCAL_MASK (0x10U) #define DDRPHY_DX3GSR0_WLCAL_SHIFT (4U) /*! WLCAL - Write Leveling Calibration */ #define DDRPHY_DX3GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLCAL_SHIFT)) & DDRPHY_DX3GSR0_WLCAL_MASK) #define DDRPHY_DX3GSR0_WLDONE_MASK (0x20U) #define DDRPHY_DX3GSR0_WLDONE_SHIFT (5U) /*! WLDONE - Write Leveling Done */ #define DDRPHY_DX3GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLDONE_SHIFT)) & DDRPHY_DX3GSR0_WLDONE_MASK) #define DDRPHY_DX3GSR0_WLERR_MASK (0x40U) #define DDRPHY_DX3GSR0_WLERR_SHIFT (6U) /*! WLERR - Write Leveling Error */ #define DDRPHY_DX3GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLERR_SHIFT)) & DDRPHY_DX3GSR0_WLERR_MASK) #define DDRPHY_DX3GSR0_WLPRD_MASK (0xFF80U) #define DDRPHY_DX3GSR0_WLPRD_SHIFT (7U) /*! WLPRD - Write Leveling Period */ #define DDRPHY_DX3GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLPRD_SHIFT)) & DDRPHY_DX3GSR0_WLPRD_MASK) #define DDRPHY_DX3GSR0_DPLOCK_MASK (0x10000U) #define DDRPHY_DX3GSR0_DPLOCK_SHIFT (16U) /*! DPLOCK - DATX8 PLL Lock */ #define DDRPHY_DX3GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_DPLOCK_SHIFT)) & DDRPHY_DX3GSR0_DPLOCK_MASK) #define DDRPHY_DX3GSR0_GDQSPRD_MASK (0x3FE0000U) #define DDRPHY_DX3GSR0_GDQSPRD_SHIFT (17U) /*! GDQSPRD - Read DQS gating Period */ #define DDRPHY_DX3GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX3GSR0_GDQSPRD_MASK) #define DDRPHY_DX3GSR0_RESERVED_29_26_MASK (0x3C000000U) #define DDRPHY_DX3GSR0_RESERVED_29_26_SHIFT (26U) /*! RESERVED_29_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX3GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX3GSR0_RESERVED_29_26_MASK) #define DDRPHY_DX3GSR0_WLDQ_MASK (0x40000000U) #define DDRPHY_DX3GSR0_WLDQ_SHIFT (30U) /*! WLDQ - Write Leveling DQ Status */ #define DDRPHY_DX3GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLDQ_SHIFT)) & DDRPHY_DX3GSR0_WLDQ_MASK) #define DDRPHY_DX3GSR0_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX3GSR0_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX3GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX3GSR0_RESERVED_31_MASK) /*! @} */ /*! @name DX3GSR1 - DATX8 n General Status Register 1 */ /*! @{ */ #define DDRPHY_DX3GSR1_DLTDONE_MASK (0x1U) #define DDRPHY_DX3GSR1_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done */ #define DDRPHY_DX3GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR1_DLTDONE_SHIFT)) & DDRPHY_DX3GSR1_DLTDONE_MASK) #define DDRPHY_DX3GSR1_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_DX3GSR1_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code */ #define DDRPHY_DX3GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR1_DLTCODE_SHIFT)) & DDRPHY_DX3GSR1_DLTCODE_MASK) #define DDRPHY_DX3GSR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX3GSR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX3GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX3GSR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX3GSR2 - DATX8 n General Status Register 2 */ /*! @{ */ #define DDRPHY_DX3GSR2_RDERR_MASK (0x1U) #define DDRPHY_DX3GSR2_RDERR_SHIFT (0U) /*! RDERR - Read Bit Deskew Error */ #define DDRPHY_DX3GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_RDERR_SHIFT)) & DDRPHY_DX3GSR2_RDERR_MASK) #define DDRPHY_DX3GSR2_RDWN_MASK (0x2U) #define DDRPHY_DX3GSR2_RDWN_SHIFT (1U) /*! RDWN - Read Bit Deskew Warning */ #define DDRPHY_DX3GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_RDWN_SHIFT)) & DDRPHY_DX3GSR2_RDWN_MASK) #define DDRPHY_DX3GSR2_WDERR_MASK (0x4U) #define DDRPHY_DX3GSR2_WDERR_SHIFT (2U) /*! WDERR - Write Bit Deskew Error */ #define DDRPHY_DX3GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WDERR_SHIFT)) & DDRPHY_DX3GSR2_WDERR_MASK) #define DDRPHY_DX3GSR2_WDWN_MASK (0x8U) #define DDRPHY_DX3GSR2_WDWN_SHIFT (3U) /*! WDWN - Write Bit Deskew Warning */ #define DDRPHY_DX3GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WDWN_SHIFT)) & DDRPHY_DX3GSR2_WDWN_MASK) #define DDRPHY_DX3GSR2_REERR_MASK (0x10U) #define DDRPHY_DX3GSR2_REERR_SHIFT (4U) /*! REERR - Read Eye Centering Error */ #define DDRPHY_DX3GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_REERR_SHIFT)) & DDRPHY_DX3GSR2_REERR_MASK) #define DDRPHY_DX3GSR2_REWN_MASK (0x20U) #define DDRPHY_DX3GSR2_REWN_SHIFT (5U) /*! REWN - Read Eye Centering Warning */ #define DDRPHY_DX3GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_REWN_SHIFT)) & DDRPHY_DX3GSR2_REWN_MASK) #define DDRPHY_DX3GSR2_WEERR_MASK (0x40U) #define DDRPHY_DX3GSR2_WEERR_SHIFT (6U) /*! WEERR - Write Eye Centering Error */ #define DDRPHY_DX3GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WEERR_SHIFT)) & DDRPHY_DX3GSR2_WEERR_MASK) #define DDRPHY_DX3GSR2_WEWN_MASK (0x80U) #define DDRPHY_DX3GSR2_WEWN_SHIFT (7U) /*! WEWN - Write Eye Centering Warning */ #define DDRPHY_DX3GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WEWN_SHIFT)) & DDRPHY_DX3GSR2_WEWN_MASK) #define DDRPHY_DX3GSR2_ESTAT_MASK (0xF00U) #define DDRPHY_DX3GSR2_ESTAT_SHIFT (8U) /*! ESTAT - Error Status */ #define DDRPHY_DX3GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_ESTAT_SHIFT)) & DDRPHY_DX3GSR2_ESTAT_MASK) #define DDRPHY_DX3GSR2_DQS2DQERR_MASK (0xFF000U) #define DDRPHY_DX3GSR2_DQS2DQERR_SHIFT (12U) /*! DQS2DQERR - Write DQS2DQ Training Error */ #define DDRPHY_DX3GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX3GSR2_DQS2DQERR_MASK) #define DDRPHY_DX3GSR2_SRDERR_MASK (0x100000U) #define DDRPHY_DX3GSR2_SRDERR_SHIFT (20U) /*! SRDERR - Static Read Error */ #define DDRPHY_DX3GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_SRDERR_SHIFT)) & DDRPHY_DX3GSR2_SRDERR_MASK) #define DDRPHY_DX3GSR2_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX3GSR2_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX3GSR2_RESERVED_21_MASK) #define DDRPHY_DX3GSR2_GSDQSCAL_MASK (0x400000U) #define DDRPHY_DX3GSR2_GSDQSCAL_SHIFT (22U) /*! GSDQSCAL - Read DQS Gating Status Calibration */ #define DDRPHY_DX3GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX3GSR2_GSDQSCAL_MASK) #define DDRPHY_DX3GSR2_GSDQSPRD_MASK (0xFF800000U) #define DDRPHY_DX3GSR2_GSDQSPRD_SHIFT (23U) /*! GSDQSPRD - Read DQS gating Status Period */ #define DDRPHY_DX3GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX3GSR2_GSDQSPRD_MASK) /*! @} */ /*! @name DX3GSR3 - DATX8 n General Status Register 3 */ /*! @{ */ #define DDRPHY_DX3GSR3_SRDPC_MASK (0x3U) #define DDRPHY_DX3GSR3_SRDPC_SHIFT (0U) /*! SRDPC - Static Read Delay Pass Count */ #define DDRPHY_DX3GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_SRDPC_SHIFT)) & DDRPHY_DX3GSR3_SRDPC_MASK) #define DDRPHY_DX3GSR3_RESERVED_7_2_MASK (0xFCU) #define DDRPHY_DX3GSR3_RESERVED_7_2_SHIFT (2U) /*! RESERVED_7_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX3GSR3_RESERVED_7_2_MASK) #define DDRPHY_DX3GSR3_HVERR_MASK (0xF00U) #define DDRPHY_DX3GSR3_HVERR_SHIFT (8U) /*! HVERR - Host VREF Training Error */ #define DDRPHY_DX3GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_HVERR_SHIFT)) & DDRPHY_DX3GSR3_HVERR_MASK) #define DDRPHY_DX3GSR3_HVWRN_MASK (0xF000U) #define DDRPHY_DX3GSR3_HVWRN_SHIFT (12U) /*! HVWRN - Host VREF Training Warning */ #define DDRPHY_DX3GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_HVWRN_SHIFT)) & DDRPHY_DX3GSR3_HVWRN_MASK) #define DDRPHY_DX3GSR3_DVERR_MASK (0xF0000U) #define DDRPHY_DX3GSR3_DVERR_SHIFT (16U) /*! DVERR - DRAM VREF Training Error */ #define DDRPHY_DX3GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_DVERR_SHIFT)) & DDRPHY_DX3GSR3_DVERR_MASK) #define DDRPHY_DX3GSR3_DVWRN_MASK (0xF00000U) #define DDRPHY_DX3GSR3_DVWRN_SHIFT (20U) /*! DVWRN - DRAM VREF Training Warning */ #define DDRPHY_DX3GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_DVWRN_SHIFT)) & DDRPHY_DX3GSR3_DVWRN_MASK) #define DDRPHY_DX3GSR3_ESTAT_MASK (0x7000000U) #define DDRPHY_DX3GSR3_ESTAT_SHIFT (24U) /*! ESTAT - VREF Training Error Status Code */ #define DDRPHY_DX3GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_ESTAT_SHIFT)) & DDRPHY_DX3GSR3_ESTAT_MASK) #define DDRPHY_DX3GSR3_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX3GSR3_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX3GSR3_RESERVED_31_27_MASK) /*! @} */ /*! @name DX3GSR4 - DATX8 n General Status Register 4 */ /*! @{ */ #define DDRPHY_DX3GSR4_RESERVED_0_MASK (0x1U) #define DDRPHY_DX3GSR4_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_0_MASK) #define DDRPHY_DX3GSR4_RESERVED_1_MASK (0x2U) #define DDRPHY_DX3GSR4_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_1_MASK) #define DDRPHY_DX3GSR4_RESERVED_2_MASK (0x4U) #define DDRPHY_DX3GSR4_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_2_MASK) #define DDRPHY_DX3GSR4_RESERVED_3_MASK (0x8U) #define DDRPHY_DX3GSR4_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_3_MASK) #define DDRPHY_DX3GSR4_RESERVED_4_MASK (0x10U) #define DDRPHY_DX3GSR4_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_4_MASK) #define DDRPHY_DX3GSR4_RESERVED_5_MASK (0x20U) #define DDRPHY_DX3GSR4_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_5_MASK) #define DDRPHY_DX3GSR4_RESERVED_6_MASK (0x40U) #define DDRPHY_DX3GSR4_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_6_MASK) #define DDRPHY_DX3GSR4_RESERVED_15_7_MASK (0xFF80U) #define DDRPHY_DX3GSR4_RESERVED_15_7_SHIFT (7U) /*! RESERVED_15_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_15_7_MASK) #define DDRPHY_DX3GSR4_RESERVED_16_MASK (0x10000U) #define DDRPHY_DX3GSR4_RESERVED_16_SHIFT (16U) /*! RESERVED_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_16_MASK) #define DDRPHY_DX3GSR4_RESERVED_25_17_MASK (0x3FE0000U) #define DDRPHY_DX3GSR4_RESERVED_25_17_SHIFT (17U) /*! RESERVED_25_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_25_17_MASK) #define DDRPHY_DX3GSR4_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_DX3GSR4_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX3GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_31_26_MASK) /*! @} */ /*! @name DX3GSR5 - DATX8 n General Status Register 5 */ /*! @{ */ #define DDRPHY_DX3GSR5_RESERVED_0_MASK (0x1U) #define DDRPHY_DX3GSR5_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_0_MASK) #define DDRPHY_DX3GSR5_RESERVED_1_MASK (0x2U) #define DDRPHY_DX3GSR5_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_1_MASK) #define DDRPHY_DX3GSR5_RESERVED_2_MASK (0x4U) #define DDRPHY_DX3GSR5_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_2_MASK) #define DDRPHY_DX3GSR5_RESERVED_3_MASK (0x8U) #define DDRPHY_DX3GSR5_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_3_MASK) #define DDRPHY_DX3GSR5_RESERVED_4_MASK (0x10U) #define DDRPHY_DX3GSR5_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_4_MASK) #define DDRPHY_DX3GSR5_RESERVED_5_MASK (0x20U) #define DDRPHY_DX3GSR5_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_5_MASK) #define DDRPHY_DX3GSR5_RESERVED_6_MASK (0x40U) #define DDRPHY_DX3GSR5_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_6_MASK) #define DDRPHY_DX3GSR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX3GSR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_7_MASK) #define DDRPHY_DX3GSR5_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX3GSR5_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_11_8_MASK) #define DDRPHY_DX3GSR5_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_DX3GSR5_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_19_12_MASK) #define DDRPHY_DX3GSR5_RESERVED_20_MASK (0x100000U) #define DDRPHY_DX3GSR5_RESERVED_20_SHIFT (20U) /*! RESERVED_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_20_MASK) #define DDRPHY_DX3GSR5_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX3GSR5_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_21_MASK) #define DDRPHY_DX3GSR5_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX3GSR5_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_22_MASK) #define DDRPHY_DX3GSR5_RESERVED_31_23_MASK (0xFF800000U) #define DDRPHY_DX3GSR5_RESERVED_31_23_SHIFT (23U) /*! RESERVED_31_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_31_23_MASK) /*! @} */ /*! @name DX3GSR6 - DATX8 n General Status Register 6 */ /*! @{ */ #define DDRPHY_DX3GSR6_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX3GSR6_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_1_0_MASK) #define DDRPHY_DX3GSR6_RESERVED_3_2_MASK (0xCU) #define DDRPHY_DX3GSR6_RESERVED_3_2_SHIFT (2U) /*! RESERVED_3_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_3_2_MASK) #define DDRPHY_DX3GSR6_RESERVED_7_4_MASK (0xF0U) #define DDRPHY_DX3GSR6_RESERVED_7_4_SHIFT (4U) /*! RESERVED_7_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_7_4_MASK) #define DDRPHY_DX3GSR6_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX3GSR6_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_11_8_MASK) #define DDRPHY_DX3GSR6_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_DX3GSR6_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_15_12_MASK) #define DDRPHY_DX3GSR6_RESERVED_19_15_MASK (0xF0000U) #define DDRPHY_DX3GSR6_RESERVED_19_15_SHIFT (16U) /*! RESERVED_19_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_19_15_MASK) #define DDRPHY_DX3GSR6_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX3GSR6_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_23_20_MASK) #define DDRPHY_DX3GSR6_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX3GSR6_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX3GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_31_24_MASK) /*! @} */ /*! @name DX4GCR0 - DATX8 n General Configuration Register 0 */ /*! @{ */ #define DDRPHY_DX4GCR0_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX4GCR0_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX4GCR0_RESERVED_1_0_MASK) #define DDRPHY_DX4GCR0_DQSGOE_MASK (0x4U) #define DDRPHY_DX4GCR0_DQSGOE_SHIFT (2U) /*! DQSGOE - DQSG Output Enable */ #define DDRPHY_DX4GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSGOE_SHIFT)) & DDRPHY_DX4GCR0_DQSGOE_MASK) #define DDRPHY_DX4GCR0_DQSGODT_MASK (0x8U) #define DDRPHY_DX4GCR0_DQSGODT_SHIFT (3U) /*! DQSGODT - DQSG On-Die Termination */ #define DDRPHY_DX4GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSGODT_SHIFT)) & DDRPHY_DX4GCR0_DQSGODT_MASK) #define DDRPHY_DX4GCR0_RESERVED_4_MASK (0x10U) #define DDRPHY_DX4GCR0_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX4GCR0_RESERVED_4_MASK) #define DDRPHY_DX4GCR0_DQSGPDR_MASK (0x20U) #define DDRPHY_DX4GCR0_DQSGPDR_SHIFT (5U) /*! DQSGPDR - DQSG Power Down Receiver */ #define DDRPHY_DX4GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX4GCR0_DQSGPDR_MASK) #define DDRPHY_DX4GCR0_DQSRPD_MASK (0x40U) #define DDRPHY_DX4GCR0_DQSRPD_SHIFT (6U) /*! DQSRPD - DQSR Power Down */ #define DDRPHY_DX4GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSRPD_SHIFT)) & DDRPHY_DX4GCR0_DQSRPD_MASK) #define DDRPHY_DX4GCR0_CPDRSHFT_MASK (0x180U) #define DDRPHY_DX4GCR0_CPDRSHFT_SHIFT (7U) /*! CPDRSHFT - Configurable PDR Phase Shift */ #define DDRPHY_DX4GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX4GCR0_CPDRSHFT_MASK) #define DDRPHY_DX4GCR0_RTTOH_MASK (0x600U) #define DDRPHY_DX4GCR0_RTTOH_SHIFT (9U) /*! RTTOH - RTT Output Hold */ #define DDRPHY_DX4GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RTTOH_SHIFT)) & DDRPHY_DX4GCR0_RTTOH_MASK) #define DDRPHY_DX4GCR0_RTTOAL_MASK (0x800U) #define DDRPHY_DX4GCR0_RTTOAL_SHIFT (11U) /*! RTTOAL - RTT On Additive Latency */ #define DDRPHY_DX4GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RTTOAL_SHIFT)) & DDRPHY_DX4GCR0_RTTOAL_MASK) #define DDRPHY_DX4GCR0_DQSSEPDR_MASK (0x1000U) #define DDRPHY_DX4GCR0_DQSSEPDR_SHIFT (12U) /*! DQSSEPDR - DQSSE Power Down Receiver */ #define DDRPHY_DX4GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX4GCR0_DQSSEPDR_MASK) #define DDRPHY_DX4GCR0_DQSNSEPDR_MASK (0x2000U) #define DDRPHY_DX4GCR0_DQSNSEPDR_SHIFT (13U) /*! DQSNSEPDR - DQSNSE Power Down Receiver */ #define DDRPHY_DX4GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX4GCR0_DQSNSEPDR_MASK) #define DDRPHY_DX4GCR0_RESERVED_19_14_MASK (0xFC000U) #define DDRPHY_DX4GCR0_RESERVED_19_14_SHIFT (14U) /*! RESERVED_19_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX4GCR0_RESERVED_19_14_MASK) #define DDRPHY_DX4GCR0_RDDLY_MASK (0xF00000U) #define DDRPHY_DX4GCR0_RDDLY_SHIFT (20U) /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY */ #define DDRPHY_DX4GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RDDLY_SHIFT)) & DDRPHY_DX4GCR0_RDDLY_MASK) #define DDRPHY_DX4GCR0_DQSDCC_MASK (0xF000000U) #define DDRPHY_DX4GCR0_DQSDCC_SHIFT (24U) /*! DQSDCC - DQS Duty Cycle Correction */ #define DDRPHY_DX4GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSDCC_SHIFT)) & DDRPHY_DX4GCR0_DQSDCC_MASK) #define DDRPHY_DX4GCR0_CODTSHFT_MASK (0x30000000U) #define DDRPHY_DX4GCR0_CODTSHFT_SHIFT (28U) /*! CODTSHFT - Configurable ODT(TE) Phase Shift */ #define DDRPHY_DX4GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX4GCR0_CODTSHFT_MASK) #define DDRPHY_DX4GCR0_MDLEN_MASK (0x40000000U) #define DDRPHY_DX4GCR0_MDLEN_SHIFT (30U) /*! MDLEN - Master Delay Line Enable */ #define DDRPHY_DX4GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_MDLEN_SHIFT)) & DDRPHY_DX4GCR0_MDLEN_MASK) #define DDRPHY_DX4GCR0_CALBYP_MASK (0x80000000U) #define DDRPHY_DX4GCR0_CALBYP_SHIFT (31U) /*! CALBYP - Calibration Bypass */ #define DDRPHY_DX4GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_CALBYP_SHIFT)) & DDRPHY_DX4GCR0_CALBYP_MASK) /*! @} */ /*! @name DX4GCR1 - DATX8 n General Configuration Register 1 */ /*! @{ */ #define DDRPHY_DX4GCR1_DQEN_MASK (0xFFU) #define DDRPHY_DX4GCR1_DQEN_SHIFT (0U) /*! DQEN - Enables DQ corresponding to each bit in a byte */ #define DDRPHY_DX4GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DQEN_SHIFT)) & DDRPHY_DX4GCR1_DQEN_MASK) #define DDRPHY_DX4GCR1_DMEN_MASK (0x100U) #define DDRPHY_DX4GCR1_DMEN_SHIFT (8U) /*! DMEN - Enables DM pin in a byte lane */ #define DDRPHY_DX4GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DMEN_SHIFT)) & DDRPHY_DX4GCR1_DMEN_MASK) #define DDRPHY_DX4GCR1_DSEN_MASK (0x200U) #define DDRPHY_DX4GCR1_DSEN_SHIFT (9U) /*! DSEN - Enables Write Data strobe in a byte lane */ #define DDRPHY_DX4GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DSEN_SHIFT)) & DDRPHY_DX4GCR1_DSEN_MASK) #define DDRPHY_DX4GCR1_TEEN_MASK (0x400U) #define DDRPHY_DX4GCR1_TEEN_SHIFT (10U) /*! TEEN - Enables ODT/TE in a byte lane */ #define DDRPHY_DX4GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_TEEN_SHIFT)) & DDRPHY_DX4GCR1_TEEN_MASK) #define DDRPHY_DX4GCR1_PDREN_MASK (0x800U) #define DDRPHY_DX4GCR1_PDREN_SHIFT (11U) /*! PDREN - Enables PDR in a byte lane */ #define DDRPHY_DX4GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_PDREN_SHIFT)) & DDRPHY_DX4GCR1_PDREN_MASK) #define DDRPHY_DX4GCR1_OEEN_MASK (0x1000U) #define DDRPHY_DX4GCR1_OEEN_SHIFT (12U) /*! OEEN - Enables Read Data Strobe in a byte lane */ #define DDRPHY_DX4GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_OEEN_SHIFT)) & DDRPHY_DX4GCR1_OEEN_MASK) #define DDRPHY_DX4GCR1_QSSEL_MASK (0x2000U) #define DDRPHY_DX4GCR1_QSSEL_SHIFT (13U) /*! QSSEL - Select the delayed or non-delayed read data strobe */ #define DDRPHY_DX4GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_QSSEL_SHIFT)) & DDRPHY_DX4GCR1_QSSEL_MASK) #define DDRPHY_DX4GCR1_QSNSEL_MASK (0x4000U) #define DDRPHY_DX4GCR1_QSNSEL_SHIFT (14U) /*! QSNSEL - Select the delayed or non-delayed read data strobe # */ #define DDRPHY_DX4GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_QSNSEL_SHIFT)) & DDRPHY_DX4GCR1_QSNSEL_MASK) #define DDRPHY_DX4GCR1_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX4GCR1_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX4GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX4GCR1_RESERVED_15_MASK) #define DDRPHY_DX4GCR1_DXPDRMODE_MASK (0xFFFF0000U) #define DDRPHY_DX4GCR1_DXPDRMODE_SHIFT (16U) /*! DXPDRMODE - Enables the PDR mode for DQ[7:0] */ #define DDRPHY_DX4GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX4GCR1_DXPDRMODE_MASK) /*! @} */ /*! @name DX4GCR2 - DATX8 n General Configuration Register 2 */ /*! @{ */ #define DDRPHY_DX4GCR2_DXTEMODE_MASK (0xFFFFU) #define DDRPHY_DX4GCR2_DXTEMODE_SHIFT (0U) /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0] */ #define DDRPHY_DX4GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX4GCR2_DXTEMODE_MASK) #define DDRPHY_DX4GCR2_DXOEMODE_MASK (0xFFFF0000U) #define DDRPHY_DX4GCR2_DXOEMODE_SHIFT (16U) /*! DXOEMODE - Enables the OE mode values for DQ[7:0] */ #define DDRPHY_DX4GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX4GCR2_DXOEMODE_MASK) /*! @} */ /*! @name DX4GCR3 - DATX8 n General Configuration Register 3 */ /*! @{ */ #define DDRPHY_DX4GCR3_WDMBVT_MASK (0x1U) #define DDRPHY_DX4GCR3_WDMBVT_SHIFT (0U) /*! WDMBVT - Write Data Mask BDL VT Compensation */ #define DDRPHY_DX4GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDMBVT_SHIFT)) & DDRPHY_DX4GCR3_WDMBVT_MASK) #define DDRPHY_DX4GCR3_RDMBVT_MASK (0x2U) #define DDRPHY_DX4GCR3_RDMBVT_SHIFT (1U) /*! RDMBVT - Read Data Mask BDL VT Compensation */ #define DDRPHY_DX4GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RDMBVT_SHIFT)) & DDRPHY_DX4GCR3_RDMBVT_MASK) #define DDRPHY_DX4GCR3_DSPDRMODE_MASK (0xCU) #define DDRPHY_DX4GCR3_DSPDRMODE_SHIFT (2U) /*! DSPDRMODE - Enables the PDR mode values for DQS. */ #define DDRPHY_DX4GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX4GCR3_DSPDRMODE_MASK) #define DDRPHY_DX4GCR3_DSTEMODE_MASK (0x30U) #define DDRPHY_DX4GCR3_DSTEMODE_SHIFT (4U) /*! DSTEMODE - Enables the TE mode values for DQS. */ #define DDRPHY_DX4GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSTEMODE_MASK) #define DDRPHY_DX4GCR3_DSOEMODE_MASK (0xC0U) #define DDRPHY_DX4GCR3_DSOEMODE_SHIFT (6U) /*! DSOEMODE - Enables the OE mode values for DQS. */ #define DDRPHY_DX4GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSOEMODE_MASK) #define DDRPHY_DX4GCR3_WDSBVT_MASK (0x100U) #define DDRPHY_DX4GCR3_WDSBVT_SHIFT (8U) /*! WDSBVT - Write Data Strobe BDL VT Compensation */ #define DDRPHY_DX4GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDSBVT_SHIFT)) & DDRPHY_DX4GCR3_WDSBVT_MASK) #define DDRPHY_DX4GCR3_RESERVED_9_MASK (0x200U) #define DDRPHY_DX4GCR3_RESERVED_9_SHIFT (9U) /*! RESERVED_9 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX4GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX4GCR3_RESERVED_9_MASK) #define DDRPHY_DX4GCR3_DMPDRMODE_MASK (0xC00U) #define DDRPHY_DX4GCR3_DMPDRMODE_SHIFT (10U) /*! DMPDRMODE - Enables the PDR mode values for DM. */ #define DDRPHY_DX4GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX4GCR3_DMPDRMODE_MASK) #define DDRPHY_DX4GCR3_DMTEMODE_MASK (0x3000U) #define DDRPHY_DX4GCR3_DMTEMODE_SHIFT (12U) /*! DMTEMODE - Enables the TE mode values for DM. */ #define DDRPHY_DX4GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX4GCR3_DMTEMODE_MASK) #define DDRPHY_DX4GCR3_DMOEMODE_MASK (0xC000U) #define DDRPHY_DX4GCR3_DMOEMODE_SHIFT (14U) /*! DMOEMODE - Enables the OE mode values for DM. */ #define DDRPHY_DX4GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX4GCR3_DMOEMODE_MASK) #define DDRPHY_DX4GCR3_DSNPDRMODE_MASK (0x30000U) #define DDRPHY_DX4GCR3_DSNPDRMODE_SHIFT (16U) /*! DSNPDRMODE - Enables the PDR mode for DQS */ #define DDRPHY_DX4GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX4GCR3_DSNPDRMODE_MASK) #define DDRPHY_DX4GCR3_DSNTEMODE_MASK (0xC0000U) #define DDRPHY_DX4GCR3_DSNTEMODE_SHIFT (18U) /*! DSNTEMODE - Enables the TE mode for DQS */ #define DDRPHY_DX4GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSNTEMODE_MASK) #define DDRPHY_DX4GCR3_DSNOEMODE_MASK (0x300000U) #define DDRPHY_DX4GCR3_DSNOEMODE_SHIFT (20U) /*! DSNOEMODE - Enables the OE mode for DQs */ #define DDRPHY_DX4GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSNOEMODE_MASK) #define DDRPHY_DX4GCR3_PDRBVT_MASK (0x400000U) #define DDRPHY_DX4GCR3_PDRBVT_SHIFT (22U) /*! PDRBVT - Power Down Receiver BDL VT Compensation */ #define DDRPHY_DX4GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_PDRBVT_SHIFT)) & DDRPHY_DX4GCR3_PDRBVT_MASK) #define DDRPHY_DX4GCR3_RGSLVT_MASK (0x800000U) #define DDRPHY_DX4GCR3_RGSLVT_SHIFT (23U) /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation */ #define DDRPHY_DX4GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RGSLVT_SHIFT)) & DDRPHY_DX4GCR3_RGSLVT_MASK) #define DDRPHY_DX4GCR3_WLLVT_MASK (0x1000000U) #define DDRPHY_DX4GCR3_WLLVT_SHIFT (24U) /*! WLLVT - Write Leveling LCDL Delay VT Compensation */ #define DDRPHY_DX4GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WLLVT_SHIFT)) & DDRPHY_DX4GCR3_WLLVT_MASK) #define DDRPHY_DX4GCR3_WDLVT_MASK (0x2000000U) #define DDRPHY_DX4GCR3_WDLVT_SHIFT (25U) /*! WDLVT - Write DQ LCDL Delay VT Compensation */ #define DDRPHY_DX4GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDLVT_SHIFT)) & DDRPHY_DX4GCR3_WDLVT_MASK) #define DDRPHY_DX4GCR3_RDLVT_MASK (0x4000000U) #define DDRPHY_DX4GCR3_RDLVT_SHIFT (26U) /*! RDLVT - Read DQS LCDL Delay VT Compensation */ #define DDRPHY_DX4GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RDLVT_SHIFT)) & DDRPHY_DX4GCR3_RDLVT_MASK) #define DDRPHY_DX4GCR3_RGLVT_MASK (0x8000000U) #define DDRPHY_DX4GCR3_RGLVT_SHIFT (27U) /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation */ #define DDRPHY_DX4GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RGLVT_SHIFT)) & DDRPHY_DX4GCR3_RGLVT_MASK) #define DDRPHY_DX4GCR3_WDBVT_MASK (0x10000000U) #define DDRPHY_DX4GCR3_WDBVT_SHIFT (28U) /*! WDBVT - Write Data BDL VT Compensation */ #define DDRPHY_DX4GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDBVT_SHIFT)) & DDRPHY_DX4GCR3_WDBVT_MASK) #define DDRPHY_DX4GCR3_RDBVT_MASK (0x20000000U) #define DDRPHY_DX4GCR3_RDBVT_SHIFT (29U) /*! RDBVT - Read Data BDL VT Compensation */ #define DDRPHY_DX4GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RDBVT_SHIFT)) & DDRPHY_DX4GCR3_RDBVT_MASK) #define DDRPHY_DX4GCR3_TEBVT_MASK (0x40000000U) #define DDRPHY_DX4GCR3_TEBVT_SHIFT (30U) /*! TEBVT - Termination Enable BDL VT Compensation */ #define DDRPHY_DX4GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_TEBVT_SHIFT)) & DDRPHY_DX4GCR3_TEBVT_MASK) #define DDRPHY_DX4GCR3_OEBVT_MASK (0x80000000U) #define DDRPHY_DX4GCR3_OEBVT_SHIFT (31U) /*! OEBVT - Output Enable BDL VT Compensation */ #define DDRPHY_DX4GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_OEBVT_SHIFT)) & DDRPHY_DX4GCR3_OEBVT_MASK) /*! @} */ /*! @name DX4GCR4 - DATX8 n General Configuration Register 4 */ /*! @{ */ #define DDRPHY_DX4GCR4_DXREFIMON_MASK (0x3U) #define DDRPHY_DX4GCR4_DXREFIMON_SHIFT (0U) /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX4GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX4GCR4_DXREFIMON_MASK) #define DDRPHY_DX4GCR4_DXREFIEN_MASK (0x3CU) #define DDRPHY_DX4GCR4_DXREFIEN_SHIFT (2U) /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX4GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFIEN_MASK) #define DDRPHY_DX4GCR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4GCR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX4GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR4_RESERVED_7_6_MASK) #define DDRPHY_DX4GCR4_DXREFSSEL_MASK (0x7F00U) #define DDRPHY_DX4GCR4_DXREFSSEL_SHIFT (8U) /*! DXREFSSEL - Byte Lane Single-End VREF Select */ #define DDRPHY_DX4GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX4GCR4_DXREFSSEL_MASK) #define DDRPHY_DX4GCR4_DXREFSSELRANGE_MASK (0x8000U) #define DDRPHY_DX4GCR4_DXREFSSELRANGE_SHIFT (15U) /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select */ #define DDRPHY_DX4GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX4GCR4_DXREFSSELRANGE_MASK) #define DDRPHY_DX4GCR4_DXREFESEL_MASK (0x7F0000U) #define DDRPHY_DX4GCR4_DXREFESEL_SHIFT (16U) /*! DXREFESEL - Byte Lane External VREF Select */ #define DDRPHY_DX4GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX4GCR4_DXREFESEL_MASK) #define DDRPHY_DX4GCR4_DXREFESELRANGE_MASK (0x800000U) #define DDRPHY_DX4GCR4_DXREFESELRANGE_SHIFT (23U) /*! DXREFESELRANGE - External VREF generator REFSEL range select */ #define DDRPHY_DX4GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX4GCR4_DXREFESELRANGE_MASK) #define DDRPHY_DX4GCR4_RESERVED_24_MASK (0x1000000U) #define DDRPHY_DX4GCR4_RESERVED_24_SHIFT (24U) /*! RESERVED_24 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX4GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX4GCR4_RESERVED_24_MASK) #define DDRPHY_DX4GCR4_DXREFSEN_MASK (0x2000000U) #define DDRPHY_DX4GCR4_DXREFSEN_SHIFT (25U) /*! DXREFSEN - Byte Lane Single-End VREF Enable */ #define DDRPHY_DX4GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFSEN_MASK) #define DDRPHY_DX4GCR4_DXREFEEN_MASK (0xC000000U) #define DDRPHY_DX4GCR4_DXREFEEN_SHIFT (26U) /*! DXREFEEN - Byte Lane Internal VREF Enable */ #define DDRPHY_DX4GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFEEN_MASK) #define DDRPHY_DX4GCR4_DXREFPEN_MASK (0x10000000U) #define DDRPHY_DX4GCR4_DXREFPEN_SHIFT (28U) /*! DXREFPEN - Byte Lane VREF Pad Enable */ #define DDRPHY_DX4GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFPEN_MASK) #define DDRPHY_DX4GCR4_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DX4GCR4_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs) */ #define DDRPHY_DX4GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX4GCR4_RESERVED_31_29_MASK) /*! @} */ /*! @name DX4GCR5 - DATX8 n General Configuration Register 5 */ /*! @{ */ #define DDRPHY_DX4GCR5_DXREFISELR0_MASK (0x7FU) #define DDRPHY_DX4GCR5_DXREFISELR0_SHIFT (0U) /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0 */ #define DDRPHY_DX4GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR0_MASK) #define DDRPHY_DX4GCR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX4GCR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX4GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_7_MASK) #define DDRPHY_DX4GCR5_DXREFISELR1_MASK (0x7F00U) #define DDRPHY_DX4GCR5_DXREFISELR1_SHIFT (8U) /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1 */ #define DDRPHY_DX4GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR1_MASK) #define DDRPHY_DX4GCR5_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX4GCR5_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX4GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_15_MASK) #define DDRPHY_DX4GCR5_DXREFISELR2_MASK (0x7F0000U) #define DDRPHY_DX4GCR5_DXREFISELR2_SHIFT (16U) /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2 */ #define DDRPHY_DX4GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR2_MASK) #define DDRPHY_DX4GCR5_RESERVED_23_MASK (0x800000U) #define DDRPHY_DX4GCR5_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX4GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_23_MASK) #define DDRPHY_DX4GCR5_DXREFISELR3_MASK (0x7F000000U) #define DDRPHY_DX4GCR5_DXREFISELR3_SHIFT (24U) /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3 */ #define DDRPHY_DX4GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR3_MASK) #define DDRPHY_DX4GCR5_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX4GCR5_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX4GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_31_MASK) /*! @} */ /*! @name DX4GCR6 - DATX8 n General Configuration Register 6 */ /*! @{ */ #define DDRPHY_DX4GCR6_DXDQVREFR0_MASK (0x3FU) #define DDRPHY_DX4GCR6_DXDQVREFR0_SHIFT (0U) /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0 */ #define DDRPHY_DX4GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR0_MASK) #define DDRPHY_DX4GCR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4GCR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX4GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_7_6_MASK) #define DDRPHY_DX4GCR6_DXDQVREFR1_MASK (0x3F00U) #define DDRPHY_DX4GCR6_DXDQVREFR1_SHIFT (8U) /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1 */ #define DDRPHY_DX4GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR1_MASK) #define DDRPHY_DX4GCR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4GCR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX4GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_15_14_MASK) #define DDRPHY_DX4GCR6_DXDQVREFR2_MASK (0x3F0000U) #define DDRPHY_DX4GCR6_DXDQVREFR2_SHIFT (16U) /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2 */ #define DDRPHY_DX4GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR2_MASK) #define DDRPHY_DX4GCR6_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX4GCR6_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX4GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_23_22_MASK) #define DDRPHY_DX4GCR6_DXDQVREFR3_MASK (0x3F000000U) #define DDRPHY_DX4GCR6_DXDQVREFR3_SHIFT (24U) /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3 */ #define DDRPHY_DX4GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR3_MASK) #define DDRPHY_DX4GCR6_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX4GCR6_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX4GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_31_30_MASK) /*! @} */ /*! @name DX4GCR7 - DATX8 n General Configuration Register 7 */ /*! @{ */ #define DDRPHY_DX4GCR7_DCALSVAL_MASK (0x1FFU) #define DDRPHY_DX4GCR7_DCALSVAL_SHIFT (0U) /*! DCALSVAL - DDL Calibration Starting Value */ #define DDRPHY_DX4GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX4GCR7_DCALSVAL_MASK) #define DDRPHY_DX4GCR7_DCALTYPE_MASK (0x200U) #define DDRPHY_DX4GCR7_DCALTYPE_SHIFT (9U) /*! DCALTYPE - DDL Calibration Type */ #define DDRPHY_DX4GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX4GCR7_DCALTYPE_MASK) #define DDRPHY_DX4GCR7_RESERVED_17_10_MASK (0x3FC00U) #define DDRPHY_DX4GCR7_RESERVED_17_10_SHIFT (10U) /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX4GCR7_RESERVED_17_10_MASK) #define DDRPHY_DX4GCR7_RESERVED_18_MASK (0x40000U) #define DDRPHY_DX4GCR7_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX4GCR7_RESERVED_18_MASK) #define DDRPHY_DX4GCR7_RESERVED_31_19_MASK (0xFFF80000U) #define DDRPHY_DX4GCR7_RESERVED_31_19_SHIFT (19U) /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX4GCR7_RESERVED_31_19_MASK) /*! @} */ /*! @name DX4GCR8 - DATX8 n General Configuration Register 8 */ /*! @{ */ #define DDRPHY_DX4GCR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX4GCR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_5_0_MASK) #define DDRPHY_DX4GCR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4GCR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_7_6_MASK) #define DDRPHY_DX4GCR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX4GCR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_13_8_MASK) #define DDRPHY_DX4GCR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4GCR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_15_14_MASK) #define DDRPHY_DX4GCR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX4GCR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_21_16_MASK) #define DDRPHY_DX4GCR8_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX4GCR8_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_23_22_MASK) #define DDRPHY_DX4GCR8_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX4GCR8_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_29_24_MASK) #define DDRPHY_DX4GCR8_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX4GCR8_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_31_30_MASK) /*! @} */ /*! @name DX4GCR9 - DATX8 n General Configuration Register 9 */ /*! @{ */ #define DDRPHY_DX4GCR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX4GCR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_5_0_MASK) #define DDRPHY_DX4GCR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4GCR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_7_6_MASK) #define DDRPHY_DX4GCR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX4GCR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_13_8_MASK) #define DDRPHY_DX4GCR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4GCR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_15_14_MASK) #define DDRPHY_DX4GCR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX4GCR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_21_16_MASK) #define DDRPHY_DX4GCR9_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX4GCR9_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_23_22_MASK) #define DDRPHY_DX4GCR9_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX4GCR9_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_29_24_MASK) #define DDRPHY_DX4GCR9_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX4GCR9_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_31_30_MASK) /*! @} */ /*! @name DX4DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */ /*! @{ */ #define DDRPHY_DX4DQMAP0_DQ0MAP_MASK (0xFU) #define DDRPHY_DX4DQMAP0_DQ0MAP_SHIFT (0U) /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index */ #define DDRPHY_DX4DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ0MAP_MASK) #define DDRPHY_DX4DQMAP0_DQ1MAP_MASK (0xF0U) #define DDRPHY_DX4DQMAP0_DQ1MAP_SHIFT (4U) /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index */ #define DDRPHY_DX4DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ1MAP_MASK) #define DDRPHY_DX4DQMAP0_DQ2MAP_MASK (0xF00U) #define DDRPHY_DX4DQMAP0_DQ2MAP_SHIFT (8U) /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index */ #define DDRPHY_DX4DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ2MAP_MASK) #define DDRPHY_DX4DQMAP0_DQ3MAP_MASK (0xF000U) #define DDRPHY_DX4DQMAP0_DQ3MAP_SHIFT (12U) /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index */ #define DDRPHY_DX4DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ3MAP_MASK) #define DDRPHY_DX4DQMAP0_DQ4MAP_MASK (0xF0000U) #define DDRPHY_DX4DQMAP0_DQ4MAP_SHIFT (16U) /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index */ #define DDRPHY_DX4DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ4MAP_MASK) #define DDRPHY_DX4DQMAP0_RESERVED_30_20_MASK (0x7FF00000U) #define DDRPHY_DX4DQMAP0_RESERVED_30_20_SHIFT (20U) /*! RESERVED_30_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX4DQMAP0_RESERVED_30_20_MASK) #define DDRPHY_DX4DQMAP0_MAPOK_MASK (0x80000000U) #define DDRPHY_DX4DQMAP0_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX4DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX4DQMAP0_MAPOK_MASK) /*! @} */ /*! @name DX4DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */ /*! @{ */ #define DDRPHY_DX4DQMAP1_DQ5MAP_MASK (0xFU) #define DDRPHY_DX4DQMAP1_DQ5MAP_SHIFT (0U) /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index */ #define DDRPHY_DX4DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX4DQMAP1_DQ5MAP_MASK) #define DDRPHY_DX4DQMAP1_DQ6MAP_MASK (0xF0U) #define DDRPHY_DX4DQMAP1_DQ6MAP_SHIFT (4U) /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index */ #define DDRPHY_DX4DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX4DQMAP1_DQ6MAP_MASK) #define DDRPHY_DX4DQMAP1_DQ7MAP_MASK (0xF00U) #define DDRPHY_DX4DQMAP1_DQ7MAP_SHIFT (8U) /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index */ #define DDRPHY_DX4DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX4DQMAP1_DQ7MAP_MASK) #define DDRPHY_DX4DQMAP1_DMMAP_MASK (0xF000U) #define DDRPHY_DX4DQMAP1_DMMAP_SHIFT (12U) /*! DMMAP - DM bit DATX8 slice mapping index */ #define DDRPHY_DX4DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX4DQMAP1_DMMAP_MASK) #define DDRPHY_DX4DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U) #define DDRPHY_DX4DQMAP1_RESERVED_30_16_SHIFT (16U) /*! RESERVED_30_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX4DQMAP1_RESERVED_30_16_MASK) #define DDRPHY_DX4DQMAP1_MAPOK_MASK (0x80000000U) #define DDRPHY_DX4DQMAP1_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX4DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX4DQMAP1_MAPOK_MASK) /*! @} */ /*! @name DX4BDLR0 - DATX8 n Bit Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX4BDLR0_DQ0WBD_MASK (0x3FU) #define DDRPHY_DX4BDLR0_DQ0WBD_SHIFT (0U) /*! DQ0WBD - DQ0 Write Bit Delay */ #define DDRPHY_DX4BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ0WBD_MASK) #define DDRPHY_DX4BDLR0_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4BDLR0_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_7_6_MASK) #define DDRPHY_DX4BDLR0_DQ1WBD_MASK (0x3F00U) #define DDRPHY_DX4BDLR0_DQ1WBD_SHIFT (8U) /*! DQ1WBD - DQ1 Write Bit Delay */ #define DDRPHY_DX4BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ1WBD_MASK) #define DDRPHY_DX4BDLR0_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4BDLR0_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_15_14_MASK) #define DDRPHY_DX4BDLR0_DQ2WBD_MASK (0x3F0000U) #define DDRPHY_DX4BDLR0_DQ2WBD_SHIFT (16U) /*! DQ2WBD - DQ2 Write Bit Delay */ #define DDRPHY_DX4BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ2WBD_MASK) #define DDRPHY_DX4BDLR0_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX4BDLR0_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_23_22_MASK) #define DDRPHY_DX4BDLR0_DQ3WBD_MASK (0x3F000000U) #define DDRPHY_DX4BDLR0_DQ3WBD_SHIFT (24U) /*! DQ3WBD - DQ3 Write Bit Delay */ #define DDRPHY_DX4BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ3WBD_MASK) #define DDRPHY_DX4BDLR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX4BDLR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_31_30_MASK) /*! @} */ /*! @name DX4BDLR1 - DATX8 n Bit Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX4BDLR1_DQ4WBD_MASK (0x3FU) #define DDRPHY_DX4BDLR1_DQ4WBD_SHIFT (0U) /*! DQ4WBD - DQ4 Write Bit Delay */ #define DDRPHY_DX4BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ4WBD_MASK) #define DDRPHY_DX4BDLR1_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4BDLR1_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_7_6_MASK) #define DDRPHY_DX4BDLR1_DQ5WBD_MASK (0x3F00U) #define DDRPHY_DX4BDLR1_DQ5WBD_SHIFT (8U) /*! DQ5WBD - DQ5 Write Bit Delay */ #define DDRPHY_DX4BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ5WBD_MASK) #define DDRPHY_DX4BDLR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4BDLR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_15_14_MASK) #define DDRPHY_DX4BDLR1_DQ6WBD_MASK (0x3F0000U) #define DDRPHY_DX4BDLR1_DQ6WBD_SHIFT (16U) /*! DQ6WBD - DQ6 Write Bit Delay */ #define DDRPHY_DX4BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ6WBD_MASK) #define DDRPHY_DX4BDLR1_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX4BDLR1_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_23_22_MASK) #define DDRPHY_DX4BDLR1_DQ7WBD_MASK (0x3F000000U) #define DDRPHY_DX4BDLR1_DQ7WBD_SHIFT (24U) /*! DQ7WBD - DQ7 Write Bit Delay */ #define DDRPHY_DX4BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ7WBD_MASK) #define DDRPHY_DX4BDLR1_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX4BDLR1_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_31_30_MASK) /*! @} */ /*! @name DX4BDLR2 - DATX8 n Bit Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX4BDLR2_DMWBD_MASK (0x3FU) #define DDRPHY_DX4BDLR2_DMWBD_SHIFT (0U) /*! DMWBD - DM Write Bit Delay */ #define DDRPHY_DX4BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DMWBD_SHIFT)) & DDRPHY_DX4BDLR2_DMWBD_MASK) #define DDRPHY_DX4BDLR2_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4BDLR2_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_7_6_MASK) #define DDRPHY_DX4BDLR2_DSWBD_MASK (0x3F00U) #define DDRPHY_DX4BDLR2_DSWBD_SHIFT (8U) /*! DSWBD - DQS Write Bit Delay */ #define DDRPHY_DX4BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DSWBD_SHIFT)) & DDRPHY_DX4BDLR2_DSWBD_MASK) #define DDRPHY_DX4BDLR2_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4BDLR2_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_15_14_MASK) #define DDRPHY_DX4BDLR2_DSOEBD_MASK (0x3F0000U) #define DDRPHY_DX4BDLR2_DSOEBD_SHIFT (16U) /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay */ #define DDRPHY_DX4BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX4BDLR2_DSOEBD_MASK) #define DDRPHY_DX4BDLR2_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX4BDLR2_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_23_22_MASK) #define DDRPHY_DX4BDLR2_DSNWBD_MASK (0x3F000000U) #define DDRPHY_DX4BDLR2_DSNWBD_SHIFT (24U) /*! DSNWBD - DQSN Write Bit Delay */ #define DDRPHY_DX4BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX4BDLR2_DSNWBD_MASK) #define DDRPHY_DX4BDLR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX4BDLR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_31_30_MASK) /*! @} */ /*! @name DX4BDLR3 - DATX8 n Bit Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX4BDLR3_DQ0RBD_MASK (0x3FU) #define DDRPHY_DX4BDLR3_DQ0RBD_SHIFT (0U) /*! DQ0RBD - DQ0 Read Bit Delay */ #define DDRPHY_DX4BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ0RBD_MASK) #define DDRPHY_DX4BDLR3_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4BDLR3_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_7_6_MASK) #define DDRPHY_DX4BDLR3_DQ1RBD_MASK (0x3F00U) #define DDRPHY_DX4BDLR3_DQ1RBD_SHIFT (8U) /*! DQ1RBD - DQ1 Read Bit Delay */ #define DDRPHY_DX4BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ1RBD_MASK) #define DDRPHY_DX4BDLR3_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4BDLR3_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_15_14_MASK) #define DDRPHY_DX4BDLR3_DQ2RBD_MASK (0x3F0000U) #define DDRPHY_DX4BDLR3_DQ2RBD_SHIFT (16U) /*! DQ2RBD - DQ2 Read Bit Delay */ #define DDRPHY_DX4BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ2RBD_MASK) #define DDRPHY_DX4BDLR3_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX4BDLR3_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_23_22_MASK) #define DDRPHY_DX4BDLR3_DQ3RBD_MASK (0x3F000000U) #define DDRPHY_DX4BDLR3_DQ3RBD_SHIFT (24U) /*! DQ3RBD - DQ3 Read Bit Delay */ #define DDRPHY_DX4BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ3RBD_MASK) #define DDRPHY_DX4BDLR3_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX4BDLR3_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_31_30_MASK) /*! @} */ /*! @name DX4BDLR4 - DATX8 n Bit Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX4BDLR4_DQ4RBD_MASK (0x3FU) #define DDRPHY_DX4BDLR4_DQ4RBD_SHIFT (0U) /*! DQ4RBD - DQ4 Read Bit Delay */ #define DDRPHY_DX4BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ4RBD_MASK) #define DDRPHY_DX4BDLR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4BDLR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_7_6_MASK) #define DDRPHY_DX4BDLR4_DQ5RBD_MASK (0x3F00U) #define DDRPHY_DX4BDLR4_DQ5RBD_SHIFT (8U) /*! DQ5RBD - DQ5 Read Bit Delay */ #define DDRPHY_DX4BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ5RBD_MASK) #define DDRPHY_DX4BDLR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4BDLR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_15_14_MASK) #define DDRPHY_DX4BDLR4_DQ6RBD_MASK (0x3F0000U) #define DDRPHY_DX4BDLR4_DQ6RBD_SHIFT (16U) /*! DQ6RBD - DQ6 Read Bit Delay */ #define DDRPHY_DX4BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ6RBD_MASK) #define DDRPHY_DX4BDLR4_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX4BDLR4_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_23_22_MASK) #define DDRPHY_DX4BDLR4_DQ7RBD_MASK (0x3F000000U) #define DDRPHY_DX4BDLR4_DQ7RBD_SHIFT (24U) /*! DQ7RBD - DQ7 Read Bit Delay */ #define DDRPHY_DX4BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ7RBD_MASK) #define DDRPHY_DX4BDLR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX4BDLR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_31_30_MASK) /*! @} */ /*! @name DX4BDLR5 - DATX8 n Bit Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX4BDLR5_DMRBD_MASK (0x3FU) #define DDRPHY_DX4BDLR5_DMRBD_SHIFT (0U) /*! DMRBD - DM Read Bit Delay */ #define DDRPHY_DX4BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR5_DMRBD_SHIFT)) & DDRPHY_DX4BDLR5_DMRBD_MASK) #define DDRPHY_DX4BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U) #define DDRPHY_DX4BDLR5_RESERVED_31_6_SHIFT (6U) /*! RESERVED_31_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX4BDLR5_RESERVED_31_6_MASK) /*! @} */ /*! @name DX4BDLR6 - DATX8 n Bit Delay Line Register 6 */ /*! @{ */ #define DDRPHY_DX4BDLR6_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_DX4BDLR6_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX4BDLR6_RESERVED_7_0_MASK) #define DDRPHY_DX4BDLR6_PDRBD_MASK (0x3F00U) #define DDRPHY_DX4BDLR6_PDRBD_SHIFT (8U) /*! PDRBD - Power down receiver Bit Delay */ #define DDRPHY_DX4BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_PDRBD_SHIFT)) & DDRPHY_DX4BDLR6_PDRBD_MASK) #define DDRPHY_DX4BDLR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4BDLR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR6_RESERVED_15_14_MASK) #define DDRPHY_DX4BDLR6_TERBD_MASK (0x3F0000U) #define DDRPHY_DX4BDLR6_TERBD_SHIFT (16U) /*! TERBD - Termination Enable Bit Delay */ #define DDRPHY_DX4BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_TERBD_SHIFT)) & DDRPHY_DX4BDLR6_TERBD_MASK) #define DDRPHY_DX4BDLR6_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX4BDLR6_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR6_RESERVED_31_22_MASK) /*! @} */ /*! @name DX4BDLR7 - DATX8 n Bit Delay Line Register 7 */ /*! @{ */ #define DDRPHY_DX4BDLR7_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX4BDLR7_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_5_0_MASK) #define DDRPHY_DX4BDLR7_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4BDLR7_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_7_6_MASK) #define DDRPHY_DX4BDLR7_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX4BDLR7_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_13_8_MASK) #define DDRPHY_DX4BDLR7_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4BDLR7_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_15_14_MASK) #define DDRPHY_DX4BDLR7_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX4BDLR7_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_21_16_MASK) #define DDRPHY_DX4BDLR7_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX4BDLR7_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_31_22_MASK) /*! @} */ /*! @name DX4BDLR8 - DATX8 n Bit Delay Line Register 8 */ /*! @{ */ #define DDRPHY_DX4BDLR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX4BDLR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_5_0_MASK) #define DDRPHY_DX4BDLR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4BDLR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_7_6_MASK) #define DDRPHY_DX4BDLR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX4BDLR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_13_8_MASK) #define DDRPHY_DX4BDLR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4BDLR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_15_14_MASK) #define DDRPHY_DX4BDLR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX4BDLR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_21_16_MASK) #define DDRPHY_DX4BDLR8_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX4BDLR8_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_31_22_MASK) /*! @} */ /*! @name DX4BDLR9 - DATX8 n Bit Delay Line Register 9 */ /*! @{ */ #define DDRPHY_DX4BDLR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX4BDLR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_5_0_MASK) #define DDRPHY_DX4BDLR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX4BDLR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_7_6_MASK) #define DDRPHY_DX4BDLR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX4BDLR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_13_8_MASK) #define DDRPHY_DX4BDLR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX4BDLR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_15_14_MASK) #define DDRPHY_DX4BDLR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX4BDLR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_21_16_MASK) #define DDRPHY_DX4BDLR9_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX4BDLR9_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_31_22_MASK) /*! @} */ /*! @name DX4LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX4LCDLR0_WLD_MASK (0x1FFU) #define DDRPHY_DX4LCDLR0_WLD_SHIFT (0U) /*! WLD - Write Leveling Delay */ #define DDRPHY_DX4LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_WLD_SHIFT)) & DDRPHY_DX4LCDLR0_WLD_MASK) #define DDRPHY_DX4LCDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX4LCDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX4LCDLR0_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX4LCDLR0_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR0_RESERVED_24_16_MASK) #define DDRPHY_DX4LCDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX4LCDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX4LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX4LCDLR1_WDQD_MASK (0x1FFU) #define DDRPHY_DX4LCDLR1_WDQD_SHIFT (0U) /*! WDQD - Write Data Delay */ #define DDRPHY_DX4LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_WDQD_SHIFT)) & DDRPHY_DX4LCDLR1_WDQD_MASK) #define DDRPHY_DX4LCDLR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX4LCDLR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR1_RESERVED_15_9_MASK) #define DDRPHY_DX4LCDLR1_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX4LCDLR1_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR1_RESERVED_24_16_MASK) #define DDRPHY_DX4LCDLR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX4LCDLR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX4LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX4LCDLR2_DQSGD_MASK (0x1FFU) #define DDRPHY_DX4LCDLR2_DQSGD_SHIFT (0U) /*! DQSGD - Read DQS Gating Delay */ #define DDRPHY_DX4LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX4LCDLR2_DQSGD_MASK) #define DDRPHY_DX4LCDLR2_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX4LCDLR2_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR2_RESERVED_15_9_MASK) #define DDRPHY_DX4LCDLR2_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX4LCDLR2_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR2_RESERVED_24_16_MASK) #define DDRPHY_DX4LCDLR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX4LCDLR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR2_RESERVED_31_25_MASK) /*! @} */ /*! @name DX4LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX4LCDLR3_RDQSD_MASK (0x1FFU) #define DDRPHY_DX4LCDLR3_RDQSD_SHIFT (0U) /*! RDQSD - Read DQS Delay */ #define DDRPHY_DX4LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX4LCDLR3_RDQSD_MASK) #define DDRPHY_DX4LCDLR3_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX4LCDLR3_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR3_RESERVED_15_9_MASK) #define DDRPHY_DX4LCDLR3_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX4LCDLR3_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR3_RESERVED_24_16_MASK) #define DDRPHY_DX4LCDLR3_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX4LCDLR3_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR3_RESERVED_31_25_MASK) /*! @} */ /*! @name DX4LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX4LCDLR4_RDQSND_MASK (0x1FFU) #define DDRPHY_DX4LCDLR4_RDQSND_SHIFT (0U) /*! RDQSND - Read DQSN Delay */ #define DDRPHY_DX4LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX4LCDLR4_RDQSND_MASK) #define DDRPHY_DX4LCDLR4_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX4LCDLR4_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR4_RESERVED_15_9_MASK) #define DDRPHY_DX4LCDLR4_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX4LCDLR4_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR4_RESERVED_24_16_MASK) #define DDRPHY_DX4LCDLR4_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX4LCDLR4_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR4_RESERVED_31_25_MASK) /*! @} */ /*! @name DX4LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX4LCDLR5_DQSGSD_MASK (0x1FFU) #define DDRPHY_DX4LCDLR5_DQSGSD_SHIFT (0U) /*! DQSGSD - DQS Gating Status Delay */ #define DDRPHY_DX4LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX4LCDLR5_DQSGSD_MASK) #define DDRPHY_DX4LCDLR5_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX4LCDLR5_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR5_RESERVED_15_9_MASK) #define DDRPHY_DX4LCDLR5_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX4LCDLR5_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR5_RESERVED_24_16_MASK) #define DDRPHY_DX4LCDLR5_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX4LCDLR5_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR5_RESERVED_31_25_MASK) /*! @} */ /*! @name DX4MDLR0 - DATX8 n Master Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX4MDLR0_IPRD_MASK (0x1FFU) #define DDRPHY_DX4MDLR0_IPRD_SHIFT (0U) /*! IPRD - Initial Period */ #define DDRPHY_DX4MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_IPRD_SHIFT)) & DDRPHY_DX4MDLR0_IPRD_MASK) #define DDRPHY_DX4MDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX4MDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX4MDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX4MDLR0_TPRD_MASK (0x1FF0000U) #define DDRPHY_DX4MDLR0_TPRD_SHIFT (16U) /*! TPRD - Target Period */ #define DDRPHY_DX4MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_TPRD_SHIFT)) & DDRPHY_DX4MDLR0_TPRD_MASK) #define DDRPHY_DX4MDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX4MDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX4MDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX4MDLR1 - DATX8 n Master Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX4MDLR1_MDLD_MASK (0x1FFU) #define DDRPHY_DX4MDLR1_MDLD_SHIFT (0U) /*! MDLD - MDL Delay */ #define DDRPHY_DX4MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR1_MDLD_SHIFT)) & DDRPHY_DX4MDLR1_MDLD_MASK) #define DDRPHY_DX4MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U) #define DDRPHY_DX4MDLR1_RESERVED_31_9_SHIFT (9U) /*! RESERVED_31_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX4MDLR1_RESERVED_31_9_MASK) /*! @} */ /*! @name DX4GTR0 - DATX8 n General Timing Register 0 */ /*! @{ */ #define DDRPHY_DX4GTR0_DGSL_MASK (0x1FU) #define DDRPHY_DX4GTR0_DGSL_SHIFT (0U) /*! DGSL - DQS Gating System Latency */ #define DDRPHY_DX4GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_DGSL_SHIFT)) & DDRPHY_DX4GTR0_DGSL_MASK) #define DDRPHY_DX4GTR0_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DX4GTR0_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_7_5_MASK) #define DDRPHY_DX4GTR0_RESERVED_12_8_MASK (0x1F00U) #define DDRPHY_DX4GTR0_RESERVED_12_8_SHIFT (8U) /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_12_8_MASK) #define DDRPHY_DX4GTR0_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_DX4GTR0_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_15_13_MASK) #define DDRPHY_DX4GTR0_WLSL_MASK (0xF0000U) #define DDRPHY_DX4GTR0_WLSL_SHIFT (16U) /*! WLSL - Write Leveling System Latency */ #define DDRPHY_DX4GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_WLSL_SHIFT)) & DDRPHY_DX4GTR0_WLSL_MASK) #define DDRPHY_DX4GTR0_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX4GTR0_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX4GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_23_20_MASK) #define DDRPHY_DX4GTR0_WDQSL_MASK (0x7000000U) #define DDRPHY_DX4GTR0_WDQSL_SHIFT (24U) /*! WDQSL - DQ Write Path Latency Pipeline */ #define DDRPHY_DX4GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_WDQSL_SHIFT)) & DDRPHY_DX4GTR0_WDQSL_MASK) #define DDRPHY_DX4GTR0_RESERVED_31_24_MASK (0xF8000000U) #define DDRPHY_DX4GTR0_RESERVED_31_24_SHIFT (27U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_31_24_MASK) /*! @} */ /*! @name DX4RSR0 - DATX8 n Rank Status Register 0 */ /*! @{ */ #define DDRPHY_DX4RSR0_QSGERR_MASK (0xFFFFU) #define DDRPHY_DX4RSR0_QSGERR_SHIFT (0U) /*! QSGERR - DQS Gate Training Error */ #define DDRPHY_DX4RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR0_QSGERR_SHIFT)) & DDRPHY_DX4RSR0_QSGERR_MASK) #define DDRPHY_DX4RSR0_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX4RSR0_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR0_RESERVED_31_16_MASK) /*! @} */ /*! @name DX4RSR1 - DATX8 n Rank Status Register 1 */ /*! @{ */ #define DDRPHY_DX4RSR1_RDLVLERR_MASK (0xFFFFU) #define DDRPHY_DX4RSR1_RDLVLERR_SHIFT (0U) /*! RDLVLERR - Read Leveling Error */ #define DDRPHY_DX4RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX4RSR1_RDLVLERR_MASK) #define DDRPHY_DX4RSR1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX4RSR1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR1_RESERVED_31_16_MASK) /*! @} */ /*! @name DX4RSR2 - DATX8 n Rank Status Register 2 */ /*! @{ */ #define DDRPHY_DX4RSR2_WLAWN_MASK (0xFFFFU) #define DDRPHY_DX4RSR2_WLAWN_SHIFT (0U) /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning */ #define DDRPHY_DX4RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR2_WLAWN_SHIFT)) & DDRPHY_DX4RSR2_WLAWN_MASK) #define DDRPHY_DX4RSR2_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX4RSR2_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR2_RESERVED_31_16_MASK) /*! @} */ /*! @name DX4RSR3 - DATX8 n Rank Status Register 3 */ /*! @{ */ #define DDRPHY_DX4RSR3_WLAERR_MASK (0xFFFFU) #define DDRPHY_DX4RSR3_WLAERR_SHIFT (0U) /*! WLAERR - Write Leveling Adjustment Error */ #define DDRPHY_DX4RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR3_WLAERR_SHIFT)) & DDRPHY_DX4RSR3_WLAERR_MASK) #define DDRPHY_DX4RSR3_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX4RSR3_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR3_RESERVED_31_16_MASK) /*! @} */ /*! @name DX4GSR0 - DATX8 n General Status Register 0 */ /*! @{ */ #define DDRPHY_DX4GSR0_WDQCAL_MASK (0x1U) #define DDRPHY_DX4GSR0_WDQCAL_SHIFT (0U) /*! WDQCAL - Write DQ Calibration */ #define DDRPHY_DX4GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WDQCAL_SHIFT)) & DDRPHY_DX4GSR0_WDQCAL_MASK) #define DDRPHY_DX4GSR0_RDQSCAL_MASK (0x2U) #define DDRPHY_DX4GSR0_RDQSCAL_SHIFT (1U) /*! RDQSCAL - Read DQS Calibration */ #define DDRPHY_DX4GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX4GSR0_RDQSCAL_MASK) #define DDRPHY_DX4GSR0_RDQSNCAL_MASK (0x4U) #define DDRPHY_DX4GSR0_RDQSNCAL_SHIFT (2U) /*! RDQSNCAL - Read DQS# Calibration */ #define DDRPHY_DX4GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX4GSR0_RDQSNCAL_MASK) #define DDRPHY_DX4GSR0_GDQSCAL_MASK (0x8U) #define DDRPHY_DX4GSR0_GDQSCAL_SHIFT (3U) /*! GDQSCAL - Read DQS gating Calibration */ #define DDRPHY_DX4GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX4GSR0_GDQSCAL_MASK) #define DDRPHY_DX4GSR0_WLCAL_MASK (0x10U) #define DDRPHY_DX4GSR0_WLCAL_SHIFT (4U) /*! WLCAL - Write Leveling Calibration */ #define DDRPHY_DX4GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLCAL_SHIFT)) & DDRPHY_DX4GSR0_WLCAL_MASK) #define DDRPHY_DX4GSR0_WLDONE_MASK (0x20U) #define DDRPHY_DX4GSR0_WLDONE_SHIFT (5U) /*! WLDONE - Write Leveling Done */ #define DDRPHY_DX4GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLDONE_SHIFT)) & DDRPHY_DX4GSR0_WLDONE_MASK) #define DDRPHY_DX4GSR0_WLERR_MASK (0x40U) #define DDRPHY_DX4GSR0_WLERR_SHIFT (6U) /*! WLERR - Write Leveling Error */ #define DDRPHY_DX4GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLERR_SHIFT)) & DDRPHY_DX4GSR0_WLERR_MASK) #define DDRPHY_DX4GSR0_WLPRD_MASK (0xFF80U) #define DDRPHY_DX4GSR0_WLPRD_SHIFT (7U) /*! WLPRD - Write Leveling Period */ #define DDRPHY_DX4GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLPRD_SHIFT)) & DDRPHY_DX4GSR0_WLPRD_MASK) #define DDRPHY_DX4GSR0_DPLOCK_MASK (0x10000U) #define DDRPHY_DX4GSR0_DPLOCK_SHIFT (16U) /*! DPLOCK - DATX8 PLL Lock */ #define DDRPHY_DX4GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_DPLOCK_SHIFT)) & DDRPHY_DX4GSR0_DPLOCK_MASK) #define DDRPHY_DX4GSR0_GDQSPRD_MASK (0x3FE0000U) #define DDRPHY_DX4GSR0_GDQSPRD_SHIFT (17U) /*! GDQSPRD - Read DQS gating Period */ #define DDRPHY_DX4GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX4GSR0_GDQSPRD_MASK) #define DDRPHY_DX4GSR0_RESERVED_29_26_MASK (0x3C000000U) #define DDRPHY_DX4GSR0_RESERVED_29_26_SHIFT (26U) /*! RESERVED_29_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX4GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX4GSR0_RESERVED_29_26_MASK) #define DDRPHY_DX4GSR0_WLDQ_MASK (0x40000000U) #define DDRPHY_DX4GSR0_WLDQ_SHIFT (30U) /*! WLDQ - Write Leveling DQ Status */ #define DDRPHY_DX4GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLDQ_SHIFT)) & DDRPHY_DX4GSR0_WLDQ_MASK) #define DDRPHY_DX4GSR0_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX4GSR0_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX4GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX4GSR0_RESERVED_31_MASK) /*! @} */ /*! @name DX4GSR1 - DATX8 n General Status Register 1 */ /*! @{ */ #define DDRPHY_DX4GSR1_DLTDONE_MASK (0x1U) #define DDRPHY_DX4GSR1_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done */ #define DDRPHY_DX4GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR1_DLTDONE_SHIFT)) & DDRPHY_DX4GSR1_DLTDONE_MASK) #define DDRPHY_DX4GSR1_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_DX4GSR1_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code */ #define DDRPHY_DX4GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR1_DLTCODE_SHIFT)) & DDRPHY_DX4GSR1_DLTCODE_MASK) #define DDRPHY_DX4GSR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX4GSR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX4GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX4GSR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX4GSR2 - DATX8 n General Status Register 2 */ /*! @{ */ #define DDRPHY_DX4GSR2_RDERR_MASK (0x1U) #define DDRPHY_DX4GSR2_RDERR_SHIFT (0U) /*! RDERR - Read Bit Deskew Error */ #define DDRPHY_DX4GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_RDERR_SHIFT)) & DDRPHY_DX4GSR2_RDERR_MASK) #define DDRPHY_DX4GSR2_RDWN_MASK (0x2U) #define DDRPHY_DX4GSR2_RDWN_SHIFT (1U) /*! RDWN - Read Bit Deskew Warning */ #define DDRPHY_DX4GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_RDWN_SHIFT)) & DDRPHY_DX4GSR2_RDWN_MASK) #define DDRPHY_DX4GSR2_WDERR_MASK (0x4U) #define DDRPHY_DX4GSR2_WDERR_SHIFT (2U) /*! WDERR - Write Bit Deskew Error */ #define DDRPHY_DX4GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WDERR_SHIFT)) & DDRPHY_DX4GSR2_WDERR_MASK) #define DDRPHY_DX4GSR2_WDWN_MASK (0x8U) #define DDRPHY_DX4GSR2_WDWN_SHIFT (3U) /*! WDWN - Write Bit Deskew Warning */ #define DDRPHY_DX4GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WDWN_SHIFT)) & DDRPHY_DX4GSR2_WDWN_MASK) #define DDRPHY_DX4GSR2_REERR_MASK (0x10U) #define DDRPHY_DX4GSR2_REERR_SHIFT (4U) /*! REERR - Read Eye Centering Error */ #define DDRPHY_DX4GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_REERR_SHIFT)) & DDRPHY_DX4GSR2_REERR_MASK) #define DDRPHY_DX4GSR2_REWN_MASK (0x20U) #define DDRPHY_DX4GSR2_REWN_SHIFT (5U) /*! REWN - Read Eye Centering Warning */ #define DDRPHY_DX4GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_REWN_SHIFT)) & DDRPHY_DX4GSR2_REWN_MASK) #define DDRPHY_DX4GSR2_WEERR_MASK (0x40U) #define DDRPHY_DX4GSR2_WEERR_SHIFT (6U) /*! WEERR - Write Eye Centering Error */ #define DDRPHY_DX4GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WEERR_SHIFT)) & DDRPHY_DX4GSR2_WEERR_MASK) #define DDRPHY_DX4GSR2_WEWN_MASK (0x80U) #define DDRPHY_DX4GSR2_WEWN_SHIFT (7U) /*! WEWN - Write Eye Centering Warning */ #define DDRPHY_DX4GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WEWN_SHIFT)) & DDRPHY_DX4GSR2_WEWN_MASK) #define DDRPHY_DX4GSR2_ESTAT_MASK (0xF00U) #define DDRPHY_DX4GSR2_ESTAT_SHIFT (8U) /*! ESTAT - Error Status */ #define DDRPHY_DX4GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_ESTAT_SHIFT)) & DDRPHY_DX4GSR2_ESTAT_MASK) #define DDRPHY_DX4GSR2_DQS2DQERR_MASK (0xFF000U) #define DDRPHY_DX4GSR2_DQS2DQERR_SHIFT (12U) /*! DQS2DQERR - Write DQS2DQ Training Error */ #define DDRPHY_DX4GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX4GSR2_DQS2DQERR_MASK) #define DDRPHY_DX4GSR2_SRDERR_MASK (0x100000U) #define DDRPHY_DX4GSR2_SRDERR_SHIFT (20U) /*! SRDERR - Static Read Error */ #define DDRPHY_DX4GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_SRDERR_SHIFT)) & DDRPHY_DX4GSR2_SRDERR_MASK) #define DDRPHY_DX4GSR2_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX4GSR2_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX4GSR2_RESERVED_21_MASK) #define DDRPHY_DX4GSR2_GSDQSCAL_MASK (0x400000U) #define DDRPHY_DX4GSR2_GSDQSCAL_SHIFT (22U) /*! GSDQSCAL - Read DQS Gating Status Calibration */ #define DDRPHY_DX4GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX4GSR2_GSDQSCAL_MASK) #define DDRPHY_DX4GSR2_GSDQSPRD_MASK (0xFF800000U) #define DDRPHY_DX4GSR2_GSDQSPRD_SHIFT (23U) /*! GSDQSPRD - Read DQS gating Status Period */ #define DDRPHY_DX4GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX4GSR2_GSDQSPRD_MASK) /*! @} */ /*! @name DX4GSR3 - DATX8 n General Status Register 3 */ /*! @{ */ #define DDRPHY_DX4GSR3_SRDPC_MASK (0x3U) #define DDRPHY_DX4GSR3_SRDPC_SHIFT (0U) /*! SRDPC - Static Read Delay Pass Count */ #define DDRPHY_DX4GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_SRDPC_SHIFT)) & DDRPHY_DX4GSR3_SRDPC_MASK) #define DDRPHY_DX4GSR3_RESERVED_7_2_MASK (0xFCU) #define DDRPHY_DX4GSR3_RESERVED_7_2_SHIFT (2U) /*! RESERVED_7_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX4GSR3_RESERVED_7_2_MASK) #define DDRPHY_DX4GSR3_HVERR_MASK (0xF00U) #define DDRPHY_DX4GSR3_HVERR_SHIFT (8U) /*! HVERR - Host VREF Training Error */ #define DDRPHY_DX4GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_HVERR_SHIFT)) & DDRPHY_DX4GSR3_HVERR_MASK) #define DDRPHY_DX4GSR3_HVWRN_MASK (0xF000U) #define DDRPHY_DX4GSR3_HVWRN_SHIFT (12U) /*! HVWRN - Host VREF Training Warning */ #define DDRPHY_DX4GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_HVWRN_SHIFT)) & DDRPHY_DX4GSR3_HVWRN_MASK) #define DDRPHY_DX4GSR3_DVERR_MASK (0xF0000U) #define DDRPHY_DX4GSR3_DVERR_SHIFT (16U) /*! DVERR - DRAM VREF Training Error */ #define DDRPHY_DX4GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_DVERR_SHIFT)) & DDRPHY_DX4GSR3_DVERR_MASK) #define DDRPHY_DX4GSR3_DVWRN_MASK (0xF00000U) #define DDRPHY_DX4GSR3_DVWRN_SHIFT (20U) /*! DVWRN - DRAM VREF Training Warning */ #define DDRPHY_DX4GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_DVWRN_SHIFT)) & DDRPHY_DX4GSR3_DVWRN_MASK) #define DDRPHY_DX4GSR3_ESTAT_MASK (0x7000000U) #define DDRPHY_DX4GSR3_ESTAT_SHIFT (24U) /*! ESTAT - VREF Training Error Status Code */ #define DDRPHY_DX4GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_ESTAT_SHIFT)) & DDRPHY_DX4GSR3_ESTAT_MASK) #define DDRPHY_DX4GSR3_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX4GSR3_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX4GSR3_RESERVED_31_27_MASK) /*! @} */ /*! @name DX4GSR4 - DATX8 n General Status Register 4 */ /*! @{ */ #define DDRPHY_DX4GSR4_RESERVED_0_MASK (0x1U) #define DDRPHY_DX4GSR4_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_0_MASK) #define DDRPHY_DX4GSR4_RESERVED_1_MASK (0x2U) #define DDRPHY_DX4GSR4_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_1_MASK) #define DDRPHY_DX4GSR4_RESERVED_2_MASK (0x4U) #define DDRPHY_DX4GSR4_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_2_MASK) #define DDRPHY_DX4GSR4_RESERVED_3_MASK (0x8U) #define DDRPHY_DX4GSR4_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_3_MASK) #define DDRPHY_DX4GSR4_RESERVED_4_MASK (0x10U) #define DDRPHY_DX4GSR4_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_4_MASK) #define DDRPHY_DX4GSR4_RESERVED_5_MASK (0x20U) #define DDRPHY_DX4GSR4_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_5_MASK) #define DDRPHY_DX4GSR4_RESERVED_6_MASK (0x40U) #define DDRPHY_DX4GSR4_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_6_MASK) #define DDRPHY_DX4GSR4_RESERVED_15_7_MASK (0xFF80U) #define DDRPHY_DX4GSR4_RESERVED_15_7_SHIFT (7U) /*! RESERVED_15_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_15_7_MASK) #define DDRPHY_DX4GSR4_RESERVED_16_MASK (0x10000U) #define DDRPHY_DX4GSR4_RESERVED_16_SHIFT (16U) /*! RESERVED_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_16_MASK) #define DDRPHY_DX4GSR4_RESERVED_25_17_MASK (0x3FE0000U) #define DDRPHY_DX4GSR4_RESERVED_25_17_SHIFT (17U) /*! RESERVED_25_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_25_17_MASK) #define DDRPHY_DX4GSR4_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_DX4GSR4_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX4GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_31_26_MASK) /*! @} */ /*! @name DX4GSR5 - DATX8 n General Status Register 5 */ /*! @{ */ #define DDRPHY_DX4GSR5_RESERVED_0_MASK (0x1U) #define DDRPHY_DX4GSR5_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_0_MASK) #define DDRPHY_DX4GSR5_RESERVED_1_MASK (0x2U) #define DDRPHY_DX4GSR5_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_1_MASK) #define DDRPHY_DX4GSR5_RESERVED_2_MASK (0x4U) #define DDRPHY_DX4GSR5_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_2_MASK) #define DDRPHY_DX4GSR5_RESERVED_3_MASK (0x8U) #define DDRPHY_DX4GSR5_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_3_MASK) #define DDRPHY_DX4GSR5_RESERVED_4_MASK (0x10U) #define DDRPHY_DX4GSR5_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_4_MASK) #define DDRPHY_DX4GSR5_RESERVED_5_MASK (0x20U) #define DDRPHY_DX4GSR5_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_5_MASK) #define DDRPHY_DX4GSR5_RESERVED_6_MASK (0x40U) #define DDRPHY_DX4GSR5_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_6_MASK) #define DDRPHY_DX4GSR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX4GSR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_7_MASK) #define DDRPHY_DX4GSR5_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX4GSR5_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_11_8_MASK) #define DDRPHY_DX4GSR5_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_DX4GSR5_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_19_12_MASK) #define DDRPHY_DX4GSR5_RESERVED_20_MASK (0x100000U) #define DDRPHY_DX4GSR5_RESERVED_20_SHIFT (20U) /*! RESERVED_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_20_MASK) #define DDRPHY_DX4GSR5_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX4GSR5_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_21_MASK) #define DDRPHY_DX4GSR5_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX4GSR5_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_22_MASK) #define DDRPHY_DX4GSR5_RESERVED_31_23_MASK (0xFF800000U) #define DDRPHY_DX4GSR5_RESERVED_31_23_SHIFT (23U) /*! RESERVED_31_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_31_23_MASK) /*! @} */ /*! @name DX4GSR6 - DATX8 n General Status Register 6 */ /*! @{ */ #define DDRPHY_DX4GSR6_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX4GSR6_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_1_0_MASK) #define DDRPHY_DX4GSR6_RESERVED_3_2_MASK (0xCU) #define DDRPHY_DX4GSR6_RESERVED_3_2_SHIFT (2U) /*! RESERVED_3_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_3_2_MASK) #define DDRPHY_DX4GSR6_RESERVED_7_4_MASK (0xF0U) #define DDRPHY_DX4GSR6_RESERVED_7_4_SHIFT (4U) /*! RESERVED_7_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_7_4_MASK) #define DDRPHY_DX4GSR6_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX4GSR6_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_11_8_MASK) #define DDRPHY_DX4GSR6_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_DX4GSR6_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_15_12_MASK) #define DDRPHY_DX4GSR6_RESERVED_19_15_MASK (0xF0000U) #define DDRPHY_DX4GSR6_RESERVED_19_15_SHIFT (16U) /*! RESERVED_19_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_19_15_MASK) #define DDRPHY_DX4GSR6_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX4GSR6_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_23_20_MASK) #define DDRPHY_DX4GSR6_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX4GSR6_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_31_24_MASK) /*! @} */ /*! @name DX5GCR0 - DATX8 n General Configuration Register 0 */ /*! @{ */ #define DDRPHY_DX5GCR0_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX5GCR0_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX5GCR0_RESERVED_1_0_MASK) #define DDRPHY_DX5GCR0_DQSGOE_MASK (0x4U) #define DDRPHY_DX5GCR0_DQSGOE_SHIFT (2U) /*! DQSGOE - DQSG Output Enable */ #define DDRPHY_DX5GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSGOE_SHIFT)) & DDRPHY_DX5GCR0_DQSGOE_MASK) #define DDRPHY_DX5GCR0_DQSGODT_MASK (0x8U) #define DDRPHY_DX5GCR0_DQSGODT_SHIFT (3U) /*! DQSGODT - DQSG On-Die Termination */ #define DDRPHY_DX5GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSGODT_SHIFT)) & DDRPHY_DX5GCR0_DQSGODT_MASK) #define DDRPHY_DX5GCR0_RESERVED_4_MASK (0x10U) #define DDRPHY_DX5GCR0_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX5GCR0_RESERVED_4_MASK) #define DDRPHY_DX5GCR0_DQSGPDR_MASK (0x20U) #define DDRPHY_DX5GCR0_DQSGPDR_SHIFT (5U) /*! DQSGPDR - DQSG Power Down Receiver */ #define DDRPHY_DX5GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX5GCR0_DQSGPDR_MASK) #define DDRPHY_DX5GCR0_DQSRPD_MASK (0x40U) #define DDRPHY_DX5GCR0_DQSRPD_SHIFT (6U) /*! DQSRPD - DQSR Power Down */ #define DDRPHY_DX5GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSRPD_SHIFT)) & DDRPHY_DX5GCR0_DQSRPD_MASK) #define DDRPHY_DX5GCR0_CPDRSHFT_MASK (0x180U) #define DDRPHY_DX5GCR0_CPDRSHFT_SHIFT (7U) /*! CPDRSHFT - Configurable PDR Phase Shift */ #define DDRPHY_DX5GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX5GCR0_CPDRSHFT_MASK) #define DDRPHY_DX5GCR0_RTTOH_MASK (0x600U) #define DDRPHY_DX5GCR0_RTTOH_SHIFT (9U) /*! RTTOH - RTT Output Hold */ #define DDRPHY_DX5GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RTTOH_SHIFT)) & DDRPHY_DX5GCR0_RTTOH_MASK) #define DDRPHY_DX5GCR0_RTTOAL_MASK (0x800U) #define DDRPHY_DX5GCR0_RTTOAL_SHIFT (11U) /*! RTTOAL - RTT On Additive Latency */ #define DDRPHY_DX5GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RTTOAL_SHIFT)) & DDRPHY_DX5GCR0_RTTOAL_MASK) #define DDRPHY_DX5GCR0_DQSSEPDR_MASK (0x1000U) #define DDRPHY_DX5GCR0_DQSSEPDR_SHIFT (12U) /*! DQSSEPDR - DQSSE Power Down Receiver */ #define DDRPHY_DX5GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX5GCR0_DQSSEPDR_MASK) #define DDRPHY_DX5GCR0_DQSNSEPDR_MASK (0x2000U) #define DDRPHY_DX5GCR0_DQSNSEPDR_SHIFT (13U) /*! DQSNSEPDR - DQSNSE Power Down Receiver */ #define DDRPHY_DX5GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX5GCR0_DQSNSEPDR_MASK) #define DDRPHY_DX5GCR0_RESERVED_19_14_MASK (0xFC000U) #define DDRPHY_DX5GCR0_RESERVED_19_14_SHIFT (14U) /*! RESERVED_19_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX5GCR0_RESERVED_19_14_MASK) #define DDRPHY_DX5GCR0_RDDLY_MASK (0xF00000U) #define DDRPHY_DX5GCR0_RDDLY_SHIFT (20U) /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY */ #define DDRPHY_DX5GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RDDLY_SHIFT)) & DDRPHY_DX5GCR0_RDDLY_MASK) #define DDRPHY_DX5GCR0_DQSDCC_MASK (0xF000000U) #define DDRPHY_DX5GCR0_DQSDCC_SHIFT (24U) /*! DQSDCC - DQS Duty Cycle Correction */ #define DDRPHY_DX5GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSDCC_SHIFT)) & DDRPHY_DX5GCR0_DQSDCC_MASK) #define DDRPHY_DX5GCR0_CODTSHFT_MASK (0x30000000U) #define DDRPHY_DX5GCR0_CODTSHFT_SHIFT (28U) /*! CODTSHFT - Configurable ODT(TE) Phase Shift */ #define DDRPHY_DX5GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX5GCR0_CODTSHFT_MASK) #define DDRPHY_DX5GCR0_MDLEN_MASK (0x40000000U) #define DDRPHY_DX5GCR0_MDLEN_SHIFT (30U) /*! MDLEN - Master Delay Line Enable */ #define DDRPHY_DX5GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_MDLEN_SHIFT)) & DDRPHY_DX5GCR0_MDLEN_MASK) #define DDRPHY_DX5GCR0_CALBYP_MASK (0x80000000U) #define DDRPHY_DX5GCR0_CALBYP_SHIFT (31U) /*! CALBYP - Calibration Bypass */ #define DDRPHY_DX5GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_CALBYP_SHIFT)) & DDRPHY_DX5GCR0_CALBYP_MASK) /*! @} */ /*! @name DX5GCR1 - DATX8 n General Configuration Register 1 */ /*! @{ */ #define DDRPHY_DX5GCR1_DQEN_MASK (0xFFU) #define DDRPHY_DX5GCR1_DQEN_SHIFT (0U) /*! DQEN - Enables DQ corresponding to each bit in a byte */ #define DDRPHY_DX5GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DQEN_SHIFT)) & DDRPHY_DX5GCR1_DQEN_MASK) #define DDRPHY_DX5GCR1_DMEN_MASK (0x100U) #define DDRPHY_DX5GCR1_DMEN_SHIFT (8U) /*! DMEN - Enables DM pin in a byte lane */ #define DDRPHY_DX5GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DMEN_SHIFT)) & DDRPHY_DX5GCR1_DMEN_MASK) #define DDRPHY_DX5GCR1_DSEN_MASK (0x200U) #define DDRPHY_DX5GCR1_DSEN_SHIFT (9U) /*! DSEN - Enables Write Data strobe in a byte lane */ #define DDRPHY_DX5GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DSEN_SHIFT)) & DDRPHY_DX5GCR1_DSEN_MASK) #define DDRPHY_DX5GCR1_TEEN_MASK (0x400U) #define DDRPHY_DX5GCR1_TEEN_SHIFT (10U) /*! TEEN - Enables ODT/TE in a byte lane */ #define DDRPHY_DX5GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_TEEN_SHIFT)) & DDRPHY_DX5GCR1_TEEN_MASK) #define DDRPHY_DX5GCR1_PDREN_MASK (0x800U) #define DDRPHY_DX5GCR1_PDREN_SHIFT (11U) /*! PDREN - Enables PDR in a byte lane */ #define DDRPHY_DX5GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_PDREN_SHIFT)) & DDRPHY_DX5GCR1_PDREN_MASK) #define DDRPHY_DX5GCR1_OEEN_MASK (0x1000U) #define DDRPHY_DX5GCR1_OEEN_SHIFT (12U) /*! OEEN - Enables Read Data Strobe in a byte lane */ #define DDRPHY_DX5GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_OEEN_SHIFT)) & DDRPHY_DX5GCR1_OEEN_MASK) #define DDRPHY_DX5GCR1_QSSEL_MASK (0x2000U) #define DDRPHY_DX5GCR1_QSSEL_SHIFT (13U) /*! QSSEL - Select the delayed or non-delayed read data strobe */ #define DDRPHY_DX5GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_QSSEL_SHIFT)) & DDRPHY_DX5GCR1_QSSEL_MASK) #define DDRPHY_DX5GCR1_QSNSEL_MASK (0x4000U) #define DDRPHY_DX5GCR1_QSNSEL_SHIFT (14U) /*! QSNSEL - Select the delayed or non-delayed read data strobe # */ #define DDRPHY_DX5GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_QSNSEL_SHIFT)) & DDRPHY_DX5GCR1_QSNSEL_MASK) #define DDRPHY_DX5GCR1_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX5GCR1_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX5GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX5GCR1_RESERVED_15_MASK) #define DDRPHY_DX5GCR1_DXPDRMODE_MASK (0xFFFF0000U) #define DDRPHY_DX5GCR1_DXPDRMODE_SHIFT (16U) /*! DXPDRMODE - Enables the PDR mode for DQ[7:0] */ #define DDRPHY_DX5GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX5GCR1_DXPDRMODE_MASK) /*! @} */ /*! @name DX5GCR2 - DATX8 n General Configuration Register 2 */ /*! @{ */ #define DDRPHY_DX5GCR2_DXTEMODE_MASK (0xFFFFU) #define DDRPHY_DX5GCR2_DXTEMODE_SHIFT (0U) /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0] */ #define DDRPHY_DX5GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX5GCR2_DXTEMODE_MASK) #define DDRPHY_DX5GCR2_DXOEMODE_MASK (0xFFFF0000U) #define DDRPHY_DX5GCR2_DXOEMODE_SHIFT (16U) /*! DXOEMODE - Enables the OE mode values for DQ[7:0] */ #define DDRPHY_DX5GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX5GCR2_DXOEMODE_MASK) /*! @} */ /*! @name DX5GCR3 - DATX8 n General Configuration Register 3 */ /*! @{ */ #define DDRPHY_DX5GCR3_WDMBVT_MASK (0x1U) #define DDRPHY_DX5GCR3_WDMBVT_SHIFT (0U) /*! WDMBVT - Write Data Mask BDL VT Compensation */ #define DDRPHY_DX5GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDMBVT_SHIFT)) & DDRPHY_DX5GCR3_WDMBVT_MASK) #define DDRPHY_DX5GCR3_RDMBVT_MASK (0x2U) #define DDRPHY_DX5GCR3_RDMBVT_SHIFT (1U) /*! RDMBVT - Read Data Mask BDL VT Compensation */ #define DDRPHY_DX5GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RDMBVT_SHIFT)) & DDRPHY_DX5GCR3_RDMBVT_MASK) #define DDRPHY_DX5GCR3_DSPDRMODE_MASK (0xCU) #define DDRPHY_DX5GCR3_DSPDRMODE_SHIFT (2U) /*! DSPDRMODE - Enables the PDR mode values for DQS. */ #define DDRPHY_DX5GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX5GCR3_DSPDRMODE_MASK) #define DDRPHY_DX5GCR3_DSTEMODE_MASK (0x30U) #define DDRPHY_DX5GCR3_DSTEMODE_SHIFT (4U) /*! DSTEMODE - Enables the TE mode values for DQS. */ #define DDRPHY_DX5GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSTEMODE_MASK) #define DDRPHY_DX5GCR3_DSOEMODE_MASK (0xC0U) #define DDRPHY_DX5GCR3_DSOEMODE_SHIFT (6U) /*! DSOEMODE - Enables the OE mode values for DQS. */ #define DDRPHY_DX5GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSOEMODE_MASK) #define DDRPHY_DX5GCR3_WDSBVT_MASK (0x100U) #define DDRPHY_DX5GCR3_WDSBVT_SHIFT (8U) /*! WDSBVT - Write Data Strobe BDL VT Compensation */ #define DDRPHY_DX5GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDSBVT_SHIFT)) & DDRPHY_DX5GCR3_WDSBVT_MASK) #define DDRPHY_DX5GCR3_RESERVED_9_MASK (0x200U) #define DDRPHY_DX5GCR3_RESERVED_9_SHIFT (9U) /*! RESERVED_9 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX5GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX5GCR3_RESERVED_9_MASK) #define DDRPHY_DX5GCR3_DMPDRMODE_MASK (0xC00U) #define DDRPHY_DX5GCR3_DMPDRMODE_SHIFT (10U) /*! DMPDRMODE - Enables the PDR mode values for DM. */ #define DDRPHY_DX5GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX5GCR3_DMPDRMODE_MASK) #define DDRPHY_DX5GCR3_DMTEMODE_MASK (0x3000U) #define DDRPHY_DX5GCR3_DMTEMODE_SHIFT (12U) /*! DMTEMODE - Enables the TE mode values for DM. */ #define DDRPHY_DX5GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX5GCR3_DMTEMODE_MASK) #define DDRPHY_DX5GCR3_DMOEMODE_MASK (0xC000U) #define DDRPHY_DX5GCR3_DMOEMODE_SHIFT (14U) /*! DMOEMODE - Enables the OE mode values for DM. */ #define DDRPHY_DX5GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX5GCR3_DMOEMODE_MASK) #define DDRPHY_DX5GCR3_DSNPDRMODE_MASK (0x30000U) #define DDRPHY_DX5GCR3_DSNPDRMODE_SHIFT (16U) /*! DSNPDRMODE - Enables the PDR mode for DQS */ #define DDRPHY_DX5GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX5GCR3_DSNPDRMODE_MASK) #define DDRPHY_DX5GCR3_DSNTEMODE_MASK (0xC0000U) #define DDRPHY_DX5GCR3_DSNTEMODE_SHIFT (18U) /*! DSNTEMODE - Enables the TE mode for DQS */ #define DDRPHY_DX5GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSNTEMODE_MASK) #define DDRPHY_DX5GCR3_DSNOEMODE_MASK (0x300000U) #define DDRPHY_DX5GCR3_DSNOEMODE_SHIFT (20U) /*! DSNOEMODE - Enables the OE mode for DQs */ #define DDRPHY_DX5GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSNOEMODE_MASK) #define DDRPHY_DX5GCR3_PDRBVT_MASK (0x400000U) #define DDRPHY_DX5GCR3_PDRBVT_SHIFT (22U) /*! PDRBVT - Power Down Receiver BDL VT Compensation */ #define DDRPHY_DX5GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_PDRBVT_SHIFT)) & DDRPHY_DX5GCR3_PDRBVT_MASK) #define DDRPHY_DX5GCR3_RGSLVT_MASK (0x800000U) #define DDRPHY_DX5GCR3_RGSLVT_SHIFT (23U) /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation */ #define DDRPHY_DX5GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RGSLVT_SHIFT)) & DDRPHY_DX5GCR3_RGSLVT_MASK) #define DDRPHY_DX5GCR3_WLLVT_MASK (0x1000000U) #define DDRPHY_DX5GCR3_WLLVT_SHIFT (24U) /*! WLLVT - Write Leveling LCDL Delay VT Compensation */ #define DDRPHY_DX5GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WLLVT_SHIFT)) & DDRPHY_DX5GCR3_WLLVT_MASK) #define DDRPHY_DX5GCR3_WDLVT_MASK (0x2000000U) #define DDRPHY_DX5GCR3_WDLVT_SHIFT (25U) /*! WDLVT - Write DQ LCDL Delay VT Compensation */ #define DDRPHY_DX5GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDLVT_SHIFT)) & DDRPHY_DX5GCR3_WDLVT_MASK) #define DDRPHY_DX5GCR3_RDLVT_MASK (0x4000000U) #define DDRPHY_DX5GCR3_RDLVT_SHIFT (26U) /*! RDLVT - Read DQS LCDL Delay VT Compensation */ #define DDRPHY_DX5GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RDLVT_SHIFT)) & DDRPHY_DX5GCR3_RDLVT_MASK) #define DDRPHY_DX5GCR3_RGLVT_MASK (0x8000000U) #define DDRPHY_DX5GCR3_RGLVT_SHIFT (27U) /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation */ #define DDRPHY_DX5GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RGLVT_SHIFT)) & DDRPHY_DX5GCR3_RGLVT_MASK) #define DDRPHY_DX5GCR3_WDBVT_MASK (0x10000000U) #define DDRPHY_DX5GCR3_WDBVT_SHIFT (28U) /*! WDBVT - Write Data BDL VT Compensation */ #define DDRPHY_DX5GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDBVT_SHIFT)) & DDRPHY_DX5GCR3_WDBVT_MASK) #define DDRPHY_DX5GCR3_RDBVT_MASK (0x20000000U) #define DDRPHY_DX5GCR3_RDBVT_SHIFT (29U) /*! RDBVT - Read Data BDL VT Compensation */ #define DDRPHY_DX5GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RDBVT_SHIFT)) & DDRPHY_DX5GCR3_RDBVT_MASK) #define DDRPHY_DX5GCR3_TEBVT_MASK (0x40000000U) #define DDRPHY_DX5GCR3_TEBVT_SHIFT (30U) /*! TEBVT - Termination Enable BDL VT Compensation */ #define DDRPHY_DX5GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_TEBVT_SHIFT)) & DDRPHY_DX5GCR3_TEBVT_MASK) #define DDRPHY_DX5GCR3_OEBVT_MASK (0x80000000U) #define DDRPHY_DX5GCR3_OEBVT_SHIFT (31U) /*! OEBVT - Output Enable BDL VT Compensation */ #define DDRPHY_DX5GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_OEBVT_SHIFT)) & DDRPHY_DX5GCR3_OEBVT_MASK) /*! @} */ /*! @name DX5GCR4 - DATX8 n General Configuration Register 4 */ /*! @{ */ #define DDRPHY_DX5GCR4_DXREFIMON_MASK (0x3U) #define DDRPHY_DX5GCR4_DXREFIMON_SHIFT (0U) /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX5GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX5GCR4_DXREFIMON_MASK) #define DDRPHY_DX5GCR4_DXREFIEN_MASK (0x3CU) #define DDRPHY_DX5GCR4_DXREFIEN_SHIFT (2U) /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX5GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFIEN_MASK) #define DDRPHY_DX5GCR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5GCR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX5GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR4_RESERVED_7_6_MASK) #define DDRPHY_DX5GCR4_DXREFSSEL_MASK (0x7F00U) #define DDRPHY_DX5GCR4_DXREFSSEL_SHIFT (8U) /*! DXREFSSEL - Byte Lane Single-End VREF Select */ #define DDRPHY_DX5GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX5GCR4_DXREFSSEL_MASK) #define DDRPHY_DX5GCR4_DXREFSSELRANGE_MASK (0x8000U) #define DDRPHY_DX5GCR4_DXREFSSELRANGE_SHIFT (15U) /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select */ #define DDRPHY_DX5GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX5GCR4_DXREFSSELRANGE_MASK) #define DDRPHY_DX5GCR4_DXREFESEL_MASK (0x7F0000U) #define DDRPHY_DX5GCR4_DXREFESEL_SHIFT (16U) /*! DXREFESEL - Byte Lane External VREF Select */ #define DDRPHY_DX5GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX5GCR4_DXREFESEL_MASK) #define DDRPHY_DX5GCR4_DXREFESELRANGE_MASK (0x800000U) #define DDRPHY_DX5GCR4_DXREFESELRANGE_SHIFT (23U) /*! DXREFESELRANGE - External VREF generator REFSEL range select */ #define DDRPHY_DX5GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX5GCR4_DXREFESELRANGE_MASK) #define DDRPHY_DX5GCR4_RESERVED_24_MASK (0x1000000U) #define DDRPHY_DX5GCR4_RESERVED_24_SHIFT (24U) /*! RESERVED_24 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX5GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX5GCR4_RESERVED_24_MASK) #define DDRPHY_DX5GCR4_DXREFSEN_MASK (0x2000000U) #define DDRPHY_DX5GCR4_DXREFSEN_SHIFT (25U) /*! DXREFSEN - Byte Lane Single-End VREF Enable */ #define DDRPHY_DX5GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFSEN_MASK) #define DDRPHY_DX5GCR4_DXREFEEN_MASK (0xC000000U) #define DDRPHY_DX5GCR4_DXREFEEN_SHIFT (26U) /*! DXREFEEN - Byte Lane Internal VREF Enable */ #define DDRPHY_DX5GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFEEN_MASK) #define DDRPHY_DX5GCR4_DXREFPEN_MASK (0x10000000U) #define DDRPHY_DX5GCR4_DXREFPEN_SHIFT (28U) /*! DXREFPEN - Byte Lane VREF Pad Enable */ #define DDRPHY_DX5GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFPEN_MASK) #define DDRPHY_DX5GCR4_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DX5GCR4_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs) */ #define DDRPHY_DX5GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX5GCR4_RESERVED_31_29_MASK) /*! @} */ /*! @name DX5GCR5 - DATX8 n General Configuration Register 5 */ /*! @{ */ #define DDRPHY_DX5GCR5_DXREFISELR0_MASK (0x7FU) #define DDRPHY_DX5GCR5_DXREFISELR0_SHIFT (0U) /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0 */ #define DDRPHY_DX5GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR0_MASK) #define DDRPHY_DX5GCR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX5GCR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX5GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_7_MASK) #define DDRPHY_DX5GCR5_DXREFISELR1_MASK (0x7F00U) #define DDRPHY_DX5GCR5_DXREFISELR1_SHIFT (8U) /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1 */ #define DDRPHY_DX5GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR1_MASK) #define DDRPHY_DX5GCR5_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX5GCR5_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX5GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_15_MASK) #define DDRPHY_DX5GCR5_DXREFISELR2_MASK (0x7F0000U) #define DDRPHY_DX5GCR5_DXREFISELR2_SHIFT (16U) /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2 */ #define DDRPHY_DX5GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR2_MASK) #define DDRPHY_DX5GCR5_RESERVED_23_MASK (0x800000U) #define DDRPHY_DX5GCR5_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX5GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_23_MASK) #define DDRPHY_DX5GCR5_DXREFISELR3_MASK (0x7F000000U) #define DDRPHY_DX5GCR5_DXREFISELR3_SHIFT (24U) /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3 */ #define DDRPHY_DX5GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR3_MASK) #define DDRPHY_DX5GCR5_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX5GCR5_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX5GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_31_MASK) /*! @} */ /*! @name DX5GCR6 - DATX8 n General Configuration Register 6 */ /*! @{ */ #define DDRPHY_DX5GCR6_DXDQVREFR0_MASK (0x3FU) #define DDRPHY_DX5GCR6_DXDQVREFR0_SHIFT (0U) /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0 */ #define DDRPHY_DX5GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR0_MASK) #define DDRPHY_DX5GCR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5GCR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX5GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_7_6_MASK) #define DDRPHY_DX5GCR6_DXDQVREFR1_MASK (0x3F00U) #define DDRPHY_DX5GCR6_DXDQVREFR1_SHIFT (8U) /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1 */ #define DDRPHY_DX5GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR1_MASK) #define DDRPHY_DX5GCR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5GCR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX5GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_15_14_MASK) #define DDRPHY_DX5GCR6_DXDQVREFR2_MASK (0x3F0000U) #define DDRPHY_DX5GCR6_DXDQVREFR2_SHIFT (16U) /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2 */ #define DDRPHY_DX5GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR2_MASK) #define DDRPHY_DX5GCR6_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX5GCR6_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX5GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_23_22_MASK) #define DDRPHY_DX5GCR6_DXDQVREFR3_MASK (0x3F000000U) #define DDRPHY_DX5GCR6_DXDQVREFR3_SHIFT (24U) /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3 */ #define DDRPHY_DX5GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR3_MASK) #define DDRPHY_DX5GCR6_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX5GCR6_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX5GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_31_30_MASK) /*! @} */ /*! @name DX5GCR7 - DATX8 n General Configuration Register 7 */ /*! @{ */ #define DDRPHY_DX5GCR7_DCALSVAL_MASK (0x1FFU) #define DDRPHY_DX5GCR7_DCALSVAL_SHIFT (0U) /*! DCALSVAL - DDL Calibration Starting Value */ #define DDRPHY_DX5GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX5GCR7_DCALSVAL_MASK) #define DDRPHY_DX5GCR7_DCALTYPE_MASK (0x200U) #define DDRPHY_DX5GCR7_DCALTYPE_SHIFT (9U) /*! DCALTYPE - DDL Calibration Type */ #define DDRPHY_DX5GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX5GCR7_DCALTYPE_MASK) #define DDRPHY_DX5GCR7_RESERVED_17_10_MASK (0x3FC00U) #define DDRPHY_DX5GCR7_RESERVED_17_10_SHIFT (10U) /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX5GCR7_RESERVED_17_10_MASK) #define DDRPHY_DX5GCR7_RESERVED_18_MASK (0x40000U) #define DDRPHY_DX5GCR7_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX5GCR7_RESERVED_18_MASK) #define DDRPHY_DX5GCR7_RESERVED_31_19_MASK (0xFFF80000U) #define DDRPHY_DX5GCR7_RESERVED_31_19_SHIFT (19U) /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX5GCR7_RESERVED_31_19_MASK) /*! @} */ /*! @name DX5GCR8 - DATX8 n General Configuration Register 8 */ /*! @{ */ #define DDRPHY_DX5GCR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX5GCR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_5_0_MASK) #define DDRPHY_DX5GCR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5GCR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_7_6_MASK) #define DDRPHY_DX5GCR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX5GCR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_13_8_MASK) #define DDRPHY_DX5GCR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5GCR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_15_14_MASK) #define DDRPHY_DX5GCR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX5GCR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_21_16_MASK) #define DDRPHY_DX5GCR8_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX5GCR8_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_23_22_MASK) #define DDRPHY_DX5GCR8_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX5GCR8_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_29_24_MASK) #define DDRPHY_DX5GCR8_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX5GCR8_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_31_30_MASK) /*! @} */ /*! @name DX5GCR9 - DATX8 n General Configuration Register 9 */ /*! @{ */ #define DDRPHY_DX5GCR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX5GCR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_5_0_MASK) #define DDRPHY_DX5GCR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5GCR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_7_6_MASK) #define DDRPHY_DX5GCR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX5GCR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_13_8_MASK) #define DDRPHY_DX5GCR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5GCR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_15_14_MASK) #define DDRPHY_DX5GCR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX5GCR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_21_16_MASK) #define DDRPHY_DX5GCR9_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX5GCR9_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_23_22_MASK) #define DDRPHY_DX5GCR9_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX5GCR9_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_29_24_MASK) #define DDRPHY_DX5GCR9_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX5GCR9_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_31_30_MASK) /*! @} */ /*! @name DX5DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */ /*! @{ */ #define DDRPHY_DX5DQMAP0_DQ0MAP_MASK (0xFU) #define DDRPHY_DX5DQMAP0_DQ0MAP_SHIFT (0U) /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index */ #define DDRPHY_DX5DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ0MAP_MASK) #define DDRPHY_DX5DQMAP0_DQ1MAP_MASK (0xF0U) #define DDRPHY_DX5DQMAP0_DQ1MAP_SHIFT (4U) /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index */ #define DDRPHY_DX5DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ1MAP_MASK) #define DDRPHY_DX5DQMAP0_DQ2MAP_MASK (0xF00U) #define DDRPHY_DX5DQMAP0_DQ2MAP_SHIFT (8U) /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index */ #define DDRPHY_DX5DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ2MAP_MASK) #define DDRPHY_DX5DQMAP0_DQ3MAP_MASK (0xF000U) #define DDRPHY_DX5DQMAP0_DQ3MAP_SHIFT (12U) /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index */ #define DDRPHY_DX5DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ3MAP_MASK) #define DDRPHY_DX5DQMAP0_DQ4MAP_MASK (0xF0000U) #define DDRPHY_DX5DQMAP0_DQ4MAP_SHIFT (16U) /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index */ #define DDRPHY_DX5DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ4MAP_MASK) #define DDRPHY_DX5DQMAP0_RESERVED_30_20_MASK (0x7FF00000U) #define DDRPHY_DX5DQMAP0_RESERVED_30_20_SHIFT (20U) /*! RESERVED_30_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX5DQMAP0_RESERVED_30_20_MASK) #define DDRPHY_DX5DQMAP0_MAPOK_MASK (0x80000000U) #define DDRPHY_DX5DQMAP0_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX5DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX5DQMAP0_MAPOK_MASK) /*! @} */ /*! @name DX5DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */ /*! @{ */ #define DDRPHY_DX5DQMAP1_DQ5MAP_MASK (0xFU) #define DDRPHY_DX5DQMAP1_DQ5MAP_SHIFT (0U) /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index */ #define DDRPHY_DX5DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX5DQMAP1_DQ5MAP_MASK) #define DDRPHY_DX5DQMAP1_DQ6MAP_MASK (0xF0U) #define DDRPHY_DX5DQMAP1_DQ6MAP_SHIFT (4U) /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index */ #define DDRPHY_DX5DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX5DQMAP1_DQ6MAP_MASK) #define DDRPHY_DX5DQMAP1_DQ7MAP_MASK (0xF00U) #define DDRPHY_DX5DQMAP1_DQ7MAP_SHIFT (8U) /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index */ #define DDRPHY_DX5DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX5DQMAP1_DQ7MAP_MASK) #define DDRPHY_DX5DQMAP1_DMMAP_MASK (0xF000U) #define DDRPHY_DX5DQMAP1_DMMAP_SHIFT (12U) /*! DMMAP - DM bit DATX8 slice mapping index */ #define DDRPHY_DX5DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX5DQMAP1_DMMAP_MASK) #define DDRPHY_DX5DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U) #define DDRPHY_DX5DQMAP1_RESERVED_30_16_SHIFT (16U) /*! RESERVED_30_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX5DQMAP1_RESERVED_30_16_MASK) #define DDRPHY_DX5DQMAP1_MAPOK_MASK (0x80000000U) #define DDRPHY_DX5DQMAP1_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX5DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX5DQMAP1_MAPOK_MASK) /*! @} */ /*! @name DX5BDLR0 - DATX8 n Bit Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX5BDLR0_DQ0WBD_MASK (0x3FU) #define DDRPHY_DX5BDLR0_DQ0WBD_SHIFT (0U) /*! DQ0WBD - DQ0 Write Bit Delay */ #define DDRPHY_DX5BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ0WBD_MASK) #define DDRPHY_DX5BDLR0_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5BDLR0_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_7_6_MASK) #define DDRPHY_DX5BDLR0_DQ1WBD_MASK (0x3F00U) #define DDRPHY_DX5BDLR0_DQ1WBD_SHIFT (8U) /*! DQ1WBD - DQ1 Write Bit Delay */ #define DDRPHY_DX5BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ1WBD_MASK) #define DDRPHY_DX5BDLR0_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5BDLR0_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_15_14_MASK) #define DDRPHY_DX5BDLR0_DQ2WBD_MASK (0x3F0000U) #define DDRPHY_DX5BDLR0_DQ2WBD_SHIFT (16U) /*! DQ2WBD - DQ2 Write Bit Delay */ #define DDRPHY_DX5BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ2WBD_MASK) #define DDRPHY_DX5BDLR0_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX5BDLR0_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_23_22_MASK) #define DDRPHY_DX5BDLR0_DQ3WBD_MASK (0x3F000000U) #define DDRPHY_DX5BDLR0_DQ3WBD_SHIFT (24U) /*! DQ3WBD - DQ3 Write Bit Delay */ #define DDRPHY_DX5BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ3WBD_MASK) #define DDRPHY_DX5BDLR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX5BDLR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_31_30_MASK) /*! @} */ /*! @name DX5BDLR1 - DATX8 n Bit Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX5BDLR1_DQ4WBD_MASK (0x3FU) #define DDRPHY_DX5BDLR1_DQ4WBD_SHIFT (0U) /*! DQ4WBD - DQ4 Write Bit Delay */ #define DDRPHY_DX5BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ4WBD_MASK) #define DDRPHY_DX5BDLR1_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5BDLR1_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_7_6_MASK) #define DDRPHY_DX5BDLR1_DQ5WBD_MASK (0x3F00U) #define DDRPHY_DX5BDLR1_DQ5WBD_SHIFT (8U) /*! DQ5WBD - DQ5 Write Bit Delay */ #define DDRPHY_DX5BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ5WBD_MASK) #define DDRPHY_DX5BDLR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5BDLR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_15_14_MASK) #define DDRPHY_DX5BDLR1_DQ6WBD_MASK (0x3F0000U) #define DDRPHY_DX5BDLR1_DQ6WBD_SHIFT (16U) /*! DQ6WBD - DQ6 Write Bit Delay */ #define DDRPHY_DX5BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ6WBD_MASK) #define DDRPHY_DX5BDLR1_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX5BDLR1_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_23_22_MASK) #define DDRPHY_DX5BDLR1_DQ7WBD_MASK (0x3F000000U) #define DDRPHY_DX5BDLR1_DQ7WBD_SHIFT (24U) /*! DQ7WBD - DQ7 Write Bit Delay */ #define DDRPHY_DX5BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ7WBD_MASK) #define DDRPHY_DX5BDLR1_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX5BDLR1_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_31_30_MASK) /*! @} */ /*! @name DX5BDLR2 - DATX8 n Bit Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX5BDLR2_DMWBD_MASK (0x3FU) #define DDRPHY_DX5BDLR2_DMWBD_SHIFT (0U) /*! DMWBD - DM Write Bit Delay */ #define DDRPHY_DX5BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DMWBD_SHIFT)) & DDRPHY_DX5BDLR2_DMWBD_MASK) #define DDRPHY_DX5BDLR2_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5BDLR2_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_7_6_MASK) #define DDRPHY_DX5BDLR2_DSWBD_MASK (0x3F00U) #define DDRPHY_DX5BDLR2_DSWBD_SHIFT (8U) /*! DSWBD - DQS Write Bit Delay */ #define DDRPHY_DX5BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DSWBD_SHIFT)) & DDRPHY_DX5BDLR2_DSWBD_MASK) #define DDRPHY_DX5BDLR2_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5BDLR2_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_15_14_MASK) #define DDRPHY_DX5BDLR2_DSOEBD_MASK (0x3F0000U) #define DDRPHY_DX5BDLR2_DSOEBD_SHIFT (16U) /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay */ #define DDRPHY_DX5BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX5BDLR2_DSOEBD_MASK) #define DDRPHY_DX5BDLR2_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX5BDLR2_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_23_22_MASK) #define DDRPHY_DX5BDLR2_DSNWBD_MASK (0x3F000000U) #define DDRPHY_DX5BDLR2_DSNWBD_SHIFT (24U) /*! DSNWBD - DQSN Write Bit Delay */ #define DDRPHY_DX5BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX5BDLR2_DSNWBD_MASK) #define DDRPHY_DX5BDLR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX5BDLR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_31_30_MASK) /*! @} */ /*! @name DX5BDLR3 - DATX8 n Bit Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX5BDLR3_DQ0RBD_MASK (0x3FU) #define DDRPHY_DX5BDLR3_DQ0RBD_SHIFT (0U) /*! DQ0RBD - DQ0 Read Bit Delay */ #define DDRPHY_DX5BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ0RBD_MASK) #define DDRPHY_DX5BDLR3_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5BDLR3_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_7_6_MASK) #define DDRPHY_DX5BDLR3_DQ1RBD_MASK (0x3F00U) #define DDRPHY_DX5BDLR3_DQ1RBD_SHIFT (8U) /*! DQ1RBD - DQ1 Read Bit Delay */ #define DDRPHY_DX5BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ1RBD_MASK) #define DDRPHY_DX5BDLR3_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5BDLR3_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_15_14_MASK) #define DDRPHY_DX5BDLR3_DQ2RBD_MASK (0x3F0000U) #define DDRPHY_DX5BDLR3_DQ2RBD_SHIFT (16U) /*! DQ2RBD - DQ2 Read Bit Delay */ #define DDRPHY_DX5BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ2RBD_MASK) #define DDRPHY_DX5BDLR3_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX5BDLR3_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_23_22_MASK) #define DDRPHY_DX5BDLR3_DQ3RBD_MASK (0x3F000000U) #define DDRPHY_DX5BDLR3_DQ3RBD_SHIFT (24U) /*! DQ3RBD - DQ3 Read Bit Delay */ #define DDRPHY_DX5BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ3RBD_MASK) #define DDRPHY_DX5BDLR3_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX5BDLR3_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_31_30_MASK) /*! @} */ /*! @name DX5BDLR4 - DATX8 n Bit Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX5BDLR4_DQ4RBD_MASK (0x3FU) #define DDRPHY_DX5BDLR4_DQ4RBD_SHIFT (0U) /*! DQ4RBD - DQ4 Read Bit Delay */ #define DDRPHY_DX5BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ4RBD_MASK) #define DDRPHY_DX5BDLR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5BDLR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_7_6_MASK) #define DDRPHY_DX5BDLR4_DQ5RBD_MASK (0x3F00U) #define DDRPHY_DX5BDLR4_DQ5RBD_SHIFT (8U) /*! DQ5RBD - DQ5 Read Bit Delay */ #define DDRPHY_DX5BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ5RBD_MASK) #define DDRPHY_DX5BDLR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5BDLR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_15_14_MASK) #define DDRPHY_DX5BDLR4_DQ6RBD_MASK (0x3F0000U) #define DDRPHY_DX5BDLR4_DQ6RBD_SHIFT (16U) /*! DQ6RBD - DQ6 Read Bit Delay */ #define DDRPHY_DX5BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ6RBD_MASK) #define DDRPHY_DX5BDLR4_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX5BDLR4_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_23_22_MASK) #define DDRPHY_DX5BDLR4_DQ7RBD_MASK (0x3F000000U) #define DDRPHY_DX5BDLR4_DQ7RBD_SHIFT (24U) /*! DQ7RBD - DQ7 Read Bit Delay */ #define DDRPHY_DX5BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ7RBD_MASK) #define DDRPHY_DX5BDLR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX5BDLR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_31_30_MASK) /*! @} */ /*! @name DX5BDLR5 - DATX8 n Bit Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX5BDLR5_DMRBD_MASK (0x3FU) #define DDRPHY_DX5BDLR5_DMRBD_SHIFT (0U) /*! DMRBD - DM Read Bit Delay */ #define DDRPHY_DX5BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR5_DMRBD_SHIFT)) & DDRPHY_DX5BDLR5_DMRBD_MASK) #define DDRPHY_DX5BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U) #define DDRPHY_DX5BDLR5_RESERVED_31_6_SHIFT (6U) /*! RESERVED_31_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX5BDLR5_RESERVED_31_6_MASK) /*! @} */ /*! @name DX5BDLR6 - DATX8 n Bit Delay Line Register 6 */ /*! @{ */ #define DDRPHY_DX5BDLR6_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_DX5BDLR6_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX5BDLR6_RESERVED_7_0_MASK) #define DDRPHY_DX5BDLR6_PDRBD_MASK (0x3F00U) #define DDRPHY_DX5BDLR6_PDRBD_SHIFT (8U) /*! PDRBD - Power down receiver Bit Delay */ #define DDRPHY_DX5BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_PDRBD_SHIFT)) & DDRPHY_DX5BDLR6_PDRBD_MASK) #define DDRPHY_DX5BDLR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5BDLR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR6_RESERVED_15_14_MASK) #define DDRPHY_DX5BDLR6_TERBD_MASK (0x3F0000U) #define DDRPHY_DX5BDLR6_TERBD_SHIFT (16U) /*! TERBD - Termination Enable Bit Delay */ #define DDRPHY_DX5BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_TERBD_SHIFT)) & DDRPHY_DX5BDLR6_TERBD_MASK) #define DDRPHY_DX5BDLR6_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX5BDLR6_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR6_RESERVED_31_22_MASK) /*! @} */ /*! @name DX5BDLR7 - DATX8 n Bit Delay Line Register 7 */ /*! @{ */ #define DDRPHY_DX5BDLR7_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX5BDLR7_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_5_0_MASK) #define DDRPHY_DX5BDLR7_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5BDLR7_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_7_6_MASK) #define DDRPHY_DX5BDLR7_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX5BDLR7_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_13_8_MASK) #define DDRPHY_DX5BDLR7_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5BDLR7_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_15_14_MASK) #define DDRPHY_DX5BDLR7_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX5BDLR7_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_21_16_MASK) #define DDRPHY_DX5BDLR7_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX5BDLR7_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_31_22_MASK) /*! @} */ /*! @name DX5BDLR8 - DATX8 n Bit Delay Line Register 8 */ /*! @{ */ #define DDRPHY_DX5BDLR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX5BDLR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_5_0_MASK) #define DDRPHY_DX5BDLR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5BDLR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_7_6_MASK) #define DDRPHY_DX5BDLR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX5BDLR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_13_8_MASK) #define DDRPHY_DX5BDLR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5BDLR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_15_14_MASK) #define DDRPHY_DX5BDLR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX5BDLR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_21_16_MASK) #define DDRPHY_DX5BDLR8_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX5BDLR8_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_31_22_MASK) /*! @} */ /*! @name DX5BDLR9 - DATX8 n Bit Delay Line Register 9 */ /*! @{ */ #define DDRPHY_DX5BDLR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX5BDLR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_5_0_MASK) #define DDRPHY_DX5BDLR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX5BDLR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_7_6_MASK) #define DDRPHY_DX5BDLR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX5BDLR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_13_8_MASK) #define DDRPHY_DX5BDLR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX5BDLR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_15_14_MASK) #define DDRPHY_DX5BDLR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX5BDLR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_21_16_MASK) #define DDRPHY_DX5BDLR9_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX5BDLR9_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_31_22_MASK) /*! @} */ /*! @name DX5LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX5LCDLR0_WLD_MASK (0x1FFU) #define DDRPHY_DX5LCDLR0_WLD_SHIFT (0U) /*! WLD - Write Leveling Delay */ #define DDRPHY_DX5LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_WLD_SHIFT)) & DDRPHY_DX5LCDLR0_WLD_MASK) #define DDRPHY_DX5LCDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX5LCDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX5LCDLR0_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX5LCDLR0_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR0_RESERVED_24_16_MASK) #define DDRPHY_DX5LCDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX5LCDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX5LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX5LCDLR1_WDQD_MASK (0x1FFU) #define DDRPHY_DX5LCDLR1_WDQD_SHIFT (0U) /*! WDQD - Write Data Delay */ #define DDRPHY_DX5LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_WDQD_SHIFT)) & DDRPHY_DX5LCDLR1_WDQD_MASK) #define DDRPHY_DX5LCDLR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX5LCDLR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR1_RESERVED_15_9_MASK) #define DDRPHY_DX5LCDLR1_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX5LCDLR1_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR1_RESERVED_24_16_MASK) #define DDRPHY_DX5LCDLR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX5LCDLR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX5LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX5LCDLR2_DQSGD_MASK (0x1FFU) #define DDRPHY_DX5LCDLR2_DQSGD_SHIFT (0U) /*! DQSGD - Read DQS Gating Delay */ #define DDRPHY_DX5LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX5LCDLR2_DQSGD_MASK) #define DDRPHY_DX5LCDLR2_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX5LCDLR2_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR2_RESERVED_15_9_MASK) #define DDRPHY_DX5LCDLR2_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX5LCDLR2_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR2_RESERVED_24_16_MASK) #define DDRPHY_DX5LCDLR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX5LCDLR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR2_RESERVED_31_25_MASK) /*! @} */ /*! @name DX5LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX5LCDLR3_RDQSD_MASK (0x1FFU) #define DDRPHY_DX5LCDLR3_RDQSD_SHIFT (0U) /*! RDQSD - Read DQS Delay */ #define DDRPHY_DX5LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX5LCDLR3_RDQSD_MASK) #define DDRPHY_DX5LCDLR3_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX5LCDLR3_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR3_RESERVED_15_9_MASK) #define DDRPHY_DX5LCDLR3_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX5LCDLR3_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR3_RESERVED_24_16_MASK) #define DDRPHY_DX5LCDLR3_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX5LCDLR3_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR3_RESERVED_31_25_MASK) /*! @} */ /*! @name DX5LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX5LCDLR4_RDQSND_MASK (0x1FFU) #define DDRPHY_DX5LCDLR4_RDQSND_SHIFT (0U) /*! RDQSND - Read DQSN Delay */ #define DDRPHY_DX5LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX5LCDLR4_RDQSND_MASK) #define DDRPHY_DX5LCDLR4_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX5LCDLR4_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR4_RESERVED_15_9_MASK) #define DDRPHY_DX5LCDLR4_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX5LCDLR4_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR4_RESERVED_24_16_MASK) #define DDRPHY_DX5LCDLR4_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX5LCDLR4_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR4_RESERVED_31_25_MASK) /*! @} */ /*! @name DX5LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX5LCDLR5_DQSGSD_MASK (0x1FFU) #define DDRPHY_DX5LCDLR5_DQSGSD_SHIFT (0U) /*! DQSGSD - DQS Gating Status Delay */ #define DDRPHY_DX5LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX5LCDLR5_DQSGSD_MASK) #define DDRPHY_DX5LCDLR5_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX5LCDLR5_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR5_RESERVED_15_9_MASK) #define DDRPHY_DX5LCDLR5_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX5LCDLR5_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR5_RESERVED_24_16_MASK) #define DDRPHY_DX5LCDLR5_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX5LCDLR5_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR5_RESERVED_31_25_MASK) /*! @} */ /*! @name DX5MDLR0 - DATX8 n Master Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX5MDLR0_IPRD_MASK (0x1FFU) #define DDRPHY_DX5MDLR0_IPRD_SHIFT (0U) /*! IPRD - Initial Period */ #define DDRPHY_DX5MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_IPRD_SHIFT)) & DDRPHY_DX5MDLR0_IPRD_MASK) #define DDRPHY_DX5MDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX5MDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX5MDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX5MDLR0_TPRD_MASK (0x1FF0000U) #define DDRPHY_DX5MDLR0_TPRD_SHIFT (16U) /*! TPRD - Target Period */ #define DDRPHY_DX5MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_TPRD_SHIFT)) & DDRPHY_DX5MDLR0_TPRD_MASK) #define DDRPHY_DX5MDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX5MDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX5MDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX5MDLR1 - DATX8 n Master Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX5MDLR1_MDLD_MASK (0x1FFU) #define DDRPHY_DX5MDLR1_MDLD_SHIFT (0U) /*! MDLD - MDL Delay */ #define DDRPHY_DX5MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR1_MDLD_SHIFT)) & DDRPHY_DX5MDLR1_MDLD_MASK) #define DDRPHY_DX5MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U) #define DDRPHY_DX5MDLR1_RESERVED_31_9_SHIFT (9U) /*! RESERVED_31_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX5MDLR1_RESERVED_31_9_MASK) /*! @} */ /*! @name DX5GTR0 - DATX8 n General Timing Register 0 */ /*! @{ */ #define DDRPHY_DX5GTR0_DGSL_MASK (0x1FU) #define DDRPHY_DX5GTR0_DGSL_SHIFT (0U) /*! DGSL - DQS Gating System Latency */ #define DDRPHY_DX5GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_DGSL_SHIFT)) & DDRPHY_DX5GTR0_DGSL_MASK) #define DDRPHY_DX5GTR0_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DX5GTR0_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_7_5_MASK) #define DDRPHY_DX5GTR0_RESERVED_12_8_MASK (0x1F00U) #define DDRPHY_DX5GTR0_RESERVED_12_8_SHIFT (8U) /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_12_8_MASK) #define DDRPHY_DX5GTR0_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_DX5GTR0_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_15_13_MASK) #define DDRPHY_DX5GTR0_WLSL_MASK (0xF0000U) #define DDRPHY_DX5GTR0_WLSL_SHIFT (16U) /*! WLSL - Write Leveling System Latency */ #define DDRPHY_DX5GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_WLSL_SHIFT)) & DDRPHY_DX5GTR0_WLSL_MASK) #define DDRPHY_DX5GTR0_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX5GTR0_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX5GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_23_20_MASK) #define DDRPHY_DX5GTR0_WDQSL_MASK (0x7000000U) #define DDRPHY_DX5GTR0_WDQSL_SHIFT (24U) /*! WDQSL - DQ Write Path Latency Pipeline */ #define DDRPHY_DX5GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_WDQSL_SHIFT)) & DDRPHY_DX5GTR0_WDQSL_MASK) #define DDRPHY_DX5GTR0_RESERVED_31_24_MASK (0xF8000000U) #define DDRPHY_DX5GTR0_RESERVED_31_24_SHIFT (27U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_31_24_MASK) /*! @} */ /*! @name DX5RSR0 - DATX8 n Rank Status Register 0 */ /*! @{ */ #define DDRPHY_DX5RSR0_QSGERR_MASK (0xFFFFU) #define DDRPHY_DX5RSR0_QSGERR_SHIFT (0U) /*! QSGERR - DQS Gate Training Error */ #define DDRPHY_DX5RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR0_QSGERR_SHIFT)) & DDRPHY_DX5RSR0_QSGERR_MASK) #define DDRPHY_DX5RSR0_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX5RSR0_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR0_RESERVED_31_16_MASK) /*! @} */ /*! @name DX5RSR1 - DATX8 n Rank Status Register 1 */ /*! @{ */ #define DDRPHY_DX5RSR1_RDLVLERR_MASK (0xFFFFU) #define DDRPHY_DX5RSR1_RDLVLERR_SHIFT (0U) /*! RDLVLERR - Read Leveling Error */ #define DDRPHY_DX5RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX5RSR1_RDLVLERR_MASK) #define DDRPHY_DX5RSR1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX5RSR1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR1_RESERVED_31_16_MASK) /*! @} */ /*! @name DX5RSR2 - DATX8 n Rank Status Register 2 */ /*! @{ */ #define DDRPHY_DX5RSR2_WLAWN_MASK (0xFFFFU) #define DDRPHY_DX5RSR2_WLAWN_SHIFT (0U) /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning */ #define DDRPHY_DX5RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR2_WLAWN_SHIFT)) & DDRPHY_DX5RSR2_WLAWN_MASK) #define DDRPHY_DX5RSR2_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX5RSR2_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR2_RESERVED_31_16_MASK) /*! @} */ /*! @name DX5RSR3 - DATX8 n Rank Status Register 3 */ /*! @{ */ #define DDRPHY_DX5RSR3_WLAERR_MASK (0xFFFFU) #define DDRPHY_DX5RSR3_WLAERR_SHIFT (0U) /*! WLAERR - Write Leveling Adjustment Error */ #define DDRPHY_DX5RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR3_WLAERR_SHIFT)) & DDRPHY_DX5RSR3_WLAERR_MASK) #define DDRPHY_DX5RSR3_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX5RSR3_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR3_RESERVED_31_16_MASK) /*! @} */ /*! @name DX5GSR0 - DATX8 n General Status Register 0 */ /*! @{ */ #define DDRPHY_DX5GSR0_WDQCAL_MASK (0x1U) #define DDRPHY_DX5GSR0_WDQCAL_SHIFT (0U) /*! WDQCAL - Write DQ Calibration */ #define DDRPHY_DX5GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WDQCAL_SHIFT)) & DDRPHY_DX5GSR0_WDQCAL_MASK) #define DDRPHY_DX5GSR0_RDQSCAL_MASK (0x2U) #define DDRPHY_DX5GSR0_RDQSCAL_SHIFT (1U) /*! RDQSCAL - Read DQS Calibration */ #define DDRPHY_DX5GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX5GSR0_RDQSCAL_MASK) #define DDRPHY_DX5GSR0_RDQSNCAL_MASK (0x4U) #define DDRPHY_DX5GSR0_RDQSNCAL_SHIFT (2U) /*! RDQSNCAL - Read DQS# Calibration */ #define DDRPHY_DX5GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX5GSR0_RDQSNCAL_MASK) #define DDRPHY_DX5GSR0_GDQSCAL_MASK (0x8U) #define DDRPHY_DX5GSR0_GDQSCAL_SHIFT (3U) /*! GDQSCAL - Read DQS gating Calibration */ #define DDRPHY_DX5GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX5GSR0_GDQSCAL_MASK) #define DDRPHY_DX5GSR0_WLCAL_MASK (0x10U) #define DDRPHY_DX5GSR0_WLCAL_SHIFT (4U) /*! WLCAL - Write Leveling Calibration */ #define DDRPHY_DX5GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLCAL_SHIFT)) & DDRPHY_DX5GSR0_WLCAL_MASK) #define DDRPHY_DX5GSR0_WLDONE_MASK (0x20U) #define DDRPHY_DX5GSR0_WLDONE_SHIFT (5U) /*! WLDONE - Write Leveling Done */ #define DDRPHY_DX5GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLDONE_SHIFT)) & DDRPHY_DX5GSR0_WLDONE_MASK) #define DDRPHY_DX5GSR0_WLERR_MASK (0x40U) #define DDRPHY_DX5GSR0_WLERR_SHIFT (6U) /*! WLERR - Write Leveling Error */ #define DDRPHY_DX5GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLERR_SHIFT)) & DDRPHY_DX5GSR0_WLERR_MASK) #define DDRPHY_DX5GSR0_WLPRD_MASK (0xFF80U) #define DDRPHY_DX5GSR0_WLPRD_SHIFT (7U) /*! WLPRD - Write Leveling Period */ #define DDRPHY_DX5GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLPRD_SHIFT)) & DDRPHY_DX5GSR0_WLPRD_MASK) #define DDRPHY_DX5GSR0_DPLOCK_MASK (0x10000U) #define DDRPHY_DX5GSR0_DPLOCK_SHIFT (16U) /*! DPLOCK - DATX8 PLL Lock */ #define DDRPHY_DX5GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_DPLOCK_SHIFT)) & DDRPHY_DX5GSR0_DPLOCK_MASK) #define DDRPHY_DX5GSR0_GDQSPRD_MASK (0x3FE0000U) #define DDRPHY_DX5GSR0_GDQSPRD_SHIFT (17U) /*! GDQSPRD - Read DQS gating Period */ #define DDRPHY_DX5GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX5GSR0_GDQSPRD_MASK) #define DDRPHY_DX5GSR0_RESERVED_29_26_MASK (0x3C000000U) #define DDRPHY_DX5GSR0_RESERVED_29_26_SHIFT (26U) /*! RESERVED_29_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX5GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX5GSR0_RESERVED_29_26_MASK) #define DDRPHY_DX5GSR0_WLDQ_MASK (0x40000000U) #define DDRPHY_DX5GSR0_WLDQ_SHIFT (30U) /*! WLDQ - Write Leveling DQ Status */ #define DDRPHY_DX5GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLDQ_SHIFT)) & DDRPHY_DX5GSR0_WLDQ_MASK) #define DDRPHY_DX5GSR0_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX5GSR0_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX5GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX5GSR0_RESERVED_31_MASK) /*! @} */ /*! @name DX5GSR1 - DATX8 n General Status Register 1 */ /*! @{ */ #define DDRPHY_DX5GSR1_DLTDONE_MASK (0x1U) #define DDRPHY_DX5GSR1_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done */ #define DDRPHY_DX5GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR1_DLTDONE_SHIFT)) & DDRPHY_DX5GSR1_DLTDONE_MASK) #define DDRPHY_DX5GSR1_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_DX5GSR1_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code */ #define DDRPHY_DX5GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR1_DLTCODE_SHIFT)) & DDRPHY_DX5GSR1_DLTCODE_MASK) #define DDRPHY_DX5GSR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX5GSR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX5GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX5GSR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX5GSR2 - DATX8 n General Status Register 2 */ /*! @{ */ #define DDRPHY_DX5GSR2_RDERR_MASK (0x1U) #define DDRPHY_DX5GSR2_RDERR_SHIFT (0U) /*! RDERR - Read Bit Deskew Error */ #define DDRPHY_DX5GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_RDERR_SHIFT)) & DDRPHY_DX5GSR2_RDERR_MASK) #define DDRPHY_DX5GSR2_RDWN_MASK (0x2U) #define DDRPHY_DX5GSR2_RDWN_SHIFT (1U) /*! RDWN - Read Bit Deskew Warning */ #define DDRPHY_DX5GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_RDWN_SHIFT)) & DDRPHY_DX5GSR2_RDWN_MASK) #define DDRPHY_DX5GSR2_WDERR_MASK (0x4U) #define DDRPHY_DX5GSR2_WDERR_SHIFT (2U) /*! WDERR - Write Bit Deskew Error */ #define DDRPHY_DX5GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WDERR_SHIFT)) & DDRPHY_DX5GSR2_WDERR_MASK) #define DDRPHY_DX5GSR2_WDWN_MASK (0x8U) #define DDRPHY_DX5GSR2_WDWN_SHIFT (3U) /*! WDWN - Write Bit Deskew Warning */ #define DDRPHY_DX5GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WDWN_SHIFT)) & DDRPHY_DX5GSR2_WDWN_MASK) #define DDRPHY_DX5GSR2_REERR_MASK (0x10U) #define DDRPHY_DX5GSR2_REERR_SHIFT (4U) /*! REERR - Read Eye Centering Error */ #define DDRPHY_DX5GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_REERR_SHIFT)) & DDRPHY_DX5GSR2_REERR_MASK) #define DDRPHY_DX5GSR2_REWN_MASK (0x20U) #define DDRPHY_DX5GSR2_REWN_SHIFT (5U) /*! REWN - Read Eye Centering Warning */ #define DDRPHY_DX5GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_REWN_SHIFT)) & DDRPHY_DX5GSR2_REWN_MASK) #define DDRPHY_DX5GSR2_WEERR_MASK (0x40U) #define DDRPHY_DX5GSR2_WEERR_SHIFT (6U) /*! WEERR - Write Eye Centering Error */ #define DDRPHY_DX5GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WEERR_SHIFT)) & DDRPHY_DX5GSR2_WEERR_MASK) #define DDRPHY_DX5GSR2_WEWN_MASK (0x80U) #define DDRPHY_DX5GSR2_WEWN_SHIFT (7U) /*! WEWN - Write Eye Centering Warning */ #define DDRPHY_DX5GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WEWN_SHIFT)) & DDRPHY_DX5GSR2_WEWN_MASK) #define DDRPHY_DX5GSR2_ESTAT_MASK (0xF00U) #define DDRPHY_DX5GSR2_ESTAT_SHIFT (8U) /*! ESTAT - Error Status */ #define DDRPHY_DX5GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_ESTAT_SHIFT)) & DDRPHY_DX5GSR2_ESTAT_MASK) #define DDRPHY_DX5GSR2_DQS2DQERR_MASK (0xFF000U) #define DDRPHY_DX5GSR2_DQS2DQERR_SHIFT (12U) /*! DQS2DQERR - Write DQS2DQ Training Error */ #define DDRPHY_DX5GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX5GSR2_DQS2DQERR_MASK) #define DDRPHY_DX5GSR2_SRDERR_MASK (0x100000U) #define DDRPHY_DX5GSR2_SRDERR_SHIFT (20U) /*! SRDERR - Static Read Error */ #define DDRPHY_DX5GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_SRDERR_SHIFT)) & DDRPHY_DX5GSR2_SRDERR_MASK) #define DDRPHY_DX5GSR2_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX5GSR2_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX5GSR2_RESERVED_21_MASK) #define DDRPHY_DX5GSR2_GSDQSCAL_MASK (0x400000U) #define DDRPHY_DX5GSR2_GSDQSCAL_SHIFT (22U) /*! GSDQSCAL - Read DQS Gating Status Calibration */ #define DDRPHY_DX5GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX5GSR2_GSDQSCAL_MASK) #define DDRPHY_DX5GSR2_GSDQSPRD_MASK (0xFF800000U) #define DDRPHY_DX5GSR2_GSDQSPRD_SHIFT (23U) /*! GSDQSPRD - Read DQS gating Status Period */ #define DDRPHY_DX5GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX5GSR2_GSDQSPRD_MASK) /*! @} */ /*! @name DX5GSR3 - DATX8 n General Status Register 3 */ /*! @{ */ #define DDRPHY_DX5GSR3_SRDPC_MASK (0x3U) #define DDRPHY_DX5GSR3_SRDPC_SHIFT (0U) /*! SRDPC - Static Read Delay Pass Count */ #define DDRPHY_DX5GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_SRDPC_SHIFT)) & DDRPHY_DX5GSR3_SRDPC_MASK) #define DDRPHY_DX5GSR3_RESERVED_7_2_MASK (0xFCU) #define DDRPHY_DX5GSR3_RESERVED_7_2_SHIFT (2U) /*! RESERVED_7_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX5GSR3_RESERVED_7_2_MASK) #define DDRPHY_DX5GSR3_HVERR_MASK (0xF00U) #define DDRPHY_DX5GSR3_HVERR_SHIFT (8U) /*! HVERR - Host VREF Training Error */ #define DDRPHY_DX5GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_HVERR_SHIFT)) & DDRPHY_DX5GSR3_HVERR_MASK) #define DDRPHY_DX5GSR3_HVWRN_MASK (0xF000U) #define DDRPHY_DX5GSR3_HVWRN_SHIFT (12U) /*! HVWRN - Host VREF Training Warning */ #define DDRPHY_DX5GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_HVWRN_SHIFT)) & DDRPHY_DX5GSR3_HVWRN_MASK) #define DDRPHY_DX5GSR3_DVERR_MASK (0xF0000U) #define DDRPHY_DX5GSR3_DVERR_SHIFT (16U) /*! DVERR - DRAM VREF Training Error */ #define DDRPHY_DX5GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_DVERR_SHIFT)) & DDRPHY_DX5GSR3_DVERR_MASK) #define DDRPHY_DX5GSR3_DVWRN_MASK (0xF00000U) #define DDRPHY_DX5GSR3_DVWRN_SHIFT (20U) /*! DVWRN - DRAM VREF Training Warning */ #define DDRPHY_DX5GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_DVWRN_SHIFT)) & DDRPHY_DX5GSR3_DVWRN_MASK) #define DDRPHY_DX5GSR3_ESTAT_MASK (0x7000000U) #define DDRPHY_DX5GSR3_ESTAT_SHIFT (24U) /*! ESTAT - VREF Training Error Status Code */ #define DDRPHY_DX5GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_ESTAT_SHIFT)) & DDRPHY_DX5GSR3_ESTAT_MASK) #define DDRPHY_DX5GSR3_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX5GSR3_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX5GSR3_RESERVED_31_27_MASK) /*! @} */ /*! @name DX5GSR4 - DATX8 n General Status Register 4 */ /*! @{ */ #define DDRPHY_DX5GSR4_RESERVED_0_MASK (0x1U) #define DDRPHY_DX5GSR4_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_0_MASK) #define DDRPHY_DX5GSR4_RESERVED_1_MASK (0x2U) #define DDRPHY_DX5GSR4_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_1_MASK) #define DDRPHY_DX5GSR4_RESERVED_2_MASK (0x4U) #define DDRPHY_DX5GSR4_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_2_MASK) #define DDRPHY_DX5GSR4_RESERVED_3_MASK (0x8U) #define DDRPHY_DX5GSR4_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_3_MASK) #define DDRPHY_DX5GSR4_RESERVED_4_MASK (0x10U) #define DDRPHY_DX5GSR4_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_4_MASK) #define DDRPHY_DX5GSR4_RESERVED_5_MASK (0x20U) #define DDRPHY_DX5GSR4_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_5_MASK) #define DDRPHY_DX5GSR4_RESERVED_6_MASK (0x40U) #define DDRPHY_DX5GSR4_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_6_MASK) #define DDRPHY_DX5GSR4_RESERVED_15_7_MASK (0xFF80U) #define DDRPHY_DX5GSR4_RESERVED_15_7_SHIFT (7U) /*! RESERVED_15_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_15_7_MASK) #define DDRPHY_DX5GSR4_RESERVED_16_MASK (0x10000U) #define DDRPHY_DX5GSR4_RESERVED_16_SHIFT (16U) /*! RESERVED_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_16_MASK) #define DDRPHY_DX5GSR4_RESERVED_25_17_MASK (0x3FE0000U) #define DDRPHY_DX5GSR4_RESERVED_25_17_SHIFT (17U) /*! RESERVED_25_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_25_17_MASK) #define DDRPHY_DX5GSR4_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_DX5GSR4_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX5GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_31_26_MASK) /*! @} */ /*! @name DX5GSR5 - DATX8 n General Status Register 5 */ /*! @{ */ #define DDRPHY_DX5GSR5_RESERVED_0_MASK (0x1U) #define DDRPHY_DX5GSR5_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_0_MASK) #define DDRPHY_DX5GSR5_RESERVED_1_MASK (0x2U) #define DDRPHY_DX5GSR5_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_1_MASK) #define DDRPHY_DX5GSR5_RESERVED_2_MASK (0x4U) #define DDRPHY_DX5GSR5_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_2_MASK) #define DDRPHY_DX5GSR5_RESERVED_3_MASK (0x8U) #define DDRPHY_DX5GSR5_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_3_MASK) #define DDRPHY_DX5GSR5_RESERVED_4_MASK (0x10U) #define DDRPHY_DX5GSR5_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_4_MASK) #define DDRPHY_DX5GSR5_RESERVED_5_MASK (0x20U) #define DDRPHY_DX5GSR5_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_5_MASK) #define DDRPHY_DX5GSR5_RESERVED_6_MASK (0x40U) #define DDRPHY_DX5GSR5_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_6_MASK) #define DDRPHY_DX5GSR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX5GSR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_7_MASK) #define DDRPHY_DX5GSR5_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX5GSR5_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_11_8_MASK) #define DDRPHY_DX5GSR5_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_DX5GSR5_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_19_12_MASK) #define DDRPHY_DX5GSR5_RESERVED_20_MASK (0x100000U) #define DDRPHY_DX5GSR5_RESERVED_20_SHIFT (20U) /*! RESERVED_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_20_MASK) #define DDRPHY_DX5GSR5_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX5GSR5_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_21_MASK) #define DDRPHY_DX5GSR5_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX5GSR5_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_22_MASK) #define DDRPHY_DX5GSR5_RESERVED_31_23_MASK (0xFF800000U) #define DDRPHY_DX5GSR5_RESERVED_31_23_SHIFT (23U) /*! RESERVED_31_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_31_23_MASK) /*! @} */ /*! @name DX5GSR6 - DATX8 n General Status Register 6 */ /*! @{ */ #define DDRPHY_DX5GSR6_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX5GSR6_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_1_0_MASK) #define DDRPHY_DX5GSR6_RESERVED_3_2_MASK (0xCU) #define DDRPHY_DX5GSR6_RESERVED_3_2_SHIFT (2U) /*! RESERVED_3_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_3_2_MASK) #define DDRPHY_DX5GSR6_RESERVED_7_4_MASK (0xF0U) #define DDRPHY_DX5GSR6_RESERVED_7_4_SHIFT (4U) /*! RESERVED_7_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_7_4_MASK) #define DDRPHY_DX5GSR6_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX5GSR6_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_11_8_MASK) #define DDRPHY_DX5GSR6_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_DX5GSR6_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_15_12_MASK) #define DDRPHY_DX5GSR6_RESERVED_19_15_MASK (0xF0000U) #define DDRPHY_DX5GSR6_RESERVED_19_15_SHIFT (16U) /*! RESERVED_19_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_19_15_MASK) #define DDRPHY_DX5GSR6_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX5GSR6_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_23_20_MASK) #define DDRPHY_DX5GSR6_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX5GSR6_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX5GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_31_24_MASK) /*! @} */ /*! @name DX6GCR0 - DATX8 n General Configuration Register 0 */ /*! @{ */ #define DDRPHY_DX6GCR0_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX6GCR0_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX6GCR0_RESERVED_1_0_MASK) #define DDRPHY_DX6GCR0_DQSGOE_MASK (0x4U) #define DDRPHY_DX6GCR0_DQSGOE_SHIFT (2U) /*! DQSGOE - DQSG Output Enable */ #define DDRPHY_DX6GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSGOE_SHIFT)) & DDRPHY_DX6GCR0_DQSGOE_MASK) #define DDRPHY_DX6GCR0_DQSGODT_MASK (0x8U) #define DDRPHY_DX6GCR0_DQSGODT_SHIFT (3U) /*! DQSGODT - DQSG On-Die Termination */ #define DDRPHY_DX6GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSGODT_SHIFT)) & DDRPHY_DX6GCR0_DQSGODT_MASK) #define DDRPHY_DX6GCR0_RESERVED_4_MASK (0x10U) #define DDRPHY_DX6GCR0_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX6GCR0_RESERVED_4_MASK) #define DDRPHY_DX6GCR0_DQSGPDR_MASK (0x20U) #define DDRPHY_DX6GCR0_DQSGPDR_SHIFT (5U) /*! DQSGPDR - DQSG Power Down Receiver */ #define DDRPHY_DX6GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX6GCR0_DQSGPDR_MASK) #define DDRPHY_DX6GCR0_DQSRPD_MASK (0x40U) #define DDRPHY_DX6GCR0_DQSRPD_SHIFT (6U) /*! DQSRPD - DQSR Power Down */ #define DDRPHY_DX6GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSRPD_SHIFT)) & DDRPHY_DX6GCR0_DQSRPD_MASK) #define DDRPHY_DX6GCR0_CPDRSHFT_MASK (0x180U) #define DDRPHY_DX6GCR0_CPDRSHFT_SHIFT (7U) /*! CPDRSHFT - Configurable PDR Phase Shift */ #define DDRPHY_DX6GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX6GCR0_CPDRSHFT_MASK) #define DDRPHY_DX6GCR0_RTTOH_MASK (0x600U) #define DDRPHY_DX6GCR0_RTTOH_SHIFT (9U) /*! RTTOH - RTT Output Hold */ #define DDRPHY_DX6GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RTTOH_SHIFT)) & DDRPHY_DX6GCR0_RTTOH_MASK) #define DDRPHY_DX6GCR0_RTTOAL_MASK (0x800U) #define DDRPHY_DX6GCR0_RTTOAL_SHIFT (11U) /*! RTTOAL - RTT On Additive Latency */ #define DDRPHY_DX6GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RTTOAL_SHIFT)) & DDRPHY_DX6GCR0_RTTOAL_MASK) #define DDRPHY_DX6GCR0_DQSSEPDR_MASK (0x1000U) #define DDRPHY_DX6GCR0_DQSSEPDR_SHIFT (12U) /*! DQSSEPDR - DQSSE Power Down Receiver */ #define DDRPHY_DX6GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX6GCR0_DQSSEPDR_MASK) #define DDRPHY_DX6GCR0_DQSNSEPDR_MASK (0x2000U) #define DDRPHY_DX6GCR0_DQSNSEPDR_SHIFT (13U) /*! DQSNSEPDR - DQSNSE Power Down Receiver */ #define DDRPHY_DX6GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX6GCR0_DQSNSEPDR_MASK) #define DDRPHY_DX6GCR0_RESERVED_19_14_MASK (0xFC000U) #define DDRPHY_DX6GCR0_RESERVED_19_14_SHIFT (14U) /*! RESERVED_19_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX6GCR0_RESERVED_19_14_MASK) #define DDRPHY_DX6GCR0_RDDLY_MASK (0xF00000U) #define DDRPHY_DX6GCR0_RDDLY_SHIFT (20U) /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY */ #define DDRPHY_DX6GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RDDLY_SHIFT)) & DDRPHY_DX6GCR0_RDDLY_MASK) #define DDRPHY_DX6GCR0_DQSDCC_MASK (0xF000000U) #define DDRPHY_DX6GCR0_DQSDCC_SHIFT (24U) /*! DQSDCC - DQS Duty Cycle Correction */ #define DDRPHY_DX6GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSDCC_SHIFT)) & DDRPHY_DX6GCR0_DQSDCC_MASK) #define DDRPHY_DX6GCR0_CODTSHFT_MASK (0x30000000U) #define DDRPHY_DX6GCR0_CODTSHFT_SHIFT (28U) /*! CODTSHFT - Configurable ODT(TE) Phase Shift */ #define DDRPHY_DX6GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX6GCR0_CODTSHFT_MASK) #define DDRPHY_DX6GCR0_MDLEN_MASK (0x40000000U) #define DDRPHY_DX6GCR0_MDLEN_SHIFT (30U) /*! MDLEN - Master Delay Line Enable */ #define DDRPHY_DX6GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_MDLEN_SHIFT)) & DDRPHY_DX6GCR0_MDLEN_MASK) #define DDRPHY_DX6GCR0_CALBYP_MASK (0x80000000U) #define DDRPHY_DX6GCR0_CALBYP_SHIFT (31U) /*! CALBYP - Calibration Bypass */ #define DDRPHY_DX6GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_CALBYP_SHIFT)) & DDRPHY_DX6GCR0_CALBYP_MASK) /*! @} */ /*! @name DX6GCR1 - DATX8 n General Configuration Register 1 */ /*! @{ */ #define DDRPHY_DX6GCR1_DQEN_MASK (0xFFU) #define DDRPHY_DX6GCR1_DQEN_SHIFT (0U) /*! DQEN - Enables DQ corresponding to each bit in a byte */ #define DDRPHY_DX6GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DQEN_SHIFT)) & DDRPHY_DX6GCR1_DQEN_MASK) #define DDRPHY_DX6GCR1_DMEN_MASK (0x100U) #define DDRPHY_DX6GCR1_DMEN_SHIFT (8U) /*! DMEN - Enables DM pin in a byte lane */ #define DDRPHY_DX6GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DMEN_SHIFT)) & DDRPHY_DX6GCR1_DMEN_MASK) #define DDRPHY_DX6GCR1_DSEN_MASK (0x200U) #define DDRPHY_DX6GCR1_DSEN_SHIFT (9U) /*! DSEN - Enables Write Data strobe in a byte lane */ #define DDRPHY_DX6GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DSEN_SHIFT)) & DDRPHY_DX6GCR1_DSEN_MASK) #define DDRPHY_DX6GCR1_TEEN_MASK (0x400U) #define DDRPHY_DX6GCR1_TEEN_SHIFT (10U) /*! TEEN - Enables ODT/TE in a byte lane */ #define DDRPHY_DX6GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_TEEN_SHIFT)) & DDRPHY_DX6GCR1_TEEN_MASK) #define DDRPHY_DX6GCR1_PDREN_MASK (0x800U) #define DDRPHY_DX6GCR1_PDREN_SHIFT (11U) /*! PDREN - Enables PDR in a byte lane */ #define DDRPHY_DX6GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_PDREN_SHIFT)) & DDRPHY_DX6GCR1_PDREN_MASK) #define DDRPHY_DX6GCR1_OEEN_MASK (0x1000U) #define DDRPHY_DX6GCR1_OEEN_SHIFT (12U) /*! OEEN - Enables Read Data Strobe in a byte lane */ #define DDRPHY_DX6GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_OEEN_SHIFT)) & DDRPHY_DX6GCR1_OEEN_MASK) #define DDRPHY_DX6GCR1_QSSEL_MASK (0x2000U) #define DDRPHY_DX6GCR1_QSSEL_SHIFT (13U) /*! QSSEL - Select the delayed or non-delayed read data strobe */ #define DDRPHY_DX6GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_QSSEL_SHIFT)) & DDRPHY_DX6GCR1_QSSEL_MASK) #define DDRPHY_DX6GCR1_QSNSEL_MASK (0x4000U) #define DDRPHY_DX6GCR1_QSNSEL_SHIFT (14U) /*! QSNSEL - Select the delayed or non-delayed read data strobe # */ #define DDRPHY_DX6GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_QSNSEL_SHIFT)) & DDRPHY_DX6GCR1_QSNSEL_MASK) #define DDRPHY_DX6GCR1_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX6GCR1_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX6GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX6GCR1_RESERVED_15_MASK) #define DDRPHY_DX6GCR1_DXPDRMODE_MASK (0xFFFF0000U) #define DDRPHY_DX6GCR1_DXPDRMODE_SHIFT (16U) /*! DXPDRMODE - Enables the PDR mode for DQ[7:0] */ #define DDRPHY_DX6GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX6GCR1_DXPDRMODE_MASK) /*! @} */ /*! @name DX6GCR2 - DATX8 n General Configuration Register 2 */ /*! @{ */ #define DDRPHY_DX6GCR2_DXTEMODE_MASK (0xFFFFU) #define DDRPHY_DX6GCR2_DXTEMODE_SHIFT (0U) /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0] */ #define DDRPHY_DX6GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX6GCR2_DXTEMODE_MASK) #define DDRPHY_DX6GCR2_DXOEMODE_MASK (0xFFFF0000U) #define DDRPHY_DX6GCR2_DXOEMODE_SHIFT (16U) /*! DXOEMODE - Enables the OE mode values for DQ[7:0] */ #define DDRPHY_DX6GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX6GCR2_DXOEMODE_MASK) /*! @} */ /*! @name DX6GCR3 - DATX8 n General Configuration Register 3 */ /*! @{ */ #define DDRPHY_DX6GCR3_WDMBVT_MASK (0x1U) #define DDRPHY_DX6GCR3_WDMBVT_SHIFT (0U) /*! WDMBVT - Write Data Mask BDL VT Compensation */ #define DDRPHY_DX6GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDMBVT_SHIFT)) & DDRPHY_DX6GCR3_WDMBVT_MASK) #define DDRPHY_DX6GCR3_RDMBVT_MASK (0x2U) #define DDRPHY_DX6GCR3_RDMBVT_SHIFT (1U) /*! RDMBVT - Read Data Mask BDL VT Compensation */ #define DDRPHY_DX6GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RDMBVT_SHIFT)) & DDRPHY_DX6GCR3_RDMBVT_MASK) #define DDRPHY_DX6GCR3_DSPDRMODE_MASK (0xCU) #define DDRPHY_DX6GCR3_DSPDRMODE_SHIFT (2U) /*! DSPDRMODE - Enables the PDR mode values for DQS. */ #define DDRPHY_DX6GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX6GCR3_DSPDRMODE_MASK) #define DDRPHY_DX6GCR3_DSTEMODE_MASK (0x30U) #define DDRPHY_DX6GCR3_DSTEMODE_SHIFT (4U) /*! DSTEMODE - Enables the TE mode values for DQS. */ #define DDRPHY_DX6GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSTEMODE_MASK) #define DDRPHY_DX6GCR3_DSOEMODE_MASK (0xC0U) #define DDRPHY_DX6GCR3_DSOEMODE_SHIFT (6U) /*! DSOEMODE - Enables the OE mode values for DQS. */ #define DDRPHY_DX6GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSOEMODE_MASK) #define DDRPHY_DX6GCR3_WDSBVT_MASK (0x100U) #define DDRPHY_DX6GCR3_WDSBVT_SHIFT (8U) /*! WDSBVT - Write Data Strobe BDL VT Compensation */ #define DDRPHY_DX6GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDSBVT_SHIFT)) & DDRPHY_DX6GCR3_WDSBVT_MASK) #define DDRPHY_DX6GCR3_RESERVED_9_MASK (0x200U) #define DDRPHY_DX6GCR3_RESERVED_9_SHIFT (9U) /*! RESERVED_9 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX6GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX6GCR3_RESERVED_9_MASK) #define DDRPHY_DX6GCR3_DMPDRMODE_MASK (0xC00U) #define DDRPHY_DX6GCR3_DMPDRMODE_SHIFT (10U) /*! DMPDRMODE - Enables the PDR mode values for DM. */ #define DDRPHY_DX6GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX6GCR3_DMPDRMODE_MASK) #define DDRPHY_DX6GCR3_DMTEMODE_MASK (0x3000U) #define DDRPHY_DX6GCR3_DMTEMODE_SHIFT (12U) /*! DMTEMODE - Enables the TE mode values for DM. */ #define DDRPHY_DX6GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX6GCR3_DMTEMODE_MASK) #define DDRPHY_DX6GCR3_DMOEMODE_MASK (0xC000U) #define DDRPHY_DX6GCR3_DMOEMODE_SHIFT (14U) /*! DMOEMODE - Enables the OE mode values for DM. */ #define DDRPHY_DX6GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX6GCR3_DMOEMODE_MASK) #define DDRPHY_DX6GCR3_DSNPDRMODE_MASK (0x30000U) #define DDRPHY_DX6GCR3_DSNPDRMODE_SHIFT (16U) /*! DSNPDRMODE - Enables the PDR mode for DQS */ #define DDRPHY_DX6GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX6GCR3_DSNPDRMODE_MASK) #define DDRPHY_DX6GCR3_DSNTEMODE_MASK (0xC0000U) #define DDRPHY_DX6GCR3_DSNTEMODE_SHIFT (18U) /*! DSNTEMODE - Enables the TE mode for DQS */ #define DDRPHY_DX6GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSNTEMODE_MASK) #define DDRPHY_DX6GCR3_DSNOEMODE_MASK (0x300000U) #define DDRPHY_DX6GCR3_DSNOEMODE_SHIFT (20U) /*! DSNOEMODE - Enables the OE mode for DQs */ #define DDRPHY_DX6GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSNOEMODE_MASK) #define DDRPHY_DX6GCR3_PDRBVT_MASK (0x400000U) #define DDRPHY_DX6GCR3_PDRBVT_SHIFT (22U) /*! PDRBVT - Power Down Receiver BDL VT Compensation */ #define DDRPHY_DX6GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_PDRBVT_SHIFT)) & DDRPHY_DX6GCR3_PDRBVT_MASK) #define DDRPHY_DX6GCR3_RGSLVT_MASK (0x800000U) #define DDRPHY_DX6GCR3_RGSLVT_SHIFT (23U) /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation */ #define DDRPHY_DX6GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RGSLVT_SHIFT)) & DDRPHY_DX6GCR3_RGSLVT_MASK) #define DDRPHY_DX6GCR3_WLLVT_MASK (0x1000000U) #define DDRPHY_DX6GCR3_WLLVT_SHIFT (24U) /*! WLLVT - Write Leveling LCDL Delay VT Compensation */ #define DDRPHY_DX6GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WLLVT_SHIFT)) & DDRPHY_DX6GCR3_WLLVT_MASK) #define DDRPHY_DX6GCR3_WDLVT_MASK (0x2000000U) #define DDRPHY_DX6GCR3_WDLVT_SHIFT (25U) /*! WDLVT - Write DQ LCDL Delay VT Compensation */ #define DDRPHY_DX6GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDLVT_SHIFT)) & DDRPHY_DX6GCR3_WDLVT_MASK) #define DDRPHY_DX6GCR3_RDLVT_MASK (0x4000000U) #define DDRPHY_DX6GCR3_RDLVT_SHIFT (26U) /*! RDLVT - Read DQS LCDL Delay VT Compensation */ #define DDRPHY_DX6GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RDLVT_SHIFT)) & DDRPHY_DX6GCR3_RDLVT_MASK) #define DDRPHY_DX6GCR3_RGLVT_MASK (0x8000000U) #define DDRPHY_DX6GCR3_RGLVT_SHIFT (27U) /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation */ #define DDRPHY_DX6GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RGLVT_SHIFT)) & DDRPHY_DX6GCR3_RGLVT_MASK) #define DDRPHY_DX6GCR3_WDBVT_MASK (0x10000000U) #define DDRPHY_DX6GCR3_WDBVT_SHIFT (28U) /*! WDBVT - Write Data BDL VT Compensation */ #define DDRPHY_DX6GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDBVT_SHIFT)) & DDRPHY_DX6GCR3_WDBVT_MASK) #define DDRPHY_DX6GCR3_RDBVT_MASK (0x20000000U) #define DDRPHY_DX6GCR3_RDBVT_SHIFT (29U) /*! RDBVT - Read Data BDL VT Compensation */ #define DDRPHY_DX6GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RDBVT_SHIFT)) & DDRPHY_DX6GCR3_RDBVT_MASK) #define DDRPHY_DX6GCR3_TEBVT_MASK (0x40000000U) #define DDRPHY_DX6GCR3_TEBVT_SHIFT (30U) /*! TEBVT - Termination Enable BDL VT Compensation */ #define DDRPHY_DX6GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_TEBVT_SHIFT)) & DDRPHY_DX6GCR3_TEBVT_MASK) #define DDRPHY_DX6GCR3_OEBVT_MASK (0x80000000U) #define DDRPHY_DX6GCR3_OEBVT_SHIFT (31U) /*! OEBVT - Output Enable BDL VT Compensation */ #define DDRPHY_DX6GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_OEBVT_SHIFT)) & DDRPHY_DX6GCR3_OEBVT_MASK) /*! @} */ /*! @name DX6GCR4 - DATX8 n General Configuration Register 4 */ /*! @{ */ #define DDRPHY_DX6GCR4_DXREFIMON_MASK (0x3U) #define DDRPHY_DX6GCR4_DXREFIMON_SHIFT (0U) /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX6GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX6GCR4_DXREFIMON_MASK) #define DDRPHY_DX6GCR4_DXREFIEN_MASK (0x3CU) #define DDRPHY_DX6GCR4_DXREFIEN_SHIFT (2U) /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX6GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFIEN_MASK) #define DDRPHY_DX6GCR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6GCR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX6GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR4_RESERVED_7_6_MASK) #define DDRPHY_DX6GCR4_DXREFSSEL_MASK (0x7F00U) #define DDRPHY_DX6GCR4_DXREFSSEL_SHIFT (8U) /*! DXREFSSEL - Byte Lane Single-End VREF Select */ #define DDRPHY_DX6GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX6GCR4_DXREFSSEL_MASK) #define DDRPHY_DX6GCR4_DXREFSSELRANGE_MASK (0x8000U) #define DDRPHY_DX6GCR4_DXREFSSELRANGE_SHIFT (15U) /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select */ #define DDRPHY_DX6GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX6GCR4_DXREFSSELRANGE_MASK) #define DDRPHY_DX6GCR4_DXREFESEL_MASK (0x7F0000U) #define DDRPHY_DX6GCR4_DXREFESEL_SHIFT (16U) /*! DXREFESEL - Byte Lane External VREF Select */ #define DDRPHY_DX6GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX6GCR4_DXREFESEL_MASK) #define DDRPHY_DX6GCR4_DXREFESELRANGE_MASK (0x800000U) #define DDRPHY_DX6GCR4_DXREFESELRANGE_SHIFT (23U) /*! DXREFESELRANGE - External VREF generator REFSEL range select */ #define DDRPHY_DX6GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX6GCR4_DXREFESELRANGE_MASK) #define DDRPHY_DX6GCR4_RESERVED_24_MASK (0x1000000U) #define DDRPHY_DX6GCR4_RESERVED_24_SHIFT (24U) /*! RESERVED_24 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX6GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX6GCR4_RESERVED_24_MASK) #define DDRPHY_DX6GCR4_DXREFSEN_MASK (0x2000000U) #define DDRPHY_DX6GCR4_DXREFSEN_SHIFT (25U) /*! DXREFSEN - Byte Lane Single-End VREF Enable */ #define DDRPHY_DX6GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFSEN_MASK) #define DDRPHY_DX6GCR4_DXREFEEN_MASK (0xC000000U) #define DDRPHY_DX6GCR4_DXREFEEN_SHIFT (26U) /*! DXREFEEN - Byte Lane Internal VREF Enable */ #define DDRPHY_DX6GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFEEN_MASK) #define DDRPHY_DX6GCR4_DXREFPEN_MASK (0x10000000U) #define DDRPHY_DX6GCR4_DXREFPEN_SHIFT (28U) /*! DXREFPEN - Byte Lane VREF Pad Enable */ #define DDRPHY_DX6GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFPEN_MASK) #define DDRPHY_DX6GCR4_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DX6GCR4_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs) */ #define DDRPHY_DX6GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX6GCR4_RESERVED_31_29_MASK) /*! @} */ /*! @name DX6GCR5 - DATX8 n General Configuration Register 5 */ /*! @{ */ #define DDRPHY_DX6GCR5_DXREFISELR0_MASK (0x7FU) #define DDRPHY_DX6GCR5_DXREFISELR0_SHIFT (0U) /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0 */ #define DDRPHY_DX6GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR0_MASK) #define DDRPHY_DX6GCR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX6GCR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX6GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_7_MASK) #define DDRPHY_DX6GCR5_DXREFISELR1_MASK (0x7F00U) #define DDRPHY_DX6GCR5_DXREFISELR1_SHIFT (8U) /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1 */ #define DDRPHY_DX6GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR1_MASK) #define DDRPHY_DX6GCR5_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX6GCR5_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX6GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_15_MASK) #define DDRPHY_DX6GCR5_DXREFISELR2_MASK (0x7F0000U) #define DDRPHY_DX6GCR5_DXREFISELR2_SHIFT (16U) /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2 */ #define DDRPHY_DX6GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR2_MASK) #define DDRPHY_DX6GCR5_RESERVED_23_MASK (0x800000U) #define DDRPHY_DX6GCR5_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX6GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_23_MASK) #define DDRPHY_DX6GCR5_DXREFISELR3_MASK (0x7F000000U) #define DDRPHY_DX6GCR5_DXREFISELR3_SHIFT (24U) /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3 */ #define DDRPHY_DX6GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR3_MASK) #define DDRPHY_DX6GCR5_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX6GCR5_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX6GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_31_MASK) /*! @} */ /*! @name DX6GCR6 - DATX8 n General Configuration Register 6 */ /*! @{ */ #define DDRPHY_DX6GCR6_DXDQVREFR0_MASK (0x3FU) #define DDRPHY_DX6GCR6_DXDQVREFR0_SHIFT (0U) /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0 */ #define DDRPHY_DX6GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR0_MASK) #define DDRPHY_DX6GCR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6GCR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX6GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_7_6_MASK) #define DDRPHY_DX6GCR6_DXDQVREFR1_MASK (0x3F00U) #define DDRPHY_DX6GCR6_DXDQVREFR1_SHIFT (8U) /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1 */ #define DDRPHY_DX6GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR1_MASK) #define DDRPHY_DX6GCR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6GCR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX6GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_15_14_MASK) #define DDRPHY_DX6GCR6_DXDQVREFR2_MASK (0x3F0000U) #define DDRPHY_DX6GCR6_DXDQVREFR2_SHIFT (16U) /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2 */ #define DDRPHY_DX6GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR2_MASK) #define DDRPHY_DX6GCR6_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX6GCR6_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX6GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_23_22_MASK) #define DDRPHY_DX6GCR6_DXDQVREFR3_MASK (0x3F000000U) #define DDRPHY_DX6GCR6_DXDQVREFR3_SHIFT (24U) /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3 */ #define DDRPHY_DX6GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR3_MASK) #define DDRPHY_DX6GCR6_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX6GCR6_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX6GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_31_30_MASK) /*! @} */ /*! @name DX6GCR7 - DATX8 n General Configuration Register 7 */ /*! @{ */ #define DDRPHY_DX6GCR7_DCALSVAL_MASK (0x1FFU) #define DDRPHY_DX6GCR7_DCALSVAL_SHIFT (0U) /*! DCALSVAL - DDL Calibration Starting Value */ #define DDRPHY_DX6GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX6GCR7_DCALSVAL_MASK) #define DDRPHY_DX6GCR7_DCALTYPE_MASK (0x200U) #define DDRPHY_DX6GCR7_DCALTYPE_SHIFT (9U) /*! DCALTYPE - DDL Calibration Type */ #define DDRPHY_DX6GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX6GCR7_DCALTYPE_MASK) #define DDRPHY_DX6GCR7_RESERVED_17_10_MASK (0x3FC00U) #define DDRPHY_DX6GCR7_RESERVED_17_10_SHIFT (10U) /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX6GCR7_RESERVED_17_10_MASK) #define DDRPHY_DX6GCR7_RESERVED_18_MASK (0x40000U) #define DDRPHY_DX6GCR7_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX6GCR7_RESERVED_18_MASK) #define DDRPHY_DX6GCR7_RESERVED_31_19_MASK (0xFFF80000U) #define DDRPHY_DX6GCR7_RESERVED_31_19_SHIFT (19U) /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX6GCR7_RESERVED_31_19_MASK) /*! @} */ /*! @name DX6GCR8 - DATX8 n General Configuration Register 8 */ /*! @{ */ #define DDRPHY_DX6GCR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX6GCR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_5_0_MASK) #define DDRPHY_DX6GCR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6GCR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_7_6_MASK) #define DDRPHY_DX6GCR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX6GCR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_13_8_MASK) #define DDRPHY_DX6GCR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6GCR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_15_14_MASK) #define DDRPHY_DX6GCR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX6GCR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_21_16_MASK) #define DDRPHY_DX6GCR8_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX6GCR8_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_23_22_MASK) #define DDRPHY_DX6GCR8_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX6GCR8_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_29_24_MASK) #define DDRPHY_DX6GCR8_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX6GCR8_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_31_30_MASK) /*! @} */ /*! @name DX6GCR9 - DATX8 n General Configuration Register 9 */ /*! @{ */ #define DDRPHY_DX6GCR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX6GCR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_5_0_MASK) #define DDRPHY_DX6GCR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6GCR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_7_6_MASK) #define DDRPHY_DX6GCR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX6GCR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_13_8_MASK) #define DDRPHY_DX6GCR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6GCR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_15_14_MASK) #define DDRPHY_DX6GCR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX6GCR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_21_16_MASK) #define DDRPHY_DX6GCR9_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX6GCR9_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_23_22_MASK) #define DDRPHY_DX6GCR9_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX6GCR9_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_29_24_MASK) #define DDRPHY_DX6GCR9_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX6GCR9_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_31_30_MASK) /*! @} */ /*! @name DX6DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */ /*! @{ */ #define DDRPHY_DX6DQMAP0_DQ0MAP_MASK (0xFU) #define DDRPHY_DX6DQMAP0_DQ0MAP_SHIFT (0U) /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index */ #define DDRPHY_DX6DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ0MAP_MASK) #define DDRPHY_DX6DQMAP0_DQ1MAP_MASK (0xF0U) #define DDRPHY_DX6DQMAP0_DQ1MAP_SHIFT (4U) /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index */ #define DDRPHY_DX6DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ1MAP_MASK) #define DDRPHY_DX6DQMAP0_DQ2MAP_MASK (0xF00U) #define DDRPHY_DX6DQMAP0_DQ2MAP_SHIFT (8U) /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index */ #define DDRPHY_DX6DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ2MAP_MASK) #define DDRPHY_DX6DQMAP0_DQ3MAP_MASK (0xF000U) #define DDRPHY_DX6DQMAP0_DQ3MAP_SHIFT (12U) /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index */ #define DDRPHY_DX6DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ3MAP_MASK) #define DDRPHY_DX6DQMAP0_DQ4MAP_MASK (0xF0000U) #define DDRPHY_DX6DQMAP0_DQ4MAP_SHIFT (16U) /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index */ #define DDRPHY_DX6DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ4MAP_MASK) #define DDRPHY_DX6DQMAP0_RESERVED_30_20_MASK (0x7FF00000U) #define DDRPHY_DX6DQMAP0_RESERVED_30_20_SHIFT (20U) /*! RESERVED_30_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX6DQMAP0_RESERVED_30_20_MASK) #define DDRPHY_DX6DQMAP0_MAPOK_MASK (0x80000000U) #define DDRPHY_DX6DQMAP0_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX6DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX6DQMAP0_MAPOK_MASK) /*! @} */ /*! @name DX6DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */ /*! @{ */ #define DDRPHY_DX6DQMAP1_DQ5MAP_MASK (0xFU) #define DDRPHY_DX6DQMAP1_DQ5MAP_SHIFT (0U) /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index */ #define DDRPHY_DX6DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX6DQMAP1_DQ5MAP_MASK) #define DDRPHY_DX6DQMAP1_DQ6MAP_MASK (0xF0U) #define DDRPHY_DX6DQMAP1_DQ6MAP_SHIFT (4U) /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index */ #define DDRPHY_DX6DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX6DQMAP1_DQ6MAP_MASK) #define DDRPHY_DX6DQMAP1_DQ7MAP_MASK (0xF00U) #define DDRPHY_DX6DQMAP1_DQ7MAP_SHIFT (8U) /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index */ #define DDRPHY_DX6DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX6DQMAP1_DQ7MAP_MASK) #define DDRPHY_DX6DQMAP1_DMMAP_MASK (0xF000U) #define DDRPHY_DX6DQMAP1_DMMAP_SHIFT (12U) /*! DMMAP - DM bit DATX8 slice mapping index */ #define DDRPHY_DX6DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX6DQMAP1_DMMAP_MASK) #define DDRPHY_DX6DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U) #define DDRPHY_DX6DQMAP1_RESERVED_30_16_SHIFT (16U) /*! RESERVED_30_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX6DQMAP1_RESERVED_30_16_MASK) #define DDRPHY_DX6DQMAP1_MAPOK_MASK (0x80000000U) #define DDRPHY_DX6DQMAP1_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX6DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX6DQMAP1_MAPOK_MASK) /*! @} */ /*! @name DX6BDLR0 - DATX8 n Bit Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX6BDLR0_DQ0WBD_MASK (0x3FU) #define DDRPHY_DX6BDLR0_DQ0WBD_SHIFT (0U) /*! DQ0WBD - DQ0 Write Bit Delay */ #define DDRPHY_DX6BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ0WBD_MASK) #define DDRPHY_DX6BDLR0_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6BDLR0_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_7_6_MASK) #define DDRPHY_DX6BDLR0_DQ1WBD_MASK (0x3F00U) #define DDRPHY_DX6BDLR0_DQ1WBD_SHIFT (8U) /*! DQ1WBD - DQ1 Write Bit Delay */ #define DDRPHY_DX6BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ1WBD_MASK) #define DDRPHY_DX6BDLR0_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6BDLR0_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_15_14_MASK) #define DDRPHY_DX6BDLR0_DQ2WBD_MASK (0x3F0000U) #define DDRPHY_DX6BDLR0_DQ2WBD_SHIFT (16U) /*! DQ2WBD - DQ2 Write Bit Delay */ #define DDRPHY_DX6BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ2WBD_MASK) #define DDRPHY_DX6BDLR0_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX6BDLR0_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_23_22_MASK) #define DDRPHY_DX6BDLR0_DQ3WBD_MASK (0x3F000000U) #define DDRPHY_DX6BDLR0_DQ3WBD_SHIFT (24U) /*! DQ3WBD - DQ3 Write Bit Delay */ #define DDRPHY_DX6BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ3WBD_MASK) #define DDRPHY_DX6BDLR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX6BDLR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_31_30_MASK) /*! @} */ /*! @name DX6BDLR1 - DATX8 n Bit Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX6BDLR1_DQ4WBD_MASK (0x3FU) #define DDRPHY_DX6BDLR1_DQ4WBD_SHIFT (0U) /*! DQ4WBD - DQ4 Write Bit Delay */ #define DDRPHY_DX6BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ4WBD_MASK) #define DDRPHY_DX6BDLR1_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6BDLR1_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_7_6_MASK) #define DDRPHY_DX6BDLR1_DQ5WBD_MASK (0x3F00U) #define DDRPHY_DX6BDLR1_DQ5WBD_SHIFT (8U) /*! DQ5WBD - DQ5 Write Bit Delay */ #define DDRPHY_DX6BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ5WBD_MASK) #define DDRPHY_DX6BDLR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6BDLR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_15_14_MASK) #define DDRPHY_DX6BDLR1_DQ6WBD_MASK (0x3F0000U) #define DDRPHY_DX6BDLR1_DQ6WBD_SHIFT (16U) /*! DQ6WBD - DQ6 Write Bit Delay */ #define DDRPHY_DX6BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ6WBD_MASK) #define DDRPHY_DX6BDLR1_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX6BDLR1_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_23_22_MASK) #define DDRPHY_DX6BDLR1_DQ7WBD_MASK (0x3F000000U) #define DDRPHY_DX6BDLR1_DQ7WBD_SHIFT (24U) /*! DQ7WBD - DQ7 Write Bit Delay */ #define DDRPHY_DX6BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ7WBD_MASK) #define DDRPHY_DX6BDLR1_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX6BDLR1_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_31_30_MASK) /*! @} */ /*! @name DX6BDLR2 - DATX8 n Bit Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX6BDLR2_DMWBD_MASK (0x3FU) #define DDRPHY_DX6BDLR2_DMWBD_SHIFT (0U) /*! DMWBD - DM Write Bit Delay */ #define DDRPHY_DX6BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DMWBD_SHIFT)) & DDRPHY_DX6BDLR2_DMWBD_MASK) #define DDRPHY_DX6BDLR2_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6BDLR2_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_7_6_MASK) #define DDRPHY_DX6BDLR2_DSWBD_MASK (0x3F00U) #define DDRPHY_DX6BDLR2_DSWBD_SHIFT (8U) /*! DSWBD - DQS Write Bit Delay */ #define DDRPHY_DX6BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DSWBD_SHIFT)) & DDRPHY_DX6BDLR2_DSWBD_MASK) #define DDRPHY_DX6BDLR2_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6BDLR2_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_15_14_MASK) #define DDRPHY_DX6BDLR2_DSOEBD_MASK (0x3F0000U) #define DDRPHY_DX6BDLR2_DSOEBD_SHIFT (16U) /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay */ #define DDRPHY_DX6BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX6BDLR2_DSOEBD_MASK) #define DDRPHY_DX6BDLR2_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX6BDLR2_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_23_22_MASK) #define DDRPHY_DX6BDLR2_DSNWBD_MASK (0x3F000000U) #define DDRPHY_DX6BDLR2_DSNWBD_SHIFT (24U) /*! DSNWBD - DQSN Write Bit Delay */ #define DDRPHY_DX6BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX6BDLR2_DSNWBD_MASK) #define DDRPHY_DX6BDLR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX6BDLR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_31_30_MASK) /*! @} */ /*! @name DX6BDLR3 - DATX8 n Bit Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX6BDLR3_DQ0RBD_MASK (0x3FU) #define DDRPHY_DX6BDLR3_DQ0RBD_SHIFT (0U) /*! DQ0RBD - DQ0 Read Bit Delay */ #define DDRPHY_DX6BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ0RBD_MASK) #define DDRPHY_DX6BDLR3_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6BDLR3_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_7_6_MASK) #define DDRPHY_DX6BDLR3_DQ1RBD_MASK (0x3F00U) #define DDRPHY_DX6BDLR3_DQ1RBD_SHIFT (8U) /*! DQ1RBD - DQ1 Read Bit Delay */ #define DDRPHY_DX6BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ1RBD_MASK) #define DDRPHY_DX6BDLR3_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6BDLR3_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_15_14_MASK) #define DDRPHY_DX6BDLR3_DQ2RBD_MASK (0x3F0000U) #define DDRPHY_DX6BDLR3_DQ2RBD_SHIFT (16U) /*! DQ2RBD - DQ2 Read Bit Delay */ #define DDRPHY_DX6BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ2RBD_MASK) #define DDRPHY_DX6BDLR3_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX6BDLR3_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_23_22_MASK) #define DDRPHY_DX6BDLR3_DQ3RBD_MASK (0x3F000000U) #define DDRPHY_DX6BDLR3_DQ3RBD_SHIFT (24U) /*! DQ3RBD - DQ3 Read Bit Delay */ #define DDRPHY_DX6BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ3RBD_MASK) #define DDRPHY_DX6BDLR3_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX6BDLR3_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_31_30_MASK) /*! @} */ /*! @name DX6BDLR4 - DATX8 n Bit Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX6BDLR4_DQ4RBD_MASK (0x3FU) #define DDRPHY_DX6BDLR4_DQ4RBD_SHIFT (0U) /*! DQ4RBD - DQ4 Read Bit Delay */ #define DDRPHY_DX6BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ4RBD_MASK) #define DDRPHY_DX6BDLR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6BDLR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_7_6_MASK) #define DDRPHY_DX6BDLR4_DQ5RBD_MASK (0x3F00U) #define DDRPHY_DX6BDLR4_DQ5RBD_SHIFT (8U) /*! DQ5RBD - DQ5 Read Bit Delay */ #define DDRPHY_DX6BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ5RBD_MASK) #define DDRPHY_DX6BDLR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6BDLR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_15_14_MASK) #define DDRPHY_DX6BDLR4_DQ6RBD_MASK (0x3F0000U) #define DDRPHY_DX6BDLR4_DQ6RBD_SHIFT (16U) /*! DQ6RBD - DQ6 Read Bit Delay */ #define DDRPHY_DX6BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ6RBD_MASK) #define DDRPHY_DX6BDLR4_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX6BDLR4_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_23_22_MASK) #define DDRPHY_DX6BDLR4_DQ7RBD_MASK (0x3F000000U) #define DDRPHY_DX6BDLR4_DQ7RBD_SHIFT (24U) /*! DQ7RBD - DQ7 Read Bit Delay */ #define DDRPHY_DX6BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ7RBD_MASK) #define DDRPHY_DX6BDLR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX6BDLR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_31_30_MASK) /*! @} */ /*! @name DX6BDLR5 - DATX8 n Bit Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX6BDLR5_DMRBD_MASK (0x3FU) #define DDRPHY_DX6BDLR5_DMRBD_SHIFT (0U) /*! DMRBD - DM Read Bit Delay */ #define DDRPHY_DX6BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR5_DMRBD_SHIFT)) & DDRPHY_DX6BDLR5_DMRBD_MASK) #define DDRPHY_DX6BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U) #define DDRPHY_DX6BDLR5_RESERVED_31_6_SHIFT (6U) /*! RESERVED_31_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX6BDLR5_RESERVED_31_6_MASK) /*! @} */ /*! @name DX6BDLR6 - DATX8 n Bit Delay Line Register 6 */ /*! @{ */ #define DDRPHY_DX6BDLR6_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_DX6BDLR6_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX6BDLR6_RESERVED_7_0_MASK) #define DDRPHY_DX6BDLR6_PDRBD_MASK (0x3F00U) #define DDRPHY_DX6BDLR6_PDRBD_SHIFT (8U) /*! PDRBD - Power down receiver Bit Delay */ #define DDRPHY_DX6BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_PDRBD_SHIFT)) & DDRPHY_DX6BDLR6_PDRBD_MASK) #define DDRPHY_DX6BDLR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6BDLR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR6_RESERVED_15_14_MASK) #define DDRPHY_DX6BDLR6_TERBD_MASK (0x3F0000U) #define DDRPHY_DX6BDLR6_TERBD_SHIFT (16U) /*! TERBD - Termination Enable Bit Delay */ #define DDRPHY_DX6BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_TERBD_SHIFT)) & DDRPHY_DX6BDLR6_TERBD_MASK) #define DDRPHY_DX6BDLR6_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX6BDLR6_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR6_RESERVED_31_22_MASK) /*! @} */ /*! @name DX6BDLR7 - DATX8 n Bit Delay Line Register 7 */ /*! @{ */ #define DDRPHY_DX6BDLR7_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX6BDLR7_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_5_0_MASK) #define DDRPHY_DX6BDLR7_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6BDLR7_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_7_6_MASK) #define DDRPHY_DX6BDLR7_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX6BDLR7_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_13_8_MASK) #define DDRPHY_DX6BDLR7_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6BDLR7_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_15_14_MASK) #define DDRPHY_DX6BDLR7_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX6BDLR7_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_21_16_MASK) #define DDRPHY_DX6BDLR7_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX6BDLR7_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_31_22_MASK) /*! @} */ /*! @name DX6BDLR8 - DATX8 n Bit Delay Line Register 8 */ /*! @{ */ #define DDRPHY_DX6BDLR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX6BDLR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_5_0_MASK) #define DDRPHY_DX6BDLR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6BDLR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_7_6_MASK) #define DDRPHY_DX6BDLR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX6BDLR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_13_8_MASK) #define DDRPHY_DX6BDLR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6BDLR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_15_14_MASK) #define DDRPHY_DX6BDLR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX6BDLR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_21_16_MASK) #define DDRPHY_DX6BDLR8_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX6BDLR8_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_31_22_MASK) /*! @} */ /*! @name DX6BDLR9 - DATX8 n Bit Delay Line Register 9 */ /*! @{ */ #define DDRPHY_DX6BDLR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX6BDLR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_5_0_MASK) #define DDRPHY_DX6BDLR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX6BDLR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_7_6_MASK) #define DDRPHY_DX6BDLR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX6BDLR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_13_8_MASK) #define DDRPHY_DX6BDLR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX6BDLR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_15_14_MASK) #define DDRPHY_DX6BDLR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX6BDLR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_21_16_MASK) #define DDRPHY_DX6BDLR9_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX6BDLR9_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_31_22_MASK) /*! @} */ /*! @name DX6LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX6LCDLR0_WLD_MASK (0x1FFU) #define DDRPHY_DX6LCDLR0_WLD_SHIFT (0U) /*! WLD - Write Leveling Delay */ #define DDRPHY_DX6LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_WLD_SHIFT)) & DDRPHY_DX6LCDLR0_WLD_MASK) #define DDRPHY_DX6LCDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX6LCDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX6LCDLR0_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX6LCDLR0_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR0_RESERVED_24_16_MASK) #define DDRPHY_DX6LCDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX6LCDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX6LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX6LCDLR1_WDQD_MASK (0x1FFU) #define DDRPHY_DX6LCDLR1_WDQD_SHIFT (0U) /*! WDQD - Write Data Delay */ #define DDRPHY_DX6LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_WDQD_SHIFT)) & DDRPHY_DX6LCDLR1_WDQD_MASK) #define DDRPHY_DX6LCDLR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX6LCDLR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR1_RESERVED_15_9_MASK) #define DDRPHY_DX6LCDLR1_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX6LCDLR1_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR1_RESERVED_24_16_MASK) #define DDRPHY_DX6LCDLR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX6LCDLR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX6LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX6LCDLR2_DQSGD_MASK (0x1FFU) #define DDRPHY_DX6LCDLR2_DQSGD_SHIFT (0U) /*! DQSGD - Read DQS Gating Delay */ #define DDRPHY_DX6LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX6LCDLR2_DQSGD_MASK) #define DDRPHY_DX6LCDLR2_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX6LCDLR2_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR2_RESERVED_15_9_MASK) #define DDRPHY_DX6LCDLR2_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX6LCDLR2_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR2_RESERVED_24_16_MASK) #define DDRPHY_DX6LCDLR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX6LCDLR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR2_RESERVED_31_25_MASK) /*! @} */ /*! @name DX6LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX6LCDLR3_RDQSD_MASK (0x1FFU) #define DDRPHY_DX6LCDLR3_RDQSD_SHIFT (0U) /*! RDQSD - Read DQS Delay */ #define DDRPHY_DX6LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX6LCDLR3_RDQSD_MASK) #define DDRPHY_DX6LCDLR3_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX6LCDLR3_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR3_RESERVED_15_9_MASK) #define DDRPHY_DX6LCDLR3_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX6LCDLR3_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR3_RESERVED_24_16_MASK) #define DDRPHY_DX6LCDLR3_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX6LCDLR3_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR3_RESERVED_31_25_MASK) /*! @} */ /*! @name DX6LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX6LCDLR4_RDQSND_MASK (0x1FFU) #define DDRPHY_DX6LCDLR4_RDQSND_SHIFT (0U) /*! RDQSND - Read DQSN Delay */ #define DDRPHY_DX6LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX6LCDLR4_RDQSND_MASK) #define DDRPHY_DX6LCDLR4_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX6LCDLR4_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR4_RESERVED_15_9_MASK) #define DDRPHY_DX6LCDLR4_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX6LCDLR4_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR4_RESERVED_24_16_MASK) #define DDRPHY_DX6LCDLR4_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX6LCDLR4_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR4_RESERVED_31_25_MASK) /*! @} */ /*! @name DX6LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX6LCDLR5_DQSGSD_MASK (0x1FFU) #define DDRPHY_DX6LCDLR5_DQSGSD_SHIFT (0U) /*! DQSGSD - DQS Gating Status Delay */ #define DDRPHY_DX6LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX6LCDLR5_DQSGSD_MASK) #define DDRPHY_DX6LCDLR5_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX6LCDLR5_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR5_RESERVED_15_9_MASK) #define DDRPHY_DX6LCDLR5_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX6LCDLR5_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR5_RESERVED_24_16_MASK) #define DDRPHY_DX6LCDLR5_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX6LCDLR5_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR5_RESERVED_31_25_MASK) /*! @} */ /*! @name DX6MDLR0 - DATX8 n Master Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX6MDLR0_IPRD_MASK (0x1FFU) #define DDRPHY_DX6MDLR0_IPRD_SHIFT (0U) /*! IPRD - Initial Period */ #define DDRPHY_DX6MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_IPRD_SHIFT)) & DDRPHY_DX6MDLR0_IPRD_MASK) #define DDRPHY_DX6MDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX6MDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX6MDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX6MDLR0_TPRD_MASK (0x1FF0000U) #define DDRPHY_DX6MDLR0_TPRD_SHIFT (16U) /*! TPRD - Target Period */ #define DDRPHY_DX6MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_TPRD_SHIFT)) & DDRPHY_DX6MDLR0_TPRD_MASK) #define DDRPHY_DX6MDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX6MDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX6MDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX6MDLR1 - DATX8 n Master Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX6MDLR1_MDLD_MASK (0x1FFU) #define DDRPHY_DX6MDLR1_MDLD_SHIFT (0U) /*! MDLD - MDL Delay */ #define DDRPHY_DX6MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR1_MDLD_SHIFT)) & DDRPHY_DX6MDLR1_MDLD_MASK) #define DDRPHY_DX6MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U) #define DDRPHY_DX6MDLR1_RESERVED_31_9_SHIFT (9U) /*! RESERVED_31_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX6MDLR1_RESERVED_31_9_MASK) /*! @} */ /*! @name DX6GTR0 - DATX8 n General Timing Register 0 */ /*! @{ */ #define DDRPHY_DX6GTR0_DGSL_MASK (0x1FU) #define DDRPHY_DX6GTR0_DGSL_SHIFT (0U) /*! DGSL - DQS Gating System Latency */ #define DDRPHY_DX6GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_DGSL_SHIFT)) & DDRPHY_DX6GTR0_DGSL_MASK) #define DDRPHY_DX6GTR0_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DX6GTR0_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_7_5_MASK) #define DDRPHY_DX6GTR0_RESERVED_12_8_MASK (0x1F00U) #define DDRPHY_DX6GTR0_RESERVED_12_8_SHIFT (8U) /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_12_8_MASK) #define DDRPHY_DX6GTR0_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_DX6GTR0_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_15_13_MASK) #define DDRPHY_DX6GTR0_WLSL_MASK (0xF0000U) #define DDRPHY_DX6GTR0_WLSL_SHIFT (16U) /*! WLSL - Write Leveling System Latency */ #define DDRPHY_DX6GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_WLSL_SHIFT)) & DDRPHY_DX6GTR0_WLSL_MASK) #define DDRPHY_DX6GTR0_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX6GTR0_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX6GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_23_20_MASK) #define DDRPHY_DX6GTR0_WDQSL_MASK (0x7000000U) #define DDRPHY_DX6GTR0_WDQSL_SHIFT (24U) /*! WDQSL - DQ Write Path Latency Pipeline */ #define DDRPHY_DX6GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_WDQSL_SHIFT)) & DDRPHY_DX6GTR0_WDQSL_MASK) #define DDRPHY_DX6GTR0_RESERVED_31_24_MASK (0xF8000000U) #define DDRPHY_DX6GTR0_RESERVED_31_24_SHIFT (27U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_31_24_MASK) /*! @} */ /*! @name DX6RSR0 - DATX8 n Rank Status Register 0 */ /*! @{ */ #define DDRPHY_DX6RSR0_QSGERR_MASK (0xFFFFU) #define DDRPHY_DX6RSR0_QSGERR_SHIFT (0U) /*! QSGERR - DQS Gate Training Error */ #define DDRPHY_DX6RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR0_QSGERR_SHIFT)) & DDRPHY_DX6RSR0_QSGERR_MASK) #define DDRPHY_DX6RSR0_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX6RSR0_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR0_RESERVED_31_16_MASK) /*! @} */ /*! @name DX6RSR1 - DATX8 n Rank Status Register 1 */ /*! @{ */ #define DDRPHY_DX6RSR1_RDLVLERR_MASK (0xFFFFU) #define DDRPHY_DX6RSR1_RDLVLERR_SHIFT (0U) /*! RDLVLERR - Read Leveling Error */ #define DDRPHY_DX6RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX6RSR1_RDLVLERR_MASK) #define DDRPHY_DX6RSR1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX6RSR1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR1_RESERVED_31_16_MASK) /*! @} */ /*! @name DX6RSR2 - DATX8 n Rank Status Register 2 */ /*! @{ */ #define DDRPHY_DX6RSR2_WLAWN_MASK (0xFFFFU) #define DDRPHY_DX6RSR2_WLAWN_SHIFT (0U) /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning */ #define DDRPHY_DX6RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR2_WLAWN_SHIFT)) & DDRPHY_DX6RSR2_WLAWN_MASK) #define DDRPHY_DX6RSR2_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX6RSR2_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR2_RESERVED_31_16_MASK) /*! @} */ /*! @name DX6RSR3 - DATX8 n Rank Status Register 3 */ /*! @{ */ #define DDRPHY_DX6RSR3_WLAERR_MASK (0xFFFFU) #define DDRPHY_DX6RSR3_WLAERR_SHIFT (0U) /*! WLAERR - Write Leveling Adjustment Error */ #define DDRPHY_DX6RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR3_WLAERR_SHIFT)) & DDRPHY_DX6RSR3_WLAERR_MASK) #define DDRPHY_DX6RSR3_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX6RSR3_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR3_RESERVED_31_16_MASK) /*! @} */ /*! @name DX6GSR0 - DATX8 n General Status Register 0 */ /*! @{ */ #define DDRPHY_DX6GSR0_WDQCAL_MASK (0x1U) #define DDRPHY_DX6GSR0_WDQCAL_SHIFT (0U) /*! WDQCAL - Write DQ Calibration */ #define DDRPHY_DX6GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WDQCAL_SHIFT)) & DDRPHY_DX6GSR0_WDQCAL_MASK) #define DDRPHY_DX6GSR0_RDQSCAL_MASK (0x2U) #define DDRPHY_DX6GSR0_RDQSCAL_SHIFT (1U) /*! RDQSCAL - Read DQS Calibration */ #define DDRPHY_DX6GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX6GSR0_RDQSCAL_MASK) #define DDRPHY_DX6GSR0_RDQSNCAL_MASK (0x4U) #define DDRPHY_DX6GSR0_RDQSNCAL_SHIFT (2U) /*! RDQSNCAL - Read DQS# Calibration */ #define DDRPHY_DX6GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX6GSR0_RDQSNCAL_MASK) #define DDRPHY_DX6GSR0_GDQSCAL_MASK (0x8U) #define DDRPHY_DX6GSR0_GDQSCAL_SHIFT (3U) /*! GDQSCAL - Read DQS gating Calibration */ #define DDRPHY_DX6GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX6GSR0_GDQSCAL_MASK) #define DDRPHY_DX6GSR0_WLCAL_MASK (0x10U) #define DDRPHY_DX6GSR0_WLCAL_SHIFT (4U) /*! WLCAL - Write Leveling Calibration */ #define DDRPHY_DX6GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLCAL_SHIFT)) & DDRPHY_DX6GSR0_WLCAL_MASK) #define DDRPHY_DX6GSR0_WLDONE_MASK (0x20U) #define DDRPHY_DX6GSR0_WLDONE_SHIFT (5U) /*! WLDONE - Write Leveling Done */ #define DDRPHY_DX6GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLDONE_SHIFT)) & DDRPHY_DX6GSR0_WLDONE_MASK) #define DDRPHY_DX6GSR0_WLERR_MASK (0x40U) #define DDRPHY_DX6GSR0_WLERR_SHIFT (6U) /*! WLERR - Write Leveling Error */ #define DDRPHY_DX6GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLERR_SHIFT)) & DDRPHY_DX6GSR0_WLERR_MASK) #define DDRPHY_DX6GSR0_WLPRD_MASK (0xFF80U) #define DDRPHY_DX6GSR0_WLPRD_SHIFT (7U) /*! WLPRD - Write Leveling Period */ #define DDRPHY_DX6GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLPRD_SHIFT)) & DDRPHY_DX6GSR0_WLPRD_MASK) #define DDRPHY_DX6GSR0_DPLOCK_MASK (0x10000U) #define DDRPHY_DX6GSR0_DPLOCK_SHIFT (16U) /*! DPLOCK - DATX8 PLL Lock */ #define DDRPHY_DX6GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_DPLOCK_SHIFT)) & DDRPHY_DX6GSR0_DPLOCK_MASK) #define DDRPHY_DX6GSR0_GDQSPRD_MASK (0x3FE0000U) #define DDRPHY_DX6GSR0_GDQSPRD_SHIFT (17U) /*! GDQSPRD - Read DQS gating Period */ #define DDRPHY_DX6GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX6GSR0_GDQSPRD_MASK) #define DDRPHY_DX6GSR0_RESERVED_29_26_MASK (0x3C000000U) #define DDRPHY_DX6GSR0_RESERVED_29_26_SHIFT (26U) /*! RESERVED_29_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX6GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX6GSR0_RESERVED_29_26_MASK) #define DDRPHY_DX6GSR0_WLDQ_MASK (0x40000000U) #define DDRPHY_DX6GSR0_WLDQ_SHIFT (30U) /*! WLDQ - Write Leveling DQ Status */ #define DDRPHY_DX6GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLDQ_SHIFT)) & DDRPHY_DX6GSR0_WLDQ_MASK) #define DDRPHY_DX6GSR0_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX6GSR0_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX6GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX6GSR0_RESERVED_31_MASK) /*! @} */ /*! @name DX6GSR1 - DATX8 n General Status Register 1 */ /*! @{ */ #define DDRPHY_DX6GSR1_DLTDONE_MASK (0x1U) #define DDRPHY_DX6GSR1_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done */ #define DDRPHY_DX6GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR1_DLTDONE_SHIFT)) & DDRPHY_DX6GSR1_DLTDONE_MASK) #define DDRPHY_DX6GSR1_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_DX6GSR1_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code */ #define DDRPHY_DX6GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR1_DLTCODE_SHIFT)) & DDRPHY_DX6GSR1_DLTCODE_MASK) #define DDRPHY_DX6GSR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX6GSR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX6GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX6GSR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX6GSR2 - DATX8 n General Status Register 2 */ /*! @{ */ #define DDRPHY_DX6GSR2_RDERR_MASK (0x1U) #define DDRPHY_DX6GSR2_RDERR_SHIFT (0U) /*! RDERR - Read Bit Deskew Error */ #define DDRPHY_DX6GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_RDERR_SHIFT)) & DDRPHY_DX6GSR2_RDERR_MASK) #define DDRPHY_DX6GSR2_RDWN_MASK (0x2U) #define DDRPHY_DX6GSR2_RDWN_SHIFT (1U) /*! RDWN - Read Bit Deskew Warning */ #define DDRPHY_DX6GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_RDWN_SHIFT)) & DDRPHY_DX6GSR2_RDWN_MASK) #define DDRPHY_DX6GSR2_WDERR_MASK (0x4U) #define DDRPHY_DX6GSR2_WDERR_SHIFT (2U) /*! WDERR - Write Bit Deskew Error */ #define DDRPHY_DX6GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WDERR_SHIFT)) & DDRPHY_DX6GSR2_WDERR_MASK) #define DDRPHY_DX6GSR2_WDWN_MASK (0x8U) #define DDRPHY_DX6GSR2_WDWN_SHIFT (3U) /*! WDWN - Write Bit Deskew Warning */ #define DDRPHY_DX6GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WDWN_SHIFT)) & DDRPHY_DX6GSR2_WDWN_MASK) #define DDRPHY_DX6GSR2_REERR_MASK (0x10U) #define DDRPHY_DX6GSR2_REERR_SHIFT (4U) /*! REERR - Read Eye Centering Error */ #define DDRPHY_DX6GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_REERR_SHIFT)) & DDRPHY_DX6GSR2_REERR_MASK) #define DDRPHY_DX6GSR2_REWN_MASK (0x20U) #define DDRPHY_DX6GSR2_REWN_SHIFT (5U) /*! REWN - Read Eye Centering Warning */ #define DDRPHY_DX6GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_REWN_SHIFT)) & DDRPHY_DX6GSR2_REWN_MASK) #define DDRPHY_DX6GSR2_WEERR_MASK (0x40U) #define DDRPHY_DX6GSR2_WEERR_SHIFT (6U) /*! WEERR - Write Eye Centering Error */ #define DDRPHY_DX6GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WEERR_SHIFT)) & DDRPHY_DX6GSR2_WEERR_MASK) #define DDRPHY_DX6GSR2_WEWN_MASK (0x80U) #define DDRPHY_DX6GSR2_WEWN_SHIFT (7U) /*! WEWN - Write Eye Centering Warning */ #define DDRPHY_DX6GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WEWN_SHIFT)) & DDRPHY_DX6GSR2_WEWN_MASK) #define DDRPHY_DX6GSR2_ESTAT_MASK (0xF00U) #define DDRPHY_DX6GSR2_ESTAT_SHIFT (8U) /*! ESTAT - Error Status */ #define DDRPHY_DX6GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_ESTAT_SHIFT)) & DDRPHY_DX6GSR2_ESTAT_MASK) #define DDRPHY_DX6GSR2_DQS2DQERR_MASK (0xFF000U) #define DDRPHY_DX6GSR2_DQS2DQERR_SHIFT (12U) /*! DQS2DQERR - Write DQS2DQ Training Error */ #define DDRPHY_DX6GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX6GSR2_DQS2DQERR_MASK) #define DDRPHY_DX6GSR2_SRDERR_MASK (0x100000U) #define DDRPHY_DX6GSR2_SRDERR_SHIFT (20U) /*! SRDERR - Static Read Error */ #define DDRPHY_DX6GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_SRDERR_SHIFT)) & DDRPHY_DX6GSR2_SRDERR_MASK) #define DDRPHY_DX6GSR2_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX6GSR2_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX6GSR2_RESERVED_21_MASK) #define DDRPHY_DX6GSR2_GSDQSCAL_MASK (0x400000U) #define DDRPHY_DX6GSR2_GSDQSCAL_SHIFT (22U) /*! GSDQSCAL - Read DQS Gating Status Calibration */ #define DDRPHY_DX6GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX6GSR2_GSDQSCAL_MASK) #define DDRPHY_DX6GSR2_GSDQSPRD_MASK (0xFF800000U) #define DDRPHY_DX6GSR2_GSDQSPRD_SHIFT (23U) /*! GSDQSPRD - Read DQS gating Status Period */ #define DDRPHY_DX6GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX6GSR2_GSDQSPRD_MASK) /*! @} */ /*! @name DX6GSR3 - DATX8 n General Status Register 3 */ /*! @{ */ #define DDRPHY_DX6GSR3_SRDPC_MASK (0x3U) #define DDRPHY_DX6GSR3_SRDPC_SHIFT (0U) /*! SRDPC - Static Read Delay Pass Count */ #define DDRPHY_DX6GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_SRDPC_SHIFT)) & DDRPHY_DX6GSR3_SRDPC_MASK) #define DDRPHY_DX6GSR3_RESERVED_7_2_MASK (0xFCU) #define DDRPHY_DX6GSR3_RESERVED_7_2_SHIFT (2U) /*! RESERVED_7_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX6GSR3_RESERVED_7_2_MASK) #define DDRPHY_DX6GSR3_HVERR_MASK (0xF00U) #define DDRPHY_DX6GSR3_HVERR_SHIFT (8U) /*! HVERR - Host VREF Training Error */ #define DDRPHY_DX6GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_HVERR_SHIFT)) & DDRPHY_DX6GSR3_HVERR_MASK) #define DDRPHY_DX6GSR3_HVWRN_MASK (0xF000U) #define DDRPHY_DX6GSR3_HVWRN_SHIFT (12U) /*! HVWRN - Host VREF Training Warning */ #define DDRPHY_DX6GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_HVWRN_SHIFT)) & DDRPHY_DX6GSR3_HVWRN_MASK) #define DDRPHY_DX6GSR3_DVERR_MASK (0xF0000U) #define DDRPHY_DX6GSR3_DVERR_SHIFT (16U) /*! DVERR - DRAM VREF Training Error */ #define DDRPHY_DX6GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_DVERR_SHIFT)) & DDRPHY_DX6GSR3_DVERR_MASK) #define DDRPHY_DX6GSR3_DVWRN_MASK (0xF00000U) #define DDRPHY_DX6GSR3_DVWRN_SHIFT (20U) /*! DVWRN - DRAM VREF Training Warning */ #define DDRPHY_DX6GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_DVWRN_SHIFT)) & DDRPHY_DX6GSR3_DVWRN_MASK) #define DDRPHY_DX6GSR3_ESTAT_MASK (0x7000000U) #define DDRPHY_DX6GSR3_ESTAT_SHIFT (24U) /*! ESTAT - VREF Training Error Status Code */ #define DDRPHY_DX6GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_ESTAT_SHIFT)) & DDRPHY_DX6GSR3_ESTAT_MASK) #define DDRPHY_DX6GSR3_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX6GSR3_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX6GSR3_RESERVED_31_27_MASK) /*! @} */ /*! @name DX6GSR4 - DATX8 n General Status Register 4 */ /*! @{ */ #define DDRPHY_DX6GSR4_RESERVED_0_MASK (0x1U) #define DDRPHY_DX6GSR4_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_0_MASK) #define DDRPHY_DX6GSR4_RESERVED_1_MASK (0x2U) #define DDRPHY_DX6GSR4_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_1_MASK) #define DDRPHY_DX6GSR4_RESERVED_2_MASK (0x4U) #define DDRPHY_DX6GSR4_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_2_MASK) #define DDRPHY_DX6GSR4_RESERVED_3_MASK (0x8U) #define DDRPHY_DX6GSR4_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_3_MASK) #define DDRPHY_DX6GSR4_RESERVED_4_MASK (0x10U) #define DDRPHY_DX6GSR4_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_4_MASK) #define DDRPHY_DX6GSR4_RESERVED_5_MASK (0x20U) #define DDRPHY_DX6GSR4_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_5_MASK) #define DDRPHY_DX6GSR4_RESERVED_6_MASK (0x40U) #define DDRPHY_DX6GSR4_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_6_MASK) #define DDRPHY_DX6GSR4_RESERVED_15_7_MASK (0xFF80U) #define DDRPHY_DX6GSR4_RESERVED_15_7_SHIFT (7U) /*! RESERVED_15_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_15_7_MASK) #define DDRPHY_DX6GSR4_RESERVED_16_MASK (0x10000U) #define DDRPHY_DX6GSR4_RESERVED_16_SHIFT (16U) /*! RESERVED_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_16_MASK) #define DDRPHY_DX6GSR4_RESERVED_25_17_MASK (0x3FE0000U) #define DDRPHY_DX6GSR4_RESERVED_25_17_SHIFT (17U) /*! RESERVED_25_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_25_17_MASK) #define DDRPHY_DX6GSR4_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_DX6GSR4_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX6GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_31_26_MASK) /*! @} */ /*! @name DX6GSR5 - DATX8 n General Status Register 5 */ /*! @{ */ #define DDRPHY_DX6GSR5_RESERVED_0_MASK (0x1U) #define DDRPHY_DX6GSR5_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_0_MASK) #define DDRPHY_DX6GSR5_RESERVED_1_MASK (0x2U) #define DDRPHY_DX6GSR5_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_1_MASK) #define DDRPHY_DX6GSR5_RESERVED_2_MASK (0x4U) #define DDRPHY_DX6GSR5_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_2_MASK) #define DDRPHY_DX6GSR5_RESERVED_3_MASK (0x8U) #define DDRPHY_DX6GSR5_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_3_MASK) #define DDRPHY_DX6GSR5_RESERVED_4_MASK (0x10U) #define DDRPHY_DX6GSR5_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_4_MASK) #define DDRPHY_DX6GSR5_RESERVED_5_MASK (0x20U) #define DDRPHY_DX6GSR5_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_5_MASK) #define DDRPHY_DX6GSR5_RESERVED_6_MASK (0x40U) #define DDRPHY_DX6GSR5_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_6_MASK) #define DDRPHY_DX6GSR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX6GSR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_7_MASK) #define DDRPHY_DX6GSR5_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX6GSR5_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_11_8_MASK) #define DDRPHY_DX6GSR5_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_DX6GSR5_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_19_12_MASK) #define DDRPHY_DX6GSR5_RESERVED_20_MASK (0x100000U) #define DDRPHY_DX6GSR5_RESERVED_20_SHIFT (20U) /*! RESERVED_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_20_MASK) #define DDRPHY_DX6GSR5_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX6GSR5_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_21_MASK) #define DDRPHY_DX6GSR5_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX6GSR5_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_22_MASK) #define DDRPHY_DX6GSR5_RESERVED_31_23_MASK (0xFF800000U) #define DDRPHY_DX6GSR5_RESERVED_31_23_SHIFT (23U) /*! RESERVED_31_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_31_23_MASK) /*! @} */ /*! @name DX6GSR6 - DATX8 n General Status Register 6 */ /*! @{ */ #define DDRPHY_DX6GSR6_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX6GSR6_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_1_0_MASK) #define DDRPHY_DX6GSR6_RESERVED_3_2_MASK (0xCU) #define DDRPHY_DX6GSR6_RESERVED_3_2_SHIFT (2U) /*! RESERVED_3_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_3_2_MASK) #define DDRPHY_DX6GSR6_RESERVED_7_4_MASK (0xF0U) #define DDRPHY_DX6GSR6_RESERVED_7_4_SHIFT (4U) /*! RESERVED_7_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_7_4_MASK) #define DDRPHY_DX6GSR6_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX6GSR6_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_11_8_MASK) #define DDRPHY_DX6GSR6_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_DX6GSR6_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_15_12_MASK) #define DDRPHY_DX6GSR6_RESERVED_19_15_MASK (0xF0000U) #define DDRPHY_DX6GSR6_RESERVED_19_15_SHIFT (16U) /*! RESERVED_19_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_19_15_MASK) #define DDRPHY_DX6GSR6_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX6GSR6_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_23_20_MASK) #define DDRPHY_DX6GSR6_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX6GSR6_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX6GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_31_24_MASK) /*! @} */ /*! @name DX7GCR0 - DATX8 n General Configuration Register 0 */ /*! @{ */ #define DDRPHY_DX7GCR0_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX7GCR0_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX7GCR0_RESERVED_1_0_MASK) #define DDRPHY_DX7GCR0_DQSGOE_MASK (0x4U) #define DDRPHY_DX7GCR0_DQSGOE_SHIFT (2U) /*! DQSGOE - DQSG Output Enable */ #define DDRPHY_DX7GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSGOE_SHIFT)) & DDRPHY_DX7GCR0_DQSGOE_MASK) #define DDRPHY_DX7GCR0_DQSGODT_MASK (0x8U) #define DDRPHY_DX7GCR0_DQSGODT_SHIFT (3U) /*! DQSGODT - DQSG On-Die Termination */ #define DDRPHY_DX7GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSGODT_SHIFT)) & DDRPHY_DX7GCR0_DQSGODT_MASK) #define DDRPHY_DX7GCR0_RESERVED_4_MASK (0x10U) #define DDRPHY_DX7GCR0_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX7GCR0_RESERVED_4_MASK) #define DDRPHY_DX7GCR0_DQSGPDR_MASK (0x20U) #define DDRPHY_DX7GCR0_DQSGPDR_SHIFT (5U) /*! DQSGPDR - DQSG Power Down Receiver */ #define DDRPHY_DX7GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX7GCR0_DQSGPDR_MASK) #define DDRPHY_DX7GCR0_DQSRPD_MASK (0x40U) #define DDRPHY_DX7GCR0_DQSRPD_SHIFT (6U) /*! DQSRPD - DQSR Power Down */ #define DDRPHY_DX7GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSRPD_SHIFT)) & DDRPHY_DX7GCR0_DQSRPD_MASK) #define DDRPHY_DX7GCR0_CPDRSHFT_MASK (0x180U) #define DDRPHY_DX7GCR0_CPDRSHFT_SHIFT (7U) /*! CPDRSHFT - Configurable PDR Phase Shift */ #define DDRPHY_DX7GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX7GCR0_CPDRSHFT_MASK) #define DDRPHY_DX7GCR0_RTTOH_MASK (0x600U) #define DDRPHY_DX7GCR0_RTTOH_SHIFT (9U) /*! RTTOH - RTT Output Hold */ #define DDRPHY_DX7GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RTTOH_SHIFT)) & DDRPHY_DX7GCR0_RTTOH_MASK) #define DDRPHY_DX7GCR0_RTTOAL_MASK (0x800U) #define DDRPHY_DX7GCR0_RTTOAL_SHIFT (11U) /*! RTTOAL - RTT On Additive Latency */ #define DDRPHY_DX7GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RTTOAL_SHIFT)) & DDRPHY_DX7GCR0_RTTOAL_MASK) #define DDRPHY_DX7GCR0_DQSSEPDR_MASK (0x1000U) #define DDRPHY_DX7GCR0_DQSSEPDR_SHIFT (12U) /*! DQSSEPDR - DQSSE Power Down Receiver */ #define DDRPHY_DX7GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX7GCR0_DQSSEPDR_MASK) #define DDRPHY_DX7GCR0_DQSNSEPDR_MASK (0x2000U) #define DDRPHY_DX7GCR0_DQSNSEPDR_SHIFT (13U) /*! DQSNSEPDR - DQSNSE Power Down Receiver */ #define DDRPHY_DX7GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX7GCR0_DQSNSEPDR_MASK) #define DDRPHY_DX7GCR0_RESERVED_19_14_MASK (0xFC000U) #define DDRPHY_DX7GCR0_RESERVED_19_14_SHIFT (14U) /*! RESERVED_19_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX7GCR0_RESERVED_19_14_MASK) #define DDRPHY_DX7GCR0_RDDLY_MASK (0xF00000U) #define DDRPHY_DX7GCR0_RDDLY_SHIFT (20U) /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY */ #define DDRPHY_DX7GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RDDLY_SHIFT)) & DDRPHY_DX7GCR0_RDDLY_MASK) #define DDRPHY_DX7GCR0_DQSDCC_MASK (0xF000000U) #define DDRPHY_DX7GCR0_DQSDCC_SHIFT (24U) /*! DQSDCC - DQS Duty Cycle Correction */ #define DDRPHY_DX7GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSDCC_SHIFT)) & DDRPHY_DX7GCR0_DQSDCC_MASK) #define DDRPHY_DX7GCR0_CODTSHFT_MASK (0x30000000U) #define DDRPHY_DX7GCR0_CODTSHFT_SHIFT (28U) /*! CODTSHFT - Configurable ODT(TE) Phase Shift */ #define DDRPHY_DX7GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX7GCR0_CODTSHFT_MASK) #define DDRPHY_DX7GCR0_MDLEN_MASK (0x40000000U) #define DDRPHY_DX7GCR0_MDLEN_SHIFT (30U) /*! MDLEN - Master Delay Line Enable */ #define DDRPHY_DX7GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_MDLEN_SHIFT)) & DDRPHY_DX7GCR0_MDLEN_MASK) #define DDRPHY_DX7GCR0_CALBYP_MASK (0x80000000U) #define DDRPHY_DX7GCR0_CALBYP_SHIFT (31U) /*! CALBYP - Calibration Bypass */ #define DDRPHY_DX7GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_CALBYP_SHIFT)) & DDRPHY_DX7GCR0_CALBYP_MASK) /*! @} */ /*! @name DX7GCR1 - DATX8 n General Configuration Register 1 */ /*! @{ */ #define DDRPHY_DX7GCR1_DQEN_MASK (0xFFU) #define DDRPHY_DX7GCR1_DQEN_SHIFT (0U) /*! DQEN - Enables DQ corresponding to each bit in a byte */ #define DDRPHY_DX7GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DQEN_SHIFT)) & DDRPHY_DX7GCR1_DQEN_MASK) #define DDRPHY_DX7GCR1_DMEN_MASK (0x100U) #define DDRPHY_DX7GCR1_DMEN_SHIFT (8U) /*! DMEN - Enables DM pin in a byte lane */ #define DDRPHY_DX7GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DMEN_SHIFT)) & DDRPHY_DX7GCR1_DMEN_MASK) #define DDRPHY_DX7GCR1_DSEN_MASK (0x200U) #define DDRPHY_DX7GCR1_DSEN_SHIFT (9U) /*! DSEN - Enables Write Data strobe in a byte lane */ #define DDRPHY_DX7GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DSEN_SHIFT)) & DDRPHY_DX7GCR1_DSEN_MASK) #define DDRPHY_DX7GCR1_TEEN_MASK (0x400U) #define DDRPHY_DX7GCR1_TEEN_SHIFT (10U) /*! TEEN - Enables ODT/TE in a byte lane */ #define DDRPHY_DX7GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_TEEN_SHIFT)) & DDRPHY_DX7GCR1_TEEN_MASK) #define DDRPHY_DX7GCR1_PDREN_MASK (0x800U) #define DDRPHY_DX7GCR1_PDREN_SHIFT (11U) /*! PDREN - Enables PDR in a byte lane */ #define DDRPHY_DX7GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_PDREN_SHIFT)) & DDRPHY_DX7GCR1_PDREN_MASK) #define DDRPHY_DX7GCR1_OEEN_MASK (0x1000U) #define DDRPHY_DX7GCR1_OEEN_SHIFT (12U) /*! OEEN - Enables Read Data Strobe in a byte lane */ #define DDRPHY_DX7GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_OEEN_SHIFT)) & DDRPHY_DX7GCR1_OEEN_MASK) #define DDRPHY_DX7GCR1_QSSEL_MASK (0x2000U) #define DDRPHY_DX7GCR1_QSSEL_SHIFT (13U) /*! QSSEL - Select the delayed or non-delayed read data strobe */ #define DDRPHY_DX7GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_QSSEL_SHIFT)) & DDRPHY_DX7GCR1_QSSEL_MASK) #define DDRPHY_DX7GCR1_QSNSEL_MASK (0x4000U) #define DDRPHY_DX7GCR1_QSNSEL_SHIFT (14U) /*! QSNSEL - Select the delayed or non-delayed read data strobe # */ #define DDRPHY_DX7GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_QSNSEL_SHIFT)) & DDRPHY_DX7GCR1_QSNSEL_MASK) #define DDRPHY_DX7GCR1_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX7GCR1_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX7GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX7GCR1_RESERVED_15_MASK) #define DDRPHY_DX7GCR1_DXPDRMODE_MASK (0xFFFF0000U) #define DDRPHY_DX7GCR1_DXPDRMODE_SHIFT (16U) /*! DXPDRMODE - Enables the PDR mode for DQ[7:0] */ #define DDRPHY_DX7GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX7GCR1_DXPDRMODE_MASK) /*! @} */ /*! @name DX7GCR2 - DATX8 n General Configuration Register 2 */ /*! @{ */ #define DDRPHY_DX7GCR2_DXTEMODE_MASK (0xFFFFU) #define DDRPHY_DX7GCR2_DXTEMODE_SHIFT (0U) /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0] */ #define DDRPHY_DX7GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX7GCR2_DXTEMODE_MASK) #define DDRPHY_DX7GCR2_DXOEMODE_MASK (0xFFFF0000U) #define DDRPHY_DX7GCR2_DXOEMODE_SHIFT (16U) /*! DXOEMODE - Enables the OE mode values for DQ[7:0] */ #define DDRPHY_DX7GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX7GCR2_DXOEMODE_MASK) /*! @} */ /*! @name DX7GCR3 - DATX8 n General Configuration Register 3 */ /*! @{ */ #define DDRPHY_DX7GCR3_WDMBVT_MASK (0x1U) #define DDRPHY_DX7GCR3_WDMBVT_SHIFT (0U) /*! WDMBVT - Write Data Mask BDL VT Compensation */ #define DDRPHY_DX7GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDMBVT_SHIFT)) & DDRPHY_DX7GCR3_WDMBVT_MASK) #define DDRPHY_DX7GCR3_RDMBVT_MASK (0x2U) #define DDRPHY_DX7GCR3_RDMBVT_SHIFT (1U) /*! RDMBVT - Read Data Mask BDL VT Compensation */ #define DDRPHY_DX7GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RDMBVT_SHIFT)) & DDRPHY_DX7GCR3_RDMBVT_MASK) #define DDRPHY_DX7GCR3_DSPDRMODE_MASK (0xCU) #define DDRPHY_DX7GCR3_DSPDRMODE_SHIFT (2U) /*! DSPDRMODE - Enables the PDR mode values for DQS. */ #define DDRPHY_DX7GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX7GCR3_DSPDRMODE_MASK) #define DDRPHY_DX7GCR3_DSTEMODE_MASK (0x30U) #define DDRPHY_DX7GCR3_DSTEMODE_SHIFT (4U) /*! DSTEMODE - Enables the TE mode values for DQS. */ #define DDRPHY_DX7GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSTEMODE_MASK) #define DDRPHY_DX7GCR3_DSOEMODE_MASK (0xC0U) #define DDRPHY_DX7GCR3_DSOEMODE_SHIFT (6U) /*! DSOEMODE - Enables the OE mode values for DQS. */ #define DDRPHY_DX7GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSOEMODE_MASK) #define DDRPHY_DX7GCR3_WDSBVT_MASK (0x100U) #define DDRPHY_DX7GCR3_WDSBVT_SHIFT (8U) /*! WDSBVT - Write Data Strobe BDL VT Compensation */ #define DDRPHY_DX7GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDSBVT_SHIFT)) & DDRPHY_DX7GCR3_WDSBVT_MASK) #define DDRPHY_DX7GCR3_RESERVED_9_MASK (0x200U) #define DDRPHY_DX7GCR3_RESERVED_9_SHIFT (9U) /*! RESERVED_9 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX7GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX7GCR3_RESERVED_9_MASK) #define DDRPHY_DX7GCR3_DMPDRMODE_MASK (0xC00U) #define DDRPHY_DX7GCR3_DMPDRMODE_SHIFT (10U) /*! DMPDRMODE - Enables the PDR mode values for DM. */ #define DDRPHY_DX7GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX7GCR3_DMPDRMODE_MASK) #define DDRPHY_DX7GCR3_DMTEMODE_MASK (0x3000U) #define DDRPHY_DX7GCR3_DMTEMODE_SHIFT (12U) /*! DMTEMODE - Enables the TE mode values for DM. */ #define DDRPHY_DX7GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX7GCR3_DMTEMODE_MASK) #define DDRPHY_DX7GCR3_DMOEMODE_MASK (0xC000U) #define DDRPHY_DX7GCR3_DMOEMODE_SHIFT (14U) /*! DMOEMODE - Enables the OE mode values for DM. */ #define DDRPHY_DX7GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX7GCR3_DMOEMODE_MASK) #define DDRPHY_DX7GCR3_DSNPDRMODE_MASK (0x30000U) #define DDRPHY_DX7GCR3_DSNPDRMODE_SHIFT (16U) /*! DSNPDRMODE - Enables the PDR mode for DQS */ #define DDRPHY_DX7GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX7GCR3_DSNPDRMODE_MASK) #define DDRPHY_DX7GCR3_DSNTEMODE_MASK (0xC0000U) #define DDRPHY_DX7GCR3_DSNTEMODE_SHIFT (18U) /*! DSNTEMODE - Enables the TE mode for DQS */ #define DDRPHY_DX7GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSNTEMODE_MASK) #define DDRPHY_DX7GCR3_DSNOEMODE_MASK (0x300000U) #define DDRPHY_DX7GCR3_DSNOEMODE_SHIFT (20U) /*! DSNOEMODE - Enables the OE mode for DQs */ #define DDRPHY_DX7GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSNOEMODE_MASK) #define DDRPHY_DX7GCR3_PDRBVT_MASK (0x400000U) #define DDRPHY_DX7GCR3_PDRBVT_SHIFT (22U) /*! PDRBVT - Power Down Receiver BDL VT Compensation */ #define DDRPHY_DX7GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_PDRBVT_SHIFT)) & DDRPHY_DX7GCR3_PDRBVT_MASK) #define DDRPHY_DX7GCR3_RGSLVT_MASK (0x800000U) #define DDRPHY_DX7GCR3_RGSLVT_SHIFT (23U) /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation */ #define DDRPHY_DX7GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RGSLVT_SHIFT)) & DDRPHY_DX7GCR3_RGSLVT_MASK) #define DDRPHY_DX7GCR3_WLLVT_MASK (0x1000000U) #define DDRPHY_DX7GCR3_WLLVT_SHIFT (24U) /*! WLLVT - Write Leveling LCDL Delay VT Compensation */ #define DDRPHY_DX7GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WLLVT_SHIFT)) & DDRPHY_DX7GCR3_WLLVT_MASK) #define DDRPHY_DX7GCR3_WDLVT_MASK (0x2000000U) #define DDRPHY_DX7GCR3_WDLVT_SHIFT (25U) /*! WDLVT - Write DQ LCDL Delay VT Compensation */ #define DDRPHY_DX7GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDLVT_SHIFT)) & DDRPHY_DX7GCR3_WDLVT_MASK) #define DDRPHY_DX7GCR3_RDLVT_MASK (0x4000000U) #define DDRPHY_DX7GCR3_RDLVT_SHIFT (26U) /*! RDLVT - Read DQS LCDL Delay VT Compensation */ #define DDRPHY_DX7GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RDLVT_SHIFT)) & DDRPHY_DX7GCR3_RDLVT_MASK) #define DDRPHY_DX7GCR3_RGLVT_MASK (0x8000000U) #define DDRPHY_DX7GCR3_RGLVT_SHIFT (27U) /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation */ #define DDRPHY_DX7GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RGLVT_SHIFT)) & DDRPHY_DX7GCR3_RGLVT_MASK) #define DDRPHY_DX7GCR3_WDBVT_MASK (0x10000000U) #define DDRPHY_DX7GCR3_WDBVT_SHIFT (28U) /*! WDBVT - Write Data BDL VT Compensation */ #define DDRPHY_DX7GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDBVT_SHIFT)) & DDRPHY_DX7GCR3_WDBVT_MASK) #define DDRPHY_DX7GCR3_RDBVT_MASK (0x20000000U) #define DDRPHY_DX7GCR3_RDBVT_SHIFT (29U) /*! RDBVT - Read Data BDL VT Compensation */ #define DDRPHY_DX7GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RDBVT_SHIFT)) & DDRPHY_DX7GCR3_RDBVT_MASK) #define DDRPHY_DX7GCR3_TEBVT_MASK (0x40000000U) #define DDRPHY_DX7GCR3_TEBVT_SHIFT (30U) /*! TEBVT - Termination Enable BDL VT Compensation */ #define DDRPHY_DX7GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_TEBVT_SHIFT)) & DDRPHY_DX7GCR3_TEBVT_MASK) #define DDRPHY_DX7GCR3_OEBVT_MASK (0x80000000U) #define DDRPHY_DX7GCR3_OEBVT_SHIFT (31U) /*! OEBVT - Output Enable BDL VT Compensation */ #define DDRPHY_DX7GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_OEBVT_SHIFT)) & DDRPHY_DX7GCR3_OEBVT_MASK) /*! @} */ /*! @name DX7GCR4 - DATX8 n General Configuration Register 4 */ /*! @{ */ #define DDRPHY_DX7GCR4_DXREFIMON_MASK (0x3U) #define DDRPHY_DX7GCR4_DXREFIMON_SHIFT (0U) /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX7GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX7GCR4_DXREFIMON_MASK) #define DDRPHY_DX7GCR4_DXREFIEN_MASK (0x3CU) #define DDRPHY_DX7GCR4_DXREFIEN_SHIFT (2U) /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX7GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFIEN_MASK) #define DDRPHY_DX7GCR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7GCR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX7GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR4_RESERVED_7_6_MASK) #define DDRPHY_DX7GCR4_DXREFSSEL_MASK (0x7F00U) #define DDRPHY_DX7GCR4_DXREFSSEL_SHIFT (8U) /*! DXREFSSEL - Byte Lane Single-End VREF Select */ #define DDRPHY_DX7GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX7GCR4_DXREFSSEL_MASK) #define DDRPHY_DX7GCR4_DXREFSSELRANGE_MASK (0x8000U) #define DDRPHY_DX7GCR4_DXREFSSELRANGE_SHIFT (15U) /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select */ #define DDRPHY_DX7GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX7GCR4_DXREFSSELRANGE_MASK) #define DDRPHY_DX7GCR4_DXREFESEL_MASK (0x7F0000U) #define DDRPHY_DX7GCR4_DXREFESEL_SHIFT (16U) /*! DXREFESEL - Byte Lane External VREF Select */ #define DDRPHY_DX7GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX7GCR4_DXREFESEL_MASK) #define DDRPHY_DX7GCR4_DXREFESELRANGE_MASK (0x800000U) #define DDRPHY_DX7GCR4_DXREFESELRANGE_SHIFT (23U) /*! DXREFESELRANGE - External VREF generator REFSEL range select */ #define DDRPHY_DX7GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX7GCR4_DXREFESELRANGE_MASK) #define DDRPHY_DX7GCR4_RESERVED_24_MASK (0x1000000U) #define DDRPHY_DX7GCR4_RESERVED_24_SHIFT (24U) /*! RESERVED_24 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX7GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX7GCR4_RESERVED_24_MASK) #define DDRPHY_DX7GCR4_DXREFSEN_MASK (0x2000000U) #define DDRPHY_DX7GCR4_DXREFSEN_SHIFT (25U) /*! DXREFSEN - Byte Lane Single-End VREF Enable */ #define DDRPHY_DX7GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFSEN_MASK) #define DDRPHY_DX7GCR4_DXREFEEN_MASK (0xC000000U) #define DDRPHY_DX7GCR4_DXREFEEN_SHIFT (26U) /*! DXREFEEN - Byte Lane Internal VREF Enable */ #define DDRPHY_DX7GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFEEN_MASK) #define DDRPHY_DX7GCR4_DXREFPEN_MASK (0x10000000U) #define DDRPHY_DX7GCR4_DXREFPEN_SHIFT (28U) /*! DXREFPEN - Byte Lane VREF Pad Enable */ #define DDRPHY_DX7GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFPEN_MASK) #define DDRPHY_DX7GCR4_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DX7GCR4_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs) */ #define DDRPHY_DX7GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX7GCR4_RESERVED_31_29_MASK) /*! @} */ /*! @name DX7GCR5 - DATX8 n General Configuration Register 5 */ /*! @{ */ #define DDRPHY_DX7GCR5_DXREFISELR0_MASK (0x7FU) #define DDRPHY_DX7GCR5_DXREFISELR0_SHIFT (0U) /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0 */ #define DDRPHY_DX7GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR0_MASK) #define DDRPHY_DX7GCR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX7GCR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX7GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_7_MASK) #define DDRPHY_DX7GCR5_DXREFISELR1_MASK (0x7F00U) #define DDRPHY_DX7GCR5_DXREFISELR1_SHIFT (8U) /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1 */ #define DDRPHY_DX7GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR1_MASK) #define DDRPHY_DX7GCR5_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX7GCR5_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX7GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_15_MASK) #define DDRPHY_DX7GCR5_DXREFISELR2_MASK (0x7F0000U) #define DDRPHY_DX7GCR5_DXREFISELR2_SHIFT (16U) /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2 */ #define DDRPHY_DX7GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR2_MASK) #define DDRPHY_DX7GCR5_RESERVED_23_MASK (0x800000U) #define DDRPHY_DX7GCR5_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX7GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_23_MASK) #define DDRPHY_DX7GCR5_DXREFISELR3_MASK (0x7F000000U) #define DDRPHY_DX7GCR5_DXREFISELR3_SHIFT (24U) /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3 */ #define DDRPHY_DX7GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR3_MASK) #define DDRPHY_DX7GCR5_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX7GCR5_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX7GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_31_MASK) /*! @} */ /*! @name DX7GCR6 - DATX8 n General Configuration Register 6 */ /*! @{ */ #define DDRPHY_DX7GCR6_DXDQVREFR0_MASK (0x3FU) #define DDRPHY_DX7GCR6_DXDQVREFR0_SHIFT (0U) /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0 */ #define DDRPHY_DX7GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR0_MASK) #define DDRPHY_DX7GCR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7GCR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX7GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_7_6_MASK) #define DDRPHY_DX7GCR6_DXDQVREFR1_MASK (0x3F00U) #define DDRPHY_DX7GCR6_DXDQVREFR1_SHIFT (8U) /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1 */ #define DDRPHY_DX7GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR1_MASK) #define DDRPHY_DX7GCR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7GCR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX7GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_15_14_MASK) #define DDRPHY_DX7GCR6_DXDQVREFR2_MASK (0x3F0000U) #define DDRPHY_DX7GCR6_DXDQVREFR2_SHIFT (16U) /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2 */ #define DDRPHY_DX7GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR2_MASK) #define DDRPHY_DX7GCR6_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX7GCR6_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX7GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_23_22_MASK) #define DDRPHY_DX7GCR6_DXDQVREFR3_MASK (0x3F000000U) #define DDRPHY_DX7GCR6_DXDQVREFR3_SHIFT (24U) /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3 */ #define DDRPHY_DX7GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR3_MASK) #define DDRPHY_DX7GCR6_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX7GCR6_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX7GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_31_30_MASK) /*! @} */ /*! @name DX7GCR7 - DATX8 n General Configuration Register 7 */ /*! @{ */ #define DDRPHY_DX7GCR7_DCALSVAL_MASK (0x1FFU) #define DDRPHY_DX7GCR7_DCALSVAL_SHIFT (0U) /*! DCALSVAL - DDL Calibration Starting Value */ #define DDRPHY_DX7GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX7GCR7_DCALSVAL_MASK) #define DDRPHY_DX7GCR7_DCALTYPE_MASK (0x200U) #define DDRPHY_DX7GCR7_DCALTYPE_SHIFT (9U) /*! DCALTYPE - DDL Calibration Type */ #define DDRPHY_DX7GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX7GCR7_DCALTYPE_MASK) #define DDRPHY_DX7GCR7_RESERVED_17_10_MASK (0x3FC00U) #define DDRPHY_DX7GCR7_RESERVED_17_10_SHIFT (10U) /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX7GCR7_RESERVED_17_10_MASK) #define DDRPHY_DX7GCR7_RESERVED_18_MASK (0x40000U) #define DDRPHY_DX7GCR7_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX7GCR7_RESERVED_18_MASK) #define DDRPHY_DX7GCR7_RESERVED_31_19_MASK (0xFFF80000U) #define DDRPHY_DX7GCR7_RESERVED_31_19_SHIFT (19U) /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX7GCR7_RESERVED_31_19_MASK) /*! @} */ /*! @name DX7GCR8 - DATX8 n General Configuration Register 8 */ /*! @{ */ #define DDRPHY_DX7GCR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX7GCR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_5_0_MASK) #define DDRPHY_DX7GCR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7GCR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_7_6_MASK) #define DDRPHY_DX7GCR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX7GCR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_13_8_MASK) #define DDRPHY_DX7GCR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7GCR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_15_14_MASK) #define DDRPHY_DX7GCR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX7GCR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_21_16_MASK) #define DDRPHY_DX7GCR8_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX7GCR8_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_23_22_MASK) #define DDRPHY_DX7GCR8_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX7GCR8_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_29_24_MASK) #define DDRPHY_DX7GCR8_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX7GCR8_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_31_30_MASK) /*! @} */ /*! @name DX7GCR9 - DATX8 n General Configuration Register 9 */ /*! @{ */ #define DDRPHY_DX7GCR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX7GCR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_5_0_MASK) #define DDRPHY_DX7GCR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7GCR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_7_6_MASK) #define DDRPHY_DX7GCR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX7GCR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_13_8_MASK) #define DDRPHY_DX7GCR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7GCR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_15_14_MASK) #define DDRPHY_DX7GCR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX7GCR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_21_16_MASK) #define DDRPHY_DX7GCR9_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX7GCR9_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_23_22_MASK) #define DDRPHY_DX7GCR9_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX7GCR9_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_29_24_MASK) #define DDRPHY_DX7GCR9_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX7GCR9_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_31_30_MASK) /*! @} */ /*! @name DX7DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */ /*! @{ */ #define DDRPHY_DX7DQMAP0_DQ0MAP_MASK (0xFU) #define DDRPHY_DX7DQMAP0_DQ0MAP_SHIFT (0U) /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index */ #define DDRPHY_DX7DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ0MAP_MASK) #define DDRPHY_DX7DQMAP0_DQ1MAP_MASK (0xF0U) #define DDRPHY_DX7DQMAP0_DQ1MAP_SHIFT (4U) /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index */ #define DDRPHY_DX7DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ1MAP_MASK) #define DDRPHY_DX7DQMAP0_DQ2MAP_MASK (0xF00U) #define DDRPHY_DX7DQMAP0_DQ2MAP_SHIFT (8U) /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index */ #define DDRPHY_DX7DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ2MAP_MASK) #define DDRPHY_DX7DQMAP0_DQ3MAP_MASK (0xF000U) #define DDRPHY_DX7DQMAP0_DQ3MAP_SHIFT (12U) /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index */ #define DDRPHY_DX7DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ3MAP_MASK) #define DDRPHY_DX7DQMAP0_DQ4MAP_MASK (0xF0000U) #define DDRPHY_DX7DQMAP0_DQ4MAP_SHIFT (16U) /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index */ #define DDRPHY_DX7DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ4MAP_MASK) #define DDRPHY_DX7DQMAP0_RESERVED_30_20_MASK (0x7FF00000U) #define DDRPHY_DX7DQMAP0_RESERVED_30_20_SHIFT (20U) /*! RESERVED_30_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX7DQMAP0_RESERVED_30_20_MASK) #define DDRPHY_DX7DQMAP0_MAPOK_MASK (0x80000000U) #define DDRPHY_DX7DQMAP0_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX7DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX7DQMAP0_MAPOK_MASK) /*! @} */ /*! @name DX7DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */ /*! @{ */ #define DDRPHY_DX7DQMAP1_DQ5MAP_MASK (0xFU) #define DDRPHY_DX7DQMAP1_DQ5MAP_SHIFT (0U) /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index */ #define DDRPHY_DX7DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX7DQMAP1_DQ5MAP_MASK) #define DDRPHY_DX7DQMAP1_DQ6MAP_MASK (0xF0U) #define DDRPHY_DX7DQMAP1_DQ6MAP_SHIFT (4U) /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index */ #define DDRPHY_DX7DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX7DQMAP1_DQ6MAP_MASK) #define DDRPHY_DX7DQMAP1_DQ7MAP_MASK (0xF00U) #define DDRPHY_DX7DQMAP1_DQ7MAP_SHIFT (8U) /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index */ #define DDRPHY_DX7DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX7DQMAP1_DQ7MAP_MASK) #define DDRPHY_DX7DQMAP1_DMMAP_MASK (0xF000U) #define DDRPHY_DX7DQMAP1_DMMAP_SHIFT (12U) /*! DMMAP - DM bit DATX8 slice mapping index */ #define DDRPHY_DX7DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX7DQMAP1_DMMAP_MASK) #define DDRPHY_DX7DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U) #define DDRPHY_DX7DQMAP1_RESERVED_30_16_SHIFT (16U) /*! RESERVED_30_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX7DQMAP1_RESERVED_30_16_MASK) #define DDRPHY_DX7DQMAP1_MAPOK_MASK (0x80000000U) #define DDRPHY_DX7DQMAP1_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX7DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX7DQMAP1_MAPOK_MASK) /*! @} */ /*! @name DX7BDLR0 - DATX8 n Bit Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX7BDLR0_DQ0WBD_MASK (0x3FU) #define DDRPHY_DX7BDLR0_DQ0WBD_SHIFT (0U) /*! DQ0WBD - DQ0 Write Bit Delay */ #define DDRPHY_DX7BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ0WBD_MASK) #define DDRPHY_DX7BDLR0_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7BDLR0_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_7_6_MASK) #define DDRPHY_DX7BDLR0_DQ1WBD_MASK (0x3F00U) #define DDRPHY_DX7BDLR0_DQ1WBD_SHIFT (8U) /*! DQ1WBD - DQ1 Write Bit Delay */ #define DDRPHY_DX7BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ1WBD_MASK) #define DDRPHY_DX7BDLR0_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7BDLR0_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_15_14_MASK) #define DDRPHY_DX7BDLR0_DQ2WBD_MASK (0x3F0000U) #define DDRPHY_DX7BDLR0_DQ2WBD_SHIFT (16U) /*! DQ2WBD - DQ2 Write Bit Delay */ #define DDRPHY_DX7BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ2WBD_MASK) #define DDRPHY_DX7BDLR0_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX7BDLR0_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_23_22_MASK) #define DDRPHY_DX7BDLR0_DQ3WBD_MASK (0x3F000000U) #define DDRPHY_DX7BDLR0_DQ3WBD_SHIFT (24U) /*! DQ3WBD - DQ3 Write Bit Delay */ #define DDRPHY_DX7BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ3WBD_MASK) #define DDRPHY_DX7BDLR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX7BDLR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_31_30_MASK) /*! @} */ /*! @name DX7BDLR1 - DATX8 n Bit Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX7BDLR1_DQ4WBD_MASK (0x3FU) #define DDRPHY_DX7BDLR1_DQ4WBD_SHIFT (0U) /*! DQ4WBD - DQ4 Write Bit Delay */ #define DDRPHY_DX7BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ4WBD_MASK) #define DDRPHY_DX7BDLR1_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7BDLR1_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_7_6_MASK) #define DDRPHY_DX7BDLR1_DQ5WBD_MASK (0x3F00U) #define DDRPHY_DX7BDLR1_DQ5WBD_SHIFT (8U) /*! DQ5WBD - DQ5 Write Bit Delay */ #define DDRPHY_DX7BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ5WBD_MASK) #define DDRPHY_DX7BDLR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7BDLR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_15_14_MASK) #define DDRPHY_DX7BDLR1_DQ6WBD_MASK (0x3F0000U) #define DDRPHY_DX7BDLR1_DQ6WBD_SHIFT (16U) /*! DQ6WBD - DQ6 Write Bit Delay */ #define DDRPHY_DX7BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ6WBD_MASK) #define DDRPHY_DX7BDLR1_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX7BDLR1_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_23_22_MASK) #define DDRPHY_DX7BDLR1_DQ7WBD_MASK (0x3F000000U) #define DDRPHY_DX7BDLR1_DQ7WBD_SHIFT (24U) /*! DQ7WBD - DQ7 Write Bit Delay */ #define DDRPHY_DX7BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ7WBD_MASK) #define DDRPHY_DX7BDLR1_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX7BDLR1_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_31_30_MASK) /*! @} */ /*! @name DX7BDLR2 - DATX8 n Bit Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX7BDLR2_DMWBD_MASK (0x3FU) #define DDRPHY_DX7BDLR2_DMWBD_SHIFT (0U) /*! DMWBD - DM Write Bit Delay */ #define DDRPHY_DX7BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DMWBD_SHIFT)) & DDRPHY_DX7BDLR2_DMWBD_MASK) #define DDRPHY_DX7BDLR2_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7BDLR2_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_7_6_MASK) #define DDRPHY_DX7BDLR2_DSWBD_MASK (0x3F00U) #define DDRPHY_DX7BDLR2_DSWBD_SHIFT (8U) /*! DSWBD - DQS Write Bit Delay */ #define DDRPHY_DX7BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DSWBD_SHIFT)) & DDRPHY_DX7BDLR2_DSWBD_MASK) #define DDRPHY_DX7BDLR2_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7BDLR2_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_15_14_MASK) #define DDRPHY_DX7BDLR2_DSOEBD_MASK (0x3F0000U) #define DDRPHY_DX7BDLR2_DSOEBD_SHIFT (16U) /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay */ #define DDRPHY_DX7BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX7BDLR2_DSOEBD_MASK) #define DDRPHY_DX7BDLR2_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX7BDLR2_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_23_22_MASK) #define DDRPHY_DX7BDLR2_DSNWBD_MASK (0x3F000000U) #define DDRPHY_DX7BDLR2_DSNWBD_SHIFT (24U) /*! DSNWBD - DQSN Write Bit Delay */ #define DDRPHY_DX7BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX7BDLR2_DSNWBD_MASK) #define DDRPHY_DX7BDLR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX7BDLR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_31_30_MASK) /*! @} */ /*! @name DX7BDLR3 - DATX8 n Bit Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX7BDLR3_DQ0RBD_MASK (0x3FU) #define DDRPHY_DX7BDLR3_DQ0RBD_SHIFT (0U) /*! DQ0RBD - DQ0 Read Bit Delay */ #define DDRPHY_DX7BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ0RBD_MASK) #define DDRPHY_DX7BDLR3_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7BDLR3_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_7_6_MASK) #define DDRPHY_DX7BDLR3_DQ1RBD_MASK (0x3F00U) #define DDRPHY_DX7BDLR3_DQ1RBD_SHIFT (8U) /*! DQ1RBD - DQ1 Read Bit Delay */ #define DDRPHY_DX7BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ1RBD_MASK) #define DDRPHY_DX7BDLR3_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7BDLR3_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_15_14_MASK) #define DDRPHY_DX7BDLR3_DQ2RBD_MASK (0x3F0000U) #define DDRPHY_DX7BDLR3_DQ2RBD_SHIFT (16U) /*! DQ2RBD - DQ2 Read Bit Delay */ #define DDRPHY_DX7BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ2RBD_MASK) #define DDRPHY_DX7BDLR3_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX7BDLR3_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_23_22_MASK) #define DDRPHY_DX7BDLR3_DQ3RBD_MASK (0x3F000000U) #define DDRPHY_DX7BDLR3_DQ3RBD_SHIFT (24U) /*! DQ3RBD - DQ3 Read Bit Delay */ #define DDRPHY_DX7BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ3RBD_MASK) #define DDRPHY_DX7BDLR3_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX7BDLR3_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_31_30_MASK) /*! @} */ /*! @name DX7BDLR4 - DATX8 n Bit Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX7BDLR4_DQ4RBD_MASK (0x3FU) #define DDRPHY_DX7BDLR4_DQ4RBD_SHIFT (0U) /*! DQ4RBD - DQ4 Read Bit Delay */ #define DDRPHY_DX7BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ4RBD_MASK) #define DDRPHY_DX7BDLR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7BDLR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_7_6_MASK) #define DDRPHY_DX7BDLR4_DQ5RBD_MASK (0x3F00U) #define DDRPHY_DX7BDLR4_DQ5RBD_SHIFT (8U) /*! DQ5RBD - DQ5 Read Bit Delay */ #define DDRPHY_DX7BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ5RBD_MASK) #define DDRPHY_DX7BDLR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7BDLR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_15_14_MASK) #define DDRPHY_DX7BDLR4_DQ6RBD_MASK (0x3F0000U) #define DDRPHY_DX7BDLR4_DQ6RBD_SHIFT (16U) /*! DQ6RBD - DQ6 Read Bit Delay */ #define DDRPHY_DX7BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ6RBD_MASK) #define DDRPHY_DX7BDLR4_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX7BDLR4_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_23_22_MASK) #define DDRPHY_DX7BDLR4_DQ7RBD_MASK (0x3F000000U) #define DDRPHY_DX7BDLR4_DQ7RBD_SHIFT (24U) /*! DQ7RBD - DQ7 Read Bit Delay */ #define DDRPHY_DX7BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ7RBD_MASK) #define DDRPHY_DX7BDLR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX7BDLR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_31_30_MASK) /*! @} */ /*! @name DX7BDLR5 - DATX8 n Bit Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX7BDLR5_DMRBD_MASK (0x3FU) #define DDRPHY_DX7BDLR5_DMRBD_SHIFT (0U) /*! DMRBD - DM Read Bit Delay */ #define DDRPHY_DX7BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR5_DMRBD_SHIFT)) & DDRPHY_DX7BDLR5_DMRBD_MASK) #define DDRPHY_DX7BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U) #define DDRPHY_DX7BDLR5_RESERVED_31_6_SHIFT (6U) /*! RESERVED_31_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX7BDLR5_RESERVED_31_6_MASK) /*! @} */ /*! @name DX7BDLR6 - DATX8 n Bit Delay Line Register 6 */ /*! @{ */ #define DDRPHY_DX7BDLR6_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_DX7BDLR6_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX7BDLR6_RESERVED_7_0_MASK) #define DDRPHY_DX7BDLR6_PDRBD_MASK (0x3F00U) #define DDRPHY_DX7BDLR6_PDRBD_SHIFT (8U) /*! PDRBD - Power down receiver Bit Delay */ #define DDRPHY_DX7BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_PDRBD_SHIFT)) & DDRPHY_DX7BDLR6_PDRBD_MASK) #define DDRPHY_DX7BDLR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7BDLR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR6_RESERVED_15_14_MASK) #define DDRPHY_DX7BDLR6_TERBD_MASK (0x3F0000U) #define DDRPHY_DX7BDLR6_TERBD_SHIFT (16U) /*! TERBD - Termination Enable Bit Delay */ #define DDRPHY_DX7BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_TERBD_SHIFT)) & DDRPHY_DX7BDLR6_TERBD_MASK) #define DDRPHY_DX7BDLR6_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX7BDLR6_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR6_RESERVED_31_22_MASK) /*! @} */ /*! @name DX7BDLR7 - DATX8 n Bit Delay Line Register 7 */ /*! @{ */ #define DDRPHY_DX7BDLR7_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX7BDLR7_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_5_0_MASK) #define DDRPHY_DX7BDLR7_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7BDLR7_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_7_6_MASK) #define DDRPHY_DX7BDLR7_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX7BDLR7_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_13_8_MASK) #define DDRPHY_DX7BDLR7_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7BDLR7_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_15_14_MASK) #define DDRPHY_DX7BDLR7_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX7BDLR7_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_21_16_MASK) #define DDRPHY_DX7BDLR7_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX7BDLR7_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_31_22_MASK) /*! @} */ /*! @name DX7BDLR8 - DATX8 n Bit Delay Line Register 8 */ /*! @{ */ #define DDRPHY_DX7BDLR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX7BDLR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_5_0_MASK) #define DDRPHY_DX7BDLR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7BDLR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_7_6_MASK) #define DDRPHY_DX7BDLR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX7BDLR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_13_8_MASK) #define DDRPHY_DX7BDLR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7BDLR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_15_14_MASK) #define DDRPHY_DX7BDLR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX7BDLR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_21_16_MASK) #define DDRPHY_DX7BDLR8_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX7BDLR8_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_31_22_MASK) /*! @} */ /*! @name DX7BDLR9 - DATX8 n Bit Delay Line Register 9 */ /*! @{ */ #define DDRPHY_DX7BDLR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX7BDLR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_5_0_MASK) #define DDRPHY_DX7BDLR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX7BDLR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_7_6_MASK) #define DDRPHY_DX7BDLR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX7BDLR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_13_8_MASK) #define DDRPHY_DX7BDLR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX7BDLR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_15_14_MASK) #define DDRPHY_DX7BDLR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX7BDLR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_21_16_MASK) #define DDRPHY_DX7BDLR9_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX7BDLR9_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_31_22_MASK) /*! @} */ /*! @name DX7LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX7LCDLR0_WLD_MASK (0x1FFU) #define DDRPHY_DX7LCDLR0_WLD_SHIFT (0U) /*! WLD - Write Leveling Delay */ #define DDRPHY_DX7LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_WLD_SHIFT)) & DDRPHY_DX7LCDLR0_WLD_MASK) #define DDRPHY_DX7LCDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX7LCDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX7LCDLR0_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX7LCDLR0_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR0_RESERVED_24_16_MASK) #define DDRPHY_DX7LCDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX7LCDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX7LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX7LCDLR1_WDQD_MASK (0x1FFU) #define DDRPHY_DX7LCDLR1_WDQD_SHIFT (0U) /*! WDQD - Write Data Delay */ #define DDRPHY_DX7LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_WDQD_SHIFT)) & DDRPHY_DX7LCDLR1_WDQD_MASK) #define DDRPHY_DX7LCDLR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX7LCDLR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR1_RESERVED_15_9_MASK) #define DDRPHY_DX7LCDLR1_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX7LCDLR1_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR1_RESERVED_24_16_MASK) #define DDRPHY_DX7LCDLR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX7LCDLR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX7LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX7LCDLR2_DQSGD_MASK (0x1FFU) #define DDRPHY_DX7LCDLR2_DQSGD_SHIFT (0U) /*! DQSGD - Read DQS Gating Delay */ #define DDRPHY_DX7LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX7LCDLR2_DQSGD_MASK) #define DDRPHY_DX7LCDLR2_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX7LCDLR2_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR2_RESERVED_15_9_MASK) #define DDRPHY_DX7LCDLR2_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX7LCDLR2_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR2_RESERVED_24_16_MASK) #define DDRPHY_DX7LCDLR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX7LCDLR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR2_RESERVED_31_25_MASK) /*! @} */ /*! @name DX7LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX7LCDLR3_RDQSD_MASK (0x1FFU) #define DDRPHY_DX7LCDLR3_RDQSD_SHIFT (0U) /*! RDQSD - Read DQS Delay */ #define DDRPHY_DX7LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX7LCDLR3_RDQSD_MASK) #define DDRPHY_DX7LCDLR3_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX7LCDLR3_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR3_RESERVED_15_9_MASK) #define DDRPHY_DX7LCDLR3_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX7LCDLR3_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR3_RESERVED_24_16_MASK) #define DDRPHY_DX7LCDLR3_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX7LCDLR3_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR3_RESERVED_31_25_MASK) /*! @} */ /*! @name DX7LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX7LCDLR4_RDQSND_MASK (0x1FFU) #define DDRPHY_DX7LCDLR4_RDQSND_SHIFT (0U) /*! RDQSND - Read DQSN Delay */ #define DDRPHY_DX7LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX7LCDLR4_RDQSND_MASK) #define DDRPHY_DX7LCDLR4_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX7LCDLR4_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR4_RESERVED_15_9_MASK) #define DDRPHY_DX7LCDLR4_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX7LCDLR4_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR4_RESERVED_24_16_MASK) #define DDRPHY_DX7LCDLR4_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX7LCDLR4_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR4_RESERVED_31_25_MASK) /*! @} */ /*! @name DX7LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX7LCDLR5_DQSGSD_MASK (0x1FFU) #define DDRPHY_DX7LCDLR5_DQSGSD_SHIFT (0U) /*! DQSGSD - DQS Gating Status Delay */ #define DDRPHY_DX7LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX7LCDLR5_DQSGSD_MASK) #define DDRPHY_DX7LCDLR5_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX7LCDLR5_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR5_RESERVED_15_9_MASK) #define DDRPHY_DX7LCDLR5_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX7LCDLR5_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR5_RESERVED_24_16_MASK) #define DDRPHY_DX7LCDLR5_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX7LCDLR5_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR5_RESERVED_31_25_MASK) /*! @} */ /*! @name DX7MDLR0 - DATX8 n Master Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX7MDLR0_IPRD_MASK (0x1FFU) #define DDRPHY_DX7MDLR0_IPRD_SHIFT (0U) /*! IPRD - Initial Period */ #define DDRPHY_DX7MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_IPRD_SHIFT)) & DDRPHY_DX7MDLR0_IPRD_MASK) #define DDRPHY_DX7MDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX7MDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX7MDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX7MDLR0_TPRD_MASK (0x1FF0000U) #define DDRPHY_DX7MDLR0_TPRD_SHIFT (16U) /*! TPRD - Target Period */ #define DDRPHY_DX7MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_TPRD_SHIFT)) & DDRPHY_DX7MDLR0_TPRD_MASK) #define DDRPHY_DX7MDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX7MDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX7MDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX7MDLR1 - DATX8 n Master Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX7MDLR1_MDLD_MASK (0x1FFU) #define DDRPHY_DX7MDLR1_MDLD_SHIFT (0U) /*! MDLD - MDL Delay */ #define DDRPHY_DX7MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR1_MDLD_SHIFT)) & DDRPHY_DX7MDLR1_MDLD_MASK) #define DDRPHY_DX7MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U) #define DDRPHY_DX7MDLR1_RESERVED_31_9_SHIFT (9U) /*! RESERVED_31_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX7MDLR1_RESERVED_31_9_MASK) /*! @} */ /*! @name DX7GTR0 - DATX8 n General Timing Register 0 */ /*! @{ */ #define DDRPHY_DX7GTR0_DGSL_MASK (0x1FU) #define DDRPHY_DX7GTR0_DGSL_SHIFT (0U) /*! DGSL - DQS Gating System Latency */ #define DDRPHY_DX7GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_DGSL_SHIFT)) & DDRPHY_DX7GTR0_DGSL_MASK) #define DDRPHY_DX7GTR0_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DX7GTR0_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_7_5_MASK) #define DDRPHY_DX7GTR0_RESERVED_12_8_MASK (0x1F00U) #define DDRPHY_DX7GTR0_RESERVED_12_8_SHIFT (8U) /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_12_8_MASK) #define DDRPHY_DX7GTR0_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_DX7GTR0_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_15_13_MASK) #define DDRPHY_DX7GTR0_WLSL_MASK (0xF0000U) #define DDRPHY_DX7GTR0_WLSL_SHIFT (16U) /*! WLSL - Write Leveling System Latency */ #define DDRPHY_DX7GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_WLSL_SHIFT)) & DDRPHY_DX7GTR0_WLSL_MASK) #define DDRPHY_DX7GTR0_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX7GTR0_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX7GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_23_20_MASK) #define DDRPHY_DX7GTR0_WDQSL_MASK (0x7000000U) #define DDRPHY_DX7GTR0_WDQSL_SHIFT (24U) /*! WDQSL - DQ Write Path Latency Pipeline */ #define DDRPHY_DX7GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_WDQSL_SHIFT)) & DDRPHY_DX7GTR0_WDQSL_MASK) #define DDRPHY_DX7GTR0_RESERVED_31_24_MASK (0xF8000000U) #define DDRPHY_DX7GTR0_RESERVED_31_24_SHIFT (27U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_31_24_MASK) /*! @} */ /*! @name DX7RSR0 - DATX8 n Rank Status Register 0 */ /*! @{ */ #define DDRPHY_DX7RSR0_QSGERR_MASK (0xFFFFU) #define DDRPHY_DX7RSR0_QSGERR_SHIFT (0U) /*! QSGERR - DQS Gate Training Error */ #define DDRPHY_DX7RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR0_QSGERR_SHIFT)) & DDRPHY_DX7RSR0_QSGERR_MASK) #define DDRPHY_DX7RSR0_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX7RSR0_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR0_RESERVED_31_16_MASK) /*! @} */ /*! @name DX7RSR1 - DATX8 n Rank Status Register 1 */ /*! @{ */ #define DDRPHY_DX7RSR1_RDLVLERR_MASK (0xFFFFU) #define DDRPHY_DX7RSR1_RDLVLERR_SHIFT (0U) /*! RDLVLERR - Read Leveling Error */ #define DDRPHY_DX7RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX7RSR1_RDLVLERR_MASK) #define DDRPHY_DX7RSR1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX7RSR1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR1_RESERVED_31_16_MASK) /*! @} */ /*! @name DX7RSR2 - DATX8 n Rank Status Register 2 */ /*! @{ */ #define DDRPHY_DX7RSR2_WLAWN_MASK (0xFFFFU) #define DDRPHY_DX7RSR2_WLAWN_SHIFT (0U) /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning */ #define DDRPHY_DX7RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR2_WLAWN_SHIFT)) & DDRPHY_DX7RSR2_WLAWN_MASK) #define DDRPHY_DX7RSR2_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX7RSR2_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR2_RESERVED_31_16_MASK) /*! @} */ /*! @name DX7RSR3 - DATX8 n Rank Status Register 3 */ /*! @{ */ #define DDRPHY_DX7RSR3_WLAERR_MASK (0xFFFFU) #define DDRPHY_DX7RSR3_WLAERR_SHIFT (0U) /*! WLAERR - Write Leveling Adjustment Error */ #define DDRPHY_DX7RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR3_WLAERR_SHIFT)) & DDRPHY_DX7RSR3_WLAERR_MASK) #define DDRPHY_DX7RSR3_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX7RSR3_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR3_RESERVED_31_16_MASK) /*! @} */ /*! @name DX7GSR0 - DATX8 n General Status Register 0 */ /*! @{ */ #define DDRPHY_DX7GSR0_WDQCAL_MASK (0x1U) #define DDRPHY_DX7GSR0_WDQCAL_SHIFT (0U) /*! WDQCAL - Write DQ Calibration */ #define DDRPHY_DX7GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WDQCAL_SHIFT)) & DDRPHY_DX7GSR0_WDQCAL_MASK) #define DDRPHY_DX7GSR0_RDQSCAL_MASK (0x2U) #define DDRPHY_DX7GSR0_RDQSCAL_SHIFT (1U) /*! RDQSCAL - Read DQS Calibration */ #define DDRPHY_DX7GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX7GSR0_RDQSCAL_MASK) #define DDRPHY_DX7GSR0_RDQSNCAL_MASK (0x4U) #define DDRPHY_DX7GSR0_RDQSNCAL_SHIFT (2U) /*! RDQSNCAL - Read DQS# Calibration */ #define DDRPHY_DX7GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX7GSR0_RDQSNCAL_MASK) #define DDRPHY_DX7GSR0_GDQSCAL_MASK (0x8U) #define DDRPHY_DX7GSR0_GDQSCAL_SHIFT (3U) /*! GDQSCAL - Read DQS gating Calibration */ #define DDRPHY_DX7GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX7GSR0_GDQSCAL_MASK) #define DDRPHY_DX7GSR0_WLCAL_MASK (0x10U) #define DDRPHY_DX7GSR0_WLCAL_SHIFT (4U) /*! WLCAL - Write Leveling Calibration */ #define DDRPHY_DX7GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLCAL_SHIFT)) & DDRPHY_DX7GSR0_WLCAL_MASK) #define DDRPHY_DX7GSR0_WLDONE_MASK (0x20U) #define DDRPHY_DX7GSR0_WLDONE_SHIFT (5U) /*! WLDONE - Write Leveling Done */ #define DDRPHY_DX7GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLDONE_SHIFT)) & DDRPHY_DX7GSR0_WLDONE_MASK) #define DDRPHY_DX7GSR0_WLERR_MASK (0x40U) #define DDRPHY_DX7GSR0_WLERR_SHIFT (6U) /*! WLERR - Write Leveling Error */ #define DDRPHY_DX7GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLERR_SHIFT)) & DDRPHY_DX7GSR0_WLERR_MASK) #define DDRPHY_DX7GSR0_WLPRD_MASK (0xFF80U) #define DDRPHY_DX7GSR0_WLPRD_SHIFT (7U) /*! WLPRD - Write Leveling Period */ #define DDRPHY_DX7GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLPRD_SHIFT)) & DDRPHY_DX7GSR0_WLPRD_MASK) #define DDRPHY_DX7GSR0_DPLOCK_MASK (0x10000U) #define DDRPHY_DX7GSR0_DPLOCK_SHIFT (16U) /*! DPLOCK - DATX8 PLL Lock */ #define DDRPHY_DX7GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_DPLOCK_SHIFT)) & DDRPHY_DX7GSR0_DPLOCK_MASK) #define DDRPHY_DX7GSR0_GDQSPRD_MASK (0x3FE0000U) #define DDRPHY_DX7GSR0_GDQSPRD_SHIFT (17U) /*! GDQSPRD - Read DQS gating Period */ #define DDRPHY_DX7GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX7GSR0_GDQSPRD_MASK) #define DDRPHY_DX7GSR0_RESERVED_29_26_MASK (0x3C000000U) #define DDRPHY_DX7GSR0_RESERVED_29_26_SHIFT (26U) /*! RESERVED_29_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX7GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX7GSR0_RESERVED_29_26_MASK) #define DDRPHY_DX7GSR0_WLDQ_MASK (0x40000000U) #define DDRPHY_DX7GSR0_WLDQ_SHIFT (30U) /*! WLDQ - Write Leveling DQ Status */ #define DDRPHY_DX7GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLDQ_SHIFT)) & DDRPHY_DX7GSR0_WLDQ_MASK) #define DDRPHY_DX7GSR0_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX7GSR0_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX7GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX7GSR0_RESERVED_31_MASK) /*! @} */ /*! @name DX7GSR1 - DATX8 n General Status Register 1 */ /*! @{ */ #define DDRPHY_DX7GSR1_DLTDONE_MASK (0x1U) #define DDRPHY_DX7GSR1_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done */ #define DDRPHY_DX7GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR1_DLTDONE_SHIFT)) & DDRPHY_DX7GSR1_DLTDONE_MASK) #define DDRPHY_DX7GSR1_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_DX7GSR1_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code */ #define DDRPHY_DX7GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR1_DLTCODE_SHIFT)) & DDRPHY_DX7GSR1_DLTCODE_MASK) #define DDRPHY_DX7GSR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX7GSR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX7GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX7GSR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX7GSR2 - DATX8 n General Status Register 2 */ /*! @{ */ #define DDRPHY_DX7GSR2_RDERR_MASK (0x1U) #define DDRPHY_DX7GSR2_RDERR_SHIFT (0U) /*! RDERR - Read Bit Deskew Error */ #define DDRPHY_DX7GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_RDERR_SHIFT)) & DDRPHY_DX7GSR2_RDERR_MASK) #define DDRPHY_DX7GSR2_RDWN_MASK (0x2U) #define DDRPHY_DX7GSR2_RDWN_SHIFT (1U) /*! RDWN - Read Bit Deskew Warning */ #define DDRPHY_DX7GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_RDWN_SHIFT)) & DDRPHY_DX7GSR2_RDWN_MASK) #define DDRPHY_DX7GSR2_WDERR_MASK (0x4U) #define DDRPHY_DX7GSR2_WDERR_SHIFT (2U) /*! WDERR - Write Bit Deskew Error */ #define DDRPHY_DX7GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WDERR_SHIFT)) & DDRPHY_DX7GSR2_WDERR_MASK) #define DDRPHY_DX7GSR2_WDWN_MASK (0x8U) #define DDRPHY_DX7GSR2_WDWN_SHIFT (3U) /*! WDWN - Write Bit Deskew Warning */ #define DDRPHY_DX7GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WDWN_SHIFT)) & DDRPHY_DX7GSR2_WDWN_MASK) #define DDRPHY_DX7GSR2_REERR_MASK (0x10U) #define DDRPHY_DX7GSR2_REERR_SHIFT (4U) /*! REERR - Read Eye Centering Error */ #define DDRPHY_DX7GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_REERR_SHIFT)) & DDRPHY_DX7GSR2_REERR_MASK) #define DDRPHY_DX7GSR2_REWN_MASK (0x20U) #define DDRPHY_DX7GSR2_REWN_SHIFT (5U) /*! REWN - Read Eye Centering Warning */ #define DDRPHY_DX7GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_REWN_SHIFT)) & DDRPHY_DX7GSR2_REWN_MASK) #define DDRPHY_DX7GSR2_WEERR_MASK (0x40U) #define DDRPHY_DX7GSR2_WEERR_SHIFT (6U) /*! WEERR - Write Eye Centering Error */ #define DDRPHY_DX7GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WEERR_SHIFT)) & DDRPHY_DX7GSR2_WEERR_MASK) #define DDRPHY_DX7GSR2_WEWN_MASK (0x80U) #define DDRPHY_DX7GSR2_WEWN_SHIFT (7U) /*! WEWN - Write Eye Centering Warning */ #define DDRPHY_DX7GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WEWN_SHIFT)) & DDRPHY_DX7GSR2_WEWN_MASK) #define DDRPHY_DX7GSR2_ESTAT_MASK (0xF00U) #define DDRPHY_DX7GSR2_ESTAT_SHIFT (8U) /*! ESTAT - Error Status */ #define DDRPHY_DX7GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_ESTAT_SHIFT)) & DDRPHY_DX7GSR2_ESTAT_MASK) #define DDRPHY_DX7GSR2_DQS2DQERR_MASK (0xFF000U) #define DDRPHY_DX7GSR2_DQS2DQERR_SHIFT (12U) /*! DQS2DQERR - Write DQS2DQ Training Error */ #define DDRPHY_DX7GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX7GSR2_DQS2DQERR_MASK) #define DDRPHY_DX7GSR2_SRDERR_MASK (0x100000U) #define DDRPHY_DX7GSR2_SRDERR_SHIFT (20U) /*! SRDERR - Static Read Error */ #define DDRPHY_DX7GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_SRDERR_SHIFT)) & DDRPHY_DX7GSR2_SRDERR_MASK) #define DDRPHY_DX7GSR2_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX7GSR2_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX7GSR2_RESERVED_21_MASK) #define DDRPHY_DX7GSR2_GSDQSCAL_MASK (0x400000U) #define DDRPHY_DX7GSR2_GSDQSCAL_SHIFT (22U) /*! GSDQSCAL - Read DQS Gating Status Calibration */ #define DDRPHY_DX7GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX7GSR2_GSDQSCAL_MASK) #define DDRPHY_DX7GSR2_GSDQSPRD_MASK (0xFF800000U) #define DDRPHY_DX7GSR2_GSDQSPRD_SHIFT (23U) /*! GSDQSPRD - Read DQS gating Status Period */ #define DDRPHY_DX7GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX7GSR2_GSDQSPRD_MASK) /*! @} */ /*! @name DX7GSR3 - DATX8 n General Status Register 3 */ /*! @{ */ #define DDRPHY_DX7GSR3_SRDPC_MASK (0x3U) #define DDRPHY_DX7GSR3_SRDPC_SHIFT (0U) /*! SRDPC - Static Read Delay Pass Count */ #define DDRPHY_DX7GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_SRDPC_SHIFT)) & DDRPHY_DX7GSR3_SRDPC_MASK) #define DDRPHY_DX7GSR3_RESERVED_7_2_MASK (0xFCU) #define DDRPHY_DX7GSR3_RESERVED_7_2_SHIFT (2U) /*! RESERVED_7_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX7GSR3_RESERVED_7_2_MASK) #define DDRPHY_DX7GSR3_HVERR_MASK (0xF00U) #define DDRPHY_DX7GSR3_HVERR_SHIFT (8U) /*! HVERR - Host VREF Training Error */ #define DDRPHY_DX7GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_HVERR_SHIFT)) & DDRPHY_DX7GSR3_HVERR_MASK) #define DDRPHY_DX7GSR3_HVWRN_MASK (0xF000U) #define DDRPHY_DX7GSR3_HVWRN_SHIFT (12U) /*! HVWRN - Host VREF Training Warning */ #define DDRPHY_DX7GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_HVWRN_SHIFT)) & DDRPHY_DX7GSR3_HVWRN_MASK) #define DDRPHY_DX7GSR3_DVERR_MASK (0xF0000U) #define DDRPHY_DX7GSR3_DVERR_SHIFT (16U) /*! DVERR - DRAM VREF Training Error */ #define DDRPHY_DX7GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_DVERR_SHIFT)) & DDRPHY_DX7GSR3_DVERR_MASK) #define DDRPHY_DX7GSR3_DVWRN_MASK (0xF00000U) #define DDRPHY_DX7GSR3_DVWRN_SHIFT (20U) /*! DVWRN - DRAM VREF Training Warning */ #define DDRPHY_DX7GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_DVWRN_SHIFT)) & DDRPHY_DX7GSR3_DVWRN_MASK) #define DDRPHY_DX7GSR3_ESTAT_MASK (0x7000000U) #define DDRPHY_DX7GSR3_ESTAT_SHIFT (24U) /*! ESTAT - VREF Training Error Status Code */ #define DDRPHY_DX7GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_ESTAT_SHIFT)) & DDRPHY_DX7GSR3_ESTAT_MASK) #define DDRPHY_DX7GSR3_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX7GSR3_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX7GSR3_RESERVED_31_27_MASK) /*! @} */ /*! @name DX7GSR4 - DATX8 n General Status Register 4 */ /*! @{ */ #define DDRPHY_DX7GSR4_RESERVED_0_MASK (0x1U) #define DDRPHY_DX7GSR4_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_0_MASK) #define DDRPHY_DX7GSR4_RESERVED_1_MASK (0x2U) #define DDRPHY_DX7GSR4_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_1_MASK) #define DDRPHY_DX7GSR4_RESERVED_2_MASK (0x4U) #define DDRPHY_DX7GSR4_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_2_MASK) #define DDRPHY_DX7GSR4_RESERVED_3_MASK (0x8U) #define DDRPHY_DX7GSR4_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_3_MASK) #define DDRPHY_DX7GSR4_RESERVED_4_MASK (0x10U) #define DDRPHY_DX7GSR4_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_4_MASK) #define DDRPHY_DX7GSR4_RESERVED_5_MASK (0x20U) #define DDRPHY_DX7GSR4_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_5_MASK) #define DDRPHY_DX7GSR4_RESERVED_6_MASK (0x40U) #define DDRPHY_DX7GSR4_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_6_MASK) #define DDRPHY_DX7GSR4_RESERVED_15_7_MASK (0xFF80U) #define DDRPHY_DX7GSR4_RESERVED_15_7_SHIFT (7U) /*! RESERVED_15_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_15_7_MASK) #define DDRPHY_DX7GSR4_RESERVED_16_MASK (0x10000U) #define DDRPHY_DX7GSR4_RESERVED_16_SHIFT (16U) /*! RESERVED_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_16_MASK) #define DDRPHY_DX7GSR4_RESERVED_25_17_MASK (0x3FE0000U) #define DDRPHY_DX7GSR4_RESERVED_25_17_SHIFT (17U) /*! RESERVED_25_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_25_17_MASK) #define DDRPHY_DX7GSR4_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_DX7GSR4_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX7GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_31_26_MASK) /*! @} */ /*! @name DX7GSR5 - DATX8 n General Status Register 5 */ /*! @{ */ #define DDRPHY_DX7GSR5_RESERVED_0_MASK (0x1U) #define DDRPHY_DX7GSR5_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_0_MASK) #define DDRPHY_DX7GSR5_RESERVED_1_MASK (0x2U) #define DDRPHY_DX7GSR5_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_1_MASK) #define DDRPHY_DX7GSR5_RESERVED_2_MASK (0x4U) #define DDRPHY_DX7GSR5_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_2_MASK) #define DDRPHY_DX7GSR5_RESERVED_3_MASK (0x8U) #define DDRPHY_DX7GSR5_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_3_MASK) #define DDRPHY_DX7GSR5_RESERVED_4_MASK (0x10U) #define DDRPHY_DX7GSR5_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_4_MASK) #define DDRPHY_DX7GSR5_RESERVED_5_MASK (0x20U) #define DDRPHY_DX7GSR5_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_5_MASK) #define DDRPHY_DX7GSR5_RESERVED_6_MASK (0x40U) #define DDRPHY_DX7GSR5_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_6_MASK) #define DDRPHY_DX7GSR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX7GSR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_7_MASK) #define DDRPHY_DX7GSR5_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX7GSR5_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_11_8_MASK) #define DDRPHY_DX7GSR5_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_DX7GSR5_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_19_12_MASK) #define DDRPHY_DX7GSR5_RESERVED_20_MASK (0x100000U) #define DDRPHY_DX7GSR5_RESERVED_20_SHIFT (20U) /*! RESERVED_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_20_MASK) #define DDRPHY_DX7GSR5_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX7GSR5_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_21_MASK) #define DDRPHY_DX7GSR5_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX7GSR5_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_22_MASK) #define DDRPHY_DX7GSR5_RESERVED_31_23_MASK (0xFF800000U) #define DDRPHY_DX7GSR5_RESERVED_31_23_SHIFT (23U) /*! RESERVED_31_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_31_23_MASK) /*! @} */ /*! @name DX7GSR6 - DATX8 n General Status Register 6 */ /*! @{ */ #define DDRPHY_DX7GSR6_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX7GSR6_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_1_0_MASK) #define DDRPHY_DX7GSR6_RESERVED_3_2_MASK (0xCU) #define DDRPHY_DX7GSR6_RESERVED_3_2_SHIFT (2U) /*! RESERVED_3_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_3_2_MASK) #define DDRPHY_DX7GSR6_RESERVED_7_4_MASK (0xF0U) #define DDRPHY_DX7GSR6_RESERVED_7_4_SHIFT (4U) /*! RESERVED_7_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_7_4_MASK) #define DDRPHY_DX7GSR6_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX7GSR6_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_11_8_MASK) #define DDRPHY_DX7GSR6_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_DX7GSR6_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_15_12_MASK) #define DDRPHY_DX7GSR6_RESERVED_19_15_MASK (0xF0000U) #define DDRPHY_DX7GSR6_RESERVED_19_15_SHIFT (16U) /*! RESERVED_19_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_19_15_MASK) #define DDRPHY_DX7GSR6_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX7GSR6_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_23_20_MASK) #define DDRPHY_DX7GSR6_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX7GSR6_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX7GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8GCR0 - DATX8 n General Configuration Register 0 */ /*! @{ */ #define DDRPHY_DX8GCR0_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX8GCR0_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX8GCR0_RESERVED_1_0_MASK) #define DDRPHY_DX8GCR0_DQSGOE_MASK (0x4U) #define DDRPHY_DX8GCR0_DQSGOE_SHIFT (2U) /*! DQSGOE - DQSG Output Enable */ #define DDRPHY_DX8GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSGOE_SHIFT)) & DDRPHY_DX8GCR0_DQSGOE_MASK) #define DDRPHY_DX8GCR0_DQSGODT_MASK (0x8U) #define DDRPHY_DX8GCR0_DQSGODT_SHIFT (3U) /*! DQSGODT - DQSG On-Die Termination */ #define DDRPHY_DX8GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSGODT_SHIFT)) & DDRPHY_DX8GCR0_DQSGODT_MASK) #define DDRPHY_DX8GCR0_RESERVED_4_MASK (0x10U) #define DDRPHY_DX8GCR0_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX8GCR0_RESERVED_4_MASK) #define DDRPHY_DX8GCR0_DQSGPDR_MASK (0x20U) #define DDRPHY_DX8GCR0_DQSGPDR_SHIFT (5U) /*! DQSGPDR - DQSG Power Down Receiver */ #define DDRPHY_DX8GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX8GCR0_DQSGPDR_MASK) #define DDRPHY_DX8GCR0_DQSRPD_MASK (0x40U) #define DDRPHY_DX8GCR0_DQSRPD_SHIFT (6U) /*! DQSRPD - DQSR Power Down */ #define DDRPHY_DX8GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSRPD_SHIFT)) & DDRPHY_DX8GCR0_DQSRPD_MASK) #define DDRPHY_DX8GCR0_CPDRSHFT_MASK (0x180U) #define DDRPHY_DX8GCR0_CPDRSHFT_SHIFT (7U) /*! CPDRSHFT - Configurable PDR Phase Shift */ #define DDRPHY_DX8GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX8GCR0_CPDRSHFT_MASK) #define DDRPHY_DX8GCR0_RTTOH_MASK (0x600U) #define DDRPHY_DX8GCR0_RTTOH_SHIFT (9U) /*! RTTOH - RTT Output Hold */ #define DDRPHY_DX8GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RTTOH_SHIFT)) & DDRPHY_DX8GCR0_RTTOH_MASK) #define DDRPHY_DX8GCR0_RTTOAL_MASK (0x800U) #define DDRPHY_DX8GCR0_RTTOAL_SHIFT (11U) /*! RTTOAL - RTT On Additive Latency */ #define DDRPHY_DX8GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RTTOAL_SHIFT)) & DDRPHY_DX8GCR0_RTTOAL_MASK) #define DDRPHY_DX8GCR0_DQSSEPDR_MASK (0x1000U) #define DDRPHY_DX8GCR0_DQSSEPDR_SHIFT (12U) /*! DQSSEPDR - DQSSE Power Down Receiver */ #define DDRPHY_DX8GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX8GCR0_DQSSEPDR_MASK) #define DDRPHY_DX8GCR0_DQSNSEPDR_MASK (0x2000U) #define DDRPHY_DX8GCR0_DQSNSEPDR_SHIFT (13U) /*! DQSNSEPDR - DQSNSE Power Down Receiver */ #define DDRPHY_DX8GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX8GCR0_DQSNSEPDR_MASK) #define DDRPHY_DX8GCR0_RESERVED_19_14_MASK (0xFC000U) #define DDRPHY_DX8GCR0_RESERVED_19_14_SHIFT (14U) /*! RESERVED_19_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX8GCR0_RESERVED_19_14_MASK) #define DDRPHY_DX8GCR0_RDDLY_MASK (0xF00000U) #define DDRPHY_DX8GCR0_RDDLY_SHIFT (20U) /*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY */ #define DDRPHY_DX8GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RDDLY_SHIFT)) & DDRPHY_DX8GCR0_RDDLY_MASK) #define DDRPHY_DX8GCR0_DQSDCC_MASK (0xF000000U) #define DDRPHY_DX8GCR0_DQSDCC_SHIFT (24U) /*! DQSDCC - DQS Duty Cycle Correction */ #define DDRPHY_DX8GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSDCC_SHIFT)) & DDRPHY_DX8GCR0_DQSDCC_MASK) #define DDRPHY_DX8GCR0_CODTSHFT_MASK (0x30000000U) #define DDRPHY_DX8GCR0_CODTSHFT_SHIFT (28U) /*! CODTSHFT - Configurable ODT(TE) Phase Shift */ #define DDRPHY_DX8GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX8GCR0_CODTSHFT_MASK) #define DDRPHY_DX8GCR0_MDLEN_MASK (0x40000000U) #define DDRPHY_DX8GCR0_MDLEN_SHIFT (30U) /*! MDLEN - Master Delay Line Enable */ #define DDRPHY_DX8GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_MDLEN_SHIFT)) & DDRPHY_DX8GCR0_MDLEN_MASK) #define DDRPHY_DX8GCR0_CALBYP_MASK (0x80000000U) #define DDRPHY_DX8GCR0_CALBYP_SHIFT (31U) /*! CALBYP - Calibration Bypass */ #define DDRPHY_DX8GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_CALBYP_SHIFT)) & DDRPHY_DX8GCR0_CALBYP_MASK) /*! @} */ /*! @name DX8GCR1 - DATX8 n General Configuration Register 1 */ /*! @{ */ #define DDRPHY_DX8GCR1_DQEN_MASK (0xFFU) #define DDRPHY_DX8GCR1_DQEN_SHIFT (0U) /*! DQEN - Enables DQ corresponding to each bit in a byte */ #define DDRPHY_DX8GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DQEN_SHIFT)) & DDRPHY_DX8GCR1_DQEN_MASK) #define DDRPHY_DX8GCR1_DMEN_MASK (0x100U) #define DDRPHY_DX8GCR1_DMEN_SHIFT (8U) /*! DMEN - Enables DM pin in a byte lane */ #define DDRPHY_DX8GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DMEN_SHIFT)) & DDRPHY_DX8GCR1_DMEN_MASK) #define DDRPHY_DX8GCR1_DSEN_MASK (0x200U) #define DDRPHY_DX8GCR1_DSEN_SHIFT (9U) /*! DSEN - Enables Write Data strobe in a byte lane */ #define DDRPHY_DX8GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DSEN_SHIFT)) & DDRPHY_DX8GCR1_DSEN_MASK) #define DDRPHY_DX8GCR1_TEEN_MASK (0x400U) #define DDRPHY_DX8GCR1_TEEN_SHIFT (10U) /*! TEEN - Enables ODT/TE in a byte lane */ #define DDRPHY_DX8GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_TEEN_SHIFT)) & DDRPHY_DX8GCR1_TEEN_MASK) #define DDRPHY_DX8GCR1_PDREN_MASK (0x800U) #define DDRPHY_DX8GCR1_PDREN_SHIFT (11U) /*! PDREN - Enables PDR in a byte lane */ #define DDRPHY_DX8GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_PDREN_SHIFT)) & DDRPHY_DX8GCR1_PDREN_MASK) #define DDRPHY_DX8GCR1_OEEN_MASK (0x1000U) #define DDRPHY_DX8GCR1_OEEN_SHIFT (12U) /*! OEEN - Enables Read Data Strobe in a byte lane */ #define DDRPHY_DX8GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_OEEN_SHIFT)) & DDRPHY_DX8GCR1_OEEN_MASK) #define DDRPHY_DX8GCR1_QSSEL_MASK (0x2000U) #define DDRPHY_DX8GCR1_QSSEL_SHIFT (13U) /*! QSSEL - Select the delayed or non-delayed read data strobe */ #define DDRPHY_DX8GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_QSSEL_SHIFT)) & DDRPHY_DX8GCR1_QSSEL_MASK) #define DDRPHY_DX8GCR1_QSNSEL_MASK (0x4000U) #define DDRPHY_DX8GCR1_QSNSEL_SHIFT (14U) /*! QSNSEL - Select the delayed or non-delayed read data strobe # */ #define DDRPHY_DX8GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_QSNSEL_SHIFT)) & DDRPHY_DX8GCR1_QSNSEL_MASK) #define DDRPHY_DX8GCR1_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX8GCR1_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX8GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX8GCR1_RESERVED_15_MASK) #define DDRPHY_DX8GCR1_DXPDRMODE_MASK (0xFFFF0000U) #define DDRPHY_DX8GCR1_DXPDRMODE_SHIFT (16U) /*! DXPDRMODE - Enables the PDR mode for DQ[7:0] */ #define DDRPHY_DX8GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX8GCR1_DXPDRMODE_MASK) /*! @} */ /*! @name DX8GCR2 - DATX8 n General Configuration Register 2 */ /*! @{ */ #define DDRPHY_DX8GCR2_DXTEMODE_MASK (0xFFFFU) #define DDRPHY_DX8GCR2_DXTEMODE_SHIFT (0U) /*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0] */ #define DDRPHY_DX8GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX8GCR2_DXTEMODE_MASK) #define DDRPHY_DX8GCR2_DXOEMODE_MASK (0xFFFF0000U) #define DDRPHY_DX8GCR2_DXOEMODE_SHIFT (16U) /*! DXOEMODE - Enables the OE mode values for DQ[7:0] */ #define DDRPHY_DX8GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX8GCR2_DXOEMODE_MASK) /*! @} */ /*! @name DX8GCR3 - DATX8 n General Configuration Register 3 */ /*! @{ */ #define DDRPHY_DX8GCR3_WDMBVT_MASK (0x1U) #define DDRPHY_DX8GCR3_WDMBVT_SHIFT (0U) /*! WDMBVT - Write Data Mask BDL VT Compensation */ #define DDRPHY_DX8GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDMBVT_SHIFT)) & DDRPHY_DX8GCR3_WDMBVT_MASK) #define DDRPHY_DX8GCR3_RDMBVT_MASK (0x2U) #define DDRPHY_DX8GCR3_RDMBVT_SHIFT (1U) /*! RDMBVT - Read Data Mask BDL VT Compensation */ #define DDRPHY_DX8GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RDMBVT_SHIFT)) & DDRPHY_DX8GCR3_RDMBVT_MASK) #define DDRPHY_DX8GCR3_DSPDRMODE_MASK (0xCU) #define DDRPHY_DX8GCR3_DSPDRMODE_SHIFT (2U) /*! DSPDRMODE - Enables the PDR mode values for DQS. */ #define DDRPHY_DX8GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX8GCR3_DSPDRMODE_MASK) #define DDRPHY_DX8GCR3_DSTEMODE_MASK (0x30U) #define DDRPHY_DX8GCR3_DSTEMODE_SHIFT (4U) /*! DSTEMODE - Enables the TE mode values for DQS. */ #define DDRPHY_DX8GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSTEMODE_MASK) #define DDRPHY_DX8GCR3_DSOEMODE_MASK (0xC0U) #define DDRPHY_DX8GCR3_DSOEMODE_SHIFT (6U) /*! DSOEMODE - Enables the OE mode values for DQS. */ #define DDRPHY_DX8GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSOEMODE_MASK) #define DDRPHY_DX8GCR3_WDSBVT_MASK (0x100U) #define DDRPHY_DX8GCR3_WDSBVT_SHIFT (8U) /*! WDSBVT - Write Data Strobe BDL VT Compensation */ #define DDRPHY_DX8GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDSBVT_SHIFT)) & DDRPHY_DX8GCR3_WDSBVT_MASK) #define DDRPHY_DX8GCR3_RESERVED_9_MASK (0x200U) #define DDRPHY_DX8GCR3_RESERVED_9_SHIFT (9U) /*! RESERVED_9 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX8GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX8GCR3_RESERVED_9_MASK) #define DDRPHY_DX8GCR3_DMPDRMODE_MASK (0xC00U) #define DDRPHY_DX8GCR3_DMPDRMODE_SHIFT (10U) /*! DMPDRMODE - Enables the PDR mode values for DM. */ #define DDRPHY_DX8GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX8GCR3_DMPDRMODE_MASK) #define DDRPHY_DX8GCR3_DMTEMODE_MASK (0x3000U) #define DDRPHY_DX8GCR3_DMTEMODE_SHIFT (12U) /*! DMTEMODE - Enables the TE mode values for DM. */ #define DDRPHY_DX8GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX8GCR3_DMTEMODE_MASK) #define DDRPHY_DX8GCR3_DMOEMODE_MASK (0xC000U) #define DDRPHY_DX8GCR3_DMOEMODE_SHIFT (14U) /*! DMOEMODE - Enables the OE mode values for DM. */ #define DDRPHY_DX8GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX8GCR3_DMOEMODE_MASK) #define DDRPHY_DX8GCR3_DSNPDRMODE_MASK (0x30000U) #define DDRPHY_DX8GCR3_DSNPDRMODE_SHIFT (16U) /*! DSNPDRMODE - Enables the PDR mode for DQS */ #define DDRPHY_DX8GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX8GCR3_DSNPDRMODE_MASK) #define DDRPHY_DX8GCR3_DSNTEMODE_MASK (0xC0000U) #define DDRPHY_DX8GCR3_DSNTEMODE_SHIFT (18U) /*! DSNTEMODE - Enables the TE mode for DQS */ #define DDRPHY_DX8GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSNTEMODE_MASK) #define DDRPHY_DX8GCR3_DSNOEMODE_MASK (0x300000U) #define DDRPHY_DX8GCR3_DSNOEMODE_SHIFT (20U) /*! DSNOEMODE - Enables the OE mode for DQs */ #define DDRPHY_DX8GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSNOEMODE_MASK) #define DDRPHY_DX8GCR3_PDRBVT_MASK (0x400000U) #define DDRPHY_DX8GCR3_PDRBVT_SHIFT (22U) /*! PDRBVT - Power Down Receiver BDL VT Compensation */ #define DDRPHY_DX8GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_PDRBVT_SHIFT)) & DDRPHY_DX8GCR3_PDRBVT_MASK) #define DDRPHY_DX8GCR3_RGSLVT_MASK (0x800000U) #define DDRPHY_DX8GCR3_RGSLVT_SHIFT (23U) /*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation */ #define DDRPHY_DX8GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RGSLVT_SHIFT)) & DDRPHY_DX8GCR3_RGSLVT_MASK) #define DDRPHY_DX8GCR3_WLLVT_MASK (0x1000000U) #define DDRPHY_DX8GCR3_WLLVT_SHIFT (24U) /*! WLLVT - Write Leveling LCDL Delay VT Compensation */ #define DDRPHY_DX8GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WLLVT_SHIFT)) & DDRPHY_DX8GCR3_WLLVT_MASK) #define DDRPHY_DX8GCR3_WDLVT_MASK (0x2000000U) #define DDRPHY_DX8GCR3_WDLVT_SHIFT (25U) /*! WDLVT - Write DQ LCDL Delay VT Compensation */ #define DDRPHY_DX8GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDLVT_SHIFT)) & DDRPHY_DX8GCR3_WDLVT_MASK) #define DDRPHY_DX8GCR3_RDLVT_MASK (0x4000000U) #define DDRPHY_DX8GCR3_RDLVT_SHIFT (26U) /*! RDLVT - Read DQS LCDL Delay VT Compensation */ #define DDRPHY_DX8GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RDLVT_SHIFT)) & DDRPHY_DX8GCR3_RDLVT_MASK) #define DDRPHY_DX8GCR3_RGLVT_MASK (0x8000000U) #define DDRPHY_DX8GCR3_RGLVT_SHIFT (27U) /*! RGLVT - Read DQS Gating LCDL Delay VT Compensation */ #define DDRPHY_DX8GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RGLVT_SHIFT)) & DDRPHY_DX8GCR3_RGLVT_MASK) #define DDRPHY_DX8GCR3_WDBVT_MASK (0x10000000U) #define DDRPHY_DX8GCR3_WDBVT_SHIFT (28U) /*! WDBVT - Write Data BDL VT Compensation */ #define DDRPHY_DX8GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDBVT_SHIFT)) & DDRPHY_DX8GCR3_WDBVT_MASK) #define DDRPHY_DX8GCR3_RDBVT_MASK (0x20000000U) #define DDRPHY_DX8GCR3_RDBVT_SHIFT (29U) /*! RDBVT - Read Data BDL VT Compensation */ #define DDRPHY_DX8GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RDBVT_SHIFT)) & DDRPHY_DX8GCR3_RDBVT_MASK) #define DDRPHY_DX8GCR3_TEBVT_MASK (0x40000000U) #define DDRPHY_DX8GCR3_TEBVT_SHIFT (30U) /*! TEBVT - Termination Enable BDL VT Compensation */ #define DDRPHY_DX8GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_TEBVT_SHIFT)) & DDRPHY_DX8GCR3_TEBVT_MASK) #define DDRPHY_DX8GCR3_OEBVT_MASK (0x80000000U) #define DDRPHY_DX8GCR3_OEBVT_SHIFT (31U) /*! OEBVT - Output Enable BDL VT Compensation */ #define DDRPHY_DX8GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_OEBVT_SHIFT)) & DDRPHY_DX8GCR3_OEBVT_MASK) /*! @} */ /*! @name DX8GCR4 - DATX8 n General Configuration Register 4 */ /*! @{ */ #define DDRPHY_DX8GCR4_DXREFIMON_MASK (0x3U) #define DDRPHY_DX8GCR4_DXREFIMON_SHIFT (0U) /*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX8GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX8GCR4_DXREFIMON_MASK) #define DDRPHY_DX8GCR4_DXREFIEN_MASK (0x3CU) #define DDRPHY_DX8GCR4_DXREFIEN_SHIFT (2U) /*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. */ #define DDRPHY_DX8GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFIEN_MASK) #define DDRPHY_DX8GCR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8GCR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX8GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR4_RESERVED_7_6_MASK) #define DDRPHY_DX8GCR4_DXREFSSEL_MASK (0x7F00U) #define DDRPHY_DX8GCR4_DXREFSSEL_SHIFT (8U) /*! DXREFSSEL - Byte Lane Single-End VREF Select */ #define DDRPHY_DX8GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX8GCR4_DXREFSSEL_MASK) #define DDRPHY_DX8GCR4_DXREFSSELRANGE_MASK (0x8000U) #define DDRPHY_DX8GCR4_DXREFSSELRANGE_SHIFT (15U) /*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select */ #define DDRPHY_DX8GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX8GCR4_DXREFSSELRANGE_MASK) #define DDRPHY_DX8GCR4_DXREFESEL_MASK (0x7F0000U) #define DDRPHY_DX8GCR4_DXREFESEL_SHIFT (16U) /*! DXREFESEL - Byte Lane External VREF Select */ #define DDRPHY_DX8GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX8GCR4_DXREFESEL_MASK) #define DDRPHY_DX8GCR4_DXREFESELRANGE_MASK (0x800000U) #define DDRPHY_DX8GCR4_DXREFESELRANGE_SHIFT (23U) /*! DXREFESELRANGE - External VREF generator REFSEL range select */ #define DDRPHY_DX8GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX8GCR4_DXREFESELRANGE_MASK) #define DDRPHY_DX8GCR4_RESERVED_24_MASK (0x1000000U) #define DDRPHY_DX8GCR4_RESERVED_24_SHIFT (24U) /*! RESERVED_24 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX8GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX8GCR4_RESERVED_24_MASK) #define DDRPHY_DX8GCR4_DXREFSEN_MASK (0x2000000U) #define DDRPHY_DX8GCR4_DXREFSEN_SHIFT (25U) /*! DXREFSEN - Byte Lane Single-End VREF Enable */ #define DDRPHY_DX8GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFSEN_MASK) #define DDRPHY_DX8GCR4_DXREFEEN_MASK (0xC000000U) #define DDRPHY_DX8GCR4_DXREFEEN_SHIFT (26U) /*! DXREFEEN - Byte Lane Internal VREF Enable */ #define DDRPHY_DX8GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFEEN_MASK) #define DDRPHY_DX8GCR4_DXREFPEN_MASK (0x10000000U) #define DDRPHY_DX8GCR4_DXREFPEN_SHIFT (28U) /*! DXREFPEN - Byte Lane VREF Pad Enable */ #define DDRPHY_DX8GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFPEN_MASK) #define DDRPHY_DX8GCR4_RESERVED_31_29_MASK (0xE0000000U) #define DDRPHY_DX8GCR4_RESERVED_31_29_SHIFT (29U) /*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs) */ #define DDRPHY_DX8GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX8GCR4_RESERVED_31_29_MASK) /*! @} */ /*! @name DX8GCR5 - DATX8 n General Configuration Register 5 */ /*! @{ */ #define DDRPHY_DX8GCR5_DXREFISELR0_MASK (0x7FU) #define DDRPHY_DX8GCR5_DXREFISELR0_SHIFT (0U) /*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0 */ #define DDRPHY_DX8GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR0_MASK) #define DDRPHY_DX8GCR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX8GCR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX8GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_7_MASK) #define DDRPHY_DX8GCR5_DXREFISELR1_MASK (0x7F00U) #define DDRPHY_DX8GCR5_DXREFISELR1_SHIFT (8U) /*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1 */ #define DDRPHY_DX8GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR1_MASK) #define DDRPHY_DX8GCR5_RESERVED_15_MASK (0x8000U) #define DDRPHY_DX8GCR5_RESERVED_15_SHIFT (15U) /*! RESERVED_15 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX8GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_15_MASK) #define DDRPHY_DX8GCR5_DXREFISELR2_MASK (0x7F0000U) #define DDRPHY_DX8GCR5_DXREFISELR2_SHIFT (16U) /*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2 */ #define DDRPHY_DX8GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR2_MASK) #define DDRPHY_DX8GCR5_RESERVED_23_MASK (0x800000U) #define DDRPHY_DX8GCR5_RESERVED_23_SHIFT (23U) /*! RESERVED_23 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX8GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_23_MASK) #define DDRPHY_DX8GCR5_DXREFISELR3_MASK (0x7F000000U) #define DDRPHY_DX8GCR5_DXREFISELR3_SHIFT (24U) /*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3 */ #define DDRPHY_DX8GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR3_MASK) #define DDRPHY_DX8GCR5_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8GCR5_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX8GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_31_MASK) /*! @} */ /*! @name DX8GCR6 - DATX8 n General Configuration Register 6 */ /*! @{ */ #define DDRPHY_DX8GCR6_DXDQVREFR0_MASK (0x3FU) #define DDRPHY_DX8GCR6_DXDQVREFR0_SHIFT (0U) /*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0 */ #define DDRPHY_DX8GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR0_MASK) #define DDRPHY_DX8GCR6_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8GCR6_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX8GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_7_6_MASK) #define DDRPHY_DX8GCR6_DXDQVREFR1_MASK (0x3F00U) #define DDRPHY_DX8GCR6_DXDQVREFR1_SHIFT (8U) /*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1 */ #define DDRPHY_DX8GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR1_MASK) #define DDRPHY_DX8GCR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8GCR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX8GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_15_14_MASK) #define DDRPHY_DX8GCR6_DXDQVREFR2_MASK (0x3F0000U) #define DDRPHY_DX8GCR6_DXDQVREFR2_SHIFT (16U) /*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2 */ #define DDRPHY_DX8GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR2_MASK) #define DDRPHY_DX8GCR6_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8GCR6_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX8GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_23_22_MASK) #define DDRPHY_DX8GCR6_DXDQVREFR3_MASK (0x3F000000U) #define DDRPHY_DX8GCR6_DXDQVREFR3_SHIFT (24U) /*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3 */ #define DDRPHY_DX8GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR3_MASK) #define DDRPHY_DX8GCR6_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8GCR6_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Returns zeros on reads. */ #define DDRPHY_DX8GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8GCR7 - DATX8 n General Configuration Register 7 */ /*! @{ */ #define DDRPHY_DX8GCR7_DCALSVAL_MASK (0x1FFU) #define DDRPHY_DX8GCR7_DCALSVAL_SHIFT (0U) /*! DCALSVAL - DDL Calibration Starting Value */ #define DDRPHY_DX8GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX8GCR7_DCALSVAL_MASK) #define DDRPHY_DX8GCR7_DCALTYPE_MASK (0x200U) #define DDRPHY_DX8GCR7_DCALTYPE_SHIFT (9U) /*! DCALTYPE - DDL Calibration Type */ #define DDRPHY_DX8GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX8GCR7_DCALTYPE_MASK) #define DDRPHY_DX8GCR7_RESERVED_17_10_MASK (0x3FC00U) #define DDRPHY_DX8GCR7_RESERVED_17_10_SHIFT (10U) /*! RESERVED_17_10 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX8GCR7_RESERVED_17_10_MASK) #define DDRPHY_DX8GCR7_RESERVED_18_MASK (0x40000U) #define DDRPHY_DX8GCR7_RESERVED_18_SHIFT (18U) /*! RESERVED_18 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX8GCR7_RESERVED_18_MASK) #define DDRPHY_DX8GCR7_RESERVED_31_19_MASK (0xFFF80000U) #define DDRPHY_DX8GCR7_RESERVED_31_19_SHIFT (19U) /*! RESERVED_31_19 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX8GCR7_RESERVED_31_19_MASK) /*! @} */ /*! @name DX8GCR8 - DATX8 n General Configuration Register 8 */ /*! @{ */ #define DDRPHY_DX8GCR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX8GCR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_5_0_MASK) #define DDRPHY_DX8GCR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8GCR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_7_6_MASK) #define DDRPHY_DX8GCR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX8GCR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_13_8_MASK) #define DDRPHY_DX8GCR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8GCR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_15_14_MASK) #define DDRPHY_DX8GCR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX8GCR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_21_16_MASK) #define DDRPHY_DX8GCR8_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8GCR8_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_23_22_MASK) #define DDRPHY_DX8GCR8_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX8GCR8_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_29_24_MASK) #define DDRPHY_DX8GCR8_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8GCR8_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8GCR9 - DATX8 n General Configuration Register 9 */ /*! @{ */ #define DDRPHY_DX8GCR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX8GCR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_5_0_MASK) #define DDRPHY_DX8GCR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8GCR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_7_6_MASK) #define DDRPHY_DX8GCR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX8GCR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_13_8_MASK) #define DDRPHY_DX8GCR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8GCR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_15_14_MASK) #define DDRPHY_DX8GCR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX8GCR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_21_16_MASK) #define DDRPHY_DX8GCR9_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8GCR9_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_23_22_MASK) #define DDRPHY_DX8GCR9_RESERVED_29_24_MASK (0x3F000000U) #define DDRPHY_DX8GCR9_RESERVED_29_24_SHIFT (24U) /*! RESERVED_29_24 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_29_24_MASK) #define DDRPHY_DX8GCR9_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8GCR9_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */ /*! @{ */ #define DDRPHY_DX8DQMAP0_DQ0MAP_MASK (0xFU) #define DDRPHY_DX8DQMAP0_DQ0MAP_SHIFT (0U) /*! DQ0MAP - DQ bit 0 DATX8 slice mapping index */ #define DDRPHY_DX8DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ0MAP_MASK) #define DDRPHY_DX8DQMAP0_DQ1MAP_MASK (0xF0U) #define DDRPHY_DX8DQMAP0_DQ1MAP_SHIFT (4U) /*! DQ1MAP - DQ bit 1 DATX8 slice mapping index */ #define DDRPHY_DX8DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ1MAP_MASK) #define DDRPHY_DX8DQMAP0_DQ2MAP_MASK (0xF00U) #define DDRPHY_DX8DQMAP0_DQ2MAP_SHIFT (8U) /*! DQ2MAP - DQ bit 2 DATX8 slice mapping index */ #define DDRPHY_DX8DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ2MAP_MASK) #define DDRPHY_DX8DQMAP0_DQ3MAP_MASK (0xF000U) #define DDRPHY_DX8DQMAP0_DQ3MAP_SHIFT (12U) /*! DQ3MAP - DQ bit 3 DATX8 slice mapping index */ #define DDRPHY_DX8DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ3MAP_MASK) #define DDRPHY_DX8DQMAP0_DQ4MAP_MASK (0xF0000U) #define DDRPHY_DX8DQMAP0_DQ4MAP_SHIFT (16U) /*! DQ4MAP - DQ bit 4 DATX8 slice mapping index */ #define DDRPHY_DX8DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ4MAP_MASK) #define DDRPHY_DX8DQMAP0_RESERVED_30_20_MASK (0x7FF00000U) #define DDRPHY_DX8DQMAP0_RESERVED_30_20_SHIFT (20U) /*! RESERVED_30_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX8DQMAP0_RESERVED_30_20_MASK) #define DDRPHY_DX8DQMAP0_MAPOK_MASK (0x80000000U) #define DDRPHY_DX8DQMAP0_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX8DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX8DQMAP0_MAPOK_MASK) /*! @} */ /*! @name DX8DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */ /*! @{ */ #define DDRPHY_DX8DQMAP1_DQ5MAP_MASK (0xFU) #define DDRPHY_DX8DQMAP1_DQ5MAP_SHIFT (0U) /*! DQ5MAP - DQ bit 5 DATX8 slice mapping index */ #define DDRPHY_DX8DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX8DQMAP1_DQ5MAP_MASK) #define DDRPHY_DX8DQMAP1_DQ6MAP_MASK (0xF0U) #define DDRPHY_DX8DQMAP1_DQ6MAP_SHIFT (4U) /*! DQ6MAP - DQ bit 6 DATX8 slice mapping index */ #define DDRPHY_DX8DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX8DQMAP1_DQ6MAP_MASK) #define DDRPHY_DX8DQMAP1_DQ7MAP_MASK (0xF00U) #define DDRPHY_DX8DQMAP1_DQ7MAP_SHIFT (8U) /*! DQ7MAP - DQ bit 7 DATX8 slice mapping index */ #define DDRPHY_DX8DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX8DQMAP1_DQ7MAP_MASK) #define DDRPHY_DX8DQMAP1_DMMAP_MASK (0xF000U) #define DDRPHY_DX8DQMAP1_DMMAP_SHIFT (12U) /*! DMMAP - DM bit DATX8 slice mapping index */ #define DDRPHY_DX8DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX8DQMAP1_DMMAP_MASK) #define DDRPHY_DX8DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U) #define DDRPHY_DX8DQMAP1_RESERVED_30_16_SHIFT (16U) /*! RESERVED_30_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX8DQMAP1_RESERVED_30_16_MASK) #define DDRPHY_DX8DQMAP1_MAPOK_MASK (0x80000000U) #define DDRPHY_DX8DQMAP1_MAPOK_SHIFT (31U) /*! MAPOK - Checksum bit */ #define DDRPHY_DX8DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX8DQMAP1_MAPOK_MASK) /*! @} */ /*! @name DX8BDLR0 - DATX8 n Bit Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX8BDLR0_DQ0WBD_MASK (0x3FU) #define DDRPHY_DX8BDLR0_DQ0WBD_SHIFT (0U) /*! DQ0WBD - DQ0 Write Bit Delay */ #define DDRPHY_DX8BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ0WBD_MASK) #define DDRPHY_DX8BDLR0_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8BDLR0_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_7_6_MASK) #define DDRPHY_DX8BDLR0_DQ1WBD_MASK (0x3F00U) #define DDRPHY_DX8BDLR0_DQ1WBD_SHIFT (8U) /*! DQ1WBD - DQ1 Write Bit Delay */ #define DDRPHY_DX8BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ1WBD_MASK) #define DDRPHY_DX8BDLR0_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8BDLR0_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_15_14_MASK) #define DDRPHY_DX8BDLR0_DQ2WBD_MASK (0x3F0000U) #define DDRPHY_DX8BDLR0_DQ2WBD_SHIFT (16U) /*! DQ2WBD - DQ2 Write Bit Delay */ #define DDRPHY_DX8BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ2WBD_MASK) #define DDRPHY_DX8BDLR0_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8BDLR0_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_23_22_MASK) #define DDRPHY_DX8BDLR0_DQ3WBD_MASK (0x3F000000U) #define DDRPHY_DX8BDLR0_DQ3WBD_SHIFT (24U) /*! DQ3WBD - DQ3 Write Bit Delay */ #define DDRPHY_DX8BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ3WBD_MASK) #define DDRPHY_DX8BDLR0_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8BDLR0_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8BDLR1 - DATX8 n Bit Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX8BDLR1_DQ4WBD_MASK (0x3FU) #define DDRPHY_DX8BDLR1_DQ4WBD_SHIFT (0U) /*! DQ4WBD - DQ4 Write Bit Delay */ #define DDRPHY_DX8BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ4WBD_MASK) #define DDRPHY_DX8BDLR1_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8BDLR1_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_7_6_MASK) #define DDRPHY_DX8BDLR1_DQ5WBD_MASK (0x3F00U) #define DDRPHY_DX8BDLR1_DQ5WBD_SHIFT (8U) /*! DQ5WBD - DQ5 Write Bit Delay */ #define DDRPHY_DX8BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ5WBD_MASK) #define DDRPHY_DX8BDLR1_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8BDLR1_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_15_14_MASK) #define DDRPHY_DX8BDLR1_DQ6WBD_MASK (0x3F0000U) #define DDRPHY_DX8BDLR1_DQ6WBD_SHIFT (16U) /*! DQ6WBD - DQ6 Write Bit Delay */ #define DDRPHY_DX8BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ6WBD_MASK) #define DDRPHY_DX8BDLR1_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8BDLR1_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_23_22_MASK) #define DDRPHY_DX8BDLR1_DQ7WBD_MASK (0x3F000000U) #define DDRPHY_DX8BDLR1_DQ7WBD_SHIFT (24U) /*! DQ7WBD - DQ7 Write Bit Delay */ #define DDRPHY_DX8BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ7WBD_MASK) #define DDRPHY_DX8BDLR1_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8BDLR1_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8BDLR2 - DATX8 n Bit Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX8BDLR2_DMWBD_MASK (0x3FU) #define DDRPHY_DX8BDLR2_DMWBD_SHIFT (0U) /*! DMWBD - DM Write Bit Delay */ #define DDRPHY_DX8BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DMWBD_SHIFT)) & DDRPHY_DX8BDLR2_DMWBD_MASK) #define DDRPHY_DX8BDLR2_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8BDLR2_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_7_6_MASK) #define DDRPHY_DX8BDLR2_DSWBD_MASK (0x3F00U) #define DDRPHY_DX8BDLR2_DSWBD_SHIFT (8U) /*! DSWBD - DQS Write Bit Delay */ #define DDRPHY_DX8BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DSWBD_SHIFT)) & DDRPHY_DX8BDLR2_DSWBD_MASK) #define DDRPHY_DX8BDLR2_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8BDLR2_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_15_14_MASK) #define DDRPHY_DX8BDLR2_DSOEBD_MASK (0x3F0000U) #define DDRPHY_DX8BDLR2_DSOEBD_SHIFT (16U) /*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay */ #define DDRPHY_DX8BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX8BDLR2_DSOEBD_MASK) #define DDRPHY_DX8BDLR2_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8BDLR2_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_23_22_MASK) #define DDRPHY_DX8BDLR2_DSNWBD_MASK (0x3F000000U) #define DDRPHY_DX8BDLR2_DSNWBD_SHIFT (24U) /*! DSNWBD - DQSN Write Bit Delay */ #define DDRPHY_DX8BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX8BDLR2_DSNWBD_MASK) #define DDRPHY_DX8BDLR2_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8BDLR2_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8BDLR3 - DATX8 n Bit Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX8BDLR3_DQ0RBD_MASK (0x3FU) #define DDRPHY_DX8BDLR3_DQ0RBD_SHIFT (0U) /*! DQ0RBD - DQ0 Read Bit Delay */ #define DDRPHY_DX8BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ0RBD_MASK) #define DDRPHY_DX8BDLR3_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8BDLR3_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_7_6_MASK) #define DDRPHY_DX8BDLR3_DQ1RBD_MASK (0x3F00U) #define DDRPHY_DX8BDLR3_DQ1RBD_SHIFT (8U) /*! DQ1RBD - DQ1 Read Bit Delay */ #define DDRPHY_DX8BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ1RBD_MASK) #define DDRPHY_DX8BDLR3_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8BDLR3_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_15_14_MASK) #define DDRPHY_DX8BDLR3_DQ2RBD_MASK (0x3F0000U) #define DDRPHY_DX8BDLR3_DQ2RBD_SHIFT (16U) /*! DQ2RBD - DQ2 Read Bit Delay */ #define DDRPHY_DX8BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ2RBD_MASK) #define DDRPHY_DX8BDLR3_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8BDLR3_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_23_22_MASK) #define DDRPHY_DX8BDLR3_DQ3RBD_MASK (0x3F000000U) #define DDRPHY_DX8BDLR3_DQ3RBD_SHIFT (24U) /*! DQ3RBD - DQ3 Read Bit Delay */ #define DDRPHY_DX8BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ3RBD_MASK) #define DDRPHY_DX8BDLR3_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8BDLR3_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8BDLR4 - DATX8 n Bit Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX8BDLR4_DQ4RBD_MASK (0x3FU) #define DDRPHY_DX8BDLR4_DQ4RBD_SHIFT (0U) /*! DQ4RBD - DQ4 Read Bit Delay */ #define DDRPHY_DX8BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ4RBD_MASK) #define DDRPHY_DX8BDLR4_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8BDLR4_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_7_6_MASK) #define DDRPHY_DX8BDLR4_DQ5RBD_MASK (0x3F00U) #define DDRPHY_DX8BDLR4_DQ5RBD_SHIFT (8U) /*! DQ5RBD - DQ5 Read Bit Delay */ #define DDRPHY_DX8BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ5RBD_MASK) #define DDRPHY_DX8BDLR4_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8BDLR4_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_15_14_MASK) #define DDRPHY_DX8BDLR4_DQ6RBD_MASK (0x3F0000U) #define DDRPHY_DX8BDLR4_DQ6RBD_SHIFT (16U) /*! DQ6RBD - DQ6 Read Bit Delay */ #define DDRPHY_DX8BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ6RBD_MASK) #define DDRPHY_DX8BDLR4_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8BDLR4_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_23_22_MASK) #define DDRPHY_DX8BDLR4_DQ7RBD_MASK (0x3F000000U) #define DDRPHY_DX8BDLR4_DQ7RBD_SHIFT (24U) /*! DQ7RBD - DQ7 Read Bit Delay */ #define DDRPHY_DX8BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ7RBD_MASK) #define DDRPHY_DX8BDLR4_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8BDLR4_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8BDLR5 - DATX8 n Bit Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX8BDLR5_DMRBD_MASK (0x3FU) #define DDRPHY_DX8BDLR5_DMRBD_SHIFT (0U) /*! DMRBD - DM Read Bit Delay */ #define DDRPHY_DX8BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR5_DMRBD_SHIFT)) & DDRPHY_DX8BDLR5_DMRBD_MASK) #define DDRPHY_DX8BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U) #define DDRPHY_DX8BDLR5_RESERVED_31_6_SHIFT (6U) /*! RESERVED_31_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX8BDLR5_RESERVED_31_6_MASK) /*! @} */ /*! @name DX8BDLR6 - DATX8 n Bit Delay Line Register 6 */ /*! @{ */ #define DDRPHY_DX8BDLR6_RESERVED_7_0_MASK (0xFFU) #define DDRPHY_DX8BDLR6_RESERVED_7_0_SHIFT (0U) /*! RESERVED_7_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX8BDLR6_RESERVED_7_0_MASK) #define DDRPHY_DX8BDLR6_PDRBD_MASK (0x3F00U) #define DDRPHY_DX8BDLR6_PDRBD_SHIFT (8U) /*! PDRBD - Power down receiver Bit Delay */ #define DDRPHY_DX8BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_PDRBD_SHIFT)) & DDRPHY_DX8BDLR6_PDRBD_MASK) #define DDRPHY_DX8BDLR6_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8BDLR6_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR6_RESERVED_15_14_MASK) #define DDRPHY_DX8BDLR6_TERBD_MASK (0x3F0000U) #define DDRPHY_DX8BDLR6_TERBD_SHIFT (16U) /*! TERBD - Termination Enable Bit Delay */ #define DDRPHY_DX8BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_TERBD_SHIFT)) & DDRPHY_DX8BDLR6_TERBD_MASK) #define DDRPHY_DX8BDLR6_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8BDLR6_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR6_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8BDLR7 - DATX8 n Bit Delay Line Register 7 */ /*! @{ */ #define DDRPHY_DX8BDLR7_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX8BDLR7_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_5_0_MASK) #define DDRPHY_DX8BDLR7_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8BDLR7_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_7_6_MASK) #define DDRPHY_DX8BDLR7_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX8BDLR7_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_13_8_MASK) #define DDRPHY_DX8BDLR7_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8BDLR7_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_15_14_MASK) #define DDRPHY_DX8BDLR7_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX8BDLR7_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_21_16_MASK) #define DDRPHY_DX8BDLR7_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8BDLR7_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8BDLR8 - DATX8 n Bit Delay Line Register 8 */ /*! @{ */ #define DDRPHY_DX8BDLR8_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX8BDLR8_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_5_0_MASK) #define DDRPHY_DX8BDLR8_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8BDLR8_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_7_6_MASK) #define DDRPHY_DX8BDLR8_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX8BDLR8_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_13_8_MASK) #define DDRPHY_DX8BDLR8_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8BDLR8_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_15_14_MASK) #define DDRPHY_DX8BDLR8_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX8BDLR8_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_21_16_MASK) #define DDRPHY_DX8BDLR8_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8BDLR8_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8BDLR9 - DATX8 n Bit Delay Line Register 9 */ /*! @{ */ #define DDRPHY_DX8BDLR9_RESERVED_5_0_MASK (0x3FU) #define DDRPHY_DX8BDLR9_RESERVED_5_0_SHIFT (0U) /*! RESERVED_5_0 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_5_0_MASK) #define DDRPHY_DX8BDLR9_RESERVED_7_6_MASK (0xC0U) #define DDRPHY_DX8BDLR9_RESERVED_7_6_SHIFT (6U) /*! RESERVED_7_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_7_6_MASK) #define DDRPHY_DX8BDLR9_RESERVED_13_8_MASK (0x3F00U) #define DDRPHY_DX8BDLR9_RESERVED_13_8_SHIFT (8U) /*! RESERVED_13_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_13_8_MASK) #define DDRPHY_DX8BDLR9_RESERVED_15_14_MASK (0xC000U) #define DDRPHY_DX8BDLR9_RESERVED_15_14_SHIFT (14U) /*! RESERVED_15_14 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_15_14_MASK) #define DDRPHY_DX8BDLR9_RESERVED_21_16_MASK (0x3F0000U) #define DDRPHY_DX8BDLR9_RESERVED_21_16_SHIFT (16U) /*! RESERVED_21_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_21_16_MASK) #define DDRPHY_DX8BDLR9_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8BDLR9_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX8LCDLR0_WLD_MASK (0x1FFU) #define DDRPHY_DX8LCDLR0_WLD_SHIFT (0U) /*! WLD - Write Leveling Delay */ #define DDRPHY_DX8LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_WLD_SHIFT)) & DDRPHY_DX8LCDLR0_WLD_MASK) #define DDRPHY_DX8LCDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX8LCDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX8LCDLR0_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX8LCDLR0_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR0_RESERVED_24_16_MASK) #define DDRPHY_DX8LCDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8LCDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX8LCDLR1_WDQD_MASK (0x1FFU) #define DDRPHY_DX8LCDLR1_WDQD_SHIFT (0U) /*! WDQD - Write Data Delay */ #define DDRPHY_DX8LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_WDQD_SHIFT)) & DDRPHY_DX8LCDLR1_WDQD_MASK) #define DDRPHY_DX8LCDLR1_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX8LCDLR1_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR1_RESERVED_15_9_MASK) #define DDRPHY_DX8LCDLR1_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX8LCDLR1_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR1_RESERVED_24_16_MASK) #define DDRPHY_DX8LCDLR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8LCDLR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */ /*! @{ */ #define DDRPHY_DX8LCDLR2_DQSGD_MASK (0x1FFU) #define DDRPHY_DX8LCDLR2_DQSGD_SHIFT (0U) /*! DQSGD - Read DQS Gating Delay */ #define DDRPHY_DX8LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX8LCDLR2_DQSGD_MASK) #define DDRPHY_DX8LCDLR2_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX8LCDLR2_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR2_RESERVED_15_9_MASK) #define DDRPHY_DX8LCDLR2_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX8LCDLR2_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR2_RESERVED_24_16_MASK) #define DDRPHY_DX8LCDLR2_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8LCDLR2_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR2_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */ /*! @{ */ #define DDRPHY_DX8LCDLR3_RDQSD_MASK (0x1FFU) #define DDRPHY_DX8LCDLR3_RDQSD_SHIFT (0U) /*! RDQSD - Read DQS Delay */ #define DDRPHY_DX8LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX8LCDLR3_RDQSD_MASK) #define DDRPHY_DX8LCDLR3_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX8LCDLR3_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR3_RESERVED_15_9_MASK) #define DDRPHY_DX8LCDLR3_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX8LCDLR3_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR3_RESERVED_24_16_MASK) #define DDRPHY_DX8LCDLR3_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8LCDLR3_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR3_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */ /*! @{ */ #define DDRPHY_DX8LCDLR4_RDQSND_MASK (0x1FFU) #define DDRPHY_DX8LCDLR4_RDQSND_SHIFT (0U) /*! RDQSND - Read DQSN Delay */ #define DDRPHY_DX8LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX8LCDLR4_RDQSND_MASK) #define DDRPHY_DX8LCDLR4_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX8LCDLR4_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR4_RESERVED_15_9_MASK) #define DDRPHY_DX8LCDLR4_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX8LCDLR4_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR4_RESERVED_24_16_MASK) #define DDRPHY_DX8LCDLR4_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8LCDLR4_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR4_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */ /*! @{ */ #define DDRPHY_DX8LCDLR5_DQSGSD_MASK (0x1FFU) #define DDRPHY_DX8LCDLR5_DQSGSD_SHIFT (0U) /*! DQSGSD - DQS Gating Status Delay */ #define DDRPHY_DX8LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX8LCDLR5_DQSGSD_MASK) #define DDRPHY_DX8LCDLR5_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX8LCDLR5_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR5_RESERVED_15_9_MASK) #define DDRPHY_DX8LCDLR5_RESERVED_24_16_MASK (0x1FF0000U) #define DDRPHY_DX8LCDLR5_RESERVED_24_16_SHIFT (16U) /*! RESERVED_24_16 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR5_RESERVED_24_16_MASK) #define DDRPHY_DX8LCDLR5_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8LCDLR5_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR5_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8MDLR0 - DATX8 n Master Delay Line Register 0 */ /*! @{ */ #define DDRPHY_DX8MDLR0_IPRD_MASK (0x1FFU) #define DDRPHY_DX8MDLR0_IPRD_SHIFT (0U) /*! IPRD - Initial Period */ #define DDRPHY_DX8MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_IPRD_SHIFT)) & DDRPHY_DX8MDLR0_IPRD_MASK) #define DDRPHY_DX8MDLR0_RESERVED_15_9_MASK (0xFE00U) #define DDRPHY_DX8MDLR0_RESERVED_15_9_SHIFT (9U) /*! RESERVED_15_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX8MDLR0_RESERVED_15_9_MASK) #define DDRPHY_DX8MDLR0_TPRD_MASK (0x1FF0000U) #define DDRPHY_DX8MDLR0_TPRD_SHIFT (16U) /*! TPRD - Target Period */ #define DDRPHY_DX8MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_TPRD_SHIFT)) & DDRPHY_DX8MDLR0_TPRD_MASK) #define DDRPHY_DX8MDLR0_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8MDLR0_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX8MDLR0_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8MDLR1 - DATX8 n Master Delay Line Register 1 */ /*! @{ */ #define DDRPHY_DX8MDLR1_MDLD_MASK (0x1FFU) #define DDRPHY_DX8MDLR1_MDLD_SHIFT (0U) /*! MDLD - MDL Delay */ #define DDRPHY_DX8MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR1_MDLD_SHIFT)) & DDRPHY_DX8MDLR1_MDLD_MASK) #define DDRPHY_DX8MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U) #define DDRPHY_DX8MDLR1_RESERVED_31_9_SHIFT (9U) /*! RESERVED_31_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX8MDLR1_RESERVED_31_9_MASK) /*! @} */ /*! @name DX8GTR0 - DATX8 n General Timing Register 0 */ /*! @{ */ #define DDRPHY_DX8GTR0_DGSL_MASK (0x1FU) #define DDRPHY_DX8GTR0_DGSL_SHIFT (0U) /*! DGSL - DQS Gating System Latency */ #define DDRPHY_DX8GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_DGSL_SHIFT)) & DDRPHY_DX8GTR0_DGSL_MASK) #define DDRPHY_DX8GTR0_RESERVED_7_5_MASK (0xE0U) #define DDRPHY_DX8GTR0_RESERVED_7_5_SHIFT (5U) /*! RESERVED_7_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_7_5_MASK) #define DDRPHY_DX8GTR0_RESERVED_12_8_MASK (0x1F00U) #define DDRPHY_DX8GTR0_RESERVED_12_8_SHIFT (8U) /*! RESERVED_12_8 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_12_8_MASK) #define DDRPHY_DX8GTR0_RESERVED_15_13_MASK (0xE000U) #define DDRPHY_DX8GTR0_RESERVED_15_13_SHIFT (13U) /*! RESERVED_15_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_15_13_MASK) #define DDRPHY_DX8GTR0_WLSL_MASK (0xF0000U) #define DDRPHY_DX8GTR0_WLSL_SHIFT (16U) /*! WLSL - Write Leveling System Latency */ #define DDRPHY_DX8GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_WLSL_SHIFT)) & DDRPHY_DX8GTR0_WLSL_MASK) #define DDRPHY_DX8GTR0_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX8GTR0_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_23_20_MASK) #define DDRPHY_DX8GTR0_WDQSL_MASK (0x7000000U) #define DDRPHY_DX8GTR0_WDQSL_SHIFT (24U) /*! WDQSL - DQ Write Path Latency Pipeline */ #define DDRPHY_DX8GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_WDQSL_SHIFT)) & DDRPHY_DX8GTR0_WDQSL_MASK) #define DDRPHY_DX8GTR0_RESERVED_31_24_MASK (0xF8000000U) #define DDRPHY_DX8GTR0_RESERVED_31_24_SHIFT (27U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8RSR0 - DATX8 n Rank Status Register 0 */ /*! @{ */ #define DDRPHY_DX8RSR0_QSGERR_MASK (0xFFFFU) #define DDRPHY_DX8RSR0_QSGERR_SHIFT (0U) /*! QSGERR - DQS Gate Training Error */ #define DDRPHY_DX8RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR0_QSGERR_SHIFT)) & DDRPHY_DX8RSR0_QSGERR_MASK) #define DDRPHY_DX8RSR0_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX8RSR0_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR0_RESERVED_31_16_MASK) /*! @} */ /*! @name DX8RSR1 - DATX8 n Rank Status Register 1 */ /*! @{ */ #define DDRPHY_DX8RSR1_RDLVLERR_MASK (0xFFFFU) #define DDRPHY_DX8RSR1_RDLVLERR_SHIFT (0U) /*! RDLVLERR - Read Leveling Error */ #define DDRPHY_DX8RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX8RSR1_RDLVLERR_MASK) #define DDRPHY_DX8RSR1_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX8RSR1_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR1_RESERVED_31_16_MASK) /*! @} */ /*! @name DX8RSR2 - DATX8 n Rank Status Register 2 */ /*! @{ */ #define DDRPHY_DX8RSR2_WLAWN_MASK (0xFFFFU) #define DDRPHY_DX8RSR2_WLAWN_SHIFT (0U) /*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning */ #define DDRPHY_DX8RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR2_WLAWN_SHIFT)) & DDRPHY_DX8RSR2_WLAWN_MASK) #define DDRPHY_DX8RSR2_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX8RSR2_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR2_RESERVED_31_16_MASK) /*! @} */ /*! @name DX8RSR3 - DATX8 n Rank Status Register 3 */ /*! @{ */ #define DDRPHY_DX8RSR3_WLAERR_MASK (0xFFFFU) #define DDRPHY_DX8RSR3_WLAERR_SHIFT (0U) /*! WLAERR - Write Leveling Adjustment Error */ #define DDRPHY_DX8RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR3_WLAERR_SHIFT)) & DDRPHY_DX8RSR3_WLAERR_MASK) #define DDRPHY_DX8RSR3_RESERVED_31_16_MASK (0xFFFF0000U) #define DDRPHY_DX8RSR3_RESERVED_31_16_SHIFT (16U) /*! RESERVED_31_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR3_RESERVED_31_16_MASK) /*! @} */ /*! @name DX8GSR0 - DATX8 n General Status Register 0 */ /*! @{ */ #define DDRPHY_DX8GSR0_WDQCAL_MASK (0x1U) #define DDRPHY_DX8GSR0_WDQCAL_SHIFT (0U) /*! WDQCAL - Write DQ Calibration */ #define DDRPHY_DX8GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WDQCAL_SHIFT)) & DDRPHY_DX8GSR0_WDQCAL_MASK) #define DDRPHY_DX8GSR0_RDQSCAL_MASK (0x2U) #define DDRPHY_DX8GSR0_RDQSCAL_SHIFT (1U) /*! RDQSCAL - Read DQS Calibration */ #define DDRPHY_DX8GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX8GSR0_RDQSCAL_MASK) #define DDRPHY_DX8GSR0_RDQSNCAL_MASK (0x4U) #define DDRPHY_DX8GSR0_RDQSNCAL_SHIFT (2U) /*! RDQSNCAL - Read DQS# Calibration */ #define DDRPHY_DX8GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX8GSR0_RDQSNCAL_MASK) #define DDRPHY_DX8GSR0_GDQSCAL_MASK (0x8U) #define DDRPHY_DX8GSR0_GDQSCAL_SHIFT (3U) /*! GDQSCAL - Read DQS gating Calibration */ #define DDRPHY_DX8GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX8GSR0_GDQSCAL_MASK) #define DDRPHY_DX8GSR0_WLCAL_MASK (0x10U) #define DDRPHY_DX8GSR0_WLCAL_SHIFT (4U) /*! WLCAL - Write Leveling Calibration */ #define DDRPHY_DX8GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLCAL_SHIFT)) & DDRPHY_DX8GSR0_WLCAL_MASK) #define DDRPHY_DX8GSR0_WLDONE_MASK (0x20U) #define DDRPHY_DX8GSR0_WLDONE_SHIFT (5U) /*! WLDONE - Write Leveling Done */ #define DDRPHY_DX8GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLDONE_SHIFT)) & DDRPHY_DX8GSR0_WLDONE_MASK) #define DDRPHY_DX8GSR0_WLERR_MASK (0x40U) #define DDRPHY_DX8GSR0_WLERR_SHIFT (6U) /*! WLERR - Write Leveling Error */ #define DDRPHY_DX8GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLERR_SHIFT)) & DDRPHY_DX8GSR0_WLERR_MASK) #define DDRPHY_DX8GSR0_WLPRD_MASK (0xFF80U) #define DDRPHY_DX8GSR0_WLPRD_SHIFT (7U) /*! WLPRD - Write Leveling Period */ #define DDRPHY_DX8GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLPRD_SHIFT)) & DDRPHY_DX8GSR0_WLPRD_MASK) #define DDRPHY_DX8GSR0_DPLOCK_MASK (0x10000U) #define DDRPHY_DX8GSR0_DPLOCK_SHIFT (16U) /*! DPLOCK - DATX8 PLL Lock */ #define DDRPHY_DX8GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_DPLOCK_SHIFT)) & DDRPHY_DX8GSR0_DPLOCK_MASK) #define DDRPHY_DX8GSR0_GDQSPRD_MASK (0x3FE0000U) #define DDRPHY_DX8GSR0_GDQSPRD_SHIFT (17U) /*! GDQSPRD - Read DQS gating Period */ #define DDRPHY_DX8GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX8GSR0_GDQSPRD_MASK) #define DDRPHY_DX8GSR0_RESERVED_29_26_MASK (0x3C000000U) #define DDRPHY_DX8GSR0_RESERVED_29_26_SHIFT (26U) /*! RESERVED_29_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX8GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX8GSR0_RESERVED_29_26_MASK) #define DDRPHY_DX8GSR0_WLDQ_MASK (0x40000000U) #define DDRPHY_DX8GSR0_WLDQ_SHIFT (30U) /*! WLDQ - Write Leveling DQ Status */ #define DDRPHY_DX8GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLDQ_SHIFT)) & DDRPHY_DX8GSR0_WLDQ_MASK) #define DDRPHY_DX8GSR0_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8GSR0_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX8GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX8GSR0_RESERVED_31_MASK) /*! @} */ /*! @name DX8GSR1 - DATX8 n General Status Register 1 */ /*! @{ */ #define DDRPHY_DX8GSR1_DLTDONE_MASK (0x1U) #define DDRPHY_DX8GSR1_DLTDONE_SHIFT (0U) /*! DLTDONE - Delay Line Test Done */ #define DDRPHY_DX8GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR1_DLTDONE_SHIFT)) & DDRPHY_DX8GSR1_DLTDONE_MASK) #define DDRPHY_DX8GSR1_DLTCODE_MASK (0x1FFFFFEU) #define DDRPHY_DX8GSR1_DLTCODE_SHIFT (1U) /*! DLTCODE - Delay Line Test Code */ #define DDRPHY_DX8GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR1_DLTCODE_SHIFT)) & DDRPHY_DX8GSR1_DLTCODE_MASK) #define DDRPHY_DX8GSR1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8GSR1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX8GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8GSR1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8GSR2 - DATX8 n General Status Register 2 */ /*! @{ */ #define DDRPHY_DX8GSR2_RDERR_MASK (0x1U) #define DDRPHY_DX8GSR2_RDERR_SHIFT (0U) /*! RDERR - Read Bit Deskew Error */ #define DDRPHY_DX8GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_RDERR_SHIFT)) & DDRPHY_DX8GSR2_RDERR_MASK) #define DDRPHY_DX8GSR2_RDWN_MASK (0x2U) #define DDRPHY_DX8GSR2_RDWN_SHIFT (1U) /*! RDWN - Read Bit Deskew Warning */ #define DDRPHY_DX8GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_RDWN_SHIFT)) & DDRPHY_DX8GSR2_RDWN_MASK) #define DDRPHY_DX8GSR2_WDERR_MASK (0x4U) #define DDRPHY_DX8GSR2_WDERR_SHIFT (2U) /*! WDERR - Write Bit Deskew Error */ #define DDRPHY_DX8GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WDERR_SHIFT)) & DDRPHY_DX8GSR2_WDERR_MASK) #define DDRPHY_DX8GSR2_WDWN_MASK (0x8U) #define DDRPHY_DX8GSR2_WDWN_SHIFT (3U) /*! WDWN - Write Bit Deskew Warning */ #define DDRPHY_DX8GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WDWN_SHIFT)) & DDRPHY_DX8GSR2_WDWN_MASK) #define DDRPHY_DX8GSR2_REERR_MASK (0x10U) #define DDRPHY_DX8GSR2_REERR_SHIFT (4U) /*! REERR - Read Eye Centering Error */ #define DDRPHY_DX8GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_REERR_SHIFT)) & DDRPHY_DX8GSR2_REERR_MASK) #define DDRPHY_DX8GSR2_REWN_MASK (0x20U) #define DDRPHY_DX8GSR2_REWN_SHIFT (5U) /*! REWN - Read Eye Centering Warning */ #define DDRPHY_DX8GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_REWN_SHIFT)) & DDRPHY_DX8GSR2_REWN_MASK) #define DDRPHY_DX8GSR2_WEERR_MASK (0x40U) #define DDRPHY_DX8GSR2_WEERR_SHIFT (6U) /*! WEERR - Write Eye Centering Error */ #define DDRPHY_DX8GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WEERR_SHIFT)) & DDRPHY_DX8GSR2_WEERR_MASK) #define DDRPHY_DX8GSR2_WEWN_MASK (0x80U) #define DDRPHY_DX8GSR2_WEWN_SHIFT (7U) /*! WEWN - Write Eye Centering Warning */ #define DDRPHY_DX8GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WEWN_SHIFT)) & DDRPHY_DX8GSR2_WEWN_MASK) #define DDRPHY_DX8GSR2_ESTAT_MASK (0xF00U) #define DDRPHY_DX8GSR2_ESTAT_SHIFT (8U) /*! ESTAT - Error Status */ #define DDRPHY_DX8GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_ESTAT_SHIFT)) & DDRPHY_DX8GSR2_ESTAT_MASK) #define DDRPHY_DX8GSR2_DQS2DQERR_MASK (0xFF000U) #define DDRPHY_DX8GSR2_DQS2DQERR_SHIFT (12U) /*! DQS2DQERR - Write DQS2DQ Training Error */ #define DDRPHY_DX8GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX8GSR2_DQS2DQERR_MASK) #define DDRPHY_DX8GSR2_SRDERR_MASK (0x100000U) #define DDRPHY_DX8GSR2_SRDERR_SHIFT (20U) /*! SRDERR - Static Read Error */ #define DDRPHY_DX8GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_SRDERR_SHIFT)) & DDRPHY_DX8GSR2_SRDERR_MASK) #define DDRPHY_DX8GSR2_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX8GSR2_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX8GSR2_RESERVED_21_MASK) #define DDRPHY_DX8GSR2_GSDQSCAL_MASK (0x400000U) #define DDRPHY_DX8GSR2_GSDQSCAL_SHIFT (22U) /*! GSDQSCAL - Read DQS Gating Status Calibration */ #define DDRPHY_DX8GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX8GSR2_GSDQSCAL_MASK) #define DDRPHY_DX8GSR2_GSDQSPRD_MASK (0xFF800000U) #define DDRPHY_DX8GSR2_GSDQSPRD_SHIFT (23U) /*! GSDQSPRD - Read DQS gating Status Period */ #define DDRPHY_DX8GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX8GSR2_GSDQSPRD_MASK) /*! @} */ /*! @name DX8GSR3 - DATX8 n General Status Register 3 */ /*! @{ */ #define DDRPHY_DX8GSR3_SRDPC_MASK (0x3U) #define DDRPHY_DX8GSR3_SRDPC_SHIFT (0U) /*! SRDPC - Static Read Delay Pass Count */ #define DDRPHY_DX8GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_SRDPC_SHIFT)) & DDRPHY_DX8GSR3_SRDPC_MASK) #define DDRPHY_DX8GSR3_RESERVED_7_2_MASK (0xFCU) #define DDRPHY_DX8GSR3_RESERVED_7_2_SHIFT (2U) /*! RESERVED_7_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX8GSR3_RESERVED_7_2_MASK) #define DDRPHY_DX8GSR3_HVERR_MASK (0xF00U) #define DDRPHY_DX8GSR3_HVERR_SHIFT (8U) /*! HVERR - Host VREF Training Error */ #define DDRPHY_DX8GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_HVERR_SHIFT)) & DDRPHY_DX8GSR3_HVERR_MASK) #define DDRPHY_DX8GSR3_HVWRN_MASK (0xF000U) #define DDRPHY_DX8GSR3_HVWRN_SHIFT (12U) /*! HVWRN - Host VREF Training Warning */ #define DDRPHY_DX8GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_HVWRN_SHIFT)) & DDRPHY_DX8GSR3_HVWRN_MASK) #define DDRPHY_DX8GSR3_DVERR_MASK (0xF0000U) #define DDRPHY_DX8GSR3_DVERR_SHIFT (16U) /*! DVERR - DRAM VREF Training Error */ #define DDRPHY_DX8GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_DVERR_SHIFT)) & DDRPHY_DX8GSR3_DVERR_MASK) #define DDRPHY_DX8GSR3_DVWRN_MASK (0xF00000U) #define DDRPHY_DX8GSR3_DVWRN_SHIFT (20U) /*! DVWRN - DRAM VREF Training Warning */ #define DDRPHY_DX8GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_DVWRN_SHIFT)) & DDRPHY_DX8GSR3_DVWRN_MASK) #define DDRPHY_DX8GSR3_ESTAT_MASK (0x7000000U) #define DDRPHY_DX8GSR3_ESTAT_SHIFT (24U) /*! ESTAT - VREF Training Error Status Code */ #define DDRPHY_DX8GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_ESTAT_SHIFT)) & DDRPHY_DX8GSR3_ESTAT_MASK) #define DDRPHY_DX8GSR3_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8GSR3_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX8GSR3_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8GSR4 - DATX8 n General Status Register 4 */ /*! @{ */ #define DDRPHY_DX8GSR4_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8GSR4_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_0_MASK) #define DDRPHY_DX8GSR4_RESERVED_1_MASK (0x2U) #define DDRPHY_DX8GSR4_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_1_MASK) #define DDRPHY_DX8GSR4_RESERVED_2_MASK (0x4U) #define DDRPHY_DX8GSR4_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_2_MASK) #define DDRPHY_DX8GSR4_RESERVED_3_MASK (0x8U) #define DDRPHY_DX8GSR4_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_3_MASK) #define DDRPHY_DX8GSR4_RESERVED_4_MASK (0x10U) #define DDRPHY_DX8GSR4_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_4_MASK) #define DDRPHY_DX8GSR4_RESERVED_5_MASK (0x20U) #define DDRPHY_DX8GSR4_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_5_MASK) #define DDRPHY_DX8GSR4_RESERVED_6_MASK (0x40U) #define DDRPHY_DX8GSR4_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_6_MASK) #define DDRPHY_DX8GSR4_RESERVED_15_7_MASK (0xFF80U) #define DDRPHY_DX8GSR4_RESERVED_15_7_SHIFT (7U) /*! RESERVED_15_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_15_7_MASK) #define DDRPHY_DX8GSR4_RESERVED_16_MASK (0x10000U) #define DDRPHY_DX8GSR4_RESERVED_16_SHIFT (16U) /*! RESERVED_16 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_16_MASK) #define DDRPHY_DX8GSR4_RESERVED_25_17_MASK (0x3FE0000U) #define DDRPHY_DX8GSR4_RESERVED_25_17_SHIFT (17U) /*! RESERVED_25_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_25_17_MASK) #define DDRPHY_DX8GSR4_RESERVED_31_26_MASK (0xFC000000U) #define DDRPHY_DX8GSR4_RESERVED_31_26_SHIFT (26U) /*! RESERVED_31_26 - Reserved. Returns zeroes on reads. */ #define DDRPHY_DX8GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_31_26_MASK) /*! @} */ /*! @name DX8GSR5 - DATX8 n General Status Register 5 */ /*! @{ */ #define DDRPHY_DX8GSR5_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8GSR5_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_0_MASK) #define DDRPHY_DX8GSR5_RESERVED_1_MASK (0x2U) #define DDRPHY_DX8GSR5_RESERVED_1_SHIFT (1U) /*! RESERVED_1 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_1_MASK) #define DDRPHY_DX8GSR5_RESERVED_2_MASK (0x4U) #define DDRPHY_DX8GSR5_RESERVED_2_SHIFT (2U) /*! RESERVED_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_2_MASK) #define DDRPHY_DX8GSR5_RESERVED_3_MASK (0x8U) #define DDRPHY_DX8GSR5_RESERVED_3_SHIFT (3U) /*! RESERVED_3 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_3_MASK) #define DDRPHY_DX8GSR5_RESERVED_4_MASK (0x10U) #define DDRPHY_DX8GSR5_RESERVED_4_SHIFT (4U) /*! RESERVED_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_4_MASK) #define DDRPHY_DX8GSR5_RESERVED_5_MASK (0x20U) #define DDRPHY_DX8GSR5_RESERVED_5_SHIFT (5U) /*! RESERVED_5 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_5_MASK) #define DDRPHY_DX8GSR5_RESERVED_6_MASK (0x40U) #define DDRPHY_DX8GSR5_RESERVED_6_SHIFT (6U) /*! RESERVED_6 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_6_MASK) #define DDRPHY_DX8GSR5_RESERVED_7_MASK (0x80U) #define DDRPHY_DX8GSR5_RESERVED_7_SHIFT (7U) /*! RESERVED_7 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_7_MASK) #define DDRPHY_DX8GSR5_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX8GSR5_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_11_8_MASK) #define DDRPHY_DX8GSR5_RESERVED_19_12_MASK (0xFF000U) #define DDRPHY_DX8GSR5_RESERVED_19_12_SHIFT (12U) /*! RESERVED_19_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_19_12_MASK) #define DDRPHY_DX8GSR5_RESERVED_20_MASK (0x100000U) #define DDRPHY_DX8GSR5_RESERVED_20_SHIFT (20U) /*! RESERVED_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_20_MASK) #define DDRPHY_DX8GSR5_RESERVED_21_MASK (0x200000U) #define DDRPHY_DX8GSR5_RESERVED_21_SHIFT (21U) /*! RESERVED_21 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_21_MASK) #define DDRPHY_DX8GSR5_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8GSR5_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_22_MASK) #define DDRPHY_DX8GSR5_RESERVED_31_23_MASK (0xFF800000U) #define DDRPHY_DX8GSR5_RESERVED_31_23_SHIFT (23U) /*! RESERVED_31_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_31_23_MASK) /*! @} */ /*! @name DX8GSR6 - DATX8 n General Status Register 6 */ /*! @{ */ #define DDRPHY_DX8GSR6_RESERVED_1_0_MASK (0x3U) #define DDRPHY_DX8GSR6_RESERVED_1_0_SHIFT (0U) /*! RESERVED_1_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_1_0_MASK) #define DDRPHY_DX8GSR6_RESERVED_3_2_MASK (0xCU) #define DDRPHY_DX8GSR6_RESERVED_3_2_SHIFT (2U) /*! RESERVED_3_2 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_3_2_MASK) #define DDRPHY_DX8GSR6_RESERVED_7_4_MASK (0xF0U) #define DDRPHY_DX8GSR6_RESERVED_7_4_SHIFT (4U) /*! RESERVED_7_4 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_7_4_MASK) #define DDRPHY_DX8GSR6_RESERVED_11_8_MASK (0xF00U) #define DDRPHY_DX8GSR6_RESERVED_11_8_SHIFT (8U) /*! RESERVED_11_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_11_8_MASK) #define DDRPHY_DX8GSR6_RESERVED_15_12_MASK (0xF000U) #define DDRPHY_DX8GSR6_RESERVED_15_12_SHIFT (12U) /*! RESERVED_15_12 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_15_12_MASK) #define DDRPHY_DX8GSR6_RESERVED_19_15_MASK (0xF0000U) #define DDRPHY_DX8GSR6_RESERVED_19_15_SHIFT (16U) /*! RESERVED_19_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_19_15_MASK) #define DDRPHY_DX8GSR6_RESERVED_23_20_MASK (0xF00000U) #define DDRPHY_DX8GSR6_RESERVED_23_20_SHIFT (20U) /*! RESERVED_23_20 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_23_20_MASK) #define DDRPHY_DX8GSR6_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8GSR6_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SL0OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */ /*! @{ */ #define DDRPHY_DX8SL0OSC_OSCEN_MASK (0x1U) #define DDRPHY_DX8SL0OSC_OSCEN_SHIFT (0U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_DX8SL0OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL0OSC_OSCEN_MASK) #define DDRPHY_DX8SL0OSC_OSCDIV_MASK (0x1EU) #define DDRPHY_DX8SL0OSC_OSCDIV_SHIFT (1U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_DX8SL0OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL0OSC_OSCDIV_MASK) #define DDRPHY_DX8SL0OSC_OSCWDL_MASK (0x60U) #define DDRPHY_DX8SL0OSC_OSCWDL_SHIFT (5U) /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select */ #define DDRPHY_DX8SL0OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL0OSC_OSCWDL_MASK) #define DDRPHY_DX8SL0OSC_RESERVED_8_7_MASK (0x180U) #define DDRPHY_DX8SL0OSC_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL0OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL0OSC_RESERVED_8_7_MASK) #define DDRPHY_DX8SL0OSC_OSCWDDL_MASK (0x600U) #define DDRPHY_DX8SL0OSC_OSCWDDL_SHIFT (9U) /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select */ #define DDRPHY_DX8SL0OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL0OSC_OSCWDDL_MASK) #define DDRPHY_DX8SL0OSC_RESERVED_12_11_MASK (0x1800U) #define DDRPHY_DX8SL0OSC_RESERVED_12_11_SHIFT (11U) /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL0OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL0OSC_RESERVED_12_11_MASK) #define DDRPHY_DX8SL0OSC_DLTMODE_MASK (0x2000U) #define DDRPHY_DX8SL0OSC_DLTMODE_SHIFT (13U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_DX8SL0OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL0OSC_DLTMODE_MASK) #define DDRPHY_DX8SL0OSC_DLTST_MASK (0x4000U) #define DDRPHY_DX8SL0OSC_DLTST_SHIFT (14U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_DX8SL0OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_DLTST_SHIFT)) & DDRPHY_DX8SL0OSC_DLTST_MASK) #define DDRPHY_DX8SL0OSC_PHYFRST_MASK (0x8000U) #define DDRPHY_DX8SL0OSC_PHYFRST_SHIFT (15U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_DX8SL0OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL0OSC_PHYFRST_MASK) #define DDRPHY_DX8SL0OSC_PHYHRST_MASK (0x10000U) #define DDRPHY_DX8SL0OSC_PHYHRST_SHIFT (16U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_DX8SL0OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL0OSC_PHYHRST_MASK) #define DDRPHY_DX8SL0OSC_LBDQSS_MASK (0x20000U) #define DDRPHY_DX8SL0OSC_LBDQSS_SHIFT (17U) /*! LBDQSS - Loopback DQS Shift */ #define DDRPHY_DX8SL0OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL0OSC_LBDQSS_MASK) #define DDRPHY_DX8SL0OSC_LBGDQS_MASK (0xC0000U) #define DDRPHY_DX8SL0OSC_LBGDQS_SHIFT (18U) /*! LBGDQS - Loopback DQS Gating */ #define DDRPHY_DX8SL0OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL0OSC_LBGDQS_MASK) #define DDRPHY_DX8SL0OSC_LBGSDQS_MASK (0x100000U) #define DDRPHY_DX8SL0OSC_LBGSDQS_SHIFT (20U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value */ #define DDRPHY_DX8SL0OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL0OSC_LBGSDQS_MASK) #define DDRPHY_DX8SL0OSC_LBMODE_MASK (0x200000U) #define DDRPHY_DX8SL0OSC_LBMODE_SHIFT (21U) /*! LBMODE - Loopback Mode */ #define DDRPHY_DX8SL0OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL0OSC_LBMODE_MASK) #define DDRPHY_DX8SL0OSC_CLKLEVEL_MASK (0xC00000U) #define DDRPHY_DX8SL0OSC_CLKLEVEL_SHIFT (22U) /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled. */ #define DDRPHY_DX8SL0OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL0OSC_CLKLEVEL_MASK) #define DDRPHY_DX8SL0OSC_GATEDXCTLCLK_MASK (0x3000000U) #define DDRPHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT (24U) /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk */ #define DDRPHY_DX8SL0OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL0OSC_GATEDXCTLCLK_MASK) #define DDRPHY_DX8SL0OSC_GATEDXDDRCLK_MASK (0xC000000U) #define DDRPHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT (26U) /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk */ #define DDRPHY_DX8SL0OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL0OSC_GATEDXDDRCLK_MASK) #define DDRPHY_DX8SL0OSC_GATEDXRDCLK_MASK (0x30000000U) #define DDRPHY_DX8SL0OSC_GATEDXRDCLK_SHIFT (28U) /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk */ #define DDRPHY_DX8SL0OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL0OSC_GATEDXRDCLK_MASK) #define DDRPHY_DX8SL0OSC_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8SL0OSC_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL0OSC_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8SL0PLLCR0 - DAXT8 0-1 PLL Control Register 0 */ /*! @{ */ #define DDRPHY_DX8SL0PLLCR0_DTC_MASK (0xFU) #define DDRPHY_DX8SL0PLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_DX8SL0PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_DTC_MASK) #define DDRPHY_DX8SL0PLLCR0_ATC_MASK (0xF0U) #define DDRPHY_DX8SL0PLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_DX8SL0PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_ATC_MASK) #define DDRPHY_DX8SL0PLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_DX8SL0PLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable (ATOEN) */ #define DDRPHY_DX8SL0PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL0PLLCR0_ATOEN_MASK) #define DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_MASK) #define DDRPHY_DX8SL0PLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_DX8SL0PLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_DX8SL0PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL0PLLCR0_GSHIFT_MASK) #define DDRPHY_DX8SL0PLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_DX8SL0PLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_DX8SL0PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_CPIC_MASK) #define DDRPHY_DX8SL0PLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_DX8SL0PLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_DX8SL0PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_CPPC_MASK) #define DDRPHY_DX8SL0PLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_DX8SL0PLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_DX8SL0PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL0PLLCR0_RLOCKM_MASK) #define DDRPHY_DX8SL0PLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_DX8SL0PLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_DX8SL0PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL0PLLCR0_FRQSEL_MASK) #define DDRPHY_DX8SL0PLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_DX8SL0PLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_DX8SL0PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL0PLLCR0_RSTOPM_MASK) #define DDRPHY_DX8SL0PLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_DX8SL0PLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_DX8SL0PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL0PLLCR0_PLLPD_MASK) #define DDRPHY_DX8SL0PLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_DX8SL0PLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_DX8SL0PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL0PLLCR0_PLLRST_MASK) #define DDRPHY_DX8SL0PLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_DX8SL0PLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_DX8SL0PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL0PLLCR0_PLLBYP_MASK) /*! @} */ /*! @name DX8SL0PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL0PLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_DX8SL0PLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_DX8SL0PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL0PLLCR1_LOCKDS_MASK) #define DDRPHY_DX8SL0PLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_DX8SL0PLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_DX8SL0PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL0PLLCR1_LOCKCS_MASK) #define DDRPHY_DX8SL0PLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_DX8SL0PLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_DX8SL0PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL0PLLCR1_LOCKPS_MASK) #define DDRPHY_DX8SL0PLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_DX8SL0PLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_DX8SL0PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL0PLLCR1_BYPVDD_MASK) #define DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_DX8SL0PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_MASK) #define DDRPHY_DX8SL0PLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_DX8SL0PLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_DX8SL0PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL0PLLCR1_BYPVREGCP_MASK) #define DDRPHY_DX8SL0PLLCR1_PLLPROG_MASK (0x3FFFC0U) #define DDRPHY_DX8SL0PLLCR1_PLLPROG_SHIFT (6U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_DX8SL0PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL0PLLCR1_PLLPROG_MASK) #define DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8SL0PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name DX8SL0PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name DX8SL0PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name DX8SL0PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DX8SL0DQSCTL - DATX8 0-1 DQS Control Register */ /*! @{ */ #define DDRPHY_DX8SL0DQSCTL_DQSRES_MASK (0xFU) #define DDRPHY_DX8SL0DQSCTL_DQSRES_SHIFT (0U) /*! DQSRES - DQS Resistor */ #define DDRPHY_DX8SL0DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DQSRES_MASK) #define DDRPHY_DX8SL0DQSCTL_DQSNRES_MASK (0xF0U) #define DDRPHY_DX8SL0DQSCTL_DQSNRES_SHIFT (4U) /*! DQSNRES - DQS_N Resistor */ #define DDRPHY_DX8SL0DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DQSNRES_MASK) #define DDRPHY_DX8SL0DQSCTL_DXSR_MASK (0x300U) #define DDRPHY_DX8SL0DQSCTL_DXSR_SHIFT (8U) /*! DXSR - Data Slew Rate */ #define DDRPHY_DX8SL0DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DXSR_MASK) #define DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_MASK (0x1C00U) #define DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT (10U) /*! RESERVED_12_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_MASK) #define DDRPHY_DX8SL0DQSCTL_UDQIOM_MASK (0x2000U) #define DDRPHY_DX8SL0DQSCTL_UDQIOM_SHIFT (13U) /*! UDQIOM - Unused DQ I/O Mode */ #define DDRPHY_DX8SL0DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL0DQSCTL_UDQIOM_MASK) #define DDRPHY_DX8SL0DQSCTL_QSCNTEN_MASK (0x4000U) #define DDRPHY_DX8SL0DQSCTL_QSCNTEN_SHIFT (14U) /*! QSCNTEN - QS Counter Enable */ #define DDRPHY_DX8SL0DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL0DQSCTL_QSCNTEN_MASK) #define DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_MASK (0x18000U) #define DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT (15U) /*! RESERVED_16_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_MASK) #define DDRPHY_DX8SL0DQSCTL_LPIOPD_MASK (0x20000U) #define DDRPHY_DX8SL0DQSCTL_LPIOPD_SHIFT (17U) /*! LPIOPD - Low Power I/O Power Down */ #define DDRPHY_DX8SL0DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL0DQSCTL_LPIOPD_MASK) #define DDRPHY_DX8SL0DQSCTL_LPPLLPD_MASK (0x40000U) #define DDRPHY_DX8SL0DQSCTL_LPPLLPD_SHIFT (18U) /*! LPPLLPD - Low Power PLL Power Down */ #define DDRPHY_DX8SL0DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL0DQSCTL_LPPLLPD_MASK) #define DDRPHY_DX8SL0DQSCTL_DQSGX_MASK (0x180000U) #define DDRPHY_DX8SL0DQSCTL_DQSGX_SHIFT (19U) /*! DQSGX - DQS Gate Extension */ #define DDRPHY_DX8SL0DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DQSGX_MASK) #define DDRPHY_DX8SL0DQSCTL_WRRMODE_MASK (0x200000U) #define DDRPHY_DX8SL0DQSCTL_WRRMODE_SHIFT (21U) /*! WRRMODE - Write Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL0DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL0DQSCTL_WRRMODE_MASK) #define DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_MASK) #define DDRPHY_DX8SL0DQSCTL_RRRMODE_MASK (0x1000000U) #define DDRPHY_DX8SL0DQSCTL_RRRMODE_SHIFT (24U) /*! RRRMODE - Read Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL0DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RRRMODE_MASK) #define DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL0TRNCTL - DATX8 0-1 Training Control Register */ /*! @{ */ #define DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL0DDLCTL - DATX8 0-1 DDL Control Register */ /*! @{ */ #define DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_MASK (0x3U) #define DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_SHIFT (0U) /*! DDLBYPMODE - Controls DDL Bypass Mode */ #define DDRPHY_DX8SL0DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_MASK) #define DDRPHY_DX8SL0DDLCTL_DXDDLBYP_MASK (0x3FFFCU) #define DDRPHY_DX8SL0DDLCTL_DXDDLBYP_SHIFT (2U) /*! DXDDLBYP - DATX8 DDL Bypass */ #define DDRPHY_DX8SL0DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DXDDLBYP_MASK) #define DDRPHY_DX8SL0DDLCTL_DXDDLLD_MASK (0x7C0000U) #define DDRPHY_DX8SL0DDLCTL_DXDDLLD_SHIFT (18U) /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load */ #define DDRPHY_DX8SL0DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DXDDLLD_MASK) #define DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_MASK (0x1800000U) #define DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_SHIFT (23U) /*! RESERVED_24_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_MASK) #define DDRPHY_DX8SL0DDLCTL_DXDDLLDT_MASK (0x2000000U) #define DDRPHY_DX8SL0DDLCTL_DXDDLLDT_SHIFT (25U) /*! DXDDLLDT - DX DDL Load Type */ #define DDRPHY_DX8SL0DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DXDDLLDT_MASK) #define DDRPHY_DX8SL0DDLCTL_DLYLDTM_MASK (0x4000000U) #define DDRPHY_DX8SL0DDLCTL_DLYLDTM_SHIFT (26U) /*! DLYLDTM - Delay Load Timing */ #define DDRPHY_DX8SL0DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DLYLDTM_MASK) #define DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8SL0DXCTL1 - DATX8 0-1 DX Control Register 1 */ /*! @{ */ #define DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_MASK (0xFFFFU) #define DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_SHIFT (0U) /*! RESERVED_15_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_MASK) #define DDRPHY_DX8SL0DXCTL1_DXTMODE_MASK (0x10000U) #define DDRPHY_DX8SL0DXCTL1_DXTMODE_SHIFT (16U) /*! DXTMODE - DATX8 Test Mode */ #define DDRPHY_DX8SL0DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXTMODE_MASK) #define DDRPHY_DX8SL0DXCTL1_DXGDBYP_MASK (0x20000U) #define DDRPHY_DX8SL0DXCTL1_DXGDBYP_SHIFT (17U) /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode */ #define DDRPHY_DX8SL0DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXGDBYP_MASK) #define DDRPHY_DX8SL0DXCTL1_DXQSDBYP_MASK (0x40000U) #define DDRPHY_DX8SL0DXCTL1_DXQSDBYP_SHIFT (18U) /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode */ #define DDRPHY_DX8SL0DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXQSDBYP_MASK) #define DDRPHY_DX8SL0DXCTL1_DXGSMD_MASK (0x80000U) #define DDRPHY_DX8SL0DXCTL1_DXGSMD_SHIFT (19U) /*! DXGSMD - Read DQS Gating Status Mode */ #define DDRPHY_DX8SL0DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXGSMD_MASK) #define DDRPHY_DX8SL0DXCTL1_DXDTOSEL_MASK (0x300000U) #define DDRPHY_DX8SL0DXCTL1_DXDTOSEL_SHIFT (20U) /*! DXDTOSEL - DATX8 Digital Test Output Select */ #define DDRPHY_DX8SL0DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXDTOSEL_MASK) #define DDRPHY_DX8SL0DXCTL1_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8SL0DXCTL1_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL0DXCTL1_RESERVED_22_MASK) #define DDRPHY_DX8SL0DXCTL1_DXRCLKMD_MASK (0x800000U) #define DDRPHY_DX8SL0DXCTL1_DXRCLKMD_SHIFT (23U) /*! DXRCLKMD - DATX8 Read Clock Mode */ #define DDRPHY_DX8SL0DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXRCLKMD_MASK) #define DDRPHY_DX8SL0DXCTL1_DXCALCLK_MASK (0x1000000U) #define DDRPHY_DX8SL0DXCTL1_DXCALCLK_SHIFT (24U) /*! DXCALCLK - DATX Calibration Clock Select */ #define DDRPHY_DX8SL0DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXCALCLK_MASK) #define DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL0DXCTL2 - DATX8 0-1 DX Control Register 2 */ /*! @{ */ #define DDRPHY_DX8SL0DXCTL2_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8SL0DXCTL2_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_0_MASK) #define DDRPHY_DX8SL0DXCTL2_DQSGLB_MASK (0x6U) #define DDRPHY_DX8SL0DXCTL2_DQSGLB_SHIFT (1U) /*! DQSGLB - Read DQS Gate I/O Loopback */ #define DDRPHY_DX8SL0DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL0DXCTL2_DQSGLB_MASK) #define DDRPHY_DX8SL0DXCTL2_DISRST_MASK (0x8U) #define DDRPHY_DX8SL0DXCTL2_DISRST_SHIFT (3U) /*! DISRST - Disables the Read FIFO Reset */ #define DDRPHY_DX8SL0DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL0DXCTL2_DISRST_MASK) #define DDRPHY_DX8SL0DXCTL2_RDMODE_MASK (0x30U) #define DDRPHY_DX8SL0DXCTL2_RDMODE_SHIFT (4U) /*! RDMODE - DATX8 Receive FIFO Read Mode */ #define DDRPHY_DX8SL0DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RDMODE_MASK) #define DDRPHY_DX8SL0DXCTL2_PRFBYP_MASK (0x40U) #define DDRPHY_DX8SL0DXCTL2_PRFBYP_SHIFT (6U) /*! PRFBYP - PUB Read FIFO Bypass */ #define DDRPHY_DX8SL0DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL0DXCTL2_PRFBYP_MASK) #define DDRPHY_DX8SL0DXCTL2_WDBI_MASK (0x80U) #define DDRPHY_DX8SL0DXCTL2_WDBI_SHIFT (7U) /*! WDBI - Write Data Bus Inversion Enable */ #define DDRPHY_DX8SL0DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL0DXCTL2_WDBI_MASK) #define DDRPHY_DX8SL0DXCTL2_RDBI_MASK (0x100U) #define DDRPHY_DX8SL0DXCTL2_RDBI_SHIFT (8U) /*! RDBI - Read Data Bus Inversion Enable */ #define DDRPHY_DX8SL0DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RDBI_MASK) #define DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U) #define DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT (9U) /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold */ #define DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK) #define DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_MASK (0x6000U) #define DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT (13U) /*! RESERVED_14_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_MASK) #define DDRPHY_DX8SL0DXCTL2_IOLB_MASK (0x8000U) #define DDRPHY_DX8SL0DXCTL2_IOLB_SHIFT (15U) /*! IOLB - I/O Loopback Select */ #define DDRPHY_DX8SL0DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL0DXCTL2_IOLB_MASK) #define DDRPHY_DX8SL0DXCTL2_IOAG_MASK (0x10000U) #define DDRPHY_DX8SL0DXCTL2_IOAG_SHIFT (16U) /*! IOAG - I/O Assisted Gate Select */ #define DDRPHY_DX8SL0DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL0DXCTL2_IOAG_MASK) #define DDRPHY_DX8SL0DXCTL2_RESERVED_17_MASK (0x20000U) #define DDRPHY_DX8SL0DXCTL2_RESERVED_17_SHIFT (17U) /*! RESERVED_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_17_MASK) #define DDRPHY_DX8SL0DXCTL2_PREOEX_MASK (0xC0000U) #define DDRPHY_DX8SL0DXCTL2_PREOEX_SHIFT (18U) /*! PREOEX - OE Extension during Pre-amble */ #define DDRPHY_DX8SL0DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL0DXCTL2_PREOEX_MASK) #define DDRPHY_DX8SL0DXCTL2_POSOEX_MASK (0x700000U) #define DDRPHY_DX8SL0DXCTL2_POSOEX_SHIFT (20U) /*! POSOEX - OX Extension during Post-amble */ #define DDRPHY_DX8SL0DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL0DXCTL2_POSOEX_MASK) #define DDRPHY_DX8SL0DXCTL2_CRDEN_MASK (0x800000U) #define DDRPHY_DX8SL0DXCTL2_CRDEN_SHIFT (23U) /*! CRDEN - Configurable Read Data Enable */ #define DDRPHY_DX8SL0DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL0DXCTL2_CRDEN_MASK) #define DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SL0IOCR - DATX8 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX8SL0IOCR_DXRXM_MASK (0x7FFU) #define DDRPHY_DX8SL0IOCR_DXRXM_SHIFT (0U) /*! DXRXM - DX IO Receiver Mode */ #define DDRPHY_DX8SL0IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXRXM_MASK) #define DDRPHY_DX8SL0IOCR_DXTXM_MASK (0x3FF800U) #define DDRPHY_DX8SL0IOCR_DXTXM_SHIFT (11U) /*! DXTXM - DX IO Transmitter Mode */ #define DDRPHY_DX8SL0IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXTXM_MASK) #define DDRPHY_DX8SL0IOCR_DXIOM_MASK (0x1C00000U) #define DDRPHY_DX8SL0IOCR_DXIOM_SHIFT (22U) /*! DXIOM - DX IO Mode */ #define DDRPHY_DX8SL0IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXIOM_MASK) #define DDRPHY_DX8SL0IOCR_DXVREFIOM_MASK (0xE000000U) #define DDRPHY_DX8SL0IOCR_DXVREFIOM_SHIFT (25U) /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring */ #define DDRPHY_DX8SL0IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXVREFIOM_MASK) #define DDRPHY_DX8SL0IOCR_DXDACRANGE_MASK (0x70000000U) #define DDRPHY_DX8SL0IOCR_DXDACRANGE_SHIFT (28U) /*! DXDACRANGE - PVREF_DAC REFSEL range select */ #define DDRPHY_DX8SL0IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL0IOCR_DXDACRANGE_MASK) #define DDRPHY_DX8SL0IOCR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8SL0IOCR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL0IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL0IOCR_RESERVED_31_MASK) /*! @} */ /*! @name DX4SL0IOCR - DATX4 Slice 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX4SL0IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX4SL0IOCR_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4SL0IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL0IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL0IOCR_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL1OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */ /*! @{ */ #define DDRPHY_DX8SL1OSC_OSCEN_MASK (0x1U) #define DDRPHY_DX8SL1OSC_OSCEN_SHIFT (0U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_DX8SL1OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL1OSC_OSCEN_MASK) #define DDRPHY_DX8SL1OSC_OSCDIV_MASK (0x1EU) #define DDRPHY_DX8SL1OSC_OSCDIV_SHIFT (1U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_DX8SL1OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL1OSC_OSCDIV_MASK) #define DDRPHY_DX8SL1OSC_OSCWDL_MASK (0x60U) #define DDRPHY_DX8SL1OSC_OSCWDL_SHIFT (5U) /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select */ #define DDRPHY_DX8SL1OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL1OSC_OSCWDL_MASK) #define DDRPHY_DX8SL1OSC_RESERVED_8_7_MASK (0x180U) #define DDRPHY_DX8SL1OSC_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL1OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL1OSC_RESERVED_8_7_MASK) #define DDRPHY_DX8SL1OSC_OSCWDDL_MASK (0x600U) #define DDRPHY_DX8SL1OSC_OSCWDDL_SHIFT (9U) /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select */ #define DDRPHY_DX8SL1OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL1OSC_OSCWDDL_MASK) #define DDRPHY_DX8SL1OSC_RESERVED_12_11_MASK (0x1800U) #define DDRPHY_DX8SL1OSC_RESERVED_12_11_SHIFT (11U) /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL1OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL1OSC_RESERVED_12_11_MASK) #define DDRPHY_DX8SL1OSC_DLTMODE_MASK (0x2000U) #define DDRPHY_DX8SL1OSC_DLTMODE_SHIFT (13U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_DX8SL1OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL1OSC_DLTMODE_MASK) #define DDRPHY_DX8SL1OSC_DLTST_MASK (0x4000U) #define DDRPHY_DX8SL1OSC_DLTST_SHIFT (14U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_DX8SL1OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_DLTST_SHIFT)) & DDRPHY_DX8SL1OSC_DLTST_MASK) #define DDRPHY_DX8SL1OSC_PHYFRST_MASK (0x8000U) #define DDRPHY_DX8SL1OSC_PHYFRST_SHIFT (15U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_DX8SL1OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL1OSC_PHYFRST_MASK) #define DDRPHY_DX8SL1OSC_PHYHRST_MASK (0x10000U) #define DDRPHY_DX8SL1OSC_PHYHRST_SHIFT (16U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_DX8SL1OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL1OSC_PHYHRST_MASK) #define DDRPHY_DX8SL1OSC_LBDQSS_MASK (0x20000U) #define DDRPHY_DX8SL1OSC_LBDQSS_SHIFT (17U) /*! LBDQSS - Loopback DQS Shift */ #define DDRPHY_DX8SL1OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL1OSC_LBDQSS_MASK) #define DDRPHY_DX8SL1OSC_LBGDQS_MASK (0xC0000U) #define DDRPHY_DX8SL1OSC_LBGDQS_SHIFT (18U) /*! LBGDQS - Loopback DQS Gating */ #define DDRPHY_DX8SL1OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL1OSC_LBGDQS_MASK) #define DDRPHY_DX8SL1OSC_LBGSDQS_MASK (0x100000U) #define DDRPHY_DX8SL1OSC_LBGSDQS_SHIFT (20U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value */ #define DDRPHY_DX8SL1OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL1OSC_LBGSDQS_MASK) #define DDRPHY_DX8SL1OSC_LBMODE_MASK (0x200000U) #define DDRPHY_DX8SL1OSC_LBMODE_SHIFT (21U) /*! LBMODE - Loopback Mode */ #define DDRPHY_DX8SL1OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL1OSC_LBMODE_MASK) #define DDRPHY_DX8SL1OSC_CLKLEVEL_MASK (0xC00000U) #define DDRPHY_DX8SL1OSC_CLKLEVEL_SHIFT (22U) /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled. */ #define DDRPHY_DX8SL1OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL1OSC_CLKLEVEL_MASK) #define DDRPHY_DX8SL1OSC_GATEDXCTLCLK_MASK (0x3000000U) #define DDRPHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT (24U) /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk */ #define DDRPHY_DX8SL1OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL1OSC_GATEDXCTLCLK_MASK) #define DDRPHY_DX8SL1OSC_GATEDXDDRCLK_MASK (0xC000000U) #define DDRPHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT (26U) /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk */ #define DDRPHY_DX8SL1OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL1OSC_GATEDXDDRCLK_MASK) #define DDRPHY_DX8SL1OSC_GATEDXRDCLK_MASK (0x30000000U) #define DDRPHY_DX8SL1OSC_GATEDXRDCLK_SHIFT (28U) /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk */ #define DDRPHY_DX8SL1OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL1OSC_GATEDXRDCLK_MASK) #define DDRPHY_DX8SL1OSC_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8SL1OSC_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL1OSC_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8SL1PLLCR0 - DAXT8 0-1 PLL Control Register 0 */ /*! @{ */ #define DDRPHY_DX8SL1PLLCR0_DTC_MASK (0xFU) #define DDRPHY_DX8SL1PLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_DX8SL1PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_DTC_MASK) #define DDRPHY_DX8SL1PLLCR0_ATC_MASK (0xF0U) #define DDRPHY_DX8SL1PLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_DX8SL1PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_ATC_MASK) #define DDRPHY_DX8SL1PLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_DX8SL1PLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable (ATOEN) */ #define DDRPHY_DX8SL1PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL1PLLCR0_ATOEN_MASK) #define DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_MASK) #define DDRPHY_DX8SL1PLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_DX8SL1PLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_DX8SL1PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL1PLLCR0_GSHIFT_MASK) #define DDRPHY_DX8SL1PLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_DX8SL1PLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_DX8SL1PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_CPIC_MASK) #define DDRPHY_DX8SL1PLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_DX8SL1PLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_DX8SL1PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_CPPC_MASK) #define DDRPHY_DX8SL1PLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_DX8SL1PLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_DX8SL1PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL1PLLCR0_RLOCKM_MASK) #define DDRPHY_DX8SL1PLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_DX8SL1PLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_DX8SL1PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL1PLLCR0_FRQSEL_MASK) #define DDRPHY_DX8SL1PLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_DX8SL1PLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_DX8SL1PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL1PLLCR0_RSTOPM_MASK) #define DDRPHY_DX8SL1PLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_DX8SL1PLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_DX8SL1PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL1PLLCR0_PLLPD_MASK) #define DDRPHY_DX8SL1PLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_DX8SL1PLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_DX8SL1PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL1PLLCR0_PLLRST_MASK) #define DDRPHY_DX8SL1PLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_DX8SL1PLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_DX8SL1PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL1PLLCR0_PLLBYP_MASK) /*! @} */ /*! @name DX8SL1PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL1PLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_DX8SL1PLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_DX8SL1PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL1PLLCR1_LOCKDS_MASK) #define DDRPHY_DX8SL1PLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_DX8SL1PLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_DX8SL1PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL1PLLCR1_LOCKCS_MASK) #define DDRPHY_DX8SL1PLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_DX8SL1PLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_DX8SL1PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL1PLLCR1_LOCKPS_MASK) #define DDRPHY_DX8SL1PLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_DX8SL1PLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_DX8SL1PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL1PLLCR1_BYPVDD_MASK) #define DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_DX8SL1PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_MASK) #define DDRPHY_DX8SL1PLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_DX8SL1PLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_DX8SL1PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL1PLLCR1_BYPVREGCP_MASK) #define DDRPHY_DX8SL1PLLCR1_PLLPROG_MASK (0x3FFFC0U) #define DDRPHY_DX8SL1PLLCR1_PLLPROG_SHIFT (6U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_DX8SL1PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL1PLLCR1_PLLPROG_MASK) #define DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8SL1PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name DX8SL1PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name DX8SL1PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name DX8SL1PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DX8SL1DQSCTL - DATX8 0-1 DQS Control Register */ /*! @{ */ #define DDRPHY_DX8SL1DQSCTL_DQSRES_MASK (0xFU) #define DDRPHY_DX8SL1DQSCTL_DQSRES_SHIFT (0U) /*! DQSRES - DQS Resistor */ #define DDRPHY_DX8SL1DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DQSRES_MASK) #define DDRPHY_DX8SL1DQSCTL_DQSNRES_MASK (0xF0U) #define DDRPHY_DX8SL1DQSCTL_DQSNRES_SHIFT (4U) /*! DQSNRES - DQS_N Resistor */ #define DDRPHY_DX8SL1DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DQSNRES_MASK) #define DDRPHY_DX8SL1DQSCTL_DXSR_MASK (0x300U) #define DDRPHY_DX8SL1DQSCTL_DXSR_SHIFT (8U) /*! DXSR - Data Slew Rate */ #define DDRPHY_DX8SL1DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DXSR_MASK) #define DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_MASK (0x1C00U) #define DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT (10U) /*! RESERVED_12_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_MASK) #define DDRPHY_DX8SL1DQSCTL_UDQIOM_MASK (0x2000U) #define DDRPHY_DX8SL1DQSCTL_UDQIOM_SHIFT (13U) /*! UDQIOM - Unused DQ I/O Mode */ #define DDRPHY_DX8SL1DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL1DQSCTL_UDQIOM_MASK) #define DDRPHY_DX8SL1DQSCTL_QSCNTEN_MASK (0x4000U) #define DDRPHY_DX8SL1DQSCTL_QSCNTEN_SHIFT (14U) /*! QSCNTEN - QS Counter Enable */ #define DDRPHY_DX8SL1DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL1DQSCTL_QSCNTEN_MASK) #define DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_MASK (0x18000U) #define DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT (15U) /*! RESERVED_16_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_MASK) #define DDRPHY_DX8SL1DQSCTL_LPIOPD_MASK (0x20000U) #define DDRPHY_DX8SL1DQSCTL_LPIOPD_SHIFT (17U) /*! LPIOPD - Low Power I/O Power Down */ #define DDRPHY_DX8SL1DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL1DQSCTL_LPIOPD_MASK) #define DDRPHY_DX8SL1DQSCTL_LPPLLPD_MASK (0x40000U) #define DDRPHY_DX8SL1DQSCTL_LPPLLPD_SHIFT (18U) /*! LPPLLPD - Low Power PLL Power Down */ #define DDRPHY_DX8SL1DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL1DQSCTL_LPPLLPD_MASK) #define DDRPHY_DX8SL1DQSCTL_DQSGX_MASK (0x180000U) #define DDRPHY_DX8SL1DQSCTL_DQSGX_SHIFT (19U) /*! DQSGX - DQS Gate Extension */ #define DDRPHY_DX8SL1DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DQSGX_MASK) #define DDRPHY_DX8SL1DQSCTL_WRRMODE_MASK (0x200000U) #define DDRPHY_DX8SL1DQSCTL_WRRMODE_SHIFT (21U) /*! WRRMODE - Write Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL1DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL1DQSCTL_WRRMODE_MASK) #define DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_MASK) #define DDRPHY_DX8SL1DQSCTL_RRRMODE_MASK (0x1000000U) #define DDRPHY_DX8SL1DQSCTL_RRRMODE_SHIFT (24U) /*! RRRMODE - Read Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL1DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RRRMODE_MASK) #define DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL1TRNCTL - DATX8 0-1 Training Control Register */ /*! @{ */ #define DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL1DDLCTL - DATX8 0-1 DDL Control Register */ /*! @{ */ #define DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_MASK (0x3U) #define DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_SHIFT (0U) /*! DDLBYPMODE - Controls DDL Bypass Mode */ #define DDRPHY_DX8SL1DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_MASK) #define DDRPHY_DX8SL1DDLCTL_DXDDLBYP_MASK (0x3FFFCU) #define DDRPHY_DX8SL1DDLCTL_DXDDLBYP_SHIFT (2U) /*! DXDDLBYP - DATX8 DDL Bypass */ #define DDRPHY_DX8SL1DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DXDDLBYP_MASK) #define DDRPHY_DX8SL1DDLCTL_DXDDLLD_MASK (0x7C0000U) #define DDRPHY_DX8SL1DDLCTL_DXDDLLD_SHIFT (18U) /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load */ #define DDRPHY_DX8SL1DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DXDDLLD_MASK) #define DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_MASK (0x1800000U) #define DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_SHIFT (23U) /*! RESERVED_24_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_MASK) #define DDRPHY_DX8SL1DDLCTL_DXDDLLDT_MASK (0x2000000U) #define DDRPHY_DX8SL1DDLCTL_DXDDLLDT_SHIFT (25U) /*! DXDDLLDT - DX DDL Load Type */ #define DDRPHY_DX8SL1DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DXDDLLDT_MASK) #define DDRPHY_DX8SL1DDLCTL_DLYLDTM_MASK (0x4000000U) #define DDRPHY_DX8SL1DDLCTL_DLYLDTM_SHIFT (26U) /*! DLYLDTM - Delay Load Timing */ #define DDRPHY_DX8SL1DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DLYLDTM_MASK) #define DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8SL1DXCTL1 - DATX8 0-1 DX Control Register 1 */ /*! @{ */ #define DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_MASK (0xFFFFU) #define DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_SHIFT (0U) /*! RESERVED_15_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_MASK) #define DDRPHY_DX8SL1DXCTL1_DXTMODE_MASK (0x10000U) #define DDRPHY_DX8SL1DXCTL1_DXTMODE_SHIFT (16U) /*! DXTMODE - DATX8 Test Mode */ #define DDRPHY_DX8SL1DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXTMODE_MASK) #define DDRPHY_DX8SL1DXCTL1_DXGDBYP_MASK (0x20000U) #define DDRPHY_DX8SL1DXCTL1_DXGDBYP_SHIFT (17U) /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode */ #define DDRPHY_DX8SL1DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXGDBYP_MASK) #define DDRPHY_DX8SL1DXCTL1_DXQSDBYP_MASK (0x40000U) #define DDRPHY_DX8SL1DXCTL1_DXQSDBYP_SHIFT (18U) /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode */ #define DDRPHY_DX8SL1DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXQSDBYP_MASK) #define DDRPHY_DX8SL1DXCTL1_DXGSMD_MASK (0x80000U) #define DDRPHY_DX8SL1DXCTL1_DXGSMD_SHIFT (19U) /*! DXGSMD - Read DQS Gating Status Mode */ #define DDRPHY_DX8SL1DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXGSMD_MASK) #define DDRPHY_DX8SL1DXCTL1_DXDTOSEL_MASK (0x300000U) #define DDRPHY_DX8SL1DXCTL1_DXDTOSEL_SHIFT (20U) /*! DXDTOSEL - DATX8 Digital Test Output Select */ #define DDRPHY_DX8SL1DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXDTOSEL_MASK) #define DDRPHY_DX8SL1DXCTL1_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8SL1DXCTL1_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL1DXCTL1_RESERVED_22_MASK) #define DDRPHY_DX8SL1DXCTL1_DXRCLKMD_MASK (0x800000U) #define DDRPHY_DX8SL1DXCTL1_DXRCLKMD_SHIFT (23U) /*! DXRCLKMD - DATX8 Read Clock Mode */ #define DDRPHY_DX8SL1DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXRCLKMD_MASK) #define DDRPHY_DX8SL1DXCTL1_DXCALCLK_MASK (0x1000000U) #define DDRPHY_DX8SL1DXCTL1_DXCALCLK_SHIFT (24U) /*! DXCALCLK - DATX Calibration Clock Select */ #define DDRPHY_DX8SL1DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXCALCLK_MASK) #define DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL1DXCTL2 - DATX8 0-1 DX Control Register 2 */ /*! @{ */ #define DDRPHY_DX8SL1DXCTL2_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8SL1DXCTL2_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_0_MASK) #define DDRPHY_DX8SL1DXCTL2_DQSGLB_MASK (0x6U) #define DDRPHY_DX8SL1DXCTL2_DQSGLB_SHIFT (1U) /*! DQSGLB - Read DQS Gate I/O Loopback */ #define DDRPHY_DX8SL1DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL1DXCTL2_DQSGLB_MASK) #define DDRPHY_DX8SL1DXCTL2_DISRST_MASK (0x8U) #define DDRPHY_DX8SL1DXCTL2_DISRST_SHIFT (3U) /*! DISRST - Disables the Read FIFO Reset */ #define DDRPHY_DX8SL1DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL1DXCTL2_DISRST_MASK) #define DDRPHY_DX8SL1DXCTL2_RDMODE_MASK (0x30U) #define DDRPHY_DX8SL1DXCTL2_RDMODE_SHIFT (4U) /*! RDMODE - DATX8 Receive FIFO Read Mode */ #define DDRPHY_DX8SL1DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RDMODE_MASK) #define DDRPHY_DX8SL1DXCTL2_PRFBYP_MASK (0x40U) #define DDRPHY_DX8SL1DXCTL2_PRFBYP_SHIFT (6U) /*! PRFBYP - PUB Read FIFO Bypass */ #define DDRPHY_DX8SL1DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL1DXCTL2_PRFBYP_MASK) #define DDRPHY_DX8SL1DXCTL2_WDBI_MASK (0x80U) #define DDRPHY_DX8SL1DXCTL2_WDBI_SHIFT (7U) /*! WDBI - Write Data Bus Inversion Enable */ #define DDRPHY_DX8SL1DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL1DXCTL2_WDBI_MASK) #define DDRPHY_DX8SL1DXCTL2_RDBI_MASK (0x100U) #define DDRPHY_DX8SL1DXCTL2_RDBI_SHIFT (8U) /*! RDBI - Read Data Bus Inversion Enable */ #define DDRPHY_DX8SL1DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RDBI_MASK) #define DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U) #define DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT (9U) /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold */ #define DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK) #define DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_MASK (0x6000U) #define DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT (13U) /*! RESERVED_14_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_MASK) #define DDRPHY_DX8SL1DXCTL2_IOLB_MASK (0x8000U) #define DDRPHY_DX8SL1DXCTL2_IOLB_SHIFT (15U) /*! IOLB - I/O Loopback Select */ #define DDRPHY_DX8SL1DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL1DXCTL2_IOLB_MASK) #define DDRPHY_DX8SL1DXCTL2_IOAG_MASK (0x10000U) #define DDRPHY_DX8SL1DXCTL2_IOAG_SHIFT (16U) /*! IOAG - I/O Assisted Gate Select */ #define DDRPHY_DX8SL1DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL1DXCTL2_IOAG_MASK) #define DDRPHY_DX8SL1DXCTL2_RESERVED_17_MASK (0x20000U) #define DDRPHY_DX8SL1DXCTL2_RESERVED_17_SHIFT (17U) /*! RESERVED_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_17_MASK) #define DDRPHY_DX8SL1DXCTL2_PREOEX_MASK (0xC0000U) #define DDRPHY_DX8SL1DXCTL2_PREOEX_SHIFT (18U) /*! PREOEX - OE Extension during Pre-amble */ #define DDRPHY_DX8SL1DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL1DXCTL2_PREOEX_MASK) #define DDRPHY_DX8SL1DXCTL2_POSOEX_MASK (0x700000U) #define DDRPHY_DX8SL1DXCTL2_POSOEX_SHIFT (20U) /*! POSOEX - OX Extension during Post-amble */ #define DDRPHY_DX8SL1DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL1DXCTL2_POSOEX_MASK) #define DDRPHY_DX8SL1DXCTL2_CRDEN_MASK (0x800000U) #define DDRPHY_DX8SL1DXCTL2_CRDEN_SHIFT (23U) /*! CRDEN - Configurable Read Data Enable */ #define DDRPHY_DX8SL1DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL1DXCTL2_CRDEN_MASK) #define DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SL1IOCR - DATX8 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX8SL1IOCR_DXRXM_MASK (0x7FFU) #define DDRPHY_DX8SL1IOCR_DXRXM_SHIFT (0U) /*! DXRXM - DX IO Receiver Mode */ #define DDRPHY_DX8SL1IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXRXM_MASK) #define DDRPHY_DX8SL1IOCR_DXTXM_MASK (0x3FF800U) #define DDRPHY_DX8SL1IOCR_DXTXM_SHIFT (11U) /*! DXTXM - DX IO Transmitter Mode */ #define DDRPHY_DX8SL1IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXTXM_MASK) #define DDRPHY_DX8SL1IOCR_DXIOM_MASK (0x1C00000U) #define DDRPHY_DX8SL1IOCR_DXIOM_SHIFT (22U) /*! DXIOM - DX IO Mode */ #define DDRPHY_DX8SL1IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXIOM_MASK) #define DDRPHY_DX8SL1IOCR_DXVREFIOM_MASK (0xE000000U) #define DDRPHY_DX8SL1IOCR_DXVREFIOM_SHIFT (25U) /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring */ #define DDRPHY_DX8SL1IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXVREFIOM_MASK) #define DDRPHY_DX8SL1IOCR_DXDACRANGE_MASK (0x70000000U) #define DDRPHY_DX8SL1IOCR_DXDACRANGE_SHIFT (28U) /*! DXDACRANGE - PVREF_DAC REFSEL range select */ #define DDRPHY_DX8SL1IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL1IOCR_DXDACRANGE_MASK) #define DDRPHY_DX8SL1IOCR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8SL1IOCR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL1IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL1IOCR_RESERVED_31_MASK) /*! @} */ /*! @name DX4SL1IOCR - DATX4 Slice 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX4SL1IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX4SL1IOCR_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4SL1IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL1IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL1IOCR_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL2OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */ /*! @{ */ #define DDRPHY_DX8SL2OSC_OSCEN_MASK (0x1U) #define DDRPHY_DX8SL2OSC_OSCEN_SHIFT (0U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_DX8SL2OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL2OSC_OSCEN_MASK) #define DDRPHY_DX8SL2OSC_OSCDIV_MASK (0x1EU) #define DDRPHY_DX8SL2OSC_OSCDIV_SHIFT (1U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_DX8SL2OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL2OSC_OSCDIV_MASK) #define DDRPHY_DX8SL2OSC_OSCWDL_MASK (0x60U) #define DDRPHY_DX8SL2OSC_OSCWDL_SHIFT (5U) /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select */ #define DDRPHY_DX8SL2OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL2OSC_OSCWDL_MASK) #define DDRPHY_DX8SL2OSC_RESERVED_8_7_MASK (0x180U) #define DDRPHY_DX8SL2OSC_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL2OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL2OSC_RESERVED_8_7_MASK) #define DDRPHY_DX8SL2OSC_OSCWDDL_MASK (0x600U) #define DDRPHY_DX8SL2OSC_OSCWDDL_SHIFT (9U) /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select */ #define DDRPHY_DX8SL2OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL2OSC_OSCWDDL_MASK) #define DDRPHY_DX8SL2OSC_RESERVED_12_11_MASK (0x1800U) #define DDRPHY_DX8SL2OSC_RESERVED_12_11_SHIFT (11U) /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL2OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL2OSC_RESERVED_12_11_MASK) #define DDRPHY_DX8SL2OSC_DLTMODE_MASK (0x2000U) #define DDRPHY_DX8SL2OSC_DLTMODE_SHIFT (13U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_DX8SL2OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL2OSC_DLTMODE_MASK) #define DDRPHY_DX8SL2OSC_DLTST_MASK (0x4000U) #define DDRPHY_DX8SL2OSC_DLTST_SHIFT (14U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_DX8SL2OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_DLTST_SHIFT)) & DDRPHY_DX8SL2OSC_DLTST_MASK) #define DDRPHY_DX8SL2OSC_PHYFRST_MASK (0x8000U) #define DDRPHY_DX8SL2OSC_PHYFRST_SHIFT (15U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_DX8SL2OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL2OSC_PHYFRST_MASK) #define DDRPHY_DX8SL2OSC_PHYHRST_MASK (0x10000U) #define DDRPHY_DX8SL2OSC_PHYHRST_SHIFT (16U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_DX8SL2OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL2OSC_PHYHRST_MASK) #define DDRPHY_DX8SL2OSC_LBDQSS_MASK (0x20000U) #define DDRPHY_DX8SL2OSC_LBDQSS_SHIFT (17U) /*! LBDQSS - Loopback DQS Shift */ #define DDRPHY_DX8SL2OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL2OSC_LBDQSS_MASK) #define DDRPHY_DX8SL2OSC_LBGDQS_MASK (0xC0000U) #define DDRPHY_DX8SL2OSC_LBGDQS_SHIFT (18U) /*! LBGDQS - Loopback DQS Gating */ #define DDRPHY_DX8SL2OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL2OSC_LBGDQS_MASK) #define DDRPHY_DX8SL2OSC_LBGSDQS_MASK (0x100000U) #define DDRPHY_DX8SL2OSC_LBGSDQS_SHIFT (20U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value */ #define DDRPHY_DX8SL2OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL2OSC_LBGSDQS_MASK) #define DDRPHY_DX8SL2OSC_LBMODE_MASK (0x200000U) #define DDRPHY_DX8SL2OSC_LBMODE_SHIFT (21U) /*! LBMODE - Loopback Mode */ #define DDRPHY_DX8SL2OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL2OSC_LBMODE_MASK) #define DDRPHY_DX8SL2OSC_CLKLEVEL_MASK (0xC00000U) #define DDRPHY_DX8SL2OSC_CLKLEVEL_SHIFT (22U) /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled. */ #define DDRPHY_DX8SL2OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL2OSC_CLKLEVEL_MASK) #define DDRPHY_DX8SL2OSC_GATEDXCTLCLK_MASK (0x3000000U) #define DDRPHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT (24U) /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk */ #define DDRPHY_DX8SL2OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL2OSC_GATEDXCTLCLK_MASK) #define DDRPHY_DX8SL2OSC_GATEDXDDRCLK_MASK (0xC000000U) #define DDRPHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT (26U) /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk */ #define DDRPHY_DX8SL2OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL2OSC_GATEDXDDRCLK_MASK) #define DDRPHY_DX8SL2OSC_GATEDXRDCLK_MASK (0x30000000U) #define DDRPHY_DX8SL2OSC_GATEDXRDCLK_SHIFT (28U) /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk */ #define DDRPHY_DX8SL2OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL2OSC_GATEDXRDCLK_MASK) #define DDRPHY_DX8SL2OSC_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8SL2OSC_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL2OSC_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8SL2PLLCR0 - DAXT8 0-1 PLL Control Register 0 */ /*! @{ */ #define DDRPHY_DX8SL2PLLCR0_DTC_MASK (0xFU) #define DDRPHY_DX8SL2PLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_DX8SL2PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_DTC_MASK) #define DDRPHY_DX8SL2PLLCR0_ATC_MASK (0xF0U) #define DDRPHY_DX8SL2PLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_DX8SL2PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_ATC_MASK) #define DDRPHY_DX8SL2PLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_DX8SL2PLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable (ATOEN) */ #define DDRPHY_DX8SL2PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL2PLLCR0_ATOEN_MASK) #define DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_MASK) #define DDRPHY_DX8SL2PLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_DX8SL2PLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_DX8SL2PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL2PLLCR0_GSHIFT_MASK) #define DDRPHY_DX8SL2PLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_DX8SL2PLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_DX8SL2PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_CPIC_MASK) #define DDRPHY_DX8SL2PLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_DX8SL2PLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_DX8SL2PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_CPPC_MASK) #define DDRPHY_DX8SL2PLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_DX8SL2PLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_DX8SL2PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL2PLLCR0_RLOCKM_MASK) #define DDRPHY_DX8SL2PLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_DX8SL2PLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_DX8SL2PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL2PLLCR0_FRQSEL_MASK) #define DDRPHY_DX8SL2PLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_DX8SL2PLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_DX8SL2PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL2PLLCR0_RSTOPM_MASK) #define DDRPHY_DX8SL2PLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_DX8SL2PLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_DX8SL2PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL2PLLCR0_PLLPD_MASK) #define DDRPHY_DX8SL2PLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_DX8SL2PLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_DX8SL2PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL2PLLCR0_PLLRST_MASK) #define DDRPHY_DX8SL2PLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_DX8SL2PLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_DX8SL2PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL2PLLCR0_PLLBYP_MASK) /*! @} */ /*! @name DX8SL2PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL2PLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_DX8SL2PLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_DX8SL2PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL2PLLCR1_LOCKDS_MASK) #define DDRPHY_DX8SL2PLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_DX8SL2PLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_DX8SL2PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL2PLLCR1_LOCKCS_MASK) #define DDRPHY_DX8SL2PLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_DX8SL2PLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_DX8SL2PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL2PLLCR1_LOCKPS_MASK) #define DDRPHY_DX8SL2PLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_DX8SL2PLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_DX8SL2PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL2PLLCR1_BYPVDD_MASK) #define DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_DX8SL2PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_MASK) #define DDRPHY_DX8SL2PLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_DX8SL2PLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_DX8SL2PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL2PLLCR1_BYPVREGCP_MASK) #define DDRPHY_DX8SL2PLLCR1_PLLPROG_MASK (0x3FFFC0U) #define DDRPHY_DX8SL2PLLCR1_PLLPROG_SHIFT (6U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_DX8SL2PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL2PLLCR1_PLLPROG_MASK) #define DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8SL2PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name DX8SL2PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name DX8SL2PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name DX8SL2PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DX8SL2DQSCTL - DATX8 0-1 DQS Control Register */ /*! @{ */ #define DDRPHY_DX8SL2DQSCTL_DQSRES_MASK (0xFU) #define DDRPHY_DX8SL2DQSCTL_DQSRES_SHIFT (0U) /*! DQSRES - DQS Resistor */ #define DDRPHY_DX8SL2DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DQSRES_MASK) #define DDRPHY_DX8SL2DQSCTL_DQSNRES_MASK (0xF0U) #define DDRPHY_DX8SL2DQSCTL_DQSNRES_SHIFT (4U) /*! DQSNRES - DQS_N Resistor */ #define DDRPHY_DX8SL2DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DQSNRES_MASK) #define DDRPHY_DX8SL2DQSCTL_DXSR_MASK (0x300U) #define DDRPHY_DX8SL2DQSCTL_DXSR_SHIFT (8U) /*! DXSR - Data Slew Rate */ #define DDRPHY_DX8SL2DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DXSR_MASK) #define DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_MASK (0x1C00U) #define DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT (10U) /*! RESERVED_12_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_MASK) #define DDRPHY_DX8SL2DQSCTL_UDQIOM_MASK (0x2000U) #define DDRPHY_DX8SL2DQSCTL_UDQIOM_SHIFT (13U) /*! UDQIOM - Unused DQ I/O Mode */ #define DDRPHY_DX8SL2DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL2DQSCTL_UDQIOM_MASK) #define DDRPHY_DX8SL2DQSCTL_QSCNTEN_MASK (0x4000U) #define DDRPHY_DX8SL2DQSCTL_QSCNTEN_SHIFT (14U) /*! QSCNTEN - QS Counter Enable */ #define DDRPHY_DX8SL2DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL2DQSCTL_QSCNTEN_MASK) #define DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_MASK (0x18000U) #define DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT (15U) /*! RESERVED_16_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_MASK) #define DDRPHY_DX8SL2DQSCTL_LPIOPD_MASK (0x20000U) #define DDRPHY_DX8SL2DQSCTL_LPIOPD_SHIFT (17U) /*! LPIOPD - Low Power I/O Power Down */ #define DDRPHY_DX8SL2DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL2DQSCTL_LPIOPD_MASK) #define DDRPHY_DX8SL2DQSCTL_LPPLLPD_MASK (0x40000U) #define DDRPHY_DX8SL2DQSCTL_LPPLLPD_SHIFT (18U) /*! LPPLLPD - Low Power PLL Power Down */ #define DDRPHY_DX8SL2DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL2DQSCTL_LPPLLPD_MASK) #define DDRPHY_DX8SL2DQSCTL_DQSGX_MASK (0x180000U) #define DDRPHY_DX8SL2DQSCTL_DQSGX_SHIFT (19U) /*! DQSGX - DQS Gate Extension */ #define DDRPHY_DX8SL2DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DQSGX_MASK) #define DDRPHY_DX8SL2DQSCTL_WRRMODE_MASK (0x200000U) #define DDRPHY_DX8SL2DQSCTL_WRRMODE_SHIFT (21U) /*! WRRMODE - Write Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL2DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL2DQSCTL_WRRMODE_MASK) #define DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_MASK) #define DDRPHY_DX8SL2DQSCTL_RRRMODE_MASK (0x1000000U) #define DDRPHY_DX8SL2DQSCTL_RRRMODE_SHIFT (24U) /*! RRRMODE - Read Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL2DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RRRMODE_MASK) #define DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL2TRNCTL - DATX8 0-1 Training Control Register */ /*! @{ */ #define DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL2DDLCTL - DATX8 0-1 DDL Control Register */ /*! @{ */ #define DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_MASK (0x3U) #define DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_SHIFT (0U) /*! DDLBYPMODE - Controls DDL Bypass Mode */ #define DDRPHY_DX8SL2DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_MASK) #define DDRPHY_DX8SL2DDLCTL_DXDDLBYP_MASK (0x3FFFCU) #define DDRPHY_DX8SL2DDLCTL_DXDDLBYP_SHIFT (2U) /*! DXDDLBYP - DATX8 DDL Bypass */ #define DDRPHY_DX8SL2DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DXDDLBYP_MASK) #define DDRPHY_DX8SL2DDLCTL_DXDDLLD_MASK (0x7C0000U) #define DDRPHY_DX8SL2DDLCTL_DXDDLLD_SHIFT (18U) /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load */ #define DDRPHY_DX8SL2DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DXDDLLD_MASK) #define DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_MASK (0x1800000U) #define DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_SHIFT (23U) /*! RESERVED_24_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_MASK) #define DDRPHY_DX8SL2DDLCTL_DXDDLLDT_MASK (0x2000000U) #define DDRPHY_DX8SL2DDLCTL_DXDDLLDT_SHIFT (25U) /*! DXDDLLDT - DX DDL Load Type */ #define DDRPHY_DX8SL2DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DXDDLLDT_MASK) #define DDRPHY_DX8SL2DDLCTL_DLYLDTM_MASK (0x4000000U) #define DDRPHY_DX8SL2DDLCTL_DLYLDTM_SHIFT (26U) /*! DLYLDTM - Delay Load Timing */ #define DDRPHY_DX8SL2DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DLYLDTM_MASK) #define DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8SL2DXCTL1 - DATX8 0-1 DX Control Register 1 */ /*! @{ */ #define DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_MASK (0xFFFFU) #define DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_SHIFT (0U) /*! RESERVED_15_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_MASK) #define DDRPHY_DX8SL2DXCTL1_DXTMODE_MASK (0x10000U) #define DDRPHY_DX8SL2DXCTL1_DXTMODE_SHIFT (16U) /*! DXTMODE - DATX8 Test Mode */ #define DDRPHY_DX8SL2DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXTMODE_MASK) #define DDRPHY_DX8SL2DXCTL1_DXGDBYP_MASK (0x20000U) #define DDRPHY_DX8SL2DXCTL1_DXGDBYP_SHIFT (17U) /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode */ #define DDRPHY_DX8SL2DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXGDBYP_MASK) #define DDRPHY_DX8SL2DXCTL1_DXQSDBYP_MASK (0x40000U) #define DDRPHY_DX8SL2DXCTL1_DXQSDBYP_SHIFT (18U) /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode */ #define DDRPHY_DX8SL2DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXQSDBYP_MASK) #define DDRPHY_DX8SL2DXCTL1_DXGSMD_MASK (0x80000U) #define DDRPHY_DX8SL2DXCTL1_DXGSMD_SHIFT (19U) /*! DXGSMD - Read DQS Gating Status Mode */ #define DDRPHY_DX8SL2DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXGSMD_MASK) #define DDRPHY_DX8SL2DXCTL1_DXDTOSEL_MASK (0x300000U) #define DDRPHY_DX8SL2DXCTL1_DXDTOSEL_SHIFT (20U) /*! DXDTOSEL - DATX8 Digital Test Output Select */ #define DDRPHY_DX8SL2DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXDTOSEL_MASK) #define DDRPHY_DX8SL2DXCTL1_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8SL2DXCTL1_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL2DXCTL1_RESERVED_22_MASK) #define DDRPHY_DX8SL2DXCTL1_DXRCLKMD_MASK (0x800000U) #define DDRPHY_DX8SL2DXCTL1_DXRCLKMD_SHIFT (23U) /*! DXRCLKMD - DATX8 Read Clock Mode */ #define DDRPHY_DX8SL2DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXRCLKMD_MASK) #define DDRPHY_DX8SL2DXCTL1_DXCALCLK_MASK (0x1000000U) #define DDRPHY_DX8SL2DXCTL1_DXCALCLK_SHIFT (24U) /*! DXCALCLK - DATX Calibration Clock Select */ #define DDRPHY_DX8SL2DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXCALCLK_MASK) #define DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL2DXCTL2 - DATX8 0-1 DX Control Register 2 */ /*! @{ */ #define DDRPHY_DX8SL2DXCTL2_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8SL2DXCTL2_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_0_MASK) #define DDRPHY_DX8SL2DXCTL2_DQSGLB_MASK (0x6U) #define DDRPHY_DX8SL2DXCTL2_DQSGLB_SHIFT (1U) /*! DQSGLB - Read DQS Gate I/O Loopback */ #define DDRPHY_DX8SL2DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL2DXCTL2_DQSGLB_MASK) #define DDRPHY_DX8SL2DXCTL2_DISRST_MASK (0x8U) #define DDRPHY_DX8SL2DXCTL2_DISRST_SHIFT (3U) /*! DISRST - Disables the Read FIFO Reset */ #define DDRPHY_DX8SL2DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL2DXCTL2_DISRST_MASK) #define DDRPHY_DX8SL2DXCTL2_RDMODE_MASK (0x30U) #define DDRPHY_DX8SL2DXCTL2_RDMODE_SHIFT (4U) /*! RDMODE - DATX8 Receive FIFO Read Mode */ #define DDRPHY_DX8SL2DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RDMODE_MASK) #define DDRPHY_DX8SL2DXCTL2_PRFBYP_MASK (0x40U) #define DDRPHY_DX8SL2DXCTL2_PRFBYP_SHIFT (6U) /*! PRFBYP - PUB Read FIFO Bypass */ #define DDRPHY_DX8SL2DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL2DXCTL2_PRFBYP_MASK) #define DDRPHY_DX8SL2DXCTL2_WDBI_MASK (0x80U) #define DDRPHY_DX8SL2DXCTL2_WDBI_SHIFT (7U) /*! WDBI - Write Data Bus Inversion Enable */ #define DDRPHY_DX8SL2DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL2DXCTL2_WDBI_MASK) #define DDRPHY_DX8SL2DXCTL2_RDBI_MASK (0x100U) #define DDRPHY_DX8SL2DXCTL2_RDBI_SHIFT (8U) /*! RDBI - Read Data Bus Inversion Enable */ #define DDRPHY_DX8SL2DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RDBI_MASK) #define DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U) #define DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT (9U) /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold */ #define DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK) #define DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_MASK (0x6000U) #define DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT (13U) /*! RESERVED_14_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_MASK) #define DDRPHY_DX8SL2DXCTL2_IOLB_MASK (0x8000U) #define DDRPHY_DX8SL2DXCTL2_IOLB_SHIFT (15U) /*! IOLB - I/O Loopback Select */ #define DDRPHY_DX8SL2DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL2DXCTL2_IOLB_MASK) #define DDRPHY_DX8SL2DXCTL2_IOAG_MASK (0x10000U) #define DDRPHY_DX8SL2DXCTL2_IOAG_SHIFT (16U) /*! IOAG - I/O Assisted Gate Select */ #define DDRPHY_DX8SL2DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL2DXCTL2_IOAG_MASK) #define DDRPHY_DX8SL2DXCTL2_RESERVED_17_MASK (0x20000U) #define DDRPHY_DX8SL2DXCTL2_RESERVED_17_SHIFT (17U) /*! RESERVED_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_17_MASK) #define DDRPHY_DX8SL2DXCTL2_PREOEX_MASK (0xC0000U) #define DDRPHY_DX8SL2DXCTL2_PREOEX_SHIFT (18U) /*! PREOEX - OE Extension during Pre-amble */ #define DDRPHY_DX8SL2DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL2DXCTL2_PREOEX_MASK) #define DDRPHY_DX8SL2DXCTL2_POSOEX_MASK (0x700000U) #define DDRPHY_DX8SL2DXCTL2_POSOEX_SHIFT (20U) /*! POSOEX - OX Extension during Post-amble */ #define DDRPHY_DX8SL2DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL2DXCTL2_POSOEX_MASK) #define DDRPHY_DX8SL2DXCTL2_CRDEN_MASK (0x800000U) #define DDRPHY_DX8SL2DXCTL2_CRDEN_SHIFT (23U) /*! CRDEN - Configurable Read Data Enable */ #define DDRPHY_DX8SL2DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL2DXCTL2_CRDEN_MASK) #define DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SL2IOCR - DATX8 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX8SL2IOCR_DXRXM_MASK (0x7FFU) #define DDRPHY_DX8SL2IOCR_DXRXM_SHIFT (0U) /*! DXRXM - DX IO Receiver Mode */ #define DDRPHY_DX8SL2IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXRXM_MASK) #define DDRPHY_DX8SL2IOCR_DXTXM_MASK (0x3FF800U) #define DDRPHY_DX8SL2IOCR_DXTXM_SHIFT (11U) /*! DXTXM - DX IO Transmitter Mode */ #define DDRPHY_DX8SL2IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXTXM_MASK) #define DDRPHY_DX8SL2IOCR_DXIOM_MASK (0x1C00000U) #define DDRPHY_DX8SL2IOCR_DXIOM_SHIFT (22U) /*! DXIOM - DX IO Mode */ #define DDRPHY_DX8SL2IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXIOM_MASK) #define DDRPHY_DX8SL2IOCR_DXVREFIOM_MASK (0xE000000U) #define DDRPHY_DX8SL2IOCR_DXVREFIOM_SHIFT (25U) /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring */ #define DDRPHY_DX8SL2IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXVREFIOM_MASK) #define DDRPHY_DX8SL2IOCR_DXDACRANGE_MASK (0x70000000U) #define DDRPHY_DX8SL2IOCR_DXDACRANGE_SHIFT (28U) /*! DXDACRANGE - PVREF_DAC REFSEL range select */ #define DDRPHY_DX8SL2IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL2IOCR_DXDACRANGE_MASK) #define DDRPHY_DX8SL2IOCR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8SL2IOCR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL2IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL2IOCR_RESERVED_31_MASK) /*! @} */ /*! @name DX4SL2IOCR - DATX4 Slice 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX4SL2IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX4SL2IOCR_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4SL2IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL2IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL2IOCR_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL3OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */ /*! @{ */ #define DDRPHY_DX8SL3OSC_OSCEN_MASK (0x1U) #define DDRPHY_DX8SL3OSC_OSCEN_SHIFT (0U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_DX8SL3OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL3OSC_OSCEN_MASK) #define DDRPHY_DX8SL3OSC_OSCDIV_MASK (0x1EU) #define DDRPHY_DX8SL3OSC_OSCDIV_SHIFT (1U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_DX8SL3OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL3OSC_OSCDIV_MASK) #define DDRPHY_DX8SL3OSC_OSCWDL_MASK (0x60U) #define DDRPHY_DX8SL3OSC_OSCWDL_SHIFT (5U) /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select */ #define DDRPHY_DX8SL3OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL3OSC_OSCWDL_MASK) #define DDRPHY_DX8SL3OSC_RESERVED_8_7_MASK (0x180U) #define DDRPHY_DX8SL3OSC_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL3OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL3OSC_RESERVED_8_7_MASK) #define DDRPHY_DX8SL3OSC_OSCWDDL_MASK (0x600U) #define DDRPHY_DX8SL3OSC_OSCWDDL_SHIFT (9U) /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select */ #define DDRPHY_DX8SL3OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL3OSC_OSCWDDL_MASK) #define DDRPHY_DX8SL3OSC_RESERVED_12_11_MASK (0x1800U) #define DDRPHY_DX8SL3OSC_RESERVED_12_11_SHIFT (11U) /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL3OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL3OSC_RESERVED_12_11_MASK) #define DDRPHY_DX8SL3OSC_DLTMODE_MASK (0x2000U) #define DDRPHY_DX8SL3OSC_DLTMODE_SHIFT (13U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_DX8SL3OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL3OSC_DLTMODE_MASK) #define DDRPHY_DX8SL3OSC_DLTST_MASK (0x4000U) #define DDRPHY_DX8SL3OSC_DLTST_SHIFT (14U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_DX8SL3OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_DLTST_SHIFT)) & DDRPHY_DX8SL3OSC_DLTST_MASK) #define DDRPHY_DX8SL3OSC_PHYFRST_MASK (0x8000U) #define DDRPHY_DX8SL3OSC_PHYFRST_SHIFT (15U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_DX8SL3OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL3OSC_PHYFRST_MASK) #define DDRPHY_DX8SL3OSC_PHYHRST_MASK (0x10000U) #define DDRPHY_DX8SL3OSC_PHYHRST_SHIFT (16U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_DX8SL3OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL3OSC_PHYHRST_MASK) #define DDRPHY_DX8SL3OSC_LBDQSS_MASK (0x20000U) #define DDRPHY_DX8SL3OSC_LBDQSS_SHIFT (17U) /*! LBDQSS - Loopback DQS Shift */ #define DDRPHY_DX8SL3OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL3OSC_LBDQSS_MASK) #define DDRPHY_DX8SL3OSC_LBGDQS_MASK (0xC0000U) #define DDRPHY_DX8SL3OSC_LBGDQS_SHIFT (18U) /*! LBGDQS - Loopback DQS Gating */ #define DDRPHY_DX8SL3OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL3OSC_LBGDQS_MASK) #define DDRPHY_DX8SL3OSC_LBGSDQS_MASK (0x100000U) #define DDRPHY_DX8SL3OSC_LBGSDQS_SHIFT (20U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value */ #define DDRPHY_DX8SL3OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL3OSC_LBGSDQS_MASK) #define DDRPHY_DX8SL3OSC_LBMODE_MASK (0x200000U) #define DDRPHY_DX8SL3OSC_LBMODE_SHIFT (21U) /*! LBMODE - Loopback Mode */ #define DDRPHY_DX8SL3OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL3OSC_LBMODE_MASK) #define DDRPHY_DX8SL3OSC_CLKLEVEL_MASK (0xC00000U) #define DDRPHY_DX8SL3OSC_CLKLEVEL_SHIFT (22U) /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled. */ #define DDRPHY_DX8SL3OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL3OSC_CLKLEVEL_MASK) #define DDRPHY_DX8SL3OSC_GATEDXCTLCLK_MASK (0x3000000U) #define DDRPHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT (24U) /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk */ #define DDRPHY_DX8SL3OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL3OSC_GATEDXCTLCLK_MASK) #define DDRPHY_DX8SL3OSC_GATEDXDDRCLK_MASK (0xC000000U) #define DDRPHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT (26U) /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk */ #define DDRPHY_DX8SL3OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL3OSC_GATEDXDDRCLK_MASK) #define DDRPHY_DX8SL3OSC_GATEDXRDCLK_MASK (0x30000000U) #define DDRPHY_DX8SL3OSC_GATEDXRDCLK_SHIFT (28U) /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk */ #define DDRPHY_DX8SL3OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL3OSC_GATEDXRDCLK_MASK) #define DDRPHY_DX8SL3OSC_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8SL3OSC_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL3OSC_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8SL3PLLCR0 - DAXT8 0-1 PLL Control Register 0 */ /*! @{ */ #define DDRPHY_DX8SL3PLLCR0_DTC_MASK (0xFU) #define DDRPHY_DX8SL3PLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_DX8SL3PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_DTC_MASK) #define DDRPHY_DX8SL3PLLCR0_ATC_MASK (0xF0U) #define DDRPHY_DX8SL3PLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_DX8SL3PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_ATC_MASK) #define DDRPHY_DX8SL3PLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_DX8SL3PLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable (ATOEN) */ #define DDRPHY_DX8SL3PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL3PLLCR0_ATOEN_MASK) #define DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_MASK) #define DDRPHY_DX8SL3PLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_DX8SL3PLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_DX8SL3PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL3PLLCR0_GSHIFT_MASK) #define DDRPHY_DX8SL3PLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_DX8SL3PLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_DX8SL3PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_CPIC_MASK) #define DDRPHY_DX8SL3PLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_DX8SL3PLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_DX8SL3PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_CPPC_MASK) #define DDRPHY_DX8SL3PLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_DX8SL3PLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_DX8SL3PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL3PLLCR0_RLOCKM_MASK) #define DDRPHY_DX8SL3PLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_DX8SL3PLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_DX8SL3PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL3PLLCR0_FRQSEL_MASK) #define DDRPHY_DX8SL3PLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_DX8SL3PLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_DX8SL3PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL3PLLCR0_RSTOPM_MASK) #define DDRPHY_DX8SL3PLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_DX8SL3PLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_DX8SL3PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL3PLLCR0_PLLPD_MASK) #define DDRPHY_DX8SL3PLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_DX8SL3PLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_DX8SL3PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL3PLLCR0_PLLRST_MASK) #define DDRPHY_DX8SL3PLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_DX8SL3PLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_DX8SL3PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL3PLLCR0_PLLBYP_MASK) /*! @} */ /*! @name DX8SL3PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL3PLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_DX8SL3PLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_DX8SL3PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL3PLLCR1_LOCKDS_MASK) #define DDRPHY_DX8SL3PLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_DX8SL3PLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_DX8SL3PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL3PLLCR1_LOCKCS_MASK) #define DDRPHY_DX8SL3PLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_DX8SL3PLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_DX8SL3PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL3PLLCR1_LOCKPS_MASK) #define DDRPHY_DX8SL3PLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_DX8SL3PLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_DX8SL3PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL3PLLCR1_BYPVDD_MASK) #define DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_DX8SL3PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_MASK) #define DDRPHY_DX8SL3PLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_DX8SL3PLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_DX8SL3PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL3PLLCR1_BYPVREGCP_MASK) #define DDRPHY_DX8SL3PLLCR1_PLLPROG_MASK (0x3FFFC0U) #define DDRPHY_DX8SL3PLLCR1_PLLPROG_SHIFT (6U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_DX8SL3PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL3PLLCR1_PLLPROG_MASK) #define DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8SL3PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name DX8SL3PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name DX8SL3PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name DX8SL3PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DX8SL3DQSCTL - DATX8 0-1 DQS Control Register */ /*! @{ */ #define DDRPHY_DX8SL3DQSCTL_DQSRES_MASK (0xFU) #define DDRPHY_DX8SL3DQSCTL_DQSRES_SHIFT (0U) /*! DQSRES - DQS Resistor */ #define DDRPHY_DX8SL3DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DQSRES_MASK) #define DDRPHY_DX8SL3DQSCTL_DQSNRES_MASK (0xF0U) #define DDRPHY_DX8SL3DQSCTL_DQSNRES_SHIFT (4U) /*! DQSNRES - DQS_N Resistor */ #define DDRPHY_DX8SL3DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DQSNRES_MASK) #define DDRPHY_DX8SL3DQSCTL_DXSR_MASK (0x300U) #define DDRPHY_DX8SL3DQSCTL_DXSR_SHIFT (8U) /*! DXSR - Data Slew Rate */ #define DDRPHY_DX8SL3DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DXSR_MASK) #define DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_MASK (0x1C00U) #define DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT (10U) /*! RESERVED_12_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_MASK) #define DDRPHY_DX8SL3DQSCTL_UDQIOM_MASK (0x2000U) #define DDRPHY_DX8SL3DQSCTL_UDQIOM_SHIFT (13U) /*! UDQIOM - Unused DQ I/O Mode */ #define DDRPHY_DX8SL3DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL3DQSCTL_UDQIOM_MASK) #define DDRPHY_DX8SL3DQSCTL_QSCNTEN_MASK (0x4000U) #define DDRPHY_DX8SL3DQSCTL_QSCNTEN_SHIFT (14U) /*! QSCNTEN - QS Counter Enable */ #define DDRPHY_DX8SL3DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL3DQSCTL_QSCNTEN_MASK) #define DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_MASK (0x18000U) #define DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT (15U) /*! RESERVED_16_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_MASK) #define DDRPHY_DX8SL3DQSCTL_LPIOPD_MASK (0x20000U) #define DDRPHY_DX8SL3DQSCTL_LPIOPD_SHIFT (17U) /*! LPIOPD - Low Power I/O Power Down */ #define DDRPHY_DX8SL3DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL3DQSCTL_LPIOPD_MASK) #define DDRPHY_DX8SL3DQSCTL_LPPLLPD_MASK (0x40000U) #define DDRPHY_DX8SL3DQSCTL_LPPLLPD_SHIFT (18U) /*! LPPLLPD - Low Power PLL Power Down */ #define DDRPHY_DX8SL3DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL3DQSCTL_LPPLLPD_MASK) #define DDRPHY_DX8SL3DQSCTL_DQSGX_MASK (0x180000U) #define DDRPHY_DX8SL3DQSCTL_DQSGX_SHIFT (19U) /*! DQSGX - DQS Gate Extension */ #define DDRPHY_DX8SL3DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DQSGX_MASK) #define DDRPHY_DX8SL3DQSCTL_WRRMODE_MASK (0x200000U) #define DDRPHY_DX8SL3DQSCTL_WRRMODE_SHIFT (21U) /*! WRRMODE - Write Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL3DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL3DQSCTL_WRRMODE_MASK) #define DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_MASK) #define DDRPHY_DX8SL3DQSCTL_RRRMODE_MASK (0x1000000U) #define DDRPHY_DX8SL3DQSCTL_RRRMODE_SHIFT (24U) /*! RRRMODE - Read Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL3DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RRRMODE_MASK) #define DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL3TRNCTL - DATX8 0-1 Training Control Register */ /*! @{ */ #define DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL3DDLCTL - DATX8 0-1 DDL Control Register */ /*! @{ */ #define DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_MASK (0x3U) #define DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_SHIFT (0U) /*! DDLBYPMODE - Controls DDL Bypass Mode */ #define DDRPHY_DX8SL3DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_MASK) #define DDRPHY_DX8SL3DDLCTL_DXDDLBYP_MASK (0x3FFFCU) #define DDRPHY_DX8SL3DDLCTL_DXDDLBYP_SHIFT (2U) /*! DXDDLBYP - DATX8 DDL Bypass */ #define DDRPHY_DX8SL3DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DXDDLBYP_MASK) #define DDRPHY_DX8SL3DDLCTL_DXDDLLD_MASK (0x7C0000U) #define DDRPHY_DX8SL3DDLCTL_DXDDLLD_SHIFT (18U) /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load */ #define DDRPHY_DX8SL3DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DXDDLLD_MASK) #define DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_MASK (0x1800000U) #define DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_SHIFT (23U) /*! RESERVED_24_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_MASK) #define DDRPHY_DX8SL3DDLCTL_DXDDLLDT_MASK (0x2000000U) #define DDRPHY_DX8SL3DDLCTL_DXDDLLDT_SHIFT (25U) /*! DXDDLLDT - DX DDL Load Type */ #define DDRPHY_DX8SL3DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DXDDLLDT_MASK) #define DDRPHY_DX8SL3DDLCTL_DLYLDTM_MASK (0x4000000U) #define DDRPHY_DX8SL3DDLCTL_DLYLDTM_SHIFT (26U) /*! DLYLDTM - Delay Load Timing */ #define DDRPHY_DX8SL3DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DLYLDTM_MASK) #define DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8SL3DXCTL1 - DATX8 0-1 DX Control Register 1 */ /*! @{ */ #define DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_MASK (0xFFFFU) #define DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_SHIFT (0U) /*! RESERVED_15_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_MASK) #define DDRPHY_DX8SL3DXCTL1_DXTMODE_MASK (0x10000U) #define DDRPHY_DX8SL3DXCTL1_DXTMODE_SHIFT (16U) /*! DXTMODE - DATX8 Test Mode */ #define DDRPHY_DX8SL3DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXTMODE_MASK) #define DDRPHY_DX8SL3DXCTL1_DXGDBYP_MASK (0x20000U) #define DDRPHY_DX8SL3DXCTL1_DXGDBYP_SHIFT (17U) /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode */ #define DDRPHY_DX8SL3DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXGDBYP_MASK) #define DDRPHY_DX8SL3DXCTL1_DXQSDBYP_MASK (0x40000U) #define DDRPHY_DX8SL3DXCTL1_DXQSDBYP_SHIFT (18U) /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode */ #define DDRPHY_DX8SL3DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXQSDBYP_MASK) #define DDRPHY_DX8SL3DXCTL1_DXGSMD_MASK (0x80000U) #define DDRPHY_DX8SL3DXCTL1_DXGSMD_SHIFT (19U) /*! DXGSMD - Read DQS Gating Status Mode */ #define DDRPHY_DX8SL3DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXGSMD_MASK) #define DDRPHY_DX8SL3DXCTL1_DXDTOSEL_MASK (0x300000U) #define DDRPHY_DX8SL3DXCTL1_DXDTOSEL_SHIFT (20U) /*! DXDTOSEL - DATX8 Digital Test Output Select */ #define DDRPHY_DX8SL3DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXDTOSEL_MASK) #define DDRPHY_DX8SL3DXCTL1_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8SL3DXCTL1_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL3DXCTL1_RESERVED_22_MASK) #define DDRPHY_DX8SL3DXCTL1_DXRCLKMD_MASK (0x800000U) #define DDRPHY_DX8SL3DXCTL1_DXRCLKMD_SHIFT (23U) /*! DXRCLKMD - DATX8 Read Clock Mode */ #define DDRPHY_DX8SL3DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXRCLKMD_MASK) #define DDRPHY_DX8SL3DXCTL1_DXCALCLK_MASK (0x1000000U) #define DDRPHY_DX8SL3DXCTL1_DXCALCLK_SHIFT (24U) /*! DXCALCLK - DATX Calibration Clock Select */ #define DDRPHY_DX8SL3DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXCALCLK_MASK) #define DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL3DXCTL2 - DATX8 0-1 DX Control Register 2 */ /*! @{ */ #define DDRPHY_DX8SL3DXCTL2_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8SL3DXCTL2_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_0_MASK) #define DDRPHY_DX8SL3DXCTL2_DQSGLB_MASK (0x6U) #define DDRPHY_DX8SL3DXCTL2_DQSGLB_SHIFT (1U) /*! DQSGLB - Read DQS Gate I/O Loopback */ #define DDRPHY_DX8SL3DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL3DXCTL2_DQSGLB_MASK) #define DDRPHY_DX8SL3DXCTL2_DISRST_MASK (0x8U) #define DDRPHY_DX8SL3DXCTL2_DISRST_SHIFT (3U) /*! DISRST - Disables the Read FIFO Reset */ #define DDRPHY_DX8SL3DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL3DXCTL2_DISRST_MASK) #define DDRPHY_DX8SL3DXCTL2_RDMODE_MASK (0x30U) #define DDRPHY_DX8SL3DXCTL2_RDMODE_SHIFT (4U) /*! RDMODE - DATX8 Receive FIFO Read Mode */ #define DDRPHY_DX8SL3DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RDMODE_MASK) #define DDRPHY_DX8SL3DXCTL2_PRFBYP_MASK (0x40U) #define DDRPHY_DX8SL3DXCTL2_PRFBYP_SHIFT (6U) /*! PRFBYP - PUB Read FIFO Bypass */ #define DDRPHY_DX8SL3DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL3DXCTL2_PRFBYP_MASK) #define DDRPHY_DX8SL3DXCTL2_WDBI_MASK (0x80U) #define DDRPHY_DX8SL3DXCTL2_WDBI_SHIFT (7U) /*! WDBI - Write Data Bus Inversion Enable */ #define DDRPHY_DX8SL3DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL3DXCTL2_WDBI_MASK) #define DDRPHY_DX8SL3DXCTL2_RDBI_MASK (0x100U) #define DDRPHY_DX8SL3DXCTL2_RDBI_SHIFT (8U) /*! RDBI - Read Data Bus Inversion Enable */ #define DDRPHY_DX8SL3DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RDBI_MASK) #define DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U) #define DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT (9U) /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold */ #define DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK) #define DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_MASK (0x6000U) #define DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT (13U) /*! RESERVED_14_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_MASK) #define DDRPHY_DX8SL3DXCTL2_IOLB_MASK (0x8000U) #define DDRPHY_DX8SL3DXCTL2_IOLB_SHIFT (15U) /*! IOLB - I/O Loopback Select */ #define DDRPHY_DX8SL3DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL3DXCTL2_IOLB_MASK) #define DDRPHY_DX8SL3DXCTL2_IOAG_MASK (0x10000U) #define DDRPHY_DX8SL3DXCTL2_IOAG_SHIFT (16U) /*! IOAG - I/O Assisted Gate Select */ #define DDRPHY_DX8SL3DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL3DXCTL2_IOAG_MASK) #define DDRPHY_DX8SL3DXCTL2_RESERVED_17_MASK (0x20000U) #define DDRPHY_DX8SL3DXCTL2_RESERVED_17_SHIFT (17U) /*! RESERVED_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_17_MASK) #define DDRPHY_DX8SL3DXCTL2_PREOEX_MASK (0xC0000U) #define DDRPHY_DX8SL3DXCTL2_PREOEX_SHIFT (18U) /*! PREOEX - OE Extension during Pre-amble */ #define DDRPHY_DX8SL3DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL3DXCTL2_PREOEX_MASK) #define DDRPHY_DX8SL3DXCTL2_POSOEX_MASK (0x700000U) #define DDRPHY_DX8SL3DXCTL2_POSOEX_SHIFT (20U) /*! POSOEX - OX Extension during Post-amble */ #define DDRPHY_DX8SL3DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL3DXCTL2_POSOEX_MASK) #define DDRPHY_DX8SL3DXCTL2_CRDEN_MASK (0x800000U) #define DDRPHY_DX8SL3DXCTL2_CRDEN_SHIFT (23U) /*! CRDEN - Configurable Read Data Enable */ #define DDRPHY_DX8SL3DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL3DXCTL2_CRDEN_MASK) #define DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SL3IOCR - DATX8 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX8SL3IOCR_DXRXM_MASK (0x7FFU) #define DDRPHY_DX8SL3IOCR_DXRXM_SHIFT (0U) /*! DXRXM - DX IO Receiver Mode */ #define DDRPHY_DX8SL3IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXRXM_MASK) #define DDRPHY_DX8SL3IOCR_DXTXM_MASK (0x3FF800U) #define DDRPHY_DX8SL3IOCR_DXTXM_SHIFT (11U) /*! DXTXM - DX IO Transmitter Mode */ #define DDRPHY_DX8SL3IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXTXM_MASK) #define DDRPHY_DX8SL3IOCR_DXIOM_MASK (0x1C00000U) #define DDRPHY_DX8SL3IOCR_DXIOM_SHIFT (22U) /*! DXIOM - DX IO Mode */ #define DDRPHY_DX8SL3IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXIOM_MASK) #define DDRPHY_DX8SL3IOCR_DXVREFIOM_MASK (0xE000000U) #define DDRPHY_DX8SL3IOCR_DXVREFIOM_SHIFT (25U) /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring */ #define DDRPHY_DX8SL3IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXVREFIOM_MASK) #define DDRPHY_DX8SL3IOCR_DXDACRANGE_MASK (0x70000000U) #define DDRPHY_DX8SL3IOCR_DXDACRANGE_SHIFT (28U) /*! DXDACRANGE - PVREF_DAC REFSEL range select */ #define DDRPHY_DX8SL3IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL3IOCR_DXDACRANGE_MASK) #define DDRPHY_DX8SL3IOCR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8SL3IOCR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL3IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL3IOCR_RESERVED_31_MASK) /*! @} */ /*! @name DX4SL3IOCR - DATX4 Slice 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX4SL3IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX4SL3IOCR_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4SL3IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL3IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL3IOCR_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL4OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */ /*! @{ */ #define DDRPHY_DX8SL4OSC_OSCEN_MASK (0x1U) #define DDRPHY_DX8SL4OSC_OSCEN_SHIFT (0U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_DX8SL4OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL4OSC_OSCEN_MASK) #define DDRPHY_DX8SL4OSC_OSCDIV_MASK (0x1EU) #define DDRPHY_DX8SL4OSC_OSCDIV_SHIFT (1U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_DX8SL4OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL4OSC_OSCDIV_MASK) #define DDRPHY_DX8SL4OSC_OSCWDL_MASK (0x60U) #define DDRPHY_DX8SL4OSC_OSCWDL_SHIFT (5U) /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select */ #define DDRPHY_DX8SL4OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL4OSC_OSCWDL_MASK) #define DDRPHY_DX8SL4OSC_RESERVED_8_7_MASK (0x180U) #define DDRPHY_DX8SL4OSC_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL4OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL4OSC_RESERVED_8_7_MASK) #define DDRPHY_DX8SL4OSC_OSCWDDL_MASK (0x600U) #define DDRPHY_DX8SL4OSC_OSCWDDL_SHIFT (9U) /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select */ #define DDRPHY_DX8SL4OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL4OSC_OSCWDDL_MASK) #define DDRPHY_DX8SL4OSC_RESERVED_12_11_MASK (0x1800U) #define DDRPHY_DX8SL4OSC_RESERVED_12_11_SHIFT (11U) /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL4OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL4OSC_RESERVED_12_11_MASK) #define DDRPHY_DX8SL4OSC_DLTMODE_MASK (0x2000U) #define DDRPHY_DX8SL4OSC_DLTMODE_SHIFT (13U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_DX8SL4OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL4OSC_DLTMODE_MASK) #define DDRPHY_DX8SL4OSC_DLTST_MASK (0x4000U) #define DDRPHY_DX8SL4OSC_DLTST_SHIFT (14U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_DX8SL4OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_DLTST_SHIFT)) & DDRPHY_DX8SL4OSC_DLTST_MASK) #define DDRPHY_DX8SL4OSC_PHYFRST_MASK (0x8000U) #define DDRPHY_DX8SL4OSC_PHYFRST_SHIFT (15U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_DX8SL4OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL4OSC_PHYFRST_MASK) #define DDRPHY_DX8SL4OSC_PHYHRST_MASK (0x10000U) #define DDRPHY_DX8SL4OSC_PHYHRST_SHIFT (16U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_DX8SL4OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL4OSC_PHYHRST_MASK) #define DDRPHY_DX8SL4OSC_LBDQSS_MASK (0x20000U) #define DDRPHY_DX8SL4OSC_LBDQSS_SHIFT (17U) /*! LBDQSS - Loopback DQS Shift */ #define DDRPHY_DX8SL4OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL4OSC_LBDQSS_MASK) #define DDRPHY_DX8SL4OSC_LBGDQS_MASK (0xC0000U) #define DDRPHY_DX8SL4OSC_LBGDQS_SHIFT (18U) /*! LBGDQS - Loopback DQS Gating */ #define DDRPHY_DX8SL4OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL4OSC_LBGDQS_MASK) #define DDRPHY_DX8SL4OSC_LBGSDQS_MASK (0x100000U) #define DDRPHY_DX8SL4OSC_LBGSDQS_SHIFT (20U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value */ #define DDRPHY_DX8SL4OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL4OSC_LBGSDQS_MASK) #define DDRPHY_DX8SL4OSC_LBMODE_MASK (0x200000U) #define DDRPHY_DX8SL4OSC_LBMODE_SHIFT (21U) /*! LBMODE - Loopback Mode */ #define DDRPHY_DX8SL4OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL4OSC_LBMODE_MASK) #define DDRPHY_DX8SL4OSC_CLKLEVEL_MASK (0xC00000U) #define DDRPHY_DX8SL4OSC_CLKLEVEL_SHIFT (22U) /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled. */ #define DDRPHY_DX8SL4OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL4OSC_CLKLEVEL_MASK) #define DDRPHY_DX8SL4OSC_GATEDXCTLCLK_MASK (0x3000000U) #define DDRPHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT (24U) /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk */ #define DDRPHY_DX8SL4OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL4OSC_GATEDXCTLCLK_MASK) #define DDRPHY_DX8SL4OSC_GATEDXDDRCLK_MASK (0xC000000U) #define DDRPHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT (26U) /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk */ #define DDRPHY_DX8SL4OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL4OSC_GATEDXDDRCLK_MASK) #define DDRPHY_DX8SL4OSC_GATEDXRDCLK_MASK (0x30000000U) #define DDRPHY_DX8SL4OSC_GATEDXRDCLK_SHIFT (28U) /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk */ #define DDRPHY_DX8SL4OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL4OSC_GATEDXRDCLK_MASK) #define DDRPHY_DX8SL4OSC_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8SL4OSC_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL4OSC_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8SL4PLLCR0 - DAXT8 0-1 PLL Control Register 0 */ /*! @{ */ #define DDRPHY_DX8SL4PLLCR0_DTC_MASK (0xFU) #define DDRPHY_DX8SL4PLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_DX8SL4PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_DTC_MASK) #define DDRPHY_DX8SL4PLLCR0_ATC_MASK (0xF0U) #define DDRPHY_DX8SL4PLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_DX8SL4PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_ATC_MASK) #define DDRPHY_DX8SL4PLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_DX8SL4PLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable (ATOEN) */ #define DDRPHY_DX8SL4PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL4PLLCR0_ATOEN_MASK) #define DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_MASK) #define DDRPHY_DX8SL4PLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_DX8SL4PLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_DX8SL4PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL4PLLCR0_GSHIFT_MASK) #define DDRPHY_DX8SL4PLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_DX8SL4PLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_DX8SL4PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_CPIC_MASK) #define DDRPHY_DX8SL4PLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_DX8SL4PLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_DX8SL4PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_CPPC_MASK) #define DDRPHY_DX8SL4PLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_DX8SL4PLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_DX8SL4PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL4PLLCR0_RLOCKM_MASK) #define DDRPHY_DX8SL4PLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_DX8SL4PLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_DX8SL4PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL4PLLCR0_FRQSEL_MASK) #define DDRPHY_DX8SL4PLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_DX8SL4PLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_DX8SL4PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL4PLLCR0_RSTOPM_MASK) #define DDRPHY_DX8SL4PLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_DX8SL4PLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_DX8SL4PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL4PLLCR0_PLLPD_MASK) #define DDRPHY_DX8SL4PLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_DX8SL4PLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_DX8SL4PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL4PLLCR0_PLLRST_MASK) #define DDRPHY_DX8SL4PLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_DX8SL4PLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_DX8SL4PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL4PLLCR0_PLLBYP_MASK) /*! @} */ /*! @name DX8SL4PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL4PLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_DX8SL4PLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_DX8SL4PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL4PLLCR1_LOCKDS_MASK) #define DDRPHY_DX8SL4PLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_DX8SL4PLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_DX8SL4PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL4PLLCR1_LOCKCS_MASK) #define DDRPHY_DX8SL4PLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_DX8SL4PLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_DX8SL4PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL4PLLCR1_LOCKPS_MASK) #define DDRPHY_DX8SL4PLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_DX8SL4PLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_DX8SL4PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL4PLLCR1_BYPVDD_MASK) #define DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_DX8SL4PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_MASK) #define DDRPHY_DX8SL4PLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_DX8SL4PLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_DX8SL4PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL4PLLCR1_BYPVREGCP_MASK) #define DDRPHY_DX8SL4PLLCR1_PLLPROG_MASK (0x3FFFC0U) #define DDRPHY_DX8SL4PLLCR1_PLLPROG_SHIFT (6U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_DX8SL4PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL4PLLCR1_PLLPROG_MASK) #define DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8SL4PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name DX8SL4PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name DX8SL4PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name DX8SL4PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DX8SL4DQSCTL - DATX8 0-1 DQS Control Register */ /*! @{ */ #define DDRPHY_DX8SL4DQSCTL_DQSRES_MASK (0xFU) #define DDRPHY_DX8SL4DQSCTL_DQSRES_SHIFT (0U) /*! DQSRES - DQS Resistor */ #define DDRPHY_DX8SL4DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DQSRES_MASK) #define DDRPHY_DX8SL4DQSCTL_DQSNRES_MASK (0xF0U) #define DDRPHY_DX8SL4DQSCTL_DQSNRES_SHIFT (4U) /*! DQSNRES - DQS_N Resistor */ #define DDRPHY_DX8SL4DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DQSNRES_MASK) #define DDRPHY_DX8SL4DQSCTL_DXSR_MASK (0x300U) #define DDRPHY_DX8SL4DQSCTL_DXSR_SHIFT (8U) /*! DXSR - Data Slew Rate */ #define DDRPHY_DX8SL4DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DXSR_MASK) #define DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_MASK (0x1C00U) #define DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT (10U) /*! RESERVED_12_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_MASK) #define DDRPHY_DX8SL4DQSCTL_UDQIOM_MASK (0x2000U) #define DDRPHY_DX8SL4DQSCTL_UDQIOM_SHIFT (13U) /*! UDQIOM - Unused DQ I/O Mode */ #define DDRPHY_DX8SL4DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL4DQSCTL_UDQIOM_MASK) #define DDRPHY_DX8SL4DQSCTL_QSCNTEN_MASK (0x4000U) #define DDRPHY_DX8SL4DQSCTL_QSCNTEN_SHIFT (14U) /*! QSCNTEN - QS Counter Enable */ #define DDRPHY_DX8SL4DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL4DQSCTL_QSCNTEN_MASK) #define DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_MASK (0x18000U) #define DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT (15U) /*! RESERVED_16_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_MASK) #define DDRPHY_DX8SL4DQSCTL_LPIOPD_MASK (0x20000U) #define DDRPHY_DX8SL4DQSCTL_LPIOPD_SHIFT (17U) /*! LPIOPD - Low Power I/O Power Down */ #define DDRPHY_DX8SL4DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL4DQSCTL_LPIOPD_MASK) #define DDRPHY_DX8SL4DQSCTL_LPPLLPD_MASK (0x40000U) #define DDRPHY_DX8SL4DQSCTL_LPPLLPD_SHIFT (18U) /*! LPPLLPD - Low Power PLL Power Down */ #define DDRPHY_DX8SL4DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL4DQSCTL_LPPLLPD_MASK) #define DDRPHY_DX8SL4DQSCTL_DQSGX_MASK (0x180000U) #define DDRPHY_DX8SL4DQSCTL_DQSGX_SHIFT (19U) /*! DQSGX - DQS Gate Extension */ #define DDRPHY_DX8SL4DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DQSGX_MASK) #define DDRPHY_DX8SL4DQSCTL_WRRMODE_MASK (0x200000U) #define DDRPHY_DX8SL4DQSCTL_WRRMODE_SHIFT (21U) /*! WRRMODE - Write Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL4DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL4DQSCTL_WRRMODE_MASK) #define DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_MASK) #define DDRPHY_DX8SL4DQSCTL_RRRMODE_MASK (0x1000000U) #define DDRPHY_DX8SL4DQSCTL_RRRMODE_SHIFT (24U) /*! RRRMODE - Read Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL4DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RRRMODE_MASK) #define DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL4TRNCTL - DATX8 0-1 Training Control Register */ /*! @{ */ #define DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL4DDLCTL - DATX8 0-1 DDL Control Register */ /*! @{ */ #define DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_MASK (0x3U) #define DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_SHIFT (0U) /*! DDLBYPMODE - Controls DDL Bypass Mode */ #define DDRPHY_DX8SL4DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_MASK) #define DDRPHY_DX8SL4DDLCTL_DXDDLBYP_MASK (0x3FFFCU) #define DDRPHY_DX8SL4DDLCTL_DXDDLBYP_SHIFT (2U) /*! DXDDLBYP - DATX8 DDL Bypass */ #define DDRPHY_DX8SL4DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DXDDLBYP_MASK) #define DDRPHY_DX8SL4DDLCTL_DXDDLLD_MASK (0x7C0000U) #define DDRPHY_DX8SL4DDLCTL_DXDDLLD_SHIFT (18U) /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load */ #define DDRPHY_DX8SL4DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DXDDLLD_MASK) #define DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_MASK (0x1800000U) #define DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_SHIFT (23U) /*! RESERVED_24_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_MASK) #define DDRPHY_DX8SL4DDLCTL_DXDDLLDT_MASK (0x2000000U) #define DDRPHY_DX8SL4DDLCTL_DXDDLLDT_SHIFT (25U) /*! DXDDLLDT - DX DDL Load Type */ #define DDRPHY_DX8SL4DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DXDDLLDT_MASK) #define DDRPHY_DX8SL4DDLCTL_DLYLDTM_MASK (0x4000000U) #define DDRPHY_DX8SL4DDLCTL_DLYLDTM_SHIFT (26U) /*! DLYLDTM - Delay Load Timing */ #define DDRPHY_DX8SL4DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DLYLDTM_MASK) #define DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8SL4DXCTL1 - DATX8 0-1 DX Control Register 1 */ /*! @{ */ #define DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_MASK (0xFFFFU) #define DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_SHIFT (0U) /*! RESERVED_15_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_MASK) #define DDRPHY_DX8SL4DXCTL1_DXTMODE_MASK (0x10000U) #define DDRPHY_DX8SL4DXCTL1_DXTMODE_SHIFT (16U) /*! DXTMODE - DATX8 Test Mode */ #define DDRPHY_DX8SL4DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXTMODE_MASK) #define DDRPHY_DX8SL4DXCTL1_DXGDBYP_MASK (0x20000U) #define DDRPHY_DX8SL4DXCTL1_DXGDBYP_SHIFT (17U) /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode */ #define DDRPHY_DX8SL4DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXGDBYP_MASK) #define DDRPHY_DX8SL4DXCTL1_DXQSDBYP_MASK (0x40000U) #define DDRPHY_DX8SL4DXCTL1_DXQSDBYP_SHIFT (18U) /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode */ #define DDRPHY_DX8SL4DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXQSDBYP_MASK) #define DDRPHY_DX8SL4DXCTL1_DXGSMD_MASK (0x80000U) #define DDRPHY_DX8SL4DXCTL1_DXGSMD_SHIFT (19U) /*! DXGSMD - Read DQS Gating Status Mode */ #define DDRPHY_DX8SL4DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXGSMD_MASK) #define DDRPHY_DX8SL4DXCTL1_DXDTOSEL_MASK (0x300000U) #define DDRPHY_DX8SL4DXCTL1_DXDTOSEL_SHIFT (20U) /*! DXDTOSEL - DATX8 Digital Test Output Select */ #define DDRPHY_DX8SL4DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXDTOSEL_MASK) #define DDRPHY_DX8SL4DXCTL1_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8SL4DXCTL1_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL4DXCTL1_RESERVED_22_MASK) #define DDRPHY_DX8SL4DXCTL1_DXRCLKMD_MASK (0x800000U) #define DDRPHY_DX8SL4DXCTL1_DXRCLKMD_SHIFT (23U) /*! DXRCLKMD - DATX8 Read Clock Mode */ #define DDRPHY_DX8SL4DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXRCLKMD_MASK) #define DDRPHY_DX8SL4DXCTL1_DXCALCLK_MASK (0x1000000U) #define DDRPHY_DX8SL4DXCTL1_DXCALCLK_SHIFT (24U) /*! DXCALCLK - DATX Calibration Clock Select */ #define DDRPHY_DX8SL4DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXCALCLK_MASK) #define DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL4DXCTL2 - DATX8 0-1 DX Control Register 2 */ /*! @{ */ #define DDRPHY_DX8SL4DXCTL2_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8SL4DXCTL2_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_0_MASK) #define DDRPHY_DX8SL4DXCTL2_DQSGLB_MASK (0x6U) #define DDRPHY_DX8SL4DXCTL2_DQSGLB_SHIFT (1U) /*! DQSGLB - Read DQS Gate I/O Loopback */ #define DDRPHY_DX8SL4DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL4DXCTL2_DQSGLB_MASK) #define DDRPHY_DX8SL4DXCTL2_DISRST_MASK (0x8U) #define DDRPHY_DX8SL4DXCTL2_DISRST_SHIFT (3U) /*! DISRST - Disables the Read FIFO Reset */ #define DDRPHY_DX8SL4DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL4DXCTL2_DISRST_MASK) #define DDRPHY_DX8SL4DXCTL2_RDMODE_MASK (0x30U) #define DDRPHY_DX8SL4DXCTL2_RDMODE_SHIFT (4U) /*! RDMODE - DATX8 Receive FIFO Read Mode */ #define DDRPHY_DX8SL4DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RDMODE_MASK) #define DDRPHY_DX8SL4DXCTL2_PRFBYP_MASK (0x40U) #define DDRPHY_DX8SL4DXCTL2_PRFBYP_SHIFT (6U) /*! PRFBYP - PUB Read FIFO Bypass */ #define DDRPHY_DX8SL4DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL4DXCTL2_PRFBYP_MASK) #define DDRPHY_DX8SL4DXCTL2_WDBI_MASK (0x80U) #define DDRPHY_DX8SL4DXCTL2_WDBI_SHIFT (7U) /*! WDBI - Write Data Bus Inversion Enable */ #define DDRPHY_DX8SL4DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL4DXCTL2_WDBI_MASK) #define DDRPHY_DX8SL4DXCTL2_RDBI_MASK (0x100U) #define DDRPHY_DX8SL4DXCTL2_RDBI_SHIFT (8U) /*! RDBI - Read Data Bus Inversion Enable */ #define DDRPHY_DX8SL4DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RDBI_MASK) #define DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U) #define DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT (9U) /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold */ #define DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK) #define DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_MASK (0x6000U) #define DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT (13U) /*! RESERVED_14_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_MASK) #define DDRPHY_DX8SL4DXCTL2_IOLB_MASK (0x8000U) #define DDRPHY_DX8SL4DXCTL2_IOLB_SHIFT (15U) /*! IOLB - I/O Loopback Select */ #define DDRPHY_DX8SL4DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL4DXCTL2_IOLB_MASK) #define DDRPHY_DX8SL4DXCTL2_IOAG_MASK (0x10000U) #define DDRPHY_DX8SL4DXCTL2_IOAG_SHIFT (16U) /*! IOAG - I/O Assisted Gate Select */ #define DDRPHY_DX8SL4DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL4DXCTL2_IOAG_MASK) #define DDRPHY_DX8SL4DXCTL2_RESERVED_17_MASK (0x20000U) #define DDRPHY_DX8SL4DXCTL2_RESERVED_17_SHIFT (17U) /*! RESERVED_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_17_MASK) #define DDRPHY_DX8SL4DXCTL2_PREOEX_MASK (0xC0000U) #define DDRPHY_DX8SL4DXCTL2_PREOEX_SHIFT (18U) /*! PREOEX - OE Extension during Pre-amble */ #define DDRPHY_DX8SL4DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL4DXCTL2_PREOEX_MASK) #define DDRPHY_DX8SL4DXCTL2_POSOEX_MASK (0x700000U) #define DDRPHY_DX8SL4DXCTL2_POSOEX_SHIFT (20U) /*! POSOEX - OX Extension during Post-amble */ #define DDRPHY_DX8SL4DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL4DXCTL2_POSOEX_MASK) #define DDRPHY_DX8SL4DXCTL2_CRDEN_MASK (0x800000U) #define DDRPHY_DX8SL4DXCTL2_CRDEN_SHIFT (23U) /*! CRDEN - Configurable Read Data Enable */ #define DDRPHY_DX8SL4DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL4DXCTL2_CRDEN_MASK) #define DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SL4IOCR - DATX8 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX8SL4IOCR_DXRXM_MASK (0x7FFU) #define DDRPHY_DX8SL4IOCR_DXRXM_SHIFT (0U) /*! DXRXM - DX IO Receiver Mode */ #define DDRPHY_DX8SL4IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXRXM_MASK) #define DDRPHY_DX8SL4IOCR_DXTXM_MASK (0x3FF800U) #define DDRPHY_DX8SL4IOCR_DXTXM_SHIFT (11U) /*! DXTXM - DX IO Transmitter Mode */ #define DDRPHY_DX8SL4IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXTXM_MASK) #define DDRPHY_DX8SL4IOCR_DXIOM_MASK (0x1C00000U) #define DDRPHY_DX8SL4IOCR_DXIOM_SHIFT (22U) /*! DXIOM - DX IO Mode */ #define DDRPHY_DX8SL4IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXIOM_MASK) #define DDRPHY_DX8SL4IOCR_DXVREFIOM_MASK (0xE000000U) #define DDRPHY_DX8SL4IOCR_DXVREFIOM_SHIFT (25U) /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring */ #define DDRPHY_DX8SL4IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXVREFIOM_MASK) #define DDRPHY_DX8SL4IOCR_DXDACRANGE_MASK (0x70000000U) #define DDRPHY_DX8SL4IOCR_DXDACRANGE_SHIFT (28U) /*! DXDACRANGE - PVREF_DAC REFSEL range select */ #define DDRPHY_DX8SL4IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL4IOCR_DXDACRANGE_MASK) #define DDRPHY_DX8SL4IOCR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8SL4IOCR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL4IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL4IOCR_RESERVED_31_MASK) /*! @} */ /*! @name DX4SL4IOCR - DATX4 Slice 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX4SL4IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX4SL4IOCR_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4SL4IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL4IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL4IOCR_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL5OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */ /*! @{ */ #define DDRPHY_DX8SL5OSC_OSCEN_MASK (0x1U) #define DDRPHY_DX8SL5OSC_OSCEN_SHIFT (0U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_DX8SL5OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL5OSC_OSCEN_MASK) #define DDRPHY_DX8SL5OSC_OSCDIV_MASK (0x1EU) #define DDRPHY_DX8SL5OSC_OSCDIV_SHIFT (1U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_DX8SL5OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL5OSC_OSCDIV_MASK) #define DDRPHY_DX8SL5OSC_OSCWDL_MASK (0x60U) #define DDRPHY_DX8SL5OSC_OSCWDL_SHIFT (5U) /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select */ #define DDRPHY_DX8SL5OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL5OSC_OSCWDL_MASK) #define DDRPHY_DX8SL5OSC_RESERVED_8_7_MASK (0x180U) #define DDRPHY_DX8SL5OSC_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL5OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL5OSC_RESERVED_8_7_MASK) #define DDRPHY_DX8SL5OSC_OSCWDDL_MASK (0x600U) #define DDRPHY_DX8SL5OSC_OSCWDDL_SHIFT (9U) /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select */ #define DDRPHY_DX8SL5OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL5OSC_OSCWDDL_MASK) #define DDRPHY_DX8SL5OSC_RESERVED_12_11_MASK (0x1800U) #define DDRPHY_DX8SL5OSC_RESERVED_12_11_SHIFT (11U) /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL5OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL5OSC_RESERVED_12_11_MASK) #define DDRPHY_DX8SL5OSC_DLTMODE_MASK (0x2000U) #define DDRPHY_DX8SL5OSC_DLTMODE_SHIFT (13U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_DX8SL5OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL5OSC_DLTMODE_MASK) #define DDRPHY_DX8SL5OSC_DLTST_MASK (0x4000U) #define DDRPHY_DX8SL5OSC_DLTST_SHIFT (14U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_DX8SL5OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_DLTST_SHIFT)) & DDRPHY_DX8SL5OSC_DLTST_MASK) #define DDRPHY_DX8SL5OSC_PHYFRST_MASK (0x8000U) #define DDRPHY_DX8SL5OSC_PHYFRST_SHIFT (15U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_DX8SL5OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL5OSC_PHYFRST_MASK) #define DDRPHY_DX8SL5OSC_PHYHRST_MASK (0x10000U) #define DDRPHY_DX8SL5OSC_PHYHRST_SHIFT (16U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_DX8SL5OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL5OSC_PHYHRST_MASK) #define DDRPHY_DX8SL5OSC_LBDQSS_MASK (0x20000U) #define DDRPHY_DX8SL5OSC_LBDQSS_SHIFT (17U) /*! LBDQSS - Loopback DQS Shift */ #define DDRPHY_DX8SL5OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL5OSC_LBDQSS_MASK) #define DDRPHY_DX8SL5OSC_LBGDQS_MASK (0xC0000U) #define DDRPHY_DX8SL5OSC_LBGDQS_SHIFT (18U) /*! LBGDQS - Loopback DQS Gating */ #define DDRPHY_DX8SL5OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL5OSC_LBGDQS_MASK) #define DDRPHY_DX8SL5OSC_LBGSDQS_MASK (0x100000U) #define DDRPHY_DX8SL5OSC_LBGSDQS_SHIFT (20U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value */ #define DDRPHY_DX8SL5OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL5OSC_LBGSDQS_MASK) #define DDRPHY_DX8SL5OSC_LBMODE_MASK (0x200000U) #define DDRPHY_DX8SL5OSC_LBMODE_SHIFT (21U) /*! LBMODE - Loopback Mode */ #define DDRPHY_DX8SL5OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL5OSC_LBMODE_MASK) #define DDRPHY_DX8SL5OSC_CLKLEVEL_MASK (0xC00000U) #define DDRPHY_DX8SL5OSC_CLKLEVEL_SHIFT (22U) /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled. */ #define DDRPHY_DX8SL5OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL5OSC_CLKLEVEL_MASK) #define DDRPHY_DX8SL5OSC_GATEDXCTLCLK_MASK (0x3000000U) #define DDRPHY_DX8SL5OSC_GATEDXCTLCLK_SHIFT (24U) /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk */ #define DDRPHY_DX8SL5OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL5OSC_GATEDXCTLCLK_MASK) #define DDRPHY_DX8SL5OSC_GATEDXDDRCLK_MASK (0xC000000U) #define DDRPHY_DX8SL5OSC_GATEDXDDRCLK_SHIFT (26U) /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk */ #define DDRPHY_DX8SL5OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL5OSC_GATEDXDDRCLK_MASK) #define DDRPHY_DX8SL5OSC_GATEDXRDCLK_MASK (0x30000000U) #define DDRPHY_DX8SL5OSC_GATEDXRDCLK_SHIFT (28U) /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk */ #define DDRPHY_DX8SL5OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL5OSC_GATEDXRDCLK_MASK) #define DDRPHY_DX8SL5OSC_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8SL5OSC_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL5OSC_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8SL5PLLCR0 - DAXT8 0-1 PLL Control Register 0 */ /*! @{ */ #define DDRPHY_DX8SL5PLLCR0_DTC_MASK (0xFU) #define DDRPHY_DX8SL5PLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_DX8SL5PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_DTC_MASK) #define DDRPHY_DX8SL5PLLCR0_ATC_MASK (0xF0U) #define DDRPHY_DX8SL5PLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_DX8SL5PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_ATC_MASK) #define DDRPHY_DX8SL5PLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_DX8SL5PLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable (ATOEN) */ #define DDRPHY_DX8SL5PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL5PLLCR0_ATOEN_MASK) #define DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_MASK) #define DDRPHY_DX8SL5PLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_DX8SL5PLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_DX8SL5PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL5PLLCR0_GSHIFT_MASK) #define DDRPHY_DX8SL5PLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_DX8SL5PLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_DX8SL5PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_CPIC_MASK) #define DDRPHY_DX8SL5PLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_DX8SL5PLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_DX8SL5PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_CPPC_MASK) #define DDRPHY_DX8SL5PLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_DX8SL5PLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_DX8SL5PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL5PLLCR0_RLOCKM_MASK) #define DDRPHY_DX8SL5PLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_DX8SL5PLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_DX8SL5PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL5PLLCR0_FRQSEL_MASK) #define DDRPHY_DX8SL5PLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_DX8SL5PLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_DX8SL5PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL5PLLCR0_RSTOPM_MASK) #define DDRPHY_DX8SL5PLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_DX8SL5PLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_DX8SL5PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL5PLLCR0_PLLPD_MASK) #define DDRPHY_DX8SL5PLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_DX8SL5PLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_DX8SL5PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL5PLLCR0_PLLRST_MASK) #define DDRPHY_DX8SL5PLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_DX8SL5PLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_DX8SL5PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL5PLLCR0_PLLBYP_MASK) /*! @} */ /*! @name DX8SL5PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL5PLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_DX8SL5PLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_DX8SL5PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL5PLLCR1_LOCKDS_MASK) #define DDRPHY_DX8SL5PLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_DX8SL5PLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_DX8SL5PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL5PLLCR1_LOCKCS_MASK) #define DDRPHY_DX8SL5PLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_DX8SL5PLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_DX8SL5PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL5PLLCR1_LOCKPS_MASK) #define DDRPHY_DX8SL5PLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_DX8SL5PLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_DX8SL5PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL5PLLCR1_BYPVDD_MASK) #define DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_DX8SL5PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_MASK) #define DDRPHY_DX8SL5PLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_DX8SL5PLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_DX8SL5PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL5PLLCR1_BYPVREGCP_MASK) #define DDRPHY_DX8SL5PLLCR1_PLLPROG_MASK (0x3FFFC0U) #define DDRPHY_DX8SL5PLLCR1_PLLPROG_SHIFT (6U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_DX8SL5PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL5PLLCR1_PLLPROG_MASK) #define DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8SL5PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name DX8SL5PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name DX8SL5PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name DX8SL5PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DX8SL5DQSCTL - DATX8 0-1 DQS Control Register */ /*! @{ */ #define DDRPHY_DX8SL5DQSCTL_DQSRES_MASK (0xFU) #define DDRPHY_DX8SL5DQSCTL_DQSRES_SHIFT (0U) /*! DQSRES - DQS Resistor */ #define DDRPHY_DX8SL5DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DQSRES_MASK) #define DDRPHY_DX8SL5DQSCTL_DQSNRES_MASK (0xF0U) #define DDRPHY_DX8SL5DQSCTL_DQSNRES_SHIFT (4U) /*! DQSNRES - DQS_N Resistor */ #define DDRPHY_DX8SL5DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DQSNRES_MASK) #define DDRPHY_DX8SL5DQSCTL_DXSR_MASK (0x300U) #define DDRPHY_DX8SL5DQSCTL_DXSR_SHIFT (8U) /*! DXSR - Data Slew Rate */ #define DDRPHY_DX8SL5DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DXSR_MASK) #define DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_MASK (0x1C00U) #define DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_SHIFT (10U) /*! RESERVED_12_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_MASK) #define DDRPHY_DX8SL5DQSCTL_UDQIOM_MASK (0x2000U) #define DDRPHY_DX8SL5DQSCTL_UDQIOM_SHIFT (13U) /*! UDQIOM - Unused DQ I/O Mode */ #define DDRPHY_DX8SL5DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL5DQSCTL_UDQIOM_MASK) #define DDRPHY_DX8SL5DQSCTL_QSCNTEN_MASK (0x4000U) #define DDRPHY_DX8SL5DQSCTL_QSCNTEN_SHIFT (14U) /*! QSCNTEN - QS Counter Enable */ #define DDRPHY_DX8SL5DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL5DQSCTL_QSCNTEN_MASK) #define DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_MASK (0x18000U) #define DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_SHIFT (15U) /*! RESERVED_16_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_MASK) #define DDRPHY_DX8SL5DQSCTL_LPIOPD_MASK (0x20000U) #define DDRPHY_DX8SL5DQSCTL_LPIOPD_SHIFT (17U) /*! LPIOPD - Low Power I/O Power Down */ #define DDRPHY_DX8SL5DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL5DQSCTL_LPIOPD_MASK) #define DDRPHY_DX8SL5DQSCTL_LPPLLPD_MASK (0x40000U) #define DDRPHY_DX8SL5DQSCTL_LPPLLPD_SHIFT (18U) /*! LPPLLPD - Low Power PLL Power Down */ #define DDRPHY_DX8SL5DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL5DQSCTL_LPPLLPD_MASK) #define DDRPHY_DX8SL5DQSCTL_DQSGX_MASK (0x180000U) #define DDRPHY_DX8SL5DQSCTL_DQSGX_SHIFT (19U) /*! DQSGX - DQS Gate Extension */ #define DDRPHY_DX8SL5DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DQSGX_MASK) #define DDRPHY_DX8SL5DQSCTL_WRRMODE_MASK (0x200000U) #define DDRPHY_DX8SL5DQSCTL_WRRMODE_SHIFT (21U) /*! WRRMODE - Write Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL5DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL5DQSCTL_WRRMODE_MASK) #define DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_MASK) #define DDRPHY_DX8SL5DQSCTL_RRRMODE_MASK (0x1000000U) #define DDRPHY_DX8SL5DQSCTL_RRRMODE_SHIFT (24U) /*! RRRMODE - Read Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL5DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RRRMODE_MASK) #define DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL5TRNCTL - DATX8 0-1 Training Control Register */ /*! @{ */ #define DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL5DDLCTL - DATX8 0-1 DDL Control Register */ /*! @{ */ #define DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_MASK (0x3U) #define DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_SHIFT (0U) /*! DDLBYPMODE - Controls DDL Bypass Mode */ #define DDRPHY_DX8SL5DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_MASK) #define DDRPHY_DX8SL5DDLCTL_DXDDLBYP_MASK (0x3FFFCU) #define DDRPHY_DX8SL5DDLCTL_DXDDLBYP_SHIFT (2U) /*! DXDDLBYP - DATX8 DDL Bypass */ #define DDRPHY_DX8SL5DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DXDDLBYP_MASK) #define DDRPHY_DX8SL5DDLCTL_DXDDLLD_MASK (0x7C0000U) #define DDRPHY_DX8SL5DDLCTL_DXDDLLD_SHIFT (18U) /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load */ #define DDRPHY_DX8SL5DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DXDDLLD_MASK) #define DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_MASK (0x1800000U) #define DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_SHIFT (23U) /*! RESERVED_24_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_MASK) #define DDRPHY_DX8SL5DDLCTL_DXDDLLDT_MASK (0x2000000U) #define DDRPHY_DX8SL5DDLCTL_DXDDLLDT_SHIFT (25U) /*! DXDDLLDT - DX DDL Load Type */ #define DDRPHY_DX8SL5DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DXDDLLDT_MASK) #define DDRPHY_DX8SL5DDLCTL_DLYLDTM_MASK (0x4000000U) #define DDRPHY_DX8SL5DDLCTL_DLYLDTM_SHIFT (26U) /*! DLYLDTM - Delay Load Timing */ #define DDRPHY_DX8SL5DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DLYLDTM_MASK) #define DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8SL5DXCTL1 - DATX8 0-1 DX Control Register 1 */ /*! @{ */ #define DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_MASK (0xFFFFU) #define DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_SHIFT (0U) /*! RESERVED_15_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_MASK) #define DDRPHY_DX8SL5DXCTL1_DXTMODE_MASK (0x10000U) #define DDRPHY_DX8SL5DXCTL1_DXTMODE_SHIFT (16U) /*! DXTMODE - DATX8 Test Mode */ #define DDRPHY_DX8SL5DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXTMODE_MASK) #define DDRPHY_DX8SL5DXCTL1_DXGDBYP_MASK (0x20000U) #define DDRPHY_DX8SL5DXCTL1_DXGDBYP_SHIFT (17U) /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode */ #define DDRPHY_DX8SL5DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXGDBYP_MASK) #define DDRPHY_DX8SL5DXCTL1_DXQSDBYP_MASK (0x40000U) #define DDRPHY_DX8SL5DXCTL1_DXQSDBYP_SHIFT (18U) /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode */ #define DDRPHY_DX8SL5DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXQSDBYP_MASK) #define DDRPHY_DX8SL5DXCTL1_DXGSMD_MASK (0x80000U) #define DDRPHY_DX8SL5DXCTL1_DXGSMD_SHIFT (19U) /*! DXGSMD - Read DQS Gating Status Mode */ #define DDRPHY_DX8SL5DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXGSMD_MASK) #define DDRPHY_DX8SL5DXCTL1_DXDTOSEL_MASK (0x300000U) #define DDRPHY_DX8SL5DXCTL1_DXDTOSEL_SHIFT (20U) /*! DXDTOSEL - DATX8 Digital Test Output Select */ #define DDRPHY_DX8SL5DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXDTOSEL_MASK) #define DDRPHY_DX8SL5DXCTL1_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8SL5DXCTL1_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL5DXCTL1_RESERVED_22_MASK) #define DDRPHY_DX8SL5DXCTL1_DXRCLKMD_MASK (0x800000U) #define DDRPHY_DX8SL5DXCTL1_DXRCLKMD_SHIFT (23U) /*! DXRCLKMD - DATX8 Read Clock Mode */ #define DDRPHY_DX8SL5DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXRCLKMD_MASK) #define DDRPHY_DX8SL5DXCTL1_DXCALCLK_MASK (0x1000000U) #define DDRPHY_DX8SL5DXCTL1_DXCALCLK_SHIFT (24U) /*! DXCALCLK - DATX Calibration Clock Select */ #define DDRPHY_DX8SL5DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXCALCLK_MASK) #define DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL5DXCTL2 - DATX8 0-1 DX Control Register 2 */ /*! @{ */ #define DDRPHY_DX8SL5DXCTL2_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8SL5DXCTL2_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_0_MASK) #define DDRPHY_DX8SL5DXCTL2_DQSGLB_MASK (0x6U) #define DDRPHY_DX8SL5DXCTL2_DQSGLB_SHIFT (1U) /*! DQSGLB - Read DQS Gate I/O Loopback */ #define DDRPHY_DX8SL5DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL5DXCTL2_DQSGLB_MASK) #define DDRPHY_DX8SL5DXCTL2_DISRST_MASK (0x8U) #define DDRPHY_DX8SL5DXCTL2_DISRST_SHIFT (3U) /*! DISRST - Disables the Read FIFO Reset */ #define DDRPHY_DX8SL5DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL5DXCTL2_DISRST_MASK) #define DDRPHY_DX8SL5DXCTL2_RDMODE_MASK (0x30U) #define DDRPHY_DX8SL5DXCTL2_RDMODE_SHIFT (4U) /*! RDMODE - DATX8 Receive FIFO Read Mode */ #define DDRPHY_DX8SL5DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RDMODE_MASK) #define DDRPHY_DX8SL5DXCTL2_PRFBYP_MASK (0x40U) #define DDRPHY_DX8SL5DXCTL2_PRFBYP_SHIFT (6U) /*! PRFBYP - PUB Read FIFO Bypass */ #define DDRPHY_DX8SL5DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL5DXCTL2_PRFBYP_MASK) #define DDRPHY_DX8SL5DXCTL2_WDBI_MASK (0x80U) #define DDRPHY_DX8SL5DXCTL2_WDBI_SHIFT (7U) /*! WDBI - Write Data Bus Inversion Enable */ #define DDRPHY_DX8SL5DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL5DXCTL2_WDBI_MASK) #define DDRPHY_DX8SL5DXCTL2_RDBI_MASK (0x100U) #define DDRPHY_DX8SL5DXCTL2_RDBI_SHIFT (8U) /*! RDBI - Read Data Bus Inversion Enable */ #define DDRPHY_DX8SL5DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RDBI_MASK) #define DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U) #define DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_SHIFT (9U) /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold */ #define DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_MASK) #define DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_MASK (0x6000U) #define DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_SHIFT (13U) /*! RESERVED_14_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_MASK) #define DDRPHY_DX8SL5DXCTL2_IOLB_MASK (0x8000U) #define DDRPHY_DX8SL5DXCTL2_IOLB_SHIFT (15U) /*! IOLB - I/O Loopback Select */ #define DDRPHY_DX8SL5DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL5DXCTL2_IOLB_MASK) #define DDRPHY_DX8SL5DXCTL2_IOAG_MASK (0x10000U) #define DDRPHY_DX8SL5DXCTL2_IOAG_SHIFT (16U) /*! IOAG - I/O Assisted Gate Select */ #define DDRPHY_DX8SL5DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL5DXCTL2_IOAG_MASK) #define DDRPHY_DX8SL5DXCTL2_RESERVED_17_MASK (0x20000U) #define DDRPHY_DX8SL5DXCTL2_RESERVED_17_SHIFT (17U) /*! RESERVED_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_17_MASK) #define DDRPHY_DX8SL5DXCTL2_PREOEX_MASK (0xC0000U) #define DDRPHY_DX8SL5DXCTL2_PREOEX_SHIFT (18U) /*! PREOEX - OE Extension during Pre-amble */ #define DDRPHY_DX8SL5DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL5DXCTL2_PREOEX_MASK) #define DDRPHY_DX8SL5DXCTL2_POSOEX_MASK (0x700000U) #define DDRPHY_DX8SL5DXCTL2_POSOEX_SHIFT (20U) /*! POSOEX - OX Extension during Post-amble */ #define DDRPHY_DX8SL5DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL5DXCTL2_POSOEX_MASK) #define DDRPHY_DX8SL5DXCTL2_CRDEN_MASK (0x800000U) #define DDRPHY_DX8SL5DXCTL2_CRDEN_SHIFT (23U) /*! CRDEN - Configurable Read Data Enable */ #define DDRPHY_DX8SL5DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL5DXCTL2_CRDEN_MASK) #define DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SL5IOCR - DATX8 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX8SL5IOCR_DXRXM_MASK (0x7FFU) #define DDRPHY_DX8SL5IOCR_DXRXM_SHIFT (0U) /*! DXRXM - DX IO Receiver Mode */ #define DDRPHY_DX8SL5IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXRXM_MASK) #define DDRPHY_DX8SL5IOCR_DXTXM_MASK (0x3FF800U) #define DDRPHY_DX8SL5IOCR_DXTXM_SHIFT (11U) /*! DXTXM - DX IO Transmitter Mode */ #define DDRPHY_DX8SL5IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXTXM_MASK) #define DDRPHY_DX8SL5IOCR_DXIOM_MASK (0x1C00000U) #define DDRPHY_DX8SL5IOCR_DXIOM_SHIFT (22U) /*! DXIOM - DX IO Mode */ #define DDRPHY_DX8SL5IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXIOM_MASK) #define DDRPHY_DX8SL5IOCR_DXVREFIOM_MASK (0xE000000U) #define DDRPHY_DX8SL5IOCR_DXVREFIOM_SHIFT (25U) /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring */ #define DDRPHY_DX8SL5IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXVREFIOM_MASK) #define DDRPHY_DX8SL5IOCR_DXDACRANGE_MASK (0x70000000U) #define DDRPHY_DX8SL5IOCR_DXDACRANGE_SHIFT (28U) /*! DXDACRANGE - PVREF_DAC REFSEL range select */ #define DDRPHY_DX8SL5IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL5IOCR_DXDACRANGE_MASK) #define DDRPHY_DX8SL5IOCR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8SL5IOCR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL5IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL5IOCR_RESERVED_31_MASK) /*! @} */ /*! @name DX4SL5IOCR - DATX4 Slice 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX4SL5IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX4SL5IOCR_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4SL5IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL5IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL5IOCR_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL6OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */ /*! @{ */ #define DDRPHY_DX8SL6OSC_OSCEN_MASK (0x1U) #define DDRPHY_DX8SL6OSC_OSCEN_SHIFT (0U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_DX8SL6OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL6OSC_OSCEN_MASK) #define DDRPHY_DX8SL6OSC_OSCDIV_MASK (0x1EU) #define DDRPHY_DX8SL6OSC_OSCDIV_SHIFT (1U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_DX8SL6OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL6OSC_OSCDIV_MASK) #define DDRPHY_DX8SL6OSC_OSCWDL_MASK (0x60U) #define DDRPHY_DX8SL6OSC_OSCWDL_SHIFT (5U) /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select */ #define DDRPHY_DX8SL6OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL6OSC_OSCWDL_MASK) #define DDRPHY_DX8SL6OSC_RESERVED_8_7_MASK (0x180U) #define DDRPHY_DX8SL6OSC_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL6OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL6OSC_RESERVED_8_7_MASK) #define DDRPHY_DX8SL6OSC_OSCWDDL_MASK (0x600U) #define DDRPHY_DX8SL6OSC_OSCWDDL_SHIFT (9U) /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select */ #define DDRPHY_DX8SL6OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL6OSC_OSCWDDL_MASK) #define DDRPHY_DX8SL6OSC_RESERVED_12_11_MASK (0x1800U) #define DDRPHY_DX8SL6OSC_RESERVED_12_11_SHIFT (11U) /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL6OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL6OSC_RESERVED_12_11_MASK) #define DDRPHY_DX8SL6OSC_DLTMODE_MASK (0x2000U) #define DDRPHY_DX8SL6OSC_DLTMODE_SHIFT (13U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_DX8SL6OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL6OSC_DLTMODE_MASK) #define DDRPHY_DX8SL6OSC_DLTST_MASK (0x4000U) #define DDRPHY_DX8SL6OSC_DLTST_SHIFT (14U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_DX8SL6OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_DLTST_SHIFT)) & DDRPHY_DX8SL6OSC_DLTST_MASK) #define DDRPHY_DX8SL6OSC_PHYFRST_MASK (0x8000U) #define DDRPHY_DX8SL6OSC_PHYFRST_SHIFT (15U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_DX8SL6OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL6OSC_PHYFRST_MASK) #define DDRPHY_DX8SL6OSC_PHYHRST_MASK (0x10000U) #define DDRPHY_DX8SL6OSC_PHYHRST_SHIFT (16U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_DX8SL6OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL6OSC_PHYHRST_MASK) #define DDRPHY_DX8SL6OSC_LBDQSS_MASK (0x20000U) #define DDRPHY_DX8SL6OSC_LBDQSS_SHIFT (17U) /*! LBDQSS - Loopback DQS Shift */ #define DDRPHY_DX8SL6OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL6OSC_LBDQSS_MASK) #define DDRPHY_DX8SL6OSC_LBGDQS_MASK (0xC0000U) #define DDRPHY_DX8SL6OSC_LBGDQS_SHIFT (18U) /*! LBGDQS - Loopback DQS Gating */ #define DDRPHY_DX8SL6OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL6OSC_LBGDQS_MASK) #define DDRPHY_DX8SL6OSC_LBGSDQS_MASK (0x100000U) #define DDRPHY_DX8SL6OSC_LBGSDQS_SHIFT (20U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value */ #define DDRPHY_DX8SL6OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL6OSC_LBGSDQS_MASK) #define DDRPHY_DX8SL6OSC_LBMODE_MASK (0x200000U) #define DDRPHY_DX8SL6OSC_LBMODE_SHIFT (21U) /*! LBMODE - Loopback Mode */ #define DDRPHY_DX8SL6OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL6OSC_LBMODE_MASK) #define DDRPHY_DX8SL6OSC_CLKLEVEL_MASK (0xC00000U) #define DDRPHY_DX8SL6OSC_CLKLEVEL_SHIFT (22U) /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled. */ #define DDRPHY_DX8SL6OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL6OSC_CLKLEVEL_MASK) #define DDRPHY_DX8SL6OSC_GATEDXCTLCLK_MASK (0x3000000U) #define DDRPHY_DX8SL6OSC_GATEDXCTLCLK_SHIFT (24U) /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk */ #define DDRPHY_DX8SL6OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL6OSC_GATEDXCTLCLK_MASK) #define DDRPHY_DX8SL6OSC_GATEDXDDRCLK_MASK (0xC000000U) #define DDRPHY_DX8SL6OSC_GATEDXDDRCLK_SHIFT (26U) /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk */ #define DDRPHY_DX8SL6OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL6OSC_GATEDXDDRCLK_MASK) #define DDRPHY_DX8SL6OSC_GATEDXRDCLK_MASK (0x30000000U) #define DDRPHY_DX8SL6OSC_GATEDXRDCLK_SHIFT (28U) /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk */ #define DDRPHY_DX8SL6OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL6OSC_GATEDXRDCLK_MASK) #define DDRPHY_DX8SL6OSC_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8SL6OSC_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL6OSC_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8SL6PLLCR0 - DAXT8 0-1 PLL Control Register 0 */ /*! @{ */ #define DDRPHY_DX8SL6PLLCR0_DTC_MASK (0xFU) #define DDRPHY_DX8SL6PLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_DX8SL6PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_DTC_MASK) #define DDRPHY_DX8SL6PLLCR0_ATC_MASK (0xF0U) #define DDRPHY_DX8SL6PLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_DX8SL6PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_ATC_MASK) #define DDRPHY_DX8SL6PLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_DX8SL6PLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable (ATOEN) */ #define DDRPHY_DX8SL6PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL6PLLCR0_ATOEN_MASK) #define DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_MASK) #define DDRPHY_DX8SL6PLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_DX8SL6PLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_DX8SL6PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL6PLLCR0_GSHIFT_MASK) #define DDRPHY_DX8SL6PLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_DX8SL6PLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_DX8SL6PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_CPIC_MASK) #define DDRPHY_DX8SL6PLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_DX8SL6PLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_DX8SL6PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_CPPC_MASK) #define DDRPHY_DX8SL6PLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_DX8SL6PLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_DX8SL6PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL6PLLCR0_RLOCKM_MASK) #define DDRPHY_DX8SL6PLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_DX8SL6PLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_DX8SL6PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL6PLLCR0_FRQSEL_MASK) #define DDRPHY_DX8SL6PLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_DX8SL6PLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_DX8SL6PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL6PLLCR0_RSTOPM_MASK) #define DDRPHY_DX8SL6PLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_DX8SL6PLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_DX8SL6PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL6PLLCR0_PLLPD_MASK) #define DDRPHY_DX8SL6PLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_DX8SL6PLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_DX8SL6PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL6PLLCR0_PLLRST_MASK) #define DDRPHY_DX8SL6PLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_DX8SL6PLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_DX8SL6PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL6PLLCR0_PLLBYP_MASK) /*! @} */ /*! @name DX8SL6PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL6PLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_DX8SL6PLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_DX8SL6PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL6PLLCR1_LOCKDS_MASK) #define DDRPHY_DX8SL6PLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_DX8SL6PLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_DX8SL6PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL6PLLCR1_LOCKCS_MASK) #define DDRPHY_DX8SL6PLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_DX8SL6PLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_DX8SL6PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL6PLLCR1_LOCKPS_MASK) #define DDRPHY_DX8SL6PLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_DX8SL6PLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_DX8SL6PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL6PLLCR1_BYPVDD_MASK) #define DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_DX8SL6PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_MASK) #define DDRPHY_DX8SL6PLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_DX8SL6PLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_DX8SL6PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL6PLLCR1_BYPVREGCP_MASK) #define DDRPHY_DX8SL6PLLCR1_PLLPROG_MASK (0x3FFFC0U) #define DDRPHY_DX8SL6PLLCR1_PLLPROG_SHIFT (6U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_DX8SL6PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL6PLLCR1_PLLPROG_MASK) #define DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8SL6PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name DX8SL6PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name DX8SL6PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name DX8SL6PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DX8SL6DQSCTL - DATX8 0-1 DQS Control Register */ /*! @{ */ #define DDRPHY_DX8SL6DQSCTL_DQSRES_MASK (0xFU) #define DDRPHY_DX8SL6DQSCTL_DQSRES_SHIFT (0U) /*! DQSRES - DQS Resistor */ #define DDRPHY_DX8SL6DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DQSRES_MASK) #define DDRPHY_DX8SL6DQSCTL_DQSNRES_MASK (0xF0U) #define DDRPHY_DX8SL6DQSCTL_DQSNRES_SHIFT (4U) /*! DQSNRES - DQS_N Resistor */ #define DDRPHY_DX8SL6DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DQSNRES_MASK) #define DDRPHY_DX8SL6DQSCTL_DXSR_MASK (0x300U) #define DDRPHY_DX8SL6DQSCTL_DXSR_SHIFT (8U) /*! DXSR - Data Slew Rate */ #define DDRPHY_DX8SL6DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DXSR_MASK) #define DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_MASK (0x1C00U) #define DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_SHIFT (10U) /*! RESERVED_12_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_MASK) #define DDRPHY_DX8SL6DQSCTL_UDQIOM_MASK (0x2000U) #define DDRPHY_DX8SL6DQSCTL_UDQIOM_SHIFT (13U) /*! UDQIOM - Unused DQ I/O Mode */ #define DDRPHY_DX8SL6DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL6DQSCTL_UDQIOM_MASK) #define DDRPHY_DX8SL6DQSCTL_QSCNTEN_MASK (0x4000U) #define DDRPHY_DX8SL6DQSCTL_QSCNTEN_SHIFT (14U) /*! QSCNTEN - QS Counter Enable */ #define DDRPHY_DX8SL6DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL6DQSCTL_QSCNTEN_MASK) #define DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_MASK (0x18000U) #define DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_SHIFT (15U) /*! RESERVED_16_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_MASK) #define DDRPHY_DX8SL6DQSCTL_LPIOPD_MASK (0x20000U) #define DDRPHY_DX8SL6DQSCTL_LPIOPD_SHIFT (17U) /*! LPIOPD - Low Power I/O Power Down */ #define DDRPHY_DX8SL6DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL6DQSCTL_LPIOPD_MASK) #define DDRPHY_DX8SL6DQSCTL_LPPLLPD_MASK (0x40000U) #define DDRPHY_DX8SL6DQSCTL_LPPLLPD_SHIFT (18U) /*! LPPLLPD - Low Power PLL Power Down */ #define DDRPHY_DX8SL6DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL6DQSCTL_LPPLLPD_MASK) #define DDRPHY_DX8SL6DQSCTL_DQSGX_MASK (0x180000U) #define DDRPHY_DX8SL6DQSCTL_DQSGX_SHIFT (19U) /*! DQSGX - DQS Gate Extension */ #define DDRPHY_DX8SL6DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DQSGX_MASK) #define DDRPHY_DX8SL6DQSCTL_WRRMODE_MASK (0x200000U) #define DDRPHY_DX8SL6DQSCTL_WRRMODE_SHIFT (21U) /*! WRRMODE - Write Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL6DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL6DQSCTL_WRRMODE_MASK) #define DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_MASK) #define DDRPHY_DX8SL6DQSCTL_RRRMODE_MASK (0x1000000U) #define DDRPHY_DX8SL6DQSCTL_RRRMODE_SHIFT (24U) /*! RRRMODE - Read Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL6DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RRRMODE_MASK) #define DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL6TRNCTL - DATX8 0-1 Training Control Register */ /*! @{ */ #define DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL6DDLCTL - DATX8 0-1 DDL Control Register */ /*! @{ */ #define DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_MASK (0x3U) #define DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_SHIFT (0U) /*! DDLBYPMODE - Controls DDL Bypass Mode */ #define DDRPHY_DX8SL6DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_MASK) #define DDRPHY_DX8SL6DDLCTL_DXDDLBYP_MASK (0x3FFFCU) #define DDRPHY_DX8SL6DDLCTL_DXDDLBYP_SHIFT (2U) /*! DXDDLBYP - DATX8 DDL Bypass */ #define DDRPHY_DX8SL6DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DXDDLBYP_MASK) #define DDRPHY_DX8SL6DDLCTL_DXDDLLD_MASK (0x7C0000U) #define DDRPHY_DX8SL6DDLCTL_DXDDLLD_SHIFT (18U) /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load */ #define DDRPHY_DX8SL6DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DXDDLLD_MASK) #define DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_MASK (0x1800000U) #define DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_SHIFT (23U) /*! RESERVED_24_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_MASK) #define DDRPHY_DX8SL6DDLCTL_DXDDLLDT_MASK (0x2000000U) #define DDRPHY_DX8SL6DDLCTL_DXDDLLDT_SHIFT (25U) /*! DXDDLLDT - DX DDL Load Type */ #define DDRPHY_DX8SL6DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DXDDLLDT_MASK) #define DDRPHY_DX8SL6DDLCTL_DLYLDTM_MASK (0x4000000U) #define DDRPHY_DX8SL6DDLCTL_DLYLDTM_SHIFT (26U) /*! DLYLDTM - Delay Load Timing */ #define DDRPHY_DX8SL6DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DLYLDTM_MASK) #define DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8SL6DXCTL1 - DATX8 0-1 DX Control Register 1 */ /*! @{ */ #define DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_MASK (0xFFFFU) #define DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_SHIFT (0U) /*! RESERVED_15_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_MASK) #define DDRPHY_DX8SL6DXCTL1_DXTMODE_MASK (0x10000U) #define DDRPHY_DX8SL6DXCTL1_DXTMODE_SHIFT (16U) /*! DXTMODE - DATX8 Test Mode */ #define DDRPHY_DX8SL6DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXTMODE_MASK) #define DDRPHY_DX8SL6DXCTL1_DXGDBYP_MASK (0x20000U) #define DDRPHY_DX8SL6DXCTL1_DXGDBYP_SHIFT (17U) /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode */ #define DDRPHY_DX8SL6DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXGDBYP_MASK) #define DDRPHY_DX8SL6DXCTL1_DXQSDBYP_MASK (0x40000U) #define DDRPHY_DX8SL6DXCTL1_DXQSDBYP_SHIFT (18U) /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode */ #define DDRPHY_DX8SL6DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXQSDBYP_MASK) #define DDRPHY_DX8SL6DXCTL1_DXGSMD_MASK (0x80000U) #define DDRPHY_DX8SL6DXCTL1_DXGSMD_SHIFT (19U) /*! DXGSMD - Read DQS Gating Status Mode */ #define DDRPHY_DX8SL6DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXGSMD_MASK) #define DDRPHY_DX8SL6DXCTL1_DXDTOSEL_MASK (0x300000U) #define DDRPHY_DX8SL6DXCTL1_DXDTOSEL_SHIFT (20U) /*! DXDTOSEL - DATX8 Digital Test Output Select */ #define DDRPHY_DX8SL6DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXDTOSEL_MASK) #define DDRPHY_DX8SL6DXCTL1_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8SL6DXCTL1_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL6DXCTL1_RESERVED_22_MASK) #define DDRPHY_DX8SL6DXCTL1_DXRCLKMD_MASK (0x800000U) #define DDRPHY_DX8SL6DXCTL1_DXRCLKMD_SHIFT (23U) /*! DXRCLKMD - DATX8 Read Clock Mode */ #define DDRPHY_DX8SL6DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXRCLKMD_MASK) #define DDRPHY_DX8SL6DXCTL1_DXCALCLK_MASK (0x1000000U) #define DDRPHY_DX8SL6DXCTL1_DXCALCLK_SHIFT (24U) /*! DXCALCLK - DATX Calibration Clock Select */ #define DDRPHY_DX8SL6DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXCALCLK_MASK) #define DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL6DXCTL2 - DATX8 0-1 DX Control Register 2 */ /*! @{ */ #define DDRPHY_DX8SL6DXCTL2_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8SL6DXCTL2_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_0_MASK) #define DDRPHY_DX8SL6DXCTL2_DQSGLB_MASK (0x6U) #define DDRPHY_DX8SL6DXCTL2_DQSGLB_SHIFT (1U) /*! DQSGLB - Read DQS Gate I/O Loopback */ #define DDRPHY_DX8SL6DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL6DXCTL2_DQSGLB_MASK) #define DDRPHY_DX8SL6DXCTL2_DISRST_MASK (0x8U) #define DDRPHY_DX8SL6DXCTL2_DISRST_SHIFT (3U) /*! DISRST - Disables the Read FIFO Reset */ #define DDRPHY_DX8SL6DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL6DXCTL2_DISRST_MASK) #define DDRPHY_DX8SL6DXCTL2_RDMODE_MASK (0x30U) #define DDRPHY_DX8SL6DXCTL2_RDMODE_SHIFT (4U) /*! RDMODE - DATX8 Receive FIFO Read Mode */ #define DDRPHY_DX8SL6DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RDMODE_MASK) #define DDRPHY_DX8SL6DXCTL2_PRFBYP_MASK (0x40U) #define DDRPHY_DX8SL6DXCTL2_PRFBYP_SHIFT (6U) /*! PRFBYP - PUB Read FIFO Bypass */ #define DDRPHY_DX8SL6DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL6DXCTL2_PRFBYP_MASK) #define DDRPHY_DX8SL6DXCTL2_WDBI_MASK (0x80U) #define DDRPHY_DX8SL6DXCTL2_WDBI_SHIFT (7U) /*! WDBI - Write Data Bus Inversion Enable */ #define DDRPHY_DX8SL6DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL6DXCTL2_WDBI_MASK) #define DDRPHY_DX8SL6DXCTL2_RDBI_MASK (0x100U) #define DDRPHY_DX8SL6DXCTL2_RDBI_SHIFT (8U) /*! RDBI - Read Data Bus Inversion Enable */ #define DDRPHY_DX8SL6DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RDBI_MASK) #define DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U) #define DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_SHIFT (9U) /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold */ #define DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_MASK) #define DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_MASK (0x6000U) #define DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_SHIFT (13U) /*! RESERVED_14_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_MASK) #define DDRPHY_DX8SL6DXCTL2_IOLB_MASK (0x8000U) #define DDRPHY_DX8SL6DXCTL2_IOLB_SHIFT (15U) /*! IOLB - I/O Loopback Select */ #define DDRPHY_DX8SL6DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL6DXCTL2_IOLB_MASK) #define DDRPHY_DX8SL6DXCTL2_IOAG_MASK (0x10000U) #define DDRPHY_DX8SL6DXCTL2_IOAG_SHIFT (16U) /*! IOAG - I/O Assisted Gate Select */ #define DDRPHY_DX8SL6DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL6DXCTL2_IOAG_MASK) #define DDRPHY_DX8SL6DXCTL2_RESERVED_17_MASK (0x20000U) #define DDRPHY_DX8SL6DXCTL2_RESERVED_17_SHIFT (17U) /*! RESERVED_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_17_MASK) #define DDRPHY_DX8SL6DXCTL2_PREOEX_MASK (0xC0000U) #define DDRPHY_DX8SL6DXCTL2_PREOEX_SHIFT (18U) /*! PREOEX - OE Extension during Pre-amble */ #define DDRPHY_DX8SL6DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL6DXCTL2_PREOEX_MASK) #define DDRPHY_DX8SL6DXCTL2_POSOEX_MASK (0x700000U) #define DDRPHY_DX8SL6DXCTL2_POSOEX_SHIFT (20U) /*! POSOEX - OX Extension during Post-amble */ #define DDRPHY_DX8SL6DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL6DXCTL2_POSOEX_MASK) #define DDRPHY_DX8SL6DXCTL2_CRDEN_MASK (0x800000U) #define DDRPHY_DX8SL6DXCTL2_CRDEN_SHIFT (23U) /*! CRDEN - Configurable Read Data Enable */ #define DDRPHY_DX8SL6DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL6DXCTL2_CRDEN_MASK) #define DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SL6IOCR - DATX8 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX8SL6IOCR_DXRXM_MASK (0x7FFU) #define DDRPHY_DX8SL6IOCR_DXRXM_SHIFT (0U) /*! DXRXM - DX IO Receiver Mode */ #define DDRPHY_DX8SL6IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXRXM_MASK) #define DDRPHY_DX8SL6IOCR_DXTXM_MASK (0x3FF800U) #define DDRPHY_DX8SL6IOCR_DXTXM_SHIFT (11U) /*! DXTXM - DX IO Transmitter Mode */ #define DDRPHY_DX8SL6IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXTXM_MASK) #define DDRPHY_DX8SL6IOCR_DXIOM_MASK (0x1C00000U) #define DDRPHY_DX8SL6IOCR_DXIOM_SHIFT (22U) /*! DXIOM - DX IO Mode */ #define DDRPHY_DX8SL6IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXIOM_MASK) #define DDRPHY_DX8SL6IOCR_DXVREFIOM_MASK (0xE000000U) #define DDRPHY_DX8SL6IOCR_DXVREFIOM_SHIFT (25U) /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring */ #define DDRPHY_DX8SL6IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXVREFIOM_MASK) #define DDRPHY_DX8SL6IOCR_DXDACRANGE_MASK (0x70000000U) #define DDRPHY_DX8SL6IOCR_DXDACRANGE_SHIFT (28U) /*! DXDACRANGE - PVREF_DAC REFSEL range select */ #define DDRPHY_DX8SL6IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL6IOCR_DXDACRANGE_MASK) #define DDRPHY_DX8SL6IOCR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8SL6IOCR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL6IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL6IOCR_RESERVED_31_MASK) /*! @} */ /*! @name DX4SL6IOCR - DATX4 Slice 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX4SL6IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX4SL6IOCR_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4SL6IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL6IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL6IOCR_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL7OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */ /*! @{ */ #define DDRPHY_DX8SL7OSC_OSCEN_MASK (0x1U) #define DDRPHY_DX8SL7OSC_OSCEN_SHIFT (0U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_DX8SL7OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL7OSC_OSCEN_MASK) #define DDRPHY_DX8SL7OSC_OSCDIV_MASK (0x1EU) #define DDRPHY_DX8SL7OSC_OSCDIV_SHIFT (1U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_DX8SL7OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL7OSC_OSCDIV_MASK) #define DDRPHY_DX8SL7OSC_OSCWDL_MASK (0x60U) #define DDRPHY_DX8SL7OSC_OSCWDL_SHIFT (5U) /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select */ #define DDRPHY_DX8SL7OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL7OSC_OSCWDL_MASK) #define DDRPHY_DX8SL7OSC_RESERVED_8_7_MASK (0x180U) #define DDRPHY_DX8SL7OSC_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL7OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL7OSC_RESERVED_8_7_MASK) #define DDRPHY_DX8SL7OSC_OSCWDDL_MASK (0x600U) #define DDRPHY_DX8SL7OSC_OSCWDDL_SHIFT (9U) /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select */ #define DDRPHY_DX8SL7OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL7OSC_OSCWDDL_MASK) #define DDRPHY_DX8SL7OSC_RESERVED_12_11_MASK (0x1800U) #define DDRPHY_DX8SL7OSC_RESERVED_12_11_SHIFT (11U) /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL7OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL7OSC_RESERVED_12_11_MASK) #define DDRPHY_DX8SL7OSC_DLTMODE_MASK (0x2000U) #define DDRPHY_DX8SL7OSC_DLTMODE_SHIFT (13U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_DX8SL7OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL7OSC_DLTMODE_MASK) #define DDRPHY_DX8SL7OSC_DLTST_MASK (0x4000U) #define DDRPHY_DX8SL7OSC_DLTST_SHIFT (14U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_DX8SL7OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_DLTST_SHIFT)) & DDRPHY_DX8SL7OSC_DLTST_MASK) #define DDRPHY_DX8SL7OSC_PHYFRST_MASK (0x8000U) #define DDRPHY_DX8SL7OSC_PHYFRST_SHIFT (15U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_DX8SL7OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL7OSC_PHYFRST_MASK) #define DDRPHY_DX8SL7OSC_PHYHRST_MASK (0x10000U) #define DDRPHY_DX8SL7OSC_PHYHRST_SHIFT (16U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_DX8SL7OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL7OSC_PHYHRST_MASK) #define DDRPHY_DX8SL7OSC_LBDQSS_MASK (0x20000U) #define DDRPHY_DX8SL7OSC_LBDQSS_SHIFT (17U) /*! LBDQSS - Loopback DQS Shift */ #define DDRPHY_DX8SL7OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL7OSC_LBDQSS_MASK) #define DDRPHY_DX8SL7OSC_LBGDQS_MASK (0xC0000U) #define DDRPHY_DX8SL7OSC_LBGDQS_SHIFT (18U) /*! LBGDQS - Loopback DQS Gating */ #define DDRPHY_DX8SL7OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL7OSC_LBGDQS_MASK) #define DDRPHY_DX8SL7OSC_LBGSDQS_MASK (0x100000U) #define DDRPHY_DX8SL7OSC_LBGSDQS_SHIFT (20U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value */ #define DDRPHY_DX8SL7OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL7OSC_LBGSDQS_MASK) #define DDRPHY_DX8SL7OSC_LBMODE_MASK (0x200000U) #define DDRPHY_DX8SL7OSC_LBMODE_SHIFT (21U) /*! LBMODE - Loopback Mode */ #define DDRPHY_DX8SL7OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL7OSC_LBMODE_MASK) #define DDRPHY_DX8SL7OSC_CLKLEVEL_MASK (0xC00000U) #define DDRPHY_DX8SL7OSC_CLKLEVEL_SHIFT (22U) /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled. */ #define DDRPHY_DX8SL7OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL7OSC_CLKLEVEL_MASK) #define DDRPHY_DX8SL7OSC_GATEDXCTLCLK_MASK (0x3000000U) #define DDRPHY_DX8SL7OSC_GATEDXCTLCLK_SHIFT (24U) /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk */ #define DDRPHY_DX8SL7OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL7OSC_GATEDXCTLCLK_MASK) #define DDRPHY_DX8SL7OSC_GATEDXDDRCLK_MASK (0xC000000U) #define DDRPHY_DX8SL7OSC_GATEDXDDRCLK_SHIFT (26U) /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk */ #define DDRPHY_DX8SL7OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL7OSC_GATEDXDDRCLK_MASK) #define DDRPHY_DX8SL7OSC_GATEDXRDCLK_MASK (0x30000000U) #define DDRPHY_DX8SL7OSC_GATEDXRDCLK_SHIFT (28U) /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk */ #define DDRPHY_DX8SL7OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL7OSC_GATEDXRDCLK_MASK) #define DDRPHY_DX8SL7OSC_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8SL7OSC_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL7OSC_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8SL7PLLCR0 - DAXT8 0-1 PLL Control Register 0 */ /*! @{ */ #define DDRPHY_DX8SL7PLLCR0_DTC_MASK (0xFU) #define DDRPHY_DX8SL7PLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_DX8SL7PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_DTC_MASK) #define DDRPHY_DX8SL7PLLCR0_ATC_MASK (0xF0U) #define DDRPHY_DX8SL7PLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_DX8SL7PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_ATC_MASK) #define DDRPHY_DX8SL7PLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_DX8SL7PLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable (ATOEN) */ #define DDRPHY_DX8SL7PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL7PLLCR0_ATOEN_MASK) #define DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_MASK) #define DDRPHY_DX8SL7PLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_DX8SL7PLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_DX8SL7PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL7PLLCR0_GSHIFT_MASK) #define DDRPHY_DX8SL7PLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_DX8SL7PLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_DX8SL7PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_CPIC_MASK) #define DDRPHY_DX8SL7PLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_DX8SL7PLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_DX8SL7PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_CPPC_MASK) #define DDRPHY_DX8SL7PLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_DX8SL7PLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_DX8SL7PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL7PLLCR0_RLOCKM_MASK) #define DDRPHY_DX8SL7PLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_DX8SL7PLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_DX8SL7PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL7PLLCR0_FRQSEL_MASK) #define DDRPHY_DX8SL7PLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_DX8SL7PLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_DX8SL7PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL7PLLCR0_RSTOPM_MASK) #define DDRPHY_DX8SL7PLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_DX8SL7PLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_DX8SL7PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL7PLLCR0_PLLPD_MASK) #define DDRPHY_DX8SL7PLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_DX8SL7PLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_DX8SL7PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL7PLLCR0_PLLRST_MASK) #define DDRPHY_DX8SL7PLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_DX8SL7PLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_DX8SL7PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL7PLLCR0_PLLBYP_MASK) /*! @} */ /*! @name DX8SL7PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL7PLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_DX8SL7PLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_DX8SL7PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL7PLLCR1_LOCKDS_MASK) #define DDRPHY_DX8SL7PLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_DX8SL7PLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_DX8SL7PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL7PLLCR1_LOCKCS_MASK) #define DDRPHY_DX8SL7PLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_DX8SL7PLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_DX8SL7PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL7PLLCR1_LOCKPS_MASK) #define DDRPHY_DX8SL7PLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_DX8SL7PLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_DX8SL7PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL7PLLCR1_BYPVDD_MASK) #define DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_DX8SL7PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_MASK) #define DDRPHY_DX8SL7PLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_DX8SL7PLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_DX8SL7PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL7PLLCR1_BYPVREGCP_MASK) #define DDRPHY_DX8SL7PLLCR1_PLLPROG_MASK (0x3FFFC0U) #define DDRPHY_DX8SL7PLLCR1_PLLPROG_SHIFT (6U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_DX8SL7PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL7PLLCR1_PLLPROG_MASK) #define DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8SL7PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name DX8SL7PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name DX8SL7PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name DX8SL7PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DX8SL7DQSCTL - DATX8 0-1 DQS Control Register */ /*! @{ */ #define DDRPHY_DX8SL7DQSCTL_DQSRES_MASK (0xFU) #define DDRPHY_DX8SL7DQSCTL_DQSRES_SHIFT (0U) /*! DQSRES - DQS Resistor */ #define DDRPHY_DX8SL7DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DQSRES_MASK) #define DDRPHY_DX8SL7DQSCTL_DQSNRES_MASK (0xF0U) #define DDRPHY_DX8SL7DQSCTL_DQSNRES_SHIFT (4U) /*! DQSNRES - DQS_N Resistor */ #define DDRPHY_DX8SL7DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DQSNRES_MASK) #define DDRPHY_DX8SL7DQSCTL_DXSR_MASK (0x300U) #define DDRPHY_DX8SL7DQSCTL_DXSR_SHIFT (8U) /*! DXSR - Data Slew Rate */ #define DDRPHY_DX8SL7DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DXSR_MASK) #define DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_MASK (0x1C00U) #define DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_SHIFT (10U) /*! RESERVED_12_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_MASK) #define DDRPHY_DX8SL7DQSCTL_UDQIOM_MASK (0x2000U) #define DDRPHY_DX8SL7DQSCTL_UDQIOM_SHIFT (13U) /*! UDQIOM - Unused DQ I/O Mode */ #define DDRPHY_DX8SL7DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL7DQSCTL_UDQIOM_MASK) #define DDRPHY_DX8SL7DQSCTL_QSCNTEN_MASK (0x4000U) #define DDRPHY_DX8SL7DQSCTL_QSCNTEN_SHIFT (14U) /*! QSCNTEN - QS Counter Enable */ #define DDRPHY_DX8SL7DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL7DQSCTL_QSCNTEN_MASK) #define DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_MASK (0x18000U) #define DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_SHIFT (15U) /*! RESERVED_16_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_MASK) #define DDRPHY_DX8SL7DQSCTL_LPIOPD_MASK (0x20000U) #define DDRPHY_DX8SL7DQSCTL_LPIOPD_SHIFT (17U) /*! LPIOPD - Low Power I/O Power Down */ #define DDRPHY_DX8SL7DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL7DQSCTL_LPIOPD_MASK) #define DDRPHY_DX8SL7DQSCTL_LPPLLPD_MASK (0x40000U) #define DDRPHY_DX8SL7DQSCTL_LPPLLPD_SHIFT (18U) /*! LPPLLPD - Low Power PLL Power Down */ #define DDRPHY_DX8SL7DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL7DQSCTL_LPPLLPD_MASK) #define DDRPHY_DX8SL7DQSCTL_DQSGX_MASK (0x180000U) #define DDRPHY_DX8SL7DQSCTL_DQSGX_SHIFT (19U) /*! DQSGX - DQS Gate Extension */ #define DDRPHY_DX8SL7DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DQSGX_MASK) #define DDRPHY_DX8SL7DQSCTL_WRRMODE_MASK (0x200000U) #define DDRPHY_DX8SL7DQSCTL_WRRMODE_SHIFT (21U) /*! WRRMODE - Write Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL7DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL7DQSCTL_WRRMODE_MASK) #define DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_MASK) #define DDRPHY_DX8SL7DQSCTL_RRRMODE_MASK (0x1000000U) #define DDRPHY_DX8SL7DQSCTL_RRRMODE_SHIFT (24U) /*! RRRMODE - Read Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL7DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RRRMODE_MASK) #define DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL7TRNCTL - DATX8 0-1 Training Control Register */ /*! @{ */ #define DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL7DDLCTL - DATX8 0-1 DDL Control Register */ /*! @{ */ #define DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_MASK (0x3U) #define DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_SHIFT (0U) /*! DDLBYPMODE - Controls DDL Bypass Mode */ #define DDRPHY_DX8SL7DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_MASK) #define DDRPHY_DX8SL7DDLCTL_DXDDLBYP_MASK (0x3FFFCU) #define DDRPHY_DX8SL7DDLCTL_DXDDLBYP_SHIFT (2U) /*! DXDDLBYP - DATX8 DDL Bypass */ #define DDRPHY_DX8SL7DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DXDDLBYP_MASK) #define DDRPHY_DX8SL7DDLCTL_DXDDLLD_MASK (0x7C0000U) #define DDRPHY_DX8SL7DDLCTL_DXDDLLD_SHIFT (18U) /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load */ #define DDRPHY_DX8SL7DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DXDDLLD_MASK) #define DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_MASK (0x1800000U) #define DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_SHIFT (23U) /*! RESERVED_24_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_MASK) #define DDRPHY_DX8SL7DDLCTL_DXDDLLDT_MASK (0x2000000U) #define DDRPHY_DX8SL7DDLCTL_DXDDLLDT_SHIFT (25U) /*! DXDDLLDT - DX DDL Load Type */ #define DDRPHY_DX8SL7DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DXDDLLDT_MASK) #define DDRPHY_DX8SL7DDLCTL_DLYLDTM_MASK (0x4000000U) #define DDRPHY_DX8SL7DDLCTL_DLYLDTM_SHIFT (26U) /*! DLYLDTM - Delay Load Timing */ #define DDRPHY_DX8SL7DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DLYLDTM_MASK) #define DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8SL7DXCTL1 - DATX8 0-1 DX Control Register 1 */ /*! @{ */ #define DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_MASK (0xFFFFU) #define DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_SHIFT (0U) /*! RESERVED_15_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_MASK) #define DDRPHY_DX8SL7DXCTL1_DXTMODE_MASK (0x10000U) #define DDRPHY_DX8SL7DXCTL1_DXTMODE_SHIFT (16U) /*! DXTMODE - DATX8 Test Mode */ #define DDRPHY_DX8SL7DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXTMODE_MASK) #define DDRPHY_DX8SL7DXCTL1_DXGDBYP_MASK (0x20000U) #define DDRPHY_DX8SL7DXCTL1_DXGDBYP_SHIFT (17U) /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode */ #define DDRPHY_DX8SL7DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXGDBYP_MASK) #define DDRPHY_DX8SL7DXCTL1_DXQSDBYP_MASK (0x40000U) #define DDRPHY_DX8SL7DXCTL1_DXQSDBYP_SHIFT (18U) /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode */ #define DDRPHY_DX8SL7DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXQSDBYP_MASK) #define DDRPHY_DX8SL7DXCTL1_DXGSMD_MASK (0x80000U) #define DDRPHY_DX8SL7DXCTL1_DXGSMD_SHIFT (19U) /*! DXGSMD - Read DQS Gating Status Mode */ #define DDRPHY_DX8SL7DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXGSMD_MASK) #define DDRPHY_DX8SL7DXCTL1_DXDTOSEL_MASK (0x300000U) #define DDRPHY_DX8SL7DXCTL1_DXDTOSEL_SHIFT (20U) /*! DXDTOSEL - DATX8 Digital Test Output Select */ #define DDRPHY_DX8SL7DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXDTOSEL_MASK) #define DDRPHY_DX8SL7DXCTL1_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8SL7DXCTL1_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL7DXCTL1_RESERVED_22_MASK) #define DDRPHY_DX8SL7DXCTL1_DXRCLKMD_MASK (0x800000U) #define DDRPHY_DX8SL7DXCTL1_DXRCLKMD_SHIFT (23U) /*! DXRCLKMD - DATX8 Read Clock Mode */ #define DDRPHY_DX8SL7DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXRCLKMD_MASK) #define DDRPHY_DX8SL7DXCTL1_DXCALCLK_MASK (0x1000000U) #define DDRPHY_DX8SL7DXCTL1_DXCALCLK_SHIFT (24U) /*! DXCALCLK - DATX Calibration Clock Select */ #define DDRPHY_DX8SL7DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXCALCLK_MASK) #define DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL7DXCTL2 - DATX8 0-1 DX Control Register 2 */ /*! @{ */ #define DDRPHY_DX8SL7DXCTL2_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8SL7DXCTL2_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_0_MASK) #define DDRPHY_DX8SL7DXCTL2_DQSGLB_MASK (0x6U) #define DDRPHY_DX8SL7DXCTL2_DQSGLB_SHIFT (1U) /*! DQSGLB - Read DQS Gate I/O Loopback */ #define DDRPHY_DX8SL7DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL7DXCTL2_DQSGLB_MASK) #define DDRPHY_DX8SL7DXCTL2_DISRST_MASK (0x8U) #define DDRPHY_DX8SL7DXCTL2_DISRST_SHIFT (3U) /*! DISRST - Disables the Read FIFO Reset */ #define DDRPHY_DX8SL7DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL7DXCTL2_DISRST_MASK) #define DDRPHY_DX8SL7DXCTL2_RDMODE_MASK (0x30U) #define DDRPHY_DX8SL7DXCTL2_RDMODE_SHIFT (4U) /*! RDMODE - DATX8 Receive FIFO Read Mode */ #define DDRPHY_DX8SL7DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RDMODE_MASK) #define DDRPHY_DX8SL7DXCTL2_PRFBYP_MASK (0x40U) #define DDRPHY_DX8SL7DXCTL2_PRFBYP_SHIFT (6U) /*! PRFBYP - PUB Read FIFO Bypass */ #define DDRPHY_DX8SL7DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL7DXCTL2_PRFBYP_MASK) #define DDRPHY_DX8SL7DXCTL2_WDBI_MASK (0x80U) #define DDRPHY_DX8SL7DXCTL2_WDBI_SHIFT (7U) /*! WDBI - Write Data Bus Inversion Enable */ #define DDRPHY_DX8SL7DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL7DXCTL2_WDBI_MASK) #define DDRPHY_DX8SL7DXCTL2_RDBI_MASK (0x100U) #define DDRPHY_DX8SL7DXCTL2_RDBI_SHIFT (8U) /*! RDBI - Read Data Bus Inversion Enable */ #define DDRPHY_DX8SL7DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RDBI_MASK) #define DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U) #define DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_SHIFT (9U) /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold */ #define DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_MASK) #define DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_MASK (0x6000U) #define DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_SHIFT (13U) /*! RESERVED_14_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_MASK) #define DDRPHY_DX8SL7DXCTL2_IOLB_MASK (0x8000U) #define DDRPHY_DX8SL7DXCTL2_IOLB_SHIFT (15U) /*! IOLB - I/O Loopback Select */ #define DDRPHY_DX8SL7DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL7DXCTL2_IOLB_MASK) #define DDRPHY_DX8SL7DXCTL2_IOAG_MASK (0x10000U) #define DDRPHY_DX8SL7DXCTL2_IOAG_SHIFT (16U) /*! IOAG - I/O Assisted Gate Select */ #define DDRPHY_DX8SL7DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL7DXCTL2_IOAG_MASK) #define DDRPHY_DX8SL7DXCTL2_RESERVED_17_MASK (0x20000U) #define DDRPHY_DX8SL7DXCTL2_RESERVED_17_SHIFT (17U) /*! RESERVED_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_17_MASK) #define DDRPHY_DX8SL7DXCTL2_PREOEX_MASK (0xC0000U) #define DDRPHY_DX8SL7DXCTL2_PREOEX_SHIFT (18U) /*! PREOEX - OE Extension during Pre-amble */ #define DDRPHY_DX8SL7DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL7DXCTL2_PREOEX_MASK) #define DDRPHY_DX8SL7DXCTL2_POSOEX_MASK (0x700000U) #define DDRPHY_DX8SL7DXCTL2_POSOEX_SHIFT (20U) /*! POSOEX - OX Extension during Post-amble */ #define DDRPHY_DX8SL7DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL7DXCTL2_POSOEX_MASK) #define DDRPHY_DX8SL7DXCTL2_CRDEN_MASK (0x800000U) #define DDRPHY_DX8SL7DXCTL2_CRDEN_SHIFT (23U) /*! CRDEN - Configurable Read Data Enable */ #define DDRPHY_DX8SL7DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL7DXCTL2_CRDEN_MASK) #define DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SL7IOCR - DATX8 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX8SL7IOCR_DXRXM_MASK (0x7FFU) #define DDRPHY_DX8SL7IOCR_DXRXM_SHIFT (0U) /*! DXRXM - DX IO Receiver Mode */ #define DDRPHY_DX8SL7IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXRXM_MASK) #define DDRPHY_DX8SL7IOCR_DXTXM_MASK (0x3FF800U) #define DDRPHY_DX8SL7IOCR_DXTXM_SHIFT (11U) /*! DXTXM - DX IO Transmitter Mode */ #define DDRPHY_DX8SL7IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXTXM_MASK) #define DDRPHY_DX8SL7IOCR_DXIOM_MASK (0x1C00000U) #define DDRPHY_DX8SL7IOCR_DXIOM_SHIFT (22U) /*! DXIOM - DX IO Mode */ #define DDRPHY_DX8SL7IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXIOM_MASK) #define DDRPHY_DX8SL7IOCR_DXVREFIOM_MASK (0xE000000U) #define DDRPHY_DX8SL7IOCR_DXVREFIOM_SHIFT (25U) /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring */ #define DDRPHY_DX8SL7IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXVREFIOM_MASK) #define DDRPHY_DX8SL7IOCR_DXDACRANGE_MASK (0x70000000U) #define DDRPHY_DX8SL7IOCR_DXDACRANGE_SHIFT (28U) /*! DXDACRANGE - PVREF_DAC REFSEL range select */ #define DDRPHY_DX8SL7IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL7IOCR_DXDACRANGE_MASK) #define DDRPHY_DX8SL7IOCR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8SL7IOCR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL7IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL7IOCR_RESERVED_31_MASK) /*! @} */ /*! @name DX4SL7IOCR - DATX4 Slice 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX4SL7IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX4SL7IOCR_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4SL7IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL7IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL7IOCR_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL8OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */ /*! @{ */ #define DDRPHY_DX8SL8OSC_OSCEN_MASK (0x1U) #define DDRPHY_DX8SL8OSC_OSCEN_SHIFT (0U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_DX8SL8OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL8OSC_OSCEN_MASK) #define DDRPHY_DX8SL8OSC_OSCDIV_MASK (0x1EU) #define DDRPHY_DX8SL8OSC_OSCDIV_SHIFT (1U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_DX8SL8OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL8OSC_OSCDIV_MASK) #define DDRPHY_DX8SL8OSC_OSCWDL_MASK (0x60U) #define DDRPHY_DX8SL8OSC_OSCWDL_SHIFT (5U) /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select */ #define DDRPHY_DX8SL8OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL8OSC_OSCWDL_MASK) #define DDRPHY_DX8SL8OSC_RESERVED_8_7_MASK (0x180U) #define DDRPHY_DX8SL8OSC_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL8OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL8OSC_RESERVED_8_7_MASK) #define DDRPHY_DX8SL8OSC_OSCWDDL_MASK (0x600U) #define DDRPHY_DX8SL8OSC_OSCWDDL_SHIFT (9U) /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select */ #define DDRPHY_DX8SL8OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL8OSC_OSCWDDL_MASK) #define DDRPHY_DX8SL8OSC_RESERVED_12_11_MASK (0x1800U) #define DDRPHY_DX8SL8OSC_RESERVED_12_11_SHIFT (11U) /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SL8OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL8OSC_RESERVED_12_11_MASK) #define DDRPHY_DX8SL8OSC_DLTMODE_MASK (0x2000U) #define DDRPHY_DX8SL8OSC_DLTMODE_SHIFT (13U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_DX8SL8OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL8OSC_DLTMODE_MASK) #define DDRPHY_DX8SL8OSC_DLTST_MASK (0x4000U) #define DDRPHY_DX8SL8OSC_DLTST_SHIFT (14U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_DX8SL8OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_DLTST_SHIFT)) & DDRPHY_DX8SL8OSC_DLTST_MASK) #define DDRPHY_DX8SL8OSC_PHYFRST_MASK (0x8000U) #define DDRPHY_DX8SL8OSC_PHYFRST_SHIFT (15U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_DX8SL8OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL8OSC_PHYFRST_MASK) #define DDRPHY_DX8SL8OSC_PHYHRST_MASK (0x10000U) #define DDRPHY_DX8SL8OSC_PHYHRST_SHIFT (16U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_DX8SL8OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL8OSC_PHYHRST_MASK) #define DDRPHY_DX8SL8OSC_LBDQSS_MASK (0x20000U) #define DDRPHY_DX8SL8OSC_LBDQSS_SHIFT (17U) /*! LBDQSS - Loopback DQS Shift */ #define DDRPHY_DX8SL8OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL8OSC_LBDQSS_MASK) #define DDRPHY_DX8SL8OSC_LBGDQS_MASK (0xC0000U) #define DDRPHY_DX8SL8OSC_LBGDQS_SHIFT (18U) /*! LBGDQS - Loopback DQS Gating */ #define DDRPHY_DX8SL8OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL8OSC_LBGDQS_MASK) #define DDRPHY_DX8SL8OSC_LBGSDQS_MASK (0x100000U) #define DDRPHY_DX8SL8OSC_LBGSDQS_SHIFT (20U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value */ #define DDRPHY_DX8SL8OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL8OSC_LBGSDQS_MASK) #define DDRPHY_DX8SL8OSC_LBMODE_MASK (0x200000U) #define DDRPHY_DX8SL8OSC_LBMODE_SHIFT (21U) /*! LBMODE - Loopback Mode */ #define DDRPHY_DX8SL8OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL8OSC_LBMODE_MASK) #define DDRPHY_DX8SL8OSC_CLKLEVEL_MASK (0xC00000U) #define DDRPHY_DX8SL8OSC_CLKLEVEL_SHIFT (22U) /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled. */ #define DDRPHY_DX8SL8OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL8OSC_CLKLEVEL_MASK) #define DDRPHY_DX8SL8OSC_GATEDXCTLCLK_MASK (0x3000000U) #define DDRPHY_DX8SL8OSC_GATEDXCTLCLK_SHIFT (24U) /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk */ #define DDRPHY_DX8SL8OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL8OSC_GATEDXCTLCLK_MASK) #define DDRPHY_DX8SL8OSC_GATEDXDDRCLK_MASK (0xC000000U) #define DDRPHY_DX8SL8OSC_GATEDXDDRCLK_SHIFT (26U) /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk */ #define DDRPHY_DX8SL8OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL8OSC_GATEDXDDRCLK_MASK) #define DDRPHY_DX8SL8OSC_GATEDXRDCLK_MASK (0x30000000U) #define DDRPHY_DX8SL8OSC_GATEDXRDCLK_SHIFT (28U) /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk */ #define DDRPHY_DX8SL8OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL8OSC_GATEDXRDCLK_MASK) #define DDRPHY_DX8SL8OSC_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8SL8OSC_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL8OSC_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8SL8PLLCR0 - DAXT8 0-1 PLL Control Register 0 */ /*! @{ */ #define DDRPHY_DX8SL8PLLCR0_DTC_MASK (0xFU) #define DDRPHY_DX8SL8PLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_DX8SL8PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_DTC_MASK) #define DDRPHY_DX8SL8PLLCR0_ATC_MASK (0xF0U) #define DDRPHY_DX8SL8PLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_DX8SL8PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_ATC_MASK) #define DDRPHY_DX8SL8PLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_DX8SL8PLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable (ATOEN) */ #define DDRPHY_DX8SL8PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL8PLLCR0_ATOEN_MASK) #define DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_MASK) #define DDRPHY_DX8SL8PLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_DX8SL8PLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_DX8SL8PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL8PLLCR0_GSHIFT_MASK) #define DDRPHY_DX8SL8PLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_DX8SL8PLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_DX8SL8PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_CPIC_MASK) #define DDRPHY_DX8SL8PLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_DX8SL8PLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_DX8SL8PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_CPPC_MASK) #define DDRPHY_DX8SL8PLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_DX8SL8PLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_DX8SL8PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL8PLLCR0_RLOCKM_MASK) #define DDRPHY_DX8SL8PLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_DX8SL8PLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_DX8SL8PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL8PLLCR0_FRQSEL_MASK) #define DDRPHY_DX8SL8PLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_DX8SL8PLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_DX8SL8PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL8PLLCR0_RSTOPM_MASK) #define DDRPHY_DX8SL8PLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_DX8SL8PLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_DX8SL8PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL8PLLCR0_PLLPD_MASK) #define DDRPHY_DX8SL8PLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_DX8SL8PLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_DX8SL8PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL8PLLCR0_PLLRST_MASK) #define DDRPHY_DX8SL8PLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_DX8SL8PLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_DX8SL8PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL8PLLCR0_PLLBYP_MASK) /*! @} */ /*! @name DX8SL8PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL8PLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_DX8SL8PLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_DX8SL8PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL8PLLCR1_LOCKDS_MASK) #define DDRPHY_DX8SL8PLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_DX8SL8PLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_DX8SL8PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL8PLLCR1_LOCKCS_MASK) #define DDRPHY_DX8SL8PLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_DX8SL8PLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_DX8SL8PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL8PLLCR1_LOCKPS_MASK) #define DDRPHY_DX8SL8PLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_DX8SL8PLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_DX8SL8PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL8PLLCR1_BYPVDD_MASK) #define DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_DX8SL8PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_MASK) #define DDRPHY_DX8SL8PLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_DX8SL8PLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_DX8SL8PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL8PLLCR1_BYPVREGCP_MASK) #define DDRPHY_DX8SL8PLLCR1_PLLPROG_MASK (0x3FFFC0U) #define DDRPHY_DX8SL8PLLCR1_PLLPROG_SHIFT (6U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_DX8SL8PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL8PLLCR1_PLLPROG_MASK) #define DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8SL8PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name DX8SL8PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name DX8SL8PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name DX8SL8PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DX8SL8DQSCTL - DATX8 0-1 DQS Control Register */ /*! @{ */ #define DDRPHY_DX8SL8DQSCTL_DQSRES_MASK (0xFU) #define DDRPHY_DX8SL8DQSCTL_DQSRES_SHIFT (0U) /*! DQSRES - DQS Resistor */ #define DDRPHY_DX8SL8DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DQSRES_MASK) #define DDRPHY_DX8SL8DQSCTL_DQSNRES_MASK (0xF0U) #define DDRPHY_DX8SL8DQSCTL_DQSNRES_SHIFT (4U) /*! DQSNRES - DQS_N Resistor */ #define DDRPHY_DX8SL8DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DQSNRES_MASK) #define DDRPHY_DX8SL8DQSCTL_DXSR_MASK (0x300U) #define DDRPHY_DX8SL8DQSCTL_DXSR_SHIFT (8U) /*! DXSR - Data Slew Rate */ #define DDRPHY_DX8SL8DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DXSR_MASK) #define DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_MASK (0x1C00U) #define DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_SHIFT (10U) /*! RESERVED_12_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_MASK) #define DDRPHY_DX8SL8DQSCTL_UDQIOM_MASK (0x2000U) #define DDRPHY_DX8SL8DQSCTL_UDQIOM_SHIFT (13U) /*! UDQIOM - Unused DQ I/O Mode */ #define DDRPHY_DX8SL8DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL8DQSCTL_UDQIOM_MASK) #define DDRPHY_DX8SL8DQSCTL_QSCNTEN_MASK (0x4000U) #define DDRPHY_DX8SL8DQSCTL_QSCNTEN_SHIFT (14U) /*! QSCNTEN - QS Counter Enable */ #define DDRPHY_DX8SL8DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL8DQSCTL_QSCNTEN_MASK) #define DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_MASK (0x18000U) #define DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_SHIFT (15U) /*! RESERVED_16_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_MASK) #define DDRPHY_DX8SL8DQSCTL_LPIOPD_MASK (0x20000U) #define DDRPHY_DX8SL8DQSCTL_LPIOPD_SHIFT (17U) /*! LPIOPD - Low Power I/O Power Down */ #define DDRPHY_DX8SL8DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL8DQSCTL_LPIOPD_MASK) #define DDRPHY_DX8SL8DQSCTL_LPPLLPD_MASK (0x40000U) #define DDRPHY_DX8SL8DQSCTL_LPPLLPD_SHIFT (18U) /*! LPPLLPD - Low Power PLL Power Down */ #define DDRPHY_DX8SL8DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL8DQSCTL_LPPLLPD_MASK) #define DDRPHY_DX8SL8DQSCTL_DQSGX_MASK (0x180000U) #define DDRPHY_DX8SL8DQSCTL_DQSGX_SHIFT (19U) /*! DQSGX - DQS Gate Extension */ #define DDRPHY_DX8SL8DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DQSGX_MASK) #define DDRPHY_DX8SL8DQSCTL_WRRMODE_MASK (0x200000U) #define DDRPHY_DX8SL8DQSCTL_WRRMODE_SHIFT (21U) /*! WRRMODE - Write Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL8DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL8DQSCTL_WRRMODE_MASK) #define DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_MASK) #define DDRPHY_DX8SL8DQSCTL_RRRMODE_MASK (0x1000000U) #define DDRPHY_DX8SL8DQSCTL_RRRMODE_SHIFT (24U) /*! RRRMODE - Read Path Rise-to-Rise Mode */ #define DDRPHY_DX8SL8DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RRRMODE_MASK) #define DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL8TRNCTL - DATX8 0-1 Training Control Register */ /*! @{ */ #define DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SL8DDLCTL - DATX8 0-1 DDL Control Register */ /*! @{ */ #define DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_MASK (0x3U) #define DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_SHIFT (0U) /*! DDLBYPMODE - Controls DDL Bypass Mode */ #define DDRPHY_DX8SL8DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_MASK) #define DDRPHY_DX8SL8DDLCTL_DXDDLBYP_MASK (0x3FFFCU) #define DDRPHY_DX8SL8DDLCTL_DXDDLBYP_SHIFT (2U) /*! DXDDLBYP - DATX8 DDL Bypass */ #define DDRPHY_DX8SL8DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DXDDLBYP_MASK) #define DDRPHY_DX8SL8DDLCTL_DXDDLLD_MASK (0x7C0000U) #define DDRPHY_DX8SL8DDLCTL_DXDDLLD_SHIFT (18U) /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load */ #define DDRPHY_DX8SL8DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DXDDLLD_MASK) #define DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_MASK (0x1800000U) #define DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_SHIFT (23U) /*! RESERVED_24_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_MASK) #define DDRPHY_DX8SL8DDLCTL_DXDDLLDT_MASK (0x2000000U) #define DDRPHY_DX8SL8DDLCTL_DXDDLLDT_SHIFT (25U) /*! DXDDLLDT - DX DDL Load Type */ #define DDRPHY_DX8SL8DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DXDDLLDT_MASK) #define DDRPHY_DX8SL8DDLCTL_DLYLDTM_MASK (0x4000000U) #define DDRPHY_DX8SL8DDLCTL_DLYLDTM_SHIFT (26U) /*! DLYLDTM - Delay Load Timing */ #define DDRPHY_DX8SL8DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DLYLDTM_MASK) #define DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8SL8DXCTL1 - DATX8 0-1 DX Control Register 1 */ /*! @{ */ #define DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_MASK (0xFFFFU) #define DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_SHIFT (0U) /*! RESERVED_15_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_MASK) #define DDRPHY_DX8SL8DXCTL1_DXTMODE_MASK (0x10000U) #define DDRPHY_DX8SL8DXCTL1_DXTMODE_SHIFT (16U) /*! DXTMODE - DATX8 Test Mode */ #define DDRPHY_DX8SL8DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXTMODE_MASK) #define DDRPHY_DX8SL8DXCTL1_DXGDBYP_MASK (0x20000U) #define DDRPHY_DX8SL8DXCTL1_DXGDBYP_SHIFT (17U) /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode */ #define DDRPHY_DX8SL8DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXGDBYP_MASK) #define DDRPHY_DX8SL8DXCTL1_DXQSDBYP_MASK (0x40000U) #define DDRPHY_DX8SL8DXCTL1_DXQSDBYP_SHIFT (18U) /*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode */ #define DDRPHY_DX8SL8DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXQSDBYP_MASK) #define DDRPHY_DX8SL8DXCTL1_DXGSMD_MASK (0x80000U) #define DDRPHY_DX8SL8DXCTL1_DXGSMD_SHIFT (19U) /*! DXGSMD - Read DQS Gating Status Mode */ #define DDRPHY_DX8SL8DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXGSMD_MASK) #define DDRPHY_DX8SL8DXCTL1_DXDTOSEL_MASK (0x300000U) #define DDRPHY_DX8SL8DXCTL1_DXDTOSEL_SHIFT (20U) /*! DXDTOSEL - DATX8 Digital Test Output Select */ #define DDRPHY_DX8SL8DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXDTOSEL_MASK) #define DDRPHY_DX8SL8DXCTL1_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8SL8DXCTL1_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL8DXCTL1_RESERVED_22_MASK) #define DDRPHY_DX8SL8DXCTL1_DXRCLKMD_MASK (0x800000U) #define DDRPHY_DX8SL8DXCTL1_DXRCLKMD_SHIFT (23U) /*! DXRCLKMD - DATX8 Read Clock Mode */ #define DDRPHY_DX8SL8DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXRCLKMD_MASK) #define DDRPHY_DX8SL8DXCTL1_DXCALCLK_MASK (0x1000000U) #define DDRPHY_DX8SL8DXCTL1_DXCALCLK_SHIFT (24U) /*! DXCALCLK - DATX Calibration Clock Select */ #define DDRPHY_DX8SL8DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXCALCLK_MASK) #define DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SL8DXCTL2 - DATX8 0-1 DX Control Register 2 */ /*! @{ */ #define DDRPHY_DX8SL8DXCTL2_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8SL8DXCTL2_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_0_MASK) #define DDRPHY_DX8SL8DXCTL2_DQSGLB_MASK (0x6U) #define DDRPHY_DX8SL8DXCTL2_DQSGLB_SHIFT (1U) /*! DQSGLB - Read DQS Gate I/O Loopback */ #define DDRPHY_DX8SL8DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL8DXCTL2_DQSGLB_MASK) #define DDRPHY_DX8SL8DXCTL2_DISRST_MASK (0x8U) #define DDRPHY_DX8SL8DXCTL2_DISRST_SHIFT (3U) /*! DISRST - Disables the Read FIFO Reset */ #define DDRPHY_DX8SL8DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL8DXCTL2_DISRST_MASK) #define DDRPHY_DX8SL8DXCTL2_RDMODE_MASK (0x30U) #define DDRPHY_DX8SL8DXCTL2_RDMODE_SHIFT (4U) /*! RDMODE - DATX8 Receive FIFO Read Mode */ #define DDRPHY_DX8SL8DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RDMODE_MASK) #define DDRPHY_DX8SL8DXCTL2_PRFBYP_MASK (0x40U) #define DDRPHY_DX8SL8DXCTL2_PRFBYP_SHIFT (6U) /*! PRFBYP - PUB Read FIFO Bypass */ #define DDRPHY_DX8SL8DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL8DXCTL2_PRFBYP_MASK) #define DDRPHY_DX8SL8DXCTL2_WDBI_MASK (0x80U) #define DDRPHY_DX8SL8DXCTL2_WDBI_SHIFT (7U) /*! WDBI - Write Data Bus Inversion Enable */ #define DDRPHY_DX8SL8DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL8DXCTL2_WDBI_MASK) #define DDRPHY_DX8SL8DXCTL2_RDBI_MASK (0x100U) #define DDRPHY_DX8SL8DXCTL2_RDBI_SHIFT (8U) /*! RDBI - Read Data Bus Inversion Enable */ #define DDRPHY_DX8SL8DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RDBI_MASK) #define DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U) #define DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_SHIFT (9U) /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold */ #define DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_MASK) #define DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_MASK (0x6000U) #define DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_SHIFT (13U) /*! RESERVED_14_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_MASK) #define DDRPHY_DX8SL8DXCTL2_IOLB_MASK (0x8000U) #define DDRPHY_DX8SL8DXCTL2_IOLB_SHIFT (15U) /*! IOLB - I/O Loopback Select */ #define DDRPHY_DX8SL8DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL8DXCTL2_IOLB_MASK) #define DDRPHY_DX8SL8DXCTL2_IOAG_MASK (0x10000U) #define DDRPHY_DX8SL8DXCTL2_IOAG_SHIFT (16U) /*! IOAG - I/O Assisted Gate Select */ #define DDRPHY_DX8SL8DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL8DXCTL2_IOAG_MASK) #define DDRPHY_DX8SL8DXCTL2_RESERVED_17_MASK (0x20000U) #define DDRPHY_DX8SL8DXCTL2_RESERVED_17_SHIFT (17U) /*! RESERVED_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_17_MASK) #define DDRPHY_DX8SL8DXCTL2_PREOEX_MASK (0xC0000U) #define DDRPHY_DX8SL8DXCTL2_PREOEX_SHIFT (18U) /*! PREOEX - OE Extension during Pre-amble */ #define DDRPHY_DX8SL8DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL8DXCTL2_PREOEX_MASK) #define DDRPHY_DX8SL8DXCTL2_POSOEX_MASK (0x700000U) #define DDRPHY_DX8SL8DXCTL2_POSOEX_SHIFT (20U) /*! POSOEX - OX Extension during Post-amble */ #define DDRPHY_DX8SL8DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL8DXCTL2_POSOEX_MASK) #define DDRPHY_DX8SL8DXCTL2_CRDEN_MASK (0x800000U) #define DDRPHY_DX8SL8DXCTL2_CRDEN_SHIFT (23U) /*! CRDEN - Configurable Read Data Enable */ #define DDRPHY_DX8SL8DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL8DXCTL2_CRDEN_MASK) #define DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SL8IOCR - DATX8 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX8SL8IOCR_DXRXM_MASK (0x7FFU) #define DDRPHY_DX8SL8IOCR_DXRXM_SHIFT (0U) /*! DXRXM - DX IO Receiver Mode */ #define DDRPHY_DX8SL8IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXRXM_MASK) #define DDRPHY_DX8SL8IOCR_DXTXM_MASK (0x3FF800U) #define DDRPHY_DX8SL8IOCR_DXTXM_SHIFT (11U) /*! DXTXM - DX IO Transmitter Mode */ #define DDRPHY_DX8SL8IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXTXM_MASK) #define DDRPHY_DX8SL8IOCR_DXIOM_MASK (0x1C00000U) #define DDRPHY_DX8SL8IOCR_DXIOM_SHIFT (22U) /*! DXIOM - DX IO Mode */ #define DDRPHY_DX8SL8IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXIOM_MASK) #define DDRPHY_DX8SL8IOCR_DXVREFIOM_MASK (0xE000000U) #define DDRPHY_DX8SL8IOCR_DXVREFIOM_SHIFT (25U) /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring */ #define DDRPHY_DX8SL8IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXVREFIOM_MASK) #define DDRPHY_DX8SL8IOCR_DXDACRANGE_MASK (0x70000000U) #define DDRPHY_DX8SL8IOCR_DXDACRANGE_SHIFT (28U) /*! DXDACRANGE - PVREF_DAC REFSEL range select */ #define DDRPHY_DX8SL8IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL8IOCR_DXDACRANGE_MASK) #define DDRPHY_DX8SL8IOCR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8SL8IOCR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SL8IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL8IOCR_RESERVED_31_MASK) /*! @} */ /*! @name DX4SL8IOCR - DATX4 Slice 0-1 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX4SL8IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX4SL8IOCR_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4SL8IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL8IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL8IOCR_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SLBOSC - DATX8 0-8 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */ /*! @{ */ #define DDRPHY_DX8SLBOSC_OSCEN_MASK (0x1U) #define DDRPHY_DX8SLBOSC_OSCEN_SHIFT (0U) /*! OSCEN - Oscillator Enable */ #define DDRPHY_DX8SLBOSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCEN_SHIFT)) & DDRPHY_DX8SLBOSC_OSCEN_MASK) #define DDRPHY_DX8SLBOSC_OSCDIV_MASK (0x1EU) #define DDRPHY_DX8SLBOSC_OSCDIV_SHIFT (1U) /*! OSCDIV - Oscillator Mode Division */ #define DDRPHY_DX8SLBOSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCDIV_SHIFT)) & DDRPHY_DX8SLBOSC_OSCDIV_MASK) #define DDRPHY_DX8SLBOSC_OSCWDL_MASK (0x60U) #define DDRPHY_DX8SLBOSC_OSCWDL_SHIFT (5U) /*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select */ #define DDRPHY_DX8SLBOSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCWDL_SHIFT)) & DDRPHY_DX8SLBOSC_OSCWDL_MASK) #define DDRPHY_DX8SLBOSC_RESERVED_8_7_MASK (0x180U) #define DDRPHY_DX8SLBOSC_RESERVED_8_7_SHIFT (7U) /*! RESERVED_8_7 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SLBOSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SLBOSC_RESERVED_8_7_MASK) #define DDRPHY_DX8SLBOSC_OSCWDDL_MASK (0x600U) #define DDRPHY_DX8SLBOSC_OSCWDDL_SHIFT (9U) /*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select */ #define DDRPHY_DX8SLBOSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SLBOSC_OSCWDDL_MASK) #define DDRPHY_DX8SLBOSC_RESERVED_12_11_MASK (0x1800U) #define DDRPHY_DX8SLBOSC_RESERVED_12_11_SHIFT (11U) /*! RESERVED_12_11 - Reserved. Caution, do not write to this register field. */ #define DDRPHY_DX8SLBOSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SLBOSC_RESERVED_12_11_MASK) #define DDRPHY_DX8SLBOSC_DLTMODE_MASK (0x2000U) #define DDRPHY_DX8SLBOSC_DLTMODE_SHIFT (13U) /*! DLTMODE - Delay Line Test Mode */ #define DDRPHY_DX8SLBOSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_DLTMODE_SHIFT)) & DDRPHY_DX8SLBOSC_DLTMODE_MASK) #define DDRPHY_DX8SLBOSC_DLTST_MASK (0x4000U) #define DDRPHY_DX8SLBOSC_DLTST_SHIFT (14U) /*! DLTST - Delay Line Test Start */ #define DDRPHY_DX8SLBOSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_DLTST_SHIFT)) & DDRPHY_DX8SLBOSC_DLTST_MASK) #define DDRPHY_DX8SLBOSC_PHYFRST_MASK (0x8000U) #define DDRPHY_DX8SLBOSC_PHYFRST_SHIFT (15U) /*! PHYFRST - PHY FIFO Reset */ #define DDRPHY_DX8SLBOSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_PHYFRST_SHIFT)) & DDRPHY_DX8SLBOSC_PHYFRST_MASK) #define DDRPHY_DX8SLBOSC_PHYHRST_MASK (0x10000U) #define DDRPHY_DX8SLBOSC_PHYHRST_SHIFT (16U) /*! PHYHRST - PHY High-Speed Reset */ #define DDRPHY_DX8SLBOSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_PHYHRST_SHIFT)) & DDRPHY_DX8SLBOSC_PHYHRST_MASK) #define DDRPHY_DX8SLBOSC_LBDQSS_MASK (0x20000U) #define DDRPHY_DX8SLBOSC_LBDQSS_SHIFT (17U) /*! LBDQSS - Loopback DQS Shift */ #define DDRPHY_DX8SLBOSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBDQSS_SHIFT)) & DDRPHY_DX8SLBOSC_LBDQSS_MASK) #define DDRPHY_DX8SLBOSC_LBGDQS_MASK (0xC0000U) #define DDRPHY_DX8SLBOSC_LBGDQS_SHIFT (18U) /*! LBGDQS - Loopback DQS Gating */ #define DDRPHY_DX8SLBOSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBGDQS_SHIFT)) & DDRPHY_DX8SLBOSC_LBGDQS_MASK) #define DDRPHY_DX8SLBOSC_LBGSDQS_MASK (0x100000U) #define DDRPHY_DX8SLBOSC_LBGSDQS_SHIFT (20U) /*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value */ #define DDRPHY_DX8SLBOSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SLBOSC_LBGSDQS_MASK) #define DDRPHY_DX8SLBOSC_LBMODE_MASK (0x200000U) #define DDRPHY_DX8SLBOSC_LBMODE_SHIFT (21U) /*! LBMODE - Loopback Mode */ #define DDRPHY_DX8SLBOSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBMODE_SHIFT)) & DDRPHY_DX8SLBOSC_LBMODE_MASK) #define DDRPHY_DX8SLBOSC_CLKLEVEL_MASK (0xC00000U) #define DDRPHY_DX8SLBOSC_CLKLEVEL_SHIFT (22U) /*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled. */ #define DDRPHY_DX8SLBOSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SLBOSC_CLKLEVEL_MASK) #define DDRPHY_DX8SLBOSC_GATEDXCTLCLK_MASK (0x3000000U) #define DDRPHY_DX8SLBOSC_GATEDXCTLCLK_SHIFT (24U) /*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk */ #define DDRPHY_DX8SLBOSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SLBOSC_GATEDXCTLCLK_MASK) #define DDRPHY_DX8SLBOSC_GATEDXDDRCLK_MASK (0xC000000U) #define DDRPHY_DX8SLBOSC_GATEDXDDRCLK_SHIFT (26U) /*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk */ #define DDRPHY_DX8SLBOSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SLBOSC_GATEDXDDRCLK_MASK) #define DDRPHY_DX8SLBOSC_GATEDXRDCLK_MASK (0x30000000U) #define DDRPHY_DX8SLBOSC_GATEDXRDCLK_SHIFT (28U) /*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk */ #define DDRPHY_DX8SLBOSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SLBOSC_GATEDXRDCLK_MASK) #define DDRPHY_DX8SLBOSC_RESERVED_31_30_MASK (0xC0000000U) #define DDRPHY_DX8SLBOSC_RESERVED_31_30_SHIFT (30U) /*! RESERVED_31_30 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBOSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SLBOSC_RESERVED_31_30_MASK) /*! @} */ /*! @name DX8SLBPLLCR0 - DAXT8 0-8 PLL Control Register 0 */ /*! @{ */ #define DDRPHY_DX8SLBPLLCR0_DTC_MASK (0xFU) #define DDRPHY_DX8SLBPLLCR0_DTC_SHIFT (0U) /*! DTC - Digital Test Control */ #define DDRPHY_DX8SLBPLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_DTC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_DTC_MASK) #define DDRPHY_DX8SLBPLLCR0_ATC_MASK (0xF0U) #define DDRPHY_DX8SLBPLLCR0_ATC_SHIFT (4U) /*! ATC - Analog Test Control */ #define DDRPHY_DX8SLBPLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_ATC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_ATC_MASK) #define DDRPHY_DX8SLBPLLCR0_ATOEN_MASK (0x100U) #define DDRPHY_DX8SLBPLLCR0_ATOEN_SHIFT (8U) /*! ATOEN - Analog Test Enable (ATOEN) */ #define DDRPHY_DX8SLBPLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SLBPLLCR0_ATOEN_MASK) #define DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_MASK (0xE00U) #define DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT (9U) /*! RESERVED_11_9 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBPLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_MASK) #define DDRPHY_DX8SLBPLLCR0_GSHIFT_MASK (0x1000U) #define DDRPHY_DX8SLBPLLCR0_GSHIFT_SHIFT (12U) /*! GSHIFT - Gear Shift */ #define DDRPHY_DX8SLBPLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SLBPLLCR0_GSHIFT_MASK) #define DDRPHY_DX8SLBPLLCR0_CPIC_MASK (0x1E000U) #define DDRPHY_DX8SLBPLLCR0_CPIC_SHIFT (13U) /*! CPIC - Charge Pump Integrating Current Control */ #define DDRPHY_DX8SLBPLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_CPIC_MASK) #define DDRPHY_DX8SLBPLLCR0_CPPC_MASK (0x7E0000U) #define DDRPHY_DX8SLBPLLCR0_CPPC_SHIFT (17U) /*! CPPC - Charge Pump Proportional Current Control */ #define DDRPHY_DX8SLBPLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_CPPC_MASK) #define DDRPHY_DX8SLBPLLCR0_RLOCKM_MASK (0x800000U) #define DDRPHY_DX8SLBPLLCR0_RLOCKM_SHIFT (23U) /*! RLOCKM - Relock Mode */ #define DDRPHY_DX8SLBPLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SLBPLLCR0_RLOCKM_MASK) #define DDRPHY_DX8SLBPLLCR0_FRQSEL_MASK (0xF000000U) #define DDRPHY_DX8SLBPLLCR0_FRQSEL_SHIFT (24U) /*! FRQSEL - PLL Frequency Select */ #define DDRPHY_DX8SLBPLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SLBPLLCR0_FRQSEL_MASK) #define DDRPHY_DX8SLBPLLCR0_RSTOPM_MASK (0x10000000U) #define DDRPHY_DX8SLBPLLCR0_RSTOPM_SHIFT (28U) /*! RSTOPM - Reference Stop Mode */ #define DDRPHY_DX8SLBPLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SLBPLLCR0_RSTOPM_MASK) #define DDRPHY_DX8SLBPLLCR0_PLLPD_MASK (0x20000000U) #define DDRPHY_DX8SLBPLLCR0_PLLPD_SHIFT (29U) /*! PLLPD - PLL Power Down */ #define DDRPHY_DX8SLBPLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SLBPLLCR0_PLLPD_MASK) #define DDRPHY_DX8SLBPLLCR0_PLLRST_MASK (0x40000000U) #define DDRPHY_DX8SLBPLLCR0_PLLRST_SHIFT (30U) /*! PLLRST - PLL Reset */ #define DDRPHY_DX8SLBPLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SLBPLLCR0_PLLRST_MASK) #define DDRPHY_DX8SLBPLLCR0_PLLBYP_MASK (0x80000000U) #define DDRPHY_DX8SLBPLLCR0_PLLBYP_SHIFT (31U) /*! PLLBYP - PLL Bypass */ #define DDRPHY_DX8SLBPLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SLBPLLCR0_PLLBYP_MASK) /*! @} */ /*! @name DX8SLBPLLCR1 - DAXT8 0-8 PLL Control Register 1 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SLBPLLCR1_LOCKDS_MASK (0x1U) #define DDRPHY_DX8SLBPLLCR1_LOCKDS_SHIFT (0U) /*! LOCKDS - Lock Detector Select */ #define DDRPHY_DX8SLBPLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SLBPLLCR1_LOCKDS_MASK) #define DDRPHY_DX8SLBPLLCR1_LOCKCS_MASK (0x2U) #define DDRPHY_DX8SLBPLLCR1_LOCKCS_SHIFT (1U) /*! LOCKCS - Lock Detector Counter Select */ #define DDRPHY_DX8SLBPLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SLBPLLCR1_LOCKCS_MASK) #define DDRPHY_DX8SLBPLLCR1_LOCKPS_MASK (0x4U) #define DDRPHY_DX8SLBPLLCR1_LOCKPS_SHIFT (2U) /*! LOCKPS - Lock Detector Phase Select */ #define DDRPHY_DX8SLBPLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SLBPLLCR1_LOCKPS_MASK) #define DDRPHY_DX8SLBPLLCR1_BYPVDD_MASK (0x8U) #define DDRPHY_DX8SLBPLLCR1_BYPVDD_SHIFT (3U) /*! BYPVDD - PLL VDD voltage level control */ #define DDRPHY_DX8SLBPLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SLBPLLCR1_BYPVDD_MASK) #define DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_MASK (0x10U) #define DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_SHIFT (4U) /*! BYPVREGDIG - Bypass PLL vreg_dig */ #define DDRPHY_DX8SLBPLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_MASK) #define DDRPHY_DX8SLBPLLCR1_BYPVREGCP_MASK (0x20U) #define DDRPHY_DX8SLBPLLCR1_BYPVREGCP_SHIFT (5U) /*! BYPVREGCP - Bypass PLL vreg_cp */ #define DDRPHY_DX8SLBPLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SLBPLLCR1_BYPVREGCP_MASK) #define DDRPHY_DX8SLBPLLCR1_PLLPROG_MASK (0x3FFFC0U) #define DDRPHY_DX8SLBPLLCR1_PLLPROG_SHIFT (6U) /*! PLLPROG - Connects to the PLL PLL_PROG bus. */ #define DDRPHY_DX8SLBPLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SLBPLLCR1_PLLPROG_MASK) #define DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_MASK (0xFFC00000U) #define DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_SHIFT (22U) /*! RESERVED_31_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBPLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_MASK) /*! @} */ /*! @name DX8SLBPLLCR2 - DAXT8 0-8 PLL Control Register 2 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_SHIFT (0U) /*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_MASK) /*! @} */ /*! @name DX8SLBPLLCR3 - DAXT8 0-8 PLL Control Register 3 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_SHIFT (0U) /*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_MASK) /*! @} */ /*! @name DX8SLBPLLCR4 - DAXT8 0-8 PLL Control Register 4 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_SHIFT (0U) /*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_MASK) /*! @} */ /*! @name DX8SLBPLLCR5 - DAXT8 0-8 PLL Control Register 5 (Type B PLL Only) */ /*! @{ */ #define DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_MASK (0xFFU) #define DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_SHIFT (0U) /*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL */ #define DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_MASK) #define DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U) #define DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_SHIFT (8U) /*! RESERVED_31_8 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBPLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_MASK) /*! @} */ /*! @name DX8SLBDQSCTL - DATX8 0-8 DQS Control Register */ /*! @{ */ #define DDRPHY_DX8SLBDQSCTL_DQSRES_MASK (0xFU) #define DDRPHY_DX8SLBDQSCTL_DQSRES_SHIFT (0U) /*! DQSRES - DQS Resistor */ #define DDRPHY_DX8SLBDQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DQSRES_MASK) #define DDRPHY_DX8SLBDQSCTL_DQSNRES_MASK (0xF0U) #define DDRPHY_DX8SLBDQSCTL_DQSNRES_SHIFT (4U) /*! DQSNRES - DQS# Resistor */ #define DDRPHY_DX8SLBDQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DQSNRES_MASK) #define DDRPHY_DX8SLBDQSCTL_DXSR_MASK (0x300U) #define DDRPHY_DX8SLBDQSCTL_DXSR_SHIFT (8U) /*! DXSR - Data Slew Rate */ #define DDRPHY_DX8SLBDQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DXSR_MASK) #define DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_MASK (0x1C00U) #define DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT (10U) /*! RESERVED_12_10 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_MASK) #define DDRPHY_DX8SLBDQSCTL_UDQIOM_MASK (0x2000U) #define DDRPHY_DX8SLBDQSCTL_UDQIOM_SHIFT (13U) /*! UDQIOM - Unused DQ I/O Mode */ #define DDRPHY_DX8SLBDQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SLBDQSCTL_UDQIOM_MASK) #define DDRPHY_DX8SLBDQSCTL_QSCNTEN_MASK (0x4000U) #define DDRPHY_DX8SLBDQSCTL_QSCNTEN_SHIFT (14U) /*! QSCNTEN - QS Counter Enable */ #define DDRPHY_DX8SLBDQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SLBDQSCTL_QSCNTEN_MASK) #define DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_MASK (0x18000U) #define DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT (15U) /*! RESERVED_16_15 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_MASK) #define DDRPHY_DX8SLBDQSCTL_LPIOPD_MASK (0x20000U) #define DDRPHY_DX8SLBDQSCTL_LPIOPD_SHIFT (17U) /*! LPIOPD - Low Power I/O Power Down */ #define DDRPHY_DX8SLBDQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SLBDQSCTL_LPIOPD_MASK) #define DDRPHY_DX8SLBDQSCTL_LPPLLPD_MASK (0x40000U) #define DDRPHY_DX8SLBDQSCTL_LPPLLPD_SHIFT (18U) /*! LPPLLPD - Low Power PLL Power Down */ #define DDRPHY_DX8SLBDQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SLBDQSCTL_LPPLLPD_MASK) #define DDRPHY_DX8SLBDQSCTL_DQSGX_MASK (0x180000U) #define DDRPHY_DX8SLBDQSCTL_DQSGX_SHIFT (19U) /*! DQSGX - DQS Gate Extension */ #define DDRPHY_DX8SLBDQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DQSGX_MASK) #define DDRPHY_DX8SLBDQSCTL_WRRMODE_MASK (0x200000U) #define DDRPHY_DX8SLBDQSCTL_WRRMODE_SHIFT (21U) /*! WRRMODE - Write Path Rise-to-Rise Mode */ #define DDRPHY_DX8SLBDQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SLBDQSCTL_WRRMODE_MASK) #define DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_MASK (0xC00000U) #define DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT (22U) /*! RESERVED_23_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_MASK) #define DDRPHY_DX8SLBDQSCTL_RRRMODE_MASK (0x1000000U) #define DDRPHY_DX8SLBDQSCTL_RRRMODE_SHIFT (24U) /*! RRRMODE - Read Path Rise-to-Rise Mode */ #define DDRPHY_DX8SLBDQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RRRMODE_MASK) #define DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SLBTRNCTL - DATX8 0-8 Training Control Register */ /*! @{ */ #define DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBTRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_MASK) /*! @} */ /*! @name DX8SLBDDLCTL - DATX8 0-8 DDL Control Register */ /*! @{ */ #define DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_MASK (0x3U) #define DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_SHIFT (0U) /*! DDLBYPMODE - Controls DDL Bypass Mode */ #define DDRPHY_DX8SLBDDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_MASK) #define DDRPHY_DX8SLBDDLCTL_DXDDLBYP_MASK (0x3FFFCU) #define DDRPHY_DX8SLBDDLCTL_DXDDLBYP_SHIFT (2U) /*! DXDDLBYP - DATX8 DDL Bypass */ #define DDRPHY_DX8SLBDDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DXDDLBYP_MASK) #define DDRPHY_DX8SLBDDLCTL_DXDDLLD_MASK (0x7C0000U) #define DDRPHY_DX8SLBDDLCTL_DXDDLLD_SHIFT (18U) /*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load */ #define DDRPHY_DX8SLBDDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DXDDLLD_MASK) #define DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_MASK (0x1800000U) #define DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_SHIFT (23U) /*! RESERVED_24_23 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_MASK) #define DDRPHY_DX8SLBDDLCTL_DXDDLLDT_MASK (0x2000000U) #define DDRPHY_DX8SLBDDLCTL_DXDDLLDT_SHIFT (25U) /*! DXDDLLDT - DX DDL Load Type */ #define DDRPHY_DX8SLBDDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DXDDLLDT_MASK) #define DDRPHY_DX8SLBDDLCTL_DLYLDTM_MASK (0x4000000U) #define DDRPHY_DX8SLBDDLCTL_DLYLDTM_SHIFT (26U) /*! DLYLDTM - Delay Load Timing */ #define DDRPHY_DX8SLBDDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DLYLDTM_MASK) #define DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_MASK (0xF8000000U) #define DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_SHIFT (27U) /*! RESERVED_31_27 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_MASK) /*! @} */ /*! @name DX8SLBDXCTL1 - DATX8 0-8 DX Control Register 1 */ /*! @{ */ #define DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_MASK (0xFFFFU) #define DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_SHIFT (0U) /*! RESERVED_15_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_MASK) #define DDRPHY_DX8SLBDXCTL1_DXTMODE_MASK (0x10000U) #define DDRPHY_DX8SLBDXCTL1_DXTMODE_SHIFT (16U) /*! DXTMODE - DATX8 Test Mode */ #define DDRPHY_DX8SLBDXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXTMODE_MASK) #define DDRPHY_DX8SLBDXCTL1_DXGDBYP_MASK (0x20000U) #define DDRPHY_DX8SLBDXCTL1_DXGDBYP_SHIFT (17U) /*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode */ #define DDRPHY_DX8SLBDXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXGDBYP_MASK) #define DDRPHY_DX8SLBDXCTL1_DXQSDBYP_MASK (0x40000U) #define DDRPHY_DX8SLBDXCTL1_DXQSDBYP_SHIFT (18U) /*! DXQSDBYP - Read DQS/DQS# Delay Load Bypass Mode */ #define DDRPHY_DX8SLBDXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXQSDBYP_MASK) #define DDRPHY_DX8SLBDXCTL1_DXGSMD_MASK (0x80000U) #define DDRPHY_DX8SLBDXCTL1_DXGSMD_SHIFT (19U) /*! DXGSMD - Read DQS Gating Status Mode */ #define DDRPHY_DX8SLBDXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXGSMD_MASK) #define DDRPHY_DX8SLBDXCTL1_DXDTOSEL_MASK (0x300000U) #define DDRPHY_DX8SLBDXCTL1_DXDTOSEL_SHIFT (20U) /*! DXDTOSEL - DATX8 Digital Test Output Select */ #define DDRPHY_DX8SLBDXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXDTOSEL_MASK) #define DDRPHY_DX8SLBDXCTL1_RESERVED_22_MASK (0x400000U) #define DDRPHY_DX8SLBDXCTL1_RESERVED_22_SHIFT (22U) /*! RESERVED_22 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SLBDXCTL1_RESERVED_22_MASK) #define DDRPHY_DX8SLBDXCTL1_DXRCLKMD_MASK (0x800000U) #define DDRPHY_DX8SLBDXCTL1_DXRCLKMD_SHIFT (23U) /*! DXRCLKMD - DATX8 Read Clock Mode */ #define DDRPHY_DX8SLBDXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXRCLKMD_MASK) #define DDRPHY_DX8SLBDXCTL1_DXCALCLK_MASK (0x1000000U) #define DDRPHY_DX8SLBDXCTL1_DXCALCLK_SHIFT (24U) /*! DXCALCLK - DATX Calibration Clock Select */ #define DDRPHY_DX8SLBDXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXCALCLK_MASK) #define DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_MASK (0xFE000000U) #define DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_SHIFT (25U) /*! RESERVED_31_25 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_MASK) /*! @} */ /*! @name DX8SLBDXCTL2 - DATX8 0-8 DX Control Register 2 */ /*! @{ */ #define DDRPHY_DX8SLBDXCTL2_RESERVED_0_MASK (0x1U) #define DDRPHY_DX8SLBDXCTL2_RESERVED_0_SHIFT (0U) /*! RESERVED_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_0_MASK) #define DDRPHY_DX8SLBDXCTL2_DQSGLB_MASK (0x6U) #define DDRPHY_DX8SLBDXCTL2_DQSGLB_SHIFT (1U) /*! DQSGLB - Read DQS Gate I/O Loopback */ #define DDRPHY_DX8SLBDXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SLBDXCTL2_DQSGLB_MASK) #define DDRPHY_DX8SLBDXCTL2_DISRST_MASK (0x8U) #define DDRPHY_DX8SLBDXCTL2_DISRST_SHIFT (3U) /*! DISRST - Disables the Read FIFO Reset */ #define DDRPHY_DX8SLBDXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SLBDXCTL2_DISRST_MASK) #define DDRPHY_DX8SLBDXCTL2_RDMODE_MASK (0x30U) #define DDRPHY_DX8SLBDXCTL2_RDMODE_SHIFT (4U) /*! RDMODE - DATX8 Receive FIFO Read Mode */ #define DDRPHY_DX8SLBDXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RDMODE_MASK) #define DDRPHY_DX8SLBDXCTL2_PRFBYP_MASK (0x40U) #define DDRPHY_DX8SLBDXCTL2_PRFBYP_SHIFT (6U) /*! PRFBYP - PUB Read FIFO Bypass */ #define DDRPHY_DX8SLBDXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SLBDXCTL2_PRFBYP_MASK) #define DDRPHY_DX8SLBDXCTL2_WDBI_MASK (0x80U) #define DDRPHY_DX8SLBDXCTL2_WDBI_SHIFT (7U) /*! WDBI - Write Data Bus Inversion Enable */ #define DDRPHY_DX8SLBDXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SLBDXCTL2_WDBI_MASK) #define DDRPHY_DX8SLBDXCTL2_RDBI_MASK (0x100U) #define DDRPHY_DX8SLBDXCTL2_RDBI_SHIFT (8U) /*! RDBI - Read Data Bus Inversion Enable */ #define DDRPHY_DX8SLBDXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RDBI_MASK) #define DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U) #define DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_SHIFT (9U) /*! LPWAKEUP_THRSH - Low Power Wakeup Threshold */ #define DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_MASK) #define DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_MASK (0x6000U) #define DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_SHIFT (13U) /*! RESERVED_14_13 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_MASK) #define DDRPHY_DX8SLBDXCTL2_IOLB_MASK (0x8000U) #define DDRPHY_DX8SLBDXCTL2_IOLB_SHIFT (15U) /*! IOLB - I/O Loopback Select */ #define DDRPHY_DX8SLBDXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SLBDXCTL2_IOLB_MASK) #define DDRPHY_DX8SLBDXCTL2_IOAG_MASK (0x10000U) #define DDRPHY_DX8SLBDXCTL2_IOAG_SHIFT (16U) /*! IOAG - I/O Assisted Gate Select */ #define DDRPHY_DX8SLBDXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SLBDXCTL2_IOAG_MASK) #define DDRPHY_DX8SLBDXCTL2_RESERVED_17_MASK (0x20000U) #define DDRPHY_DX8SLBDXCTL2_RESERVED_17_SHIFT (17U) /*! RESERVED_17 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_17_MASK) #define DDRPHY_DX8SLBDXCTL2_PREOEX_MASK (0xC0000U) #define DDRPHY_DX8SLBDXCTL2_PREOEX_SHIFT (18U) /*! PREOEX - OE Extension during Pre-amble */ #define DDRPHY_DX8SLBDXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SLBDXCTL2_PREOEX_MASK) #define DDRPHY_DX8SLBDXCTL2_POSOEX_MASK (0x700000U) #define DDRPHY_DX8SLBDXCTL2_POSOEX_SHIFT (20U) /*! POSOEX - OX Extension during Post-amble */ #define DDRPHY_DX8SLBDXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SLBDXCTL2_POSOEX_MASK) #define DDRPHY_DX8SLBDXCTL2_CRDEN_MASK (0x800000U) #define DDRPHY_DX8SLBDXCTL2_CRDEN_SHIFT (23U) /*! CRDEN - Configurable Read Data Enable */ #define DDRPHY_DX8SLBDXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SLBDXCTL2_CRDEN_MASK) #define DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_MASK (0xFF000000U) #define DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_SHIFT (24U) /*! RESERVED_31_24 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBDXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_MASK) /*! @} */ /*! @name DX8SLBIOCR - DATX8 0-8 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX8SLBIOCR_DXRXM_MASK (0x7FFU) #define DDRPHY_DX8SLBIOCR_DXRXM_SHIFT (0U) /*! DXRXM - DX IO Receiver Mode */ #define DDRPHY_DX8SLBIOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXRXM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXRXM_MASK) #define DDRPHY_DX8SLBIOCR_DXTXM_MASK (0x3FF800U) #define DDRPHY_DX8SLBIOCR_DXTXM_SHIFT (11U) /*! DXTXM - DX IO Transmitter Mode */ #define DDRPHY_DX8SLBIOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXTXM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXTXM_MASK) #define DDRPHY_DX8SLBIOCR_DXIOM_MASK (0x1C00000U) #define DDRPHY_DX8SLBIOCR_DXIOM_SHIFT (22U) /*! DXIOM - DX IO Mode */ #define DDRPHY_DX8SLBIOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXIOM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXIOM_MASK) #define DDRPHY_DX8SLBIOCR_DXVREFIOM_MASK (0xE000000U) #define DDRPHY_DX8SLBIOCR_DXVREFIOM_SHIFT (25U) /*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring */ #define DDRPHY_DX8SLBIOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXVREFIOM_MASK) #define DDRPHY_DX8SLBIOCR_DXDACRANGE_MASK (0x70000000U) #define DDRPHY_DX8SLBIOCR_DXDACRANGE_SHIFT (28U) /*! DXDACRANGE - PVREF_DAC REFSEL range select */ #define DDRPHY_DX8SLBIOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SLBIOCR_DXDACRANGE_MASK) #define DDRPHY_DX8SLBIOCR_RESERVED_31_MASK (0x80000000U) #define DDRPHY_DX8SLBIOCR_RESERVED_31_SHIFT (31U) /*! RESERVED_31 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX8SLBIOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SLBIOCR_RESERVED_31_MASK) /*! @} */ /*! @name DX4SLBIOCR - DATX4 0-8 I/O Configuration Register */ /*! @{ */ #define DDRPHY_DX4SLBIOCR_RESERVED_31_0_MASK (0xFFFFFFFFU) #define DDRPHY_DX4SLBIOCR_RESERVED_31_0_SHIFT (0U) /*! RESERVED_31_0 - Reserved. Return zeroes on reads. */ #define DDRPHY_DX4SLBIOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SLBIOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SLBIOCR_RESERVED_31_0_MASK) /*! @} */ /*! * @} */ /* end of group DDRPHY_Register_Masks */ /* DDRPHY - Peripheral instance base addresses */ /** Peripheral DRC__DDR_PHY base address */ #define DRC__DDR_PHY_BASE (0x5C010000u) /** Peripheral DRC__DDR_PHY base pointer */ #define DRC__DDR_PHY ((DDRPHY_Type *)DRC__DDR_PHY_BASE) /** Array initializer of DDRPHY peripheral base addresses */ #define DDRPHY_BASE_ADDRS { DRC__DDR_PHY_BASE } /** Array initializer of DDRPHY peripheral base pointers */ #define DDRPHY_BASE_PTRS { DRC__DDR_PHY } /*! * @} */ /* end of group DDRPHY_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer * @{ */ /** DMA - Register Layout Typedef */ typedef struct { __IO uint32_t MP_CSR; /**< Management Page Control Register, offset: 0x0 */ __I uint32_t MP_ES; /**< Management Page Error Status Register, offset: 0x4 */ uint8_t RESERVED_0[4]; __I uint32_t MP_HRS; /**< Management Page Hardware Request Status Register, offset: 0xC */ uint8_t RESERVED_1[240]; __IO uint32_t CH_GRPRI[32]; /**< Channel Arbitration Group Register, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_2[65152]; struct { /* offset: 0x10000, array step: 0x10000 */ __IO uint32_t CH_CSR; /**< Channel Control and Status Register, array offset: 0x10000, array step: 0x10000 */ __IO uint32_t CH_ES; /**< Channel Error Status Register, array offset: 0x10004, array step: 0x10000 */ __IO uint32_t CH_INT; /**< Channel Interrupt Status Register, array offset: 0x10008, array step: 0x10000 */ __IO uint32_t CH_SBR; /**< Channel System Bus Register, array offset: 0x1000C, array step: 0x10000 */ __IO uint32_t CH_PRI; /**< Channel Priority Register, array offset: 0x10010, array step: 0x10000 */ __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */ uint8_t RESERVED_0[8]; __IO uint32_t TCD_SADDR; /**< TCD Source Address Register, array offset: 0x10020, array step: 0x10000 */ __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset Register, array offset: 0x10024, array step: 0x10000 */ __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes Register, array offset: 0x10026, array step: 0x10000 */ union { /* offset: 0x10028, array step: 0x10000 */ __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size without Minor Loop Offsets Register, array offset: 0x10028, array step: 0x10000 */ __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets Register, array offset: 0x10028, array step: 0x10000 */ }; __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address Register, array offset: 0x1002C, array step: 0x10000 */ __IO uint32_t TCD_DADDR; /**< TCD Destination Address Register, array offset: 0x10030, array step: 0x10000 */ __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset Register, array offset: 0x10034, array step: 0x10000 */ union { /* offset: 0x10036, array step: 0x10000 */ __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x10036, array step: 0x10000 */ __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x10036, array step: 0x10000 */ }; __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address Register, array offset: 0x10038, array step: 0x10000 */ __IO uint16_t TCD_CSR; /**< TCD Control and Status Register, array offset: 0x1003C, array step: 0x10000 */ union { /* offset: 0x1003E, array step: 0x10000 */ __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x1003E, array step: 0x10000 */ __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x1003E, array step: 0x10000 */ }; uint8_t RESERVED_1[65472]; } CH[32]; } DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /*! @name MP_CSR - Management Page Control Register */ /*! @{ */ #define DMA_MP_CSR_EBW_MASK (0x1U) #define DMA_MP_CSR_EBW_SHIFT (0U) /*! EBW - Enable Buffered Writes * 0b0..Buffered writes on the system bus are disabled. * 0b1..Buffered writes on the system bus are enabled. */ #define DMA_MP_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EBW_SHIFT)) & DMA_MP_CSR_EBW_MASK) #define DMA_MP_CSR_EDBG_MASK (0x2U) #define DMA_MP_CSR_EDBG_SHIFT (1U) /*! EDBG - Enable Debug * 0b0..Debug mode is disabled. * 0b1..Debug mode is enabled. */ #define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) #define DMA_MP_CSR_ERCA_MASK (0x4U) #define DMA_MP_CSR_ERCA_SHIFT (2U) /*! ERCA - Enable Round Robin Channel Arbitration * 0b0..Round robin channel arbitration is disabled. * 0b1..Round robin channel arbitration is enabled. */ #define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) #define DMA_MP_CSR_HAE_MASK (0x10U) #define DMA_MP_CSR_HAE_SHIFT (4U) /*! HAE - Halt After Error * 0b0..Normal operation * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. */ #define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) #define DMA_MP_CSR_HALT_MASK (0x20U) #define DMA_MP_CSR_HALT_SHIFT (5U) /*! HALT - Halt DMA Operations * 0b0..Normal operation * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. */ #define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) #define DMA_MP_CSR_GCLC_MASK (0x40U) #define DMA_MP_CSR_GCLC_SHIFT (6U) /*! GCLC - Global Channel Linking Control * 0b0..Channel linking is disabled for all channels. * 0b1..Channel linking is available and controlled by each channel's link settings. */ #define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) #define DMA_MP_CSR_GMRC_MASK (0x80U) #define DMA_MP_CSR_GMRC_SHIFT (7U) /*! GMRC - Global Master ID Replication Control * 0b0..Master ID replication is disabled for all channels. * 0b1..Master ID replication is available and is controlled by each channel's CHn_SBR[EMI] setting. */ #define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) #define DMA_MP_CSR_ECX_MASK (0x100U) #define DMA_MP_CSR_ECX_SHIFT (8U) /*! ECX - Cancel Transfer with Error * 0b0..Normal operation * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and * force the minor loop to finish. The cancel takes effect after the last write of the current read/write * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an * optional error interrupt. */ #define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) #define DMA_MP_CSR_CX_MASK (0x200U) #define DMA_MP_CSR_CX_SHIFT (9U) /*! CX - Cancel Transfer * 0b0..Normal operation * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. */ #define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) #define DMA_MP_CSR_ACTIVE_ID_MASK (0x1F000000U) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */ #define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) /*! ACTIVE_ID - Active channel ID */ #define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */ #define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) #define DMA_MP_CSR_ACTIVE_SHIFT (31U) /*! ACTIVE - DMA Active Status * 0b0..eDMA is idle. * 0b1..eDMA is executing a channel. */ #define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) /*! @} */ /*! @name MP_ES - Management Page Error Status Register */ /*! @{ */ #define DMA_MP_ES_DBE_MASK (0x1U) #define DMA_MP_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No destination bus error * 0b1..The last recorded error was a bus error on a destination write */ #define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) #define DMA_MP_ES_SBE_MASK (0x2U) #define DMA_MP_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No source bus error * 0b1..The last recorded error was a bus error on a source read */ #define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) #define DMA_MP_ES_SGE_MASK (0x4U) #define DMA_MP_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No scatter/gather configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. */ #define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) #define DMA_MP_ES_NCE_MASK (0x8U) #define DMA_MP_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error */ #define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) #define DMA_MP_ES_DOE_MASK (0x10U) #define DMA_MP_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No destination offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) #define DMA_MP_ES_DAE_MASK (0x20U) #define DMA_MP_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No destination address configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) #define DMA_MP_ES_SOE_MASK (0x40U) #define DMA_MP_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No source offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) #define DMA_MP_ES_SAE_MASK (0x80U) #define DMA_MP_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No source address configuration error. * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) #define DMA_MP_ES_ECX_MASK (0x100U) #define DMA_MP_ES_ECX_SHIFT (8U) /*! ECX - Transfer Canceled * 0b0..No canceled transfers * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input. */ #define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) #define DMA_MP_ES_ERRCHN_MASK (0x1F000000U) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */ #define DMA_MP_ES_ERRCHN_SHIFT (24U) /*! ERRCHN - Error Channel Number or Canceled Channel Number */ #define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */ #define DMA_MP_ES_VLD_MASK (0x80000000U) #define DMA_MP_ES_VLD_SHIFT (31U) /*! VLD - Valid * 0b0..No ERR bits are set. * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. */ #define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) /*! @} */ /*! @name MP_HRS - Management Page Hardware Request Status Register */ /*! @{ */ #define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) #define DMA_MP_HRS_HRS_SHIFT (0U) /*! HRS - Hardware Request Status * 0b00000000000000000000000000000000..A hardware service request for the channel is not present * 0b00000000000000000000000000000001..A hardware service request for channel 0 is present */ #define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) /*! @} */ /*! @name CH_GRPRI - Channel Arbitration Group Register */ /*! @{ */ #define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) #define DMA_CH_GRPRI_GRPRI_SHIFT (0U) /*! GRPRI - Arbitration Group for channel n. */ #define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) /*! @} */ /* The count of DMA_CH_GRPRI */ #define DMA_CH_GRPRI_COUNT (32U) /*! @name CH_CSR - Channel Control and Status Register */ /*! @{ */ #define DMA_CH_CSR_ERQ_MASK (0x1U) #define DMA_CH_CSR_ERQ_SHIFT (0U) /*! ERQ - Enable DMA Request * 0b0..The DMA hardware request signal for the corresponding channel is disabled. * 0b1..The DMA hardware request signal for the corresponding channel is enabled. */ #define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK) #define DMA_CH_CSR_EARQ_MASK (0x2U) #define DMA_CH_CSR_EARQ_SHIFT (1U) /*! EARQ - Enable Asynchronous DMA Request in stop mode for channel * 0b0..Disable asynchronous DMA request for the channel. * 0b1..Enable asynchronous DMA request for the channel. */ #define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK) #define DMA_CH_CSR_EEI_MASK (0x4U) #define DMA_CH_CSR_EEI_SHIFT (2U) /*! EEI - Enable Error Interrupt * 0b0..The error signal for corresponding channel does not generate an error interrupt * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request */ #define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK) #define DMA_CH_CSR_DONE_MASK (0x40000000U) #define DMA_CH_CSR_DONE_SHIFT (30U) /*! DONE - Channel Done */ #define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK) #define DMA_CH_CSR_ACTIVE_MASK (0x80000000U) #define DMA_CH_CSR_ACTIVE_SHIFT (31U) /*! ACTIVE - Channel Active */ #define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK) /*! @} */ /* The count of DMA_CH_CSR */ #define DMA_CH_CSR_COUNT (32U) /*! @name CH_ES - Channel Error Status Register */ /*! @{ */ #define DMA_CH_ES_DBE_MASK (0x1U) #define DMA_CH_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No destination bus error * 0b1..The last recorded error was a bus error on a destination write */ #define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK) #define DMA_CH_ES_SBE_MASK (0x2U) #define DMA_CH_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No source bus error * 0b1..The last recorded error was a bus error on a source read */ #define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK) #define DMA_CH_ES_SGE_MASK (0x4U) #define DMA_CH_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No scatter/gather configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. */ #define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK) #define DMA_CH_ES_NCE_MASK (0x8U) #define DMA_CH_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] */ #define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK) #define DMA_CH_ES_DOE_MASK (0x10U) #define DMA_CH_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No destination offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK) #define DMA_CH_ES_DAE_MASK (0x20U) #define DMA_CH_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No destination address configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. */ #define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK) #define DMA_CH_ES_SOE_MASK (0x40U) #define DMA_CH_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No source offset configuration error * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK) #define DMA_CH_ES_SAE_MASK (0x80U) #define DMA_CH_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No source address configuration error. * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. */ #define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK) #define DMA_CH_ES_ERR_MASK (0x80000000U) #define DMA_CH_ES_ERR_SHIFT (31U) /*! ERR - Error In Channel * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK) /*! @} */ /* The count of DMA_CH_ES */ #define DMA_CH_ES_COUNT (32U) /*! @name CH_INT - Channel Interrupt Status Register */ /*! @{ */ #define DMA_CH_INT_INT_MASK (0x1U) #define DMA_CH_INT_INT_SHIFT (0U) /*! INT - Interrupt Request * 0b0..The interrupt request for corresponding channel is cleared * 0b1..The interrupt request for corresponding channel is active */ #define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK) /*! @} */ /* The count of DMA_CH_INT */ #define DMA_CH_INT_COUNT (32U) /*! @name CH_SBR - Channel System Bus Register */ /*! @{ */ #define DMA_CH_SBR_MID_MASK (0x1FU) #define DMA_CH_SBR_MID_SHIFT (0U) /*! MID - Master ID */ #define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) #define DMA_CH_SBR_PAL_MASK (0x8000U) #define DMA_CH_SBR_PAL_SHIFT (15U) /*! PAL - Privileged Access Level * 0b0..User protection level for DMA transfers * 0b1..Privileged protection level for DMA transfers */ #define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK) #define DMA_CH_SBR_EMI_MASK (0x10000U) #define DMA_CH_SBR_EMI_SHIFT (16U) /*! EMI - Enable Master ID replication * 0b0..Master ID replication is disabled * 0b1..Master ID replication is enabled */ #define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) #define DMA_CH_SBR_ATTR_MASK (0x7E0000U) #define DMA_CH_SBR_ATTR_SHIFT (17U) /*! ATTR - Attribute Output */ #define DMA_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK) /*! @} */ /* The count of DMA_CH_SBR */ #define DMA_CH_SBR_COUNT (32U) /*! @name CH_PRI - Channel Priority Register */ /*! @{ */ #define DMA_CH_PRI_APL_MASK (0x7U) #define DMA_CH_PRI_APL_SHIFT (0U) /*! APL - Arbitration Priority Level */ #define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK) #define DMA_CH_PRI_DPA_MASK (0x40000000U) #define DMA_CH_PRI_DPA_SHIFT (30U) /*! DPA - Disable Preempt Ability. * 0b0..The channel can suspend a lower priority channel. * 0b1..The channel cannot suspend any other channel, regardless of channel priority. */ #define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK) #define DMA_CH_PRI_ECP_MASK (0x80000000U) #define DMA_CH_PRI_ECP_SHIFT (31U) /*! ECP - Enable Channel Preemption. * 0b0..The channel cannot be suspended by a higher priority channel's service request. * 0b1..The channel can be temporarily suspended by the service request of a higher priority channel. */ #define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK) /*! @} */ /* The count of DMA_CH_PRI */ #define DMA_CH_PRI_COUNT (32U) /*! @name CH_MUX - Channel Multiplexor Configuration */ /*! @{ */ #define DMA_CH_MUX_SRC_MASK (0x1FU) #define DMA_CH_MUX_SRC_SHIFT (0U) /*! SRC - Service Request Source */ #define DMA_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK) /*! @} */ /* The count of DMA_CH_MUX */ #define DMA_CH_MUX_COUNT (32U) /*! @name TCD_SADDR - TCD Source Address Register */ /*! @{ */ #define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_TCD_SADDR_SADDR_SHIFT (0U) /*! SADDR - Source Address */ #define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) /*! @} */ /* The count of DMA_TCD_SADDR */ #define DMA_TCD_SADDR_COUNT (32U) /*! @name TCD_SOFF - TCD Signed Source Address Offset Register */ /*! @{ */ #define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) #define DMA_TCD_SOFF_SOFF_SHIFT (0U) /*! SOFF - Source address signed offset */ #define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) /*! @} */ /* The count of DMA_TCD_SOFF */ #define DMA_TCD_SOFF_COUNT (32U) /*! @name TCD_ATTR - TCD Transfer Attributes Register */ /*! @{ */ #define DMA_TCD_ATTR_DSIZE_MASK (0x7U) #define DMA_TCD_ATTR_DSIZE_SHIFT (0U) /*! DSIZE - Destination data transfer size */ #define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) #define DMA_TCD_ATTR_DMOD_MASK (0xF8U) #define DMA_TCD_ATTR_DMOD_SHIFT (3U) /*! DMOD - Destination address modulo */ #define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) #define DMA_TCD_ATTR_SSIZE_MASK (0x700U) #define DMA_TCD_ATTR_SSIZE_SHIFT (8U) /*! SSIZE - Source data transfer size * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit * 0b011..64-bit * 0b100..16-byte * 0b101..32-byte * 0b110..64-byte * 0b111..Reserved */ #define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) #define DMA_TCD_ATTR_SMOD_MASK (0xF800U) #define DMA_TCD_ATTR_SMOD_SHIFT (11U) /*! SMOD - Source address modulo * 0b00000..Source address modulo feature is disabled * 0b00001..Source address modulo feature is enabled for any non-zero value [1-31] */ #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) /*! @} */ /* The count of DMA_TCD_ATTR */ #define DMA_TCD_ATTR_COUNT (32U) /*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size without Minor Loop Offsets Register */ /*! @{ */ #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) /*! NBYTES - Number of Bytes to transfer per service request */ #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the DADDR * 0b1..The minor loop offset is applied to the DADDR */ #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the SADDR * 0b1..The minor loop offset is applied to the SADDR */ #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) /*! @} */ /* The count of DMA_TCD_NBYTES_MLOFFNO */ #define DMA_TCD_NBYTES_MLOFFNO_COUNT (32U) /*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets Register */ /*! @{ */ #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) /*! NBYTES - Number of Bytes to transfer per service request */ #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) /*! MLOFF - Minor Loop Offset */ #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the DADDR * 0b1..The minor loop offset is applied to the DADDR */ #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..The minor loop offset is not applied to the SADDR * 0b1..The minor loop offset is applied to the SADDR */ #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) /*! @} */ /* The count of DMA_TCD_NBYTES_MLOFFYES */ #define DMA_TCD_NBYTES_MLOFFYES_COUNT (32U) /*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address Register */ /*! @{ */ #define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) #define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) /*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ #define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) /*! @} */ /* The count of DMA_TCD_SLAST_SDA */ #define DMA_TCD_SLAST_SDA_COUNT (32U) /*! @name TCD_DADDR - TCD Destination Address Register */ /*! @{ */ #define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_TCD_DADDR_DADDR_SHIFT (0U) /*! DADDR - Destination Address */ #define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) /*! @} */ /* The count of DMA_TCD_DADDR */ #define DMA_TCD_DADDR_COUNT (32U) /*! @name TCD_DOFF - TCD Signed Destination Address Offset Register */ /*! @{ */ #define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) #define DMA_TCD_DOFF_DOFF_SHIFT (0U) /*! DOFF - Destination Address Signed Offset */ #define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) /*! @} */ /* The count of DMA_TCD_DOFF */ #define DMA_TCD_DOFF_COUNT (32U) /*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register */ /*! @{ */ #define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) #define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_CITER_ELINKNO */ #define DMA_TCD_CITER_ELINKNO_COUNT (32U) /*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register */ /*! @{ */ #define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x3E00U) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */ #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Minor Loop Link Channel Number */ #define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */ #define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enable channel-to-channel linking on minor-loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_CITER_ELINKYES */ #define DMA_TCD_CITER_ELINKYES_COUNT (32U) /*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address Register */ /*! @{ */ #define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) #define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) /*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ #define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) /*! @} */ /* The count of DMA_TCD_DLAST_SGA */ #define DMA_TCD_DLAST_SGA_COUNT (32U) /*! @name TCD_CSR - TCD Control and Status Register */ /*! @{ */ #define DMA_TCD_CSR_START_MASK (0x1U) #define DMA_TCD_CSR_START_SHIFT (0U) /*! START - Channel Start * 0b0..The channel is not explicitly started. * 0b1..The channel is explicitly started via a software initiated service request. */ #define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) #define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) #define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) /*! INTMAJOR - Enable an interrupt when major iteration count completes. * 0b0..The end-of-major loop interrupt is disabled. * 0b1..The end-of-major loop interrupt is enabled. */ #define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) #define DMA_TCD_CSR_INTHALF_MASK (0x4U) #define DMA_TCD_CSR_INTHALF_SHIFT (2U) /*! INTHALF - Enable an interrupt when major counter is half complete. * 0b0..The half-point interrupt is disabled. * 0b1..The half-point interrupt is enabled. */ #define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) #define DMA_TCD_CSR_DREQ_MASK (0x8U) #define DMA_TCD_CSR_DREQ_SHIFT (3U) /*! DREQ - Disable request * 0b0..No operation * 0b1..Clear the ERQ bit upon major loop completion, thus disabling hardware service requests. */ #define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) #define DMA_TCD_CSR_ESG_MASK (0x10U) #define DMA_TCD_CSR_ESG_SHIFT (4U) /*! ESG - Enable Scatter/Gather processing * 0b0..The current channel's TCD is normal format. * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer * to the next TCD to be loaded into this channel after the major loop completes its execution. */ #define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) #define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) #define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) /*! MAJORELINK - Enable channel-to-channel linking on major loop complete * 0b0..The channel-to-channel linking is disabled. * 0b1..The channel-to-channel linking is enabled. */ #define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) #define DMA_TCD_CSR_EEOP_MASK (0x40U) #define DMA_TCD_CSR_EEOP_SHIFT (6U) /*! EEOP - Enable end-of-packet processing * 0b0..The end-of-packet operation is disabled. * 0b1..The end-of-packet hardware input signal is enabled. */ #define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK) #define DMA_TCD_CSR_ESDA_MASK (0x80U) #define DMA_TCD_CSR_ESDA_SHIFT (7U) /*! ESDA - Enable store destination address * 0b0..The store destination address to system memory operation is disabled. * 0b1..The store destination address to system memory operation is enabled. */ #define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK) #define DMA_TCD_CSR_MAJORLINKCH_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */ #define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) /*! MAJORLINKCH - Major loop link channel number */ #define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */ #define DMA_TCD_CSR_BWC_MASK (0xC000U) #define DMA_TCD_CSR_BWC_SHIFT (14U) /*! BWC - Bandwidth Control * 0b00..No eDMA engine stalls. * 0b01..Reserved * 0b10..eDMA engine stalls for 4 cycles after each R/W. * 0b11..eDMA engine stalls for 8 cycles after each R/W. */ #define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) /*! @} */ /* The count of DMA_TCD_CSR */ #define DMA_TCD_CSR_COUNT (32U) /*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register */ /*! @{ */ #define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) /*! BITER - Starting Major Iteration Count */ #define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) #define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_BITER_ELINKNO */ #define DMA_TCD_BITER_ELINKNO_COUNT (32U) /*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register */ /*! @{ */ #define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) /*! BITER - Starting major iteration count */ #define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x3E00U) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */ #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Link Channel Number */ #define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */ #define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enables channel-to-channel linking on minor loop complete * 0b0..The channel-to-channel linking is disabled * 0b1..The channel-to-channel linking is enabled */ #define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_BITER_ELINKYES */ #define DMA_TCD_BITER_ELINKYES_COUNT (32U) /*! * @} */ /* end of group DMA_Register_Masks */ /* DMA - Peripheral instance base addresses */ /** Peripheral ADMA__EDMA0 base address */ #define ADMA__EDMA0_BASE (0x591F0000u) /** Peripheral ADMA__EDMA0 base pointer */ #define ADMA__EDMA0 ((DMA_Type *)ADMA__EDMA0_BASE) /** Peripheral ADMA__EDMA1 base address */ #define ADMA__EDMA1_BASE (0x599F0000u) /** Peripheral ADMA__EDMA1 base pointer */ #define ADMA__EDMA1 ((DMA_Type *)ADMA__EDMA1_BASE) /** Peripheral ADMA__EDMA2 base address */ #define ADMA__EDMA2_BASE (0x5A1F0000u) /** Peripheral ADMA__EDMA2 base pointer */ #define ADMA__EDMA2 ((DMA_Type *)ADMA__EDMA2_BASE) /** Peripheral ADMA__EDMA3 base address */ #define ADMA__EDMA3_BASE (0x5A9F0000u) /** Peripheral ADMA__EDMA3 base pointer */ #define ADMA__EDMA3 ((DMA_Type *)ADMA__EDMA3_BASE) /** Peripheral CONNECTIVITY__EDMA base address */ #define CONNECTIVITY__EDMA_BASE (0x5B070000u) /** Peripheral CONNECTIVITY__EDMA base pointer */ #define CONNECTIVITY__EDMA ((DMA_Type *)CONNECTIVITY__EDMA_BASE) /** Array initializer of DMA peripheral base addresses */ #define DMA_BASE_ADDRS { ADMA__EDMA0_BASE, ADMA__EDMA1_BASE, ADMA__EDMA2_BASE, ADMA__EDMA3_BASE, CONNECTIVITY__EDMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { ADMA__EDMA0, ADMA__EDMA1, ADMA__EDMA2, ADMA__EDMA3, CONNECTIVITY__EDMA } /** Interrupt vectors for the DMA peripheral type */ #define DMA_IRQS { { ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn }, \ { ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn }, \ { ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn }, \ { ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn }, \ { CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn } } #define DMA_ERROR_IRQS { ADMA_EDMA0_ERR_INT_IRQn, ADMA_EDMA1_ERR_INT_IRQn, ADMA_EDMA2_ERR_INT_IRQn, ADMA_EDMA3_ERR_INT_IRQn, CONNECTIVITY_DMA_ERR_INT_IRQn } /*! * @} */ /* end of group DMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DPR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DPR_Peripheral_Access_Layer DPR Peripheral Access Layer * @{ */ /** DPR - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< System Control 0, offset: 0x0 */ __IO uint32_t SET; /**< System Control 0, offset: 0x4 */ __IO uint32_t CLR; /**< System Control 0, offset: 0x8 */ __IO uint32_t TOG; /**< System Control 0, offset: 0xC */ } SYSTEM_CTRL0; uint8_t RESERVED_0[16]; struct { /* offset: 0x20 */ __IO uint32_t RW; /**< Interrupt Mask, offset: 0x20 */ __IO uint32_t SET; /**< Interrupt Mask, offset: 0x24 */ __IO uint32_t CLR; /**< Interrupt Mask, offset: 0x28 */ __IO uint32_t TOG; /**< Interrupt Mask, offset: 0x2C */ } IRQ_MASK; struct { /* offset: 0x30 */ __I uint32_t RW; /**< Status Register of Masked IRQ, offset: 0x30 */ __I uint32_t SET; /**< Status Register of Masked IRQ, offset: 0x34 */ __I uint32_t CLR; /**< Status Register of Masked IRQ, offset: 0x38 */ __I uint32_t TOG; /**< Status Register of Masked IRQ, offset: 0x3C */ } IRQ_MASK_STATUS; struct { /* offset: 0x40 */ __IO uint32_t RW; /**< Status of Non-Masked IRQ, offset: 0x40 */ __IO uint32_t SET; /**< Status of Non-Masked IRQ, offset: 0x44 */ __IO uint32_t CLR; /**< Status of Non-Masked IRQ, offset: 0x48 */ __IO uint32_t TOG; /**< Status of Non-Masked IRQ, offset: 0x4C */ } IRQ_NONMASK_STATUS; struct { /* offset: 0x50 */ __IO uint32_t RW; /**< Mode Control 0, offset: 0x50 */ __IO uint32_t SET; /**< Mode Control 0, offset: 0x54 */ __IO uint32_t CLR; /**< Mode Control 0, offset: 0x58 */ __IO uint32_t TOG; /**< Mode Control 0, offset: 0x5C */ } MODE_CTRL0; uint8_t RESERVED_1[16]; struct { /* offset: 0x70 */ __IO uint32_t RW; /**< Frame Control 0, offset: 0x70 */ __IO uint32_t SET; /**< Frame Control 0, offset: 0x74 */ __IO uint32_t CLR; /**< Frame Control 0, offset: 0x78 */ __IO uint32_t TOG; /**< Frame Control 0, offset: 0x7C */ } FRAME_CTRL0; uint8_t RESERVED_2[16]; struct { /* offset: 0x90 */ __IO uint32_t RW; /**< Frame 1-Plane Control 0, offset: 0x90 */ __IO uint32_t SET; /**< Frame 1-Plane Control 0, offset: 0x94 */ __IO uint32_t CLR; /**< Frame 1-Plane Control 0, offset: 0x98 */ __IO uint32_t TOG; /**< Frame 1-Plane Control 0, offset: 0x9C */ } FRAME_1P_CTRL0; struct { /* offset: 0xA0 */ __IO uint32_t RW; /**< Frame 1-Plane Pix X Control, offset: 0xA0 */ __IO uint32_t SET; /**< Frame 1-Plane Pix X Control, offset: 0xA4 */ __IO uint32_t CLR; /**< Frame 1-Plane Pix X Control, offset: 0xA8 */ __IO uint32_t TOG; /**< Frame 1-Plane Pix X Control, offset: 0xAC */ } FRAME_1P_PIX_X_CTRL; struct { /* offset: 0xB0 */ __IO uint32_t RW; /**< Frame 1-Plane Pix Y Control, offset: 0xB0 */ __IO uint32_t SET; /**< Frame 1-Plane Pix Y Control, offset: 0xB4 */ __IO uint32_t CLR; /**< Frame 1-Plane Pix Y Control, offset: 0xB8 */ __IO uint32_t TOG; /**< Frame 1-Plane Pix Y Control, offset: 0xBC */ } FRAME_1P_PIX_Y_CTRL; struct { /* offset: 0xC0 */ __IO uint32_t RW; /**< Frame 1-Plane Base Address Control 0, offset: 0xC0 */ __IO uint32_t SET; /**< Frame 1-Plane Base Address Control 0, offset: 0xC4 */ __IO uint32_t CLR; /**< Frame 1-Plane Base Address Control 0, offset: 0xC8 */ __IO uint32_t TOG; /**< Frame 1-Plane Base Address Control 0, offset: 0xCC */ } FRAME_1P_BASE_ADDR_CTRL0; uint8_t RESERVED_3[16]; struct { /* offset: 0xE0 */ __IO uint32_t RW; /**< Frame 2-Plane Control 0, offset: 0xE0 */ __IO uint32_t SET; /**< Frame 2-Plane Control 0, offset: 0xE4 */ __IO uint32_t CLR; /**< Frame 2-Plane Control 0, offset: 0xE8 */ __IO uint32_t TOG; /**< Frame 2-Plane Control 0, offset: 0xEC */ } FRAME_2P_CTRL0; struct { /* offset: 0xF0 */ __IO uint32_t RW; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF0 */ __IO uint32_t SET; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF4 */ __IO uint32_t CLR; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF8 */ __IO uint32_t TOG; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xFC */ } FRAME_PIX_X_ULC_CTRL; struct { /* offset: 0x100 */ __IO uint32_t RW; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x100 */ __IO uint32_t SET; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x104 */ __IO uint32_t CLR; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x108 */ __IO uint32_t TOG; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x10C */ } FRAME_PIX_Y_ULC_CTRL; struct { /* offset: 0x110 */ __IO uint32_t RW; /**< Frame 2-Plane Base Address Control 0, offset: 0x110 */ __IO uint32_t SET; /**< Frame 2-Plane Base Address Control 0, offset: 0x114 */ __IO uint32_t CLR; /**< Frame 2-Plane Base Address Control 0, offset: 0x118 */ __IO uint32_t TOG; /**< Frame 2-Plane Base Address Control 0, offset: 0x11C */ } FRAME_2P_BASE_ADDR_CTRL0; uint8_t RESERVED_4[16]; struct { /* offset: 0x130 */ __IO uint32_t RW; /**< Status Control 0, offset: 0x130 */ __IO uint32_t SET; /**< Status Control 0, offset: 0x134 */ __IO uint32_t CLR; /**< Status Control 0, offset: 0x138 */ __IO uint32_t TOG; /**< Status Control 0, offset: 0x13C */ } STATUS_CTRL0; struct { /* offset: 0x140 */ __I uint32_t RW; /**< Status Control 1, offset: 0x140 */ __I uint32_t SET; /**< Status Control 1, offset: 0x144 */ __I uint32_t CLR; /**< Status Control 1, offset: 0x148 */ __I uint32_t TOG; /**< Status Control 1, offset: 0x14C */ } STATUS_CTRL1; uint8_t RESERVED_5[176]; struct { /* offset: 0x200 */ __IO uint32_t RW; /**< RTRAM Control 0, offset: 0x200 */ __IO uint32_t SET; /**< RTRAM Control 0, offset: 0x204 */ __IO uint32_t CLR; /**< RTRAM Control 0, offset: 0x208 */ __IO uint32_t TOG; /**< RTRAM Control 0, offset: 0x20C */ } RTRAM_CTRL0; } DPR_Type; /* ---------------------------------------------------------------------------- -- DPR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DPR_Register_Masks DPR Register Masks * @{ */ /*! @name SYSTEM_CTRL0 - System Control 0 */ /*! @{ */ #define DPR_SYSTEM_CTRL0_RUN_EN_MASK (0x1U) #define DPR_SYSTEM_CTRL0_RUN_EN_SHIFT (0U) /*! RUN_EN - Run Enable */ #define DPR_SYSTEM_CTRL0_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_RUN_EN_SHIFT)) & DPR_SYSTEM_CTRL0_RUN_EN_MASK) #define DPR_SYSTEM_CTRL0_SOFT_RESET_MASK (0x2U) #define DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT (1U) /*! SOFT_RESET - Soft Reset */ #define DPR_SYSTEM_CTRL0_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT)) & DPR_SYSTEM_CTRL0_SOFT_RESET_MASK) #define DPR_SYSTEM_CTRL0_REPEAT_EN_MASK (0x4U) #define DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT (2U) /*! REPEAT_EN - Repeat Enable */ #define DPR_SYSTEM_CTRL0_REPEAT_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT)) & DPR_SYSTEM_CTRL0_REPEAT_EN_MASK) #define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK (0x8U) #define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT (3U) /*! SHADOW_LOAD_EN - Shadow Load Enable */ #define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT)) & DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK) #define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK (0x10U) #define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT (4U) /*! SW_SHADOW_LOAD_SEL - Software Shadow Load Select */ #define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT)) & DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK) #define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK (0x10000U) #define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT (16U) /*! BCMD2AXI_MSTR_ID_CTRL - Buscmd To AXI Master ID Control */ #define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT)) & DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK) /*! @} */ /*! @name IRQ_MASK - Interrupt Mask */ /*! @{ */ #define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK (0x1U) #define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT (0U) /*! IRQ_DPR_CTRL_DONE - DPR Control Done IRQ Mask */ #define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK) #define DPR_IRQ_MASK_IRQ_DPR_RUN_MASK (0x2U) #define DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT (1U) /*! IRQ_DPR_RUN - DPR Run IRQ Mask */ #define DPR_IRQ_MASK_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_RUN_MASK) #define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK (0x4U) #define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT (2U) /*! IRQ_DPR_SHADOW_LOADED_MASK - DPR Shadow Loaded IRQ Mask */ #define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK) #define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK (0x8U) #define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT (3U) /*! IRQ_AXI_READ_ERROR - AXI Read Error IRQ Mask */ #define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK) #define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) #define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) /*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow IRQ Mask */ #define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK) #define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) #define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) /*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow IRQ Mask */ #define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK) #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer ready IRQ error Mask */ #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer ready IRQ error Mask */ #define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) /*! @} */ /*! @name IRQ_MASK_STATUS - Status Register of Masked IRQ */ /*! @{ */ #define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U) #define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U) /*! IRQ_DPR_CTRL_DONE - DPR Control Done Masked IRQ */ #define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK) #define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK (0x2U) #define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT (1U) /*! IRQ_DPR_RUN - DPR Run Masked IRQ */ #define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK) #define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK (0x4U) #define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT (2U) /*! IRQ_DPR_SHADOW_LOADED - DPR Shadow Loaded Masked IRQ */ #define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK) #define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U) #define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U) /*! IRQ_AXI_READ_ERROR - AXI Read Error Masked IRQ */ #define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK) #define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) #define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) /*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow Masked IRQ */ #define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK) #define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) #define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) /*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow Masked IRQ */ #define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK) #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer error Masked IRQ */ #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer error Masked IRQ */ #define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) /*! @} */ /*! @name IRQ_NONMASK_STATUS - Status of Non-Masked IRQ */ /*! @{ */ #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U) #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U) /*! IRQ_DPR_CTRL_DONE - DPR Control Done Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK) #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK (0x2U) #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT (1U) /*! IRQ_DPR_RUN - DPR Run Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK) #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK (0x4U) #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT (2U) /*! IRQ_DPR_SHADOW_LOADED_NMSTAT - DPR Shadow Loaded Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK) #define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U) #define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U) /*! IRQ_AXI_READ_ERROR - AXI Read Error Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U) /*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U) /*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer ready error Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U) #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U) /*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer ready error Non-Masked IRQ */ #define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK) /*! @} */ /*! @name MODE_CTRL0 - Mode Control 0 */ /*! @{ */ #define DPR_MODE_CTRL0_RTR_3BUF_EN_MASK (0x1U) #define DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT (0U) /*! RTR_3BUF_EN - RTRAM Buffer Implementation */ #define DPR_MODE_CTRL0_RTR_3BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_3BUF_EN_MASK) #define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK (0x2U) #define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT (1U) /*! RTR_4LINE_BUF_EN - RTRAM Lines Per Buffer */ #define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK) #define DPR_MODE_CTRL0_TILE_TYPE_MASK (0xCU) #define DPR_MODE_CTRL0_TILE_TYPE_SHIFT (2U) /*! TILE_TYPE - Tile Type */ #define DPR_MODE_CTRL0_TILE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_TILE_TYPE_SHIFT)) & DPR_MODE_CTRL0_TILE_TYPE_MASK) #define DPR_MODE_CTRL0_YUV_EN_MASK (0x10U) #define DPR_MODE_CTRL0_YUV_EN_SHIFT (4U) /*! YUV_EN - YUV Enable */ #define DPR_MODE_CTRL0_YUV_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_YUV_EN_SHIFT)) & DPR_MODE_CTRL0_YUV_EN_MASK) #define DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK (0x20U) #define DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT (5U) /*! COMP_2PLANE_EN - Component 2-Plane Enable */ #define DPR_MODE_CTRL0_COMP_2PLANE_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT)) & DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK) #define DPR_MODE_CTRL0_PIX_SIZE_MASK (0xC0U) #define DPR_MODE_CTRL0_PIX_SIZE_SHIFT (6U) /*! PIX_SIZE - Pixel Size */ #define DPR_MODE_CTRL0_PIX_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_SIZE_SHIFT)) & DPR_MODE_CTRL0_PIX_SIZE_MASK) #define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK (0x100U) #define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT (8U) /*! PIX_LUMA_UV_SWAP - Pixel luma/UV position Swap */ #define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK) #define DPR_MODE_CTRL0_PIX_UV_SWAP_MASK (0x200U) #define DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT (9U) /*! PIX_UV_SWAP - Pixel UV Swap */ #define DPR_MODE_CTRL0_PIX_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_UV_SWAP_MASK) #define DPR_MODE_CTRL0_B_COMP_SEL_MASK (0xC00U) #define DPR_MODE_CTRL0_B_COMP_SEL_SHIFT (10U) /*! B_COMP_SEL - B Component Select */ #define DPR_MODE_CTRL0_B_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_B_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_B_COMP_SEL_MASK) #define DPR_MODE_CTRL0_G_COMP_SEL_MASK (0x3000U) #define DPR_MODE_CTRL0_G_COMP_SEL_SHIFT (12U) /*! G_COMP_SEL - G Component Select */ #define DPR_MODE_CTRL0_G_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_G_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_G_COMP_SEL_MASK) #define DPR_MODE_CTRL0_R_COMP_SEL_MASK (0xC000U) #define DPR_MODE_CTRL0_R_COMP_SEL_SHIFT (14U) /*! R_COMP_SEL - R Component Select */ #define DPR_MODE_CTRL0_R_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_R_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_R_COMP_SEL_MASK) #define DPR_MODE_CTRL0_A_COMP_SEL_MASK (0x30000U) #define DPR_MODE_CTRL0_A_COMP_SEL_SHIFT (16U) /*! A_COMP_SEL - A Component Select */ #define DPR_MODE_CTRL0_A_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_A_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_A_COMP_SEL_MASK) /*! @} */ /*! @name FRAME_CTRL0 - Frame Control 0 */ /*! @{ */ #define DPR_FRAME_CTRL0_HFLIP_EN_MASK (0x1U) #define DPR_FRAME_CTRL0_HFLIP_EN_SHIFT (0U) /*! HFLIP_EN - Horizontal Flip Enable */ #define DPR_FRAME_CTRL0_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_HFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_HFLIP_EN_MASK) #define DPR_FRAME_CTRL0_VFLIP_EN_MASK (0x2U) #define DPR_FRAME_CTRL0_VFLIP_EN_SHIFT (1U) /*! VFLIP_EN - Vertical Flip Enable */ #define DPR_FRAME_CTRL0_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_VFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_VFLIP_EN_MASK) #define DPR_FRAME_CTRL0_ROT_ENC_MASK (0xCU) #define DPR_FRAME_CTRL0_ROT_ENC_SHIFT (2U) /*! ROT_ENC - Encoded Rotation */ #define DPR_FRAME_CTRL0_ROT_ENC(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_ENC_SHIFT)) & DPR_FRAME_CTRL0_ROT_ENC_MASK) #define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK (0x10U) #define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT (4U) /*! ROT_FLIP_ORDER_EN - Rotation Flip Order */ #define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT)) & DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK) #define DPR_FRAME_CTRL0_PITCH_MASK (0xFFFF0000U) #define DPR_FRAME_CTRL0_PITCH_SHIFT (16U) /*! PITCH - Image Pitch */ #define DPR_FRAME_CTRL0_PITCH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_PITCH_SHIFT)) & DPR_FRAME_CTRL0_PITCH_MASK) /*! @} */ /*! @name FRAME_1P_CTRL0 - Frame 1-Plane Control 0 */ /*! @{ */ #define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U) #define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U) /*! MAX_BYTES_PREQ - Max Bytes Per Request */ #define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK) /*! @} */ /*! @name FRAME_1P_PIX_X_CTRL - Frame 1-Plane Pix X Control */ /*! @{ */ #define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK (0xFFFFU) #define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT (0U) /*! NUM_X_PIX_WIDE - Number of Pixels Wide in X-direction */ #define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT)) & DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK) /*! @} */ /*! @name FRAME_1P_PIX_Y_CTRL - Frame 1-Plane Pix Y Control */ /*! @{ */ #define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK (0xFFFFU) #define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT (0U) /*! NUM_Y_PIX_HIGH - Number of Pixels High in Y-direction */ #define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT)) & DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK) /*! @} */ /*! @name FRAME_1P_BASE_ADDR_CTRL0 - Frame 1-Plane Base Address Control 0 */ /*! @{ */ #define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU) #define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U) /*! BASE_ADDR - Base Address */ #define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK) /*! @} */ /*! @name FRAME_2P_CTRL0 - Frame 2-Plane Control 0 */ /*! @{ */ #define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U) #define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U) /*! MAX_BYTES_PREQ - Max Bytes Per Request */ #define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK) /*! @} */ /*! @name FRAME_PIX_X_ULC_CTRL - Frame Pixel X Upper Left Coordinate Control */ /*! @{ */ #define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_MASK (0xFFFFU) #define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_SHIFT (0U) /*! CROP_ULC_X - Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma) */ #define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_SHIFT)) & DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_MASK) /*! @} */ /*! @name FRAME_PIX_Y_ULC_CTRL - Frame Pixel Y Upper Left Coordinate Control */ /*! @{ */ #define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_MASK (0xFFFFU) #define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_SHIFT (0U) /*! CROP_ULC_y - Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma) */ #define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_SHIFT)) & DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_MASK) /*! @} */ /*! @name FRAME_2P_BASE_ADDR_CTRL0 - Frame 2-Plane Base Address Control 0 */ /*! @{ */ #define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU) #define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U) /*! BASE_ADDR - Base Address */ #define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK) /*! @} */ /*! @name STATUS_CTRL0 - Status Control 0 */ /*! @{ */ #define DPR_STATUS_CTRL0_STATUS_MUX_SEL_MASK (0x7U) #define DPR_STATUS_CTRL0_STATUS_MUX_SEL_SHIFT (0U) /*! STATUS_MUX_SEL - Status Mux Select */ #define DPR_STATUS_CTRL0_STATUS_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL0_STATUS_MUX_SEL_SHIFT)) & DPR_STATUS_CTRL0_STATUS_MUX_SEL_MASK) #define DPR_STATUS_CTRL0_STATUS_SRC_SEL_MASK (0x70000U) #define DPR_STATUS_CTRL0_STATUS_SRC_SEL_SHIFT (16U) /*! STATUS_SRC_SEL - Status Source Select */ #define DPR_STATUS_CTRL0_STATUS_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL0_STATUS_SRC_SEL_SHIFT)) & DPR_STATUS_CTRL0_STATUS_SRC_SEL_MASK) /*! @} */ /*! @name STATUS_CTRL1 - Status Control 1 */ /*! @{ */ #define DPR_STATUS_CTRL1_STATUS_MASK (0xFFFFFFFFU) #define DPR_STATUS_CTRL1_STATUS_SHIFT (0U) /*! STATUS - Status Register */ #define DPR_STATUS_CTRL1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL1_STATUS_SHIFT)) & DPR_STATUS_CTRL1_STATUS_MASK) /*! @} */ /*! @name RTRAM_CTRL0 - RTRAM Control 0 */ /*! @{ */ #define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK (0x1U) #define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT (0U) /*! NUM_ROWS_ACTIVE - Number of Rows Active */ #define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT)) & DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK) #define DPR_RTRAM_CTRL0_THRES_HIGH_MASK (0xEU) #define DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT (1U) /*! THRES_HIGH - Threshold High */ #define DPR_RTRAM_CTRL0_THRES_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT)) & DPR_RTRAM_CTRL0_THRES_HIGH_MASK) #define DPR_RTRAM_CTRL0_THRES_LOW_MASK (0x70U) #define DPR_RTRAM_CTRL0_THRES_LOW_SHIFT (4U) /*! THRES_LOW - Threshold Low */ #define DPR_RTRAM_CTRL0_THRES_LOW(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_LOW_SHIFT)) & DPR_RTRAM_CTRL0_THRES_LOW_MASK) #define DPR_RTRAM_CTRL0_ABORT_SEL_MASK (0x80U) #define DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT (7U) /*! ABORT_SEL - Abort Select */ #define DPR_RTRAM_CTRL0_ABORT_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT)) & DPR_RTRAM_CTRL0_ABORT_SEL_MASK) /*! @} */ /*! * @} */ /* end of group DPR_Register_Masks */ /* DPR - Peripheral instance base addresses */ /** Peripheral DC__DPR0 base address */ #define DC__DPR0_BASE (0x560D0000u) /** Peripheral DC__DPR0 base pointer */ #define DC__DPR0 ((DPR_Type *)DC__DPR0_BASE) /** Peripheral DC__DPR1 base address */ #define DC__DPR1_BASE (0x56100000u) /** Peripheral DC__DPR1 base pointer */ #define DC__DPR1 ((DPR_Type *)DC__DPR1_BASE) /** Array initializer of DPR peripheral base addresses */ #define DPR_BASE_ADDRS { DC__DPR0_BASE, DC__DPR1_BASE } /** Array initializer of DPR peripheral base pointers */ #define DPR_BASE_PTRS { DC__DPR0, DC__DPR1 } /* Backward compatibility */ /** Peripheral DC__DPR0_CH0 base address */ #define DC__DPR0_CH0_BASE DC__DPR0_BASE /** Peripheral DC__DPR0_CH0 base pointer */ #define DC__DPR0_CH0 ((DPR_Type *)DC__DPR0_CH0_BASE) /** Peripheral DC__DPR0_CH1 base address */ #define DC__DPR0_CH1_BASE (0x560E0000u) /** Peripheral DC__DPR0_CH1 base pointer */ #define DC__DPR0_CH1 ((DPR_Type *)DC__DPR0_CH1_BASE) /** Peripheral DC__DPR0_CH2 base address */ #define DC__DPR0_CH2_BASE (0x560F0000u) /** Peripheral DC__DPR0_CH2 base pointer */ #define DC__DPR0_CH2 ((DPR_Type *)DC__DPR0_CH2_BASE) /** Peripheral DC__DPR1_CH0 base address */ #define DC__DPR1_CH0_BASE DC__DPR1_BASE /** Peripheral DC__DPR1_CH0 base pointer */ #define DC__DPR1_CH0 ((DPR_Type *)DC__DPR1_CH0_BASE) /** Peripheral DC__DPR1_CH1 base address */ #define DC__DPR1_CH1_BASE (0x56110000u) /** Peripheral DC__DPR1_CH1 base pointer */ #define DC__DPR1_CH1 ((DPR_Type *)DC__DPR1_CH1_BASE) /** Peripheral DC__DPR1_CH2 base address */ #define DC__DPR1_CH2_BASE (0x56120000u) /** Peripheral DC__DPR1_CH2 base pointer */ #define DC__DPR1_CH2 ((DPR_Type *)DC__DPR1_CH2_BASE) /** Array initializer of DPR peripheral base addresses */ #define DPR_CH_BASE_ADDRS { DC__DPR0_CH0_BASE, DC__DPR0_CH1_BASE, DC__DPR0_CH2_BASE, DC__DPR1_CH0_BASE, DC__DPR1_CH1_BASE, DC__DPR1_CH2_BASE } /** Array initializer of DPR peripheral base pointers */ #define DPR_CH_BASE_PTRS { DC__DPR0_CH0, DC__DPR0_CH1, DC__DPR0_CH2, DC__DPR1_CH0, DC__DPR1_CH1, DC__DPR1_CH2 } /*! * @} */ /* end of group DPR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer * @{ */ /** ENET - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */ __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */ uint8_t RESERVED_2[12]; __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ uint8_t RESERVED_3[24]; __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ uint8_t RESERVED_4[28]; __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ uint8_t RESERVED_5[28]; __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ uint8_t RESERVED_6[60]; __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ uint8_t RESERVED_7[28]; __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */ uint8_t RESERVED_8[4]; __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_9[12]; __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ uint8_t RESERVED_10[28]; __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ uint8_t RESERVED_11[24]; __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */ __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */ __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */ __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */ __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */ __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */ uint8_t RESERVED_12[8]; __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */ __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */ __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */ uint8_t RESERVED_13[4]; __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ uint8_t RESERVED_14[12]; __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */ uint8_t RESERVED_15[8]; __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */ __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */ __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */ __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */ __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */ __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */ uint8_t RESERVED_16[12]; uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ uint8_t RESERVED_17[12]; __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ uint8_t RESERVED_18[284]; __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ uint8_t RESERVED_19[356]; __IO uint32_t MDATA; /**< Pattern Match Data Register, offset: 0x580 */ __IO uint32_t MMASK; /**< Match Entry Mask Register, offset: 0x584 */ __IO uint32_t MCONFIG; /**< Match Entry Rules Configuration Register, offset: 0x588 */ __IO uint32_t MENTRYRW; /**< Match Entry Read/Write Command Register, offset: 0x58C */ __IO uint32_t RXPCTL; /**< Receive Parser Control Register, offset: 0x590 */ __IO uint32_t MAXFRMOFF; /**< Maximum Frame Offset, offset: 0x594 */ __I uint32_t RXPARST; /**< Receive Parser Status, offset: 0x598 */ uint8_t RESERVED_20[4]; __I uint32_t PARSDSCD; /**< Parser Discard Count, offset: 0x5A0 */ __I uint32_t PRSACPT0; /**< Parser Accept Count 0, offset: 0x5A4 */ __I uint32_t PRSRJCT0; /**< Parser Reject Count 0, offset: 0x5A8 */ __I uint32_t PRSACPT1; /**< Parser Accept Count 1, offset: 0x5AC */ __I uint32_t PRSRJCT1; /**< Parser Reject Count 1, offset: 0x5B0 */ __I uint32_t PRSACPT2; /**< Parser Accept Count 2, offset: 0x5B4 */ __I uint32_t PRSRJCT2; /**< Parser Reject Count 2, offset: 0x5B8 */ uint8_t RESERVED_21[72]; __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ struct { /* offset: 0x608, array step: 0x8 */ __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ } CHANNEL[4]; } ENET_Type; /* ---------------------------------------------------------------------------- -- ENET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Register_Masks ENET Register Masks * @{ */ /*! @name EIR - Interrupt Event Register */ /*! @{ */ #define ENET_EIR_RXB1_MASK (0x1U) #define ENET_EIR_RXB1_SHIFT (0U) /*! RXB1 - Receive buffer interrupt, class 1 */ #define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK) #define ENET_EIR_RXF1_MASK (0x2U) #define ENET_EIR_RXF1_SHIFT (1U) /*! RXF1 - Receive frame interrupt, class 1 */ #define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK) #define ENET_EIR_TXB1_MASK (0x4U) #define ENET_EIR_TXB1_SHIFT (2U) /*! TXB1 - Transmit buffer interrupt, class 1 */ #define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK) #define ENET_EIR_TXF1_MASK (0x8U) #define ENET_EIR_TXF1_SHIFT (3U) /*! TXF1 - Transmit frame interrupt, class 1 */ #define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK) #define ENET_EIR_RXB2_MASK (0x10U) #define ENET_EIR_RXB2_SHIFT (4U) /*! RXB2 - Receive buffer interrupt, class 2 */ #define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK) #define ENET_EIR_RXF2_MASK (0x20U) #define ENET_EIR_RXF2_SHIFT (5U) /*! RXF2 - Receive frame interrupt, class 2 */ #define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK) #define ENET_EIR_TXB2_MASK (0x40U) #define ENET_EIR_TXB2_SHIFT (6U) /*! TXB2 - Transmit buffer interrupt, class 2 */ #define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK) #define ENET_EIR_TXF2_MASK (0x80U) #define ENET_EIR_TXF2_SHIFT (7U) /*! TXF2 - Transmit frame interrupt, class 2 */ #define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK) #define ENET_EIR_PARSRF_MASK (0x200U) #define ENET_EIR_PARSRF_SHIFT (9U) #define ENET_EIR_PARSRF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PARSRF_SHIFT)) & ENET_EIR_PARSRF_MASK) #define ENET_EIR_PARSERR_MASK (0x400U) #define ENET_EIR_PARSERR_SHIFT (10U) #define ENET_EIR_PARSERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PARSERR_SHIFT)) & ENET_EIR_PARSERR_MASK) #define ENET_EIR_RXFLUSH_0_MASK (0x1000U) #define ENET_EIR_RXFLUSH_0_SHIFT (12U) #define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK) #define ENET_EIR_RXFLUSH_1_MASK (0x2000U) #define ENET_EIR_RXFLUSH_1_SHIFT (13U) #define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK) #define ENET_EIR_RXFLUSH_2_MASK (0x4000U) #define ENET_EIR_RXFLUSH_2_SHIFT (14U) #define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK) #define ENET_EIR_TS_TIMER_MASK (0x8000U) #define ENET_EIR_TS_TIMER_SHIFT (15U) /*! TS_TIMER - Timestamp Timer */ #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) #define ENET_EIR_TS_AVAIL_MASK (0x10000U) #define ENET_EIR_TS_AVAIL_SHIFT (16U) /*! TS_AVAIL - Transmit Timestamp Available */ #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) #define ENET_EIR_WAKEUP_MASK (0x20000U) #define ENET_EIR_WAKEUP_SHIFT (17U) /*! WAKEUP - Node Wakeup Request Indication */ #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) #define ENET_EIR_PLR_MASK (0x40000U) #define ENET_EIR_PLR_SHIFT (18U) /*! PLR - Payload Receive Error */ #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) #define ENET_EIR_UN_MASK (0x80000U) #define ENET_EIR_UN_SHIFT (19U) /*! UN - Transmit FIFO Underrun */ #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) #define ENET_EIR_RL_MASK (0x100000U) #define ENET_EIR_RL_SHIFT (20U) /*! RL - Collision Retry Limit */ #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) #define ENET_EIR_LC_MASK (0x200000U) #define ENET_EIR_LC_SHIFT (21U) /*! LC - Late Collision */ #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) #define ENET_EIR_EBERR_MASK (0x400000U) #define ENET_EIR_EBERR_SHIFT (22U) /*! EBERR - Ethernet Bus Error */ #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) #define ENET_EIR_MII_MASK (0x800000U) #define ENET_EIR_MII_SHIFT (23U) /*! MII - MII Interrupt. */ #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) #define ENET_EIR_RXB_MASK (0x1000000U) #define ENET_EIR_RXB_SHIFT (24U) /*! RXB - Receive Buffer Interrupt */ #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) #define ENET_EIR_RXF_MASK (0x2000000U) #define ENET_EIR_RXF_SHIFT (25U) /*! RXF - Receive Frame Interrupt */ #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) #define ENET_EIR_TXB_MASK (0x4000000U) #define ENET_EIR_TXB_SHIFT (26U) /*! TXB - Transmit Buffer Interrupt */ #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) #define ENET_EIR_TXF_MASK (0x8000000U) #define ENET_EIR_TXF_SHIFT (27U) /*! TXF - Transmit Frame Interrupt */ #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) #define ENET_EIR_GRA_MASK (0x10000000U) #define ENET_EIR_GRA_SHIFT (28U) /*! GRA - Graceful Stop Complete */ #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) #define ENET_EIR_BABT_MASK (0x20000000U) #define ENET_EIR_BABT_SHIFT (29U) /*! BABT - Babbling Transmit Error */ #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) #define ENET_EIR_BABR_MASK (0x40000000U) #define ENET_EIR_BABR_SHIFT (30U) /*! BABR - Babbling Receive Error */ #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) /*! @} */ /*! @name EIMR - Interrupt Mask Register */ /*! @{ */ #define ENET_EIMR_RXB1_MASK (0x1U) #define ENET_EIMR_RXB1_SHIFT (0U) /*! RXB1 - Receive buffer interrupt, class 1 */ #define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK) #define ENET_EIMR_RXF1_MASK (0x2U) #define ENET_EIMR_RXF1_SHIFT (1U) /*! RXF1 - Receive frame interrupt, class 1 */ #define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK) #define ENET_EIMR_TXB1_MASK (0x4U) #define ENET_EIMR_TXB1_SHIFT (2U) /*! TXB1 - Transmit buffer interrupt, class 1 */ #define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK) #define ENET_EIMR_TXF1_MASK (0x8U) #define ENET_EIMR_TXF1_SHIFT (3U) /*! TXF1 - Transmit frame interrupt, class 1 */ #define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK) #define ENET_EIMR_RXB2_MASK (0x10U) #define ENET_EIMR_RXB2_SHIFT (4U) /*! RXB2 - Receive buffer interrupt, class 2 */ #define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK) #define ENET_EIMR_RXF2_MASK (0x20U) #define ENET_EIMR_RXF2_SHIFT (5U) /*! RXF2 - Receive frame interrupt, class 2 */ #define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK) #define ENET_EIMR_TXB2_MASK (0x40U) #define ENET_EIMR_TXB2_SHIFT (6U) /*! TXB2 - Transmit buffer interrupt, class 2 */ #define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK) #define ENET_EIMR_TXF2_MASK (0x80U) #define ENET_EIMR_TXF2_SHIFT (7U) /*! TXF2 - Transmit frame interrupt, class 2 */ #define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK) #define ENET_EIMR_PARSRF_MASK (0x200U) #define ENET_EIMR_PARSRF_SHIFT (9U) #define ENET_EIMR_PARSRF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PARSRF_SHIFT)) & ENET_EIMR_PARSRF_MASK) #define ENET_EIMR_PARSERR_MASK (0x400U) #define ENET_EIMR_PARSERR_SHIFT (10U) #define ENET_EIMR_PARSERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PARSERR_SHIFT)) & ENET_EIMR_PARSERR_MASK) #define ENET_EIMR_RXFLUSH_0_MASK (0x1000U) #define ENET_EIMR_RXFLUSH_0_SHIFT (12U) #define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK) #define ENET_EIMR_RXFLUSH_1_MASK (0x2000U) #define ENET_EIMR_RXFLUSH_1_SHIFT (13U) #define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK) #define ENET_EIMR_RXFLUSH_2_MASK (0x4000U) #define ENET_EIMR_RXFLUSH_2_SHIFT (14U) #define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK) #define ENET_EIMR_TS_TIMER_MASK (0x8000U) #define ENET_EIMR_TS_TIMER_SHIFT (15U) /*! TS_TIMER - TS_TIMER Interrupt Mask */ #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) #define ENET_EIMR_TS_AVAIL_MASK (0x10000U) #define ENET_EIMR_TS_AVAIL_SHIFT (16U) /*! TS_AVAIL - TS_AVAIL Interrupt Mask */ #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) #define ENET_EIMR_WAKEUP_MASK (0x20000U) #define ENET_EIMR_WAKEUP_SHIFT (17U) /*! WAKEUP - WAKEUP Interrupt Mask */ #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) #define ENET_EIMR_PLR_MASK (0x40000U) #define ENET_EIMR_PLR_SHIFT (18U) /*! PLR - PLR Interrupt Mask */ #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) #define ENET_EIMR_UN_MASK (0x80000U) #define ENET_EIMR_UN_SHIFT (19U) /*! UN - UN Interrupt Mask */ #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) #define ENET_EIMR_RL_MASK (0x100000U) #define ENET_EIMR_RL_SHIFT (20U) /*! RL - RL Interrupt Mask */ #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) #define ENET_EIMR_LC_MASK (0x200000U) #define ENET_EIMR_LC_SHIFT (21U) /*! LC - LC Interrupt Mask */ #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) #define ENET_EIMR_EBERR_MASK (0x400000U) #define ENET_EIMR_EBERR_SHIFT (22U) /*! EBERR - EBERR Interrupt Mask */ #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) #define ENET_EIMR_MII_MASK (0x800000U) #define ENET_EIMR_MII_SHIFT (23U) /*! MII - MII Interrupt Mask */ #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) #define ENET_EIMR_RXB_MASK (0x1000000U) #define ENET_EIMR_RXB_SHIFT (24U) /*! RXB - RXB Interrupt Mask */ #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) #define ENET_EIMR_RXF_MASK (0x2000000U) #define ENET_EIMR_RXF_SHIFT (25U) /*! RXF - RXF Interrupt Mask */ #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) #define ENET_EIMR_TXB_MASK (0x4000000U) #define ENET_EIMR_TXB_SHIFT (26U) /*! TXB - TXB Interrupt Mask * 0b0..The corresponding interrupt source is masked. * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) #define ENET_EIMR_TXF_MASK (0x8000000U) #define ENET_EIMR_TXF_SHIFT (27U) /*! TXF - TXF Interrupt Mask * 0b0..The corresponding interrupt source is masked. * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) #define ENET_EIMR_GRA_MASK (0x10000000U) #define ENET_EIMR_GRA_SHIFT (28U) /*! GRA - GRA Interrupt Mask * 0b0..The corresponding interrupt source is masked. * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) #define ENET_EIMR_BABT_MASK (0x20000000U) #define ENET_EIMR_BABT_SHIFT (29U) /*! BABT - BABT Interrupt Mask * 0b0..The corresponding interrupt source is masked. * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) #define ENET_EIMR_BABR_MASK (0x40000000U) #define ENET_EIMR_BABR_SHIFT (30U) /*! BABR - BABR Interrupt Mask * 0b0..The corresponding interrupt source is masked. * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) /*! @} */ /*! @name RDAR - Receive Descriptor Active Register - Ring 0 */ /*! @{ */ #define ENET_RDAR_RDAR_MASK (0x1000000U) #define ENET_RDAR_RDAR_SHIFT (24U) /*! RDAR - Receive Descriptor Active */ #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) /*! @} */ /*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */ /*! @{ */ #define ENET_TDAR_TDAR_MASK (0x1000000U) #define ENET_TDAR_TDAR_SHIFT (24U) /*! TDAR - Transmit Descriptor Active */ #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) /*! @} */ /*! @name ECR - Ethernet Control Register */ /*! @{ */ #define ENET_ECR_RESET_MASK (0x1U) #define ENET_ECR_RESET_SHIFT (0U) /*! RESET - Ethernet MAC Reset */ #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) #define ENET_ECR_ETHEREN_MASK (0x2U) #define ENET_ECR_ETHEREN_SHIFT (1U) /*! ETHEREN - Ethernet Enable * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. * 0b1..MAC is enabled, and reception and transmission are possible. */ #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) #define ENET_ECR_MAGICEN_MASK (0x4U) #define ENET_ECR_MAGICEN_SHIFT (2U) /*! MAGICEN - Magic Packet Detection Enable * 0b0..Magic detection logic disabled. * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. */ #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) #define ENET_ECR_SLEEP_MASK (0x8U) #define ENET_ECR_SLEEP_SHIFT (3U) /*! SLEEP - Sleep Mode Enable * 0b0..Normal operating mode. * 0b1..Sleep mode. */ #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) #define ENET_ECR_EN1588_MASK (0x10U) #define ENET_ECR_EN1588_SHIFT (4U) /*! EN1588 - EN1588 Enable * 0b0..Legacy FEC buffer descriptors and functions enabled. * 0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588. */ #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) #define ENET_ECR_SPEED_MASK (0x20U) #define ENET_ECR_SPEED_SHIFT (5U) /*! SPEED * 0b0..10/100-Mbit/s mode * 0b1..1000-Mbit/s mode */ #define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK) #define ENET_ECR_DBGEN_MASK (0x40U) #define ENET_ECR_DBGEN_SHIFT (6U) /*! DBGEN - Debug Enable * 0b0..MAC continues operation in debug mode. * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. */ #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) #define ENET_ECR_DBSWP_MASK (0x100U) #define ENET_ECR_DBSWP_SHIFT (8U) /*! DBSWP - Descriptor Byte Swapping Enable * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. */ #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) #define ENET_ECR_SVLANEN_MASK (0x200U) #define ENET_ECR_SVLANEN_SHIFT (9U) /*! SVLANEN - S-VLAN enable * 0b0..Only the EtherType 0x8100 will be considered for VLAN detection. * 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in * receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the * classification match comparators, RCMRn. */ #define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK) #define ENET_ECR_VLANUSE2ND_MASK (0x400U) #define ENET_ECR_VLANUSE2ND_SHIFT (10U) /*! VLANUSE2ND - VLAN use second tag * 0b0..Always extract data from the first VLAN tag if it exists. * 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A * double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The * second tag must be a C-VLAN */ #define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK) #define ENET_ECR_SVLANDBL_MASK (0x800U) #define ENET_ECR_SVLANDBL_SHIFT (11U) /*! SVLANDBL - S-VLAN double tag */ #define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK) #define ENET_ECR_TXC_DLY_MASK (0x10000U) #define ENET_ECR_TXC_DLY_SHIFT (16U) /*! TXC_DLY - Transmit clock delay * 0b0..RGMII_TXC is not delayed. * 0b1..Generate delayed version of RGMII_TXC. */ #define ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK) #define ENET_ECR_RXC_DLY_MASK (0x20000U) #define ENET_ECR_RXC_DLY_SHIFT (17U) /*! RXC_DLY - Receive clock delay * 0b0..Use non-delayed version of RGMII_RXC. * 0b1..Use delayed version of RGMII_RXC. */ #define ENET_ECR_RXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RXC_DLY_SHIFT)) & ENET_ECR_RXC_DLY_MASK) /*! @} */ /*! @name MMFR - MII Management Frame Register */ /*! @{ */ #define ENET_MMFR_DATA_MASK (0xFFFFU) #define ENET_MMFR_DATA_SHIFT (0U) /*! DATA - Management Frame Data */ #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) #define ENET_MMFR_TA_MASK (0x30000U) #define ENET_MMFR_TA_SHIFT (16U) /*! TA - Turn Around */ #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) #define ENET_MMFR_RA_MASK (0x7C0000U) #define ENET_MMFR_RA_SHIFT (18U) /*! RA - Register Address */ #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) #define ENET_MMFR_PA_MASK (0xF800000U) #define ENET_MMFR_PA_SHIFT (23U) /*! PA - PHY Address */ #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) #define ENET_MMFR_OP_MASK (0x30000000U) #define ENET_MMFR_OP_SHIFT (28U) /*! OP - Operation Code */ #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) #define ENET_MMFR_ST_MASK (0xC0000000U) #define ENET_MMFR_ST_SHIFT (30U) /*! ST - Start Of Frame Delimiter */ #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) /*! @} */ /*! @name MSCR - MII Speed Control Register */ /*! @{ */ #define ENET_MSCR_MII_SPEED_MASK (0x7EU) #define ENET_MSCR_MII_SPEED_SHIFT (1U) /*! MII_SPEED - MII Speed */ #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) #define ENET_MSCR_DIS_PRE_MASK (0x80U) #define ENET_MSCR_DIS_PRE_SHIFT (7U) /*! DIS_PRE - Disable Preamble * 0b0..Preamble enabled. * 0b1..Preamble (32 ones) is not prepended to the MII management frame. */ #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) #define ENET_MSCR_HOLDTIME_MASK (0x700U) #define ENET_MSCR_HOLDTIME_SHIFT (8U) /*! HOLDTIME - Hold time On MDIO Output * 0b000..1 internal module clock cycle * 0b001..2 internal module clock cycles * 0b010..3 internal module clock cycles * 0b111..8 internal module clock cycles */ #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) /*! @} */ /*! @name MIBC - MIB Control Register */ /*! @{ */ #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) /*! MIB_CLEAR - MIB Clear * 0b0..See note above. * 0b1..All statistics counters are reset to 0. */ #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) #define ENET_MIBC_MIB_IDLE_SHIFT (30U) /*! MIB_IDLE - MIB Idle * 0b0..The MIB block is updating MIB counters. * 0b1..The MIB block is not currently updating any MIB counters. */ #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) #define ENET_MIBC_MIB_DIS_SHIFT (31U) /*! MIB_DIS - Disable MIB Logic * 0b0..MIB logic is enabled. * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. */ #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) /*! @} */ /*! @name RCR - Receive Control Register */ /*! @{ */ #define ENET_RCR_LOOP_MASK (0x1U) #define ENET_RCR_LOOP_SHIFT (0U) /*! LOOP - Internal Loopback * 0b0..Loopback disabled. * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. */ #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) #define ENET_RCR_DRT_MASK (0x2U) #define ENET_RCR_DRT_SHIFT (1U) /*! DRT - Disable Receive On Transmit * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) */ #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) #define ENET_RCR_MII_MODE_MASK (0x4U) #define ENET_RCR_MII_MODE_SHIFT (2U) /*! MII_MODE - Media Independent Interface Mode * 0b0..Reserved. * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. */ #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) #define ENET_RCR_PROM_MASK (0x8U) #define ENET_RCR_PROM_SHIFT (3U) /*! PROM - Promiscuous Mode * 0b0..Disabled. * 0b1..Enabled. */ #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) #define ENET_RCR_BC_REJ_MASK (0x10U) #define ENET_RCR_BC_REJ_SHIFT (4U) /*! BC_REJ - Broadcast Frame Reject */ #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) #define ENET_RCR_FCE_MASK (0x20U) #define ENET_RCR_FCE_SHIFT (5U) /*! FCE - Flow Control Enable */ #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) #define ENET_RCR_RGMII_EN_MASK (0x40U) #define ENET_RCR_RGMII_EN_SHIFT (6U) /*! RGMII_EN - RGMII Mode Enable * 0b0..MAC configured for non-RGMII operation * 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If * ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode. */ #define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK) #define ENET_RCR_RMII_MODE_MASK (0x100U) #define ENET_RCR_RMII_MODE_SHIFT (8U) /*! RMII_MODE - RMII Mode Enable * 0b0..MAC configured for MII mode. * 0b1..MAC configured for RMII operation. */ #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) #define ENET_RCR_RMII_10T_MASK (0x200U) #define ENET_RCR_RMII_10T_SHIFT (9U) /*! RMII_10T * 0b0..100-Mbit/s operation. * 0b1..10-Mbit/s operation. */ #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) #define ENET_RCR_PADEN_MASK (0x1000U) #define ENET_RCR_PADEN_SHIFT (12U) /*! PADEN - Enable Frame Padding Remove On Receive * 0b0..No padding is removed on receive by the MAC. * 0b1..Padding is removed from received frames. */ #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) #define ENET_RCR_PAUFWD_MASK (0x2000U) #define ENET_RCR_PAUFWD_SHIFT (13U) /*! PAUFWD - Terminate/Forward Pause Frames * 0b0..Pause frames are terminated and discarded in the MAC. * 0b1..Pause frames are forwarded to the user application. */ #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) #define ENET_RCR_CRCFWD_MASK (0x4000U) #define ENET_RCR_CRCFWD_SHIFT (14U) /*! CRCFWD - Terminate/Forward Received CRC * 0b0..The CRC field of received frames is transmitted to the user application. * 0b1..The CRC field is stripped from the frame. */ #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) #define ENET_RCR_CFEN_MASK (0x8000U) #define ENET_RCR_CFEN_SHIFT (15U) /*! CFEN - MAC Control Frame Enable * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. */ #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) #define ENET_RCR_MAX_FL_SHIFT (16U) /*! MAX_FL - Maximum Frame Length */ #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) #define ENET_RCR_NLC_MASK (0x40000000U) #define ENET_RCR_NLC_SHIFT (30U) /*! NLC - Payload Length Check Disable * 0b0..The payload length check is disabled. * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. */ #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) #define ENET_RCR_GRS_MASK (0x80000000U) #define ENET_RCR_GRS_SHIFT (31U) /*! GRS - Graceful Receive Stopped */ #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) /*! @} */ /*! @name TCR - Transmit Control Register */ /*! @{ */ #define ENET_TCR_GTS_MASK (0x1U) #define ENET_TCR_GTS_SHIFT (0U) /*! GTS - Graceful Transmit Stop */ #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) #define ENET_TCR_FDEN_MASK (0x4U) #define ENET_TCR_FDEN_SHIFT (2U) /*! FDEN - Full-Duplex Enable */ #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) #define ENET_TCR_TFC_PAUSE_MASK (0x8U) #define ENET_TCR_TFC_PAUSE_SHIFT (3U) /*! TFC_PAUSE - Transmit Frame Control Pause * 0b0..No PAUSE frame transmitted. * 0b1..The MAC stops transmission of data frames after the current transmission is complete. */ #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) #define ENET_TCR_RFC_PAUSE_MASK (0x10U) #define ENET_TCR_RFC_PAUSE_SHIFT (4U) /*! RFC_PAUSE - Receive Frame Control Pause */ #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) #define ENET_TCR_ADDSEL_MASK (0xE0U) #define ENET_TCR_ADDSEL_SHIFT (5U) /*! ADDSEL - Source MAC Address Select On Transmit * 0b000..Node MAC address programmed on PADDR1/2 registers. * 0b100..Reserved. * 0b101..Reserved. * 0b110..Reserved. */ #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) #define ENET_TCR_ADDINS_MASK (0x100U) #define ENET_TCR_ADDINS_SHIFT (8U) /*! ADDINS - Set MAC Address On Transmit * 0b0..The source MAC address is not modified by the MAC. * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. */ #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) #define ENET_TCR_CRCFWD_MASK (0x200U) #define ENET_TCR_CRCFWD_SHIFT (9U) /*! CRCFWD - Forward Frame From Application With CRC * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. */ #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) /*! @} */ /*! @name PALR - Physical Address Lower Register */ /*! @{ */ #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) #define ENET_PALR_PADDR1_SHIFT (0U) /*! PADDR1 - Pause Address */ #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) /*! @} */ /*! @name PAUR - Physical Address Upper Register */ /*! @{ */ #define ENET_PAUR_TYPE_MASK (0xFFFFU) #define ENET_PAUR_TYPE_SHIFT (0U) /*! TYPE - Type Field In PAUSE Frames */ #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) #define ENET_PAUR_PADDR2_SHIFT (16U) #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) /*! @} */ /*! @name OPD - Opcode/Pause Duration Register */ /*! @{ */ #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) #define ENET_OPD_PAUSE_DUR_SHIFT (0U) /*! PAUSE_DUR - Pause Duration */ #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) #define ENET_OPD_OPCODE_SHIFT (16U) /*! OPCODE - Opcode Field In PAUSE Frames */ #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) /*! @} */ /*! @name TXIC - Transmit Interrupt Coalescing Register */ /*! @{ */ #define ENET_TXIC_ICTT_MASK (0xFFFFU) #define ENET_TXIC_ICTT_SHIFT (0U) /*! ICTT - Interrupt coalescing timer threshold */ #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) #define ENET_TXIC_ICFT_MASK (0xFF00000U) #define ENET_TXIC_ICFT_SHIFT (20U) /*! ICFT - Interrupt coalescing frame count threshold */ #define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) #define ENET_TXIC_ICCS_MASK (0x40000000U) #define ENET_TXIC_ICCS_SHIFT (30U) /*! ICCS - Interrupt Coalescing Timer Clock Source Select * 0b0..Use MII/GMII TX clocks. * 0b1..Use ENET system clock. */ #define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) #define ENET_TXIC_ICEN_MASK (0x80000000U) #define ENET_TXIC_ICEN_SHIFT (31U) /*! ICEN - Interrupt Coalescing Enable * 0b0..Disable Interrupt coalescing. * 0b1..Enable Interrupt coalescing. */ #define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) /*! @} */ /* The count of ENET_TXIC */ #define ENET_TXIC_COUNT (3U) /*! @name RXIC - Receive Interrupt Coalescing Register */ /*! @{ */ #define ENET_RXIC_ICTT_MASK (0xFFFFU) #define ENET_RXIC_ICTT_SHIFT (0U) /*! ICTT - Interrupt coalescing timer threshold */ #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) #define ENET_RXIC_ICFT_MASK (0xFF00000U) #define ENET_RXIC_ICFT_SHIFT (20U) /*! ICFT - Interrupt coalescing frame count threshold */ #define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) #define ENET_RXIC_ICCS_MASK (0x40000000U) #define ENET_RXIC_ICCS_SHIFT (30U) /*! ICCS - Interrupt Coalescing Timer Clock Source Select * 0b0..Use MII/GMII TX clocks. * 0b1..Use ENET system clock. */ #define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) #define ENET_RXIC_ICEN_MASK (0x80000000U) #define ENET_RXIC_ICEN_SHIFT (31U) /*! ICEN - Interrupt Coalescing Enable * 0b0..Disable Interrupt coalescing. * 0b1..Enable Interrupt coalescing. */ #define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) /*! @} */ /* The count of ENET_RXIC */ #define ENET_RXIC_COUNT (3U) /*! @name IAUR - Descriptor Individual Upper Address Register */ /*! @{ */ #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) #define ENET_IAUR_IADDR1_SHIFT (0U) #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) /*! @} */ /*! @name IALR - Descriptor Individual Lower Address Register */ /*! @{ */ #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) #define ENET_IALR_IADDR2_SHIFT (0U) #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) /*! @} */ /*! @name GAUR - Descriptor Group Upper Address Register */ /*! @{ */ #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) #define ENET_GAUR_GADDR1_SHIFT (0U) #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) /*! @} */ /*! @name GALR - Descriptor Group Lower Address Register */ /*! @{ */ #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) #define ENET_GALR_GADDR2_SHIFT (0U) #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) /*! @} */ /*! @name TFWR - Transmit FIFO Watermark Register */ /*! @{ */ #define ENET_TFWR_TFWR_MASK (0x3FU) #define ENET_TFWR_TFWR_SHIFT (0U) /*! TFWR - Transmit FIFO Write * 0b000000..64 bytes written. * 0b000001..64 bytes written. * 0b000010..128 bytes written. * 0b000011..192 bytes written. * 0b111111..4032 bytes written. */ #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) #define ENET_TFWR_STRFWD_MASK (0x100U) #define ENET_TFWR_STRFWD_SHIFT (8U) /*! STRFWD - Store And Forward Enable * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. * 0b1..Enabled. */ #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) /*! @} */ /*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */ /*! @{ */ #define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR1_R_DES_START_SHIFT (3U) #define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK) /*! @} */ /*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */ /*! @{ */ #define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR1_X_DES_START_SHIFT (3U) #define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK) /*! @} */ /*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */ /*! @{ */ #define ENET_MRBR1_R_BUF_SIZE_MASK (0x3FF0U) #define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK) /*! @} */ /*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */ /*! @{ */ #define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR2_R_DES_START_SHIFT (3U) #define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK) /*! @} */ /*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */ /*! @{ */ #define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR2_X_DES_START_SHIFT (3U) #define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK) /*! @} */ /*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */ /*! @{ */ #define ENET_MRBR2_R_BUF_SIZE_MASK (0x3FF0U) #define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK) /*! @} */ /*! @name RDSR - Receive Descriptor Ring 0 Start Register */ /*! @{ */ #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR_R_DES_START_SHIFT (3U) #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) /*! @} */ /*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */ /*! @{ */ #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR_X_DES_START_SHIFT (3U) #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) /*! @} */ /*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */ /*! @{ */ #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) /*! @} */ /*! @name RSFL - Receive FIFO Section Full Threshold */ /*! @{ */ #define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) /*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold */ #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) /*! @} */ /*! @name RSEM - Receive FIFO Section Empty Threshold */ /*! @{ */ #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) /*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold */ #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) /*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold */ #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) /*! @} */ /*! @name RAEM - Receive FIFO Almost Empty Threshold */ /*! @{ */ #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) /*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold */ #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) /*! @} */ /*! @name RAFL - Receive FIFO Almost Full Threshold */ /*! @{ */ #define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) /*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold */ #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) /*! @} */ /*! @name TSEM - Transmit FIFO Section Empty Threshold */ /*! @{ */ #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) /*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold */ #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) /*! @} */ /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ /*! @{ */ #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) /*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold */ #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) /*! @} */ /*! @name TAFL - Transmit FIFO Almost Full Threshold */ /*! @{ */ #define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) /*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold */ #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) /*! @} */ /*! @name TIPG - Transmit Inter-Packet Gap */ /*! @{ */ #define ENET_TIPG_IPG_MASK (0x1FU) #define ENET_TIPG_IPG_SHIFT (0U) /*! IPG - Transmit Inter-Packet Gap */ #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) /*! @} */ /*! @name FTRL - Frame Truncation Length */ /*! @{ */ #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) #define ENET_FTRL_TRUNC_FL_SHIFT (0U) /*! TRUNC_FL - Frame Truncation Length */ #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) /*! @} */ /*! @name TACC - Transmit Accelerator Function Configuration */ /*! @{ */ #define ENET_TACC_SHIFT16_MASK (0x1U) #define ENET_TACC_SHIFT16_SHIFT (0U) /*! SHIFT16 - TX FIFO Shift-16 * 0b0..Disabled. * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is * extended to a 16-byte header. */ #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) #define ENET_TACC_IPCHK_MASK (0x8U) #define ENET_TACC_IPCHK_SHIFT (3U) /*! IPCHK * 0b0..Checksum is not inserted. * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must * be cleared. If a non-IP frame is transmitted the frame is not modified. */ #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) #define ENET_TACC_PROCHK_MASK (0x10U) #define ENET_TACC_PROCHK_SHIFT (4U) /*! PROCHK * 0b0..Checksum not inserted. * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the * frame. The checksum field must be cleared. The other frames are not modified. */ #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) /*! @} */ /*! @name RACC - Receive Accelerator Function Configuration */ /*! @{ */ #define ENET_RACC_PADREM_MASK (0x1U) #define ENET_RACC_PADREM_SHIFT (0U) /*! PADREM - Enable Padding Removal For Short IP Frames * 0b0..Padding not removed. * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. */ #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) #define ENET_RACC_IPDIS_MASK (0x2U) #define ENET_RACC_IPDIS_SHIFT (1U) /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum * 0b0..Frames with wrong IPv4 header checksum are not discarded. * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in * store and forward mode (RSFL cleared). */ #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) #define ENET_RACC_PRODIS_MASK (0x4U) #define ENET_RACC_PRODIS_SHIFT (2U) /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum * 0b0..Frames with wrong checksum are not discarded. * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL * cleared). */ #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) #define ENET_RACC_LINEDIS_MASK (0x40U) #define ENET_RACC_LINEDIS_SHIFT (6U) /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors * 0b0..Frames with errors are not discarded. * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. */ #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) #define ENET_RACC_SHIFT16_MASK (0x80U) #define ENET_RACC_SHIFT16_SHIFT (7U) /*! SHIFT16 - RX FIFO Shift-16 * 0b0..Disabled. * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. */ #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) /*! @} */ /*! @name RCMR - Receive Classification Match Register for Class n */ /*! @{ */ #define ENET_RCMR_CMP0_MASK (0x7U) #define ENET_RCMR_CMP0_SHIFT (0U) /*! CMP0 - Compare 0 */ #define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK) #define ENET_RCMR_CMP1_MASK (0x70U) #define ENET_RCMR_CMP1_SHIFT (4U) /*! CMP1 - Compare 1 */ #define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK) #define ENET_RCMR_CMP2_MASK (0x700U) #define ENET_RCMR_CMP2_SHIFT (8U) /*! CMP2 - Compare 2 */ #define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK) #define ENET_RCMR_CMP3_MASK (0x7000U) #define ENET_RCMR_CMP3_SHIFT (12U) /*! CMP3 - Compare 3 */ #define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK) #define ENET_RCMR_MATCHEN_MASK (0x10000U) #define ENET_RCMR_MATCHEN_SHIFT (16U) /*! MATCHEN - Match Enable * 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert. * 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received. */ #define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK) /*! @} */ /* The count of ENET_RCMR */ #define ENET_RCMR_COUNT (2U) /*! @name DMACFG - DMA Class Based Configuration */ /*! @{ */ #define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU) #define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U) /*! IDLE_SLOPE - Idle slope */ #define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK) #define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U) #define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U) /*! DMA_CLASS_EN - DMA class enable * 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also * requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 * queues are disabled then their frames will be placed in queue 0. * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic. */ #define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK) #define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U) #define ENET_DMACFG_CALC_NOIPG_SHIFT (17U) /*! CALC_NOIPG - Calculate no IPG * 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred * for a frame when doing bandwidth calculations. This is the default. * 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, * when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every * frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames * will become more bandwidth than large frames due to the relation of data to IPG overhead). */ #define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK) /*! @} */ /* The count of ENET_DMACFG */ #define ENET_DMACFG_COUNT (2U) /*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */ /*! @{ */ #define ENET_RDAR1_RDAR_MASK (0x1000000U) #define ENET_RDAR1_RDAR_SHIFT (24U) /*! RDAR - Receive Descriptor Active */ #define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK) /*! @} */ /*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */ /*! @{ */ #define ENET_TDAR1_TDAR_MASK (0x1000000U) #define ENET_TDAR1_TDAR_SHIFT (24U) /*! TDAR - Transmit Descriptor Active */ #define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK) /*! @} */ /*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */ /*! @{ */ #define ENET_RDAR2_RDAR_MASK (0x1000000U) #define ENET_RDAR2_RDAR_SHIFT (24U) /*! RDAR - Receive Descriptor Active */ #define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK) /*! @} */ /*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */ /*! @{ */ #define ENET_TDAR2_TDAR_MASK (0x1000000U) #define ENET_TDAR2_TDAR_SHIFT (24U) /*! TDAR - Transmit Descriptor Active */ #define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK) /*! @} */ /*! @name QOS - QOS Scheme */ /*! @{ */ #define ENET_QOS_TX_SCHEME_MASK (0x7U) #define ENET_QOS_TX_SCHEME_SHIFT (0U) /*! TX_SCHEME - TX scheme configuration * 0b000..Credit-based scheme * 0b001..Round-robin scheme * 0b010-0b111..Reserved */ #define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK) #define ENET_QOS_RX_FLUSH0_MASK (0x8U) #define ENET_QOS_RX_FLUSH0_SHIFT (3U) /*! RX_FLUSH0 - RX Flush Ring 0 * 0b0..Disable * 0b1..Enable */ #define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK) #define ENET_QOS_RX_FLUSH1_MASK (0x10U) #define ENET_QOS_RX_FLUSH1_SHIFT (4U) /*! RX_FLUSH1 - RX Flush Ring 1 * 0b0..Disable * 0b1..Enable */ #define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK) #define ENET_QOS_RX_FLUSH2_MASK (0x20U) #define ENET_QOS_RX_FLUSH2_SHIFT (5U) /*! RX_FLUSH2 - RX Flush Ring 2 * 0b0..Disable * 0b1..Enable */ #define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK) /*! @} */ /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ /*! @{ */ #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) /*! TXPKTS - Packet count */ #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) /*! TXPKTS - Broadcast packets */ #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) /*! TXPKTS - Multicast packets */ #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ /*! @{ */ #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) /*! TXPKTS - Packets with CRC/align error */ #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ /*! @{ */ #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC */ #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ /*! @{ */ #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC */ #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ /*! @{ */ #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of packets less than 64 bytes with bad CRC */ #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ /*! @{ */ #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC */ #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ /*! @{ */ #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of transmit collisions */ #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 64-byte transmit packets */ #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 65- to 127-byte transmit packets */ #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 128- to 255-byte transmit packets */ #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 256- to 511-byte transmit packets */ #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 512- to 1023-byte transmit packets */ #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 1024- to 2047-byte transmit packets */ #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ /*! @{ */ #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of transmit packets greater than 2048 bytes */ #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) /*! @} */ /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ /*! @{ */ #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) /*! TXOCTS - Number of transmit octets */ #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) /*! @} */ /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ /*! @{ */ #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted OK */ #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) /*! @} */ /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ /*! @{ */ #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with one collision */ #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) /*! @} */ /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ /*! @{ */ #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with multiple collisions */ #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) /*! @} */ /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ /*! @{ */ #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with deferral delay */ #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) /*! @} */ /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ /*! @{ */ #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with late collision */ #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) /*! @} */ /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ /*! @{ */ #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with excessive collisions */ #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) /*! @} */ /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ /*! @{ */ #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with transmit FIFO underrun */ #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) /*! @} */ /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ /*! @{ */ #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with carrier sense error */ #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) /*! @} */ /*! @name IEEE_T_SQE - Reserved Statistic Register */ /*! @{ */ #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) /*! COUNT - This read-only field is reserved and always has the value 0 */ #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) /*! @} */ /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ /*! @{ */ #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) /*! COUNT - Number of flow-control pause frames transmitted */ #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) /*! @} */ /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ /*! @{ */ #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) /*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). */ #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) /*! @} */ /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ /*! @{ */ #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) /*! COUNT - Number of packets received */ #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) /*! @} */ /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) /*! COUNT - Number of receive broadcast packets */ #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) /*! @} */ /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) /*! COUNT - Number of receive multicast packets */ #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) /*! @} */ /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ /*! @{ */ #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) /*! COUNT - Number of receive packets with CRC or align error */ #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) /*! @} */ /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ /*! @{ */ #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) /*! COUNT - Number of receive packets with less than 64 bytes and good CRC */ #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) /*! @} */ /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ /*! @{ */ #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) /*! COUNT - Number of receive packets greater than MAX_FL and good CRC */ #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) /*! @} */ /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ /*! @{ */ #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) /*! COUNT - Number of receive packets with less than 64 bytes and bad CRC */ #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) /*! @} */ /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ /*! @{ */ #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_JAB_COUNT_SHIFT (0U) /*! COUNT - Number of receive packets greater than MAX_FL and bad CRC */ #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) /*! @} */ /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P64_COUNT_SHIFT (0U) /*! COUNT - Number of 64-byte receive packets */ #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) /*! @} */ /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) /*! COUNT - Number of 65- to 127-byte recieve packets */ #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) /*! @} */ /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) /*! COUNT - Number of 128- to 255-byte recieve packets */ #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) /*! @} */ /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) /*! COUNT - Number of 256- to 511-byte recieve packets */ #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) /*! @} */ /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) /*! COUNT - Number of 512- to 1023-byte recieve packets */ #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) /*! @} */ /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ /*! @{ */ #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) /*! COUNT - Number of 1024- to 2047-byte recieve packets */ #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) /*! @} */ /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ /*! @{ */ #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) /*! COUNT - Number of greater-than-2048-byte recieve packets */ #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) /*! @} */ /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ /*! @{ */ #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) /*! COUNT - Number of receive octets */ #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) /*! @} */ /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ /*! @{ */ #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) /*! COUNT - Frame count */ #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) /*! @} */ /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ /*! @{ */ #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) /*! COUNT - Number of frames received OK */ #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) /*! @} */ /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ /*! @{ */ #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) /*! COUNT - Number of frames received with CRC error */ #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) /*! @} */ /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ /*! @{ */ #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) /*! COUNT - Number of frames received with alignment error */ #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) /*! @} */ /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ /*! @{ */ #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) /*! COUNT - Receive FIFO overflow count */ #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) /*! @} */ /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ /*! @{ */ #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) /*! COUNT - Number of flow-control pause frames received */ #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) /*! @} */ /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ /*! @{ */ #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) /*! COUNT - Number of octets for frames received without error */ #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) /*! @} */ /*! @name ATCR - Adjustable Timer Control Register */ /*! @{ */ #define ENET_ATCR_EN_MASK (0x1U) #define ENET_ATCR_EN_SHIFT (0U) /*! EN - Enable Timer * 0b0..The timer stops at the current value. * 0b1..The timer starts incrementing. */ #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) #define ENET_ATCR_OFFEN_MASK (0x4U) #define ENET_ATCR_OFFEN_SHIFT (2U) /*! OFFEN - Enable One-Shot Offset Event * 0b0..Disable. * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared * when the offset event is reached, so no further event occurs until the field is set again. The timer * offset value must be set before setting this field. */ #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) #define ENET_ATCR_OFFRST_MASK (0x8U) #define ENET_ATCR_OFFRST_SHIFT (3U) /*! OFFRST - Reset Timer On Offset Event * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. */ #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) #define ENET_ATCR_PEREN_MASK (0x10U) #define ENET_ATCR_PEREN_SHIFT (4U) /*! PEREN - Enable Periodical Event * 0b0..Disable. * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before * setting this bit. Not all devices contain the event signal output. See the chip configuration details. */ #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) #define ENET_ATCR_PINPER_MASK (0x80U) #define ENET_ATCR_PINPER_SHIFT (7U) /*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event * 0b0..Disable. * 0b1..Enable. */ #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) #define ENET_ATCR_RESTART_MASK (0x200U) #define ENET_ATCR_RESTART_SHIFT (9U) /*! RESTART - Reset Timer */ #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) #define ENET_ATCR_CAPTURE_MASK (0x800U) #define ENET_ATCR_CAPTURE_SHIFT (11U) /*! CAPTURE - Capture Timer Value * 0b0..No effect. * 0b1..The current time is captured and can be read from the ATVR register. */ #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) #define ENET_ATCR_SLAVE_MASK (0x2000U) #define ENET_ATCR_SLAVE_SHIFT (13U) /*! SLAVE - Enable Timer Slave Mode * 0b0..The timer is active and all configuration fields in this register are relevant. * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. */ #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) /*! @} */ /*! @name ATVR - Timer Value Register */ /*! @{ */ #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) #define ENET_ATVR_ATIME_SHIFT (0U) #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) /*! @} */ /*! @name ATOFF - Timer Offset Register */ /*! @{ */ #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) #define ENET_ATOFF_OFFSET_SHIFT (0U) #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) /*! @} */ /*! @name ATPER - Timer Period Register */ /*! @{ */ #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) #define ENET_ATPER_PERIOD_SHIFT (0U) /*! PERIOD - Value for generating periodic events */ #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) /*! @} */ /*! @name ATCOR - Timer Correction Register */ /*! @{ */ #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) #define ENET_ATCOR_COR_SHIFT (0U) /*! COR - Correction Counter Wrap-Around Value */ #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) /*! @} */ /*! @name ATINC - Time-Stamping Clock Period Register */ /*! @{ */ #define ENET_ATINC_INC_MASK (0x7FU) #define ENET_ATINC_INC_SHIFT (0U) /*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds */ #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) #define ENET_ATINC_INC_CORR_MASK (0x7F00U) #define ENET_ATINC_INC_CORR_SHIFT (8U) /*! INC_CORR - Correction Increment Value */ #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) /*! @} */ /*! @name ATSTMP - Timestamp of Last Transmitted Frame */ /*! @{ */ #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) /*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the * ff_tx_ts_frm signal asserted from the user application */ #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) /*! @} */ /*! @name MDATA - Pattern Match Data Register */ /*! @{ */ #define ENET_MDATA_MATCHDATA_MASK (0xFFFFFFFFU) #define ENET_MDATA_MATCHDATA_SHIFT (0U) /*! MATCHDATA - Match Data */ #define ENET_MDATA_MATCHDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MDATA_MATCHDATA_SHIFT)) & ENET_MDATA_MATCHDATA_MASK) /*! @} */ /*! @name MMASK - Match Entry Mask Register */ /*! @{ */ #define ENET_MMASK_MATCHMASK_MASK (0xFFFFFFFFU) #define ENET_MMASK_MATCHMASK_SHIFT (0U) /*! MATCHMASK - Match Mask */ #define ENET_MMASK_MATCHMASK(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMASK_MATCHMASK_SHIFT)) & ENET_MMASK_MATCHMASK_MASK) /*! @} */ /*! @name MCONFIG - Match Entry Rules Configuration Register */ /*! @{ */ #define ENET_MCONFIG_FRMOFF_MASK (0xFCU) #define ENET_MCONFIG_FRMOFF_SHIFT (2U) /*! FRMOFF - Frame Offset */ #define ENET_MCONFIG_FRMOFF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_FRMOFF_SHIFT)) & ENET_MCONFIG_FRMOFF_MASK) #define ENET_MCONFIG_OK_INDEX_MASK (0xFF0000U) #define ENET_MCONFIG_OK_INDEX_SHIFT (16U) /*! OK_INDEX - When AF = 0 and RF = 0, this value shows the next entry of the matching table to be * used for comparison instead of using the next entry sequentially */ #define ENET_MCONFIG_OK_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_OK_INDEX_SHIFT)) & ENET_MCONFIG_OK_INDEX_MASK) #define ENET_MCONFIG_IM_MASK (0x20000000U) #define ENET_MCONFIG_IM_SHIFT (29U) /*! IM - Invert Match */ #define ENET_MCONFIG_IM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_IM_SHIFT)) & ENET_MCONFIG_IM_MASK) #define ENET_MCONFIG_RF_MASK (0x40000000U) #define ENET_MCONFIG_RF_SHIFT (30U) /*! RF - Reject Frame */ #define ENET_MCONFIG_RF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_RF_SHIFT)) & ENET_MCONFIG_RF_MASK) #define ENET_MCONFIG_AF_MASK (0x80000000U) #define ENET_MCONFIG_AF_SHIFT (31U) /*! AF - Accept Frame */ #define ENET_MCONFIG_AF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_AF_SHIFT)) & ENET_MCONFIG_AF_MASK) /*! @} */ /*! @name MENTRYRW - Match Entry Read/Write Command Register */ /*! @{ */ #define ENET_MENTRYRW_ENTRYADD_MASK (0xFFU) #define ENET_MENTRYRW_ENTRYADD_SHIFT (0U) /*! ENTRYADD - Entry Address */ #define ENET_MENTRYRW_ENTRYADD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MENTRYRW_ENTRYADD_SHIFT)) & ENET_MENTRYRW_ENTRYADD_MASK) #define ENET_MENTRYRW_WR_MASK (0x100U) #define ENET_MENTRYRW_WR_SHIFT (8U) /*! WR - Entry write command */ #define ENET_MENTRYRW_WR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MENTRYRW_WR_SHIFT)) & ENET_MENTRYRW_WR_MASK) #define ENET_MENTRYRW_RD_MASK (0x200U) #define ENET_MENTRYRW_RD_SHIFT (9U) /*! RD - Entry Read Command */ #define ENET_MENTRYRW_RD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MENTRYRW_RD_SHIFT)) & ENET_MENTRYRW_RD_MASK) /*! @} */ /*! @name RXPCTL - Receive Parser Control Register */ /*! @{ */ #define ENET_RXPCTL_ENPARSER_MASK (0x1U) #define ENET_RXPCTL_ENPARSER_SHIFT (0U) /*! ENPARSER - Enable Receive Parser * 0b0..Parser is disabled. * 0b1..Parser is enabled. */ #define ENET_RXPCTL_ENPARSER(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_ENPARSER_SHIFT)) & ENET_RXPCTL_ENPARSER_MASK) #define ENET_RXPCTL_INVBYTORD_MASK (0x2U) #define ENET_RXPCTL_INVBYTORD_SHIFT (1U) /*! INVBYTORD - Inverse Frame Byte Order */ #define ENET_RXPCTL_INVBYTORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_INVBYTORD_SHIFT)) & ENET_RXPCTL_INVBYTORD_MASK) #define ENET_RXPCTL_PRSRSCLR_MASK (0x10U) #define ENET_RXPCTL_PRSRSCLR_SHIFT (4U) /*! PRSRSCLR - Clear Parser Statistics Counter */ #define ENET_RXPCTL_PRSRSCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_PRSRSCLR_SHIFT)) & ENET_RXPCTL_PRSRSCLR_MASK) #define ENET_RXPCTL_MAXINDEX_MASK (0xFF00U) #define ENET_RXPCTL_MAXINDEX_SHIFT (8U) /*! MAXINDEX - Maximum Index */ #define ENET_RXPCTL_MAXINDEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_MAXINDEX_SHIFT)) & ENET_RXPCTL_MAXINDEX_MASK) #define ENET_RXPCTL_ENDERRQ_MASK (0xFF0000U) #define ENET_RXPCTL_ENDERRQ_SHIFT (16U) /*! ENDERRQ - End Error Queue * 0b00000001..Place the frame in Queue 0 * 0b00000010..Place the frame in Queue 1 * 0b00000100..Place the frame in Queue 2 */ #define ENET_RXPCTL_ENDERRQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_ENDERRQ_SHIFT)) & ENET_RXPCTL_ENDERRQ_MASK) #define ENET_RXPCTL_ACPTEERR_MASK (0x1000000U) #define ENET_RXPCTL_ACPTEERR_SHIFT (24U) /*! ACPTEERR - Accept End Error */ #define ENET_RXPCTL_ACPTEERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_ACPTEERR_SHIFT)) & ENET_RXPCTL_ACPTEERR_MASK) /*! @} */ /*! @name MAXFRMOFF - Maximum Frame Offset */ /*! @{ */ #define ENET_MAXFRMOFF_MXFRMOFF_MASK (0x3FU) #define ENET_MAXFRMOFF_MXFRMOFF_SHIFT (0U) /*! MXFRMOFF - Max. Frame Offset */ #define ENET_MAXFRMOFF_MXFRMOFF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAXFRMOFF_MXFRMOFF_SHIFT)) & ENET_MAXFRMOFF_MXFRMOFF_MASK) /*! @} */ /*! @name RXPARST - Receive Parser Status */ /*! @{ */ #define ENET_RXPARST_MXINDERR_MASK (0x1U) #define ENET_RXPARST_MXINDERR_SHIFT (0U) /*! MXINDERR - Maximum Index Error */ #define ENET_RXPARST_MXINDERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_MXINDERR_SHIFT)) & ENET_RXPARST_MXINDERR_MASK) #define ENET_RXPARST_TBLDPTERR_MASK (0x2U) #define ENET_RXPARST_TBLDPTERR_SHIFT (1U) /*! TBLDPTERR - Table Depth Error */ #define ENET_RXPARST_TBLDPTERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_TBLDPTERR_SHIFT)) & ENET_RXPARST_TBLDPTERR_MASK) #define ENET_RXPARST_NOMTCERR_MASK (0x4U) #define ENET_RXPARST_NOMTCERR_SHIFT (2U) /*! NOMTCERR - No Match Error */ #define ENET_RXPARST_NOMTCERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_NOMTCERR_SHIFT)) & ENET_RXPARST_NOMTCERR_MASK) #define ENET_RXPARST_FMOFFERR_MASK (0x8U) #define ENET_RXPARST_FMOFFERR_SHIFT (3U) /*! FMOFFERR - Maximum Frame Offset Error */ #define ENET_RXPARST_FMOFFERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_FMOFFERR_SHIFT)) & ENET_RXPARST_FMOFFERR_MASK) #define ENET_RXPARST_PRSENDERR_MASK (0x10U) #define ENET_RXPARST_PRSENDERR_SHIFT (4U) /*! PRSENDERR - Parser End Error */ #define ENET_RXPARST_PRSENDERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_PRSENDERR_SHIFT)) & ENET_RXPARST_PRSENDERR_MASK) #define ENET_RXPARST_INVMAXIDX_MASK (0x20U) #define ENET_RXPARST_INVMAXIDX_SHIFT (5U) /*! INVMAXIDX - Invalid Value of MAXINDEX */ #define ENET_RXPARST_INVMAXIDX(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_INVMAXIDX_SHIFT)) & ENET_RXPARST_INVMAXIDX_MASK) #define ENET_RXPARST_RXPRSDN_MASK (0x100U) #define ENET_RXPARST_RXPRSDN_SHIFT (8U) /*! RXPRSDN - Receive Parser Done */ #define ENET_RXPARST_RXPRSDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_RXPRSDN_SHIFT)) & ENET_RXPARST_RXPRSDN_MASK) /*! @} */ /*! @name PARSDSCD - Parser Discard Count */ /*! @{ */ #define ENET_PARSDSCD_COUNT_MASK (0xFFFFFFFFU) #define ENET_PARSDSCD_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENET_PARSDSCD_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PARSDSCD_COUNT_SHIFT)) & ENET_PARSDSCD_COUNT_MASK) /*! @} */ /*! @name PRSACPT0 - Parser Accept Count 0 */ /*! @{ */ #define ENET_PRSACPT0_COUNT_MASK (0xFFFFFFFFU) #define ENET_PRSACPT0_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENET_PRSACPT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSACPT0_COUNT_SHIFT)) & ENET_PRSACPT0_COUNT_MASK) /*! @} */ /*! @name PRSRJCT0 - Parser Reject Count 0 */ /*! @{ */ #define ENET_PRSRJCT0_COUNT_MASK (0xFFFFFFFFU) #define ENET_PRSRJCT0_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENET_PRSRJCT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSRJCT0_COUNT_SHIFT)) & ENET_PRSRJCT0_COUNT_MASK) /*! @} */ /*! @name PRSACPT1 - Parser Accept Count 1 */ /*! @{ */ #define ENET_PRSACPT1_COUNT_MASK (0xFFFFFFFFU) #define ENET_PRSACPT1_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENET_PRSACPT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSACPT1_COUNT_SHIFT)) & ENET_PRSACPT1_COUNT_MASK) /*! @} */ /*! @name PRSRJCT1 - Parser Reject Count 1 */ /*! @{ */ #define ENET_PRSRJCT1_COUNT_MASK (0xFFFFFFFFU) #define ENET_PRSRJCT1_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENET_PRSRJCT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSRJCT1_COUNT_SHIFT)) & ENET_PRSRJCT1_COUNT_MASK) /*! @} */ /*! @name PRSACPT2 - Parser Accept Count 2 */ /*! @{ */ #define ENET_PRSACPT2_COUNT_MASK (0xFFFFFFFFU) #define ENET_PRSACPT2_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENET_PRSACPT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSACPT2_COUNT_SHIFT)) & ENET_PRSACPT2_COUNT_MASK) /*! @} */ /*! @name PRSRJCT2 - Parser Reject Count 2 */ /*! @{ */ #define ENET_PRSRJCT2_COUNT_MASK (0xFFFFFFFFU) #define ENET_PRSRJCT2_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENET_PRSRJCT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSRJCT2_COUNT_SHIFT)) & ENET_PRSRJCT2_COUNT_MASK) /*! @} */ /*! @name TGSR - Timer Global Status Register */ /*! @{ */ #define ENET_TGSR_TF0_MASK (0x1U) #define ENET_TGSR_TF0_SHIFT (0U) /*! TF0 - Copy Of Timer Flag For Channel 0 * 0b0..Timer Flag for Channel 0 is clear * 0b1..Timer Flag for Channel 0 is set */ #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) #define ENET_TGSR_TF1_MASK (0x2U) #define ENET_TGSR_TF1_SHIFT (1U) /*! TF1 - Copy Of Timer Flag For Channel 1 * 0b0..Timer Flag for Channel 1 is clear * 0b1..Timer Flag for Channel 1 is set */ #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) #define ENET_TGSR_TF2_MASK (0x4U) #define ENET_TGSR_TF2_SHIFT (2U) /*! TF2 - Copy Of Timer Flag For Channel 2 * 0b0..Timer Flag for Channel 2 is clear * 0b1..Timer Flag for Channel 2 is set */ #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) #define ENET_TGSR_TF3_MASK (0x8U) #define ENET_TGSR_TF3_SHIFT (3U) /*! TF3 - Copy Of Timer Flag For Channel 3 * 0b0..Timer Flag for Channel 3 is clear * 0b1..Timer Flag for Channel 3 is set */ #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) /*! @} */ /*! @name TCSR - Timer Control Status Register */ /*! @{ */ #define ENET_TCSR_TDRE_MASK (0x1U) #define ENET_TCSR_TDRE_SHIFT (0U) /*! TDRE - Timer DMA Request Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) #define ENET_TCSR_TMODE_MASK (0x3CU) #define ENET_TCSR_TMODE_SHIFT (2U) /*! TMODE - Timer Mode * 0b0000..Timer Channel is disabled. * 0b0001..Timer Channel is configured for Input Capture on rising edge. * 0b0010..Timer Channel is configured for Input Capture on falling edge. * 0b0011..Timer Channel is configured for Input Capture on both edges. * 0b0100..Timer Channel is configured for Output Compare - software only. * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. * 0b0111..Timer Channel is configured for Output Compare - set output on compare. * 0b1000..Reserved * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. * 0b110x..Reserved * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. */ #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) #define ENET_TCSR_TIE_MASK (0x40U) #define ENET_TCSR_TIE_SHIFT (6U) /*! TIE - Timer Interrupt Enable * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) #define ENET_TCSR_TF_MASK (0x80U) #define ENET_TCSR_TF_SHIFT (7U) /*! TF - Timer Flag * 0b0..Input Capture or Output Compare has not occurred. * 0b1..Input Capture or Output Compare has occurred. */ #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) #define ENET_TCSR_TPWC_MASK (0xF800U) #define ENET_TCSR_TPWC_SHIFT (11U) /*! TPWC - Timer PulseWidth Control * 0b00000..Pulse width is one 1588-clock cycle. * 0b00001..Pulse width is two 1588-clock cycles. * 0b00010..Pulse width is three 1588-clock cycles. * 0b00011..Pulse width is four 1588-clock cycles. * 0b11111..Pulse width is 32 1588-clock cycles. */ #define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) /*! @} */ /* The count of ENET_TCSR */ #define ENET_TCSR_COUNT (4U) /*! @name TCCR - Timer Compare Capture Register */ /*! @{ */ #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) #define ENET_TCCR_TCC_SHIFT (0U) /*! TCC - Timer Capture Compare */ #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) /*! @} */ /* The count of ENET_TCCR */ #define ENET_TCCR_COUNT (4U) /*! * @} */ /* end of group ENET_Register_Masks */ /* ENET - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__ENET0 base address */ #define CONNECTIVITY__ENET0_BASE (0x5B040000u) /** Peripheral CONNECTIVITY__ENET0 base pointer */ #define CONNECTIVITY__ENET0 ((ENET_Type *)CONNECTIVITY__ENET0_BASE) /** Peripheral CONNECTIVITY__ENET1 base address */ #define CONNECTIVITY__ENET1_BASE (0x5B050000u) /** Peripheral CONNECTIVITY__ENET1 base pointer */ #define CONNECTIVITY__ENET1 ((ENET_Type *)CONNECTIVITY__ENET1_BASE) /** Array initializer of ENET peripheral base addresses */ #define ENET_BASE_ADDRS { CONNECTIVITY__ENET0_BASE, CONNECTIVITY__ENET1_BASE } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { CONNECTIVITY__ENET0, CONNECTIVITY__ENET1 } /* ENET Buffer Descriptor and Buffer Address Alignment. */ #define ENET_BUFF_ALIGNMENT (64U) /* Interrupt vectors for the ENET peripheral type */ #define ENET_Transmit_IRQS { NotAvail_IRQn, NotAvail_IRQn } #define ENET_Receive_IRQS { NotAvail_IRQn, NotAvail_IRQn } #define ENET_Error_IRQS { NotAvail_IRQn, NotAvail_IRQn } #define ENET_1588_Timer_IRQS { NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group ENET_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ESAI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer * @{ */ /** ESAI - Register Layout Typedef */ typedef struct { __O uint32_t ETDR; /**< ESAI Transmit Data Register, offset: 0x0 */ __I uint32_t ERDR; /**< ESAI Receive Data Register, offset: 0x4 */ __IO uint32_t ECR; /**< ESAI Control Register, offset: 0x8 */ __I uint32_t ESR; /**< ESAI Status Register, offset: 0xC */ __IO uint32_t TFCR; /**< Transmit FIFO Configuration Register, offset: 0x10 */ __I uint32_t TFSR; /**< Transmit FIFO Status Register, offset: 0x14 */ __IO uint32_t RFCR; /**< Receive FIFO Configuration Register, offset: 0x18 */ __I uint32_t RFSR; /**< Receive FIFO Status Register, offset: 0x1C */ uint8_t RESERVED_0[96]; __O uint32_t TX[6]; /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */ __O uint32_t TSR; /**< ESAI Transmit Slot Register, offset: 0x98 */ uint8_t RESERVED_1[4]; __I uint32_t RX[4]; /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_2[28]; __I uint32_t SAISR; /**< Serial Audio Interface Status Register, offset: 0xCC */ __IO uint32_t SAICR; /**< Serial Audio Interface Control Register, offset: 0xD0 */ __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xD4 */ __IO uint32_t TCCR; /**< Transmit Clock Control Register, offset: 0xD8 */ __IO uint32_t RCR; /**< Receive Control Register, offset: 0xDC */ __IO uint32_t RCCR; /**< Receive Clock Control Register, offset: 0xE0 */ __IO uint32_t TSMA; /**< Transmit Slot Mask Register A, offset: 0xE4 */ __IO uint32_t TSMB; /**< Transmit Slot Mask Register B, offset: 0xE8 */ __IO uint32_t RSMA; /**< Receive Slot Mask Register A, offset: 0xEC */ __IO uint32_t RSMB; /**< Receive Slot Mask Register B, offset: 0xF0 */ uint8_t RESERVED_3[4]; __IO uint32_t PRRC; /**< Port C Direction Register, offset: 0xF8 */ __IO uint32_t PCRC; /**< Port C Control Register, offset: 0xFC */ } ESAI_Type; /* ---------------------------------------------------------------------------- -- ESAI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ESAI_Register_Masks ESAI Register Masks * @{ */ /*! @name ETDR - ESAI Transmit Data Register */ /*! @{ */ #define ESAI_ETDR_ETDR_MASK (0xFFFFFFFFU) #define ESAI_ETDR_ETDR_SHIFT (0U) /*! ETDR - ETDR */ #define ESAI_ETDR_ETDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ETDR_ETDR_SHIFT)) & ESAI_ETDR_ETDR_MASK) /*! @} */ /*! @name ERDR - ESAI Receive Data Register */ /*! @{ */ #define ESAI_ERDR_ERDR_MASK (0xFFFFFFFFU) #define ESAI_ERDR_ERDR_SHIFT (0U) /*! ERDR - ERDR */ #define ESAI_ERDR_ERDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ERDR_ERDR_SHIFT)) & ESAI_ERDR_ERDR_MASK) /*! @} */ /*! @name ECR - ESAI Control Register */ /*! @{ */ #define ESAI_ECR_ESAIEN_MASK (0x1U) #define ESAI_ECR_ESAIEN_SHIFT (0U) /*! ESAIEN - ESAIEN * 0b0..ESAI disabled. * 0b1..ESAI enabled. */ #define ESAI_ECR_ESAIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ESAIEN_SHIFT)) & ESAI_ECR_ESAIEN_MASK) #define ESAI_ECR_ERST_MASK (0x2U) #define ESAI_ECR_ERST_SHIFT (1U) /*! ERST - ERST * 0b0..ESAI not reset. * 0b1..ESAI reset. */ #define ESAI_ECR_ERST(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERST_SHIFT)) & ESAI_ECR_ERST_MASK) #define ESAI_ECR_ERO_MASK (0x10000U) #define ESAI_ECR_ERO_SHIFT (16U) /*! ERO - ERO * 0b0..HCKR pin has normal function. * 0b1..EXTAL driven onto HCKR pin. */ #define ESAI_ECR_ERO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERO_SHIFT)) & ESAI_ECR_ERO_MASK) #define ESAI_ECR_ERI_MASK (0x20000U) #define ESAI_ECR_ERI_SHIFT (17U) /*! ERI - ERI * 0b0..HCKR pin has normal function. * 0b1..EXTAL muxed into HCKR input. */ #define ESAI_ECR_ERI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERI_SHIFT)) & ESAI_ECR_ERI_MASK) #define ESAI_ECR_ETO_MASK (0x40000U) #define ESAI_ECR_ETO_SHIFT (18U) /*! ETO - ETO * 0b0..HCKT pin has normal function. * 0b1..EXTAL driven onto HCKT pin. */ #define ESAI_ECR_ETO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETO_SHIFT)) & ESAI_ECR_ETO_MASK) #define ESAI_ECR_ETI_MASK (0x80000U) #define ESAI_ECR_ETI_SHIFT (19U) /*! ETI - ETI * 0b0..HCKT pin has normal function. * 0b1..EXTAL muxed into HCKT input. */ #define ESAI_ECR_ETI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETI_SHIFT)) & ESAI_ECR_ETI_MASK) /*! @} */ /*! @name ESR - ESAI Status Register */ /*! @{ */ #define ESAI_ESR_RD_MASK (0x1U) #define ESAI_ESR_RD_SHIFT (0U) /*! RD - RD * 0b0..RD is not the highest priority active interrupt. * 0b1..RD is the highest priority active interrupt. */ #define ESAI_ESR_RD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RD_SHIFT)) & ESAI_ESR_RD_MASK) #define ESAI_ESR_RED_MASK (0x2U) #define ESAI_ESR_RED_SHIFT (1U) /*! RED - RED * 0b0..RED is not the highest priority active interrupt. * 0b1..RED is the highest priority active interrupt. */ #define ESAI_ESR_RED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RED_SHIFT)) & ESAI_ESR_RED_MASK) #define ESAI_ESR_RDE_MASK (0x4U) #define ESAI_ESR_RDE_SHIFT (2U) /*! RDE - RDE * 0b0..RDE is not the highest priority active interrupt. * 0b1..RDE is the highest priority active interrupt. */ #define ESAI_ESR_RDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RDE_SHIFT)) & ESAI_ESR_RDE_MASK) #define ESAI_ESR_RLS_MASK (0x8U) #define ESAI_ESR_RLS_SHIFT (3U) /*! RLS - RLS * 0b0..RLS is not the highest priority active interrupt. * 0b1..RLS is the highest priority active interrupt. */ #define ESAI_ESR_RLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RLS_SHIFT)) & ESAI_ESR_RLS_MASK) #define ESAI_ESR_TD_MASK (0x10U) #define ESAI_ESR_TD_SHIFT (4U) /*! TD - TD * 0b0..TD is not the highest priority active interrupt. * 0b1..TD is the highest priority active interrupt. */ #define ESAI_ESR_TD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TD_SHIFT)) & ESAI_ESR_TD_MASK) #define ESAI_ESR_TED_MASK (0x20U) #define ESAI_ESR_TED_SHIFT (5U) /*! TED - TED * 0b0..TED is not the highest priority active interrupt. * 0b1..TED is the highest priority active interrupt. */ #define ESAI_ESR_TED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TED_SHIFT)) & ESAI_ESR_TED_MASK) #define ESAI_ESR_TDE_MASK (0x40U) #define ESAI_ESR_TDE_SHIFT (6U) /*! TDE - TDE * 0b0..TDE is not the highest priority active interrupt. * 0b1..TDE is the highest priority active interrupt. */ #define ESAI_ESR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TDE_SHIFT)) & ESAI_ESR_TDE_MASK) #define ESAI_ESR_TLS_MASK (0x80U) #define ESAI_ESR_TLS_SHIFT (7U) /*! TLS - TLS * 0b0..TLS is not the highest priority active interrupt. * 0b1..TLS is the highest priority active interrupt. */ #define ESAI_ESR_TLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TLS_SHIFT)) & ESAI_ESR_TLS_MASK) #define ESAI_ESR_TFE_MASK (0x100U) #define ESAI_ESR_TFE_SHIFT (8U) /*! TFE - TFE * 0b0..Number of empty slots in Transmit FIFO less than Transmit FIFO watermark. * 0b1..Number of empty slots in Transmit FIFO is equal to or greater than Transmit FIFO watermark. */ #define ESAI_ESR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TFE_SHIFT)) & ESAI_ESR_TFE_MASK) #define ESAI_ESR_RFF_MASK (0x200U) #define ESAI_ESR_RFF_SHIFT (9U) /*! RFF - RFF * 0b0..Number of words in Receive FIFO less than Receive FIFO watermark. * 0b1..Number of words in Receive FIFO is equal to or greater than Receive FIFO watermark. */ #define ESAI_ESR_RFF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RFF_SHIFT)) & ESAI_ESR_RFF_MASK) #define ESAI_ESR_TINIT_MASK (0x400U) #define ESAI_ESR_TINIT_SHIFT (10U) /*! TINIT - TINIT * 0b0..Transmitter has finished initializing the Transmit Data Registers (or Transmit FIFO is not enabled or * Transmit Initialization is not enabled). * 0b1..Transmitter has not finished initializing the Transmit Data Registers. */ #define ESAI_ESR_TINIT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TINIT_SHIFT)) & ESAI_ESR_TINIT_MASK) /*! @} */ /*! @name TFCR - Transmit FIFO Configuration Register */ /*! @{ */ #define ESAI_TFCR_TFE_MASK (0x1U) #define ESAI_TFCR_TFE_SHIFT (0U) /*! TFE - TFE * 0b0..Transmit FIFO disabled. * 0b1..Transmit FIFO enabled. */ #define ESAI_TFCR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFE_SHIFT)) & ESAI_TFCR_TFE_MASK) #define ESAI_TFCR_TFR_MASK (0x2U) #define ESAI_TFCR_TFR_SHIFT (1U) /*! TFR - TFR * 0b0..Transmit FIFO not reset. * 0b1..Transmit FIFO reset. */ #define ESAI_TFCR_TFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFR_SHIFT)) & ESAI_TFCR_TFR_MASK) #define ESAI_TFCR_TE0_MASK (0x4U) #define ESAI_TFCR_TE0_SHIFT (2U) /*! TE0 - TE0 * 0b0..Transmitter #0 is not using the Transmit FIFO. * 0b1..Transmitter #0 is using the Transmit FIFO. */ #define ESAI_TFCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE0_SHIFT)) & ESAI_TFCR_TE0_MASK) #define ESAI_TFCR_TE1_MASK (0x8U) #define ESAI_TFCR_TE1_SHIFT (3U) /*! TE1 - TE1 * 0b0..Transmitter #1 is not using the Transmit FIFO. * 0b1..Transmitter #1 is using the Transmit FIFO. */ #define ESAI_TFCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE1_SHIFT)) & ESAI_TFCR_TE1_MASK) #define ESAI_TFCR_TE2_MASK (0x10U) #define ESAI_TFCR_TE2_SHIFT (4U) /*! TE2 - TE2 * 0b0..Transmitter #2 is not using the Transmit FIFO. * 0b1..Transmitter #2 is using the Transmit FIFO. */ #define ESAI_TFCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE2_SHIFT)) & ESAI_TFCR_TE2_MASK) #define ESAI_TFCR_TE3_MASK (0x20U) #define ESAI_TFCR_TE3_SHIFT (5U) /*! TE3 - TE3 * 0b0..Transmitter #3 is not using the Transmit FIFO. * 0b1..Transmitter #3 is using the Transmit FIFO. */ #define ESAI_TFCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE3_SHIFT)) & ESAI_TFCR_TE3_MASK) #define ESAI_TFCR_TE4_MASK (0x40U) #define ESAI_TFCR_TE4_SHIFT (6U) /*! TE4 - TE4 * 0b0..Transmitter #4 is not using the Transmit FIFO. * 0b1..Transmitter #4 is using the Transmit FIFO. */ #define ESAI_TFCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE4_SHIFT)) & ESAI_TFCR_TE4_MASK) #define ESAI_TFCR_TE5_MASK (0x80U) #define ESAI_TFCR_TE5_SHIFT (7U) /*! TE5 - TE5 * 0b0..Transmitter #5 is not using the Transmit FIFO. * 0b1..Transmitter #5 is using the Transmit FIFO. */ #define ESAI_TFCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE5_SHIFT)) & ESAI_TFCR_TE5_MASK) #define ESAI_TFCR_TFWM_MASK (0xFF00U) #define ESAI_TFCR_TFWM_SHIFT (8U) /*! TFWM - TFWM */ #define ESAI_TFCR_TFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFWM_SHIFT)) & ESAI_TFCR_TFWM_MASK) #define ESAI_TFCR_TWA_MASK (0x70000U) #define ESAI_TFCR_TWA_SHIFT (16U) /*! TWA - TWA * 0b000..MSB of data is bit 31. Data bits 7-0 are ignored when passed to transmit shift register. * 0b001..MSB of data is bit 27. Data bits 3-0 are ignored when passed to transmit shift register. * 0b010..MSB of data is bit 23. * 0b011..MSB of data is bit 19. Bottom 4 bits of transmit shift register are zeroed. * 0b100..MSB of data is bit 15. Bottom 8 bits of transmit shift register are zeroed. * 0b101..MSB of data is bit 11. Bottom 12 bits of transmit shift register are zeroed. * 0b110..MSB of data is bit 7. Bottom 16 bits of transmit shift register are zeroed. * 0b111..MSB of data is bit 3. Bottom 20 bits of transmit shift register are zeroed. */ #define ESAI_TFCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TWA_SHIFT)) & ESAI_TFCR_TWA_MASK) #define ESAI_TFCR_TIEN_MASK (0x80000U) #define ESAI_TFCR_TIEN_SHIFT (19U) /*! TIEN - TIEN * 0b0..Transmit Data Registers are not initialized from the FIFO once the Transmit FIFO is enabled. Software * must manually initialize the Transmit Data Registers separately. * 0b1..Transmit Data Registers are initialized from the FIFO once the Transmit FIFO is enabled. */ #define ESAI_TFCR_TIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TIEN_SHIFT)) & ESAI_TFCR_TIEN_MASK) /*! @} */ /*! @name TFSR - Transmit FIFO Status Register */ /*! @{ */ #define ESAI_TFSR_TFCNT_MASK (0xFFU) #define ESAI_TFSR_TFCNT_SHIFT (0U) /*! TFCNT - TFCNT */ #define ESAI_TFSR_TFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_TFCNT_SHIFT)) & ESAI_TFSR_TFCNT_MASK) #define ESAI_TFSR_NTFI_MASK (0x700U) #define ESAI_TFSR_NTFI_SHIFT (8U) /*! NTFI - NTFI * 0b000..Transmitter #0 receives next word written to the Transmit FIFO. * 0b001..Transmitter #1 receives next word written to the Transmit FIFO. * 0b010..Transmitter #2 receives next word written to the Transmit FIFO. * 0b011..Transmitter #3 receives next word written to the Transmit FIFO. * 0b100..Transmitter #4 receives next word written to the Transmit FIFO. * 0b101..Transmitter #5 receives next word written to the Transmit FIFO. * 0b110..Reserved. * 0b111..Reserved. */ #define ESAI_TFSR_NTFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFI_SHIFT)) & ESAI_TFSR_NTFI_MASK) #define ESAI_TFSR_NTFO_MASK (0x7000U) #define ESAI_TFSR_NTFO_SHIFT (12U) /*! NTFO - NTFO * 0b000..Transmitter #0 receives next word from the Transmit FIFO. * 0b001..Transmitter #1 receives next word from the Transmit FIFO. * 0b010..Transmitter #2 receives next word from the Transmit FIFO. * 0b011..Transmitter #3 receives next word from the Transmit FIFO. * 0b100..Transmitter #4 receives next word from the Transmit FIFO. * 0b101..Transmitter #5 receives next word from the Transmit FIFO. * 0b110..Reserved. * 0b111..Reserved. */ #define ESAI_TFSR_NTFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFO_SHIFT)) & ESAI_TFSR_NTFO_MASK) /*! @} */ /*! @name RFCR - Receive FIFO Configuration Register */ /*! @{ */ #define ESAI_RFCR_RFE_MASK (0x1U) #define ESAI_RFCR_RFE_SHIFT (0U) /*! RFE - RFE * 0b0..Receive FIFO disabled. * 0b1..Receive FIFO enabled. */ #define ESAI_RFCR_RFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFE_SHIFT)) & ESAI_RFCR_RFE_MASK) #define ESAI_RFCR_RFR_MASK (0x2U) #define ESAI_RFCR_RFR_SHIFT (1U) /*! RFR - RFR * 0b0..Receive FIFO not reset. * 0b1..Receive FIFO reset. */ #define ESAI_RFCR_RFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFR_SHIFT)) & ESAI_RFCR_RFR_MASK) #define ESAI_RFCR_RE0_MASK (0x4U) #define ESAI_RFCR_RE0_SHIFT (2U) /*! RE0 - RE0 * 0b0..Receiver #0 is not using the Receive FIFO. * 0b1..Receiver #0 is using the Receive FIFO. */ #define ESAI_RFCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE0_SHIFT)) & ESAI_RFCR_RE0_MASK) #define ESAI_RFCR_RE1_MASK (0x8U) #define ESAI_RFCR_RE1_SHIFT (3U) /*! RE1 - RE1 * 0b0..Receiver #1 is not using the Receive FIFO. * 0b1..Receiver #1 is using the Receive FIFO. */ #define ESAI_RFCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE1_SHIFT)) & ESAI_RFCR_RE1_MASK) #define ESAI_RFCR_RE2_MASK (0x10U) #define ESAI_RFCR_RE2_SHIFT (4U) /*! RE2 - RE2 * 0b0..Receiver #2 is not using the Receive FIFO. * 0b1..Receiver #2 is using the Receive FIFO. */ #define ESAI_RFCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE2_SHIFT)) & ESAI_RFCR_RE2_MASK) #define ESAI_RFCR_RE3_MASK (0x20U) #define ESAI_RFCR_RE3_SHIFT (5U) /*! RE3 - RE3 * 0b0..Receiver #3 is not using the Receive FIFO. * 0b1..Receiver #3 is using the Receive FIFO. */ #define ESAI_RFCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE3_SHIFT)) & ESAI_RFCR_RE3_MASK) #define ESAI_RFCR_RFWM_MASK (0xFF00U) #define ESAI_RFCR_RFWM_SHIFT (8U) /*! RFWM - RFWM */ #define ESAI_RFCR_RFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFWM_SHIFT)) & ESAI_RFCR_RFWM_MASK) #define ESAI_RFCR_RWA_MASK (0x70000U) #define ESAI_RFCR_RWA_SHIFT (16U) /*! RWA - RWA * 0b000..MSB of data is at bit 31. Data bits 7-0 are zeroed. * 0b001..MSB of data is at bit 27. Data bits 3-0 are zeroed. * 0b010..MSB of data is at bit 23. * 0b011..MSB of data is at bit 19. Data bits 3-0 from receive shift register are ignored. * 0b100..MSB of data is at bit 15. Data bits 7-0 from receive shift register are ignored. * 0b101..MSB of data is at bit 11. Data bits 11-0 from receive shift register are ignored. * 0b110..MSB of data is at bit 7. Data bits 15-0 from receive shift register are ignored. * 0b111..MSB of data is at bit 3. Data bits 19-0 from receive shift register are ignored. */ #define ESAI_RFCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RWA_SHIFT)) & ESAI_RFCR_RWA_MASK) #define ESAI_RFCR_REXT_MASK (0x80000U) #define ESAI_RFCR_REXT_SHIFT (19U) /*! REXT - REXT * 0b0..Receive data is zero extended. * 0b1..Receive data is sign extended. */ #define ESAI_RFCR_REXT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_REXT_SHIFT)) & ESAI_RFCR_REXT_MASK) /*! @} */ /*! @name RFSR - Receive FIFO Status Register */ /*! @{ */ #define ESAI_RFSR_RFCNT_MASK (0xFFU) #define ESAI_RFSR_RFCNT_SHIFT (0U) /*! RFCNT - RFCNT */ #define ESAI_RFSR_RFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_RFCNT_SHIFT)) & ESAI_RFSR_RFCNT_MASK) #define ESAI_RFSR_NRFO_MASK (0x300U) #define ESAI_RFSR_NRFO_SHIFT (8U) /*! NRFO - NRFO * 0b00..Receiver #0 returns next word from the Receive FIFO. * 0b01..Receiver #1 returns next word from the Receive FIFO. * 0b10..Receiver #2 returns next word from the Receive FIFO. * 0b11..Receiver #3 returns next word from the Receive FIFO. */ #define ESAI_RFSR_NRFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFO_SHIFT)) & ESAI_RFSR_NRFO_MASK) #define ESAI_RFSR_NRFI_MASK (0x3000U) #define ESAI_RFSR_NRFI_SHIFT (12U) /*! NRFI - NRFI * 0b00..Receiver #0 returns next word to the Receive FIFO. * 0b01..Receiver #1 returns next word to the Receive FIFO. * 0b10..Receiver #2 returns next word to the Receive FIFO. * 0b11..Receiver #3 returns next word to the Receive FIFO. */ #define ESAI_RFSR_NRFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFI_SHIFT)) & ESAI_RFSR_NRFI_MASK) /*! @} */ /*! @name TX - Transmit Data Register n */ /*! @{ */ #define ESAI_TX_TXn_MASK (0xFFFFFFU) #define ESAI_TX_TXn_SHIFT (0U) /*! TXn - TXn */ #define ESAI_TX_TXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TX_TXn_SHIFT)) & ESAI_TX_TXn_MASK) /*! @} */ /* The count of ESAI_TX */ #define ESAI_TX_COUNT (6U) /*! @name TSR - ESAI Transmit Slot Register */ /*! @{ */ #define ESAI_TSR_TSR_MASK (0xFFFFFFU) #define ESAI_TSR_TSR_SHIFT (0U) /*! TSR - TSR */ #define ESAI_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSR_TSR_SHIFT)) & ESAI_TSR_TSR_MASK) /*! @} */ /*! @name RX - Receive Data Register n */ /*! @{ */ #define ESAI_RX_RXn_MASK (0xFFFFFFU) #define ESAI_RX_RXn_SHIFT (0U) /*! RXn - RXn */ #define ESAI_RX_RXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RX_RXn_SHIFT)) & ESAI_RX_RXn_MASK) /*! @} */ /* The count of ESAI_RX */ #define ESAI_RX_COUNT (4U) /*! @name SAISR - Serial Audio Interface Status Register */ /*! @{ */ #define ESAI_SAISR_IF0_MASK (0x1U) #define ESAI_SAISR_IF0_SHIFT (0U) /*! IF0 - IF0 */ #define ESAI_SAISR_IF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF0_SHIFT)) & ESAI_SAISR_IF0_MASK) #define ESAI_SAISR_IF1_MASK (0x2U) #define ESAI_SAISR_IF1_SHIFT (1U) /*! IF1 - IF1 */ #define ESAI_SAISR_IF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF1_SHIFT)) & ESAI_SAISR_IF1_MASK) #define ESAI_SAISR_IF2_MASK (0x4U) #define ESAI_SAISR_IF2_SHIFT (2U) /*! IF2 - IF2 */ #define ESAI_SAISR_IF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF2_SHIFT)) & ESAI_SAISR_IF2_MASK) #define ESAI_SAISR_RFS_MASK (0x40U) #define ESAI_SAISR_RFS_SHIFT (6U) /*! RFS - RFS */ #define ESAI_SAISR_RFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RFS_SHIFT)) & ESAI_SAISR_RFS_MASK) #define ESAI_SAISR_ROE_MASK (0x80U) #define ESAI_SAISR_ROE_SHIFT (7U) /*! ROE - ROE */ #define ESAI_SAISR_ROE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_ROE_SHIFT)) & ESAI_SAISR_ROE_MASK) #define ESAI_SAISR_RDF_MASK (0x100U) #define ESAI_SAISR_RDF_SHIFT (8U) /*! RDF - RDF */ #define ESAI_SAISR_RDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RDF_SHIFT)) & ESAI_SAISR_RDF_MASK) #define ESAI_SAISR_REDF_MASK (0x200U) #define ESAI_SAISR_REDF_SHIFT (9U) /*! REDF - REDF */ #define ESAI_SAISR_REDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_REDF_SHIFT)) & ESAI_SAISR_REDF_MASK) #define ESAI_SAISR_RODF_MASK (0x400U) #define ESAI_SAISR_RODF_SHIFT (10U) /*! RODF - RODF */ #define ESAI_SAISR_RODF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RODF_SHIFT)) & ESAI_SAISR_RODF_MASK) #define ESAI_SAISR_TFS_MASK (0x2000U) #define ESAI_SAISR_TFS_SHIFT (13U) /*! TFS - TFS */ #define ESAI_SAISR_TFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TFS_SHIFT)) & ESAI_SAISR_TFS_MASK) #define ESAI_SAISR_TUE_MASK (0x4000U) #define ESAI_SAISR_TUE_SHIFT (14U) /*! TUE - TUE */ #define ESAI_SAISR_TUE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TUE_SHIFT)) & ESAI_SAISR_TUE_MASK) #define ESAI_SAISR_TDE_MASK (0x8000U) #define ESAI_SAISR_TDE_SHIFT (15U) /*! TDE - TDE */ #define ESAI_SAISR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TDE_SHIFT)) & ESAI_SAISR_TDE_MASK) #define ESAI_SAISR_TEDE_MASK (0x10000U) #define ESAI_SAISR_TEDE_SHIFT (16U) /*! TEDE - TEDE */ #define ESAI_SAISR_TEDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TEDE_SHIFT)) & ESAI_SAISR_TEDE_MASK) #define ESAI_SAISR_TODFE_MASK (0x20000U) #define ESAI_SAISR_TODFE_SHIFT (17U) /*! TODFE - TODFE */ #define ESAI_SAISR_TODFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TODFE_SHIFT)) & ESAI_SAISR_TODFE_MASK) /*! @} */ /*! @name SAICR - Serial Audio Interface Control Register */ /*! @{ */ #define ESAI_SAICR_OF0_MASK (0x1U) #define ESAI_SAICR_OF0_SHIFT (0U) /*! OF0 - OF0 */ #define ESAI_SAICR_OF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF0_SHIFT)) & ESAI_SAICR_OF0_MASK) #define ESAI_SAICR_OF1_MASK (0x2U) #define ESAI_SAICR_OF1_SHIFT (1U) /*! OF1 - OF1 */ #define ESAI_SAICR_OF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF1_SHIFT)) & ESAI_SAICR_OF1_MASK) #define ESAI_SAICR_OF2_MASK (0x4U) #define ESAI_SAICR_OF2_SHIFT (2U) /*! OF2 - OF2 */ #define ESAI_SAICR_OF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF2_SHIFT)) & ESAI_SAICR_OF2_MASK) #define ESAI_SAICR_SYN_MASK (0x40U) #define ESAI_SAICR_SYN_SHIFT (6U) /*! SYN - SYN */ #define ESAI_SAICR_SYN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_SYN_SHIFT)) & ESAI_SAICR_SYN_MASK) #define ESAI_SAICR_TEBE_MASK (0x80U) #define ESAI_SAICR_TEBE_SHIFT (7U) /*! TEBE - TEBE */ #define ESAI_SAICR_TEBE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_TEBE_SHIFT)) & ESAI_SAICR_TEBE_MASK) #define ESAI_SAICR_ALC_MASK (0x100U) #define ESAI_SAICR_ALC_SHIFT (8U) /*! ALC - ALC */ #define ESAI_SAICR_ALC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_ALC_SHIFT)) & ESAI_SAICR_ALC_MASK) /*! @} */ /*! @name TCR - Transmit Control Register */ /*! @{ */ #define ESAI_TCR_TE0_MASK (0x1U) #define ESAI_TCR_TE0_SHIFT (0U) /*! TE0 - TE0 */ #define ESAI_TCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE0_SHIFT)) & ESAI_TCR_TE0_MASK) #define ESAI_TCR_TE1_MASK (0x2U) #define ESAI_TCR_TE1_SHIFT (1U) /*! TE1 - TE1 */ #define ESAI_TCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE1_SHIFT)) & ESAI_TCR_TE1_MASK) #define ESAI_TCR_TE2_MASK (0x4U) #define ESAI_TCR_TE2_SHIFT (2U) /*! TE2 - TE2 */ #define ESAI_TCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE2_SHIFT)) & ESAI_TCR_TE2_MASK) #define ESAI_TCR_TE3_MASK (0x8U) #define ESAI_TCR_TE3_SHIFT (3U) /*! TE3 - TE3 */ #define ESAI_TCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE3_SHIFT)) & ESAI_TCR_TE3_MASK) #define ESAI_TCR_TE4_MASK (0x10U) #define ESAI_TCR_TE4_SHIFT (4U) /*! TE4 - TE4 */ #define ESAI_TCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE4_SHIFT)) & ESAI_TCR_TE4_MASK) #define ESAI_TCR_TE5_MASK (0x20U) #define ESAI_TCR_TE5_SHIFT (5U) /*! TE5 - TE5 */ #define ESAI_TCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE5_SHIFT)) & ESAI_TCR_TE5_MASK) #define ESAI_TCR_TSHFD_MASK (0x40U) #define ESAI_TCR_TSHFD_SHIFT (6U) /*! TSHFD - TSHFD */ #define ESAI_TCR_TSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSHFD_SHIFT)) & ESAI_TCR_TSHFD_MASK) #define ESAI_TCR_TWA_MASK (0x80U) #define ESAI_TCR_TWA_SHIFT (7U) /*! TWA - TWA */ #define ESAI_TCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TWA_SHIFT)) & ESAI_TCR_TWA_MASK) #define ESAI_TCR_TMOD_MASK (0x300U) #define ESAI_TCR_TMOD_SHIFT (8U) /*! TMOD - TMOD */ #define ESAI_TCR_TMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TMOD_SHIFT)) & ESAI_TCR_TMOD_MASK) #define ESAI_TCR_TSWS_MASK (0x7C00U) #define ESAI_TCR_TSWS_SHIFT (10U) /*! TSWS - TSWS */ #define ESAI_TCR_TSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSWS_SHIFT)) & ESAI_TCR_TSWS_MASK) #define ESAI_TCR_TFSL_MASK (0x8000U) #define ESAI_TCR_TFSL_SHIFT (15U) /*! TFSL - TFSL */ #define ESAI_TCR_TFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSL_SHIFT)) & ESAI_TCR_TFSL_MASK) #define ESAI_TCR_TFSR_MASK (0x10000U) #define ESAI_TCR_TFSR_SHIFT (16U) /*! TFSR - TFSR */ #define ESAI_TCR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSR_SHIFT)) & ESAI_TCR_TFSR_MASK) #define ESAI_TCR_PADC_MASK (0x20000U) #define ESAI_TCR_PADC_SHIFT (17U) /*! PADC - PADC */ #define ESAI_TCR_PADC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_PADC_SHIFT)) & ESAI_TCR_PADC_MASK) #define ESAI_TCR_TPR_MASK (0x80000U) #define ESAI_TCR_TPR_SHIFT (19U) /*! TPR - TPR */ #define ESAI_TCR_TPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TPR_SHIFT)) & ESAI_TCR_TPR_MASK) #define ESAI_TCR_TEIE_MASK (0x100000U) #define ESAI_TCR_TEIE_SHIFT (20U) /*! TEIE - TEIE */ #define ESAI_TCR_TEIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEIE_SHIFT)) & ESAI_TCR_TEIE_MASK) #define ESAI_TCR_TEDIE_MASK (0x200000U) #define ESAI_TCR_TEDIE_SHIFT (21U) /*! TEDIE - TEDIE */ #define ESAI_TCR_TEDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEDIE_SHIFT)) & ESAI_TCR_TEDIE_MASK) #define ESAI_TCR_TIE_MASK (0x400000U) #define ESAI_TCR_TIE_SHIFT (22U) /*! TIE - TIE */ #define ESAI_TCR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TIE_SHIFT)) & ESAI_TCR_TIE_MASK) #define ESAI_TCR_TLIE_MASK (0x800000U) #define ESAI_TCR_TLIE_SHIFT (23U) /*! TLIE - TLIE */ #define ESAI_TCR_TLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TLIE_SHIFT)) & ESAI_TCR_TLIE_MASK) /*! @} */ /*! @name TCCR - Transmit Clock Control Register */ /*! @{ */ #define ESAI_TCCR_TPM_MASK (0xFFU) #define ESAI_TCCR_TPM_SHIFT (0U) /*! TPM - TPM */ #define ESAI_TCCR_TPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPM_SHIFT)) & ESAI_TCCR_TPM_MASK) #define ESAI_TCCR_TPSR_MASK (0x100U) #define ESAI_TCCR_TPSR_SHIFT (8U) /*! TPSR - TPSR */ #define ESAI_TCCR_TPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPSR_SHIFT)) & ESAI_TCCR_TPSR_MASK) #define ESAI_TCCR_TDC_MASK (0x3E00U) #define ESAI_TCCR_TDC_SHIFT (9U) /*! TDC - TDC */ #define ESAI_TCCR_TDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TDC_SHIFT)) & ESAI_TCCR_TDC_MASK) #define ESAI_TCCR_TFP_MASK (0x3C000U) #define ESAI_TCCR_TFP_SHIFT (14U) /*! TFP - TFP */ #define ESAI_TCCR_TFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFP_SHIFT)) & ESAI_TCCR_TFP_MASK) #define ESAI_TCCR_TCKP_MASK (0x40000U) #define ESAI_TCCR_TCKP_SHIFT (18U) /*! TCKP - TCKP */ #define ESAI_TCCR_TCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKP_SHIFT)) & ESAI_TCCR_TCKP_MASK) #define ESAI_TCCR_TFSP_MASK (0x80000U) #define ESAI_TCCR_TFSP_SHIFT (19U) /*! TFSP - TFSP */ #define ESAI_TCCR_TFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSP_SHIFT)) & ESAI_TCCR_TFSP_MASK) #define ESAI_TCCR_THCKP_MASK (0x100000U) #define ESAI_TCCR_THCKP_SHIFT (20U) /*! THCKP - THCKP */ #define ESAI_TCCR_THCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKP_SHIFT)) & ESAI_TCCR_THCKP_MASK) #define ESAI_TCCR_TCKD_MASK (0x200000U) #define ESAI_TCCR_TCKD_SHIFT (21U) /*! TCKD - TCKD */ #define ESAI_TCCR_TCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKD_SHIFT)) & ESAI_TCCR_TCKD_MASK) #define ESAI_TCCR_TFSD_MASK (0x400000U) #define ESAI_TCCR_TFSD_SHIFT (22U) /*! TFSD - TFSD */ #define ESAI_TCCR_TFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSD_SHIFT)) & ESAI_TCCR_TFSD_MASK) #define ESAI_TCCR_THCKD_MASK (0x800000U) #define ESAI_TCCR_THCKD_SHIFT (23U) /*! THCKD - THCKD */ #define ESAI_TCCR_THCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKD_SHIFT)) & ESAI_TCCR_THCKD_MASK) /*! @} */ /*! @name RCR - Receive Control Register */ /*! @{ */ #define ESAI_RCR_RE0_MASK (0x1U) #define ESAI_RCR_RE0_SHIFT (0U) /*! RE0 - RE0 */ #define ESAI_RCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE0_SHIFT)) & ESAI_RCR_RE0_MASK) #define ESAI_RCR_RE1_MASK (0x2U) #define ESAI_RCR_RE1_SHIFT (1U) /*! RE1 - RE1 */ #define ESAI_RCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE1_SHIFT)) & ESAI_RCR_RE1_MASK) #define ESAI_RCR_RE2_MASK (0x4U) #define ESAI_RCR_RE2_SHIFT (2U) /*! RE2 - RE2 */ #define ESAI_RCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE2_SHIFT)) & ESAI_RCR_RE2_MASK) #define ESAI_RCR_RE3_MASK (0x8U) #define ESAI_RCR_RE3_SHIFT (3U) /*! RE3 - RE3 */ #define ESAI_RCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE3_SHIFT)) & ESAI_RCR_RE3_MASK) #define ESAI_RCR_RSHFD_MASK (0x40U) #define ESAI_RCR_RSHFD_SHIFT (6U) /*! RSHFD - RSHFD */ #define ESAI_RCR_RSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSHFD_SHIFT)) & ESAI_RCR_RSHFD_MASK) #define ESAI_RCR_RWA_MASK (0x80U) #define ESAI_RCR_RWA_SHIFT (7U) /*! RWA - RWA */ #define ESAI_RCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RWA_SHIFT)) & ESAI_RCR_RWA_MASK) #define ESAI_RCR_RMOD_MASK (0x300U) #define ESAI_RCR_RMOD_SHIFT (8U) /*! RMOD - RMOD */ #define ESAI_RCR_RMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RMOD_SHIFT)) & ESAI_RCR_RMOD_MASK) #define ESAI_RCR_RSWS_MASK (0x7C00U) #define ESAI_RCR_RSWS_SHIFT (10U) /*! RSWS - RSWS */ #define ESAI_RCR_RSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSWS_SHIFT)) & ESAI_RCR_RSWS_MASK) #define ESAI_RCR_RFSL_MASK (0x8000U) #define ESAI_RCR_RFSL_SHIFT (15U) /*! RFSL - RFSL */ #define ESAI_RCR_RFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSL_SHIFT)) & ESAI_RCR_RFSL_MASK) #define ESAI_RCR_RFSR_MASK (0x10000U) #define ESAI_RCR_RFSR_SHIFT (16U) /*! RFSR - RFSR */ #define ESAI_RCR_RFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSR_SHIFT)) & ESAI_RCR_RFSR_MASK) #define ESAI_RCR_RPR_MASK (0x80000U) #define ESAI_RCR_RPR_SHIFT (19U) /*! RPR - RPR */ #define ESAI_RCR_RPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RPR_SHIFT)) & ESAI_RCR_RPR_MASK) #define ESAI_RCR_REIE_MASK (0x100000U) #define ESAI_RCR_REIE_SHIFT (20U) /*! REIE - REIE */ #define ESAI_RCR_REIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REIE_SHIFT)) & ESAI_RCR_REIE_MASK) #define ESAI_RCR_REDIE_MASK (0x200000U) #define ESAI_RCR_REDIE_SHIFT (21U) /*! REDIE - REDIE */ #define ESAI_RCR_REDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REDIE_SHIFT)) & ESAI_RCR_REDIE_MASK) #define ESAI_RCR_RIE_MASK (0x400000U) #define ESAI_RCR_RIE_SHIFT (22U) /*! RIE - RIE */ #define ESAI_RCR_RIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RIE_SHIFT)) & ESAI_RCR_RIE_MASK) #define ESAI_RCR_RLIE_MASK (0x800000U) #define ESAI_RCR_RLIE_SHIFT (23U) /*! RLIE - RLIE */ #define ESAI_RCR_RLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RLIE_SHIFT)) & ESAI_RCR_RLIE_MASK) /*! @} */ /*! @name RCCR - Receive Clock Control Register */ /*! @{ */ #define ESAI_RCCR_RPM_MASK (0xFFU) #define ESAI_RCCR_RPM_SHIFT (0U) /*! RPM - RPM */ #define ESAI_RCCR_RPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPM_SHIFT)) & ESAI_RCCR_RPM_MASK) #define ESAI_RCCR_RPSR_MASK (0x100U) #define ESAI_RCCR_RPSR_SHIFT (8U) /*! RPSR - RPSR */ #define ESAI_RCCR_RPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPSR_SHIFT)) & ESAI_RCCR_RPSR_MASK) #define ESAI_RCCR_RDC_MASK (0x3E00U) #define ESAI_RCCR_RDC_SHIFT (9U) /*! RDC - RDC */ #define ESAI_RCCR_RDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RDC_SHIFT)) & ESAI_RCCR_RDC_MASK) #define ESAI_RCCR_RFP_MASK (0x3C000U) #define ESAI_RCCR_RFP_SHIFT (14U) /*! RFP - RFP */ #define ESAI_RCCR_RFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFP_SHIFT)) & ESAI_RCCR_RFP_MASK) #define ESAI_RCCR_RCKP_MASK (0x40000U) #define ESAI_RCCR_RCKP_SHIFT (18U) /*! RCKP - RCKP */ #define ESAI_RCCR_RCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKP_SHIFT)) & ESAI_RCCR_RCKP_MASK) #define ESAI_RCCR_RFSP_MASK (0x80000U) #define ESAI_RCCR_RFSP_SHIFT (19U) /*! RFSP - RFSP */ #define ESAI_RCCR_RFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSP_SHIFT)) & ESAI_RCCR_RFSP_MASK) #define ESAI_RCCR_RHCKP_MASK (0x100000U) #define ESAI_RCCR_RHCKP_SHIFT (20U) /*! RHCKP - RHCKP */ #define ESAI_RCCR_RHCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKP_SHIFT)) & ESAI_RCCR_RHCKP_MASK) #define ESAI_RCCR_RCKD_MASK (0x200000U) #define ESAI_RCCR_RCKD_SHIFT (21U) /*! RCKD - RCKD */ #define ESAI_RCCR_RCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKD_SHIFT)) & ESAI_RCCR_RCKD_MASK) #define ESAI_RCCR_RFSD_MASK (0x400000U) #define ESAI_RCCR_RFSD_SHIFT (22U) /*! RFSD - RFSD */ #define ESAI_RCCR_RFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSD_SHIFT)) & ESAI_RCCR_RFSD_MASK) #define ESAI_RCCR_RHCKD_MASK (0x800000U) #define ESAI_RCCR_RHCKD_SHIFT (23U) /*! RHCKD - RHCKD */ #define ESAI_RCCR_RHCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKD_SHIFT)) & ESAI_RCCR_RHCKD_MASK) /*! @} */ /*! @name TSMA - Transmit Slot Mask Register A */ /*! @{ */ #define ESAI_TSMA_TS_MASK (0xFFFFU) #define ESAI_TSMA_TS_SHIFT (0U) /*! TS - Lower 16 bits of TS */ #define ESAI_TSMA_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMA_TS_SHIFT)) & ESAI_TSMA_TS_MASK) /*! @} */ /*! @name TSMB - Transmit Slot Mask Register B */ /*! @{ */ #define ESAI_TSMB_TS_MASK (0xFFFFU) #define ESAI_TSMB_TS_SHIFT (0U) /*! TS - TS */ #define ESAI_TSMB_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMB_TS_SHIFT)) & ESAI_TSMB_TS_MASK) /*! @} */ /*! @name RSMA - Receive Slot Mask Register A */ /*! @{ */ #define ESAI_RSMA_RS_MASK (0xFFFFU) #define ESAI_RSMA_RS_SHIFT (0U) /*! RS - RS */ #define ESAI_RSMA_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMA_RS_SHIFT)) & ESAI_RSMA_RS_MASK) /*! @} */ /*! @name RSMB - Receive Slot Mask Register B */ /*! @{ */ #define ESAI_RSMB_RS_MASK (0xFFFFU) #define ESAI_RSMB_RS_SHIFT (0U) /*! RS - RS */ #define ESAI_RSMB_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMB_RS_SHIFT)) & ESAI_RSMB_RS_MASK) /*! @} */ /*! @name PRRC - Port C Direction Register */ /*! @{ */ #define ESAI_PRRC_PDC_MASK (0xFFFU) #define ESAI_PRRC_PDC_SHIFT (0U) /*! PDC - PDC */ #define ESAI_PRRC_PDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PRRC_PDC_SHIFT)) & ESAI_PRRC_PDC_MASK) /*! @} */ /*! @name PCRC - Port C Control Register */ /*! @{ */ #define ESAI_PCRC_PC_MASK (0xFFFU) #define ESAI_PCRC_PC_SHIFT (0U) /*! PC - PC */ #define ESAI_PCRC_PC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PCRC_PC_SHIFT)) & ESAI_PCRC_PC_MASK) /*! @} */ /*! * @} */ /* end of group ESAI_Register_Masks */ /* ESAI - Peripheral instance base addresses */ /** Peripheral ADMA__ESAI0 base address */ #define ADMA__ESAI0_BASE (0x59010000u) /** Peripheral ADMA__ESAI0 base pointer */ #define ADMA__ESAI0 ((ESAI_Type *)ADMA__ESAI0_BASE) /** Array initializer of ESAI peripheral base addresses */ #define ESAI_BASE_ADDRS { ADMA__ESAI0_BASE } /** Array initializer of ESAI peripheral base pointers */ #define ESAI_BASE_PTRS { ADMA__ESAI0 } /** Interrupt vectors for the ESAI peripheral type */ #define ESAI_IRQS { ADMA_ESAI0_INT_IRQn } /*! * @} */ /* end of group ESAI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FLEXSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer * @{ */ /** FLEXSPI - Register Layout Typedef */ typedef struct { __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ __IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; __IO uint32_t FLSHCR0[4]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */ __IO uint32_t FLSHCR1[4]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */ __IO uint32_t FLSHCR2[4]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ uint8_t RESERVED_2[8]; __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ uint8_t RESERVED_3[8]; __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */ __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[24]; __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ uint8_t RESERVED_5[8]; __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ __IO uint32_t LUT[128]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */ } FLEXSPI_Type; /* ---------------------------------------------------------------------------- -- FLEXSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks * @{ */ /*! @name MCR0 - Module Control Register 0 */ /*! @{ */ #define FLEXSPI_MCR0_SWRESET_MASK (0x1U) #define FLEXSPI_MCR0_SWRESET_SHIFT (0U) /*! SWRESET - Software Reset */ #define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) #define FLEXSPI_MCR0_MDIS_MASK (0x2U) #define FLEXSPI_MCR0_MDIS_SHIFT (1U) /*! MDIS - Module Disable */ #define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) /*! RXCLKSRC - Sample Clock source selection for Flash Reading * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. * 0b10..Reserved * 0b11..Flash provided Read strobe and input from DQS pad */ #define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) #define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) #define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) /*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. */ #define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) #define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) #define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) /*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. */ #define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) #define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) #define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) /*! SERCLKDIV - The serial root clock could be divided inside FlexSPI wrapper. Refer Clocks chapter for more details on clocking. * 0b000..Divided by 1 * 0b001..Divided by 2 * 0b010..Divided by 3 * 0b011..Divided by 4 * 0b100..Divided by 5 * 0b101..Divided by 6 * 0b110..Divided by 7 * 0b111..Divided by 8 */ #define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) #define FLEXSPI_MCR0_HSEN_MASK (0x800U) #define FLEXSPI_MCR0_HSEN_SHIFT (11U) /*! HSEN - Half Speed Serial Flash access Enable. * 0b0..Disable divide by 2 of serial flash clock for half speed commands. * 0b1..Enable divide by 2 of serial flash clock for half speed commands. */ #define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) #define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) #define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) /*! DOZEEN - Doze mode enable bit * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. */ #define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) #define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) /*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]). * 0b0..Disable. * 0b1..Enable. */ #define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) /*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is * enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). * 0b0..Disable. * 0b1..Enable. */ #define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) #define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U) #define FLEXSPI_MCR0_LEARNEN_SHIFT (15U) /*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is * disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction * is correctly executed. * 0b0..Disable. * 0b1..Enable. */ #define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK) #define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) /*! IPGRANTWAIT - Time out wait cycle for IP command grant. */ #define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) /*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant. */ #define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) /*! @} */ /*! @name MCR1 - Module Control Register 1 */ /*! @{ */ #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) /*! @} */ /*! @name MCR2 - Module Control Register 2 */ /*! @{ */ #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) /*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned * automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP * mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. */ #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) /*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is * written with 0x1. This bit will be auto-cleared immediately. */ #define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) /*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash * A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be * ignored. * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. */ #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) /*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to * A_SCLK). In this case, port B flash access is not available. After changing the value of this * field, MCR0[SWRESET] should be set. * 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. * 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available. */ #define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) #define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) /*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. */ #define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) /*! @} */ /*! @name AHBCR - AHB Bus Control Register */ /*! @{ */ #define FLEXSPI_AHBCR_APAREN_MASK (0x1U) #define FLEXSPI_AHBCR_APAREN_SHIFT (0U) /*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . * 0b0..Flash will be accessed in Individual mode. * 0b1..Flash will be accessed in Parallel mode. */ #define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) #define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) /*! CACHABLEEN - Enable AHB bus cachable read access support. * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. */ #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) /*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat * of AHB write access, refer for more details about AHB bufferable write. * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus * ready after all data is transmitted to External device and AHB command finished. * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is * granted by arbitrator and will not wait for AHB command finished. */ #define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) #define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) /*! PREFETCHEN - AHB Read Prefetch Enable. */ #define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) /*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB * burst required to meet the alignment requirement. */ #define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable Register */ /*! @{ */ #define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) /*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable. */ #define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) #define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) /*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable. */ #define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) #define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) /*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable. */ #define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) #define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) #define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) /*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable. */ #define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) #define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) /*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable. */ #define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) #define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) #define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) /*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable. */ #define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) #define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) #define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) /*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable. */ #define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) #define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) #define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) /*! DATALEARNFAILEN - Data Learning failed interrupt enable. */ #define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK) #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) /*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. */ #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) /*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. */ #define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) /*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. */ #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) /*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. */ #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) /*! @} */ /*! @name INTR - Interrupt Register */ /*! @{ */ #define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) /*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also * generated when there is IPCMDGE or IPCMDERR interrupt generated. */ #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) #define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) #define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) /*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt. */ #define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) #define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) /*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt. */ #define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) #define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) #define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) /*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for * IP command, this command will be ignored and not executed at all. */ #define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) #define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) #define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) /*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for * AHB command, this command will be ignored and not executed at all. */ #define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) #define FLEXSPI_INTR_IPRXWA_MASK (0x20U) #define FLEXSPI_INTR_IPRXWA_SHIFT (5U) /*! IPRXWA - IP RX FIFO watermark available interrupt. */ #define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) #define FLEXSPI_INTR_IPTXWE_MASK (0x40U) #define FLEXSPI_INTR_IPTXWE_SHIFT (6U) /*! IPTXWE - IP TX FIFO watermark empty interrupt. */ #define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) #define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U) #define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) /*! DATALEARNFAIL - Data Learning failed interrupt. */ #define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) #define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) /*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt. */ #define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) #define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) /*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt. */ #define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) #define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) #define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) /*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details. */ #define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) #define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) /*! SEQTIMEOUT - Sequence execution timeout interrupt. */ #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) /*! @} */ /*! @name LUTKEY - LUT Key Register */ /*! @{ */ #define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) #define FLEXSPI_LUTKEY_KEY_SHIFT (0U) /*! KEY - The Key to lock or unlock LUT. */ #define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) /*! @} */ /*! @name LUTCR - LUT Control Register */ /*! @{ */ #define FLEXSPI_LUTCR_LOCK_MASK (0x1U) #define FLEXSPI_LUTCR_LOCK_SHIFT (0U) /*! LOCK - Lock LUT */ #define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) #define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) #define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) /*! UNLOCK - Unlock LUT */ #define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) /*! @} */ /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */ /*! @{ */ #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) /*! BUFSZ - AHB RX Buffer Size in 64 bits. */ #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) /*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). */ #define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) /*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. */ #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) /*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. */ #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ /* The count of FLEXSPI_AHBRXBUFCR0 */ #define FLEXSPI_AHBRXBUFCR0_COUNT (8U) /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ #define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) /*! FLSHSZ - Flash Size in KByte. */ #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) /*! @} */ /* The count of FLEXSPI_FLSHCR0 */ #define FLEXSPI_FLSHCR0_COUNT (4U) /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ #define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) #define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) /*! TCSS - Serial Flash CS setup time. */ #define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) #define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) #define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) /*! TCSH - Serial Flash CS Hold time. */ #define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) #define FLEXSPI_FLSHCR1_WA_MASK (0x400U) #define FLEXSPI_FLSHCR1_WA_SHIFT (10U) /*! WA - Word Addressable. */ #define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) #define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) #define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) /*! CAS - Column Address Size. */ #define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) /*! CSINTERVALUNIT - CS interval unit * 0b0..The CS interval unit is 1 serial clock cycle * 0b1..The CS interval unit is 256 serial clock cycle */ #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) /*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection * deassertion and flash device Chip selection assertion. If external flash has a limitation on * the interval between command sequences, this field should be set accordingly. If there is no * limitation, set this field with value 0x0. */ #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ /* The count of FLEXSPI_FLSHCR1 */ #define FLEXSPI_FLSHCR1_COUNT (4U) /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ #define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0x1FU) #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) /*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT. */ #define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) /*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT. */ #define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) #define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U) #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) /*! AWRSEQID - Sequence Index for AHB Write triggered Command. */ #define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) /*! AWRSEQNUM - Sequence Number for AHB Write triggered Command. */ #define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) #define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) #define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) /*! AWRWAITUNIT - AWRWAIT unit * 0b000..The AWRWAIT unit is 2 ahb clock cycle * 0b001..The AWRWAIT unit is 8 ahb clock cycle * 0b010..The AWRWAIT unit is 32 ahb clock cycle * 0b011..The AWRWAIT unit is 128 ahb clock cycle * 0b100..The AWRWAIT unit is 512 ahb clock cycle * 0b101..The AWRWAIT unit is 2048 ahb clock cycle * 0b110..The AWRWAIT unit is 8192 ahb clock cycle * 0b111..The AWRWAIT unit is 32768 ahb clock cycle */ #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) /*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. * Refer Programmable Sequence Engine for details. */ #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ /* The count of FLEXSPI_FLSHCR2 */ #define FLEXSPI_FLSHCR2_COUNT (4U) /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) /*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write * burst start address alignment when flash is accessed in individual mode. * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write * burst start address alignment when flash is accessed in individual mode. */ #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) #define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) #define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for * memory device on port A, this bit must be set. * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. */ #define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) #define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) #define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for * memory device on port B, this bit must be set. * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. */ #define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) /*! @} */ /*! @name IPCR0 - IP Control Register 0 */ /*! @{ */ #define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) #define FLEXSPI_IPCR0_SFAR_SHIFT (0U) /*! SFAR - Serial Flash Address for IP command. */ #define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) /*! @} */ /*! @name IPCR1 - IP Control Register 1 */ /*! @{ */ #define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) #define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) /*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command. */ #define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) #define FLEXSPI_IPCR1_ISEQID_MASK (0x1F0000U) #define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) /*! ISEQID - Sequence Index in LUT for IP command. */ #define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) #define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) #define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */ #define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) #define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) #define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) /*! IPAREN - Parallel mode Enabled for IP command. * 0b0..Flash will be accessed in Individual mode. * 0b1..Flash will be accessed in Parallel mode. */ #define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) /*! @} */ /*! @name IPCMD - IP Command Register */ /*! @{ */ #define FLEXSPI_IPCMD_TRG_MASK (0x1U) #define FLEXSPI_IPCMD_TRG_SHIFT (0U) /*! TRG - Setting this bit will trigger an IP Command. */ #define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) /*! @} */ /*! @name DLPR - Data Learn Pattern Register */ /*! @{ */ #define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU) #define FLEXSPI_DLPR_DLP_SHIFT (0U) /*! DLP - Data Learning Pattern. */ #define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK) /*! @} */ /*! @name IPRXFCR - IP RX FIFO Control Register */ /*! @{ */ #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) /*! CLRIPRXF - Clear all valid data entries in IP RX FIFO. */ #define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) #define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) /*! RXDMAEN - IP RX FIFO reading by DMA enabled. * 0b0..IP RX FIFO would be read by processor. * 0b1..IP RX FIFO would be read by DMA. */ #define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0xFCU) #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) /*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits. */ #define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) /*! @} */ /*! @name IPTXFCR - IP TX FIFO Control Register */ /*! @{ */ #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) /*! CLRIPTXF - Clear all valid data entries in IP TX FIFO. */ #define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) #define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) /*! TXDMAEN - IP TX FIFO filling by DMA enabled. * 0b0..IP TX FIFO would be filled by processor. * 0b1..IP TX FIFO would be filled by DMA. */ #define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) #define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) /*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits. */ #define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) /*! @} */ /*! @name DLLCR - DLL Control Register 0 */ /*! @{ */ #define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) #define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) /*! DLLEN - DLL calibration enable. */ #define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) #define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) #define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) /*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the * DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset * action is edge triggered, so software need to clear this bit after set this bit (no delay * limitation). */ #define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) /*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). */ #define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) #define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) #define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) /*! OVRDEN - Slave clock delay line delay cell number selection override enable. */ #define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) #define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) /*! OVRDVAL - Slave clock delay line delay cell number selection override value. */ #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) /*! @} */ /* The count of FLEXSPI_DLLCR */ #define FLEXSPI_DLLCR_COUNT (2U) /*! @name STS0 - Status Register 0 */ /*! @{ */ #define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) #define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) /*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command * sequence executing on FlexSPI interface. */ #define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) #define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) #define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) /*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command * sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state * (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So * this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. */ #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). * 0b00..Triggered by AHB read command (triggered by AHB read). * 0b01..Triggered by AHB write command (triggered by AHB Write). * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). * 0b11..Triggered by suspended command (resumed). */ #define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) #define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) #define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U) /*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning. */ #define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK) #define FLEXSPI_STS0_DATALEARNPHASEB_MASK (0xF00U) #define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT (8U) /*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning. */ #define FLEXSPI_STS0_DATALEARNPHASEB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK) /*! @} */ /*! @name STS1 - Status Register 1 */ /*! @{ */ #define FLEXSPI_STS1_AHBCMDERRID_MASK (0x1FU) #define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) /*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field * will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). */ #define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be * cleared when INTR[AHBCMDERR] is write-1-clear(w1c). * 0b0000..No error. * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. * 0b0011..There is unknown instruction opcode in the sequence. * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. * 0b1110..Sequence execution timeout. */ #define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) #define FLEXSPI_STS1_IPCMDERRID_MASK (0x1F0000U) #define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) /*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be * cleared when INTR[IPCMDERR] is write-1-clear(w1c). */ #define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) #define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) /*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be * cleared when INTR[IPCMDERR] is write-1-clear(w1c). * 0b0000..No error. * 0b0010..IP command with JMP_ON_CS instruction used in the sequence. * 0b0011..There is unknown instruction opcode in the sequence. * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). * 0b1110..Sequence execution timeout. * 0b1111..Flash boundary crossed. */ #define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) /*! @} */ /*! @name STS2 - Status Register 2 */ /*! @{ */ #define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) #define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) /*! ASLVLOCK - Flash A sample clock slave delay line locked. */ #define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) #define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) #define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) /*! AREFLOCK - Flash A sample clock reference delay line locked. */ #define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) #define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) #define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) /*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection . */ #define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) #define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) #define FLEXSPI_STS2_AREFSEL_SHIFT (8U) /*! AREFSEL - Flash A sample clock reference delay line delay cell number selection. */ #define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) #define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) #define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) /*! BSLVLOCK - Flash B sample clock slave delay line locked. */ #define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) #define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) #define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) /*! BREFLOCK - Flash B sample clock reference delay line locked. */ #define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) #define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) #define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) /*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection. */ #define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) #define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) #define FLEXSPI_STS2_BREFSEL_SHIFT (24U) /*! BREFSEL - Flash B sample clock reference delay line delay cell number selection. */ #define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) /*! @} */ /*! @name AHBSPNDSTS - AHB Suspend Status Register */ /*! @{ */ #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) /*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended. */ #define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) #define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) /*! BUFID - AHB RX BUF ID for suspended command sequence. */ #define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) /*! DATLFT - Left Data size for suspended command sequence (in byte). */ #define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) /*! @} */ /*! @name IPRXFSTS - IP RX FIFO Status Register */ /*! @{ */ #define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) /*! FILL - Fill level of IP RX FIFO. */ #define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) #define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) /*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits. */ #define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) /*! @} */ /*! @name IPTXFSTS - IP TX FIFO Status Register */ /*! @{ */ #define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) /*! FILL - Fill level of IP TX FIFO. */ #define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) #define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) /*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits. */ #define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) /*! @} */ /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ /*! @{ */ #define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_RFDR_RXDATA_SHIFT (0U) /*! RXDATA - RX Data */ #define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) /*! @} */ /* The count of FLEXSPI_RFDR */ #define FLEXSPI_RFDR_COUNT (32U) /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ /*! @{ */ #define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_TFDR_TXDATA_SHIFT (0U) /*! TXDATA - TX Data */ #define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) /*! @} */ /* The count of FLEXSPI_TFDR */ #define FLEXSPI_TFDR_COUNT (32U) /*! @name LUT - LUT 0..LUT 127 */ /*! @{ */ #define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) #define FLEXSPI_LUT_OPERAND0_SHIFT (0U) /*! OPERAND0 - OPERAND0 */ #define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) #define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) #define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) /*! NUM_PADS0 - NUM_PADS0 */ #define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) #define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) #define FLEXSPI_LUT_OPCODE0_SHIFT (10U) /*! OPCODE0 - OPCODE */ #define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) #define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) #define FLEXSPI_LUT_OPERAND1_SHIFT (16U) /*! OPERAND1 - OPERAND1 */ #define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) #define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) #define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) /*! NUM_PADS1 - NUM_PADS1 */ #define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) #define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) #define FLEXSPI_LUT_OPCODE1_SHIFT (26U) /*! OPCODE1 - OPCODE1 */ #define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) /*! @} */ /* The count of FLEXSPI_LUT */ #define FLEXSPI_LUT_COUNT (128U) /*! * @} */ /* end of group FLEXSPI_Register_Masks */ /* FLEXSPI - Peripheral instance base addresses */ /** Peripheral LSIO__FLEXSPI0 base address */ #define LSIO__FLEXSPI0_BASE (0x5D120000u) /** Peripheral LSIO__FLEXSPI0 base pointer */ #define LSIO__FLEXSPI0 ((FLEXSPI_Type *)LSIO__FLEXSPI0_BASE) /** Peripheral LSIO__FLEXSPI1 base address */ #define LSIO__FLEXSPI1_BASE (0x5D130000u) /** Peripheral LSIO__FLEXSPI1 base pointer */ #define LSIO__FLEXSPI1 ((FLEXSPI_Type *)LSIO__FLEXSPI1_BASE) /** Array initializer of FLEXSPI peripheral base addresses */ #define FLEXSPI_BASE_ADDRS { LSIO__FLEXSPI0_BASE, LSIO__FLEXSPI1_BASE } /** Array initializer of FLEXSPI peripheral base pointers */ #define FLEXSPI_BASE_PTRS { LSIO__FLEXSPI0, LSIO__FLEXSPI1 } /** Interrupt vectors for the FLEXSPI peripheral type */ #define FLEXSPI_IRQS { LSIO_OCTASPI0_INT_IRQn, LSIO_OCTASPI1_INT_IRQn } /* FlexSPI0 AMBA address. */ #define FlexSPI0_AMBA_BASE (0x08000000U) /*! * @} */ /* end of group FLEXSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FTM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer * @{ */ /** FTM - Register Layout Typedef */ typedef struct { __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ __IO uint32_t CNT; /**< Counter, offset: 0x4 */ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ struct { /* offset: 0xC, array step: 0x8 */ __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ } CONTROLS[8]; __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ __IO uint32_t DEADTIME; /**< Deadtime Configuration, offset: 0x68 */ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ __IO uint32_t HCR; /**< Half Cycle Register, offset: 0x9C */ uint8_t RESERVED_0[352]; __IO uint32_t MOD_MIRROR; /**< Mirror of Modulo Value, offset: 0x200 */ __IO uint32_t CV_MIRROR[8]; /**< Mirror of Channel (n) Match Value, array offset: 0x204, array step: 0x4 */ } FTM_Type; /* ---------------------------------------------------------------------------- -- FTM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FTM_Register_Masks FTM Register Masks * @{ */ /*! @name SC - Status And Control */ /*! @{ */ #define FTM_SC_PS_MASK (0x7U) #define FTM_SC_PS_SHIFT (0U) /*! PS - Prescale Factor Selection * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) #define FTM_SC_CLKS_MASK (0x18U) #define FTM_SC_CLKS_SHIFT (3U) /*! CLKS - Clock Source Selection * 0b00..No clock selected. This in effect disables the FTM counter. * 0b01..FTM input clock * 0b10..Fixed frequency clock * 0b11..External clock */ #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) #define FTM_SC_CPWMS_MASK (0x20U) #define FTM_SC_CPWMS_SHIFT (5U) /*! CPWMS - Center-Aligned PWM Select * 0b0..FTM counter operates in Up Counting mode. * 0b1..FTM counter operates in Up-Down Counting mode. */ #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) #define FTM_SC_RIE_MASK (0x40U) #define FTM_SC_RIE_SHIFT (6U) /*! RIE - Reload Point Interrupt Enable * 0b0..Reload point interrupt is disabled. * 0b1..Reload point interrupt is enabled. */ #define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RIE_SHIFT)) & FTM_SC_RIE_MASK) #define FTM_SC_RF_MASK (0x80U) #define FTM_SC_RF_SHIFT (7U) /*! RF - Reload Flag * 0b0..A selected reload point did not happen. * 0b1..A selected reload point happened. */ #define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RF_SHIFT)) & FTM_SC_RF_MASK) #define FTM_SC_TOIE_MASK (0x100U) #define FTM_SC_TOIE_SHIFT (8U) /*! TOIE - Timer Overflow Interrupt Enable * 0b0..Disable TOF interrupts. Use software polling. * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. */ #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) #define FTM_SC_TOF_MASK (0x200U) #define FTM_SC_TOF_SHIFT (9U) /*! TOF - Timer Overflow Flag * 0b0..FTM counter has not overflowed. * 0b1..FTM counter has overflowed. */ #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) #define FTM_SC_PWMEN0_MASK (0x10000U) #define FTM_SC_PWMEN0_SHIFT (16U) /*! PWMEN0 - Channel 0 PWM enable bit * 0b0..Channel output port is disabled. * 0b1..Channel output port is enabled. */ #define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN0_SHIFT)) & FTM_SC_PWMEN0_MASK) #define FTM_SC_PWMEN1_MASK (0x20000U) #define FTM_SC_PWMEN1_SHIFT (17U) /*! PWMEN1 - Channel 1 PWM enable bit * 0b0..Channel output port is disabled. * 0b1..Channel output port is enabled. */ #define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN1_SHIFT)) & FTM_SC_PWMEN1_MASK) #define FTM_SC_PWMEN2_MASK (0x40000U) #define FTM_SC_PWMEN2_SHIFT (18U) /*! PWMEN2 - Channel 2 PWM enable bit * 0b0..Channel output port is disabled. * 0b1..Channel output port is enabled. */ #define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN2_SHIFT)) & FTM_SC_PWMEN2_MASK) #define FTM_SC_PWMEN3_MASK (0x80000U) #define FTM_SC_PWMEN3_SHIFT (19U) /*! PWMEN3 - Channel 3 PWM enable bit * 0b0..Channel output port is disabled. * 0b1..Channel output port is enabled. */ #define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN3_SHIFT)) & FTM_SC_PWMEN3_MASK) #define FTM_SC_PWMEN4_MASK (0x100000U) #define FTM_SC_PWMEN4_SHIFT (20U) /*! PWMEN4 - Channel 4 PWM enable bit * 0b0..Channel output port is disabled. * 0b1..Channel output port is enabled. */ #define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN4_SHIFT)) & FTM_SC_PWMEN4_MASK) #define FTM_SC_PWMEN5_MASK (0x200000U) #define FTM_SC_PWMEN5_SHIFT (21U) /*! PWMEN5 - Channel 5 PWM enable bit * 0b0..Channel output port is disabled. * 0b1..Channel output port is enabled. */ #define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN5_SHIFT)) & FTM_SC_PWMEN5_MASK) #define FTM_SC_PWMEN6_MASK (0x400000U) #define FTM_SC_PWMEN6_SHIFT (22U) /*! PWMEN6 - Channel 6 PWM enable bit * 0b0..Channel output port is disabled. * 0b1..Channel output port is enabled. */ #define FTM_SC_PWMEN6(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN6_SHIFT)) & FTM_SC_PWMEN6_MASK) #define FTM_SC_PWMEN7_MASK (0x800000U) #define FTM_SC_PWMEN7_SHIFT (23U) /*! PWMEN7 - Channel 7 PWM enable bit * 0b0..Channel output port is disabled. * 0b1..Channel output port is enabled. */ #define FTM_SC_PWMEN7(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN7_SHIFT)) & FTM_SC_PWMEN7_MASK) #define FTM_SC_FLTPS_MASK (0xF000000U) #define FTM_SC_FLTPS_SHIFT (24U) /*! FLTPS - Filter Prescaler * 0b0000..Divide by 1 * 0b0001..Divide by 2 * 0b0010..Divide by 3 * 0b0011..Divide by 4 * 0b0100..Divide by 5 * 0b0101..Divide by 6 * 0b0110..Divide by 7 * 0b0111..Divide by 8 * 0b1000..Divide by 9 * 0b1001..Divide by 10 * 0b1010..Divide by 11 * 0b1011..Divide by 12 * 0b1100..Divide by 13 * 0b1101..Divide by 14 * 0b1110..Divide by 15 * 0b1111..Divide by 16 */ #define FTM_SC_FLTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_FLTPS_SHIFT)) & FTM_SC_FLTPS_MASK) /*! @} */ /*! @name CNT - Counter */ /*! @{ */ #define FTM_CNT_COUNT_MASK (0xFFFFU) #define FTM_CNT_COUNT_SHIFT (0U) /*! COUNT - Counter Value */ #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) /*! @} */ /*! @name MOD - Modulo */ /*! @{ */ #define FTM_MOD_MOD_MASK (0xFFFFU) #define FTM_MOD_MOD_SHIFT (0U) /*! MOD - MOD */ #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) /*! @} */ /*! @name CnSC - Channel (n) Status And Control */ /*! @{ */ #define FTM_CnSC_DMA_MASK (0x1U) #define FTM_CnSC_DMA_SHIFT (0U) /*! DMA - DMA Enable * 0b0..Disable DMA transfers. * 0b1..Enable DMA transfers. */ #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) #define FTM_CnSC_ICRST_MASK (0x2U) #define FTM_CnSC_ICRST_SHIFT (1U) /*! ICRST - FTM counter reset by the selected input capture event. * 0b0..FTM counter is not reset when the selected channel (n) input event is detected. * 0b1..FTM counter is reset when the selected channel (n) input event is detected. */ #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK) #define FTM_CnSC_ELSA_MASK (0x4U) #define FTM_CnSC_ELSA_SHIFT (2U) /*! ELSA - Channel (n) Edge or Level Select */ #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) #define FTM_CnSC_ELSB_MASK (0x8U) #define FTM_CnSC_ELSB_SHIFT (3U) /*! ELSB - Channel (n) Edge or Level Select */ #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) #define FTM_CnSC_MSA_MASK (0x10U) #define FTM_CnSC_MSA_SHIFT (4U) /*! MSA - Channel (n) Mode Select */ #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) #define FTM_CnSC_MSB_MASK (0x20U) #define FTM_CnSC_MSB_SHIFT (5U) /*! MSB - Channel (n) Mode Select */ #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) #define FTM_CnSC_CHIE_MASK (0x40U) #define FTM_CnSC_CHIE_SHIFT (6U) /*! CHIE - Channel (n) Interrupt Enable * 0b0..Disable channel (n) interrupt. Use software polling. * 0b1..Enable channel (n) interrupt. */ #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) #define FTM_CnSC_CHF_MASK (0x80U) #define FTM_CnSC_CHF_SHIFT (7U) /*! CHF - Channel (n) Flag * 0b0..No channel (n) event has occurred. * 0b1..A channel (n) event has occurred. */ #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) #define FTM_CnSC_TRIGMODE_MASK (0x100U) #define FTM_CnSC_TRIGMODE_SHIFT (8U) /*! TRIGMODE - Trigger mode control * 0b0..Channel outputs will generate the normal PWM outputs without generating a pulse. * 0b1..If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. */ #define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_TRIGMODE_SHIFT)) & FTM_CnSC_TRIGMODE_MASK) #define FTM_CnSC_CHIS_MASK (0x200U) #define FTM_CnSC_CHIS_SHIFT (9U) /*! CHIS - Channel (n) Input State * 0b0..The channel (n) input is zero. * 0b1..The channel (n) input is one. */ #define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIS_SHIFT)) & FTM_CnSC_CHIS_MASK) #define FTM_CnSC_CHOV_MASK (0x400U) #define FTM_CnSC_CHOV_SHIFT (10U) /*! CHOV - Channel (n) Output Value * 0b0..The channel (n) output is zero. * 0b1..The channel (n) output is one. */ #define FTM_CnSC_CHOV(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHOV_SHIFT)) & FTM_CnSC_CHOV_MASK) /*! @} */ /* The count of FTM_CnSC */ #define FTM_CnSC_COUNT (8U) /*! @name CnV - Channel (n) Value */ /*! @{ */ #define FTM_CnV_VAL_MASK (0xFFFFU) #define FTM_CnV_VAL_SHIFT (0U) /*! VAL - Channel Value */ #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) /*! @} */ /* The count of FTM_CnV */ #define FTM_CnV_COUNT (8U) /*! @name CNTIN - Counter Initial Value */ /*! @{ */ #define FTM_CNTIN_INIT_MASK (0xFFFFU) #define FTM_CNTIN_INIT_SHIFT (0U) /*! INIT - INIT */ #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) /*! @} */ /*! @name STATUS - Capture And Compare Status */ /*! @{ */ #define FTM_STATUS_CH0F_MASK (0x1U) #define FTM_STATUS_CH0F_SHIFT (0U) /*! CH0F - Channel 0 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) #define FTM_STATUS_CH1F_MASK (0x2U) #define FTM_STATUS_CH1F_SHIFT (1U) /*! CH1F - Channel 1 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) #define FTM_STATUS_CH2F_MASK (0x4U) #define FTM_STATUS_CH2F_SHIFT (2U) /*! CH2F - Channel 2 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) #define FTM_STATUS_CH3F_MASK (0x8U) #define FTM_STATUS_CH3F_SHIFT (3U) /*! CH3F - Channel 3 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) #define FTM_STATUS_CH4F_MASK (0x10U) #define FTM_STATUS_CH4F_SHIFT (4U) /*! CH4F - Channel 4 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) #define FTM_STATUS_CH5F_MASK (0x20U) #define FTM_STATUS_CH5F_SHIFT (5U) /*! CH5F - Channel 5 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) #define FTM_STATUS_CH6F_MASK (0x40U) #define FTM_STATUS_CH6F_SHIFT (6U) /*! CH6F - Channel 6 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) #define FTM_STATUS_CH7F_MASK (0x80U) #define FTM_STATUS_CH7F_SHIFT (7U) /*! CH7F - Channel 7 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) /*! @} */ /*! @name MODE - Features Mode Selection */ /*! @{ */ #define FTM_MODE_FTMEN_MASK (0x1U) #define FTM_MODE_FTMEN_SHIFT (0U) /*! FTMEN - FTM Enable * 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. * 0b1..Free running counter and synchronization are different from TPM behavior. */ #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) #define FTM_MODE_INIT_MASK (0x2U) #define FTM_MODE_INIT_SHIFT (1U) /*! INIT - Initialize The Channels Output */ #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) #define FTM_MODE_WPDIS_MASK (0x4U) #define FTM_MODE_WPDIS_SHIFT (2U) /*! WPDIS - Write Protection Disable * 0b0..Write protection is enabled. * 0b1..Write protection is disabled. */ #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) #define FTM_MODE_PWMSYNC_MASK (0x8U) #define FTM_MODE_PWMSYNC_SHIFT (3U) /*! PWMSYNC - PWM Synchronization Mode * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used * by OUTMASK and FTM counter synchronization. */ #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) #define FTM_MODE_CAPTEST_MASK (0x10U) #define FTM_MODE_CAPTEST_SHIFT (4U) /*! CAPTEST - Capture Test Mode Enable * 0b0..Capture test mode is disabled. * 0b1..Capture test mode is enabled. */ #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) #define FTM_MODE_FAULTM_MASK (0x60U) #define FTM_MODE_FAULTM_SHIFT (5U) /*! FAULTM - Fault Control Mode * 0b00..Fault control is disabled for all channels. * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. */ #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) #define FTM_MODE_FAULTIE_MASK (0x80U) #define FTM_MODE_FAULTIE_SHIFT (7U) /*! FAULTIE - Fault Interrupt Enable * 0b0..Fault control interrupt is disabled. * 0b1..Fault control interrupt is enabled. */ #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) /*! @} */ /*! @name SYNC - Synchronization */ /*! @{ */ #define FTM_SYNC_CNTMIN_MASK (0x1U) #define FTM_SYNC_CNTMIN_SHIFT (0U) /*! CNTMIN - Minimum Loading Point Enable * 0b0..The minimum loading point is disabled. * 0b1..The minimum loading point is enabled. */ #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) #define FTM_SYNC_CNTMAX_MASK (0x2U) #define FTM_SYNC_CNTMAX_SHIFT (1U) /*! CNTMAX - Maximum Loading Point Enable * 0b0..The maximum loading point is disabled. * 0b1..The maximum loading point is enabled. */ #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) #define FTM_SYNC_REINIT_MASK (0x4U) #define FTM_SYNC_REINIT_SHIFT (2U) /*! REINIT - FTM Counter Reinitialization by Synchronization * 0b0..FTM counter continues to count normally. * 0b1..FTM counter is updated with its initial value when the selected trigger is detected. */ #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) #define FTM_SYNC_SYNCHOM_MASK (0x8U) #define FTM_SYNC_SYNCHOM_SHIFT (3U) /*! SYNCHOM - Output Mask Synchronization * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock. * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization. */ #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) #define FTM_SYNC_TRIG0_MASK (0x10U) #define FTM_SYNC_TRIG0_SHIFT (4U) /*! TRIG0 - PWM Synchronization Hardware Trigger 0 * 0b0..Trigger is disabled. * 0b1..Trigger is enabled. */ #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) #define FTM_SYNC_TRIG1_MASK (0x20U) #define FTM_SYNC_TRIG1_SHIFT (5U) /*! TRIG1 - PWM Synchronization Hardware Trigger 1 * 0b0..Trigger is disabled. * 0b1..Trigger is enabled. */ #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) #define FTM_SYNC_TRIG2_MASK (0x40U) #define FTM_SYNC_TRIG2_SHIFT (6U) /*! TRIG2 - PWM Synchronization Hardware Trigger 2 * 0b0..Trigger is disabled. * 0b1..Trigger is enabled. */ #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) #define FTM_SYNC_SWSYNC_MASK (0x80U) #define FTM_SYNC_SWSYNC_SHIFT (7U) /*! SWSYNC - PWM Synchronization Software Trigger * 0b0..Software trigger is not selected. * 0b1..Software trigger is selected. */ #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) /*! @} */ /*! @name OUTINIT - Initial State For Channels Output */ /*! @{ */ #define FTM_OUTINIT_CH0OI_MASK (0x1U) #define FTM_OUTINIT_CH0OI_SHIFT (0U) /*! CH0OI - Channel 0 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) #define FTM_OUTINIT_CH1OI_MASK (0x2U) #define FTM_OUTINIT_CH1OI_SHIFT (1U) /*! CH1OI - Channel 1 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) #define FTM_OUTINIT_CH2OI_MASK (0x4U) #define FTM_OUTINIT_CH2OI_SHIFT (2U) /*! CH2OI - Channel 2 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) #define FTM_OUTINIT_CH3OI_MASK (0x8U) #define FTM_OUTINIT_CH3OI_SHIFT (3U) /*! CH3OI - Channel 3 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) #define FTM_OUTINIT_CH4OI_MASK (0x10U) #define FTM_OUTINIT_CH4OI_SHIFT (4U) /*! CH4OI - Channel 4 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) #define FTM_OUTINIT_CH5OI_MASK (0x20U) #define FTM_OUTINIT_CH5OI_SHIFT (5U) /*! CH5OI - Channel 5 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) #define FTM_OUTINIT_CH6OI_MASK (0x40U) #define FTM_OUTINIT_CH6OI_SHIFT (6U) /*! CH6OI - Channel 6 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) #define FTM_OUTINIT_CH7OI_MASK (0x80U) #define FTM_OUTINIT_CH7OI_SHIFT (7U) /*! CH7OI - Channel 7 Output Initialization Value * 0b0..The initialization value is 0. * 0b1..The initialization value is 1. */ #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) /*! @} */ /*! @name OUTMASK - Output Mask */ /*! @{ */ #define FTM_OUTMASK_CH0OM_MASK (0x1U) #define FTM_OUTMASK_CH0OM_SHIFT (0U) /*! CH0OM - Channel 0 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) #define FTM_OUTMASK_CH1OM_MASK (0x2U) #define FTM_OUTMASK_CH1OM_SHIFT (1U) /*! CH1OM - Channel 1 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) #define FTM_OUTMASK_CH2OM_MASK (0x4U) #define FTM_OUTMASK_CH2OM_SHIFT (2U) /*! CH2OM - Channel 2 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) #define FTM_OUTMASK_CH3OM_MASK (0x8U) #define FTM_OUTMASK_CH3OM_SHIFT (3U) /*! CH3OM - Channel 3 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) #define FTM_OUTMASK_CH4OM_MASK (0x10U) #define FTM_OUTMASK_CH4OM_SHIFT (4U) /*! CH4OM - Channel 4 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) #define FTM_OUTMASK_CH5OM_MASK (0x20U) #define FTM_OUTMASK_CH5OM_SHIFT (5U) /*! CH5OM - Channel 5 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) #define FTM_OUTMASK_CH6OM_MASK (0x40U) #define FTM_OUTMASK_CH6OM_SHIFT (6U) /*! CH6OM - Channel 6 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) #define FTM_OUTMASK_CH7OM_MASK (0x80U) #define FTM_OUTMASK_CH7OM_SHIFT (7U) /*! CH7OM - Channel 7 Output Mask * 0b0..Channel output is not masked. It continues to operate normally. * 0b1..Channel output is masked. It is forced to its inactive state. */ #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) /*! @} */ /*! @name COMBINE - Function For Linked Channels */ /*! @{ */ #define FTM_COMBINE_COMBINE0_MASK (0x1U) #define FTM_COMBINE_COMBINE0_SHIFT (0U) /*! COMBINE0 - Combine Channels For n = 0 */ #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) #define FTM_COMBINE_COMP0_MASK (0x2U) #define FTM_COMBINE_COMP0_SHIFT (1U) /*! COMP0 - Complement Of Channel (n) For n = 0 * 0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output * is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the * channel (n+1) output is independent from channel (n) output. * 0b1..The channel (n+1) output is the complement of the channel (n) output. */ #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) #define FTM_COMBINE_DECAPEN0_MASK (0x4U) #define FTM_COMBINE_DECAPEN0_SHIFT (2U) /*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 */ #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) #define FTM_COMBINE_DECAP0_MASK (0x8U) #define FTM_COMBINE_DECAP0_SHIFT (3U) /*! DECAP0 - Dual Edge Capture Mode Captures For n = 0 * 0b0..The dual edge captures are inactive. * 0b1..The dual edge captures are active. */ #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) #define FTM_COMBINE_DTEN0_MASK (0x10U) #define FTM_COMBINE_DTEN0_SHIFT (4U) /*! DTEN0 - Deadtime Enable For n = 0 * 0b0..The deadtime insertion in this pair of channels is disabled. * 0b1..The deadtime insertion in this pair of channels is enabled. */ #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) #define FTM_COMBINE_SYNCEN0_MASK (0x20U) #define FTM_COMBINE_SYNCEN0_SHIFT (5U) /*! SYNCEN0 - Synchronization Enable For n = 0 * 0b0..The PWM synchronization in this pair of channels is disabled. * 0b1..The PWM synchronization in this pair of channels is enabled. */ #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) #define FTM_COMBINE_FAULTEN0_MASK (0x40U) #define FTM_COMBINE_FAULTEN0_SHIFT (6U) /*! FAULTEN0 - Fault Control Enable For n = 0 * 0b0..The fault control in this pair of channels is disabled. * 0b1..The fault control in this pair of channels is enabled. */ #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) #define FTM_COMBINE_MCOMBINE0_MASK (0x80U) #define FTM_COMBINE_MCOMBINE0_SHIFT (7U) /*! MCOMBINE0 - Modified Combine Mode For n = 0 */ #define FTM_COMBINE_MCOMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE0_SHIFT)) & FTM_COMBINE_MCOMBINE0_MASK) #define FTM_COMBINE_COMBINE1_MASK (0x100U) #define FTM_COMBINE_COMBINE1_SHIFT (8U) /*! COMBINE1 - Combine Channels For n = 2 */ #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) #define FTM_COMBINE_COMP1_MASK (0x200U) #define FTM_COMBINE_COMP1_SHIFT (9U) /*! COMP1 - Complement Of Channel (n) For n = 2 * 0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output * is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the * channel (n+1) output is independent from channel (n) output. * 0b1..The channel (n+1) output is the complement of the channel (n) output. */ #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) #define FTM_COMBINE_DECAPEN1_MASK (0x400U) #define FTM_COMBINE_DECAPEN1_SHIFT (10U) /*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 */ #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) #define FTM_COMBINE_DECAP1_MASK (0x800U) #define FTM_COMBINE_DECAP1_SHIFT (11U) /*! DECAP1 - Dual Edge Capture Mode Captures For n = 2 * 0b0..The dual edge captures are inactive. * 0b1..The dual edge captures are active. */ #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) #define FTM_COMBINE_DTEN1_MASK (0x1000U) #define FTM_COMBINE_DTEN1_SHIFT (12U) /*! DTEN1 - Deadtime Enable For n = 2 * 0b0..The deadtime insertion in this pair of channels is disabled. * 0b1..The deadtime insertion in this pair of channels is enabled. */ #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) #define FTM_COMBINE_SYNCEN1_SHIFT (13U) /*! SYNCEN1 - Synchronization Enable For n = 2 * 0b0..The PWM synchronization in this pair of channels is disabled. * 0b1..The PWM synchronization in this pair of channels is enabled. */ #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) #define FTM_COMBINE_FAULTEN1_SHIFT (14U) /*! FAULTEN1 - Fault Control Enable For n = 2 * 0b0..The fault control in this pair of channels is disabled. * 0b1..The fault control in this pair of channels is enabled. */ #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) #define FTM_COMBINE_MCOMBINE1_MASK (0x8000U) #define FTM_COMBINE_MCOMBINE1_SHIFT (15U) /*! MCOMBINE1 - Modified Combine Mode For n = 2 */ #define FTM_COMBINE_MCOMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE1_SHIFT)) & FTM_COMBINE_MCOMBINE1_MASK) #define FTM_COMBINE_COMBINE2_MASK (0x10000U) #define FTM_COMBINE_COMBINE2_SHIFT (16U) /*! COMBINE2 - Combine Channels For n = 4 */ #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) #define FTM_COMBINE_COMP2_MASK (0x20000U) #define FTM_COMBINE_COMP2_SHIFT (17U) /*! COMP2 - Complement Of Channel (n) For n = 4 * 0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output * is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the * channel (n+1) output is independent from channel (n) output. * 0b1..The channel (n+1) output is the complement of the channel (n) output. */ #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) #define FTM_COMBINE_DECAPEN2_SHIFT (18U) /*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 */ #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) #define FTM_COMBINE_DECAP2_MASK (0x80000U) #define FTM_COMBINE_DECAP2_SHIFT (19U) /*! DECAP2 - Dual Edge Capture Mode Captures For n = 4 * 0b0..The dual edge captures are inactive. * 0b1..The dual edge captures are active. */ #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) #define FTM_COMBINE_DTEN2_MASK (0x100000U) #define FTM_COMBINE_DTEN2_SHIFT (20U) /*! DTEN2 - Deadtime Enable For n = 4 * 0b0..The deadtime insertion in this pair of channels is disabled. * 0b1..The deadtime insertion in this pair of channels is enabled. */ #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) #define FTM_COMBINE_SYNCEN2_SHIFT (21U) /*! SYNCEN2 - Synchronization Enable For n = 4 * 0b0..The PWM synchronization in this pair of channels is disabled. * 0b1..The PWM synchronization in this pair of channels is enabled. */ #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) #define FTM_COMBINE_FAULTEN2_SHIFT (22U) /*! FAULTEN2 - Fault Control Enable For n = 4 * 0b0..The fault control in this pair of channels is disabled. * 0b1..The fault control in this pair of channels is enabled. */ #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) #define FTM_COMBINE_MCOMBINE2_MASK (0x800000U) #define FTM_COMBINE_MCOMBINE2_SHIFT (23U) /*! MCOMBINE2 - Modified Combine Mode For n = 4 */ #define FTM_COMBINE_MCOMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE2_SHIFT)) & FTM_COMBINE_MCOMBINE2_MASK) #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) #define FTM_COMBINE_COMBINE3_SHIFT (24U) /*! COMBINE3 - Combine Channels For n = 6 */ #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) #define FTM_COMBINE_COMP3_MASK (0x2000000U) #define FTM_COMBINE_COMP3_SHIFT (25U) /*! COMP3 - Complement Of Channel (n) for n = 6 * 0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output * is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the * channel (n+1) output is independent from channel (n) output. * 0b1..The channel (n+1) output is the complement of the channel (n) output. */ #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) #define FTM_COMBINE_DECAPEN3_SHIFT (26U) /*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 */ #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) #define FTM_COMBINE_DECAP3_MASK (0x8000000U) #define FTM_COMBINE_DECAP3_SHIFT (27U) /*! DECAP3 - Dual Edge Capture Mode Captures For n = 6 * 0b0..The dual edge captures are inactive. * 0b1..The dual edge captures are active. */ #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) #define FTM_COMBINE_DTEN3_MASK (0x10000000U) #define FTM_COMBINE_DTEN3_SHIFT (28U) /*! DTEN3 - Deadtime Enable For n = 6 * 0b0..The deadtime insertion in this pair of channels is disabled. * 0b1..The deadtime insertion in this pair of channels is enabled. */ #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) #define FTM_COMBINE_SYNCEN3_SHIFT (29U) /*! SYNCEN3 - Synchronization Enable For n = 6 * 0b0..The PWM synchronization in this pair of channels is disabled. * 0b1..The PWM synchronization in this pair of channels is enabled. */ #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) #define FTM_COMBINE_FAULTEN3_SHIFT (30U) /*! FAULTEN3 - Fault Control Enable For n = 6 * 0b0..The fault control in this pair of channels is disabled. * 0b1..The fault control in this pair of channels is enabled. */ #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) #define FTM_COMBINE_MCOMBINE3_MASK (0x80000000U) #define FTM_COMBINE_MCOMBINE3_SHIFT (31U) /*! MCOMBINE3 - Modified Combine Mode For n = 6 */ #define FTM_COMBINE_MCOMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE3_SHIFT)) & FTM_COMBINE_MCOMBINE3_MASK) /*! @} */ /*! @name DEADTIME - Deadtime Configuration */ /*! @{ */ #define FTM_DEADTIME_DTVAL_MASK (0x3FU) #define FTM_DEADTIME_DTVAL_SHIFT (0U) /*! DTVAL - Deadtime Value */ #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) #define FTM_DEADTIME_DTPS_MASK (0xC0U) #define FTM_DEADTIME_DTPS_SHIFT (6U) /*! DTPS - Deadtime Prescaler Value * 0b0x..Divide the FTM input clock by 1. * 0b10..Divide the FTM input clock by 4. * 0b11..Divide the FTM input clock by 16. */ #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) #define FTM_DEADTIME_DTVALEX_MASK (0xF0000U) #define FTM_DEADTIME_DTVALEX_SHIFT (16U) /*! DTVALEX - Extended Deadtime Value */ #define FTM_DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVALEX_SHIFT)) & FTM_DEADTIME_DTVALEX_MASK) /*! @} */ /*! @name EXTTRIG - FTM External Trigger */ /*! @{ */ #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) /*! CH2TRIG - Channel 2 External Trigger Enable * 0b0..The generation of this external trigger is disabled. * 0b1..The generation of this external trigger is enabled. */ #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) /*! CH3TRIG - Channel 3 External Trigger Enable * 0b0..The generation of this external trigger is disabled. * 0b1..The generation of this external trigger is enabled. */ #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) /*! CH4TRIG - Channel 4 External Trigger Enable * 0b0..The generation of this external trigger is disabled. * 0b1..The generation of this external trigger is enabled. */ #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) /*! CH5TRIG - Channel 5 External Trigger Enable * 0b0..The generation of this external trigger is disabled. * 0b1..The generation of this external trigger is enabled. */ #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) /*! CH0TRIG - Channel 0 External Trigger Enable * 0b0..The generation of this external trigger is disabled. * 0b1..The generation of this external trigger is enabled. */ #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) /*! CH1TRIG - Channel 1 External Trigger Enable * 0b0..The generation of this external trigger is disabled. * 0b1..The generation of this external trigger is enabled. */ #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) /*! INITTRIGEN - Initialization Trigger Enable * 0b0..The generation of initialization trigger is disabled. * 0b1..The generation of initialization trigger is enabled. */ #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) #define FTM_EXTTRIG_TRIGF_MASK (0x80U) #define FTM_EXTTRIG_TRIGF_SHIFT (7U) /*! TRIGF - Channel Trigger Flag * 0b0..No channel trigger was generated. * 0b1..A channel trigger was generated. */ #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) #define FTM_EXTTRIG_CH6TRIG_MASK (0x100U) #define FTM_EXTTRIG_CH6TRIG_SHIFT (8U) /*! CH6TRIG - Channel 6 External Trigger Enable * 0b0..The generation of this external trigger is disabled. * 0b1..The generation of this external trigger is enabled. */ #define FTM_EXTTRIG_CH6TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH6TRIG_SHIFT)) & FTM_EXTTRIG_CH6TRIG_MASK) #define FTM_EXTTRIG_CH7TRIG_MASK (0x200U) #define FTM_EXTTRIG_CH7TRIG_SHIFT (9U) /*! CH7TRIG - Channel 7 External Trigger Enable * 0b0..The generation of this external trigger is disabled. * 0b1..The generation of this external trigger is enabled. */ #define FTM_EXTTRIG_CH7TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH7TRIG_SHIFT)) & FTM_EXTTRIG_CH7TRIG_MASK) /*! @} */ /*! @name POL - Channels Polarity */ /*! @{ */ #define FTM_POL_POL0_MASK (0x1U) #define FTM_POL_POL0_SHIFT (0U) /*! POL0 - Channel 0 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) #define FTM_POL_POL1_MASK (0x2U) #define FTM_POL_POL1_SHIFT (1U) /*! POL1 - Channel 1 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) #define FTM_POL_POL2_MASK (0x4U) #define FTM_POL_POL2_SHIFT (2U) /*! POL2 - Channel 2 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) #define FTM_POL_POL3_MASK (0x8U) #define FTM_POL_POL3_SHIFT (3U) /*! POL3 - Channel 3 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) #define FTM_POL_POL4_MASK (0x10U) #define FTM_POL_POL4_SHIFT (4U) /*! POL4 - Channel 4 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) #define FTM_POL_POL5_MASK (0x20U) #define FTM_POL_POL5_SHIFT (5U) /*! POL5 - Channel 5 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) #define FTM_POL_POL6_MASK (0x40U) #define FTM_POL_POL6_SHIFT (6U) /*! POL6 - Channel 6 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) #define FTM_POL_POL7_MASK (0x80U) #define FTM_POL_POL7_SHIFT (7U) /*! POL7 - Channel 7 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) /*! @} */ /*! @name FMS - Fault Mode Status */ /*! @{ */ #define FTM_FMS_FAULTF0_MASK (0x1U) #define FTM_FMS_FAULTF0_SHIFT (0U) /*! FAULTF0 - Fault Detection Flag 0 * 0b0..No fault condition was detected at the fault input. * 0b1..A fault condition was detected at the fault input. */ #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) #define FTM_FMS_FAULTF1_MASK (0x2U) #define FTM_FMS_FAULTF1_SHIFT (1U) /*! FAULTF1 - Fault Detection Flag 1 * 0b0..No fault condition was detected at the fault input. * 0b1..A fault condition was detected at the fault input. */ #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) #define FTM_FMS_FAULTF2_MASK (0x4U) #define FTM_FMS_FAULTF2_SHIFT (2U) /*! FAULTF2 - Fault Detection Flag 2 * 0b0..No fault condition was detected at the fault input. * 0b1..A fault condition was detected at the fault input. */ #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) #define FTM_FMS_FAULTF3_MASK (0x8U) #define FTM_FMS_FAULTF3_SHIFT (3U) /*! FAULTF3 - Fault Detection Flag 3 * 0b0..No fault condition was detected at the fault input. * 0b1..A fault condition was detected at the fault input. */ #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) #define FTM_FMS_FAULTIN_MASK (0x20U) #define FTM_FMS_FAULTIN_SHIFT (5U) /*! FAULTIN - Fault Inputs * 0b0..The logic OR of the enabled fault inputs is 0. * 0b1..The logic OR of the enabled fault inputs is 1. */ #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) #define FTM_FMS_WPEN_MASK (0x40U) #define FTM_FMS_WPEN_SHIFT (6U) /*! WPEN - Write Protection Enable * 0b0..Write protection is disabled. Write protected bits can be written. * 0b1..Write protection is enabled. Write protected bits cannot be written. */ #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) #define FTM_FMS_FAULTF_MASK (0x80U) #define FTM_FMS_FAULTF_SHIFT (7U) /*! FAULTF - Fault Detection Flag * 0b0..No fault condition was detected. * 0b1..A fault condition was detected. */ #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) /*! @} */ /*! @name FILTER - Input Capture Filter Control */ /*! @{ */ #define FTM_FILTER_CH0FVAL_MASK (0xFU) #define FTM_FILTER_CH0FVAL_SHIFT (0U) /*! CH0FVAL - Channel 0 Input Filter */ #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) #define FTM_FILTER_CH1FVAL_MASK (0xF0U) #define FTM_FILTER_CH1FVAL_SHIFT (4U) /*! CH1FVAL - Channel 1 Input Filter */ #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) #define FTM_FILTER_CH2FVAL_MASK (0xF00U) #define FTM_FILTER_CH2FVAL_SHIFT (8U) /*! CH2FVAL - Channel 2 Input Filter */ #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) #define FTM_FILTER_CH3FVAL_MASK (0xF000U) #define FTM_FILTER_CH3FVAL_SHIFT (12U) /*! CH3FVAL - Channel 3 Input Filter */ #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) /*! @} */ /*! @name FLTCTRL - Fault Control */ /*! @{ */ #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) /*! FAULT0EN - Fault Input 0 Enable * 0b0..Fault input is disabled. * 0b1..Fault input is enabled. */ #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) /*! FAULT1EN - Fault Input 1 Enable * 0b0..Fault input is disabled. * 0b1..Fault input is enabled. */ #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) /*! FAULT2EN - Fault Input 2 Enable * 0b0..Fault input is disabled. * 0b1..Fault input is enabled. */ #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) /*! FAULT3EN - Fault Input 3 Enable * 0b0..Fault input is disabled. * 0b1..Fault input is enabled. */ #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) /*! FFLTR0EN - Fault Input 0 Filter Enable * 0b0..Fault input filter is disabled. * 0b1..Fault input filter is enabled. */ #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) /*! FFLTR1EN - Fault Input 1 Filter Enable * 0b0..Fault input filter is disabled. * 0b1..Fault input filter is enabled. */ #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) /*! FFLTR2EN - Fault Input 2 Filter Enable * 0b0..Fault input filter is disabled. * 0b1..Fault input filter is enabled. */ #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) /*! FFLTR3EN - Fault Input 3 Filter Enable * 0b0..Fault input filter is disabled. * 0b1..Fault input filter is enabled. */ #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) #define FTM_FLTCTRL_FFVAL_SHIFT (8U) /*! FFVAL - Fault Input Filter */ #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) #define FTM_FLTCTRL_FSTATE_MASK (0x8000U) #define FTM_FLTCTRL_FSTATE_SHIFT (15U) /*! FSTATE - Fault output state * 0b0..FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits). * 0b1..FTM outputs will be tri-stated when fault event is ongoing */ #define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FSTATE_SHIFT)) & FTM_FLTCTRL_FSTATE_MASK) /*! @} */ /*! @name QDCTRL - Quadrature Decoder Control And Status */ /*! @{ */ #define FTM_QDCTRL_QUADEN_MASK (0x1U) #define FTM_QDCTRL_QUADEN_SHIFT (0U) /*! QUADEN - Quadrature Decoder Mode Enable * 0b0..Quadrature Decoder mode is disabled. * 0b1..Quadrature Decoder mode is enabled. */ #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) #define FTM_QDCTRL_TOFDIR_MASK (0x2U) #define FTM_QDCTRL_TOFDIR_SHIFT (1U) /*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes * from its minimum value (CNTIN register) to its maximum value (MOD register). * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from * its maximum value (MOD register) to its minimum value (CNTIN register). */ #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) #define FTM_QDCTRL_QUADIR_MASK (0x4U) #define FTM_QDCTRL_QUADIR_SHIFT (2U) /*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode * 0b0..Counting direction is decreasing (FTM counter decrement). * 0b1..Counting direction is increasing (FTM counter increment). */ #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) #define FTM_QDCTRL_QUADMODE_MASK (0x8U) #define FTM_QDCTRL_QUADMODE_SHIFT (3U) /*! QUADMODE - Quadrature Decoder Mode * 0b0..Phase A and phase B encoding mode. * 0b1..Count and direction encoding mode. */ #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) #define FTM_QDCTRL_PHBPOL_MASK (0x10U) #define FTM_QDCTRL_PHBPOL_SHIFT (4U) /*! PHBPOL - Phase B Input Polarity * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. */ #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) #define FTM_QDCTRL_PHAPOL_MASK (0x20U) #define FTM_QDCTRL_PHAPOL_SHIFT (5U) /*! PHAPOL - Phase A Input Polarity * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. */ #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) /*! PHBFLTREN - Phase B Input Filter Enable * 0b0..Phase B input filter is disabled. * 0b1..Phase B input filter is enabled. */ #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) /*! PHAFLTREN - Phase A Input Filter Enable * 0b0..Phase A input filter is disabled. * 0b1..Phase A input filter is enabled. */ #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) /*! @} */ /*! @name CONF - Configuration */ /*! @{ */ #define FTM_CONF_LDFQ_MASK (0x1FU) #define FTM_CONF_LDFQ_SHIFT (0U) /*! LDFQ - Frequency of the Reload Opportunities */ #define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_LDFQ_SHIFT)) & FTM_CONF_LDFQ_MASK) #define FTM_CONF_BDMMODE_MASK (0xC0U) #define FTM_CONF_BDMMODE_SHIFT (6U) /*! BDMMODE - BDM Mode */ #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) #define FTM_CONF_GTBEEN_MASK (0x200U) #define FTM_CONF_GTBEEN_SHIFT (9U) /*! GTBEEN - Global Time Base Enable * 0b0..Use of an external global time base is disabled. * 0b1..Use of an external global time base is enabled. */ #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) #define FTM_CONF_GTBEOUT_MASK (0x400U) #define FTM_CONF_GTBEOUT_SHIFT (10U) /*! GTBEOUT - Global Time Base Output * 0b0..A global time base signal generation is disabled. * 0b1..A global time base signal generation is enabled. */ #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) #define FTM_CONF_ITRIGR_MASK (0x800U) #define FTM_CONF_ITRIGR_SHIFT (11U) /*! ITRIGR - Initialization trigger on Reload Point * 0b0..Initialization trigger is generated on counter wrap events. * 0b1..Initialization trigger is generated when a reload point is reached. */ #define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_ITRIGR_SHIFT)) & FTM_CONF_ITRIGR_MASK) /*! @} */ /*! @name FLTPOL - FTM Fault Input Polarity */ /*! @{ */ #define FTM_FLTPOL_FLT0POL_MASK (0x1U) #define FTM_FLTPOL_FLT0POL_SHIFT (0U) /*! FLT0POL - Fault Input 0 Polarity * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. */ #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) #define FTM_FLTPOL_FLT1POL_MASK (0x2U) #define FTM_FLTPOL_FLT1POL_SHIFT (1U) /*! FLT1POL - Fault Input 1 Polarity * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. */ #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) #define FTM_FLTPOL_FLT2POL_MASK (0x4U) #define FTM_FLTPOL_FLT2POL_SHIFT (2U) /*! FLT2POL - Fault Input 2 Polarity * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. */ #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) #define FTM_FLTPOL_FLT3POL_MASK (0x8U) #define FTM_FLTPOL_FLT3POL_SHIFT (3U) /*! FLT3POL - Fault Input 3 Polarity * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. */ #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) /*! @} */ /*! @name SYNCONF - Synchronization Configuration */ /*! @{ */ #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) /*! HWTRIGMODE - Hardware Trigger Mode * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. */ #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) #define FTM_SYNCONF_CNTINC_MASK (0x4U) #define FTM_SYNCONF_CNTINC_SHIFT (2U) /*! CNTINC - CNTIN Register Synchronization * 0b0..CNTIN register is updated with its buffer value at all rising edges of FTM input clock. * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization. */ #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) #define FTM_SYNCONF_INVC_MASK (0x10U) #define FTM_SYNCONF_INVC_SHIFT (4U) /*! INVC - INVCTRL Register Synchronization * 0b0..INVCTRL register is updated with its buffer value at all rising edges of FTM input clock. * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization. */ #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) #define FTM_SYNCONF_SWOC_MASK (0x20U) #define FTM_SYNCONF_SWOC_SHIFT (5U) /*! SWOC - SWOCTRL Register Synchronization * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock. * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization. */ #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) /*! SYNCMODE - Synchronization Mode * 0b0..Legacy PWM synchronization is selected. * 0b1..Enhanced PWM synchronization is selected. */ #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) /*! SWRSTCNT - FTM counter synchronization is activated by the software trigger * 0b0..The software trigger does not activate the FTM counter synchronization. * 0b1..The software trigger activates the FTM counter synchronization. */ #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) /*! SWWRBUF - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger * 0b0..The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. * 0b1..The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization. */ #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) #define FTM_SYNCONF_SWOM_MASK (0x400U) #define FTM_SYNCONF_SWOM_SHIFT (10U) /*! SWOM - Output mask synchronization is activated by the software trigger * 0b0..The software trigger does not activate the OUTMASK register synchronization. * 0b1..The software trigger activates the OUTMASK register synchronization. */ #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) #define FTM_SYNCONF_SWINVC_MASK (0x800U) #define FTM_SYNCONF_SWINVC_SHIFT (11U) /*! SWINVC - Inverting control synchronization is activated by the software trigger * 0b0..The software trigger does not activate the INVCTRL register synchronization. * 0b1..The software trigger activates the INVCTRL register synchronization. */ #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) #define FTM_SYNCONF_SWSOC_MASK (0x1000U) #define FTM_SYNCONF_SWSOC_SHIFT (12U) /*! SWSOC - Software output control synchronization is activated by the software trigger * 0b0..The software trigger does not activate the SWOCTRL register synchronization. * 0b1..The software trigger activates the SWOCTRL register synchronization. */ #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) /*! HWRSTCNT - FTM counter synchronization is activated by a hardware trigger * 0b0..A hardware trigger does not activate the FTM counter synchronization. * 0b1..A hardware trigger activates the FTM counter synchronization. */ #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) /*! HWWRBUF - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger * 0b0..A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. * 0b1..A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization. */ #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) #define FTM_SYNCONF_HWOM_MASK (0x40000U) #define FTM_SYNCONF_HWOM_SHIFT (18U) /*! HWOM - Output mask synchronization is activated by a hardware trigger * 0b0..A hardware trigger does not activate the OUTMASK register synchronization. * 0b1..A hardware trigger activates the OUTMASK register synchronization. */ #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) #define FTM_SYNCONF_HWINVC_MASK (0x80000U) #define FTM_SYNCONF_HWINVC_SHIFT (19U) /*! HWINVC - Inverting control synchronization is activated by a hardware trigger * 0b0..A hardware trigger does not activate the INVCTRL register synchronization. * 0b1..A hardware trigger activates the INVCTRL register synchronization. */ #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) #define FTM_SYNCONF_HWSOC_MASK (0x100000U) #define FTM_SYNCONF_HWSOC_SHIFT (20U) /*! HWSOC - Software output control synchronization is activated by a hardware trigger * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. * 0b1..A hardware trigger activates the SWOCTRL register synchronization. */ #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) /*! @} */ /*! @name INVCTRL - FTM Inverting Control */ /*! @{ */ #define FTM_INVCTRL_INV0EN_MASK (0x1U) #define FTM_INVCTRL_INV0EN_SHIFT (0U) /*! INV0EN - Pair Channels 0 Inverting Enable * 0b0..Inverting is disabled. * 0b1..Inverting is enabled. */ #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) #define FTM_INVCTRL_INV1EN_MASK (0x2U) #define FTM_INVCTRL_INV1EN_SHIFT (1U) /*! INV1EN - Pair Channels 1 Inverting Enable * 0b0..Inverting is disabled. * 0b1..Inverting is enabled. */ #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) #define FTM_INVCTRL_INV2EN_MASK (0x4U) #define FTM_INVCTRL_INV2EN_SHIFT (2U) /*! INV2EN - Pair Channels 2 Inverting Enable * 0b0..Inverting is disabled. * 0b1..Inverting is enabled. */ #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) #define FTM_INVCTRL_INV3EN_MASK (0x8U) #define FTM_INVCTRL_INV3EN_SHIFT (3U) /*! INV3EN - Pair Channels 3 Inverting Enable * 0b0..Inverting is disabled. * 0b1..Inverting is enabled. */ #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) /*! @} */ /*! @name SWOCTRL - FTM Software Output Control */ /*! @{ */ #define FTM_SWOCTRL_CH0OC_MASK (0x1U) #define FTM_SWOCTRL_CH0OC_SHIFT (0U) /*! CH0OC - Channel 0 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) #define FTM_SWOCTRL_CH1OC_MASK (0x2U) #define FTM_SWOCTRL_CH1OC_SHIFT (1U) /*! CH1OC - Channel 1 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) #define FTM_SWOCTRL_CH2OC_MASK (0x4U) #define FTM_SWOCTRL_CH2OC_SHIFT (2U) /*! CH2OC - Channel 2 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) #define FTM_SWOCTRL_CH3OC_MASK (0x8U) #define FTM_SWOCTRL_CH3OC_SHIFT (3U) /*! CH3OC - Channel 3 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) #define FTM_SWOCTRL_CH4OC_MASK (0x10U) #define FTM_SWOCTRL_CH4OC_SHIFT (4U) /*! CH4OC - Channel 4 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) #define FTM_SWOCTRL_CH5OC_MASK (0x20U) #define FTM_SWOCTRL_CH5OC_SHIFT (5U) /*! CH5OC - Channel 5 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) #define FTM_SWOCTRL_CH6OC_MASK (0x40U) #define FTM_SWOCTRL_CH6OC_SHIFT (6U) /*! CH6OC - Channel 6 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) #define FTM_SWOCTRL_CH7OC_MASK (0x80U) #define FTM_SWOCTRL_CH7OC_SHIFT (7U) /*! CH7OC - Channel 7 Software Output Control Enable * 0b0..The channel output is not affected by software output control. * 0b1..The channel output is affected by software output control. */ #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) /*! CH0OCV - Channel 0 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) /*! CH1OCV - Channel 1 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) /*! CH2OCV - Channel 2 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) /*! CH3OCV - Channel 3 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) /*! CH4OCV - Channel 4 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) /*! CH5OCV - Channel 5 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) /*! CH6OCV - Channel 6 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) /*! CH7OCV - Channel 7 Software Output Control Value * 0b0..The software output control forces 0 to the channel output. * 0b1..The software output control forces 1 to the channel output. */ #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) /*! @} */ /*! @name PWMLOAD - FTM PWM Load */ /*! @{ */ #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) /*! CH0SEL - Channel 0 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) /*! CH1SEL - Channel 1 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) /*! CH2SEL - Channel 2 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) /*! CH3SEL - Channel 3 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) /*! CH4SEL - Channel 4 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) /*! CH5SEL - Channel 5 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) /*! CH6SEL - Channel 6 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) /*! CH7SEL - Channel 7 Select * 0b0..Channel match is not included as a reload opportunity. * 0b1..Channel match is included as a reload opportunity. */ #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) #define FTM_PWMLOAD_HCSEL_MASK (0x100U) #define FTM_PWMLOAD_HCSEL_SHIFT (8U) /*! HCSEL - Half Cycle Select * 0b0..Half cycle reload is disabled and it is not considered as a reload opportunity. * 0b1..Half cycle reload is enabled and it is considered as a reload opportunity. */ #define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_HCSEL_SHIFT)) & FTM_PWMLOAD_HCSEL_MASK) #define FTM_PWMLOAD_LDOK_MASK (0x200U) #define FTM_PWMLOAD_LDOK_SHIFT (9U) /*! LDOK - Load Enable * 0b0..Loading updated values is disabled. * 0b1..Loading updated values is enabled. */ #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) #define FTM_PWMLOAD_GLEN_MASK (0x400U) #define FTM_PWMLOAD_GLEN_SHIFT (10U) /*! GLEN - Global Load Enable * 0b0..Global Load Ok disabled. * 0b1..Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit. */ #define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLEN_SHIFT)) & FTM_PWMLOAD_GLEN_MASK) #define FTM_PWMLOAD_GLDOK_MASK (0x800U) #define FTM_PWMLOAD_GLDOK_SHIFT (11U) /*! GLDOK - Global Load OK * 0b0..No action. * 0b1..LDOK bit is set. */ #define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLDOK_SHIFT)) & FTM_PWMLOAD_GLDOK_MASK) /*! @} */ /*! @name HCR - Half Cycle Register */ /*! @{ */ #define FTM_HCR_HCVAL_MASK (0xFFFFU) #define FTM_HCR_HCVAL_SHIFT (0U) /*! HCVAL - Half Cycle Value */ #define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_HCR_HCVAL_SHIFT)) & FTM_HCR_HCVAL_MASK) /*! @} */ /*! @name MOD_MIRROR - Mirror of Modulo Value */ /*! @{ */ #define FTM_MOD_MIRROR_FRACMOD_MASK (0xF800U) #define FTM_MOD_MIRROR_FRACMOD_SHIFT (11U) /*! FRACMOD - Modulo Fractional Value */ #define FTM_MOD_MIRROR_FRACMOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_FRACMOD_SHIFT)) & FTM_MOD_MIRROR_FRACMOD_MASK) #define FTM_MOD_MIRROR_MOD_MASK (0xFFFF0000U) #define FTM_MOD_MIRROR_MOD_SHIFT (16U) /*! MOD - Mirror of the Modulo Integer Value */ #define FTM_MOD_MIRROR_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_MOD_SHIFT)) & FTM_MOD_MIRROR_MOD_MASK) /*! @} */ /*! @name CV_MIRROR - Mirror of Channel (n) Match Value */ /*! @{ */ #define FTM_CV_MIRROR_FRACVAL_MASK (0xF800U) #define FTM_CV_MIRROR_FRACVAL_SHIFT (11U) /*! FRACVAL - Channel (n) Match Fractional Value */ #define FTM_CV_MIRROR_FRACVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_FRACVAL_SHIFT)) & FTM_CV_MIRROR_FRACVAL_MASK) #define FTM_CV_MIRROR_VAL_MASK (0xFFFF0000U) #define FTM_CV_MIRROR_VAL_SHIFT (16U) /*! VAL - Mirror of the Channel (n) Match Integer Value */ #define FTM_CV_MIRROR_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_VAL_SHIFT)) & FTM_CV_MIRROR_VAL_MASK) /*! @} */ /* The count of FTM_CV_MIRROR */ #define FTM_CV_MIRROR_COUNT (8U) /*! * @} */ /* end of group FTM_Register_Masks */ /* FTM - Peripheral instance base addresses */ /** Peripheral ADMA__FTM0 base address */ #define ADMA__FTM0_BASE (0x5A8A0000u) /** Peripheral ADMA__FTM0 base pointer */ #define ADMA__FTM0 ((FTM_Type *)ADMA__FTM0_BASE) /** Peripheral ADMA__FTM1 base address */ #define ADMA__FTM1_BASE (0x5A8B0000u) /** Peripheral ADMA__FTM1 base pointer */ #define ADMA__FTM1 ((FTM_Type *)ADMA__FTM1_BASE) /** Array initializer of FTM peripheral base addresses */ #define FTM_BASE_ADDRS { ADMA__FTM0_BASE, ADMA__FTM1_BASE } /** Array initializer of FTM peripheral base pointers */ #define FTM_BASE_PTRS { ADMA__FTM0, ADMA__FTM1 } /** Interrupt vectors for the FTM peripheral type */ #define FTM_IRQS { ADMA_FTM0_INT_IRQn, ADMA_FTM1_INT_IRQn } /*! * @} */ /* end of group FTM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer * @{ */ /** GPIO - Register Layout Typedef */ typedef struct { __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ uint8_t RESERVED_0[100]; __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */ __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */ __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */ } GPIO_Type; /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /*! @name DR - GPIO data register */ /*! @{ */ #define GPIO_DR_DR_MASK (0xFFFFFFFFU) #define GPIO_DR_DR_SHIFT (0U) /*! DR - DR */ #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) /*! @} */ /*! @name GDIR - GPIO direction register */ /*! @{ */ #define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) #define GPIO_GDIR_GDIR_SHIFT (0U) /*! GDIR - GDIR */ #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) /*! @} */ /*! @name PSR - GPIO pad status register */ /*! @{ */ #define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) #define GPIO_PSR_PSR_SHIFT (0U) /*! PSR - PSR */ #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) /*! @} */ /*! @name ICR1 - GPIO interrupt configuration register1 */ /*! @{ */ #define GPIO_ICR1_ICR0_MASK (0x3U) #define GPIO_ICR1_ICR0_SHIFT (0U) /*! ICR0 - ICR0 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) #define GPIO_ICR1_ICR1_MASK (0xCU) #define GPIO_ICR1_ICR1_SHIFT (2U) /*! ICR1 - ICR1 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) #define GPIO_ICR1_ICR2_MASK (0x30U) #define GPIO_ICR1_ICR2_SHIFT (4U) /*! ICR2 - ICR2 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) #define GPIO_ICR1_ICR3_MASK (0xC0U) #define GPIO_ICR1_ICR3_SHIFT (6U) /*! ICR3 - ICR3 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) #define GPIO_ICR1_ICR4_MASK (0x300U) #define GPIO_ICR1_ICR4_SHIFT (8U) /*! ICR4 - ICR4 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) #define GPIO_ICR1_ICR5_MASK (0xC00U) #define GPIO_ICR1_ICR5_SHIFT (10U) /*! ICR5 - ICR5 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) #define GPIO_ICR1_ICR6_MASK (0x3000U) #define GPIO_ICR1_ICR6_SHIFT (12U) /*! ICR6 - ICR6 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) #define GPIO_ICR1_ICR7_MASK (0xC000U) #define GPIO_ICR1_ICR7_SHIFT (14U) /*! ICR7 - ICR7 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) #define GPIO_ICR1_ICR8_MASK (0x30000U) #define GPIO_ICR1_ICR8_SHIFT (16U) /*! ICR8 - ICR8 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) #define GPIO_ICR1_ICR9_MASK (0xC0000U) #define GPIO_ICR1_ICR9_SHIFT (18U) /*! ICR9 - ICR9 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) #define GPIO_ICR1_ICR10_MASK (0x300000U) #define GPIO_ICR1_ICR10_SHIFT (20U) /*! ICR10 - ICR10 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) #define GPIO_ICR1_ICR11_MASK (0xC00000U) #define GPIO_ICR1_ICR11_SHIFT (22U) /*! ICR11 - ICR11 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) #define GPIO_ICR1_ICR12_MASK (0x3000000U) #define GPIO_ICR1_ICR12_SHIFT (24U) /*! ICR12 - ICR12 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) #define GPIO_ICR1_ICR13_MASK (0xC000000U) #define GPIO_ICR1_ICR13_SHIFT (26U) /*! ICR13 - ICR13 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) #define GPIO_ICR1_ICR14_MASK (0x30000000U) #define GPIO_ICR1_ICR14_SHIFT (28U) /*! ICR14 - ICR14 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) #define GPIO_ICR1_ICR15_MASK (0xC0000000U) #define GPIO_ICR1_ICR15_SHIFT (30U) /*! ICR15 - ICR15 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) /*! @} */ /*! @name ICR2 - GPIO interrupt configuration register2 */ /*! @{ */ #define GPIO_ICR2_ICR16_MASK (0x3U) #define GPIO_ICR2_ICR16_SHIFT (0U) /*! ICR16 - ICR16 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) #define GPIO_ICR2_ICR17_MASK (0xCU) #define GPIO_ICR2_ICR17_SHIFT (2U) /*! ICR17 - ICR17 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) #define GPIO_ICR2_ICR18_MASK (0x30U) #define GPIO_ICR2_ICR18_SHIFT (4U) /*! ICR18 - ICR18 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) #define GPIO_ICR2_ICR19_MASK (0xC0U) #define GPIO_ICR2_ICR19_SHIFT (6U) /*! ICR19 - ICR19 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) #define GPIO_ICR2_ICR20_MASK (0x300U) #define GPIO_ICR2_ICR20_SHIFT (8U) /*! ICR20 - ICR20 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) #define GPIO_ICR2_ICR21_MASK (0xC00U) #define GPIO_ICR2_ICR21_SHIFT (10U) /*! ICR21 - ICR21 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) #define GPIO_ICR2_ICR22_MASK (0x3000U) #define GPIO_ICR2_ICR22_SHIFT (12U) /*! ICR22 - ICR22 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) #define GPIO_ICR2_ICR23_MASK (0xC000U) #define GPIO_ICR2_ICR23_SHIFT (14U) /*! ICR23 - ICR23 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) #define GPIO_ICR2_ICR24_MASK (0x30000U) #define GPIO_ICR2_ICR24_SHIFT (16U) /*! ICR24 - ICR24 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) #define GPIO_ICR2_ICR25_MASK (0xC0000U) #define GPIO_ICR2_ICR25_SHIFT (18U) /*! ICR25 - ICR25 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) #define GPIO_ICR2_ICR26_MASK (0x300000U) #define GPIO_ICR2_ICR26_SHIFT (20U) /*! ICR26 - ICR26 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) #define GPIO_ICR2_ICR27_MASK (0xC00000U) #define GPIO_ICR2_ICR27_SHIFT (22U) /*! ICR27 - ICR27 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) #define GPIO_ICR2_ICR28_MASK (0x3000000U) #define GPIO_ICR2_ICR28_SHIFT (24U) /*! ICR28 - ICR28 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) #define GPIO_ICR2_ICR29_MASK (0xC000000U) #define GPIO_ICR2_ICR29_SHIFT (26U) /*! ICR29 - ICR29 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) #define GPIO_ICR2_ICR30_MASK (0x30000000U) #define GPIO_ICR2_ICR30_SHIFT (28U) /*! ICR30 - ICR30 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) #define GPIO_ICR2_ICR31_MASK (0xC0000000U) #define GPIO_ICR2_ICR31_SHIFT (30U) /*! ICR31 - ICR31 * 0b00..Interrupt n is low-level sensitive. * 0b01..Interrupt n is high-level sensitive. * 0b10..Interrupt n is rising-edge sensitive. * 0b11..Interrupt n is falling-edge sensitive. */ #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) /*! @} */ /*! @name IMR - GPIO interrupt mask register */ /*! @{ */ #define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) #define GPIO_IMR_IMR_SHIFT (0U) /*! IMR - IMR */ #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) /*! @} */ /*! @name ISR - GPIO interrupt status register */ /*! @{ */ #define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) #define GPIO_ISR_ISR_SHIFT (0U) /*! ISR - ISR */ #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) /*! @} */ /*! @name EDGE_SEL - GPIO edge select register */ /*! @{ */ #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) /*! GPIO_EDGE_SEL - GPIO_EDGE_SEL */ #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) /*! @} */ /*! @name DR_SET - GPIO data register SET */ /*! @{ */ #define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) #define GPIO_DR_SET_DR_SET_SHIFT (0U) /*! DR_SET - DR_SET */ #define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) /*! @} */ /*! @name DR_CLEAR - GPIO data register CLEAR */ /*! @{ */ #define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) #define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) /*! DR_CLEAR - DR_CLEAR */ #define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) /*! @} */ /*! @name DR_TOGGLE - GPIO data register TOGGLE */ /*! @{ */ #define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) #define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) /*! DR_TOGGLE - DR_TOGGLE */ #define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) /*! @} */ /*! * @} */ /* end of group GPIO_Register_Masks */ /* GPIO - Peripheral instance base addresses */ /** Peripheral CI_PI__GPIO base address */ #define CI_PI__GPIO_BASE (0x58262000u) /** Peripheral CI_PI__GPIO base pointer */ #define CI_PI__GPIO ((GPIO_Type *)CI_PI__GPIO_BASE) /** Peripheral DI_MIPI_DSI_LVDS_0__GPIO base address */ #define DI_MIPI_DSI_LVDS_0__GPIO_BASE (0x56222000u) /** Peripheral DI_MIPI_DSI_LVDS_0__GPIO base pointer */ #define DI_MIPI_DSI_LVDS_0__GPIO ((GPIO_Type *)DI_MIPI_DSI_LVDS_0__GPIO_BASE) /** Peripheral DI_MIPI_DSI_LVDS_1__GPIO base address */ #define DI_MIPI_DSI_LVDS_1__GPIO_BASE (0x56242000u) /** Peripheral DI_MIPI_DSI_LVDS_1__GPIO base pointer */ #define DI_MIPI_DSI_LVDS_1__GPIO ((GPIO_Type *)DI_MIPI_DSI_LVDS_1__GPIO_BASE) /** Peripheral HSIO__GPIO base address */ #define HSIO__GPIO_BASE (0x5F170000u) /** Peripheral HSIO__GPIO base pointer */ #define HSIO__GPIO ((GPIO_Type *)HSIO__GPIO_BASE) /** Peripheral LSIO__GPIO0 base address */ #define LSIO__GPIO0_BASE (0x5D080000u) /** Peripheral LSIO__GPIO0 base pointer */ #define LSIO__GPIO0 ((GPIO_Type *)LSIO__GPIO0_BASE) /** Peripheral LSIO__GPIO1 base address */ #define LSIO__GPIO1_BASE (0x5D090000u) /** Peripheral LSIO__GPIO1 base pointer */ #define LSIO__GPIO1 ((GPIO_Type *)LSIO__GPIO1_BASE) /** Peripheral LSIO__GPIO2 base address */ #define LSIO__GPIO2_BASE (0x5D0A0000u) /** Peripheral LSIO__GPIO2 base pointer */ #define LSIO__GPIO2 ((GPIO_Type *)LSIO__GPIO2_BASE) /** Peripheral LSIO__GPIO3 base address */ #define LSIO__GPIO3_BASE (0x5D0B0000u) /** Peripheral LSIO__GPIO3 base pointer */ #define LSIO__GPIO3 ((GPIO_Type *)LSIO__GPIO3_BASE) /** Peripheral LSIO__GPIO4 base address */ #define LSIO__GPIO4_BASE (0x5D0C0000u) /** Peripheral LSIO__GPIO4 base pointer */ #define LSIO__GPIO4 ((GPIO_Type *)LSIO__GPIO4_BASE) /** Peripheral LSIO__GPIO5 base address */ #define LSIO__GPIO5_BASE (0x5D0D0000u) /** Peripheral LSIO__GPIO5 base pointer */ #define LSIO__GPIO5 ((GPIO_Type *)LSIO__GPIO5_BASE) /** Peripheral LSIO__GPIO6 base address */ #define LSIO__GPIO6_BASE (0x5D0E0000u) /** Peripheral LSIO__GPIO6 base pointer */ #define LSIO__GPIO6 ((GPIO_Type *)LSIO__GPIO6_BASE) /** Peripheral LSIO__GPIO7 base address */ #define LSIO__GPIO7_BASE (0x5D0F0000u) /** Peripheral LSIO__GPIO7 base pointer */ #define LSIO__GPIO7 ((GPIO_Type *)LSIO__GPIO7_BASE) /** Peripheral MIPI_CSI__GPIO base address */ #define MIPI_CSI__GPIO_BASE (0x58222000u) /** Peripheral MIPI_CSI__GPIO base pointer */ #define MIPI_CSI__GPIO ((GPIO_Type *)MIPI_CSI__GPIO_BASE) /** Array initializer of GPIO peripheral base addresses */ #define GPIO_BASE_ADDRS { CI_PI__GPIO_BASE, DI_MIPI_DSI_LVDS_0__GPIO_BASE, DI_MIPI_DSI_LVDS_1__GPIO_BASE, HSIO__GPIO_BASE, LSIO__GPIO0_BASE, LSIO__GPIO1_BASE, LSIO__GPIO2_BASE, LSIO__GPIO3_BASE, LSIO__GPIO4_BASE, LSIO__GPIO5_BASE, LSIO__GPIO6_BASE, LSIO__GPIO7_BASE, MIPI_CSI__GPIO_BASE } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS { CI_PI__GPIO, DI_MIPI_DSI_LVDS_0__GPIO, DI_MIPI_DSI_LVDS_1__GPIO, HSIO__GPIO, LSIO__GPIO0, LSIO__GPIO1, LSIO__GPIO2, LSIO__GPIO3, LSIO__GPIO4, LSIO__GPIO5, LSIO__GPIO6, LSIO__GPIO7, MIPI_CSI__GPIO } /** Interrupt vectors for the GPIO peripheral type */ #define GPIO_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, LSIO_GPIO_INT0_IRQn, LSIO_GPIO_INT1_IRQn, LSIO_GPIO_INT2_IRQn, LSIO_GPIO_INT3_IRQn, LSIO_GPIO_INT4_IRQn, LSIO_GPIO_INT5_IRQn, LSIO_GPIO_INT6_IRQn, LSIO_GPIO_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group GPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPMI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer * @{ */ /** GPMI - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< GPMI Control Register 0 Description, offset: 0x0 */ __IO uint32_t SET; /**< GPMI Control Register 0 Description, offset: 0x4 */ __IO uint32_t CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */ __IO uint32_t TOG; /**< GPMI Control Register 0 Description, offset: 0xC */ } CTRL0; __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */ uint8_t RESERVED_0[12]; struct { /* offset: 0x20 */ __IO uint32_t RW; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */ __IO uint32_t SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */ __IO uint32_t CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */ __IO uint32_t TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */ } ECCCTRL; __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */ uint8_t RESERVED_1[12]; __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */ uint8_t RESERVED_2[12]; __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */ uint8_t RESERVED_3[12]; struct { /* offset: 0x60 */ __IO uint32_t RW; /**< GPMI Control Register 1 Description, offset: 0x60 */ __IO uint32_t SET; /**< GPMI Control Register 1 Description, offset: 0x64 */ __IO uint32_t CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */ __IO uint32_t TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */ } CTRL1; __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */ uint8_t RESERVED_4[12]; __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */ uint8_t RESERVED_5[12]; __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */ uint8_t RESERVED_6[12]; __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */ uint8_t RESERVED_7[12]; __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */ uint8_t RESERVED_8[12]; __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */ uint8_t RESERVED_9[12]; __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ uint8_t RESERVED_10[12]; __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ uint8_t RESERVED_11[12]; __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ uint8_t RESERVED_12[12]; __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */ uint8_t RESERVED_13[12]; __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */ uint8_t RESERVED_14[12]; __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ uint8_t RESERVED_15[12]; __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */ uint8_t RESERVED_16[12]; __IO uint32_t TIMING3; /**< GPMI Timing Register 3 Description, offset: 0x140 */ uint8_t RESERVED_17[12]; __IO uint32_t CTRL2; /**< GPMI Control Register 2 Description, offset: 0x150 */ } GPMI_Type; /* ---------------------------------------------------------------------------- -- GPMI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPMI_Register_Masks GPMI Register Masks * @{ */ /*! @name CTRL0 - GPMI Control Register 0 Description */ /*! @{ */ #define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU) #define GPMI_CTRL0_XFER_COUNT_SHIFT (0U) /*! XFER_COUNT - XFER_COUNT */ #define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK) #define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U) #define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U) /*! ADDRESS_INCREMENT - ADDRESS_INCREMENT */ #define GPMI_CTRL0_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK) #define GPMI_CTRL0_ADDRESS_MASK (0xE0000U) #define GPMI_CTRL0_ADDRESS_SHIFT (17U) /*! ADDRESS - ADDRESS */ #define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK) #define GPMI_CTRL0_CS_MASK (0x700000U) #define GPMI_CTRL0_CS_SHIFT (20U) /*! CS - CS */ #define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK) #define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U) #define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U) /*! WORD_LENGTH - WORD_LENGTH * 0b0..Reserved. * 0b1..8-bit Data Bus mode. */ #define GPMI_CTRL0_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK) #define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U) #define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U) /*! COMMAND_MODE - COMMAND_MODE * 0b00..Write mode. * 0b01..Read Mode. * 0b10..Read and Compare Mode (setting sense flop). * 0b11..Wait for Ready. */ #define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK) #define GPMI_CTRL0_UDMA_MASK (0x4000000U) #define GPMI_CTRL0_UDMA_SHIFT (26U) /*! UDMA - UDMA * 0b0..Use ATA-PIO mode on the external bus. * 0b1..Use ATA-Ultra DMA mode on the external bus. */ #define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK) #define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U) #define GPMI_CTRL0_LOCK_CS_SHIFT (27U) /*! LOCK_CS - LOCK_CS */ #define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK) #define GPMI_CTRL0_WR_DATA_EN_MASK (0x10000000U) #define GPMI_CTRL0_WR_DATA_EN_SHIFT (28U) /*! WR_DATA_EN - WR_DATA_EN */ #define GPMI_CTRL0_WR_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WR_DATA_EN_SHIFT)) & GPMI_CTRL0_WR_DATA_EN_MASK) #define GPMI_CTRL0_RUN_MASK (0x20000000U) #define GPMI_CTRL0_RUN_SHIFT (29U) /*! RUN - RUN */ #define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK) #define GPMI_CTRL0_CLKGATE_MASK (0x40000000U) #define GPMI_CTRL0_CLKGATE_SHIFT (30U) /*! CLKGATE - CLKGATE */ #define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK) #define GPMI_CTRL0_SFTRST_MASK (0x80000000U) #define GPMI_CTRL0_SFTRST_SHIFT (31U) /*! SFTRST - SFTRST */ #define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK) /*! @} */ /*! @name COMPARE - GPMI Compare Register Description */ /*! @{ */ #define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU) #define GPMI_COMPARE_REFERENCE_SHIFT (0U) /*! REFERENCE - REFERENCE */ #define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK) #define GPMI_COMPARE_MASK_MASK (0xFFFF0000U) #define GPMI_COMPARE_MASK_SHIFT (16U) /*! MASK - MASK */ #define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK) /*! @} */ /*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */ /*! @{ */ #define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU) #define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U) /*! BUFFER_MASK - BUFFER_MASK */ #define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK) #define GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK (0x600U) #define GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT (9U) /*! RANDOMIZER_TYPE - RANDOMIZER_TYPE * 0b00..Type 0 * 0b01..Type 1 * 0b10..Type 2 */ #define GPMI_ECCCTRL_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK) #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK (0x800U) #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT (11U) /*! RANDOMIZER_ENABLE - RANDOMIZER_ENABLE * 0b0..disable * 0b1..enable */ #define GPMI_ECCCTRL_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK) #define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U) #define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U) /*! ENABLE_ECC - ENABLE_ECC */ #define GPMI_ECCCTRL_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK) #define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U) #define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U) /*! ECC_CMD - ECC_CMD */ #define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK) #define GPMI_ECCCTRL_RSVD2_MASK (0x8000U) #define GPMI_ECCCTRL_RSVD2_SHIFT (15U) /*! RSVD2 - RSVD2 */ #define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK) #define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U) #define GPMI_ECCCTRL_HANDLE_SHIFT (16U) /*! HANDLE - HANDLE */ #define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK) /*! @} */ /*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */ /*! @{ */ #define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU) #define GPMI_ECCCOUNT_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK) #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK (0xFF0000U) #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT (16U) /*! RANDOMIZER_PAGE - RANDOMIZER_PAGE */ #define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT)) & GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK) /*! @} */ /*! @name PAYLOAD - GPMI Payload Address Register Description */ /*! @{ */ #define GPMI_PAYLOAD_RSVD0_MASK (0x3U) #define GPMI_PAYLOAD_RSVD0_SHIFT (0U) /*! RSVD0 - RSVD0 */ #define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK) #define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU) #define GPMI_PAYLOAD_ADDRESS_SHIFT (2U) /*! ADDRESS - ADDRESS */ #define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK) /*! @} */ /*! @name AUXILIARY - GPMI Auxiliary Address Register Description */ /*! @{ */ #define GPMI_AUXILIARY_RSVD0_MASK (0x3U) #define GPMI_AUXILIARY_RSVD0_SHIFT (0U) /*! RSVD0 - RSVD0 */ #define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK) #define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU) #define GPMI_AUXILIARY_ADDRESS_SHIFT (2U) /*! ADDRESS - ADDRESS */ #define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK) /*! @} */ /*! @name CTRL1 - GPMI Control Register 1 Description */ /*! @{ */ #define GPMI_CTRL1_GPMI_MODE_MASK (0x1U) #define GPMI_CTRL1_GPMI_MODE_SHIFT (0U) /*! GPMI_MODE - GPMI_MODE * 0b0..NAND mode. * 0b1..ATA mode. */ #define GPMI_CTRL1_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK) #define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U) #define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U) /*! CAMERA_MODE - CAMERA_MODE */ #define GPMI_CTRL1_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK) #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U) #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U) /*! ATA_IRQRDY_POLARITY - ATA_IRQRDY_POLARITY * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. */ #define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK) #define GPMI_CTRL1_DEV_RESET_MASK (0x8U) #define GPMI_CTRL1_DEV_RESET_SHIFT (3U) /*! DEV_RESET - DEV_RESET * 0b0..NANDF_WP_B pin is held low (asserted). * 0b1..NANDF_WP_B pin is held high (de-asserted). */ #define GPMI_CTRL1_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK) #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) /*! ABORT_WAIT_FOR_READY_CHANNEL - ABORT_WAIT_FOR_READY_CHANNEL */ #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK) #define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U) #define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U) /*! ABORT_WAIT_REQUEST - ABORT_WAIT_REQUEST */ #define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK) #define GPMI_CTRL1_BURST_EN_MASK (0x100U) #define GPMI_CTRL1_BURST_EN_SHIFT (8U) /*! BURST_EN - BURST_EN */ #define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK) #define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U) #define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U) /*! TIMEOUT_IRQ - TIMEOUT_IRQ */ #define GPMI_CTRL1_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK) #define GPMI_CTRL1_DEV_IRQ_MASK (0x400U) #define GPMI_CTRL1_DEV_IRQ_SHIFT (10U) /*! DEV_IRQ - DEV_IRQ */ #define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK) #define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U) #define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U) /*! DMA2ECC_MODE - DMA2ECC_MODE */ #define GPMI_CTRL1_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK) #define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U) #define GPMI_CTRL1_RDN_DELAY_SHIFT (12U) /*! RDN_DELAY - RDN_DELAY */ #define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK) #define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U) #define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U) /*! HALF_PERIOD - HALF_PERIOD */ #define GPMI_CTRL1_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK) #define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U) #define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U) /*! DLL_ENABLE - DLL_ENABLE */ #define GPMI_CTRL1_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK) #define GPMI_CTRL1_BCH_MODE_MASK (0x40000U) #define GPMI_CTRL1_BCH_MODE_SHIFT (18U) /*! BCH_MODE - BCH_MODE */ #define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK) #define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U) #define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U) /*! GANGED_RDYBUSY - GANGED_RDYBUSY */ #define GPMI_CTRL1_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK) #define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U) #define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U) /*! TIMEOUT_IRQ_EN - TIMEOUT_IRQ_EN */ #define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK) #define GPMI_CTRL1_RSVD1_MASK (0x200000U) #define GPMI_CTRL1_RSVD1_SHIFT (21U) /*! RSVD1 - RSVD1 */ #define GPMI_CTRL1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RSVD1_SHIFT)) & GPMI_CTRL1_RSVD1_MASK) #define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U) #define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U) /*! WRN_DLY_SEL - WRN_DLY_SEL */ #define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK) #define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U) #define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U) /*! DECOUPLE_CS - DECOUPLE_CS */ #define GPMI_CTRL1_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK) #define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U) #define GPMI_CTRL1_SSYNCMODE_SHIFT (25U) /*! SSYNCMODE - SSYNCMODE */ #define GPMI_CTRL1_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK) #define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U) #define GPMI_CTRL1_UPDATE_CS_SHIFT (26U) /*! UPDATE_CS - UPDATE_CS */ #define GPMI_CTRL1_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK) #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U) #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U) /*! GPMI_CLK_DIV2_EN - GPMI_CLK_DIV2_EN * 0b0..internal factor-2 clock divider is disabled * 0b1..internal factor-2 clock divider is enabled. */ #define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK) #define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U) #define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U) /*! TOGGLE_MODE - TOGGLE_MODE */ #define GPMI_CTRL1_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK) #define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U) #define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U) /*! WRITE_CLK_STOP - WRITE_CLK_STOP */ #define GPMI_CTRL1_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK) #define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U) #define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U) /*! SSYNC_CLK_STOP - SSYNC_CLK_STOP */ #define GPMI_CTRL1_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK) #define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U) #define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U) /*! DEV_CLK_STOP - DEV_CLK_STOP */ #define GPMI_CTRL1_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK) /*! @} */ /*! @name TIMING0 - GPMI Timing Register 0 Description */ /*! @{ */ #define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU) #define GPMI_TIMING0_DATA_SETUP_SHIFT (0U) /*! DATA_SETUP - DATA_SETUP */ #define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK) #define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U) #define GPMI_TIMING0_DATA_HOLD_SHIFT (8U) /*! DATA_HOLD - DATA_HOLD */ #define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK) #define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U) #define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U) /*! ADDRESS_SETUP - ADDRESS_SETUP */ #define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK) #define GPMI_TIMING0_RSVD1_MASK (0xFF000000U) #define GPMI_TIMING0_RSVD1_SHIFT (24U) /*! RSVD1 - RSVD1 */ #define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK) /*! @} */ /*! @name TIMING1 - GPMI Timing Register 1 Description */ /*! @{ */ #define GPMI_TIMING1_RSVD1_MASK (0xFFFFU) #define GPMI_TIMING1_RSVD1_SHIFT (0U) /*! RSVD1 - RSVD1 */ #define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK) #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U) #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U) /*! DEVICE_BUSY_TIMEOUT - DEVICE_BUSY_TIMEOUT */ #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK) /*! @} */ /*! @name TIMING2 - GPMI Timing Register 2 Description */ /*! @{ */ #define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU) #define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U) /*! DATA_PAUSE - DATA_PAUSE */ #define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK) #define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U) #define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U) /*! CMDADD_PAUSE - CMDADD_PAUSE */ #define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK) #define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U) #define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U) /*! POSTAMBLE_DELAY - POSTAMBLE_DELAY */ #define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK) #define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U) #define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U) /*! PREAMBLE_DELAY - PREAMBLE_DELAY */ #define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK) #define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U) #define GPMI_TIMING2_CE_DELAY_SHIFT (16U) /*! CE_DELAY - CE_DELAY */ #define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK) #define GPMI_TIMING2_RSVD0_MASK (0xE00000U) #define GPMI_TIMING2_RSVD0_SHIFT (21U) /*! RSVD0 - RSVD0 */ #define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK) #define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U) #define GPMI_TIMING2_READ_LATENCY_SHIFT (24U) /*! READ_LATENCY - READ_LATENCY * 0b000..READ LATENCY is 0 * 0b001..READ LATENCY is 1 * 0b010..READ LATENCY is 2 * 0b011..READ LATENCY is 3 * 0b100..READ LATENCY is 4 * 0b101..READ LATENCY is 5 */ #define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK) #define GPMI_TIMING2_TCR_MASK (0x18000000U) #define GPMI_TIMING2_TCR_SHIFT (27U) /*! TCR - TCR */ #define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK) #define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U) #define GPMI_TIMING2_TRPSTH_SHIFT (29U) /*! TRPSTH - TRPSTH */ #define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK) /*! @} */ /*! @name DATA - GPMI DMA Data Transfer Register Description */ /*! @{ */ #define GPMI_DATA_DATA_MASK (0xFFFFFFFFU) #define GPMI_DATA_DATA_SHIFT (0U) /*! DATA - DATA */ #define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK) /*! @} */ /*! @name STAT - GPMI Status Register Description */ /*! @{ */ #define GPMI_STAT_PRESENT_MASK (0x1U) #define GPMI_STAT_PRESENT_SHIFT (0U) /*! PRESENT - PRESENT * 0b0..GPMI is not present in this product. * 0b1..GPMI is present is in this product. */ #define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK) #define GPMI_STAT_FIFO_FULL_MASK (0x2U) #define GPMI_STAT_FIFO_FULL_SHIFT (1U) /*! FIFO_FULL - FIFO_FULL * 0b0..FIFO is not full. * 0b1..FIFO is full. */ #define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK) #define GPMI_STAT_FIFO_EMPTY_MASK (0x4U) #define GPMI_STAT_FIFO_EMPTY_SHIFT (2U) /*! FIFO_EMPTY - FIFO_EMPTY * 0b0..FIFO is not empty. * 0b1..FIFO is empty. */ #define GPMI_STAT_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK) #define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U) #define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U) /*! INVALID_BUFFER_MASK - INVALID_BUFFER_MASK * 0b0..ECC Buffer Mask is not invalid. * 0b1..ECC Buffer Mask is invalid. */ #define GPMI_STAT_INVALID_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK) #define GPMI_STAT_ATA_IRQ_MASK (0x10U) #define GPMI_STAT_ATA_IRQ_SHIFT (4U) /*! ATA_IRQ - ATA_IRQ */ #define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK) #define GPMI_STAT_RSVD1_MASK (0xE0U) #define GPMI_STAT_RSVD1_SHIFT (5U) /*! RSVD1 - RSVD1 */ #define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK) #define GPMI_STAT_DEV0_ERROR_MASK (0x100U) #define GPMI_STAT_DEV0_ERROR_SHIFT (8U) /*! DEV0_ERROR - DEV0_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK) #define GPMI_STAT_DEV1_ERROR_MASK (0x200U) #define GPMI_STAT_DEV1_ERROR_SHIFT (9U) /*! DEV1_ERROR - DEV1_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV1_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK) #define GPMI_STAT_DEV2_ERROR_MASK (0x400U) #define GPMI_STAT_DEV2_ERROR_SHIFT (10U) /*! DEV2_ERROR - DEV2_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV2_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK) #define GPMI_STAT_DEV3_ERROR_MASK (0x800U) #define GPMI_STAT_DEV3_ERROR_SHIFT (11U) /*! DEV3_ERROR - DEV3_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK) #define GPMI_STAT_DEV4_ERROR_MASK (0x1000U) #define GPMI_STAT_DEV4_ERROR_SHIFT (12U) /*! DEV4_ERROR - DEV4_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV4_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK) #define GPMI_STAT_DEV5_ERROR_MASK (0x2000U) #define GPMI_STAT_DEV5_ERROR_SHIFT (13U) /*! DEV5_ERROR - DEV5_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV5_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK) #define GPMI_STAT_DEV6_ERROR_MASK (0x4000U) #define GPMI_STAT_DEV6_ERROR_SHIFT (14U) /*! DEV6_ERROR - DEV6_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV6_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK) #define GPMI_STAT_DEV7_ERROR_MASK (0x8000U) #define GPMI_STAT_DEV7_ERROR_SHIFT (15U) /*! DEV7_ERROR - DEV7_ERROR * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7. * 0b1..An Error has occurred on ATA/NAND Device accessed by */ #define GPMI_STAT_DEV7_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK) #define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U) #define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U) /*! RDY_TIMEOUT - RDY_TIMEOUT */ #define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK) #define GPMI_STAT_READY_BUSY_MASK (0xFF000000U) #define GPMI_STAT_READY_BUSY_SHIFT (24U) /*! READY_BUSY - READY_BUSY */ #define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK) /*! @} */ /*! @name DEBUG - GPMI Debug Information Register Description */ /*! @{ */ #define GPMI_DEBUG_CMD_END_MASK (0xFFU) #define GPMI_DEBUG_CMD_END_SHIFT (0U) /*! CMD_END - CMD_END */ #define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK) #define GPMI_DEBUG_DMAREQ_MASK (0xFF00U) #define GPMI_DEBUG_DMAREQ_SHIFT (8U) /*! DMAREQ - DMAREQ */ #define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK) #define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U) #define GPMI_DEBUG_DMA_SENSE_SHIFT (16U) /*! DMA_SENSE - DMA_SENSE */ #define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK) #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U) #define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U) /*! WAIT_FOR_READY_END - WAIT_FOR_READY_END */ #define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK) /*! @} */ /*! @name VERSION - GPMI Version Register Description */ /*! @{ */ #define GPMI_VERSION_STEP_MASK (0xFFFFU) #define GPMI_VERSION_STEP_SHIFT (0U) /*! STEP - STEP */ #define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK) #define GPMI_VERSION_MINOR_MASK (0xFF0000U) #define GPMI_VERSION_MINOR_SHIFT (16U) /*! MINOR - MINOR */ #define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK) #define GPMI_VERSION_MAJOR_MASK (0xFF000000U) #define GPMI_VERSION_MAJOR_SHIFT (24U) /*! MAJOR - MAJOR */ #define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK) /*! @} */ /*! @name DEBUG2 - GPMI Debug2 Information Register Description */ /*! @{ */ #define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU) #define GPMI_DEBUG2_RDN_TAP_SHIFT (0U) /*! RDN_TAP - RDN_TAP */ #define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK) #define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U) #define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U) /*! UPDATE_WINDOW - UPDATE_WINDOW */ #define GPMI_DEBUG2_UPDATE_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK) #define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U) #define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U) /*! VIEW_DELAYED_RDN - VIEW_DELAYED_RDN */ #define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK) #define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U) #define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U) /*! SYND2GPMI_READY - SYND2GPMI_READY */ #define GPMI_DEBUG2_SYND2GPMI_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK) #define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U) #define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U) /*! SYND2GPMI_VALID - SYND2GPMI_VALID */ #define GPMI_DEBUG2_SYND2GPMI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK) #define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U) #define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U) /*! GPMI2SYND_READY - GPMI2SYND_READY */ #define GPMI_DEBUG2_GPMI2SYND_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK) #define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U) #define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U) /*! GPMI2SYND_VALID - GPMI2SYND_VALID */ #define GPMI_DEBUG2_GPMI2SYND_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK) #define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U) #define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U) /*! SYND2GPMI_BE - SYND2GPMI_BE */ #define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK) #define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U) #define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U) /*! MAIN_STATE - MAIN_STATE */ #define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK) #define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U) #define GPMI_DEBUG2_PIN_STATE_SHIFT (20U) /*! PIN_STATE - PIN_STATE */ #define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK) #define GPMI_DEBUG2_BUSY_MASK (0x800000U) #define GPMI_DEBUG2_BUSY_SHIFT (23U) /*! BUSY - BUSY */ #define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK) #define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U) #define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U) /*! UDMA_STATE - UDMA_STATE */ #define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK) #define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U) #define GPMI_DEBUG2_RSVD1_SHIFT (28U) /*! RSVD1 - RSVD1 */ #define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK) /*! @} */ /*! @name DEBUG3 - GPMI Debug3 Information Register Description */ /*! @{ */ #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU) #define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U) /*! DEV_WORD_CNTR - DEV_WORD_CNTR */ #define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK) #define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U) #define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U) /*! APB_WORD_CNTR - APB_WORD_CNTR */ #define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK) /*! @} */ /*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */ /*! @{ */ #define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U) #define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U) /*! ENABLE - ENABLE */ #define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK) #define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U) #define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U) /*! RESET - RESET */ #define GPMI_READ_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK) #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! SLV_FORCE_UPD - SLV_FORCE_UPD */ #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) /*! SLV_DLY_TARGET - SLV_DLY_TARGET */ #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) /*! GATE_UPDATE - GATE_UPDATE */ #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK) #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) /*! REFCLK_ON - REFCLK_ON */ #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK) #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) /*! SLV_OVERRIDE - SLV_OVERRIDE */ #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) /*! SLV_OVERRIDE_VAL - SLV_OVERRIDE_VAL */ #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) #define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U) /*! RSVD1 - RSVD1 */ #define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK) #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! SLV_UPDATE_INT - SLV_UPDATE_INT */ #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! REF_UPDATE_INT - REF_UPDATE_INT */ #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */ /*! @{ */ #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U) #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U) /*! ENABLE - ENABLE */ #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U) #define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U) /*! RESET - RESET */ #define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! SLV_FORCE_UPD - SLV_FORCE_UPD */ #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) /*! SLV_DLY_TARGET - SLV_DLY_TARGET */ #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) /*! GATE_UPDATE - GATE_UPDATE */ #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) /*! REFCLK_ON - REFCLK_ON */ #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) /*! SLV_OVERRIDE - SLV_OVERRIDE */ #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) /*! SLV_OVERRIDE_VAL - SLV_OVERRIDE_VAL */ #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U) /*! RSVD1 - RSVD1 */ #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! SLV_UPDATE_INT - SLV_UPDATE_INT */ #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! REF_UPDATE_INT - REF_UPDATE_INT */ #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */ /*! @{ */ #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) /*! SLV_LOCK - SLV_LOCK */ #define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK) #define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) #define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U) /*! SLV_SEL - SLV_SEL */ #define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK) #define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U) #define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U) /*! RSVD0 - RSVD0 */ #define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK) #define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) #define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U) /*! REF_LOCK - REF_LOCK */ #define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK) #define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) #define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U) /*! REF_SEL - REF_SEL */ #define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK) #define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) #define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U) /*! RSVD1 - RSVD1 */ #define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK) /*! @} */ /*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */ /*! @{ */ #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) /*! SLV_LOCK - SLV_LOCK */ #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK) #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U) /*! SLV_SEL - SLV_SEL */ #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK) #define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U) #define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U) /*! RSVD0 - RSVD0 */ #define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK) #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U) /*! REF_LOCK - REF_LOCK */ #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK) #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U) /*! REF_SEL - REF_SEL */ #define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK) #define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) #define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U) /*! RSVD1 - RSVD1 */ #define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK) /*! @} */ /*! @name TIMING3 - GPMI Timing Register 3 Description */ /*! @{ */ #define GPMI_TIMING3_TWWARMUP_MASK (0x1FU) #define GPMI_TIMING3_TWWARMUP_SHIFT (0U) /*! TWWARMUP - TWWARMUP */ #define GPMI_TIMING3_TWWARMUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_TWWARMUP_SHIFT)) & GPMI_TIMING3_TWWARMUP_MASK) #define GPMI_TIMING3_RSVD0_MASK (0xE0U) #define GPMI_TIMING3_RSVD0_SHIFT (5U) /*! RSVD0 - RSVD0 */ #define GPMI_TIMING3_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_RSVD0_SHIFT)) & GPMI_TIMING3_RSVD0_MASK) #define GPMI_TIMING3_TRWARMUP_MASK (0x1F00U) #define GPMI_TIMING3_TRWARMUP_SHIFT (8U) /*! TRWARMUP - TRWARMUP */ #define GPMI_TIMING3_TRWARMUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_TRWARMUP_SHIFT)) & GPMI_TIMING3_TRWARMUP_MASK) #define GPMI_TIMING3_RSVD1_MASK (0xFFFFE000U) #define GPMI_TIMING3_RSVD1_SHIFT (13U) /*! RSVD1 - RSVD1 */ #define GPMI_TIMING3_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_RSVD1_SHIFT)) & GPMI_TIMING3_RSVD1_MASK) /*! @} */ /*! @name CTRL2 - GPMI Control Register 2 Description */ /*! @{ */ #define GPMI_CTRL2_NVDDR2_MODE_MASK (0x1U) #define GPMI_CTRL2_NVDDR2_MODE_SHIFT (0U) /*! NVDDR2_MODE - NVDDR2_MODE */ #define GPMI_CTRL2_NVDDR2_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_NVDDR2_MODE_SHIFT)) & GPMI_CTRL2_NVDDR2_MODE_MASK) #define GPMI_CTRL2_TOGGLE20_MODE_MASK (0x2U) #define GPMI_CTRL2_TOGGLE20_MODE_SHIFT (1U) /*! TOGGLE20_MODE - TOGGLE20_MODE */ #define GPMI_CTRL2_TOGGLE20_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_TOGGLE20_MODE_SHIFT)) & GPMI_CTRL2_TOGGLE20_MODE_MASK) #define GPMI_CTRL2_WARMUP_EN_MASK (0x4U) #define GPMI_CTRL2_WARMUP_EN_SHIFT (2U) /*! WARMUP_EN - WARMUP_EN */ #define GPMI_CTRL2_WARMUP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_WARMUP_EN_SHIFT)) & GPMI_CTRL2_WARMUP_EN_MASK) #define GPMI_CTRL2_CEN_REDUCTION_MASK (0x8U) #define GPMI_CTRL2_CEN_REDUCTION_SHIFT (3U) /*! CEN_REDUCTION - CEN_REDUCTION */ #define GPMI_CTRL2_CEN_REDUCTION(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_CEN_REDUCTION_SHIFT)) & GPMI_CTRL2_CEN_REDUCTION_MASK) #define GPMI_CTRL2_RSVD0_MASK (0xFFFFFFF0U) #define GPMI_CTRL2_RSVD0_SHIFT (4U) /*! RSVD0 - RSVD0 */ #define GPMI_CTRL2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_RSVD0_SHIFT)) & GPMI_CTRL2_RSVD0_MASK) /*! @} */ /*! * @} */ /* end of group GPMI_Register_Masks */ /* GPMI - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__GPMI base address */ #define CONNECTIVITY__GPMI_BASE (0x5B812000u) /** Peripheral CONNECTIVITY__GPMI base pointer */ #define CONNECTIVITY__GPMI ((GPMI_Type *)CONNECTIVITY__GPMI_BASE) /** Array initializer of GPMI peripheral base addresses */ #define GPMI_BASE_ADDRS { CONNECTIVITY__GPMI_BASE } /** Array initializer of GPMI peripheral base pointers */ #define GPMI_BASE_PTRS { CONNECTIVITY__GPMI } /*! * @} */ /* end of group GPMI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer * @{ */ /** GPT - Register Layout Typedef */ typedef struct { __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ } GPT_Type; /* ---------------------------------------------------------------------------- -- GPT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPT_Register_Masks GPT Register Masks * @{ */ /*! @name CR - GPT Control Register */ /*! @{ */ #define GPT_CR_EN_MASK (0x1U) #define GPT_CR_EN_SHIFT (0U) /*! EN - EN * 0b0..GPT is disabled. * 0b1..GPT is enabled. */ #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) #define GPT_CR_ENMOD_MASK (0x2U) #define GPT_CR_ENMOD_SHIFT (1U) /*! ENMOD - ENMOD * 0b0..GPT counter will retain its value when it is disabled. * 0b1..GPT counter value is reset to 0 when it is disabled. */ #define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) #define GPT_CR_DBGEN_MASK (0x4U) #define GPT_CR_DBGEN_SHIFT (2U) /*! DBGEN - DBGEN * 0b0..GPT is disabled in debug mode. * 0b1..GPT is enabled in debug mode. */ #define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) #define GPT_CR_WAITEN_MASK (0x8U) #define GPT_CR_WAITEN_SHIFT (3U) /*! WAITEN - WAITEN * 0b0..GPT is disabled in wait mode. * 0b1..GPT is enabled in wait mode. */ #define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) #define GPT_CR_DOZEEN_MASK (0x10U) #define GPT_CR_DOZEEN_SHIFT (4U) /*! DOZEEN - DOZEEN * 0b0..GPT is disabled in doze mode. * 0b1..GPT is enabled in doze mode. */ #define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) #define GPT_CR_STOPEN_MASK (0x20U) #define GPT_CR_STOPEN_SHIFT (5U) /*! STOPEN - STOPEN * 0b0..GPT is disabled in Stop mode. * 0b1..GPT is enabled in Stop mode. */ #define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) #define GPT_CR_CLKSRC_MASK (0x1C0U) #define GPT_CR_CLKSRC_SHIFT (6U) /*! CLKSRC - CLKSRC * 0b000..No clock * 0b001..Peripheral Clock (ipg_clk) * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) * 0b011..External Clock * 0b100..Low Frequency Reference Clock (ipg_clk_32k) * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) */ #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) #define GPT_CR_FRR_MASK (0x200U) #define GPT_CR_FRR_SHIFT (9U) /*! FRR - FRR * 0b0..Restart mode * 0b1..Free-Run mode */ #define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) #define GPT_CR_EN_24M_MASK (0x400U) #define GPT_CR_EN_24M_SHIFT (10U) /*! EN_24M - EN_24M * 0b0..24M clock disabled * 0b1..24M clock enabled */ #define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) #define GPT_CR_SWR_MASK (0x8000U) #define GPT_CR_SWR_SHIFT (15U) /*! SWR - SWR * 0b0..GPT is not in reset state * 0b1..GPT is in reset state */ #define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) #define GPT_CR_IM1_MASK (0x30000U) #define GPT_CR_IM1_SHIFT (16U) /*! IM1 - IM1 */ #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) #define GPT_CR_IM2_MASK (0xC0000U) #define GPT_CR_IM2_SHIFT (18U) /*! IM2 - IM2 * 0b00..capture disabled * 0b01..capture on rising edge only * 0b10..capture on falling edge only * 0b11..capture on both edges */ #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) #define GPT_CR_OM1_MASK (0x700000U) #define GPT_CR_OM1_SHIFT (20U) /*! OM1 - OM1 */ #define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) #define GPT_CR_OM2_MASK (0x3800000U) #define GPT_CR_OM2_SHIFT (23U) /*! OM2 - OM2 */ #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) #define GPT_CR_OM3_MASK (0x1C000000U) #define GPT_CR_OM3_SHIFT (26U) /*! OM3 - OM3 * 0b000..Output disconnected. No response on pin. * 0b001..Toggle output pin * 0b010..Clear output pin * 0b011..Set output pin * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. */ #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) #define GPT_CR_FO1_MASK (0x20000000U) #define GPT_CR_FO1_SHIFT (29U) /*! FO1 - FO1 */ #define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) #define GPT_CR_FO2_MASK (0x40000000U) #define GPT_CR_FO2_SHIFT (30U) /*! FO2 - FO2 */ #define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) #define GPT_CR_FO3_MASK (0x80000000U) #define GPT_CR_FO3_SHIFT (31U) /*! FO3 - FO3 * 0b0..Writing a 0 has no effect. * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. */ #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) /*! @} */ /*! @name PR - GPT Prescaler Register */ /*! @{ */ #define GPT_PR_PRESCALER_MASK (0xFFFU) #define GPT_PR_PRESCALER_SHIFT (0U) /*! PRESCALER - PRESCALER * 0b000000000000..Divide by 1 * 0b000000000001..Divide by 2 * 0b111111111111..Divide by 4096 */ #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) #define GPT_PR_PRESCALER24M_MASK (0xF000U) #define GPT_PR_PRESCALER24M_SHIFT (12U) /*! PRESCALER24M - PRESCALER24M * 0b0000..Divide by 1 * 0b0001..Divide by 2 * 0b1111..Divide by 16 */ #define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) /*! @} */ /*! @name SR - GPT Status Register */ /*! @{ */ #define GPT_SR_OF1_MASK (0x1U) #define GPT_SR_OF1_SHIFT (0U) /*! OF1 - OF1 */ #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) #define GPT_SR_OF2_MASK (0x2U) #define GPT_SR_OF2_SHIFT (1U) /*! OF2 - OF2 */ #define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) #define GPT_SR_OF3_MASK (0x4U) #define GPT_SR_OF3_SHIFT (2U) /*! OF3 - OF3 * 0b0..Compare event has not occurred. * 0b1..Compare event has occurred. */ #define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) #define GPT_SR_IF1_MASK (0x8U) #define GPT_SR_IF1_SHIFT (3U) /*! IF1 - IF1 */ #define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) #define GPT_SR_IF2_MASK (0x10U) #define GPT_SR_IF2_SHIFT (4U) /*! IF2 - IF2 * 0b0..Capture event has not occurred. * 0b1..Capture event has occurred. */ #define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) #define GPT_SR_ROV_MASK (0x20U) #define GPT_SR_ROV_SHIFT (5U) /*! ROV - ROV * 0b0..Rollover has not occurred. * 0b1..Rollover has occurred. */ #define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) /*! @} */ /*! @name IR - GPT Interrupt Register */ /*! @{ */ #define GPT_IR_OF1IE_MASK (0x1U) #define GPT_IR_OF1IE_SHIFT (0U) /*! OF1IE - OF1IE */ #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) #define GPT_IR_OF2IE_MASK (0x2U) #define GPT_IR_OF2IE_SHIFT (1U) /*! OF2IE - OF2IE */ #define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) #define GPT_IR_OF3IE_MASK (0x4U) #define GPT_IR_OF3IE_SHIFT (2U) /*! OF3IE - OF3IE * 0b0..Output Compare Channel n interrupt is disabled. * 0b1..Output Compare Channel n interrupt is enabled. */ #define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) #define GPT_IR_IF1IE_MASK (0x8U) #define GPT_IR_IF1IE_SHIFT (3U) /*! IF1IE - IF1IE */ #define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) #define GPT_IR_IF2IE_MASK (0x10U) #define GPT_IR_IF2IE_SHIFT (4U) /*! IF2IE - IF2IE * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. */ #define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) #define GPT_IR_ROVIE_MASK (0x20U) #define GPT_IR_ROVIE_SHIFT (5U) /*! ROVIE - ROVIE * 0b0..Rollover interrupt is disabled. * 0b1..Rollover interrupt enabled. */ #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) /*! @} */ /*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ /*! @{ */ #define GPT_OCR_COMP_MASK (0xFFFFFFFFU) #define GPT_OCR_COMP_SHIFT (0U) /*! COMP - COMP */ #define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) /*! @} */ /* The count of GPT_OCR */ #define GPT_OCR_COUNT (3U) /*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ /*! @{ */ #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) #define GPT_ICR_CAPT_SHIFT (0U) /*! CAPT - CAPT */ #define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) /*! @} */ /* The count of GPT_ICR */ #define GPT_ICR_COUNT (2U) /*! @name CNT - GPT Counter Register */ /*! @{ */ #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) #define GPT_CNT_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) /*! @} */ /*! * @} */ /* end of group GPT_Register_Masks */ /* GPT - Peripheral instance base addresses */ /** Peripheral ADMA__GPT0 base address */ #define ADMA__GPT0_BASE (0x590B0000u) /** Peripheral ADMA__GPT0 base pointer */ #define ADMA__GPT0 ((GPT_Type *)ADMA__GPT0_BASE) /** Peripheral ADMA__GPT1 base address */ #define ADMA__GPT1_BASE (0x590C0000u) /** Peripheral ADMA__GPT1 base pointer */ #define ADMA__GPT1 ((GPT_Type *)ADMA__GPT1_BASE) /** Peripheral ADMA__GPT2 base address */ #define ADMA__GPT2_BASE (0x590D0000u) /** Peripheral ADMA__GPT2 base pointer */ #define ADMA__GPT2 ((GPT_Type *)ADMA__GPT2_BASE) /** Peripheral ADMA__GPT3 base address */ #define ADMA__GPT3_BASE (0x590E0000u) /** Peripheral ADMA__GPT3 base pointer */ #define ADMA__GPT3 ((GPT_Type *)ADMA__GPT3_BASE) /** Peripheral ADMA__GPT4 base address */ #define ADMA__GPT4_BASE (0x590F0000u) /** Peripheral ADMA__GPT4 base pointer */ #define ADMA__GPT4 ((GPT_Type *)ADMA__GPT4_BASE) /** Peripheral ADMA__GPT5 base address */ #define ADMA__GPT5_BASE (0x59100000u) /** Peripheral ADMA__GPT5 base pointer */ #define ADMA__GPT5 ((GPT_Type *)ADMA__GPT5_BASE) /** Peripheral LSIO__GPT0 base address */ #define LSIO__GPT0_BASE (0x5D140000u) /** Peripheral LSIO__GPT0 base pointer */ #define LSIO__GPT0 ((GPT_Type *)LSIO__GPT0_BASE) /** Peripheral LSIO__GPT1 base address */ #define LSIO__GPT1_BASE (0x5D150000u) /** Peripheral LSIO__GPT1 base pointer */ #define LSIO__GPT1 ((GPT_Type *)LSIO__GPT1_BASE) /** Peripheral LSIO__GPT2 base address */ #define LSIO__GPT2_BASE (0x5D160000u) /** Peripheral LSIO__GPT2 base pointer */ #define LSIO__GPT2 ((GPT_Type *)LSIO__GPT2_BASE) /** Peripheral LSIO__GPT3 base address */ #define LSIO__GPT3_BASE (0x5D170000u) /** Peripheral LSIO__GPT3 base pointer */ #define LSIO__GPT3 ((GPT_Type *)LSIO__GPT3_BASE) /** Peripheral LSIO__GPT4 base address */ #define LSIO__GPT4_BASE (0x5D180000u) /** Peripheral LSIO__GPT4 base pointer */ #define LSIO__GPT4 ((GPT_Type *)LSIO__GPT4_BASE) /** Array initializer of GPT peripheral base addresses */ #define GPT_BASE_ADDRS { ADMA__GPT0_BASE, ADMA__GPT1_BASE, ADMA__GPT2_BASE, ADMA__GPT3_BASE, ADMA__GPT4_BASE, ADMA__GPT5_BASE, LSIO__GPT0_BASE, LSIO__GPT1_BASE, LSIO__GPT2_BASE, LSIO__GPT3_BASE, LSIO__GPT4_BASE } /** Array initializer of GPT peripheral base pointers */ #define GPT_BASE_PTRS { ADMA__GPT0, ADMA__GPT1, ADMA__GPT2, ADMA__GPT3, ADMA__GPT4, ADMA__GPT5, LSIO__GPT0, LSIO__GPT1, LSIO__GPT2, LSIO__GPT3, LSIO__GPT4 } /** Interrupt vectors for the GPT peripheral type */ #define GPT_IRQS { ADMA_GPT0_INT_IRQn, ADMA_GPT1_INT_IRQn, ADMA_GPT2_INT_IRQn, ADMA_GPT3_INT_IRQn, ADMA_GPT4_INT_IRQn, ADMA_GPT5_INT_IRQn, LSIO_GPT0_INT_IRQn, LSIO_GPT1_INT_IRQn, LSIO_GPT2_INT_IRQn, LSIO_GPT3_INT_IRQn, LSIO_GPT4_INT_IRQn } /*! * @} */ /* end of group GPT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- HSIO_CSR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup HSIO_CSR_Peripheral_Access_Layer HSIO_CSR Peripheral Access Layer * @{ */ /** HSIO_CSR - Register Layout Typedef */ typedef struct { __IO uint32_t PHYX1_CTRL0; /**< , offset: 0x0 */ __I uint32_t PHYX1_STTS0; /**< , offset: 0x4 */ uint8_t RESERVED_0[131064]; __IO uint32_t PCIEX1_CTRL0; /**< , offset: 0x20000 */ __IO uint32_t PCIEX1_CTRL1; /**< , offset: 0x20004 */ __IO uint32_t PCIEX1_CTRL2; /**< , offset: 0x20008 */ __I uint32_t PCIEX1_STTS0; /**< , offset: 0x2000C */ __I uint32_t PCIEX1_STTS1; /**< , offset: 0x20010 */ __I uint32_t PCIEX1_STTS2; /**< , offset: 0x20014 */ uint8_t RESERVED_1[131048]; __IO uint32_t MISC_CTRL0; /**< , offset: 0x40000 */ uint32_t MISC_STTS0; /**< , offset: 0x40004 */ } HSIO_CSR_Type; /* ---------------------------------------------------------------------------- -- HSIO_CSR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup HSIO_CSR_Register_Masks HSIO_CSR Register Masks * @{ */ /*! @name PHYX1_CTRL0 - */ /*! @{ */ #define HSIO_CSR_PHYX1_CTRL0_APB_RSTN_MASK (0x1U) #define HSIO_CSR_PHYX1_CTRL0_APB_RSTN_SHIFT (0U) #define HSIO_CSR_PHYX1_CTRL0_APB_RSTN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_APB_RSTN_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_APB_RSTN_MASK) #define HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_MASK (0x400U) #define HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_SHIFT (10U) #define HSIO_CSR_PHYX1_CTRL0_AIDDQ_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_MASK) #define HSIO_CSR_PHYX1_CTRL0_PHY_MODE_MASK (0x1E0000U) #define HSIO_CSR_PHYX1_CTRL0_PHY_MODE_SHIFT (17U) #define HSIO_CSR_PHYX1_CTRL0_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_PHY_MODE_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_PHY_MODE_MASK) #define HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_MASK (0x200000U) #define HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_SHIFT (21U) #define HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_MASK) #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_MASK (0x1000000U) #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_SHIFT (24U) #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_MASK) #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_MASK (0x2000000U) #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_SHIFT (25U) #define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_MASK) /*! @} */ /*! @name PHYX1_STTS0 - */ /*! @{ */ #define HSIO_CSR_PHYX1_STTS0_TEST_OUT_MASK (0xFFU) #define HSIO_CSR_PHYX1_STTS0_TEST_OUT_SHIFT (0U) /*! TEST_OUT - TEST_OUT[7:0] */ #define HSIO_CSR_PHYX1_STTS0_TEST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_STTS0_TEST_OUT_SHIFT)) & HSIO_CSR_PHYX1_STTS0_TEST_OUT_MASK) #define HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_MASK (0x10000U) #define HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_SHIFT (16U) #define HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_SHIFT)) & HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_MASK) #define HSIO_CSR_PHYX1_STTS0_EPCS_READY_MASK (0x40000U) #define HSIO_CSR_PHYX1_STTS0_EPCS_READY_SHIFT (18U) #define HSIO_CSR_PHYX1_STTS0_EPCS_READY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_STTS0_EPCS_READY_SHIFT)) & HSIO_CSR_PHYX1_STTS0_EPCS_READY_MASK) /*! @} */ /*! @name PCIEX1_CTRL0 - */ /*! @{ */ #define HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_MASK (0xFFFFU) #define HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_SHIFT (0U) #define HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_MASK) #define HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_MASK (0xFF0000U) #define HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_SHIFT (16U) #define HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_MASK) #define HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_MASK (0xF000000U) #define HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_SHIFT (24U) #define HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_SHIFT)) & HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_MASK) /*! @} */ /*! @name PCIEX1_CTRL1 - */ /*! @{ */ #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_MASK (0x3FU) #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_SHIFT (0U) #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_MASK) #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_MASK (0x3C0U) #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_SHIFT (6U) #define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_MASK) #define HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_MASK (0x400U) #define HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_SHIFT (10U) #define HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_MASK) #define HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_MASK (0x800U) #define HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_SHIFT (11U) #define HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_MASK) #define HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_MASK (0x4000U) #define HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_SHIFT (14U) #define HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_MASK) /*! @} */ /*! @name PCIEX1_CTRL2 - */ /*! @{ */ #define HSIO_CSR_PCIEX1_CTRL2_SYS_INT_MASK (0x3U) #define HSIO_CSR_PCIEX1_CTRL2_SYS_INT_SHIFT (0U) #define HSIO_CSR_PCIEX1_CTRL2_SYS_INT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_SYS_INT_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_SYS_INT_MASK) #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_MASK (0x4U) #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_SHIFT (2U) #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_MASK) #define HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_MASK (0x8U) #define HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_SHIFT (3U) #define HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_MASK) #define HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_MASK (0x10U) #define HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_SHIFT (4U) #define HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_MASK) #define HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_MASK (0x20U) #define HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_SHIFT (5U) #define HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_MASK) #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_MASK (0x40U) #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_SHIFT (6U) #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_MASK) #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_MASK (0x80U) #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_SHIFT (7U) #define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_MASK) #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_MASK (0x100U) #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_SHIFT (8U) #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_MASK) #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_MASK (0x200U) #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_SHIFT (9U) #define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_MASK) #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_MASK (0x400U) #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_SHIFT (10U) #define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_MASK) #define HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_MASK (0x800U) #define HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_SHIFT (11U) #define HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_MASK) #define HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_MASK (0x1E000U) #define HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_SHIFT (13U) #define HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_MASK) #define HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_MASK (0xE0000U) #define HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_SHIFT (17U) #define HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_MASK) #define HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_MASK (0x200000U) #define HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_SHIFT (21U) #define HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_MASK) #define HSIO_CSR_PCIEX1_CTRL2_PERST_N_MASK (0x400000U) #define HSIO_CSR_PCIEX1_CTRL2_PERST_N_SHIFT (22U) #define HSIO_CSR_PCIEX1_CTRL2_PERST_N(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_PERST_N_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_PERST_N_MASK) #define HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__MASK (0x800000U) #define HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__SHIFT (23U) #define HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N_(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__MASK) #define HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_MASK (0x4000000U) #define HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_SHIFT (26U) #define HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_MASK) /*! @} */ /*! @name PCIEX1_STTS0 - */ /*! @{ */ #define HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_MASK (0x3FU) #define HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_SHIFT (0U) #define HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_MASK) #define HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_MASK (0x40U) #define HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_SHIFT (6U) #define HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_MASK) #define HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_MASK (0x380U) #define HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_SHIFT (7U) #define HSIO_CSR_PCIEX1_STTS0_PM_DSTATE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_MASK) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_MASK (0x400U) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_SHIFT (10U) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_MASK) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_MASK (0x800U) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_SHIFT (11U) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_MASK) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_MASK (0x1000U) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_SHIFT (12U) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_MASK) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_MASK (0x2000U) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_SHIFT (13U) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_MASK) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_MASK (0x4000U) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_SHIFT (14U) #define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_MASK) #define HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_MASK (0x8000U) #define HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_SHIFT (15U) #define HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_MASK) #define HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_MASK (0x10000U) #define HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_SHIFT (16U) #define HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_MASK) #define HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_MASK (0x20000U) #define HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_SHIFT (17U) #define HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_MASK) #define HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_MASK (0x40000U) #define HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_SHIFT (18U) #define HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_MASK) #define HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_MASK (0x80000U) #define HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_SHIFT (19U) #define HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_MASK) #define HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_MASK (0x400000U) #define HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_SHIFT (22U) #define HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_MASK) /*! @} */ /*! @name PCIEX1_STTS1 - */ /*! @{ */ #define HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_MASK (0xFFFFU) #define HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_SHIFT (0U) #define HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_SHIFT)) & HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_MASK) /*! @} */ /*! @name PCIEX1_STTS2 - */ /*! @{ */ #define HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_MASK (0xFFFFFFFFU) #define HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_SHIFT (0U) #define HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_SHIFT)) & HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_MASK) /*! @} */ /*! @name MISC_CTRL0 - */ /*! @{ */ #define HSIO_CSR_MISC_CTRL0_IOB_RXENA_MASK (0x1U) #define HSIO_CSR_MISC_CTRL0_IOB_RXENA_SHIFT (0U) #define HSIO_CSR_MISC_CTRL0_IOB_RXENA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_RXENA_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_RXENA_MASK) #define HSIO_CSR_MISC_CTRL0_IOB_TXENA_MASK (0x2U) #define HSIO_CSR_MISC_CTRL0_IOB_TXENA_SHIFT (1U) #define HSIO_CSR_MISC_CTRL0_IOB_TXENA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_TXENA_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_TXENA_MASK) #define HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_MASK (0x4U) #define HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_SHIFT (2U) #define HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_MASK) #define HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_MASK (0x18U) #define HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_SHIFT (3U) #define HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_MASK) #define HSIO_CSR_MISC_CTRL0_FAST_INIT_MASK (0x800U) #define HSIO_CSR_MISC_CTRL0_FAST_INIT_SHIFT (11U) #define HSIO_CSR_MISC_CTRL0_FAST_INIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_FAST_INIT_SHIFT)) & HSIO_CSR_MISC_CTRL0_FAST_INIT_MASK) #define HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_MASK (0x1000U) #define HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_SHIFT (12U) /*! PHY_X1_EPCS_SEL - PHY_X1_EPCS_SEL will be used for ECO for PCIe controller bug fix. */ #define HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_SHIFT)) & HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_MASK) #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_MASK (0x400000U) #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_SHIFT (22U) #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_MASK) #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_MASK (0x1000000U) #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_SHIFT (24U) #define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_MASK) #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_MASK (0x4000000U) #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_SHIFT (26U) #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_MASK) #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_MASK (0x10000000U) #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_SHIFT (28U) #define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_MASK) /*! @} */ /*! * @} */ /* end of group HSIO_CSR_Register_Masks */ /* HSIO_CSR - Peripheral instance base addresses */ /** Peripheral HSIO_CSR base address */ #define HSIO_CSR_BASE (0x5F120000u) /** Peripheral HSIO_CSR base pointer */ #define HSIO_CSR ((HSIO_CSR_Type *)HSIO_CSR_BASE) /** Array initializer of HSIO_CSR peripheral base addresses */ #define HSIO_CSR_BASE_ADDRS { HSIO_CSR_BASE } /** Array initializer of HSIO_CSR peripheral base pointers */ #define HSIO_CSR_BASE_PTRS { HSIO_CSR } /*! * @} */ /* end of group HSIO_CSR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I2S Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer * @{ */ /** I2S - Register Layout Typedef */ typedef struct { __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ uint8_t RESERVED_0[8]; __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[28]; __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ uint8_t RESERVED_2[28]; __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ uint8_t RESERVED_3[28]; __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ uint8_t RESERVED_4[8]; __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_5[28]; __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_6[28]; __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ } I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /*! @name TCSR - SAI Transmit Control Register */ /*! @{ */ #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag * 0b0..Transmit FIFO watermark has not been reached. * 0b1..Transmit FIFO watermark has been reached. */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag * 0b0..No enabled transmit FIFO is empty. * 0b1..Enabled transmit FIFO is empty. */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag * 0b0..Transmit underrun not detected. * 0b1..Transmit underrun detected. */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag * 0b0..Sync error not detected. * 0b1..Frame sync error detected. */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag * 0b0..Start of word not detected. * 0b1..Start of word detected. */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) #define I2S_TCSR_SR_MASK (0x1000000U) #define I2S_TCSR_SR_SHIFT (24U) /*! SR - Software Reset * 0b0..No effect. * 0b1..Software reset. */ #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) /*! FR - FIFO Reset * 0b0..No effect. * 0b1..FIFO reset. */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable * 0b0..Transmit bit clock is disabled. * 0b1..Transmit bit clock is enabled. */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. * 0b1..Transmitter is enabled in Debug mode. */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable * 0b0..Transmitter disabled in Stop mode. * 0b1..Transmitter enabled in Stop mode. */ #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) /*! TE - Transmitter Enable * 0b0..Transmitter is disabled. * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. */ #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) /*! @} */ /*! @name TCR1 - SAI Transmit Configuration 1 Register */ /*! @{ */ #define I2S_TCR1_TFW_MASK (0x3FU) #define I2S_TCR1_TFW_SHIFT (0U) /*! TFW - Transmit FIFO Watermark */ #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /*! @} */ /*! @name TCR2 - SAI Transmit Configuration 2 Register */ /*! @{ */ #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) /*! DIV - Bit Clock Divide */ #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction * 0b0..Bit clock is generated externally in Slave mode. * 0b1..Bit clock is generated internally in Master mode. */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select * 0b00..Bus Clock selected. * 0b01..Master Clock (MCLK) 1 option selected. * 0b10..Master Clock (MCLK) 2 option selected. * 0b11..Master Clock (MCLK) 3 option selected. */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input * 0b0..No effect. * 0b1..Internal logic is clocked as if bit clock was externally generated. */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap * 0b0..Use the normal bit clock source. * 0b1..Swap the bit clock source. */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) #define I2S_TCR2_SYNC_MASK (0xC0000000U) #define I2S_TCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode * 0b00..Asynchronous mode. * 0b01..Synchronous with receiver. * 0b10..Synchronous with another SAI transmitter. * 0b11..Synchronous with another SAI receiver. */ #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) /*! @} */ /*! @name TCR3 - SAI Transmit Configuration 3 Register */ /*! @{ */ #define I2S_TCR3_WDFL_MASK (0x1FU) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define I2S_TCR3_WDFL_SHIFT (0U) /*! WDFL - Word Flag Configuration */ #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define I2S_TCR3_TCE_MASK (0x10000U) #define I2S_TCR3_TCE_SHIFT (16U) /*! TCE - Transmit Channel Enable */ #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /*! @} */ /*! @name TCR4 - SAI Transmit Configuration 4 Register */ /*! @{ */ #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction * 0b0..Frame sync is generated externally in Slave mode. * 0b1..Frame sync is generated internally in Master mode. */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity * 0b0..Frame sync is active high. * 0b1..Frame sync is active low. */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_ONDEM_MASK (0x4U) #define I2S_TCR4_ONDEM_SHIFT (2U) /*! ONDEM - On Demand Mode * 0b0..Internal frame sync is generated continuously. * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. */ #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early * 0b0..Frame sync asserts with the first bit of the frame. * 0b1..Frame sync asserts one bit before the first bit of the frame. */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) /*! MF - MSB First * 0b0..LSB is transmitted first. * 0b1..MSB is transmitted first. */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_SYWD_MASK (0x1F00U) #define I2S_TCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width */ #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) #define I2S_TCR4_FRSZ_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define I2S_TCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame size */ #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define I2S_TCR4_FPACK_MASK (0x3000000U) #define I2S_TCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode * 0b00..FIFO packing is disabled * 0b01..Reserved * 0b10..8-bit FIFO packing is enabled * 0b11..16-bit FIFO packing is enabled */ #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. */ #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) /*! @} */ /*! @name TCR5 - SAI Transmit Configuration 5 Register */ /*! @{ */ #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted */ #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) #define I2S_TCR5_W0W_MASK (0x1F0000U) #define I2S_TCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width */ #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) /*! WNW - Word N Width */ #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) /*! @} */ /*! @name TDR - SAI Transmit Data Register */ /*! @{ */ #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) /*! TDR - Transmit Data Register */ #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) /*! @} */ /* The count of I2S_TDR */ #define I2S_TDR_COUNT (1U) /*! @name TFR - SAI Transmit FIFO Register */ /*! @{ */ #define I2S_TFR_RFP_MASK (0x7FU) #define I2S_TFR_RFP_SHIFT (0U) /*! RFP - Read FIFO Pointer */ #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) #define I2S_TFR_WFP_MASK (0x7F0000U) #define I2S_TFR_WFP_SHIFT (16U) /*! WFP - Write FIFO Pointer */ #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) /*! @} */ /* The count of I2S_TFR */ #define I2S_TFR_COUNT (1U) /*! @name TMR - SAI Transmit Mask Register */ /*! @{ */ #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (8, 32), largest definition used */ #define I2S_TMR_TWM_SHIFT (0U) /*! TWM - Transmit Word Mask * 0b00000000000000000000000000000000..Word N is enabled. * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked. */ #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) /* Merged from fields with different position or width, of widths (8, 32), largest definition used */ /*! @} */ /*! @name RCSR - SAI Receive Control Register */ /*! @{ */ #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable * 0b0..Disables the DMA request. * 0b1..Enables the DMA request. */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disables the interrupt. * 0b1..Enables the interrupt. */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable * 0b0..Disables interrupt. * 0b1..Enables interrupt. */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag * 0b0..Receive FIFO watermark not reached. * 0b1..Receive FIFO watermark has been reached. */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag * 0b0..No enabled receive FIFO is full. * 0b1..Enabled receive FIFO is full. */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag * 0b0..Receive overflow not detected. * 0b1..Receive overflow detected. */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag * 0b0..Sync error not detected. * 0b1..Frame sync error detected. */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag * 0b0..Start of word not detected. * 0b1..Start of word detected. */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) /*! SR - Software Reset * 0b0..No effect. * 0b1..Software reset. */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) /*! FR - FIFO Reset * 0b0..No effect. * 0b1..FIFO reset. */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable * 0b0..Receive bit clock is disabled. * 0b1..Receive bit clock is enabled. */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable * 0b0..Receiver is disabled in Debug mode, after completing the current frame. * 0b1..Receiver is enabled in Debug mode. */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable * 0b0..Receiver disabled in Stop mode. * 0b1..Receiver enabled in Stop mode. */ #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) /*! RE - Receiver Enable * 0b0..Receiver is disabled. * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. */ #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) /*! @} */ /*! @name RCR1 - SAI Receive Configuration 1 Register */ /*! @{ */ #define I2S_RCR1_RFW_MASK (0x3FU) #define I2S_RCR1_RFW_SHIFT (0U) /*! RFW - Receive FIFO Watermark */ #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /*! @} */ /*! @name RCR2 - SAI Receive Configuration 2 Register */ /*! @{ */ #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) /*! DIV - Bit Clock Divide */ #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction * 0b0..Bit clock is generated externally in Slave mode. * 0b1..Bit clock is generated internally in Master mode. */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select * 0b00..Bus Clock selected. * 0b01..Master Clock (MCLK) 1 option selected. * 0b10..Master Clock (MCLK) 2 option selected. * 0b11..Master Clock (MCLK) 3 option selected. */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input * 0b0..No effect. * 0b1..Internal logic is clocked as if bit clock was externally generated. */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap * 0b0..Use the normal bit clock source. * 0b1..Swap the bit clock source. */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) #define I2S_RCR2_SYNC_MASK (0xC0000000U) #define I2S_RCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode * 0b00..Asynchronous mode. * 0b01..Synchronous with transmitter. * 0b10..Synchronous with another SAI receiver. * 0b11..Synchronous with another SAI transmitter. */ #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) /*! @} */ /*! @name RCR3 - SAI Receive Configuration 3 Register */ /*! @{ */ #define I2S_RCR3_WDFL_MASK (0x1FU) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define I2S_RCR3_WDFL_SHIFT (0U) /*! WDFL - Word Flag Configuration */ #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define I2S_RCR3_RCE_MASK (0x10000U) #define I2S_RCR3_RCE_SHIFT (16U) /*! RCE - Receive Channel Enable */ #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /*! @} */ /*! @name RCR4 - SAI Receive Configuration 4 Register */ /*! @{ */ #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction * 0b0..Frame Sync is generated externally in Slave mode. * 0b1..Frame Sync is generated internally in Master mode. */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity * 0b0..Frame sync is active high. * 0b1..Frame sync is active low. */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_ONDEM_MASK (0x4U) #define I2S_RCR4_ONDEM_SHIFT (2U) /*! ONDEM - On Demand Mode * 0b0..Internal frame sync is generated continuously. * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. */ #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early * 0b0..Frame sync asserts with the first bit of the frame. * 0b1..Frame sync asserts one bit before the first bit of the frame. */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) /*! MF - MSB First * 0b0..LSB is received first. * 0b1..MSB is received first. */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width */ #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) #define I2S_RCR4_FRSZ_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define I2S_RCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame Size */ #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define I2S_RCR4_FPACK_MASK (0x3000000U) #define I2S_RCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode * 0b00..FIFO packing is disabled * 0b01..Reserved. * 0b10..8-bit FIFO packing is enabled * 0b11..16-bit FIFO packing is enabled */ #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. */ #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) /*! @} */ /*! @name RCR5 - SAI Receive Configuration 5 Register */ /*! @{ */ #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted */ #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) #define I2S_RCR5_W0W_MASK (0x1F0000U) #define I2S_RCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width */ #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) /*! WNW - Word N Width */ #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) /*! @} */ /*! @name RDR - SAI Receive Data Register */ /*! @{ */ #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) /*! RDR - Receive Data Register */ #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) /*! @} */ /* The count of I2S_RDR */ #define I2S_RDR_COUNT (1U) /*! @name RFR - SAI Receive FIFO Register */ /*! @{ */ #define I2S_RFR_RFP_MASK (0x7FU) #define I2S_RFR_RFP_SHIFT (0U) /*! RFP - Read FIFO Pointer */ #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) #define I2S_RFR_WFP_MASK (0x7F0000U) #define I2S_RFR_WFP_SHIFT (16U) /*! WFP - Write FIFO Pointer */ #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) /*! @} */ /* The count of I2S_RFR */ #define I2S_RFR_COUNT (1U) /*! @name RMR - SAI Receive Mask Register */ /*! @{ */ #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (8, 32), largest definition used */ #define I2S_RMR_RWM_SHIFT (0U) /*! RWM - Receive Word Mask * 0b00000000000000000000000000000000..Word N is enabled. * 0b00000000000000000000000000000001..Word N is masked. */ #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /* Merged from fields with different position or width, of widths (8, 32), largest definition used */ /*! @} */ /*! * @} */ /* end of group I2S_Register_Masks */ /* I2S - Peripheral instance base addresses */ /** Peripheral ADMA__SAI0 base address */ #define ADMA__SAI0_BASE (0x59040000u) /** Peripheral ADMA__SAI0 base pointer */ #define ADMA__SAI0 ((I2S_Type *)ADMA__SAI0_BASE) /** Peripheral ADMA__SAI1 base address */ #define ADMA__SAI1_BASE (0x59050000u) /** Peripheral ADMA__SAI1 base pointer */ #define ADMA__SAI1 ((I2S_Type *)ADMA__SAI1_BASE) /** Peripheral ADMA__SAI2 base address */ #define ADMA__SAI2_BASE (0x59060000u) /** Peripheral ADMA__SAI2 base pointer */ #define ADMA__SAI2 ((I2S_Type *)ADMA__SAI2_BASE) /** Peripheral ADMA__SAI3 base address */ #define ADMA__SAI3_BASE (0x59070000u) /** Peripheral ADMA__SAI3 base pointer */ #define ADMA__SAI3 ((I2S_Type *)ADMA__SAI3_BASE) /** Peripheral ADMA__SAI4 base address */ #define ADMA__SAI4_BASE (0x59820000u) /** Peripheral ADMA__SAI4 base pointer */ #define ADMA__SAI4 ((I2S_Type *)ADMA__SAI4_BASE) /** Peripheral ADMA__SAI5 base address */ #define ADMA__SAI5_BASE (0x59830000u) /** Peripheral ADMA__SAI5 base pointer */ #define ADMA__SAI5 ((I2S_Type *)ADMA__SAI5_BASE) /** Array initializer of I2S peripheral base addresses */ #define I2S_BASE_ADDRS { ADMA__SAI0_BASE, ADMA__SAI1_BASE, ADMA__SAI2_BASE, ADMA__SAI3_BASE, ADMA__SAI4_BASE, ADMA__SAI5_BASE } /** Array initializer of I2S peripheral base pointers */ #define I2S_BASE_PTRS { ADMA__SAI0, ADMA__SAI1, ADMA__SAI2, ADMA__SAI3, ADMA__SAI4, ADMA__SAI5 } /** Interrupt vectors for the I2S peripheral type */ #define I2S_RX_IRQS { ADMA_SAI0_INT_IRQn, ADMA_SAI1_INT_IRQn, ADMA_SAI2_INT_IRQn, ADMA_SAI3_INT_IRQn, ADMA_SAI4_INT_IRQn, ADMA_SAI5_INT_IRQn } #define I2S_TX_IRQS { ADMA_SAI0_INT_IRQn, ADMA_SAI1_INT_IRQn, ADMA_SAI2_INT_IRQn, ADMA_SAI3_INT_IRQn, ADMA_SAI4_INT_IRQn, ADMA_SAI5_INT_IRQn } /*! * @} */ /* end of group I2S_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_MJPEG_COMMON_DEC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_MJPEG_COMMON_DEC_Peripheral_Access_Layer IMAGING_LPCG_MJPEG_COMMON_DEC Peripheral Access Layer * @{ */ /** IMAGING_LPCG_MJPEG_COMMON_DEC - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MJPEG_COMMON_DEC_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_MJPEG_COMMON_DEC_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_MJPEG_COMMON_DEC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_MJPEG_COMMON_DEC_Register_Masks IMAGING_LPCG_MJPEG_COMMON_DEC Register Masks * @{ */ /*! @name LPCG_MJPEG_COMMON_DEC_0 - na */ /*! @{ */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_MASK (0x1U) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_SHIFT (0U) /*! decode_jpeg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_MASK) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_MASK (0x2U) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_SHIFT (1U) /*! decode_jpeg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_MASK) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_SHIFT (2U) /*! LPCG_MJPEG_Common_Dec_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_MASK) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_MASK (0x8U) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_SHIFT (3U) /*! decode_jpeg_clk_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_MASK) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_MASK (0x1FFF0U) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_SHIFT (4U) /*! LPCG_MJPEG_Common_Dec_0_reserved_4_16 - reserved */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_MASK) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_MASK (0x20000U) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_SHIFT (17U) /*! decode_ips_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_MASK) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_MASK (0x40000U) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_SHIFT (18U) /*! LPCG_MJPEG_Common_Dec_0_reserved_18_18 - reserved */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_MASK) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_MASK (0x80000U) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_SHIFT (19U) /*! decode_ips_clk_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_MASK) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_MASK (0xFFF00000U) #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_SHIFT (20U) /*! LPCG_MJPEG_Common_Dec_0_reserved_20_31 - reserved */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_MJPEG_COMMON_DEC_Register_Masks */ /* IMAGING_LPCG_MJPEG_COMMON_DEC - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_DECODE_IPS_CLK base address */ #define IMAGING__LPCG_DECODE_IPS_CLK_BASE (0x585D0000u) /** Peripheral IMAGING__LPCG_DECODE_IPS_CLK base pointer */ #define IMAGING__LPCG_DECODE_IPS_CLK ((IMAGING_LPCG_MJPEG_COMMON_DEC_Type *)IMAGING__LPCG_DECODE_IPS_CLK_BASE) /** Peripheral IMAGING__LPCG_DECODE_JPEG_CLK base address */ #define IMAGING__LPCG_DECODE_JPEG_CLK_BASE (0x585D0000u) /** Peripheral IMAGING__LPCG_DECODE_JPEG_CLK base pointer */ #define IMAGING__LPCG_DECODE_JPEG_CLK ((IMAGING_LPCG_MJPEG_COMMON_DEC_Type *)IMAGING__LPCG_DECODE_JPEG_CLK_BASE) /** Array initializer of IMAGING_LPCG_MJPEG_COMMON_DEC peripheral base addresses * */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_BASE_ADDRS { IMAGING__LPCG_DECODE_IPS_CLK_BASE, IMAGING__LPCG_DECODE_JPEG_CLK_BASE } /** Array initializer of IMAGING_LPCG_MJPEG_COMMON_DEC peripheral base pointers * */ #define IMAGING_LPCG_MJPEG_COMMON_DEC_BASE_PTRS { IMAGING__LPCG_DECODE_IPS_CLK, IMAGING__LPCG_DECODE_JPEG_CLK } /*! * @} */ /* end of group IMAGING_LPCG_MJPEG_COMMON_DEC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_MJPEG_COMMON_ENC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_MJPEG_COMMON_ENC_Peripheral_Access_Layer IMAGING_LPCG_MJPEG_COMMON_ENC Peripheral Access Layer * @{ */ /** IMAGING_LPCG_MJPEG_COMMON_ENC - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MJPEG_COMMON_ENC_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_MJPEG_COMMON_ENC_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_MJPEG_COMMON_ENC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_MJPEG_COMMON_ENC_Register_Masks IMAGING_LPCG_MJPEG_COMMON_ENC Register Masks * @{ */ /*! @name LPCG_MJPEG_COMMON_ENC_0 - na */ /*! @{ */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_MASK (0x1U) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_SHIFT (0U) /*! encode_jpeg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_MASK) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_MASK (0x2U) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_SHIFT (1U) /*! encode_jpeg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_MASK) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_SHIFT (2U) /*! LPCG_MJPEG_Common_Enc_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_MASK) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_MASK (0x8U) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_SHIFT (3U) /*! encode_jpeg_clk_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_MASK) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_MASK (0x1FFF0U) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_SHIFT (4U) /*! LPCG_MJPEG_Common_Enc_0_reserved_4_16 - reserved */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_MASK) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_MASK (0x20000U) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_SHIFT (17U) /*! encode_ips_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_MASK) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_MASK (0x40000U) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_SHIFT (18U) /*! LPCG_MJPEG_Common_Enc_0_reserved_18_18 - reserved */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_MASK) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_MASK (0x80000U) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_SHIFT (19U) /*! encode_ips_clk_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_MASK) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_MASK (0xFFF00000U) #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_SHIFT (20U) /*! LPCG_MJPEG_Common_Enc_0_reserved_20_31 - reserved */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_MJPEG_COMMON_ENC_Register_Masks */ /* IMAGING_LPCG_MJPEG_COMMON_ENC - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_ENCODE_IPS_CLK base address */ #define IMAGING__LPCG_ENCODE_IPS_CLK_BASE (0x585F0000u) /** Peripheral IMAGING__LPCG_ENCODE_IPS_CLK base pointer */ #define IMAGING__LPCG_ENCODE_IPS_CLK ((IMAGING_LPCG_MJPEG_COMMON_ENC_Type *)IMAGING__LPCG_ENCODE_IPS_CLK_BASE) /** Peripheral IMAGING__LPCG_ENCODE_JPEG_CLK base address */ #define IMAGING__LPCG_ENCODE_JPEG_CLK_BASE (0x585F0000u) /** Peripheral IMAGING__LPCG_ENCODE_JPEG_CLK base pointer */ #define IMAGING__LPCG_ENCODE_JPEG_CLK ((IMAGING_LPCG_MJPEG_COMMON_ENC_Type *)IMAGING__LPCG_ENCODE_JPEG_CLK_BASE) /** Array initializer of IMAGING_LPCG_MJPEG_COMMON_ENC peripheral base addresses * */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_BASE_ADDRS { IMAGING__LPCG_ENCODE_IPS_CLK_BASE, IMAGING__LPCG_ENCODE_JPEG_CLK_BASE } /** Array initializer of IMAGING_LPCG_MJPEG_COMMON_ENC peripheral base pointers * */ #define IMAGING_LPCG_MJPEG_COMMON_ENC_BASE_PTRS { IMAGING__LPCG_ENCODE_IPS_CLK, IMAGING__LPCG_ENCODE_JPEG_CLK } /*! * @} */ /* end of group IMAGING_LPCG_MJPEG_COMMON_ENC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA0_Peripheral_Access_Layer IMAGING_LPCG_PDMA0 Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PDMA0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PDMA0_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PDMA0_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA0_Register_Masks IMAGING_LPCG_PDMA0 Register Masks * @{ */ /*! @name LPCG_PDMA0_0 - na */ /*! @{ */ #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_MASK (0x1U) #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_SHIFT (0U) /*! isi_ipg_proc_clk_0_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_MASK) #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_MASK (0x2U) #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_SHIFT (1U) /*! isi_ipg_proc_clk_0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_MASK) #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_SHIFT (2U) /*! LPCG_PDMA0_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_MASK) #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_MASK (0x8U) #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_SHIFT (3U) /*! isi_ipg_proc_clk_0_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_MASK) #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_SHIFT (4U) /*! LPCG_PDMA0_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PDMA0_Register_Masks */ /* IMAGING_LPCG_PDMA0 - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PROC_CLK_0 base address */ #define IMAGING__LPCG_PROC_CLK_0_BASE (0x58500000u) /** Peripheral IMAGING__LPCG_PROC_CLK_0 base pointer */ #define IMAGING__LPCG_PROC_CLK_0 ((IMAGING_LPCG_PDMA0_Type *)IMAGING__LPCG_PROC_CLK_0_BASE) /** Array initializer of IMAGING_LPCG_PDMA0 peripheral base addresses */ #define IMAGING_LPCG_PDMA0_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_0_BASE } /** Array initializer of IMAGING_LPCG_PDMA0 peripheral base pointers */ #define IMAGING_LPCG_PDMA0_BASE_PTRS { IMAGING__LPCG_PROC_CLK_0 } /*! * @} */ /* end of group IMAGING_LPCG_PDMA0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA1_Peripheral_Access_Layer IMAGING_LPCG_PDMA1 Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PDMA1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PDMA1_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PDMA1_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA1_Register_Masks IMAGING_LPCG_PDMA1 Register Masks * @{ */ /*! @name LPCG_PDMA1_0 - na */ /*! @{ */ #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_MASK (0x1U) #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_SHIFT (0U) /*! isi_ipg_proc_clk_1_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_MASK) #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_MASK (0x2U) #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_SHIFT (1U) /*! isi_ipg_proc_clk_1_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_MASK) #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_SHIFT (2U) /*! LPCG_PDMA1_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_MASK) #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_MASK (0x8U) #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_SHIFT (3U) /*! isi_ipg_proc_clk_1_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_MASK) #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_SHIFT (4U) /*! LPCG_PDMA1_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PDMA1_Register_Masks */ /* IMAGING_LPCG_PDMA1 - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PROC_CLK_1 base address */ #define IMAGING__LPCG_PROC_CLK_1_BASE (0x58510000u) /** Peripheral IMAGING__LPCG_PROC_CLK_1 base pointer */ #define IMAGING__LPCG_PROC_CLK_1 ((IMAGING_LPCG_PDMA1_Type *)IMAGING__LPCG_PROC_CLK_1_BASE) /** Array initializer of IMAGING_LPCG_PDMA1 peripheral base addresses */ #define IMAGING_LPCG_PDMA1_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_1_BASE } /** Array initializer of IMAGING_LPCG_PDMA1 peripheral base pointers */ #define IMAGING_LPCG_PDMA1_BASE_PTRS { IMAGING__LPCG_PROC_CLK_1 } /*! * @} */ /* end of group IMAGING_LPCG_PDMA1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA2_Peripheral_Access_Layer IMAGING_LPCG_PDMA2 Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PDMA2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PDMA2_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PDMA2_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA2_Register_Masks IMAGING_LPCG_PDMA2 Register Masks * @{ */ /*! @name LPCG_PDMA2_0 - na */ /*! @{ */ #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_MASK (0x1U) #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_SHIFT (0U) /*! isi_ipg_proc_clk_2_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_MASK) #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_MASK (0x2U) #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_SHIFT (1U) /*! isi_ipg_proc_clk_2_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_MASK) #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_SHIFT (2U) /*! LPCG_PDMA2_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_MASK) #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_MASK (0x8U) #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_SHIFT (3U) /*! isi_ipg_proc_clk_2_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_MASK) #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_SHIFT (4U) /*! LPCG_PDMA2_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PDMA2_Register_Masks */ /* IMAGING_LPCG_PDMA2 - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PROC_CLK_2 base address */ #define IMAGING__LPCG_PROC_CLK_2_BASE (0x58520000u) /** Peripheral IMAGING__LPCG_PROC_CLK_2 base pointer */ #define IMAGING__LPCG_PROC_CLK_2 ((IMAGING_LPCG_PDMA2_Type *)IMAGING__LPCG_PROC_CLK_2_BASE) /** Array initializer of IMAGING_LPCG_PDMA2 peripheral base addresses */ #define IMAGING_LPCG_PDMA2_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_2_BASE } /** Array initializer of IMAGING_LPCG_PDMA2 peripheral base pointers */ #define IMAGING_LPCG_PDMA2_BASE_PTRS { IMAGING__LPCG_PROC_CLK_2 } /*! * @} */ /* end of group IMAGING_LPCG_PDMA2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA3_Peripheral_Access_Layer IMAGING_LPCG_PDMA3 Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PDMA3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PDMA3_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PDMA3_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA3_Register_Masks IMAGING_LPCG_PDMA3 Register Masks * @{ */ /*! @name LPCG_PDMA3_0 - na */ /*! @{ */ #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_MASK (0x1U) #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_SHIFT (0U) /*! isi_ipg_proc_clk_3_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_MASK) #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_MASK (0x2U) #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_SHIFT (1U) /*! isi_ipg_proc_clk_3_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_MASK) #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_SHIFT (2U) /*! LPCG_PDMA3_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_MASK) #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_MASK (0x8U) #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_SHIFT (3U) /*! isi_ipg_proc_clk_3_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_MASK) #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_SHIFT (4U) /*! LPCG_PDMA3_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PDMA3_Register_Masks */ /* IMAGING_LPCG_PDMA3 - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PROC_CLK_3 base address */ #define IMAGING__LPCG_PROC_CLK_3_BASE (0x58530000u) /** Peripheral IMAGING__LPCG_PROC_CLK_3 base pointer */ #define IMAGING__LPCG_PROC_CLK_3 ((IMAGING_LPCG_PDMA3_Type *)IMAGING__LPCG_PROC_CLK_3_BASE) /** Array initializer of IMAGING_LPCG_PDMA3 peripheral base addresses */ #define IMAGING_LPCG_PDMA3_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_3_BASE } /** Array initializer of IMAGING_LPCG_PDMA3 peripheral base pointers */ #define IMAGING_LPCG_PDMA3_BASE_PTRS { IMAGING__LPCG_PROC_CLK_3 } /*! * @} */ /* end of group IMAGING_LPCG_PDMA3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA4_Peripheral_Access_Layer IMAGING_LPCG_PDMA4 Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PDMA4 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PDMA4_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PDMA4_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA4_Register_Masks IMAGING_LPCG_PDMA4 Register Masks * @{ */ /*! @name LPCG_PDMA4_0 - na */ /*! @{ */ #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_MASK (0x1U) #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_SHIFT (0U) /*! isi_ipg_proc_clk_4_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_MASK) #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_MASK (0x2U) #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_SHIFT (1U) /*! isi_ipg_proc_clk_4_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_MASK) #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_SHIFT (2U) /*! LPCG_PDMA4_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_MASK) #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_MASK (0x8U) #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_SHIFT (3U) /*! isi_ipg_proc_clk_4_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_MASK) #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_SHIFT (4U) /*! LPCG_PDMA4_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PDMA4_Register_Masks */ /* IMAGING_LPCG_PDMA4 - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PROC_CLK_4 base address */ #define IMAGING__LPCG_PROC_CLK_4_BASE (0x58540000u) /** Peripheral IMAGING__LPCG_PROC_CLK_4 base pointer */ #define IMAGING__LPCG_PROC_CLK_4 ((IMAGING_LPCG_PDMA4_Type *)IMAGING__LPCG_PROC_CLK_4_BASE) /** Array initializer of IMAGING_LPCG_PDMA4 peripheral base addresses */ #define IMAGING_LPCG_PDMA4_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_4_BASE } /** Array initializer of IMAGING_LPCG_PDMA4 peripheral base pointers */ #define IMAGING_LPCG_PDMA4_BASE_PTRS { IMAGING__LPCG_PROC_CLK_4 } /*! * @} */ /* end of group IMAGING_LPCG_PDMA4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA5_Peripheral_Access_Layer IMAGING_LPCG_PDMA5 Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PDMA5 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PDMA5_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PDMA5_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PDMA5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PDMA5_Register_Masks IMAGING_LPCG_PDMA5 Register Masks * @{ */ /*! @name LPCG_PDMA5_0 - na */ /*! @{ */ #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_MASK (0x1U) #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_SHIFT (0U) /*! isi_ipg_proc_clk_5_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_MASK) #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_MASK (0x2U) #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_SHIFT (1U) /*! isi_ipg_proc_clk_5_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_MASK) #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_SHIFT (2U) /*! LPCG_PDMA5_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_MASK) #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_MASK (0x8U) #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_SHIFT (3U) /*! isi_ipg_proc_clk_5_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_MASK) #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_SHIFT (4U) /*! LPCG_PDMA5_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PDMA5_Register_Masks */ /* IMAGING_LPCG_PDMA5 - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PROC_CLK_5 base address */ #define IMAGING__LPCG_PROC_CLK_5_BASE (0x58550000u) /** Peripheral IMAGING__LPCG_PROC_CLK_5 base pointer */ #define IMAGING__LPCG_PROC_CLK_5 ((IMAGING_LPCG_PDMA5_Type *)IMAGING__LPCG_PROC_CLK_5_BASE) /** Array initializer of IMAGING_LPCG_PDMA5 peripheral base addresses */ #define IMAGING_LPCG_PDMA5_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_5_BASE } /** Array initializer of IMAGING_LPCG_PDMA5 peripheral base pointers */ #define IMAGING_LPCG_PDMA5_BASE_PTRS { IMAGING__LPCG_PROC_CLK_5 } /*! * @} */ /* end of group IMAGING_LPCG_PDMA5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PIXEL_LINK_SLAVE_CSI1_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Register Masks * @{ */ /*! @name LPCG_PIXEL_LINK_SLAVE_CSI1_0 - na */ /*! @{ */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_MASK (0x1U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_SHIFT (0U) /*! LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_MASK (0x2U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_SHIFT (1U) /*! pixel_link_slv_csi1_ingress_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_SHIFT (2U) /*! LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_MASK (0x8U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_SHIFT (3U) /*! pixel_link_slv_csi1_ingress_clk_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_SHIFT (4U) /*! LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Register_Masks */ /* IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 base address */ #define IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE (0x58580000u) /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 base pointer */ #define IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 ((IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE) /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 peripheral base * addresses */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE } /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 peripheral base * pointers */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 } /*! * @} */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PIXEL_LINK_SLAVE_CSI2_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Register Masks * @{ */ /*! @name LPCG_PIXEL_LINK_SLAVE_CSI2_0 - na */ /*! @{ */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_MASK (0x1U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_SHIFT (0U) /*! LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_MASK (0x2U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_SHIFT (1U) /*! pixel_link_slv_csi2_ingress_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_SHIFT (2U) /*! LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_MASK (0x8U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_SHIFT (3U) /*! pixel_link_slv_csi2_ingress_clk_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_SHIFT (4U) /*! LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Register_Masks */ /* IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 base address */ #define IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE (0x58590000u) /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 base pointer */ #define IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 ((IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE) /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 peripheral base * addresses */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE } /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 peripheral base * pointers */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 } /*! * @} */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PIXEL_LINK_SLAVE_DC0_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Register Masks * @{ */ /*! @name LPCG_PIXEL_LINK_SLAVE_DC0_0 - na */ /*! @{ */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_MASK (0x1U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_SHIFT (0U) /*! LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_MASK (0x2U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_SHIFT (1U) /*! pixel_link_slv_dc0_ingress_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_SHIFT (2U) /*! LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_MASK (0x8U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_SHIFT (3U) /*! pixel_link_slv_dc0_ingress_clk_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_SHIFT (4U) /*! LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Register_Masks */ /* IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK base address */ #define IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE (0x585C0000u) /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK base pointer */ #define IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE) /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 peripheral base * addresses */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE } /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 peripheral base * pointers */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK } /*! * @} */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PIXEL_LINK_SLAVE_DC1_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Register Masks * @{ */ /*! @name LPCG_PIXEL_LINK_SLAVE_DC1_0 - na */ /*! @{ */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_MASK (0x1U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_SHIFT (0U) /*! LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_MASK (0x2U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_SHIFT (1U) /*! pixel_link_slv_dc1_ingress_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_SHIFT (2U) /*! LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_MASK (0x8U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_SHIFT (3U) /*! pixel_link_slv_dc1_ingress_clk_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_SHIFT (4U) /*! LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Register_Masks */ /* IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK base address */ #define IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE (0x585E0000u) /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK base pointer */ #define IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE) /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 peripheral base * addresses */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE } /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 peripheral base * pointers */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK } /*! * @} */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Peripheral Access Layer * @{ */ /** IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0; /**< na, offset: 0x0 */ } IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Type; /* ---------------------------------------------------------------------------- -- IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Register Masks * @{ */ /*! @name LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0 - na */ /*! @{ */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_MASK (0x1U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_SHIFT (0U) /*! LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_MASK (0x2U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_SHIFT (1U) /*! pixel_link_slv_hdmi_in_ingress_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_MASK (0x4U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_SHIFT (2U) /*! LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_MASK (0x8U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_SHIFT (3U) /*! pixel_link_slv_hdmi_in_ingress_clk_STOP - show clock root status, 1 means clock stopped */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_MASK) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_MASK (0xFFFFFFF0U) #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_SHIFT (4U) /*! LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31 - reserved */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Register_Masks */ /* IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN - Peripheral instance base addresses */ /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK base address */ #define IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE (0x585A0000u) /** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK base pointer */ #define IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE) /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN peripheral base * addresses */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE } /** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN peripheral base * pointers */ #define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK } /*! * @} */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- INTMUX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer * @{ */ /** INTMUX - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x40 */ __IO uint32_t CHn_CSR; /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */ __I uint32_t CHn_VEC; /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */ uint8_t RESERVED_0[8]; __IO uint32_t CHn_IER_31_0; /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */ uint8_t RESERVED_1[12]; __I uint32_t CHn_IPR_31_0; /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */ uint8_t RESERVED_2[28]; } CHANNEL[8]; } INTMUX_Type; /* ---------------------------------------------------------------------------- -- INTMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup INTMUX_Register_Masks INTMUX Register Masks * @{ */ /*! @name CHn_CSR - Channel n Control Status Register */ /*! @{ */ #define INTMUX_CHn_CSR_RST_MASK (0x1U) #define INTMUX_CHn_CSR_RST_SHIFT (0U) /*! RST - Software Reset * 0b0..No operation. * 0b1..Perform a software reset on this channel. */ #define INTMUX_CHn_CSR_RST(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK) #define INTMUX_CHn_CSR_AND_MASK (0x2U) #define INTMUX_CHn_CSR_AND_SHIFT (1U) /*! AND - Logic AND * 0b0..Logic OR all enabled interrupt inputs. * 0b1..Logic AND all enabled interrupt inputs. */ #define INTMUX_CHn_CSR_AND(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK) #define INTMUX_CHn_CSR_IRQN_MASK (0x30U) #define INTMUX_CHn_CSR_IRQN_SHIFT (4U) /*! IRQN - Channel Input Number * 0b00..32 interrupt inputs * 0b01..Reserved * 0b10..Reserved * 0b11..Reserved */ #define INTMUX_CHn_CSR_IRQN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK) #define INTMUX_CHn_CSR_CHIN_MASK (0xF00U) #define INTMUX_CHn_CSR_CHIN_SHIFT (8U) /*! CHIN - Channel Instance Number */ #define INTMUX_CHn_CSR_CHIN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK) #define INTMUX_CHn_CSR_IRQP_MASK (0x80000000U) #define INTMUX_CHn_CSR_IRQP_SHIFT (31U) /*! IRQP - Channel Interrupt Request Pending * 0b0..No interrupt is pending. * 0b1..The interrupt output of this channel is pending. */ #define INTMUX_CHn_CSR_IRQP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK) /*! @} */ /* The count of INTMUX_CHn_CSR */ #define INTMUX_CHn_CSR_COUNT (8U) /*! @name CHn_VEC - Channel n Vector Number Register */ /*! @{ */ #define INTMUX_CHn_VEC_VECN_MASK (0x3FFCU) #define INTMUX_CHn_VEC_VECN_SHIFT (2U) /*! VECN - Vector Number */ #define INTMUX_CHn_VEC_VECN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK) /*! @} */ /* The count of INTMUX_CHn_VEC */ #define INTMUX_CHn_VEC_COUNT (8U) /*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */ /*! @{ */ #define INTMUX_CHn_IER_31_0_INTE_MASK (0xFFFFFFFFU) #define INTMUX_CHn_IER_31_0_INTE_SHIFT (0U) /*! INTE - Interrupt Enable */ #define INTMUX_CHn_IER_31_0_INTE(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK) /*! @} */ /* The count of INTMUX_CHn_IER_31_0 */ #define INTMUX_CHn_IER_31_0_COUNT (8U) /*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */ /*! @{ */ #define INTMUX_CHn_IPR_31_0_INTP_MASK (0xFFFFFFFFU) #define INTMUX_CHn_IPR_31_0_INTP_SHIFT (0U) /*! INTP - Interrupt Pending */ #define INTMUX_CHn_IPR_31_0_INTP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK) /*! @} */ /* The count of INTMUX_CHn_IPR_31_0 */ #define INTMUX_CHn_IPR_31_0_COUNT (8U) /*! * @} */ /* end of group INTMUX_Register_Masks */ /* INTMUX - Peripheral instance base addresses */ /** Peripheral CM4__INTMUX base address */ #define CM4__INTMUX_BASE (0x41400000u) /** Peripheral CM4__INTMUX base pointer */ #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) /** Peripheral SCU__INTMUX base address */ #define SCU__INTMUX_BASE (0x33400000u) /** Peripheral SCU__INTMUX base pointer */ #define SCU__INTMUX ((INTMUX_Type *)SCU__INTMUX_BASE) /** Array initializer of INTMUX peripheral base addresses */ #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE } /** Array initializer of INTMUX peripheral base pointers */ #define INTMUX_BASE_PTRS { CM4__INTMUX, SCU__INTMUX } /*! * @} */ /* end of group INTMUX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IOMUXD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXD_Peripheral_Access_Layer IOMUXD Peripheral Access Layer * @{ */ /** IOMUXD - Register Layout Typedef */ typedef struct { __IO uint32_t PCIE_CTRL0_PERST_B; /**< PCIE_CTRL0_PERST_B, offset: 0x0 */ uint8_t RESERVED_0[60]; __IO uint32_t PCIE_CTRL0_CLKREQ_B; /**< PCIE_CTRL0_CLKREQ_B, offset: 0x40 */ uint8_t RESERVED_1[60]; __IO uint32_t PCIE_CTRL0_WAKE_B; /**< PCIE_CTRL0_WAKE_B, offset: 0x80 */ uint8_t RESERVED_2[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP, offset: 0xC0 */ uint8_t RESERVED_3[60]; __IO uint32_t USB_SS3_TC0; /**< USB_SS3_TC0, offset: 0x100 */ uint8_t RESERVED_4[60]; __IO uint32_t USB_SS3_TC1; /**< USB_SS3_TC1, offset: 0x140 */ uint8_t RESERVED_5[60]; __IO uint32_t USB_SS3_TC2; /**< USB_SS3_TC2, offset: 0x180 */ uint8_t RESERVED_6[60]; __IO uint32_t USB_SS3_TC3; /**< USB_SS3_TC3, offset: 0x1C0 */ uint8_t RESERVED_7[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_3V3_USB3IO; /**< IOMUXD_COMP_CTL_GPIO_3V3_USB3IO, offset: 0x200 */ uint8_t RESERVED_8[508]; __I uint32_t IOMUXD_GROUP_0_0; /**< na, offset: 0x400 */ uint8_t RESERVED_9[130044]; __IO uint32_t EMMC0_CLK; /**< EMMC0_CLK, offset: 0x20000 */ uint8_t RESERVED_10[60]; __IO uint32_t EMMC0_CMD; /**< EMMC0_CMD, offset: 0x20040 */ uint8_t RESERVED_11[60]; __IO uint32_t EMMC0_DATA0; /**< EMMC0_DATA0, offset: 0x20080 */ uint8_t RESERVED_12[60]; __IO uint32_t EMMC0_DATA1; /**< EMMC0_DATA1, offset: 0x200C0 */ uint8_t RESERVED_13[60]; __IO uint32_t EMMC0_DATA2; /**< EMMC0_DATA2, offset: 0x20100 */ uint8_t RESERVED_14[60]; __IO uint32_t EMMC0_DATA3; /**< EMMC0_DATA3, offset: 0x20140 */ uint8_t RESERVED_15[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0, offset: 0x20180 */ uint8_t RESERVED_16[60]; __IO uint32_t EMMC0_DATA4; /**< EMMC0_DATA4, offset: 0x201C0 */ uint8_t RESERVED_17[60]; __IO uint32_t EMMC0_DATA5; /**< EMMC0_DATA5, offset: 0x20200 */ uint8_t RESERVED_18[60]; __IO uint32_t EMMC0_DATA6; /**< EMMC0_DATA6, offset: 0x20240 */ uint8_t RESERVED_19[60]; __IO uint32_t EMMC0_DATA7; /**< EMMC0_DATA7, offset: 0x20280 */ uint8_t RESERVED_20[60]; __IO uint32_t EMMC0_STROBE; /**< EMMC0_STROBE, offset: 0x202C0 */ uint8_t RESERVED_21[60]; __IO uint32_t EMMC0_RESET_B; /**< EMMC0_RESET_B, offset: 0x20300 */ uint8_t RESERVED_22[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1, offset: 0x20340 */ uint8_t RESERVED_23[60]; __IO uint32_t USDHC1_RESET_B; /**< USDHC1_RESET_B, offset: 0x20380 */ uint8_t RESERVED_24[124]; __I uint32_t IOMUXD_GROUP_1_0; /**< na, offset: 0x20400 */ uint8_t RESERVED_25[3068]; __IO uint32_t USDHC1_VSELECT; /**< USDHC1_VSELECT, offset: 0x21000 */ uint8_t RESERVED_26[60]; __IO uint32_t IOMUXD_CTL_NAND_RE_P_N; /**< IOMUXD_CTL_NAND_RE_P_N, offset: 0x21040 */ uint8_t RESERVED_27[60]; __IO uint32_t USDHC1_WP; /**< USDHC1_WP, offset: 0x21080 */ uint8_t RESERVED_28[60]; __IO uint32_t USDHC1_CD_B; /**< USDHC1_CD_B, offset: 0x210C0 */ uint8_t RESERVED_29[60]; __IO uint32_t IOMUXD_CTL_NAND_DQS_P_N; /**< IOMUXD_CTL_NAND_DQS_P_N, offset: 0x21100 */ uint8_t RESERVED_30[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP, offset: 0x21140 */ uint8_t RESERVED_31[60]; __IO uint32_t USDHC1_CLK; /**< USDHC1_CLK, offset: 0x21180 */ uint8_t RESERVED_32[60]; __IO uint32_t USDHC1_CMD; /**< USDHC1_CMD, offset: 0x211C0 */ uint8_t RESERVED_33[60]; __IO uint32_t USDHC1_DATA0; /**< USDHC1_DATA0, offset: 0x21200 */ uint8_t RESERVED_34[60]; __IO uint32_t USDHC1_DATA1; /**< USDHC1_DATA1, offset: 0x21240 */ uint8_t RESERVED_35[60]; __IO uint32_t USDHC1_DATA2; /**< USDHC1_DATA2, offset: 0x21280 */ uint8_t RESERVED_36[60]; __IO uint32_t USDHC1_DATA3; /**< USDHC1_DATA3, offset: 0x212C0 */ uint8_t RESERVED_37[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3, offset: 0x21300 */ uint8_t RESERVED_38[60]; __IO uint32_t ENET0_RGMII_TXC; /**< ENET0_RGMII_TXC, offset: 0x21340 */ uint8_t RESERVED_39[60]; __IO uint32_t ENET0_RGMII_TX_CTL; /**< ENET0_RGMII_TX_CTL, offset: 0x21380 */ uint8_t RESERVED_40[124]; __I uint32_t IOMUXD_GROUP_1_1; /**< na, offset: 0x21400 */ uint8_t RESERVED_41[3068]; __IO uint32_t ENET0_RGMII_TXD0; /**< ENET0_RGMII_TXD0, offset: 0x22000 */ uint8_t RESERVED_42[60]; __IO uint32_t ENET0_RGMII_TXD1; /**< ENET0_RGMII_TXD1, offset: 0x22040 */ uint8_t RESERVED_43[60]; __IO uint32_t ENET0_RGMII_TXD2; /**< ENET0_RGMII_TXD2, offset: 0x22080 */ uint8_t RESERVED_44[60]; __IO uint32_t ENET0_RGMII_TXD3; /**< ENET0_RGMII_TXD3, offset: 0x220C0 */ uint8_t RESERVED_45[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0, offset: 0x22100 */ uint8_t RESERVED_46[60]; __IO uint32_t ENET0_RGMII_RXC; /**< ENET0_RGMII_RXC, offset: 0x22140 */ uint8_t RESERVED_47[60]; __IO uint32_t ENET0_RGMII_RX_CTL; /**< ENET0_RGMII_RX_CTL, offset: 0x22180 */ uint8_t RESERVED_48[60]; __IO uint32_t ENET0_RGMII_RXD0; /**< ENET0_RGMII_RXD0, offset: 0x221C0 */ uint8_t RESERVED_49[60]; __IO uint32_t ENET0_RGMII_RXD1; /**< ENET0_RGMII_RXD1, offset: 0x22200 */ uint8_t RESERVED_50[60]; __IO uint32_t ENET0_RGMII_RXD2; /**< ENET0_RGMII_RXD2, offset: 0x22240 */ uint8_t RESERVED_51[60]; __IO uint32_t ENET0_RGMII_RXD3; /**< ENET0_RGMII_RXD3, offset: 0x22280 */ uint8_t RESERVED_52[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1, offset: 0x222C0 */ uint8_t RESERVED_53[60]; __IO uint32_t ENET0_REFCLK_125M_25M; /**< ENET0_REFCLK_125M_25M, offset: 0x22300 */ uint8_t RESERVED_54[252]; __I uint32_t IOMUXD_GROUP_1_2; /**< na, offset: 0x22400 */ uint8_t RESERVED_55[3068]; __IO uint32_t ENET0_MDIO; /**< ENET0_MDIO, offset: 0x23000 */ uint8_t RESERVED_56[60]; __IO uint32_t ENET0_MDC; /**< ENET0_MDC, offset: 0x23040 */ uint8_t RESERVED_57[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT, offset: 0x23080 */ uint8_t RESERVED_58[60]; __IO uint32_t ESAI0_FSR; /**< ESAI0_FSR, offset: 0x230C0 */ uint8_t RESERVED_59[60]; __IO uint32_t ESAI0_FST; /**< ESAI0_FST, offset: 0x23100 */ uint8_t RESERVED_60[60]; __IO uint32_t ESAI0_SCKR; /**< ESAI0_SCKR, offset: 0x23140 */ uint8_t RESERVED_61[60]; __IO uint32_t ESAI0_SCKT; /**< ESAI0_SCKT, offset: 0x23180 */ uint8_t RESERVED_62[60]; __IO uint32_t ESAI0_TX0; /**< ESAI0_TX0, offset: 0x231C0 */ uint8_t RESERVED_63[60]; __IO uint32_t ESAI0_TX1; /**< ESAI0_TX1, offset: 0x23200 */ uint8_t RESERVED_64[60]; __IO uint32_t ESAI0_TX2_RX3; /**< ESAI0_TX2_RX3, offset: 0x23240 */ uint8_t RESERVED_65[60]; __IO uint32_t ESAI0_TX3_RX2; /**< ESAI0_TX3_RX2, offset: 0x23280 */ uint8_t RESERVED_66[60]; __IO uint32_t ESAI0_TX4_RX1; /**< ESAI0_TX4_RX1, offset: 0x232C0 */ uint8_t RESERVED_67[60]; __IO uint32_t ESAI0_TX5_RX0; /**< ESAI0_TX5_RX0, offset: 0x23300 */ uint8_t RESERVED_68[60]; __IO uint32_t SPDIF0_RX; /**< SPDIF0_RX, offset: 0x23340 */ uint8_t RESERVED_69[60]; __IO uint32_t SPDIF0_TX; /**< SPDIF0_TX, offset: 0x23380 */ uint8_t RESERVED_70[124]; __I uint32_t IOMUXD_GROUP_1_3; /**< na, offset: 0x23400 */ uint8_t RESERVED_71[3068]; __IO uint32_t SPDIF0_EXT_CLK; /**< SPDIF0_EXT_CLK, offset: 0x24000 */ uint8_t RESERVED_72[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB, offset: 0x24040 */ uint8_t RESERVED_73[60]; __IO uint32_t SPI3_SCK; /**< SPI3_SCK, offset: 0x24080 */ uint8_t RESERVED_74[60]; __IO uint32_t SPI3_SDO; /**< SPI3_SDO, offset: 0x240C0 */ uint8_t RESERVED_75[60]; __IO uint32_t SPI3_SDI; /**< SPI3_SDI, offset: 0x24100 */ uint8_t RESERVED_76[60]; __IO uint32_t SPI3_CS0; /**< SPI3_CS0, offset: 0x24140 */ uint8_t RESERVED_77[60]; __IO uint32_t SPI3_CS1; /**< SPI3_CS1, offset: 0x24180 */ uint8_t RESERVED_78[60]; __IO uint32_t MCLK_IN1; /**< MCLK_IN1, offset: 0x241C0 */ uint8_t RESERVED_79[60]; __IO uint32_t MCLK_IN0; /**< MCLK_IN0, offset: 0x24200 */ uint8_t RESERVED_80[60]; __IO uint32_t MCLK_OUT0; /**< MCLK_OUT0, offset: 0x24240 */ uint8_t RESERVED_81[60]; __IO uint32_t UART1_TX; /**< UART1_TX, offset: 0x24280 */ uint8_t RESERVED_82[60]; __IO uint32_t UART1_RX; /**< UART1_RX, offset: 0x242C0 */ uint8_t RESERVED_83[60]; __IO uint32_t UART1_RTS_B; /**< UART1_RTS_B, offset: 0x24300 */ uint8_t RESERVED_84[60]; __IO uint32_t UART1_CTS_B; /**< UART1_CTS_B, offset: 0x24340 */ uint8_t RESERVED_85[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK, offset: 0x24380 */ uint8_t RESERVED_86[124]; __I uint32_t IOMUXD_GROUP_1_4; /**< na, offset: 0x24400 */ uint8_t RESERVED_87[113660]; __IO uint32_t SAI0_TXD; /**< SAI0_TXD, offset: 0x40000 */ uint8_t RESERVED_88[60]; __IO uint32_t SAI0_TXC; /**< SAI0_TXC, offset: 0x40040 */ uint8_t RESERVED_89[60]; __IO uint32_t SAI0_RXD; /**< SAI0_RXD, offset: 0x40080 */ uint8_t RESERVED_90[60]; __IO uint32_t SAI0_TXFS; /**< SAI0_TXFS, offset: 0x400C0 */ uint8_t RESERVED_91[60]; __IO uint32_t SAI1_RXD; /**< SAI1_RXD, offset: 0x40100 */ uint8_t RESERVED_92[60]; __IO uint32_t SAI1_RXC; /**< SAI1_RXC, offset: 0x40140 */ uint8_t RESERVED_93[60]; __IO uint32_t SAI1_RXFS; /**< SAI1_RXFS, offset: 0x40180 */ uint8_t RESERVED_94[60]; __IO uint32_t SPI2_CS0; /**< SPI2_CS0, offset: 0x401C0 */ uint8_t RESERVED_95[60]; __IO uint32_t SPI2_SDO; /**< SPI2_SDO, offset: 0x40200 */ uint8_t RESERVED_96[60]; __IO uint32_t SPI2_SDI; /**< SPI2_SDI, offset: 0x40240 */ uint8_t RESERVED_97[60]; __IO uint32_t SPI2_SCK; /**< SPI2_SCK, offset: 0x40280 */ uint8_t RESERVED_98[60]; __IO uint32_t SPI0_SCK; /**< SPI0_SCK, offset: 0x402C0 */ uint8_t RESERVED_99[60]; __IO uint32_t SPI0_SDI; /**< SPI0_SDI, offset: 0x40300 */ uint8_t RESERVED_100[60]; __IO uint32_t SPI0_SDO; /**< SPI0_SDO, offset: 0x40340 */ uint8_t RESERVED_101[60]; __IO uint32_t SPI0_CS1; /**< SPI0_CS1, offset: 0x40380 */ uint8_t RESERVED_102[124]; __I uint32_t IOMUXD_GROUP_2_0; /**< na, offset: 0x40400 */ uint8_t RESERVED_103[3068]; __IO uint32_t SPI0_CS0; /**< SPI0_CS0, offset: 0x41000 */ uint8_t RESERVED_104[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT, offset: 0x41040 */ uint8_t RESERVED_105[60]; __IO uint32_t ADC_IN1; /**< ADC_IN1, offset: 0x41080 */ uint8_t RESERVED_106[60]; __IO uint32_t ADC_IN0; /**< ADC_IN0, offset: 0x410C0 */ uint8_t RESERVED_107[60]; __IO uint32_t ADC_IN3; /**< ADC_IN3, offset: 0x41100 */ uint8_t RESERVED_108[60]; __IO uint32_t ADC_IN2; /**< ADC_IN2, offset: 0x41140 */ uint8_t RESERVED_109[60]; __IO uint32_t ADC_IN5; /**< ADC_IN5, offset: 0x41180 */ uint8_t RESERVED_110[60]; __IO uint32_t ADC_IN4; /**< ADC_IN4, offset: 0x411C0 */ uint8_t RESERVED_111[60]; __IO uint32_t FLEXCAN0_RX; /**< FLEXCAN0_RX, offset: 0x41200 */ uint8_t RESERVED_112[60]; __IO uint32_t FLEXCAN0_TX; /**< FLEXCAN0_TX, offset: 0x41240 */ uint8_t RESERVED_113[60]; __IO uint32_t FLEXCAN1_RX; /**< FLEXCAN1_RX, offset: 0x41280 */ uint8_t RESERVED_114[60]; __IO uint32_t FLEXCAN1_TX; /**< FLEXCAN1_TX, offset: 0x412C0 */ uint8_t RESERVED_115[60]; __IO uint32_t FLEXCAN2_RX; /**< FLEXCAN2_RX, offset: 0x41300 */ uint8_t RESERVED_116[60]; __IO uint32_t FLEXCAN2_TX; /**< FLEXCAN2_TX, offset: 0x41340 */ uint8_t RESERVED_117[60]; __IO uint32_t UART0_RX; /**< UART0_RX, offset: 0x41380 */ uint8_t RESERVED_118[124]; __I uint32_t IOMUXD_GROUP_2_1; /**< na, offset: 0x41400 */ uint8_t RESERVED_119[3068]; __IO uint32_t UART0_TX; /**< UART0_TX, offset: 0x42000 */ uint8_t RESERVED_120[60]; __IO uint32_t UART2_TX; /**< UART2_TX, offset: 0x42040 */ uint8_t RESERVED_121[60]; __IO uint32_t UART2_RX; /**< UART2_RX, offset: 0x42080 */ uint8_t RESERVED_122[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH, offset: 0x420C0 */ uint8_t RESERVED_123[60]; __IO uint32_t MIPI_DSI0_I2C0_SCL; /**< MIPI_DSI0_I2C0_SCL, offset: 0x42100 */ uint8_t RESERVED_124[60]; __IO uint32_t MIPI_DSI0_I2C0_SDA; /**< MIPI_DSI0_I2C0_SDA, offset: 0x42140 */ uint8_t RESERVED_125[60]; __IO uint32_t MIPI_DSI0_GPIO0_00; /**< MIPI_DSI0_GPIO0_00, offset: 0x42180 */ uint8_t RESERVED_126[60]; __IO uint32_t MIPI_DSI0_GPIO0_01; /**< MIPI_DSI0_GPIO0_01, offset: 0x421C0 */ uint8_t RESERVED_127[60]; __IO uint32_t MIPI_DSI1_I2C0_SCL; /**< MIPI_DSI1_I2C0_SCL, offset: 0x42200 */ uint8_t RESERVED_128[60]; __IO uint32_t MIPI_DSI1_I2C0_SDA; /**< MIPI_DSI1_I2C0_SDA, offset: 0x42240 */ uint8_t RESERVED_129[60]; __IO uint32_t MIPI_DSI1_GPIO0_00; /**< MIPI_DSI1_GPIO0_00, offset: 0x42280 */ uint8_t RESERVED_130[60]; __IO uint32_t MIPI_DSI1_GPIO0_01; /**< MIPI_DSI1_GPIO0_01, offset: 0x422C0 */ uint8_t RESERVED_131[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO, offset: 0x42300 */ uint8_t RESERVED_132[60]; __IO uint32_t SCU_WDOG_OUT; /**< SCU_WDOG_OUT, offset: 0x42340 */ uint8_t RESERVED_133[60]; __IO uint32_t PMIC_I2C_SCL; /**< PMIC_I2C_SCL, offset: 0x42380 */ uint8_t RESERVED_134[124]; __I uint32_t IOMUXD_GROUP_2_2; /**< na, offset: 0x42400 */ uint8_t RESERVED_135[3068]; __IO uint32_t PMIC_I2C_SDA; /**< PMIC_I2C_SDA, offset: 0x43000 */ uint8_t RESERVED_136[60]; __IO uint32_t PMIC_INT_B; /**< PMIC_INT_B, offset: 0x43040 */ uint8_t RESERVED_137[60]; __IO uint32_t SCU_GPIO0_00; /**< SCU_GPIO0_00, offset: 0x43080 */ uint8_t RESERVED_138[60]; __IO uint32_t SCU_GPIO0_01; /**< SCU_GPIO0_01, offset: 0x430C0 */ uint8_t RESERVED_139[60]; __IO uint32_t SCU_PMIC_STANDBY; /**< SCU_PMIC_STANDBY, offset: 0x43100 */ uint8_t RESERVED_140[60]; __IO uint32_t SCU_BOOT_MODE0; /**< SCU_BOOT_MODE0, offset: 0x43140 */ uint8_t RESERVED_141[60]; __IO uint32_t SCU_BOOT_MODE1; /**< SCU_BOOT_MODE1, offset: 0x43180 */ uint8_t RESERVED_142[60]; __IO uint32_t SCU_BOOT_MODE2; /**< SCU_BOOT_MODE2, offset: 0x431C0 */ uint8_t RESERVED_143[60]; __IO uint32_t SCU_BOOT_MODE3; /**< SCU_BOOT_MODE3, offset: 0x43200 */ uint8_t RESERVED_144[60]; __IO uint32_t CSI_DIG_D00; /**< CSI_DIG_D00, offset: 0x43240 */ uint8_t RESERVED_145[60]; __IO uint32_t CSI_DIG_D01; /**< CSI_DIG_D01, offset: 0x43280 */ uint8_t RESERVED_146[60]; __IO uint32_t CSI_DIG_D02; /**< CSI_DIG_D02, offset: 0x432C0 */ uint8_t RESERVED_147[60]; __IO uint32_t CSI_DIG_D03; /**< CSI_DIG_D03, offset: 0x43300 */ uint8_t RESERVED_148[60]; __IO uint32_t CSI_DIG_D04; /**< CSI_DIG_D04, offset: 0x43340 */ uint8_t RESERVED_149[60]; __IO uint32_t CSI_DIG_D05; /**< CSI_DIG_D05, offset: 0x43380 */ uint8_t RESERVED_150[124]; __I uint32_t IOMUXD_GROUP_2_3; /**< na, offset: 0x43400 */ uint8_t RESERVED_151[3068]; __IO uint32_t CSI_DIG_D06; /**< CSI_DIG_D06, offset: 0x44000 */ uint8_t RESERVED_152[60]; __IO uint32_t CSI_DIG_D07; /**< CSI_DIG_D07, offset: 0x44040 */ uint8_t RESERVED_153[60]; __IO uint32_t CSI_DIG_HSYNC; /**< CSI_DIG_HSYNC, offset: 0x44080 */ uint8_t RESERVED_154[60]; __IO uint32_t CSI_DIG_VSYNC; /**< CSI_DIG_VSYNC, offset: 0x440C0 */ uint8_t RESERVED_155[60]; __IO uint32_t CSI_PCLK; /**< CSI_PCLK, offset: 0x44100 */ uint8_t RESERVED_156[60]; __IO uint32_t CSI_MCLK; /**< CSI_MCLK, offset: 0x44140 */ uint8_t RESERVED_157[60]; __IO uint32_t CSI_EN; /**< CSI_EN, offset: 0x44180 */ uint8_t RESERVED_158[60]; __IO uint32_t CSI_RESET; /**< CSI_RESET, offset: 0x441C0 */ uint8_t RESERVED_159[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD, offset: 0x44200 */ uint8_t RESERVED_160[60]; __IO uint32_t MIPI_CSI0_MCLK_OUT; /**< MIPI_CSI0_MCLK_OUT, offset: 0x44240 */ uint8_t RESERVED_161[60]; __IO uint32_t MIPI_CSI0_I2C0_SCL; /**< MIPI_CSI0_I2C0_SCL, offset: 0x44280 */ uint8_t RESERVED_162[60]; __IO uint32_t MIPI_CSI0_I2C0_SDA; /**< MIPI_CSI0_I2C0_SDA, offset: 0x442C0 */ uint8_t RESERVED_163[60]; __IO uint32_t MIPI_CSI0_GPIO0_01; /**< MIPI_CSI0_GPIO0_01, offset: 0x44300 */ uint8_t RESERVED_164[60]; __IO uint32_t MIPI_CSI0_GPIO0_00; /**< MIPI_CSI0_GPIO0_00, offset: 0x44340 */ uint8_t RESERVED_165[188]; __I uint32_t IOMUXD_GROUP_2_4; /**< na, offset: 0x44400 */ uint8_t RESERVED_166[113660]; __IO uint32_t QSPI0A_DATA0; /**< QSPI0A_DATA0, offset: 0x60000 */ uint8_t RESERVED_167[60]; __IO uint32_t QSPI0A_DATA1; /**< QSPI0A_DATA1, offset: 0x60040 */ uint8_t RESERVED_168[60]; __IO uint32_t QSPI0A_DATA2; /**< QSPI0A_DATA2, offset: 0x60080 */ uint8_t RESERVED_169[60]; __IO uint32_t QSPI0A_DATA3; /**< QSPI0A_DATA3, offset: 0x600C0 */ uint8_t RESERVED_170[60]; __IO uint32_t QSPI0A_DQS; /**< QSPI0A_DQS, offset: 0x60100 */ uint8_t RESERVED_171[60]; __IO uint32_t QSPI0A_SS0_B; /**< QSPI0A_SS0_B, offset: 0x60140 */ uint8_t RESERVED_172[60]; __IO uint32_t QSPI0A_SS1_B; /**< QSPI0A_SS1_B, offset: 0x60180 */ uint8_t RESERVED_173[60]; __IO uint32_t QSPI0A_SCLK; /**< QSPI0A_SCLK, offset: 0x601C0 */ uint8_t RESERVED_174[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A, offset: 0x60200 */ uint8_t RESERVED_175[60]; __IO uint32_t QSPI0B_SCLK; /**< QSPI0B_SCLK, offset: 0x60240 */ uint8_t RESERVED_176[60]; __IO uint32_t QSPI0B_DATA0; /**< QSPI0B_DATA0, offset: 0x60280 */ uint8_t RESERVED_177[60]; __IO uint32_t QSPI0B_DATA1; /**< QSPI0B_DATA1, offset: 0x602C0 */ uint8_t RESERVED_178[60]; __IO uint32_t QSPI0B_DATA2; /**< QSPI0B_DATA2, offset: 0x60300 */ uint8_t RESERVED_179[60]; __IO uint32_t QSPI0B_DATA3; /**< QSPI0B_DATA3, offset: 0x60340 */ uint8_t RESERVED_180[60]; __IO uint32_t QSPI0B_DQS; /**< QSPI0B_DQS, offset: 0x60380 */ uint8_t RESERVED_181[124]; __I uint32_t IOMUXD_GROUP_3_0; /**< na, offset: 0x60400 */ uint8_t RESERVED_182[3068]; __IO uint32_t QSPI0B_SS0_B; /**< QSPI0B_SS0_B, offset: 0x61000 */ uint8_t RESERVED_183[60]; __IO uint32_t QSPI0B_SS1_B; /**< QSPI0B_SS1_B, offset: 0x61040 */ uint8_t RESERVED_184[60]; __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B, offset: 0x61080 */ uint8_t RESERVED_185[892]; __I uint32_t IOMUXD_GROUP_3_1; /**< na, offset: 0x61400 */ } IOMUXD_Type; /* ---------------------------------------------------------------------------- -- IOMUXD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXD_Register_Masks IOMUXD Register Masks * @{ */ /*! @name PCIE_CTRL0_PERST_B - PCIE_CTRL0_PERST_B */ /*! @{ */ #define IOMUXD_PCIE_CTRL0_PERST_B_PDRV_MASK (0x1U) #define IOMUXD_PCIE_CTRL0_PERST_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_PCIE_CTRL0_PERST_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PDRV_MASK) #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_SHIFT (1U) /*! PCIE_CTRL0_PERST_B_reserved_1_4 - reserved */ #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_MASK) #define IOMUXD_PCIE_CTRL0_PERST_B_PULL_MASK (0x60U) #define IOMUXD_PCIE_CTRL0_PERST_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_PCIE_CTRL0_PERST_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PULL_MASK) #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_SHIFT (7U) /*! PCIE_CTRL0_PERST_B_reserved_7_18 - reserved */ #define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_MASK) #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_MASK) #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_MASK) #define IOMUXD_PCIE_CTRL0_PERST_B_lp_config_MASK (0x1800000U) #define IOMUXD_PCIE_CTRL0_PERST_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_PCIE_CTRL0_PERST_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_lp_config_MASK) #define IOMUXD_PCIE_CTRL0_PERST_B_sw_config_MASK (0x6000000U) #define IOMUXD_PCIE_CTRL0_PERST_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_PCIE_CTRL0_PERST_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_sw_config_MASK) #define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_MASK (0x38000000U) #define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..HSIO.PCIE0.PERST_B * 0b100..LSIO.GPIO4.IO00 */ #define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_MASK) #define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_MASK) #define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_MASK) /*! @} */ /*! @name PCIE_CTRL0_CLKREQ_B - PCIE_CTRL0_CLKREQ_B */ /*! @{ */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_MASK (0x1U) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_MASK) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_SHIFT (1U) /*! PCIE_CTRL0_CLKREQ_B_reserved_1_4 - reserved */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_MASK) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_MASK (0x60U) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_MASK) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_SHIFT (7U) /*! PCIE_CTRL0_CLKREQ_B_reserved_7_18 - reserved */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_MASK) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_MASK) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_MASK) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_MASK (0x1800000U) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_MASK) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_MASK (0x6000000U) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_MASK) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_MASK (0x38000000U) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..HSIO.PCIE0.CLKREQ_B * 0b100..LSIO.GPIO4.IO01 */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_MASK) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_MASK) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_MASK) /*! @} */ /*! @name PCIE_CTRL0_WAKE_B - PCIE_CTRL0_WAKE_B */ /*! @{ */ #define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_MASK (0x1U) #define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_MASK) #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_SHIFT (1U) /*! PCIE_CTRL0_WAKE_B_reserved_1_4 - reserved */ #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_MASK) #define IOMUXD_PCIE_CTRL0_WAKE_B_PULL_MASK (0x60U) #define IOMUXD_PCIE_CTRL0_WAKE_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_PCIE_CTRL0_WAKE_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PULL_MASK) #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_SHIFT (7U) /*! PCIE_CTRL0_WAKE_B_reserved_7_18 - reserved */ #define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_MASK) #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_MASK) #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_MASK) #define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_MASK (0x1800000U) #define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_MASK) #define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_MASK (0x6000000U) #define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_MASK) #define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_MASK (0x38000000U) #define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..HSIO.PCIE0.WAKE_B * 0b100..LSIO.GPIO4.IO02 */ #define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_MASK) #define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_MASK) #define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP - IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_MASK) /*! @} */ /*! @name USB_SS3_TC0 - USB_SS3_TC0 */ /*! @{ */ #define IOMUXD_USB_SS3_TC0_DSE_MASK (0x3U) #define IOMUXD_USB_SS3_TC0_DSE_SHIFT (0U) /*! DSE - Drive * 0b00..Drive select 2mA * 0b11..Drive select 12mA * 0b01..Drive select 4mA * 0b10..Drive select 8mA */ #define IOMUXD_USB_SS3_TC0_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_DSE_SHIFT)) & IOMUXD_USB_SS3_TC0_DSE_MASK) #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_MASK (0x1CU) #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_SHIFT (2U) /*! USB_SS3_TC0_reserved_2_4 - reserved */ #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_MASK) #define IOMUXD_USB_SS3_TC0_PULL_MASK (0x60U) #define IOMUXD_USB_SS3_TC0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_USB_SS3_TC0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_PULL_SHIFT)) & IOMUXD_USB_SS3_TC0_PULL_MASK) #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_SHIFT (7U) /*! USB_SS3_TC0_reserved_7_18 - reserved */ #define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_MASK) #define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_MASK) #define IOMUXD_USB_SS3_TC0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USB_SS3_TC0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USB_SS3_TC0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC0_WAKEUP_MASK_MASK) #define IOMUXD_USB_SS3_TC0_lp_config_MASK (0x1800000U) #define IOMUXD_USB_SS3_TC0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USB_SS3_TC0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC0_lp_config_MASK) #define IOMUXD_USB_SS3_TC0_sw_config_MASK (0x6000000U) #define IOMUXD_USB_SS3_TC0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USB_SS3_TC0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC0_sw_config_MASK) #define IOMUXD_USB_SS3_TC0_mux_mode_MASK (0x38000000U) #define IOMUXD_USB_SS3_TC0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.I2C1.SCL * 0b001..CONN.USB_OTG1.PWR * 0b010..CONN.USB_OTG2.PWR * 0b100..LSIO.GPIO4.IO03 */ #define IOMUXD_USB_SS3_TC0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC0_mux_mode_MASK) #define IOMUXD_USB_SS3_TC0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USB_SS3_TC0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USB_SS3_TC0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC0_update_pad_ctl_MASK) #define IOMUXD_USB_SS3_TC0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USB_SS3_TC0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USB_SS3_TC0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC0_update_mux_mode_MASK) /*! @} */ /*! @name USB_SS3_TC1 - USB_SS3_TC1 */ /*! @{ */ #define IOMUXD_USB_SS3_TC1_DSE_MASK (0x3U) #define IOMUXD_USB_SS3_TC1_DSE_SHIFT (0U) /*! DSE - Drive * 0b00..Drive select 2mA * 0b11..Drive select 12mA * 0b01..Drive select 4mA * 0b10..Drive select 8mA */ #define IOMUXD_USB_SS3_TC1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_DSE_SHIFT)) & IOMUXD_USB_SS3_TC1_DSE_MASK) #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_MASK (0x1CU) #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_SHIFT (2U) /*! USB_SS3_TC1_reserved_2_4 - reserved */ #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_MASK) #define IOMUXD_USB_SS3_TC1_PULL_MASK (0x60U) #define IOMUXD_USB_SS3_TC1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_USB_SS3_TC1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_PULL_SHIFT)) & IOMUXD_USB_SS3_TC1_PULL_MASK) #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_SHIFT (7U) /*! USB_SS3_TC1_reserved_7_18 - reserved */ #define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_MASK) #define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_MASK) #define IOMUXD_USB_SS3_TC1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USB_SS3_TC1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USB_SS3_TC1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC1_WAKEUP_MASK_MASK) #define IOMUXD_USB_SS3_TC1_lp_config_MASK (0x1800000U) #define IOMUXD_USB_SS3_TC1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USB_SS3_TC1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC1_lp_config_MASK) #define IOMUXD_USB_SS3_TC1_sw_config_MASK (0x6000000U) #define IOMUXD_USB_SS3_TC1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USB_SS3_TC1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC1_sw_config_MASK) #define IOMUXD_USB_SS3_TC1_mux_mode_MASK (0x38000000U) #define IOMUXD_USB_SS3_TC1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.I2C1.SCL * 0b001..CONN.USB_OTG2.PWR * 0b100..LSIO.GPIO4.IO04 */ #define IOMUXD_USB_SS3_TC1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC1_mux_mode_MASK) #define IOMUXD_USB_SS3_TC1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USB_SS3_TC1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USB_SS3_TC1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC1_update_pad_ctl_MASK) #define IOMUXD_USB_SS3_TC1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USB_SS3_TC1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USB_SS3_TC1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC1_update_mux_mode_MASK) /*! @} */ /*! @name USB_SS3_TC2 - USB_SS3_TC2 */ /*! @{ */ #define IOMUXD_USB_SS3_TC2_DSE_MASK (0x3U) #define IOMUXD_USB_SS3_TC2_DSE_SHIFT (0U) /*! DSE - Drive * 0b00..Drive select 2mA * 0b11..Drive select 12mA * 0b01..Drive select 4mA * 0b10..Drive select 8mA */ #define IOMUXD_USB_SS3_TC2_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_DSE_SHIFT)) & IOMUXD_USB_SS3_TC2_DSE_MASK) #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_MASK (0x1CU) #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_SHIFT (2U) /*! USB_SS3_TC2_reserved_2_4 - reserved */ #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_MASK) #define IOMUXD_USB_SS3_TC2_PULL_MASK (0x60U) #define IOMUXD_USB_SS3_TC2_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_USB_SS3_TC2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_PULL_SHIFT)) & IOMUXD_USB_SS3_TC2_PULL_MASK) #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_SHIFT (7U) /*! USB_SS3_TC2_reserved_7_18 - reserved */ #define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_MASK) #define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_MASK) #define IOMUXD_USB_SS3_TC2_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USB_SS3_TC2_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USB_SS3_TC2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC2_WAKEUP_MASK_MASK) #define IOMUXD_USB_SS3_TC2_lp_config_MASK (0x1800000U) #define IOMUXD_USB_SS3_TC2_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USB_SS3_TC2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC2_lp_config_MASK) #define IOMUXD_USB_SS3_TC2_sw_config_MASK (0x6000000U) #define IOMUXD_USB_SS3_TC2_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USB_SS3_TC2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC2_sw_config_MASK) #define IOMUXD_USB_SS3_TC2_mux_mode_MASK (0x38000000U) #define IOMUXD_USB_SS3_TC2_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.I2C1.SDA * 0b001..CONN.USB_OTG1.OC * 0b010..CONN.USB_OTG2.OC * 0b100..LSIO.GPIO4.IO05 */ #define IOMUXD_USB_SS3_TC2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC2_mux_mode_MASK) #define IOMUXD_USB_SS3_TC2_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USB_SS3_TC2_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USB_SS3_TC2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC2_update_pad_ctl_MASK) #define IOMUXD_USB_SS3_TC2_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USB_SS3_TC2_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USB_SS3_TC2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC2_update_mux_mode_MASK) /*! @} */ /*! @name USB_SS3_TC3 - USB_SS3_TC3 */ /*! @{ */ #define IOMUXD_USB_SS3_TC3_DSE_MASK (0x3U) #define IOMUXD_USB_SS3_TC3_DSE_SHIFT (0U) /*! DSE - Drive * 0b00..Drive select 2mA * 0b11..Drive select 12mA * 0b01..Drive select 4mA * 0b10..Drive select 8mA */ #define IOMUXD_USB_SS3_TC3_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_DSE_SHIFT)) & IOMUXD_USB_SS3_TC3_DSE_MASK) #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_MASK (0x1CU) #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_SHIFT (2U) /*! USB_SS3_TC3_reserved_2_4 - reserved */ #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_MASK) #define IOMUXD_USB_SS3_TC3_PULL_MASK (0x60U) #define IOMUXD_USB_SS3_TC3_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_USB_SS3_TC3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_PULL_SHIFT)) & IOMUXD_USB_SS3_TC3_PULL_MASK) #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_SHIFT (7U) /*! USB_SS3_TC3_reserved_7_18 - reserved */ #define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_MASK) #define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_MASK) #define IOMUXD_USB_SS3_TC3_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USB_SS3_TC3_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USB_SS3_TC3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC3_WAKEUP_MASK_MASK) #define IOMUXD_USB_SS3_TC3_lp_config_MASK (0x1800000U) #define IOMUXD_USB_SS3_TC3_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USB_SS3_TC3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC3_lp_config_MASK) #define IOMUXD_USB_SS3_TC3_sw_config_MASK (0x6000000U) #define IOMUXD_USB_SS3_TC3_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USB_SS3_TC3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC3_sw_config_MASK) #define IOMUXD_USB_SS3_TC3_mux_mode_MASK (0x38000000U) #define IOMUXD_USB_SS3_TC3_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.I2C1.SDA * 0b001..CONN.USB_OTG2.OC * 0b100..LSIO.GPIO4.IO06 */ #define IOMUXD_USB_SS3_TC3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC3_mux_mode_MASK) #define IOMUXD_USB_SS3_TC3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USB_SS3_TC3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USB_SS3_TC3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC3_update_pad_ctl_MASK) #define IOMUXD_USB_SS3_TC3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USB_SS3_TC3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USB_SS3_TC3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC3_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_3V3_USB3IO - IOMUXD_COMP_CTL_GPIO_3V3_USB3IO */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_MASK (0x7FFFFFU) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_SHIFT (0U) /*! IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..LAST * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_0_0 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_SHIFT (0U) /*! PCIE_CTRL0_PERST_B - wakeup from PCIE_CTRL0_PERST_B */ #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_MASK) #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_SHIFT (1U) /*! PCIE_CTRL0_CLKREQ_B - wakeup from PCIE_CTRL0_CLKREQ_B */ #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_MASK) #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_SHIFT (2U) /*! PCIE_CTRL0_WAKE_B - wakeup from PCIE_CTRL0_WAKE_B */ #define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_MASK) #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_SHIFT (3U) /*! iomuxd_group_0_0_reserved_3_3 - reserved */ #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_MASK) #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_SHIFT (4U) /*! USB_SS3_TC0 - wakeup from USB_SS3_TC0 */ #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_MASK) #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_SHIFT (5U) /*! USB_SS3_TC1 - wakeup from USB_SS3_TC1 */ #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_MASK) #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_SHIFT (6U) /*! USB_SS3_TC2 - wakeup from USB_SS3_TC2 */ #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_MASK) #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_SHIFT (7U) /*! USB_SS3_TC3 - wakeup from USB_SS3_TC3 */ #define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_MASK) #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_MASK (0xFFFFFF00U) #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_SHIFT (8U) /*! iomuxd_group_0_0_reserved_8_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_MASK) /*! @} */ /*! @name EMMC0_CLK - EMMC0_CLK */ /*! @{ */ #define IOMUXD_EMMC0_CLK_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_CLK_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_CLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_PDRV_SHIFT)) & IOMUXD_EMMC0_CLK_PDRV_MASK) #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_SHIFT (1U) /*! EMMC0_CLK_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_MASK) #define IOMUXD_EMMC0_CLK_PULL_MASK (0x60U) #define IOMUXD_EMMC0_CLK_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_CLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_PULL_SHIFT)) & IOMUXD_EMMC0_CLK_PULL_MASK) #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_SHIFT (7U) /*! EMMC0_CLK_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_MASK) #define IOMUXD_EMMC0_CLK_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_CLK_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_CLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_CLK_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_CLK_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_CLK_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_CLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_CLK_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_CLK_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_CLK_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_CLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_lp_config_SHIFT)) & IOMUXD_EMMC0_CLK_lp_config_MASK) #define IOMUXD_EMMC0_CLK_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_CLK_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_CLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_sw_config_SHIFT)) & IOMUXD_EMMC0_CLK_sw_config_MASK) #define IOMUXD_EMMC0_CLK_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_CLK_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.CLK * 0b001..CONN.NAND.READY_B * 0b100..LSIO.GPIO4.IO07 */ #define IOMUXD_EMMC0_CLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_mux_mode_SHIFT)) & IOMUXD_EMMC0_CLK_mux_mode_MASK) #define IOMUXD_EMMC0_CLK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_CLK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_CLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_CLK_update_pad_ctl_MASK) #define IOMUXD_EMMC0_CLK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_CLK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_CLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_CLK_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_CMD - EMMC0_CMD */ /*! @{ */ #define IOMUXD_EMMC0_CMD_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_CMD_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_CMD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_PDRV_SHIFT)) & IOMUXD_EMMC0_CMD_PDRV_MASK) #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_SHIFT (1U) /*! EMMC0_CMD_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_MASK) #define IOMUXD_EMMC0_CMD_PULL_MASK (0x60U) #define IOMUXD_EMMC0_CMD_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_CMD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_PULL_SHIFT)) & IOMUXD_EMMC0_CMD_PULL_MASK) #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_SHIFT (7U) /*! EMMC0_CMD_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_MASK) #define IOMUXD_EMMC0_CMD_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_CMD_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_CMD_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_CMD_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_CMD_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_CMD_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_CMD_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_CMD_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_CMD_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_CMD_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_CMD_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_lp_config_SHIFT)) & IOMUXD_EMMC0_CMD_lp_config_MASK) #define IOMUXD_EMMC0_CMD_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_CMD_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_CMD_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_sw_config_SHIFT)) & IOMUXD_EMMC0_CMD_sw_config_MASK) #define IOMUXD_EMMC0_CMD_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_CMD_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.CMD * 0b001..CONN.NAND.DQS * 0b100..LSIO.GPIO4.IO08 */ #define IOMUXD_EMMC0_CMD_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_mux_mode_SHIFT)) & IOMUXD_EMMC0_CMD_mux_mode_MASK) #define IOMUXD_EMMC0_CMD_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_CMD_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_CMD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_CMD_update_pad_ctl_MASK) #define IOMUXD_EMMC0_CMD_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_CMD_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_CMD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_CMD_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_DATA0 - EMMC0_DATA0 */ /*! @{ */ #define IOMUXD_EMMC0_DATA0_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_DATA0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_DATA0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA0_PDRV_MASK) #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_SHIFT (1U) /*! EMMC0_DATA0_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_MASK) #define IOMUXD_EMMC0_DATA0_PULL_MASK (0x60U) #define IOMUXD_EMMC0_DATA0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_DATA0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_PULL_SHIFT)) & IOMUXD_EMMC0_DATA0_PULL_MASK) #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_SHIFT (7U) /*! EMMC0_DATA0_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_MASK) #define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_DATA0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_DATA0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_DATA0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA0_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_DATA0_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_DATA0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_DATA0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA0_lp_config_MASK) #define IOMUXD_EMMC0_DATA0_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_DATA0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_DATA0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA0_sw_config_MASK) #define IOMUXD_EMMC0_DATA0_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_DATA0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.DATA0 * 0b001..CONN.NAND.DATA00 * 0b100..LSIO.GPIO4.IO09 */ #define IOMUXD_EMMC0_DATA0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA0_mux_mode_MASK) #define IOMUXD_EMMC0_DATA0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_DATA0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_DATA0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA0_update_pad_ctl_MASK) #define IOMUXD_EMMC0_DATA0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_DATA0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_DATA0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA0_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_DATA1 - EMMC0_DATA1 */ /*! @{ */ #define IOMUXD_EMMC0_DATA1_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_DATA1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_DATA1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA1_PDRV_MASK) #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_SHIFT (1U) /*! EMMC0_DATA1_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_MASK) #define IOMUXD_EMMC0_DATA1_PULL_MASK (0x60U) #define IOMUXD_EMMC0_DATA1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_DATA1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_PULL_SHIFT)) & IOMUXD_EMMC0_DATA1_PULL_MASK) #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_SHIFT (7U) /*! EMMC0_DATA1_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_MASK) #define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_DATA1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_DATA1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_DATA1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA1_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_DATA1_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_DATA1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_DATA1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA1_lp_config_MASK) #define IOMUXD_EMMC0_DATA1_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_DATA1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_DATA1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA1_sw_config_MASK) #define IOMUXD_EMMC0_DATA1_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_DATA1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.DATA1 * 0b001..CONN.NAND.DATA01 * 0b100..LSIO.GPIO4.IO10 */ #define IOMUXD_EMMC0_DATA1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA1_mux_mode_MASK) #define IOMUXD_EMMC0_DATA1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_DATA1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_DATA1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA1_update_pad_ctl_MASK) #define IOMUXD_EMMC0_DATA1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_DATA1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_DATA1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA1_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_DATA2 - EMMC0_DATA2 */ /*! @{ */ #define IOMUXD_EMMC0_DATA2_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_DATA2_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_DATA2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA2_PDRV_MASK) #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_SHIFT (1U) /*! EMMC0_DATA2_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_MASK) #define IOMUXD_EMMC0_DATA2_PULL_MASK (0x60U) #define IOMUXD_EMMC0_DATA2_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_DATA2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_PULL_SHIFT)) & IOMUXD_EMMC0_DATA2_PULL_MASK) #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_SHIFT (7U) /*! EMMC0_DATA2_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_MASK) #define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_DATA2_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_DATA2_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_DATA2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA2_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_DATA2_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_DATA2_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_DATA2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA2_lp_config_MASK) #define IOMUXD_EMMC0_DATA2_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_DATA2_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_DATA2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA2_sw_config_MASK) #define IOMUXD_EMMC0_DATA2_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_DATA2_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.DATA2 * 0b001..CONN.NAND.DATA02 * 0b100..LSIO.GPIO4.IO11 */ #define IOMUXD_EMMC0_DATA2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA2_mux_mode_MASK) #define IOMUXD_EMMC0_DATA2_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_DATA2_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_DATA2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA2_update_pad_ctl_MASK) #define IOMUXD_EMMC0_DATA2_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_DATA2_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_DATA2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA2_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_DATA3 - EMMC0_DATA3 */ /*! @{ */ #define IOMUXD_EMMC0_DATA3_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_DATA3_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_DATA3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA3_PDRV_MASK) #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_SHIFT (1U) /*! EMMC0_DATA3_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_MASK) #define IOMUXD_EMMC0_DATA3_PULL_MASK (0x60U) #define IOMUXD_EMMC0_DATA3_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_DATA3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_PULL_SHIFT)) & IOMUXD_EMMC0_DATA3_PULL_MASK) #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_SHIFT (7U) /*! EMMC0_DATA3_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_MASK) #define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_DATA3_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_DATA3_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_DATA3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA3_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_DATA3_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_DATA3_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_DATA3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA3_lp_config_MASK) #define IOMUXD_EMMC0_DATA3_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_DATA3_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_DATA3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA3_sw_config_MASK) #define IOMUXD_EMMC0_DATA3_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_DATA3_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.DATA3 * 0b001..CONN.NAND.DATA03 * 0b100..LSIO.GPIO4.IO12 */ #define IOMUXD_EMMC0_DATA3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA3_mux_mode_MASK) #define IOMUXD_EMMC0_DATA3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_DATA3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_DATA3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA3_update_pad_ctl_MASK) #define IOMUXD_EMMC0_DATA3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_DATA3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_DATA3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA3_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_DATA4 - EMMC0_DATA4 */ /*! @{ */ #define IOMUXD_EMMC0_DATA4_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_DATA4_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_DATA4_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA4_PDRV_MASK) #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_SHIFT (1U) /*! EMMC0_DATA4_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_MASK) #define IOMUXD_EMMC0_DATA4_PULL_MASK (0x60U) #define IOMUXD_EMMC0_DATA4_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_DATA4_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_PULL_SHIFT)) & IOMUXD_EMMC0_DATA4_PULL_MASK) #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_SHIFT (7U) /*! EMMC0_DATA4_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_MASK) #define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_DATA4_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_DATA4_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_DATA4_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA4_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_DATA4_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_DATA4_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_DATA4_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA4_lp_config_MASK) #define IOMUXD_EMMC0_DATA4_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_DATA4_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_DATA4_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA4_sw_config_MASK) #define IOMUXD_EMMC0_DATA4_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_DATA4_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.DATA4 * 0b001..CONN.NAND.DATA04 * 0b011..CONN.EMMC0.WP * 0b100..LSIO.GPIO4.IO13 */ #define IOMUXD_EMMC0_DATA4_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA4_mux_mode_MASK) #define IOMUXD_EMMC0_DATA4_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_DATA4_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_DATA4_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA4_update_pad_ctl_MASK) #define IOMUXD_EMMC0_DATA4_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_DATA4_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_DATA4_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA4_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_DATA5 - EMMC0_DATA5 */ /*! @{ */ #define IOMUXD_EMMC0_DATA5_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_DATA5_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_DATA5_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA5_PDRV_MASK) #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_SHIFT (1U) /*! EMMC0_DATA5_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_MASK) #define IOMUXD_EMMC0_DATA5_PULL_MASK (0x60U) #define IOMUXD_EMMC0_DATA5_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_DATA5_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_PULL_SHIFT)) & IOMUXD_EMMC0_DATA5_PULL_MASK) #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_SHIFT (7U) /*! EMMC0_DATA5_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_MASK) #define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_DATA5_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_DATA5_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_DATA5_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA5_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_DATA5_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_DATA5_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_DATA5_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA5_lp_config_MASK) #define IOMUXD_EMMC0_DATA5_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_DATA5_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_DATA5_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA5_sw_config_MASK) #define IOMUXD_EMMC0_DATA5_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_DATA5_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.DATA5 * 0b001..CONN.NAND.DATA05 * 0b011..CONN.EMMC0.VSELECT * 0b100..LSIO.GPIO4.IO14 */ #define IOMUXD_EMMC0_DATA5_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA5_mux_mode_MASK) #define IOMUXD_EMMC0_DATA5_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_DATA5_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_DATA5_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA5_update_pad_ctl_MASK) #define IOMUXD_EMMC0_DATA5_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_DATA5_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_DATA5_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA5_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_DATA6 - EMMC0_DATA6 */ /*! @{ */ #define IOMUXD_EMMC0_DATA6_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_DATA6_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_DATA6_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA6_PDRV_MASK) #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_SHIFT (1U) /*! EMMC0_DATA6_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_MASK) #define IOMUXD_EMMC0_DATA6_PULL_MASK (0x60U) #define IOMUXD_EMMC0_DATA6_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_DATA6_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_PULL_SHIFT)) & IOMUXD_EMMC0_DATA6_PULL_MASK) #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_SHIFT (7U) /*! EMMC0_DATA6_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_MASK) #define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_DATA6_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_DATA6_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_DATA6_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA6_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_DATA6_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_DATA6_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_DATA6_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA6_lp_config_MASK) #define IOMUXD_EMMC0_DATA6_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_DATA6_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_DATA6_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA6_sw_config_MASK) #define IOMUXD_EMMC0_DATA6_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_DATA6_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.DATA6 * 0b001..CONN.NAND.DATA06 * 0b011..CONN.MLB.CLK * 0b100..LSIO.GPIO4.IO15 */ #define IOMUXD_EMMC0_DATA6_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA6_mux_mode_MASK) #define IOMUXD_EMMC0_DATA6_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_DATA6_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_DATA6_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA6_update_pad_ctl_MASK) #define IOMUXD_EMMC0_DATA6_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_DATA6_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_DATA6_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA6_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_DATA7 - EMMC0_DATA7 */ /*! @{ */ #define IOMUXD_EMMC0_DATA7_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_DATA7_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_DATA7_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA7_PDRV_MASK) #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_SHIFT (1U) /*! EMMC0_DATA7_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_MASK) #define IOMUXD_EMMC0_DATA7_PULL_MASK (0x60U) #define IOMUXD_EMMC0_DATA7_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_DATA7_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_PULL_SHIFT)) & IOMUXD_EMMC0_DATA7_PULL_MASK) #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_SHIFT (7U) /*! EMMC0_DATA7_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_MASK) #define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_DATA7_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_DATA7_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_DATA7_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA7_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_DATA7_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_DATA7_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_DATA7_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA7_lp_config_MASK) #define IOMUXD_EMMC0_DATA7_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_DATA7_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_DATA7_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA7_sw_config_MASK) #define IOMUXD_EMMC0_DATA7_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_DATA7_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.DATA7 * 0b001..CONN.NAND.DATA07 * 0b011..CONN.MLB.SIG * 0b100..LSIO.GPIO4.IO16 */ #define IOMUXD_EMMC0_DATA7_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA7_mux_mode_MASK) #define IOMUXD_EMMC0_DATA7_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_DATA7_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_DATA7_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA7_update_pad_ctl_MASK) #define IOMUXD_EMMC0_DATA7_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_DATA7_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_DATA7_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA7_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_STROBE - EMMC0_STROBE */ /*! @{ */ #define IOMUXD_EMMC0_STROBE_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_STROBE_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_STROBE_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_PDRV_SHIFT)) & IOMUXD_EMMC0_STROBE_PDRV_MASK) #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_SHIFT (1U) /*! EMMC0_STROBE_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_MASK) #define IOMUXD_EMMC0_STROBE_PULL_MASK (0x60U) #define IOMUXD_EMMC0_STROBE_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_STROBE_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_PULL_SHIFT)) & IOMUXD_EMMC0_STROBE_PULL_MASK) #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_SHIFT (7U) /*! EMMC0_STROBE_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_MASK) #define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_STROBE_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_STROBE_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_STROBE_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_STROBE_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_STROBE_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_STROBE_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_STROBE_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_lp_config_SHIFT)) & IOMUXD_EMMC0_STROBE_lp_config_MASK) #define IOMUXD_EMMC0_STROBE_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_STROBE_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_STROBE_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_sw_config_SHIFT)) & IOMUXD_EMMC0_STROBE_sw_config_MASK) #define IOMUXD_EMMC0_STROBE_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_STROBE_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.STROBE * 0b001..CONN.NAND.CLE * 0b011..CONN.MLB.DATA * 0b100..LSIO.GPIO4.IO17 */ #define IOMUXD_EMMC0_STROBE_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_mux_mode_SHIFT)) & IOMUXD_EMMC0_STROBE_mux_mode_MASK) #define IOMUXD_EMMC0_STROBE_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_STROBE_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_STROBE_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_STROBE_update_pad_ctl_MASK) #define IOMUXD_EMMC0_STROBE_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_STROBE_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_STROBE_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_STROBE_update_mux_mode_MASK) /*! @} */ /*! @name EMMC0_RESET_B - EMMC0_RESET_B */ /*! @{ */ #define IOMUXD_EMMC0_RESET_B_PDRV_MASK (0x1U) #define IOMUXD_EMMC0_RESET_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_EMMC0_RESET_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_PDRV_SHIFT)) & IOMUXD_EMMC0_RESET_B_PDRV_MASK) #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_SHIFT (1U) /*! EMMC0_RESET_B_reserved_1_4 - reserved */ #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_MASK) #define IOMUXD_EMMC0_RESET_B_PULL_MASK (0x60U) #define IOMUXD_EMMC0_RESET_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_EMMC0_RESET_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_PULL_SHIFT)) & IOMUXD_EMMC0_RESET_B_PULL_MASK) #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_SHIFT (7U) /*! EMMC0_RESET_B_reserved_7_18 - reserved */ #define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_MASK) #define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_MASK) #define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_MASK) #define IOMUXD_EMMC0_RESET_B_lp_config_MASK (0x1800000U) #define IOMUXD_EMMC0_RESET_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_EMMC0_RESET_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_lp_config_SHIFT)) & IOMUXD_EMMC0_RESET_B_lp_config_MASK) #define IOMUXD_EMMC0_RESET_B_sw_config_MASK (0x6000000U) #define IOMUXD_EMMC0_RESET_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_EMMC0_RESET_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_sw_config_SHIFT)) & IOMUXD_EMMC0_RESET_B_sw_config_MASK) #define IOMUXD_EMMC0_RESET_B_mux_mode_MASK (0x38000000U) #define IOMUXD_EMMC0_RESET_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.EMMC0.RESET_B * 0b001..CONN.NAND.WP_B * 0b100..LSIO.GPIO4.IO18 */ #define IOMUXD_EMMC0_RESET_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_mux_mode_SHIFT)) & IOMUXD_EMMC0_RESET_B_mux_mode_MASK) #define IOMUXD_EMMC0_RESET_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_EMMC0_RESET_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_EMMC0_RESET_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_RESET_B_update_pad_ctl_MASK) #define IOMUXD_EMMC0_RESET_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_EMMC0_RESET_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_EMMC0_RESET_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_RESET_B_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_MASK) /*! @} */ /*! @name USDHC1_RESET_B - USDHC1_RESET_B */ /*! @{ */ #define IOMUXD_USDHC1_RESET_B_PDRV_MASK (0x1U) #define IOMUXD_USDHC1_RESET_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_USDHC1_RESET_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_PDRV_SHIFT)) & IOMUXD_USDHC1_RESET_B_PDRV_MASK) #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_SHIFT (1U) /*! USDHC1_RESET_B_reserved_1_4 - reserved */ #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_MASK) #define IOMUXD_USDHC1_RESET_B_PULL_MASK (0x60U) #define IOMUXD_USDHC1_RESET_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_USDHC1_RESET_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_PULL_SHIFT)) & IOMUXD_USDHC1_RESET_B_PULL_MASK) #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_SHIFT (7U) /*! USDHC1_RESET_B_reserved_7_18 - reserved */ #define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_MASK) #define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_MASK) #define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_MASK) #define IOMUXD_USDHC1_RESET_B_lp_config_MASK (0x1800000U) #define IOMUXD_USDHC1_RESET_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USDHC1_RESET_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_lp_config_SHIFT)) & IOMUXD_USDHC1_RESET_B_lp_config_MASK) #define IOMUXD_USDHC1_RESET_B_sw_config_MASK (0x6000000U) #define IOMUXD_USDHC1_RESET_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USDHC1_RESET_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_sw_config_SHIFT)) & IOMUXD_USDHC1_RESET_B_sw_config_MASK) #define IOMUXD_USDHC1_RESET_B_mux_mode_MASK (0x38000000U) #define IOMUXD_USDHC1_RESET_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.USDHC1.RESET_B * 0b001..CONN.NAND.RE_N * 0b010..ADMA.SPI2.SCK * 0b100..LSIO.GPIO4.IO19 */ #define IOMUXD_USDHC1_RESET_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_mux_mode_SHIFT)) & IOMUXD_USDHC1_RESET_B_mux_mode_MASK) #define IOMUXD_USDHC1_RESET_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USDHC1_RESET_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USDHC1_RESET_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_RESET_B_update_pad_ctl_MASK) #define IOMUXD_USDHC1_RESET_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USDHC1_RESET_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USDHC1_RESET_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_RESET_B_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_1_0 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_SHIFT (0U) /*! EMMC0_CLK - wakeup from EMMC0_CLK */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_SHIFT (1U) /*! EMMC0_CMD - wakeup from EMMC0_CMD */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_SHIFT (2U) /*! EMMC0_DATA0 - wakeup from EMMC0_DATA0 */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_SHIFT (3U) /*! EMMC0_DATA1 - wakeup from EMMC0_DATA1 */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_SHIFT (4U) /*! EMMC0_DATA2 - wakeup from EMMC0_DATA2 */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_SHIFT (5U) /*! EMMC0_DATA3 - wakeup from EMMC0_DATA3 */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_SHIFT (6U) /*! iomuxd_group_1_0_reserved_6_6 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_SHIFT (7U) /*! EMMC0_DATA4 - wakeup from EMMC0_DATA4 */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_SHIFT (8U) /*! EMMC0_DATA5 - wakeup from EMMC0_DATA5 */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_SHIFT (9U) /*! EMMC0_DATA6 - wakeup from EMMC0_DATA6 */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_SHIFT (10U) /*! EMMC0_DATA7 - wakeup from EMMC0_DATA7 */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_SHIFT (11U) /*! EMMC0_STROBE - wakeup from EMMC0_STROBE */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_SHIFT (12U) /*! EMMC0_RESET_B - wakeup from EMMC0_RESET_B */ #define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_MASK (0x2000U) #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_SHIFT (13U) /*! iomuxd_group_1_0_reserved_13_13 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_MASK (0x4000U) #define IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_SHIFT (14U) /*! USDHC1_RESET_B - wakeup from USDHC1_RESET_B */ #define IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_MASK) #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_MASK (0xFFFF8000U) #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_SHIFT (15U) /*! iomuxd_group_1_0_reserved_15_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_MASK) /*! @} */ /*! @name USDHC1_VSELECT - USDHC1_VSELECT */ /*! @{ */ #define IOMUXD_USDHC1_VSELECT_PDRV_MASK (0x1U) #define IOMUXD_USDHC1_VSELECT_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_USDHC1_VSELECT_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_PDRV_SHIFT)) & IOMUXD_USDHC1_VSELECT_PDRV_MASK) #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_MASK (0x1EU) #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_SHIFT (1U) /*! USDHC1_VSELECT_reserved_1_4 - reserved */ #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_MASK) #define IOMUXD_USDHC1_VSELECT_PULL_MASK (0x60U) #define IOMUXD_USDHC1_VSELECT_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_USDHC1_VSELECT_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_PULL_SHIFT)) & IOMUXD_USDHC1_VSELECT_PULL_MASK) #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_SHIFT (7U) /*! USDHC1_VSELECT_reserved_7_18 - reserved */ #define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_MASK) #define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_MASK) #define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_MASK) #define IOMUXD_USDHC1_VSELECT_lp_config_MASK (0x1800000U) #define IOMUXD_USDHC1_VSELECT_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USDHC1_VSELECT_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_lp_config_SHIFT)) & IOMUXD_USDHC1_VSELECT_lp_config_MASK) #define IOMUXD_USDHC1_VSELECT_sw_config_MASK (0x6000000U) #define IOMUXD_USDHC1_VSELECT_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USDHC1_VSELECT_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_sw_config_SHIFT)) & IOMUXD_USDHC1_VSELECT_sw_config_MASK) #define IOMUXD_USDHC1_VSELECT_mux_mode_MASK (0x38000000U) #define IOMUXD_USDHC1_VSELECT_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.USDHC1.VSELECT * 0b001..CONN.NAND.RE_P * 0b010..ADMA.SPI2.SDO * 0b011..CONN.NAND.RE_B * 0b100..LSIO.GPIO4.IO20 */ #define IOMUXD_USDHC1_VSELECT_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_mux_mode_SHIFT)) & IOMUXD_USDHC1_VSELECT_mux_mode_MASK) #define IOMUXD_USDHC1_VSELECT_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USDHC1_VSELECT_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USDHC1_VSELECT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_VSELECT_update_pad_ctl_MASK) #define IOMUXD_USDHC1_VSELECT_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USDHC1_VSELECT_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USDHC1_VSELECT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_VSELECT_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_CTL_NAND_RE_P_N - IOMUXD_CTL_NAND_RE_P_N */ /*! @{ */ #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_MASK (0x1U) #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_SHIFT (0U) /*! P_N_SELECT - P_N_SELECT * 0b0.. * 0b1.. */ #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_MASK) #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_MASK (0x3FFFFFFEU) #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_SHIFT (1U) /*! IOMUXD_CTL_NAND_RE_P_N_reserved_1_29 - reserved */ #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_MASK) #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_MASK) /*! @} */ /*! @name USDHC1_WP - USDHC1_WP */ /*! @{ */ #define IOMUXD_USDHC1_WP_PDRV_MASK (0x1U) #define IOMUXD_USDHC1_WP_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_USDHC1_WP_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_PDRV_SHIFT)) & IOMUXD_USDHC1_WP_PDRV_MASK) #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_MASK (0x1EU) #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_SHIFT (1U) /*! USDHC1_WP_reserved_1_4 - reserved */ #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_MASK) #define IOMUXD_USDHC1_WP_PULL_MASK (0x60U) #define IOMUXD_USDHC1_WP_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_USDHC1_WP_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_PULL_SHIFT)) & IOMUXD_USDHC1_WP_PULL_MASK) #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_SHIFT (7U) /*! USDHC1_WP_reserved_7_18 - reserved */ #define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_MASK) #define IOMUXD_USDHC1_WP_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USDHC1_WP_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USDHC1_WP_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_WP_WAKEUP_CTRL_MASK) #define IOMUXD_USDHC1_WP_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USDHC1_WP_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USDHC1_WP_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_WP_WAKEUP_MASK_MASK) #define IOMUXD_USDHC1_WP_lp_config_MASK (0x1800000U) #define IOMUXD_USDHC1_WP_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USDHC1_WP_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_lp_config_SHIFT)) & IOMUXD_USDHC1_WP_lp_config_MASK) #define IOMUXD_USDHC1_WP_sw_config_MASK (0x6000000U) #define IOMUXD_USDHC1_WP_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USDHC1_WP_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_sw_config_SHIFT)) & IOMUXD_USDHC1_WP_sw_config_MASK) #define IOMUXD_USDHC1_WP_mux_mode_MASK (0x38000000U) #define IOMUXD_USDHC1_WP_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.USDHC1.WP * 0b001..CONN.NAND.DQS_N * 0b010..ADMA.SPI2.SDI * 0b100..LSIO.GPIO4.IO21 */ #define IOMUXD_USDHC1_WP_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_mux_mode_SHIFT)) & IOMUXD_USDHC1_WP_mux_mode_MASK) #define IOMUXD_USDHC1_WP_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USDHC1_WP_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USDHC1_WP_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_WP_update_pad_ctl_MASK) #define IOMUXD_USDHC1_WP_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USDHC1_WP_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USDHC1_WP_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_WP_update_mux_mode_MASK) /*! @} */ /*! @name USDHC1_CD_B - USDHC1_CD_B */ /*! @{ */ #define IOMUXD_USDHC1_CD_B_PDRV_MASK (0x1U) #define IOMUXD_USDHC1_CD_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_USDHC1_CD_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_PDRV_SHIFT)) & IOMUXD_USDHC1_CD_B_PDRV_MASK) #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_SHIFT (1U) /*! USDHC1_CD_B_reserved_1_4 - reserved */ #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_MASK) #define IOMUXD_USDHC1_CD_B_PULL_MASK (0x60U) #define IOMUXD_USDHC1_CD_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_USDHC1_CD_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_PULL_SHIFT)) & IOMUXD_USDHC1_CD_B_PULL_MASK) #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_SHIFT (7U) /*! USDHC1_CD_B_reserved_7_18 - reserved */ #define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_MASK) #define IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USDHC1_CD_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_MASK) #define IOMUXD_USDHC1_CD_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USDHC1_CD_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USDHC1_CD_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CD_B_WAKEUP_MASK_MASK) #define IOMUXD_USDHC1_CD_B_lp_config_MASK (0x1800000U) #define IOMUXD_USDHC1_CD_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USDHC1_CD_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_lp_config_SHIFT)) & IOMUXD_USDHC1_CD_B_lp_config_MASK) #define IOMUXD_USDHC1_CD_B_sw_config_MASK (0x6000000U) #define IOMUXD_USDHC1_CD_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USDHC1_CD_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_sw_config_SHIFT)) & IOMUXD_USDHC1_CD_B_sw_config_MASK) #define IOMUXD_USDHC1_CD_B_mux_mode_MASK (0x38000000U) #define IOMUXD_USDHC1_CD_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.USDHC1.CD_B * 0b001..CONN.NAND.DQS_P * 0b010..ADMA.SPI2.CS0 * 0b011..CONN.NAND.DQS * 0b100..LSIO.GPIO4.IO22 */ #define IOMUXD_USDHC1_CD_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_mux_mode_SHIFT)) & IOMUXD_USDHC1_CD_B_mux_mode_MASK) #define IOMUXD_USDHC1_CD_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USDHC1_CD_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USDHC1_CD_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CD_B_update_pad_ctl_MASK) #define IOMUXD_USDHC1_CD_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USDHC1_CD_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USDHC1_CD_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CD_B_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_CTL_NAND_DQS_P_N - IOMUXD_CTL_NAND_DQS_P_N */ /*! @{ */ #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_MASK (0x1U) #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_SHIFT (0U) /*! P_N_SELECT - P_N_SELECT * 0b0.. * 0b1.. */ #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_MASK) #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_MASK (0x3FFFFFFEU) #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_SHIFT (1U) /*! IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29 - reserved */ #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_MASK) #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP - IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_MASK) /*! @} */ /*! @name USDHC1_CLK - USDHC1_CLK */ /*! @{ */ #define IOMUXD_USDHC1_CLK_PDRV_MASK (0x1U) #define IOMUXD_USDHC1_CLK_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_USDHC1_CLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_PDRV_SHIFT)) & IOMUXD_USDHC1_CLK_PDRV_MASK) #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_MASK (0x1EU) #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_SHIFT (1U) /*! USDHC1_CLK_reserved_1_4 - reserved */ #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_MASK) #define IOMUXD_USDHC1_CLK_PULL_MASK (0x60U) #define IOMUXD_USDHC1_CLK_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_USDHC1_CLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_PULL_SHIFT)) & IOMUXD_USDHC1_CLK_PULL_MASK) #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_SHIFT (7U) /*! USDHC1_CLK_reserved_7_18 - reserved */ #define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_MASK) #define IOMUXD_USDHC1_CLK_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USDHC1_CLK_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USDHC1_CLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CLK_WAKEUP_CTRL_MASK) #define IOMUXD_USDHC1_CLK_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USDHC1_CLK_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USDHC1_CLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CLK_WAKEUP_MASK_MASK) #define IOMUXD_USDHC1_CLK_lp_config_MASK (0x1800000U) #define IOMUXD_USDHC1_CLK_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USDHC1_CLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_lp_config_SHIFT)) & IOMUXD_USDHC1_CLK_lp_config_MASK) #define IOMUXD_USDHC1_CLK_sw_config_MASK (0x6000000U) #define IOMUXD_USDHC1_CLK_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USDHC1_CLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_sw_config_SHIFT)) & IOMUXD_USDHC1_CLK_sw_config_MASK) #define IOMUXD_USDHC1_CLK_mux_mode_MASK (0x38000000U) #define IOMUXD_USDHC1_CLK_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.USDHC1.CLK * 0b010..ADMA.UART3.RX * 0b100..LSIO.GPIO4.IO23 */ #define IOMUXD_USDHC1_CLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_mux_mode_SHIFT)) & IOMUXD_USDHC1_CLK_mux_mode_MASK) #define IOMUXD_USDHC1_CLK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USDHC1_CLK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USDHC1_CLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CLK_update_pad_ctl_MASK) #define IOMUXD_USDHC1_CLK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USDHC1_CLK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USDHC1_CLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CLK_update_mux_mode_MASK) /*! @} */ /*! @name USDHC1_CMD - USDHC1_CMD */ /*! @{ */ #define IOMUXD_USDHC1_CMD_PDRV_MASK (0x1U) #define IOMUXD_USDHC1_CMD_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_USDHC1_CMD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_PDRV_SHIFT)) & IOMUXD_USDHC1_CMD_PDRV_MASK) #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_MASK (0x1EU) #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_SHIFT (1U) /*! USDHC1_CMD_reserved_1_4 - reserved */ #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_MASK) #define IOMUXD_USDHC1_CMD_PULL_MASK (0x60U) #define IOMUXD_USDHC1_CMD_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_USDHC1_CMD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_PULL_SHIFT)) & IOMUXD_USDHC1_CMD_PULL_MASK) #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_SHIFT (7U) /*! USDHC1_CMD_reserved_7_18 - reserved */ #define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_MASK) #define IOMUXD_USDHC1_CMD_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USDHC1_CMD_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USDHC1_CMD_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CMD_WAKEUP_CTRL_MASK) #define IOMUXD_USDHC1_CMD_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USDHC1_CMD_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USDHC1_CMD_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CMD_WAKEUP_MASK_MASK) #define IOMUXD_USDHC1_CMD_lp_config_MASK (0x1800000U) #define IOMUXD_USDHC1_CMD_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USDHC1_CMD_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_lp_config_SHIFT)) & IOMUXD_USDHC1_CMD_lp_config_MASK) #define IOMUXD_USDHC1_CMD_sw_config_MASK (0x6000000U) #define IOMUXD_USDHC1_CMD_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USDHC1_CMD_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_sw_config_SHIFT)) & IOMUXD_USDHC1_CMD_sw_config_MASK) #define IOMUXD_USDHC1_CMD_mux_mode_MASK (0x38000000U) #define IOMUXD_USDHC1_CMD_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.USDHC1.CMD * 0b001..CONN.NAND.CE0_B * 0b010..ADMA.MQS.R * 0b100..LSIO.GPIO4.IO24 */ #define IOMUXD_USDHC1_CMD_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_mux_mode_SHIFT)) & IOMUXD_USDHC1_CMD_mux_mode_MASK) #define IOMUXD_USDHC1_CMD_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USDHC1_CMD_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USDHC1_CMD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CMD_update_pad_ctl_MASK) #define IOMUXD_USDHC1_CMD_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USDHC1_CMD_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USDHC1_CMD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CMD_update_mux_mode_MASK) /*! @} */ /*! @name USDHC1_DATA0 - USDHC1_DATA0 */ /*! @{ */ #define IOMUXD_USDHC1_DATA0_PDRV_MASK (0x1U) #define IOMUXD_USDHC1_DATA0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_USDHC1_DATA0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA0_PDRV_MASK) #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_MASK (0x1EU) #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_SHIFT (1U) /*! USDHC1_DATA0_reserved_1_4 - reserved */ #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_MASK) #define IOMUXD_USDHC1_DATA0_PULL_MASK (0x60U) #define IOMUXD_USDHC1_DATA0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_USDHC1_DATA0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_PULL_SHIFT)) & IOMUXD_USDHC1_DATA0_PULL_MASK) #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_SHIFT (7U) /*! USDHC1_DATA0_reserved_7_18 - reserved */ #define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_MASK) #define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_MASK) #define IOMUXD_USDHC1_DATA0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USDHC1_DATA0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USDHC1_DATA0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA0_WAKEUP_MASK_MASK) #define IOMUXD_USDHC1_DATA0_lp_config_MASK (0x1800000U) #define IOMUXD_USDHC1_DATA0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USDHC1_DATA0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA0_lp_config_MASK) #define IOMUXD_USDHC1_DATA0_sw_config_MASK (0x6000000U) #define IOMUXD_USDHC1_DATA0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USDHC1_DATA0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA0_sw_config_MASK) #define IOMUXD_USDHC1_DATA0_mux_mode_MASK (0x38000000U) #define IOMUXD_USDHC1_DATA0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.USDHC1.DATA0 * 0b001..CONN.NAND.CE1_B * 0b010..ADMA.MQS.L * 0b100..LSIO.GPIO4.IO25 */ #define IOMUXD_USDHC1_DATA0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA0_mux_mode_MASK) #define IOMUXD_USDHC1_DATA0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USDHC1_DATA0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USDHC1_DATA0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA0_update_pad_ctl_MASK) #define IOMUXD_USDHC1_DATA0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USDHC1_DATA0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USDHC1_DATA0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA0_update_mux_mode_MASK) /*! @} */ /*! @name USDHC1_DATA1 - USDHC1_DATA1 */ /*! @{ */ #define IOMUXD_USDHC1_DATA1_PDRV_MASK (0x1U) #define IOMUXD_USDHC1_DATA1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_USDHC1_DATA1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA1_PDRV_MASK) #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_MASK (0x1EU) #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_SHIFT (1U) /*! USDHC1_DATA1_reserved_1_4 - reserved */ #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_MASK) #define IOMUXD_USDHC1_DATA1_PULL_MASK (0x60U) #define IOMUXD_USDHC1_DATA1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_USDHC1_DATA1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_PULL_SHIFT)) & IOMUXD_USDHC1_DATA1_PULL_MASK) #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_SHIFT (7U) /*! USDHC1_DATA1_reserved_7_18 - reserved */ #define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_MASK) #define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_MASK) #define IOMUXD_USDHC1_DATA1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USDHC1_DATA1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USDHC1_DATA1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA1_WAKEUP_MASK_MASK) #define IOMUXD_USDHC1_DATA1_lp_config_MASK (0x1800000U) #define IOMUXD_USDHC1_DATA1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USDHC1_DATA1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA1_lp_config_MASK) #define IOMUXD_USDHC1_DATA1_sw_config_MASK (0x6000000U) #define IOMUXD_USDHC1_DATA1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USDHC1_DATA1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA1_sw_config_MASK) #define IOMUXD_USDHC1_DATA1_mux_mode_MASK (0x38000000U) #define IOMUXD_USDHC1_DATA1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.USDHC1.DATA1 * 0b001..CONN.NAND.RE_B * 0b010..ADMA.UART3.TX * 0b100..LSIO.GPIO4.IO26 */ #define IOMUXD_USDHC1_DATA1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA1_mux_mode_MASK) #define IOMUXD_USDHC1_DATA1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USDHC1_DATA1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USDHC1_DATA1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA1_update_pad_ctl_MASK) #define IOMUXD_USDHC1_DATA1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USDHC1_DATA1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USDHC1_DATA1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA1_update_mux_mode_MASK) /*! @} */ /*! @name USDHC1_DATA2 - USDHC1_DATA2 */ /*! @{ */ #define IOMUXD_USDHC1_DATA2_PDRV_MASK (0x1U) #define IOMUXD_USDHC1_DATA2_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_USDHC1_DATA2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA2_PDRV_MASK) #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_MASK (0x1EU) #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_SHIFT (1U) /*! USDHC1_DATA2_reserved_1_4 - reserved */ #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_MASK) #define IOMUXD_USDHC1_DATA2_PULL_MASK (0x60U) #define IOMUXD_USDHC1_DATA2_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_USDHC1_DATA2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_PULL_SHIFT)) & IOMUXD_USDHC1_DATA2_PULL_MASK) #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_SHIFT (7U) /*! USDHC1_DATA2_reserved_7_18 - reserved */ #define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_MASK) #define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_MASK) #define IOMUXD_USDHC1_DATA2_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USDHC1_DATA2_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USDHC1_DATA2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA2_WAKEUP_MASK_MASK) #define IOMUXD_USDHC1_DATA2_lp_config_MASK (0x1800000U) #define IOMUXD_USDHC1_DATA2_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USDHC1_DATA2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA2_lp_config_MASK) #define IOMUXD_USDHC1_DATA2_sw_config_MASK (0x6000000U) #define IOMUXD_USDHC1_DATA2_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USDHC1_DATA2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA2_sw_config_MASK) #define IOMUXD_USDHC1_DATA2_mux_mode_MASK (0x38000000U) #define IOMUXD_USDHC1_DATA2_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.USDHC1.DATA2 * 0b001..CONN.NAND.WE_B * 0b010..ADMA.UART3.CTS_B * 0b100..LSIO.GPIO4.IO27 */ #define IOMUXD_USDHC1_DATA2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA2_mux_mode_MASK) #define IOMUXD_USDHC1_DATA2_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USDHC1_DATA2_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USDHC1_DATA2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA2_update_pad_ctl_MASK) #define IOMUXD_USDHC1_DATA2_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USDHC1_DATA2_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USDHC1_DATA2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA2_update_mux_mode_MASK) /*! @} */ /*! @name USDHC1_DATA3 - USDHC1_DATA3 */ /*! @{ */ #define IOMUXD_USDHC1_DATA3_PDRV_MASK (0x1U) #define IOMUXD_USDHC1_DATA3_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_USDHC1_DATA3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA3_PDRV_MASK) #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_MASK (0x1EU) #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_SHIFT (1U) /*! USDHC1_DATA3_reserved_1_4 - reserved */ #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_MASK) #define IOMUXD_USDHC1_DATA3_PULL_MASK (0x60U) #define IOMUXD_USDHC1_DATA3_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_USDHC1_DATA3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_PULL_SHIFT)) & IOMUXD_USDHC1_DATA3_PULL_MASK) #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_SHIFT (7U) /*! USDHC1_DATA3_reserved_7_18 - reserved */ #define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_MASK) #define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_MASK) #define IOMUXD_USDHC1_DATA3_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_USDHC1_DATA3_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_USDHC1_DATA3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA3_WAKEUP_MASK_MASK) #define IOMUXD_USDHC1_DATA3_lp_config_MASK (0x1800000U) #define IOMUXD_USDHC1_DATA3_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_USDHC1_DATA3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA3_lp_config_MASK) #define IOMUXD_USDHC1_DATA3_sw_config_MASK (0x6000000U) #define IOMUXD_USDHC1_DATA3_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_USDHC1_DATA3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA3_sw_config_MASK) #define IOMUXD_USDHC1_DATA3_mux_mode_MASK (0x38000000U) #define IOMUXD_USDHC1_DATA3_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.USDHC1.DATA3 * 0b001..CONN.NAND.ALE * 0b010..ADMA.UART3.RTS_B * 0b100..LSIO.GPIO4.IO28 */ #define IOMUXD_USDHC1_DATA3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA3_mux_mode_MASK) #define IOMUXD_USDHC1_DATA3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_USDHC1_DATA3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_USDHC1_DATA3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA3_update_pad_ctl_MASK) #define IOMUXD_USDHC1_DATA3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_USDHC1_DATA3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_USDHC1_DATA3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA3_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_TXC - ENET0_RGMII_TXC */ /*! @{ */ #define IOMUXD_ENET0_RGMII_TXC_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_TXC_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_TXC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_PDRV_MASK) #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_TXC_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_TXC_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_TXC_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_TXC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_PULL_MASK) #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_TXC_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_TXC_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_TXC_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_TXC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_lp_config_MASK) #define IOMUXD_ENET0_RGMII_TXC_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_TXC_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_TXC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_sw_config_MASK) #define IOMUXD_ENET0_RGMII_TXC_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_TXC_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_TXC * 0b001..CONN.ENET0.RCLK50M_OUT * 0b010..CONN.ENET0.RCLK50M_IN * 0b011..CONN.NAND.CE1_B * 0b100..LSIO.GPIO4.IO29 */ #define IOMUXD_ENET0_RGMII_TXC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_TXC_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_TXC_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_TXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_TX_CTL - ENET0_RGMII_TX_CTL */ /*! @{ */ #define IOMUXD_ENET0_RGMII_TX_CTL_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_TX_CTL_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_TX_CTL_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_PDRV_MASK) #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_TX_CTL_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_TX_CTL_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_TX_CTL_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_TX_CTL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_PULL_MASK) #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_TX_CTL_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_TX_CTL_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_TX_CTL_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_TX_CTL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_lp_config_MASK) #define IOMUXD_ENET0_RGMII_TX_CTL_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_TX_CTL_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_TX_CTL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_sw_config_MASK) #define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_TX_CTL * 0b011..CONN.USDHC1.RESET_B * 0b100..LSIO.GPIO4.IO30 */ #define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_1_1 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_SHIFT (0U) /*! USDHC1_VSELECT - wakeup from USDHC1_VSELECT */ #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_SHIFT (1U) /*! iomuxd_group_1_1_reserved_1_1 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_SHIFT (2U) /*! USDHC1_WP - wakeup from USDHC1_WP */ #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_SHIFT (3U) /*! USDHC1_CD_B - wakeup from USDHC1_CD_B */ #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_MASK (0x30U) #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_SHIFT (4U) /*! iomuxd_group_1_1_reserved_4_5 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_SHIFT (6U) /*! USDHC1_CLK - wakeup from USDHC1_CLK */ #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_SHIFT (7U) /*! USDHC1_CMD - wakeup from USDHC1_CMD */ #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_SHIFT (8U) /*! USDHC1_DATA0 - wakeup from USDHC1_DATA0 */ #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_SHIFT (9U) /*! USDHC1_DATA1 - wakeup from USDHC1_DATA1 */ #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_SHIFT (10U) /*! USDHC1_DATA2 - wakeup from USDHC1_DATA2 */ #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_SHIFT (11U) /*! USDHC1_DATA3 - wakeup from USDHC1_DATA3 */ #define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_SHIFT (12U) /*! iomuxd_group_1_1_reserved_12_12 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_MASK (0x2000U) #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_SHIFT (13U) /*! ENET0_RGMII_TXC - wakeup from ENET0_RGMII_TXC */ #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_MASK (0x4000U) #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_SHIFT (14U) /*! ENET0_RGMII_TX_CTL - wakeup from ENET0_RGMII_TX_CTL */ #define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_MASK) #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_MASK (0xFFFF8000U) #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_SHIFT (15U) /*! iomuxd_group_1_1_reserved_15_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_MASK) /*! @} */ /*! @name ENET0_RGMII_TXD0 - ENET0_RGMII_TXD0 */ /*! @{ */ #define IOMUXD_ENET0_RGMII_TXD0_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_TXD0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_TXD0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_PDRV_MASK) #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_TXD0_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_TXD0_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_TXD0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_TXD0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_PULL_MASK) #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_TXD0_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_TXD0_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_TXD0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_TXD0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_lp_config_MASK) #define IOMUXD_ENET0_RGMII_TXD0_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_TXD0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_TXD0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_sw_config_MASK) #define IOMUXD_ENET0_RGMII_TXD0_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_TXD0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_TXD0 * 0b011..CONN.USDHC1.VSELECT * 0b100..LSIO.GPIO4.IO31 */ #define IOMUXD_ENET0_RGMII_TXD0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_TXD1 - ENET0_RGMII_TXD1 */ /*! @{ */ #define IOMUXD_ENET0_RGMII_TXD1_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_TXD1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_TXD1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_PDRV_MASK) #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_TXD1_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_TXD1_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_TXD1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_TXD1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_PULL_MASK) #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_TXD1_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_TXD1_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_TXD1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_TXD1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_lp_config_MASK) #define IOMUXD_ENET0_RGMII_TXD1_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_TXD1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_TXD1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_sw_config_MASK) #define IOMUXD_ENET0_RGMII_TXD1_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_TXD1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_TXD1 * 0b011..CONN.USDHC1.WP * 0b100..LSIO.GPIO5.IO00 */ #define IOMUXD_ENET0_RGMII_TXD1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_TXD2 - ENET0_RGMII_TXD2 */ /*! @{ */ #define IOMUXD_ENET0_RGMII_TXD2_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_TXD2_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_TXD2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_PDRV_MASK) #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_TXD2_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_TXD2_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_TXD2_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_TXD2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_PULL_MASK) #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_TXD2_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_TXD2_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_TXD2_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_TXD2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_lp_config_MASK) #define IOMUXD_ENET0_RGMII_TXD2_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_TXD2_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_TXD2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_sw_config_MASK) #define IOMUXD_ENET0_RGMII_TXD2_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_TXD2_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_TXD2 * 0b001..CONN.MLB.CLK * 0b010..CONN.NAND.CE0_B * 0b011..CONN.USDHC1.CD_B * 0b100..LSIO.GPIO5.IO01 */ #define IOMUXD_ENET0_RGMII_TXD2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_TXD3 - ENET0_RGMII_TXD3 */ /*! @{ */ #define IOMUXD_ENET0_RGMII_TXD3_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_TXD3_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_TXD3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_PDRV_MASK) #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_TXD3_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_TXD3_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_TXD3_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_TXD3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_PULL_MASK) #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_TXD3_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_TXD3_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_TXD3_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_TXD3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_lp_config_MASK) #define IOMUXD_ENET0_RGMII_TXD3_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_TXD3_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_TXD3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_sw_config_MASK) #define IOMUXD_ENET0_RGMII_TXD3_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_TXD3_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_TXD3 * 0b001..CONN.MLB.SIG * 0b010..CONN.NAND.RE_B * 0b100..LSIO.GPIO5.IO02 */ #define IOMUXD_ENET0_RGMII_TXD3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_SHIFT (4U) /*! PSW_OVR - PSW_OVR * 0b1..override output of voltage detector when using 2.5V IO operation * 0b0..selection coming from voltage detector cell for 1.8V or 3.3V IO operation */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..LAST * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_RXC - ENET0_RGMII_RXC */ /*! @{ */ #define IOMUXD_ENET0_RGMII_RXC_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_RXC_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_RXC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_PDRV_MASK) #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_RXC_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_RXC_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_RXC_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_RXC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_PULL_MASK) #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_RXC_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_RXC_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_RXC_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_RXC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_lp_config_MASK) #define IOMUXD_ENET0_RGMII_RXC_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_RXC_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_RXC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_sw_config_MASK) #define IOMUXD_ENET0_RGMII_RXC_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_RXC_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_RXC * 0b001..CONN.MLB.DATA * 0b010..CONN.NAND.WE_B * 0b011..CONN.USDHC1.CLK * 0b100..LSIO.GPIO5.IO03 */ #define IOMUXD_ENET0_RGMII_RXC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_RXC_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_RXC_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_RXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_RX_CTL - ENET0_RGMII_RX_CTL */ /*! @{ */ #define IOMUXD_ENET0_RGMII_RX_CTL_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_RX_CTL_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_RX_CTL_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_PDRV_MASK) #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_RX_CTL_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_RX_CTL_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_RX_CTL_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_RX_CTL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_PULL_MASK) #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_RX_CTL_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_RX_CTL_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_RX_CTL_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_RX_CTL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_lp_config_MASK) #define IOMUXD_ENET0_RGMII_RX_CTL_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_RX_CTL_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_RX_CTL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_sw_config_MASK) #define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_RX_CTL * 0b011..CONN.USDHC1.CMD * 0b100..LSIO.GPIO5.IO04 */ #define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_RXD0 - ENET0_RGMII_RXD0 */ /*! @{ */ #define IOMUXD_ENET0_RGMII_RXD0_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_RXD0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_RXD0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_PDRV_MASK) #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_RXD0_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_RXD0_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_RXD0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_RXD0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_PULL_MASK) #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_RXD0_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_RXD0_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_RXD0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_RXD0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_lp_config_MASK) #define IOMUXD_ENET0_RGMII_RXD0_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_RXD0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_RXD0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_sw_config_MASK) #define IOMUXD_ENET0_RGMII_RXD0_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_RXD0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_RXD0 * 0b011..CONN.USDHC1.DATA0 * 0b100..LSIO.GPIO5.IO05 */ #define IOMUXD_ENET0_RGMII_RXD0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_RXD1 - ENET0_RGMII_RXD1 */ /*! @{ */ #define IOMUXD_ENET0_RGMII_RXD1_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_RXD1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_RXD1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_PDRV_MASK) #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_RXD1_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_RXD1_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_RXD1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_RXD1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_PULL_MASK) #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_RXD1_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_RXD1_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_RXD1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_RXD1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_lp_config_MASK) #define IOMUXD_ENET0_RGMII_RXD1_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_RXD1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_RXD1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_sw_config_MASK) #define IOMUXD_ENET0_RGMII_RXD1_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_RXD1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_RXD1 * 0b011..CONN.USDHC1.DATA1 * 0b100..LSIO.GPIO5.IO06 */ #define IOMUXD_ENET0_RGMII_RXD1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_RXD2 - ENET0_RGMII_RXD2 */ /*! @{ */ #define IOMUXD_ENET0_RGMII_RXD2_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_RXD2_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_RXD2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_PDRV_MASK) #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_RXD2_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_RXD2_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_RXD2_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_RXD2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_PULL_MASK) #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_RXD2_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_RXD2_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_RXD2_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_RXD2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_lp_config_MASK) #define IOMUXD_ENET0_RGMII_RXD2_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_RXD2_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_RXD2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_sw_config_MASK) #define IOMUXD_ENET0_RGMII_RXD2_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_RXD2_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_RXD2 * 0b001..CONN.ENET0.RMII_RX_ER * 0b011..CONN.USDHC1.DATA2 * 0b100..LSIO.GPIO5.IO07 */ #define IOMUXD_ENET0_RGMII_RXD2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_RGMII_RXD3 - ENET0_RGMII_RXD3 */ /*! @{ */ #define IOMUXD_ENET0_RGMII_RXD3_PDRV_MASK (0x1U) #define IOMUXD_ENET0_RGMII_RXD3_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_RGMII_RXD3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_PDRV_MASK) #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_SHIFT (1U) /*! ENET0_RGMII_RXD3_reserved_1_4 - reserved */ #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_MASK) #define IOMUXD_ENET0_RGMII_RXD3_PULL_MASK (0x60U) #define IOMUXD_ENET0_RGMII_RXD3_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_RGMII_RXD3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_PULL_MASK) #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_SHIFT (7U) /*! ENET0_RGMII_RXD3_reserved_7_18 - reserved */ #define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_MASK) #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_RGMII_RXD3_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_RGMII_RXD3_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_RGMII_RXD3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_lp_config_MASK) #define IOMUXD_ENET0_RGMII_RXD3_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_RGMII_RXD3_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_RGMII_RXD3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_sw_config_MASK) #define IOMUXD_ENET0_RGMII_RXD3_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_RGMII_RXD3_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.RGMII_RXD3 * 0b010..CONN.NAND.ALE * 0b011..CONN.USDHC1.DATA3 * 0b100..LSIO.GPIO5.IO08 */ #define IOMUXD_ENET0_RGMII_RXD3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_mux_mode_MASK) #define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_MASK) #define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_SHIFT (4U) /*! PSW_OVR - PSW_OVR * 0b1..override output of voltage detector when using 2.5V IO operation * 0b0..selection coming from voltage detector cell for 1.8V or 3.3V IO operation */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..LAST * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_REFCLK_125M_25M - ENET0_REFCLK_125M_25M */ /*! @{ */ #define IOMUXD_ENET0_REFCLK_125M_25M_PDRV_MASK (0x1U) #define IOMUXD_ENET0_REFCLK_125M_25M_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_REFCLK_125M_25M_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_PDRV_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_PDRV_MASK) #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_SHIFT (1U) /*! ENET0_REFCLK_125M_25M_reserved_1_4 - reserved */ #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_MASK) #define IOMUXD_ENET0_REFCLK_125M_25M_PULL_MASK (0x60U) #define IOMUXD_ENET0_REFCLK_125M_25M_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_REFCLK_125M_25M_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_PULL_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_PULL_MASK) #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_SHIFT (7U) /*! ENET0_REFCLK_125M_25M_reserved_7_18 - reserved */ #define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_MASK) #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_REFCLK_125M_25M_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_REFCLK_125M_25M_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_REFCLK_125M_25M_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_lp_config_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_lp_config_MASK) #define IOMUXD_ENET0_REFCLK_125M_25M_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_REFCLK_125M_25M_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_REFCLK_125M_25M_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_sw_config_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_sw_config_MASK) #define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.REFCLK_125M_25M * 0b001..CONN.ENET0.PPS * 0b010..CONN.ENET1.PPS * 0b100..LSIO.GPIO5.IO09 */ #define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_MASK) #define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_MASK) #define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_1_2 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_SHIFT (0U) /*! ENET0_RGMII_TXD0 - wakeup from ENET0_RGMII_TXD0 */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_SHIFT (1U) /*! ENET0_RGMII_TXD1 - wakeup from ENET0_RGMII_TXD1 */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_SHIFT (2U) /*! ENET0_RGMII_TXD2 - wakeup from ENET0_RGMII_TXD2 */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_SHIFT (3U) /*! ENET0_RGMII_TXD3 - wakeup from ENET0_RGMII_TXD3 */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_SHIFT (4U) /*! iomuxd_group_1_2_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_SHIFT (5U) /*! ENET0_RGMII_RXC - wakeup from ENET0_RGMII_RXC */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_SHIFT (6U) /*! ENET0_RGMII_RX_CTL - wakeup from ENET0_RGMII_RX_CTL */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_SHIFT (7U) /*! ENET0_RGMII_RXD0 - wakeup from ENET0_RGMII_RXD0 */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_SHIFT (8U) /*! ENET0_RGMII_RXD1 - wakeup from ENET0_RGMII_RXD1 */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_SHIFT (9U) /*! ENET0_RGMII_RXD2 - wakeup from ENET0_RGMII_RXD2 */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_SHIFT (10U) /*! ENET0_RGMII_RXD3 - wakeup from ENET0_RGMII_RXD3 */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_SHIFT (11U) /*! iomuxd_group_1_2_reserved_11_11 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_SHIFT (12U) /*! ENET0_REFCLK_125M_25M - wakeup from ENET0_REFCLK_125M_25M */ #define IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_MASK) #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_MASK (0xFFFFE000U) #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_SHIFT (13U) /*! iomuxd_group_1_2_reserved_13_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_MASK) /*! @} */ /*! @name ENET0_MDIO - ENET0_MDIO */ /*! @{ */ #define IOMUXD_ENET0_MDIO_PDRV_MASK (0x1U) #define IOMUXD_ENET0_MDIO_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_MDIO_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_PDRV_SHIFT)) & IOMUXD_ENET0_MDIO_PDRV_MASK) #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_SHIFT (1U) /*! ENET0_MDIO_reserved_1_4 - reserved */ #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_SHIFT)) & IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_MASK) #define IOMUXD_ENET0_MDIO_PULL_MASK (0x60U) #define IOMUXD_ENET0_MDIO_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_MDIO_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_PULL_SHIFT)) & IOMUXD_ENET0_MDIO_PULL_MASK) #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_SHIFT (7U) /*! ENET0_MDIO_reserved_7_18 - reserved */ #define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_SHIFT)) & IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_MASK) #define IOMUXD_ENET0_MDIO_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_MDIO_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_MDIO_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_MDIO_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_MDIO_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_MDIO_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_MDIO_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_MDIO_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_MDIO_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_MDIO_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_MDIO_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_lp_config_SHIFT)) & IOMUXD_ENET0_MDIO_lp_config_MASK) #define IOMUXD_ENET0_MDIO_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_MDIO_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_MDIO_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_sw_config_SHIFT)) & IOMUXD_ENET0_MDIO_sw_config_MASK) #define IOMUXD_ENET0_MDIO_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_MDIO_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.MDIO * 0b001..ADMA.I2C3.SDA * 0b010..CONN.ENET1.MDIO * 0b100..LSIO.GPIO5.IO10 */ #define IOMUXD_ENET0_MDIO_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_mux_mode_SHIFT)) & IOMUXD_ENET0_MDIO_mux_mode_MASK) #define IOMUXD_ENET0_MDIO_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_MDIO_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_MDIO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_MDIO_update_pad_ctl_MASK) #define IOMUXD_ENET0_MDIO_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_MDIO_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_MDIO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_update_mux_mode_SHIFT)) & IOMUXD_ENET0_MDIO_update_mux_mode_MASK) /*! @} */ /*! @name ENET0_MDC - ENET0_MDC */ /*! @{ */ #define IOMUXD_ENET0_MDC_PDRV_MASK (0x1U) #define IOMUXD_ENET0_MDC_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ENET0_MDC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_PDRV_SHIFT)) & IOMUXD_ENET0_MDC_PDRV_MASK) #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_MASK (0x1EU) #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_SHIFT (1U) /*! ENET0_MDC_reserved_1_4 - reserved */ #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_MASK) #define IOMUXD_ENET0_MDC_PULL_MASK (0x60U) #define IOMUXD_ENET0_MDC_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ENET0_MDC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_PULL_SHIFT)) & IOMUXD_ENET0_MDC_PULL_MASK) #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_SHIFT (7U) /*! ENET0_MDC_reserved_7_18 - reserved */ #define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_MASK) #define IOMUXD_ENET0_MDC_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ENET0_MDC_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ENET0_MDC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_MDC_WAKEUP_CTRL_MASK) #define IOMUXD_ENET0_MDC_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ENET0_MDC_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ENET0_MDC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_MDC_WAKEUP_MASK_MASK) #define IOMUXD_ENET0_MDC_lp_config_MASK (0x1800000U) #define IOMUXD_ENET0_MDC_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ENET0_MDC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_lp_config_SHIFT)) & IOMUXD_ENET0_MDC_lp_config_MASK) #define IOMUXD_ENET0_MDC_sw_config_MASK (0x6000000U) #define IOMUXD_ENET0_MDC_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ENET0_MDC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_sw_config_SHIFT)) & IOMUXD_ENET0_MDC_sw_config_MASK) #define IOMUXD_ENET0_MDC_mux_mode_MASK (0x38000000U) #define IOMUXD_ENET0_MDC_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CONN.ENET0.MDC * 0b001..ADMA.I2C3.SCL * 0b010..CONN.ENET1.MDC * 0b100..LSIO.GPIO5.IO11 */ #define IOMUXD_ENET0_MDC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_mux_mode_SHIFT)) & IOMUXD_ENET0_MDC_mux_mode_MASK) #define IOMUXD_ENET0_MDC_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ENET0_MDC_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ENET0_MDC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_MDC_update_pad_ctl_MASK) #define IOMUXD_ENET0_MDC_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ENET0_MDC_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ENET0_MDC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_MDC_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_MASK) /*! @} */ /*! @name ESAI0_FSR - ESAI0_FSR */ /*! @{ */ #define IOMUXD_ESAI0_FSR_PDRV_MASK (0x1U) #define IOMUXD_ESAI0_FSR_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ESAI0_FSR_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_PDRV_SHIFT)) & IOMUXD_ESAI0_FSR_PDRV_MASK) #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_MASK (0x1EU) #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_SHIFT (1U) /*! ESAI0_FSR_reserved_1_4 - reserved */ #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_MASK) #define IOMUXD_ESAI0_FSR_PULL_MASK (0x60U) #define IOMUXD_ESAI0_FSR_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ESAI0_FSR_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_PULL_SHIFT)) & IOMUXD_ESAI0_FSR_PULL_MASK) #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_SHIFT (7U) /*! ESAI0_FSR_reserved_7_18 - reserved */ #define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_MASK) #define IOMUXD_ESAI0_FSR_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ESAI0_FSR_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ESAI0_FSR_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_FSR_WAKEUP_CTRL_MASK) #define IOMUXD_ESAI0_FSR_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ESAI0_FSR_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ESAI0_FSR_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_FSR_WAKEUP_MASK_MASK) #define IOMUXD_ESAI0_FSR_lp_config_MASK (0x1800000U) #define IOMUXD_ESAI0_FSR_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ESAI0_FSR_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_lp_config_SHIFT)) & IOMUXD_ESAI0_FSR_lp_config_MASK) #define IOMUXD_ESAI0_FSR_sw_config_MASK (0x6000000U) #define IOMUXD_ESAI0_FSR_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ESAI0_FSR_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_sw_config_SHIFT)) & IOMUXD_ESAI0_FSR_sw_config_MASK) #define IOMUXD_ESAI0_FSR_mux_mode_MASK (0x38000000U) #define IOMUXD_ESAI0_FSR_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ESAI0.FSR * 0b001..CONN.ENET1.RCLK50M_OUT * 0b010..ADMA.LCDIF.D00 * 0b011..CONN.ENET1.RGMII_TXC * 0b100..CONN.ENET1.RCLK50M_IN */ #define IOMUXD_ESAI0_FSR_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_mux_mode_SHIFT)) & IOMUXD_ESAI0_FSR_mux_mode_MASK) #define IOMUXD_ESAI0_FSR_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ESAI0_FSR_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ESAI0_FSR_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_FSR_update_pad_ctl_MASK) #define IOMUXD_ESAI0_FSR_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ESAI0_FSR_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ESAI0_FSR_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_FSR_update_mux_mode_MASK) /*! @} */ /*! @name ESAI0_FST - ESAI0_FST */ /*! @{ */ #define IOMUXD_ESAI0_FST_PDRV_MASK (0x1U) #define IOMUXD_ESAI0_FST_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ESAI0_FST_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_PDRV_SHIFT)) & IOMUXD_ESAI0_FST_PDRV_MASK) #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_MASK (0x1EU) #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_SHIFT (1U) /*! ESAI0_FST_reserved_1_4 - reserved */ #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_MASK) #define IOMUXD_ESAI0_FST_PULL_MASK (0x60U) #define IOMUXD_ESAI0_FST_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ESAI0_FST_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_PULL_SHIFT)) & IOMUXD_ESAI0_FST_PULL_MASK) #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_SHIFT (7U) /*! ESAI0_FST_reserved_7_18 - reserved */ #define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_MASK) #define IOMUXD_ESAI0_FST_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ESAI0_FST_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ESAI0_FST_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_FST_WAKEUP_CTRL_MASK) #define IOMUXD_ESAI0_FST_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ESAI0_FST_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ESAI0_FST_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_FST_WAKEUP_MASK_MASK) #define IOMUXD_ESAI0_FST_lp_config_MASK (0x1800000U) #define IOMUXD_ESAI0_FST_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ESAI0_FST_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_lp_config_SHIFT)) & IOMUXD_ESAI0_FST_lp_config_MASK) #define IOMUXD_ESAI0_FST_sw_config_MASK (0x6000000U) #define IOMUXD_ESAI0_FST_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ESAI0_FST_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_sw_config_SHIFT)) & IOMUXD_ESAI0_FST_sw_config_MASK) #define IOMUXD_ESAI0_FST_mux_mode_MASK (0x38000000U) #define IOMUXD_ESAI0_FST_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ESAI0.FST * 0b001..CONN.MLB.CLK * 0b010..ADMA.LCDIF.D01 * 0b011..CONN.ENET1.RGMII_TXD2 * 0b100..LSIO.GPIO0.IO01 */ #define IOMUXD_ESAI0_FST_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_mux_mode_SHIFT)) & IOMUXD_ESAI0_FST_mux_mode_MASK) #define IOMUXD_ESAI0_FST_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ESAI0_FST_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ESAI0_FST_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_FST_update_pad_ctl_MASK) #define IOMUXD_ESAI0_FST_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ESAI0_FST_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ESAI0_FST_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_FST_update_mux_mode_MASK) /*! @} */ /*! @name ESAI0_SCKR - ESAI0_SCKR */ /*! @{ */ #define IOMUXD_ESAI0_SCKR_PDRV_MASK (0x1U) #define IOMUXD_ESAI0_SCKR_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ESAI0_SCKR_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_PDRV_SHIFT)) & IOMUXD_ESAI0_SCKR_PDRV_MASK) #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_MASK (0x1EU) #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_SHIFT (1U) /*! ESAI0_SCKR_reserved_1_4 - reserved */ #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_MASK) #define IOMUXD_ESAI0_SCKR_PULL_MASK (0x60U) #define IOMUXD_ESAI0_SCKR_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ESAI0_SCKR_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_PULL_SHIFT)) & IOMUXD_ESAI0_SCKR_PULL_MASK) #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_SHIFT (7U) /*! ESAI0_SCKR_reserved_7_18 - reserved */ #define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_MASK) #define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_MASK) #define IOMUXD_ESAI0_SCKR_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ESAI0_SCKR_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ESAI0_SCKR_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_SCKR_WAKEUP_MASK_MASK) #define IOMUXD_ESAI0_SCKR_lp_config_MASK (0x1800000U) #define IOMUXD_ESAI0_SCKR_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ESAI0_SCKR_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_lp_config_SHIFT)) & IOMUXD_ESAI0_SCKR_lp_config_MASK) #define IOMUXD_ESAI0_SCKR_sw_config_MASK (0x6000000U) #define IOMUXD_ESAI0_SCKR_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ESAI0_SCKR_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_sw_config_SHIFT)) & IOMUXD_ESAI0_SCKR_sw_config_MASK) #define IOMUXD_ESAI0_SCKR_mux_mode_MASK (0x38000000U) #define IOMUXD_ESAI0_SCKR_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ESAI0.SCKR * 0b010..ADMA.LCDIF.D02 * 0b011..CONN.ENET1.RGMII_TX_CTL * 0b100..LSIO.GPIO0.IO02 */ #define IOMUXD_ESAI0_SCKR_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKR_mux_mode_MASK) #define IOMUXD_ESAI0_SCKR_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ESAI0_SCKR_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ESAI0_SCKR_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_SCKR_update_pad_ctl_MASK) #define IOMUXD_ESAI0_SCKR_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ESAI0_SCKR_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ESAI0_SCKR_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKR_update_mux_mode_MASK) /*! @} */ /*! @name ESAI0_SCKT - ESAI0_SCKT */ /*! @{ */ #define IOMUXD_ESAI0_SCKT_PDRV_MASK (0x1U) #define IOMUXD_ESAI0_SCKT_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ESAI0_SCKT_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_PDRV_SHIFT)) & IOMUXD_ESAI0_SCKT_PDRV_MASK) #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_MASK (0x1EU) #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_SHIFT (1U) /*! ESAI0_SCKT_reserved_1_4 - reserved */ #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_MASK) #define IOMUXD_ESAI0_SCKT_PULL_MASK (0x60U) #define IOMUXD_ESAI0_SCKT_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ESAI0_SCKT_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_PULL_SHIFT)) & IOMUXD_ESAI0_SCKT_PULL_MASK) #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_SHIFT (7U) /*! ESAI0_SCKT_reserved_7_18 - reserved */ #define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_MASK) #define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_MASK) #define IOMUXD_ESAI0_SCKT_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ESAI0_SCKT_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ESAI0_SCKT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_SCKT_WAKEUP_MASK_MASK) #define IOMUXD_ESAI0_SCKT_lp_config_MASK (0x1800000U) #define IOMUXD_ESAI0_SCKT_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ESAI0_SCKT_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_lp_config_SHIFT)) & IOMUXD_ESAI0_SCKT_lp_config_MASK) #define IOMUXD_ESAI0_SCKT_sw_config_MASK (0x6000000U) #define IOMUXD_ESAI0_SCKT_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ESAI0_SCKT_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_sw_config_SHIFT)) & IOMUXD_ESAI0_SCKT_sw_config_MASK) #define IOMUXD_ESAI0_SCKT_mux_mode_MASK (0x38000000U) #define IOMUXD_ESAI0_SCKT_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ESAI0.SCKT * 0b001..CONN.MLB.SIG * 0b010..ADMA.LCDIF.D03 * 0b011..CONN.ENET1.RGMII_TXD3 * 0b100..LSIO.GPIO0.IO03 */ #define IOMUXD_ESAI0_SCKT_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKT_mux_mode_MASK) #define IOMUXD_ESAI0_SCKT_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ESAI0_SCKT_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ESAI0_SCKT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_SCKT_update_pad_ctl_MASK) #define IOMUXD_ESAI0_SCKT_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ESAI0_SCKT_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ESAI0_SCKT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKT_update_mux_mode_MASK) /*! @} */ /*! @name ESAI0_TX0 - ESAI0_TX0 */ /*! @{ */ #define IOMUXD_ESAI0_TX0_PDRV_MASK (0x1U) #define IOMUXD_ESAI0_TX0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ESAI0_TX0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_PDRV_SHIFT)) & IOMUXD_ESAI0_TX0_PDRV_MASK) #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_MASK (0x1EU) #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_SHIFT (1U) /*! ESAI0_TX0_reserved_1_4 - reserved */ #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_MASK) #define IOMUXD_ESAI0_TX0_PULL_MASK (0x60U) #define IOMUXD_ESAI0_TX0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ESAI0_TX0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_PULL_SHIFT)) & IOMUXD_ESAI0_TX0_PULL_MASK) #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_SHIFT (7U) /*! ESAI0_TX0_reserved_7_18 - reserved */ #define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_MASK) #define IOMUXD_ESAI0_TX0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ESAI0_TX0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ESAI0_TX0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX0_WAKEUP_CTRL_MASK) #define IOMUXD_ESAI0_TX0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ESAI0_TX0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ESAI0_TX0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX0_WAKEUP_MASK_MASK) #define IOMUXD_ESAI0_TX0_lp_config_MASK (0x1800000U) #define IOMUXD_ESAI0_TX0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ESAI0_TX0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_lp_config_SHIFT)) & IOMUXD_ESAI0_TX0_lp_config_MASK) #define IOMUXD_ESAI0_TX0_sw_config_MASK (0x6000000U) #define IOMUXD_ESAI0_TX0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ESAI0_TX0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_sw_config_SHIFT)) & IOMUXD_ESAI0_TX0_sw_config_MASK) #define IOMUXD_ESAI0_TX0_mux_mode_MASK (0x38000000U) #define IOMUXD_ESAI0_TX0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ESAI0.TX0 * 0b001..CONN.MLB.DATA * 0b010..ADMA.LCDIF.D04 * 0b011..CONN.ENET1.RGMII_RXC * 0b100..LSIO.GPIO0.IO04 */ #define IOMUXD_ESAI0_TX0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX0_mux_mode_MASK) #define IOMUXD_ESAI0_TX0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ESAI0_TX0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ESAI0_TX0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX0_update_pad_ctl_MASK) #define IOMUXD_ESAI0_TX0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ESAI0_TX0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ESAI0_TX0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX0_update_mux_mode_MASK) /*! @} */ /*! @name ESAI0_TX1 - ESAI0_TX1 */ /*! @{ */ #define IOMUXD_ESAI0_TX1_PDRV_MASK (0x1U) #define IOMUXD_ESAI0_TX1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ESAI0_TX1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_PDRV_SHIFT)) & IOMUXD_ESAI0_TX1_PDRV_MASK) #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_MASK (0x1EU) #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_SHIFT (1U) /*! ESAI0_TX1_reserved_1_4 - reserved */ #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_MASK) #define IOMUXD_ESAI0_TX1_PULL_MASK (0x60U) #define IOMUXD_ESAI0_TX1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ESAI0_TX1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_PULL_SHIFT)) & IOMUXD_ESAI0_TX1_PULL_MASK) #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_SHIFT (7U) /*! ESAI0_TX1_reserved_7_18 - reserved */ #define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_MASK) #define IOMUXD_ESAI0_TX1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ESAI0_TX1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ESAI0_TX1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX1_WAKEUP_CTRL_MASK) #define IOMUXD_ESAI0_TX1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ESAI0_TX1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ESAI0_TX1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX1_WAKEUP_MASK_MASK) #define IOMUXD_ESAI0_TX1_lp_config_MASK (0x1800000U) #define IOMUXD_ESAI0_TX1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ESAI0_TX1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_lp_config_SHIFT)) & IOMUXD_ESAI0_TX1_lp_config_MASK) #define IOMUXD_ESAI0_TX1_sw_config_MASK (0x6000000U) #define IOMUXD_ESAI0_TX1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ESAI0_TX1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_sw_config_SHIFT)) & IOMUXD_ESAI0_TX1_sw_config_MASK) #define IOMUXD_ESAI0_TX1_mux_mode_MASK (0x38000000U) #define IOMUXD_ESAI0_TX1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ESAI0.TX1 * 0b010..ADMA.LCDIF.D05 * 0b011..CONN.ENET1.RGMII_RXD3 * 0b100..LSIO.GPIO0.IO05 */ #define IOMUXD_ESAI0_TX1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX1_mux_mode_MASK) #define IOMUXD_ESAI0_TX1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ESAI0_TX1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ESAI0_TX1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX1_update_pad_ctl_MASK) #define IOMUXD_ESAI0_TX1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ESAI0_TX1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ESAI0_TX1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX1_update_mux_mode_MASK) /*! @} */ /*! @name ESAI0_TX2_RX3 - ESAI0_TX2_RX3 */ /*! @{ */ #define IOMUXD_ESAI0_TX2_RX3_PDRV_MASK (0x1U) #define IOMUXD_ESAI0_TX2_RX3_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ESAI0_TX2_RX3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_PDRV_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_PDRV_MASK) #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_MASK (0x1EU) #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_SHIFT (1U) /*! ESAI0_TX2_RX3_reserved_1_4 - reserved */ #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_MASK) #define IOMUXD_ESAI0_TX2_RX3_PULL_MASK (0x60U) #define IOMUXD_ESAI0_TX2_RX3_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ESAI0_TX2_RX3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_PULL_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_PULL_MASK) #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_SHIFT (7U) /*! ESAI0_TX2_RX3_reserved_7_18 - reserved */ #define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_MASK) #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_MASK) #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_MASK) #define IOMUXD_ESAI0_TX2_RX3_lp_config_MASK (0x1800000U) #define IOMUXD_ESAI0_TX2_RX3_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ESAI0_TX2_RX3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_lp_config_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_lp_config_MASK) #define IOMUXD_ESAI0_TX2_RX3_sw_config_MASK (0x6000000U) #define IOMUXD_ESAI0_TX2_RX3_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ESAI0_TX2_RX3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_sw_config_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_sw_config_MASK) #define IOMUXD_ESAI0_TX2_RX3_mux_mode_MASK (0x38000000U) #define IOMUXD_ESAI0_TX2_RX3_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ESAI0.TX2_RX3 * 0b001..CONN.ENET1.RMII_RX_ER * 0b010..ADMA.LCDIF.D06 * 0b011..CONN.ENET1.RGMII_RXD2 * 0b100..LSIO.GPIO0.IO06 */ #define IOMUXD_ESAI0_TX2_RX3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_mux_mode_MASK) #define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_MASK) #define IOMUXD_ESAI0_TX2_RX3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ESAI0_TX2_RX3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ESAI0_TX2_RX3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_update_mux_mode_MASK) /*! @} */ /*! @name ESAI0_TX3_RX2 - ESAI0_TX3_RX2 */ /*! @{ */ #define IOMUXD_ESAI0_TX3_RX2_PDRV_MASK (0x1U) #define IOMUXD_ESAI0_TX3_RX2_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ESAI0_TX3_RX2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_PDRV_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_PDRV_MASK) #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_MASK (0x1EU) #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_SHIFT (1U) /*! ESAI0_TX3_RX2_reserved_1_4 - reserved */ #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_MASK) #define IOMUXD_ESAI0_TX3_RX2_PULL_MASK (0x60U) #define IOMUXD_ESAI0_TX3_RX2_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ESAI0_TX3_RX2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_PULL_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_PULL_MASK) #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_SHIFT (7U) /*! ESAI0_TX3_RX2_reserved_7_18 - reserved */ #define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_MASK) #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_MASK) #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_MASK) #define IOMUXD_ESAI0_TX3_RX2_lp_config_MASK (0x1800000U) #define IOMUXD_ESAI0_TX3_RX2_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ESAI0_TX3_RX2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_lp_config_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_lp_config_MASK) #define IOMUXD_ESAI0_TX3_RX2_sw_config_MASK (0x6000000U) #define IOMUXD_ESAI0_TX3_RX2_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ESAI0_TX3_RX2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_sw_config_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_sw_config_MASK) #define IOMUXD_ESAI0_TX3_RX2_mux_mode_MASK (0x38000000U) #define IOMUXD_ESAI0_TX3_RX2_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ESAI0.TX3_RX2 * 0b010..ADMA.LCDIF.D07 * 0b011..CONN.ENET1.RGMII_RXD1 * 0b100..LSIO.GPIO0.IO07 */ #define IOMUXD_ESAI0_TX3_RX2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_mux_mode_MASK) #define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_MASK) #define IOMUXD_ESAI0_TX3_RX2_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ESAI0_TX3_RX2_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ESAI0_TX3_RX2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_update_mux_mode_MASK) /*! @} */ /*! @name ESAI0_TX4_RX1 - ESAI0_TX4_RX1 */ /*! @{ */ #define IOMUXD_ESAI0_TX4_RX1_PDRV_MASK (0x1U) #define IOMUXD_ESAI0_TX4_RX1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ESAI0_TX4_RX1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_PDRV_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_PDRV_MASK) #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_MASK (0x1EU) #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_SHIFT (1U) /*! ESAI0_TX4_RX1_reserved_1_4 - reserved */ #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_MASK) #define IOMUXD_ESAI0_TX4_RX1_PULL_MASK (0x60U) #define IOMUXD_ESAI0_TX4_RX1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ESAI0_TX4_RX1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_PULL_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_PULL_MASK) #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_SHIFT (7U) /*! ESAI0_TX4_RX1_reserved_7_18 - reserved */ #define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_MASK) #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_MASK) #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_MASK) #define IOMUXD_ESAI0_TX4_RX1_lp_config_MASK (0x1800000U) #define IOMUXD_ESAI0_TX4_RX1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ESAI0_TX4_RX1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_lp_config_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_lp_config_MASK) #define IOMUXD_ESAI0_TX4_RX1_sw_config_MASK (0x6000000U) #define IOMUXD_ESAI0_TX4_RX1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ESAI0_TX4_RX1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_sw_config_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_sw_config_MASK) #define IOMUXD_ESAI0_TX4_RX1_mux_mode_MASK (0x38000000U) #define IOMUXD_ESAI0_TX4_RX1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ESAI0.TX4_RX1 * 0b010..ADMA.LCDIF.D08 * 0b011..CONN.ENET1.RGMII_TXD0 * 0b100..LSIO.GPIO0.IO08 */ #define IOMUXD_ESAI0_TX4_RX1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_mux_mode_MASK) #define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_MASK) #define IOMUXD_ESAI0_TX4_RX1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ESAI0_TX4_RX1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ESAI0_TX4_RX1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_update_mux_mode_MASK) /*! @} */ /*! @name ESAI0_TX5_RX0 - ESAI0_TX5_RX0 */ /*! @{ */ #define IOMUXD_ESAI0_TX5_RX0_PDRV_MASK (0x1U) #define IOMUXD_ESAI0_TX5_RX0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_ESAI0_TX5_RX0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_PDRV_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_PDRV_MASK) #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_MASK (0x1EU) #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_SHIFT (1U) /*! ESAI0_TX5_RX0_reserved_1_4 - reserved */ #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_MASK) #define IOMUXD_ESAI0_TX5_RX0_PULL_MASK (0x60U) #define IOMUXD_ESAI0_TX5_RX0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_ESAI0_TX5_RX0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_PULL_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_PULL_MASK) #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_SHIFT (7U) /*! ESAI0_TX5_RX0_reserved_7_18 - reserved */ #define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_MASK) #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_MASK) #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_MASK) #define IOMUXD_ESAI0_TX5_RX0_lp_config_MASK (0x1800000U) #define IOMUXD_ESAI0_TX5_RX0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ESAI0_TX5_RX0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_lp_config_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_lp_config_MASK) #define IOMUXD_ESAI0_TX5_RX0_sw_config_MASK (0x6000000U) #define IOMUXD_ESAI0_TX5_RX0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ESAI0_TX5_RX0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_sw_config_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_sw_config_MASK) #define IOMUXD_ESAI0_TX5_RX0_mux_mode_MASK (0x38000000U) #define IOMUXD_ESAI0_TX5_RX0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ESAI0.TX5_RX0 * 0b010..ADMA.LCDIF.D09 * 0b011..CONN.ENET1.RGMII_TXD1 * 0b100..LSIO.GPIO0.IO09 */ #define IOMUXD_ESAI0_TX5_RX0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_mux_mode_MASK) #define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_MASK) #define IOMUXD_ESAI0_TX5_RX0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ESAI0_TX5_RX0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ESAI0_TX5_RX0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_update_mux_mode_MASK) /*! @} */ /*! @name SPDIF0_RX - SPDIF0_RX */ /*! @{ */ #define IOMUXD_SPDIF0_RX_PDRV_MASK (0x1U) #define IOMUXD_SPDIF0_RX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPDIF0_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_PDRV_SHIFT)) & IOMUXD_SPDIF0_RX_PDRV_MASK) #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_SHIFT (1U) /*! SPDIF0_RX_reserved_1_4 - reserved */ #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_MASK) #define IOMUXD_SPDIF0_RX_PULL_MASK (0x60U) #define IOMUXD_SPDIF0_RX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPDIF0_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_PULL_SHIFT)) & IOMUXD_SPDIF0_RX_PULL_MASK) #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_SHIFT (7U) /*! SPDIF0_RX_reserved_7_18 - reserved */ #define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_MASK) #define IOMUXD_SPDIF0_RX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPDIF0_RX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPDIF0_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_RX_WAKEUP_CTRL_MASK) #define IOMUXD_SPDIF0_RX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPDIF0_RX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPDIF0_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_RX_WAKEUP_MASK_MASK) #define IOMUXD_SPDIF0_RX_lp_config_MASK (0x1800000U) #define IOMUXD_SPDIF0_RX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPDIF0_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_lp_config_SHIFT)) & IOMUXD_SPDIF0_RX_lp_config_MASK) #define IOMUXD_SPDIF0_RX_sw_config_MASK (0x6000000U) #define IOMUXD_SPDIF0_RX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPDIF0_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_sw_config_SHIFT)) & IOMUXD_SPDIF0_RX_sw_config_MASK) #define IOMUXD_SPDIF0_RX_mux_mode_MASK (0x38000000U) #define IOMUXD_SPDIF0_RX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPDIF0.RX * 0b001..ADMA.MQS.R * 0b010..ADMA.LCDIF.D10 * 0b011..CONN.ENET1.RGMII_RXD0 * 0b100..LSIO.GPIO0.IO10 */ #define IOMUXD_SPDIF0_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_mux_mode_SHIFT)) & IOMUXD_SPDIF0_RX_mux_mode_MASK) #define IOMUXD_SPDIF0_RX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPDIF0_RX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPDIF0_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_RX_update_pad_ctl_MASK) #define IOMUXD_SPDIF0_RX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPDIF0_RX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPDIF0_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_RX_update_mux_mode_MASK) /*! @} */ /*! @name SPDIF0_TX - SPDIF0_TX */ /*! @{ */ #define IOMUXD_SPDIF0_TX_PDRV_MASK (0x1U) #define IOMUXD_SPDIF0_TX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPDIF0_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_PDRV_SHIFT)) & IOMUXD_SPDIF0_TX_PDRV_MASK) #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_SHIFT (1U) /*! SPDIF0_TX_reserved_1_4 - reserved */ #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_MASK) #define IOMUXD_SPDIF0_TX_PULL_MASK (0x60U) #define IOMUXD_SPDIF0_TX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPDIF0_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_PULL_SHIFT)) & IOMUXD_SPDIF0_TX_PULL_MASK) #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_SHIFT (7U) /*! SPDIF0_TX_reserved_7_18 - reserved */ #define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_MASK) #define IOMUXD_SPDIF0_TX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPDIF0_TX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPDIF0_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_TX_WAKEUP_CTRL_MASK) #define IOMUXD_SPDIF0_TX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPDIF0_TX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPDIF0_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_TX_WAKEUP_MASK_MASK) #define IOMUXD_SPDIF0_TX_lp_config_MASK (0x1800000U) #define IOMUXD_SPDIF0_TX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPDIF0_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_lp_config_SHIFT)) & IOMUXD_SPDIF0_TX_lp_config_MASK) #define IOMUXD_SPDIF0_TX_sw_config_MASK (0x6000000U) #define IOMUXD_SPDIF0_TX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPDIF0_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_sw_config_SHIFT)) & IOMUXD_SPDIF0_TX_sw_config_MASK) #define IOMUXD_SPDIF0_TX_mux_mode_MASK (0x38000000U) #define IOMUXD_SPDIF0_TX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPDIF0.TX * 0b001..ADMA.MQS.L * 0b010..ADMA.LCDIF.D11 * 0b011..CONN.ENET1.RGMII_RX_CTL * 0b100..LSIO.GPIO0.IO11 */ #define IOMUXD_SPDIF0_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_mux_mode_SHIFT)) & IOMUXD_SPDIF0_TX_mux_mode_MASK) #define IOMUXD_SPDIF0_TX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPDIF0_TX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPDIF0_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_TX_update_pad_ctl_MASK) #define IOMUXD_SPDIF0_TX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPDIF0_TX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPDIF0_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_TX_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_1_3 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_SHIFT (0U) /*! ENET0_MDIO - wakeup from ENET0_MDIO */ #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_SHIFT (1U) /*! ENET0_MDC - wakeup from ENET0_MDC */ #define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_SHIFT (2U) /*! iomuxd_group_1_3_reserved_2_2 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_SHIFT (3U) /*! ESAI0_FSR - wakeup from ESAI0_FSR */ #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_SHIFT (4U) /*! ESAI0_FST - wakeup from ESAI0_FST */ #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_SHIFT (5U) /*! ESAI0_SCKR - wakeup from ESAI0_SCKR */ #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_SHIFT (6U) /*! ESAI0_SCKT - wakeup from ESAI0_SCKT */ #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_SHIFT (7U) /*! ESAI0_TX0 - wakeup from ESAI0_TX0 */ #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_SHIFT (8U) /*! ESAI0_TX1 - wakeup from ESAI0_TX1 */ #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_SHIFT (9U) /*! ESAI0_TX2_RX3 - wakeup from ESAI0_TX2_RX3 */ #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_SHIFT (10U) /*! ESAI0_TX3_RX2 - wakeup from ESAI0_TX3_RX2 */ #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_SHIFT (11U) /*! ESAI0_TX4_RX1 - wakeup from ESAI0_TX4_RX1 */ #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_SHIFT (12U) /*! ESAI0_TX5_RX0 - wakeup from ESAI0_TX5_RX0 */ #define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_MASK (0x2000U) #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_SHIFT (13U) /*! SPDIF0_RX - wakeup from SPDIF0_RX */ #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_MASK (0x4000U) #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_SHIFT (14U) /*! SPDIF0_TX - wakeup from SPDIF0_TX */ #define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_MASK) #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_MASK (0xFFFF8000U) #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_SHIFT (15U) /*! iomuxd_group_1_3_reserved_15_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_MASK) /*! @} */ /*! @name SPDIF0_EXT_CLK - SPDIF0_EXT_CLK */ /*! @{ */ #define IOMUXD_SPDIF0_EXT_CLK_PDRV_MASK (0x1U) #define IOMUXD_SPDIF0_EXT_CLK_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPDIF0_EXT_CLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_PDRV_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_PDRV_MASK) #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_SHIFT (1U) /*! SPDIF0_EXT_CLK_reserved_1_4 - reserved */ #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_MASK) #define IOMUXD_SPDIF0_EXT_CLK_PULL_MASK (0x60U) #define IOMUXD_SPDIF0_EXT_CLK_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPDIF0_EXT_CLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_PULL_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_PULL_MASK) #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_SHIFT (7U) /*! SPDIF0_EXT_CLK_reserved_7_18 - reserved */ #define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_MASK) #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_MASK) #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_MASK) #define IOMUXD_SPDIF0_EXT_CLK_lp_config_MASK (0x1800000U) #define IOMUXD_SPDIF0_EXT_CLK_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPDIF0_EXT_CLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_lp_config_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_lp_config_MASK) #define IOMUXD_SPDIF0_EXT_CLK_sw_config_MASK (0x6000000U) #define IOMUXD_SPDIF0_EXT_CLK_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPDIF0_EXT_CLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_sw_config_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_sw_config_MASK) #define IOMUXD_SPDIF0_EXT_CLK_mux_mode_MASK (0x38000000U) #define IOMUXD_SPDIF0_EXT_CLK_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPDIF0.EXT_CLK * 0b010..ADMA.LCDIF.D12 * 0b011..CONN.ENET1.REFCLK_125M_25M * 0b100..LSIO.GPIO0.IO12 */ #define IOMUXD_SPDIF0_EXT_CLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_mux_mode_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_mux_mode_MASK) #define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_MASK) #define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_SHIFT (4U) /*! PSW_OVR - PSW_OVR * 0b1..override output of voltage detector when using 2.5V IO operation * 0b0..selection coming from voltage detector cell for 1.8V or 3.3V IO operation */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..LAST * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_MASK) /*! @} */ /*! @name SPI3_SCK - SPI3_SCK */ /*! @{ */ #define IOMUXD_SPI3_SCK_PDRV_MASK (0x1U) #define IOMUXD_SPI3_SCK_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI3_SCK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_PDRV_SHIFT)) & IOMUXD_SPI3_SCK_PDRV_MASK) #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_SHIFT (1U) /*! SPI3_SCK_reserved_1_4 - reserved */ #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_MASK) #define IOMUXD_SPI3_SCK_PULL_MASK (0x60U) #define IOMUXD_SPI3_SCK_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI3_SCK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_PULL_SHIFT)) & IOMUXD_SPI3_SCK_PULL_MASK) #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_SHIFT (7U) /*! SPI3_SCK_reserved_7_18 - reserved */ #define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_MASK) #define IOMUXD_SPI3_SCK_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI3_SCK_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI3_SCK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SCK_WAKEUP_CTRL_MASK) #define IOMUXD_SPI3_SCK_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI3_SCK_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI3_SCK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SCK_WAKEUP_MASK_MASK) #define IOMUXD_SPI3_SCK_lp_config_MASK (0x1800000U) #define IOMUXD_SPI3_SCK_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI3_SCK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_lp_config_SHIFT)) & IOMUXD_SPI3_SCK_lp_config_MASK) #define IOMUXD_SPI3_SCK_sw_config_MASK (0x6000000U) #define IOMUXD_SPI3_SCK_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI3_SCK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_sw_config_SHIFT)) & IOMUXD_SPI3_SCK_sw_config_MASK) #define IOMUXD_SPI3_SCK_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI3_SCK_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI3.SCK * 0b010..ADMA.LCDIF.D13 * 0b100..LSIO.GPIO0.IO13 */ #define IOMUXD_SPI3_SCK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_mux_mode_SHIFT)) & IOMUXD_SPI3_SCK_mux_mode_MASK) #define IOMUXD_SPI3_SCK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI3_SCK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI3_SCK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SCK_update_pad_ctl_MASK) #define IOMUXD_SPI3_SCK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI3_SCK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI3_SCK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SCK_update_mux_mode_MASK) /*! @} */ /*! @name SPI3_SDO - SPI3_SDO */ /*! @{ */ #define IOMUXD_SPI3_SDO_PDRV_MASK (0x1U) #define IOMUXD_SPI3_SDO_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI3_SDO_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_PDRV_SHIFT)) & IOMUXD_SPI3_SDO_PDRV_MASK) #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_SHIFT (1U) /*! SPI3_SDO_reserved_1_4 - reserved */ #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_MASK) #define IOMUXD_SPI3_SDO_PULL_MASK (0x60U) #define IOMUXD_SPI3_SDO_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI3_SDO_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_PULL_SHIFT)) & IOMUXD_SPI3_SDO_PULL_MASK) #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_SHIFT (7U) /*! SPI3_SDO_reserved_7_18 - reserved */ #define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_MASK) #define IOMUXD_SPI3_SDO_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI3_SDO_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI3_SDO_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SDO_WAKEUP_CTRL_MASK) #define IOMUXD_SPI3_SDO_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI3_SDO_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI3_SDO_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SDO_WAKEUP_MASK_MASK) #define IOMUXD_SPI3_SDO_lp_config_MASK (0x1800000U) #define IOMUXD_SPI3_SDO_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI3_SDO_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_lp_config_SHIFT)) & IOMUXD_SPI3_SDO_lp_config_MASK) #define IOMUXD_SPI3_SDO_sw_config_MASK (0x6000000U) #define IOMUXD_SPI3_SDO_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI3_SDO_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_sw_config_SHIFT)) & IOMUXD_SPI3_SDO_sw_config_MASK) #define IOMUXD_SPI3_SDO_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI3_SDO_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI3.SDO * 0b010..ADMA.LCDIF.D14 * 0b100..LSIO.GPIO0.IO14 */ #define IOMUXD_SPI3_SDO_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_mux_mode_SHIFT)) & IOMUXD_SPI3_SDO_mux_mode_MASK) #define IOMUXD_SPI3_SDO_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI3_SDO_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI3_SDO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SDO_update_pad_ctl_MASK) #define IOMUXD_SPI3_SDO_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI3_SDO_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI3_SDO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SDO_update_mux_mode_MASK) /*! @} */ /*! @name SPI3_SDI - SPI3_SDI */ /*! @{ */ #define IOMUXD_SPI3_SDI_PDRV_MASK (0x1U) #define IOMUXD_SPI3_SDI_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI3_SDI_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_PDRV_SHIFT)) & IOMUXD_SPI3_SDI_PDRV_MASK) #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_SHIFT (1U) /*! SPI3_SDI_reserved_1_4 - reserved */ #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_MASK) #define IOMUXD_SPI3_SDI_PULL_MASK (0x60U) #define IOMUXD_SPI3_SDI_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI3_SDI_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_PULL_SHIFT)) & IOMUXD_SPI3_SDI_PULL_MASK) #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_SHIFT (7U) /*! SPI3_SDI_reserved_7_18 - reserved */ #define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_MASK) #define IOMUXD_SPI3_SDI_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI3_SDI_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI3_SDI_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SDI_WAKEUP_CTRL_MASK) #define IOMUXD_SPI3_SDI_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI3_SDI_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI3_SDI_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SDI_WAKEUP_MASK_MASK) #define IOMUXD_SPI3_SDI_lp_config_MASK (0x1800000U) #define IOMUXD_SPI3_SDI_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI3_SDI_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_lp_config_SHIFT)) & IOMUXD_SPI3_SDI_lp_config_MASK) #define IOMUXD_SPI3_SDI_sw_config_MASK (0x6000000U) #define IOMUXD_SPI3_SDI_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI3_SDI_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_sw_config_SHIFT)) & IOMUXD_SPI3_SDI_sw_config_MASK) #define IOMUXD_SPI3_SDI_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI3_SDI_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI3.SDI * 0b010..ADMA.LCDIF.D15 * 0b100..LSIO.GPIO0.IO15 */ #define IOMUXD_SPI3_SDI_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_mux_mode_SHIFT)) & IOMUXD_SPI3_SDI_mux_mode_MASK) #define IOMUXD_SPI3_SDI_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI3_SDI_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI3_SDI_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SDI_update_pad_ctl_MASK) #define IOMUXD_SPI3_SDI_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI3_SDI_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI3_SDI_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SDI_update_mux_mode_MASK) /*! @} */ /*! @name SPI3_CS0 - SPI3_CS0 */ /*! @{ */ #define IOMUXD_SPI3_CS0_PDRV_MASK (0x1U) #define IOMUXD_SPI3_CS0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI3_CS0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_PDRV_SHIFT)) & IOMUXD_SPI3_CS0_PDRV_MASK) #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_SHIFT (1U) /*! SPI3_CS0_reserved_1_4 - reserved */ #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_MASK) #define IOMUXD_SPI3_CS0_PULL_MASK (0x60U) #define IOMUXD_SPI3_CS0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI3_CS0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_PULL_SHIFT)) & IOMUXD_SPI3_CS0_PULL_MASK) #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_SHIFT (7U) /*! SPI3_CS0_reserved_7_18 - reserved */ #define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_MASK) #define IOMUXD_SPI3_CS0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI3_CS0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI3_CS0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_CS0_WAKEUP_CTRL_MASK) #define IOMUXD_SPI3_CS0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI3_CS0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI3_CS0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_CS0_WAKEUP_MASK_MASK) #define IOMUXD_SPI3_CS0_lp_config_MASK (0x1800000U) #define IOMUXD_SPI3_CS0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI3_CS0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_lp_config_SHIFT)) & IOMUXD_SPI3_CS0_lp_config_MASK) #define IOMUXD_SPI3_CS0_sw_config_MASK (0x6000000U) #define IOMUXD_SPI3_CS0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI3_CS0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_sw_config_SHIFT)) & IOMUXD_SPI3_CS0_sw_config_MASK) #define IOMUXD_SPI3_CS0_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI3_CS0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI3.CS0 * 0b001..ADMA.ACM.MCLK_OUT1 * 0b010..ADMA.LCDIF.HSYNC * 0b100..LSIO.GPIO0.IO16 */ #define IOMUXD_SPI3_CS0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_mux_mode_SHIFT)) & IOMUXD_SPI3_CS0_mux_mode_MASK) #define IOMUXD_SPI3_CS0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI3_CS0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI3_CS0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_CS0_update_pad_ctl_MASK) #define IOMUXD_SPI3_CS0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI3_CS0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI3_CS0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI3_CS0_update_mux_mode_MASK) /*! @} */ /*! @name SPI3_CS1 - SPI3_CS1 */ /*! @{ */ #define IOMUXD_SPI3_CS1_PDRV_MASK (0x1U) #define IOMUXD_SPI3_CS1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI3_CS1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_PDRV_SHIFT)) & IOMUXD_SPI3_CS1_PDRV_MASK) #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_SHIFT (1U) /*! SPI3_CS1_reserved_1_4 - reserved */ #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_SHIFT)) & IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_MASK) #define IOMUXD_SPI3_CS1_PULL_MASK (0x60U) #define IOMUXD_SPI3_CS1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI3_CS1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_PULL_SHIFT)) & IOMUXD_SPI3_CS1_PULL_MASK) #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_SHIFT (7U) /*! SPI3_CS1_reserved_7_18 - reserved */ #define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_SHIFT)) & IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_MASK) #define IOMUXD_SPI3_CS1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI3_CS1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI3_CS1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_CS1_WAKEUP_CTRL_MASK) #define IOMUXD_SPI3_CS1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI3_CS1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI3_CS1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_CS1_WAKEUP_MASK_MASK) #define IOMUXD_SPI3_CS1_lp_config_MASK (0x1800000U) #define IOMUXD_SPI3_CS1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI3_CS1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_lp_config_SHIFT)) & IOMUXD_SPI3_CS1_lp_config_MASK) #define IOMUXD_SPI3_CS1_sw_config_MASK (0x6000000U) #define IOMUXD_SPI3_CS1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI3_CS1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_sw_config_SHIFT)) & IOMUXD_SPI3_CS1_sw_config_MASK) #define IOMUXD_SPI3_CS1_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI3_CS1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI3.CS1 * 0b001..ADMA.I2C3.SCL * 0b010..ADMA.LCDIF.RESET * 0b011..ADMA.SPI2.CS0 * 0b100..ADMA.LCDIF.D16 */ #define IOMUXD_SPI3_CS1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_mux_mode_SHIFT)) & IOMUXD_SPI3_CS1_mux_mode_MASK) #define IOMUXD_SPI3_CS1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI3_CS1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI3_CS1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_CS1_update_pad_ctl_MASK) #define IOMUXD_SPI3_CS1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI3_CS1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI3_CS1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_update_mux_mode_SHIFT)) & IOMUXD_SPI3_CS1_update_mux_mode_MASK) /*! @} */ /*! @name MCLK_IN1 - MCLK_IN1 */ /*! @{ */ #define IOMUXD_MCLK_IN1_PDRV_MASK (0x1U) #define IOMUXD_MCLK_IN1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MCLK_IN1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_PDRV_SHIFT)) & IOMUXD_MCLK_IN1_PDRV_MASK) #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_MASK (0x1EU) #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_SHIFT (1U) /*! MCLK_IN1_reserved_1_4 - reserved */ #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_SHIFT)) & IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_MASK) #define IOMUXD_MCLK_IN1_PULL_MASK (0x60U) #define IOMUXD_MCLK_IN1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MCLK_IN1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_PULL_SHIFT)) & IOMUXD_MCLK_IN1_PULL_MASK) #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_SHIFT (7U) /*! MCLK_IN1_reserved_7_18 - reserved */ #define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_SHIFT)) & IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_MASK) #define IOMUXD_MCLK_IN1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MCLK_IN1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MCLK_IN1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_IN1_WAKEUP_CTRL_MASK) #define IOMUXD_MCLK_IN1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MCLK_IN1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MCLK_IN1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_IN1_WAKEUP_MASK_MASK) #define IOMUXD_MCLK_IN1_lp_config_MASK (0x1800000U) #define IOMUXD_MCLK_IN1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MCLK_IN1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_lp_config_SHIFT)) & IOMUXD_MCLK_IN1_lp_config_MASK) #define IOMUXD_MCLK_IN1_sw_config_MASK (0x6000000U) #define IOMUXD_MCLK_IN1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MCLK_IN1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_sw_config_SHIFT)) & IOMUXD_MCLK_IN1_sw_config_MASK) #define IOMUXD_MCLK_IN1_mux_mode_MASK (0x38000000U) #define IOMUXD_MCLK_IN1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ACM.MCLK_IN1 * 0b001..ADMA.I2C3.SDA * 0b010..ADMA.LCDIF.EN * 0b011..ADMA.SPI2.SCK * 0b100..ADMA.LCDIF.D17 */ #define IOMUXD_MCLK_IN1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_mux_mode_SHIFT)) & IOMUXD_MCLK_IN1_mux_mode_MASK) #define IOMUXD_MCLK_IN1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MCLK_IN1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MCLK_IN1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_IN1_update_pad_ctl_MASK) #define IOMUXD_MCLK_IN1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MCLK_IN1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MCLK_IN1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_update_mux_mode_SHIFT)) & IOMUXD_MCLK_IN1_update_mux_mode_MASK) /*! @} */ /*! @name MCLK_IN0 - MCLK_IN0 */ /*! @{ */ #define IOMUXD_MCLK_IN0_PDRV_MASK (0x1U) #define IOMUXD_MCLK_IN0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MCLK_IN0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_PDRV_SHIFT)) & IOMUXD_MCLK_IN0_PDRV_MASK) #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_MASK (0x1EU) #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_SHIFT (1U) /*! MCLK_IN0_reserved_1_4 - reserved */ #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_SHIFT)) & IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_MASK) #define IOMUXD_MCLK_IN0_PULL_MASK (0x60U) #define IOMUXD_MCLK_IN0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MCLK_IN0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_PULL_SHIFT)) & IOMUXD_MCLK_IN0_PULL_MASK) #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_SHIFT (7U) /*! MCLK_IN0_reserved_7_18 - reserved */ #define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_SHIFT)) & IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_MASK) #define IOMUXD_MCLK_IN0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MCLK_IN0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MCLK_IN0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_IN0_WAKEUP_CTRL_MASK) #define IOMUXD_MCLK_IN0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MCLK_IN0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MCLK_IN0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_IN0_WAKEUP_MASK_MASK) #define IOMUXD_MCLK_IN0_lp_config_MASK (0x1800000U) #define IOMUXD_MCLK_IN0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MCLK_IN0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_lp_config_SHIFT)) & IOMUXD_MCLK_IN0_lp_config_MASK) #define IOMUXD_MCLK_IN0_sw_config_MASK (0x6000000U) #define IOMUXD_MCLK_IN0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MCLK_IN0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_sw_config_SHIFT)) & IOMUXD_MCLK_IN0_sw_config_MASK) #define IOMUXD_MCLK_IN0_mux_mode_MASK (0x38000000U) #define IOMUXD_MCLK_IN0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ACM.MCLK_IN0 * 0b001..ADMA.ESAI0.RX_HF_CLK * 0b010..ADMA.LCDIF.VSYNC * 0b011..ADMA.SPI2.SDI * 0b100..LSIO.GPIO0.IO19 */ #define IOMUXD_MCLK_IN0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_mux_mode_SHIFT)) & IOMUXD_MCLK_IN0_mux_mode_MASK) #define IOMUXD_MCLK_IN0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MCLK_IN0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MCLK_IN0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_IN0_update_pad_ctl_MASK) #define IOMUXD_MCLK_IN0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MCLK_IN0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MCLK_IN0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_update_mux_mode_SHIFT)) & IOMUXD_MCLK_IN0_update_mux_mode_MASK) /*! @} */ /*! @name MCLK_OUT0 - MCLK_OUT0 */ /*! @{ */ #define IOMUXD_MCLK_OUT0_PDRV_MASK (0x1U) #define IOMUXD_MCLK_OUT0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MCLK_OUT0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_PDRV_SHIFT)) & IOMUXD_MCLK_OUT0_PDRV_MASK) #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_MASK (0x1EU) #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_SHIFT (1U) /*! MCLK_OUT0_reserved_1_4 - reserved */ #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_SHIFT)) & IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_MASK) #define IOMUXD_MCLK_OUT0_PULL_MASK (0x60U) #define IOMUXD_MCLK_OUT0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MCLK_OUT0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_PULL_SHIFT)) & IOMUXD_MCLK_OUT0_PULL_MASK) #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_SHIFT (7U) /*! MCLK_OUT0_reserved_7_18 - reserved */ #define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_SHIFT)) & IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_MASK) #define IOMUXD_MCLK_OUT0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MCLK_OUT0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MCLK_OUT0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_OUT0_WAKEUP_CTRL_MASK) #define IOMUXD_MCLK_OUT0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MCLK_OUT0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MCLK_OUT0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_OUT0_WAKEUP_MASK_MASK) #define IOMUXD_MCLK_OUT0_lp_config_MASK (0x1800000U) #define IOMUXD_MCLK_OUT0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MCLK_OUT0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_lp_config_SHIFT)) & IOMUXD_MCLK_OUT0_lp_config_MASK) #define IOMUXD_MCLK_OUT0_sw_config_MASK (0x6000000U) #define IOMUXD_MCLK_OUT0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MCLK_OUT0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_sw_config_SHIFT)) & IOMUXD_MCLK_OUT0_sw_config_MASK) #define IOMUXD_MCLK_OUT0_mux_mode_MASK (0x38000000U) #define IOMUXD_MCLK_OUT0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ACM.MCLK_OUT0 * 0b001..ADMA.ESAI0.TX_HF_CLK * 0b010..ADMA.LCDIF.CLK * 0b011..ADMA.SPI2.SDO * 0b100..LSIO.GPIO0.IO20 */ #define IOMUXD_MCLK_OUT0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_mux_mode_SHIFT)) & IOMUXD_MCLK_OUT0_mux_mode_MASK) #define IOMUXD_MCLK_OUT0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MCLK_OUT0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MCLK_OUT0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_OUT0_update_pad_ctl_MASK) #define IOMUXD_MCLK_OUT0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MCLK_OUT0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MCLK_OUT0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_update_mux_mode_SHIFT)) & IOMUXD_MCLK_OUT0_update_mux_mode_MASK) /*! @} */ /*! @name UART1_TX - UART1_TX */ /*! @{ */ #define IOMUXD_UART1_TX_PDRV_MASK (0x1U) #define IOMUXD_UART1_TX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_UART1_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_PDRV_SHIFT)) & IOMUXD_UART1_TX_PDRV_MASK) #define IOMUXD_UART1_TX_UART1_TX_reserved_1_4_MASK (0x1EU) #define IOMUXD_UART1_TX_UART1_TX_reserved_1_4_SHIFT (1U) /*! UART1_TX_reserved_1_4 - reserved */ #define IOMUXD_UART1_TX_UART1_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_UART1_TX_reserved_1_4_SHIFT)) & IOMUXD_UART1_TX_UART1_TX_reserved_1_4_MASK) #define IOMUXD_UART1_TX_PULL_MASK (0x60U) #define IOMUXD_UART1_TX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_UART1_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_PULL_SHIFT)) & IOMUXD_UART1_TX_PULL_MASK) #define IOMUXD_UART1_TX_UART1_TX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_UART1_TX_UART1_TX_reserved_7_18_SHIFT (7U) /*! UART1_TX_reserved_7_18 - reserved */ #define IOMUXD_UART1_TX_UART1_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_UART1_TX_reserved_7_18_SHIFT)) & IOMUXD_UART1_TX_UART1_TX_reserved_7_18_MASK) #define IOMUXD_UART1_TX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_UART1_TX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_UART1_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_TX_WAKEUP_CTRL_MASK) #define IOMUXD_UART1_TX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_UART1_TX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_UART1_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_TX_WAKEUP_MASK_MASK) #define IOMUXD_UART1_TX_lp_config_MASK (0x1800000U) #define IOMUXD_UART1_TX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_UART1_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_lp_config_SHIFT)) & IOMUXD_UART1_TX_lp_config_MASK) #define IOMUXD_UART1_TX_sw_config_MASK (0x6000000U) #define IOMUXD_UART1_TX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_UART1_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_sw_config_SHIFT)) & IOMUXD_UART1_TX_sw_config_MASK) #define IOMUXD_UART1_TX_mux_mode_MASK (0x38000000U) #define IOMUXD_UART1_TX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.UART1.TX * 0b001..LSIO.PWM0.OUT * 0b010..LSIO.GPT0.CAPTURE * 0b100..LSIO.GPIO0.IO21 */ #define IOMUXD_UART1_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_mux_mode_SHIFT)) & IOMUXD_UART1_TX_mux_mode_MASK) #define IOMUXD_UART1_TX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_UART1_TX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_UART1_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART1_TX_update_pad_ctl_MASK) #define IOMUXD_UART1_TX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_UART1_TX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_UART1_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_update_mux_mode_SHIFT)) & IOMUXD_UART1_TX_update_mux_mode_MASK) /*! @} */ /*! @name UART1_RX - UART1_RX */ /*! @{ */ #define IOMUXD_UART1_RX_PDRV_MASK (0x1U) #define IOMUXD_UART1_RX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_UART1_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_PDRV_SHIFT)) & IOMUXD_UART1_RX_PDRV_MASK) #define IOMUXD_UART1_RX_UART1_RX_reserved_1_4_MASK (0x1EU) #define IOMUXD_UART1_RX_UART1_RX_reserved_1_4_SHIFT (1U) /*! UART1_RX_reserved_1_4 - reserved */ #define IOMUXD_UART1_RX_UART1_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_UART1_RX_reserved_1_4_SHIFT)) & IOMUXD_UART1_RX_UART1_RX_reserved_1_4_MASK) #define IOMUXD_UART1_RX_PULL_MASK (0x60U) #define IOMUXD_UART1_RX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_UART1_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_PULL_SHIFT)) & IOMUXD_UART1_RX_PULL_MASK) #define IOMUXD_UART1_RX_UART1_RX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_UART1_RX_UART1_RX_reserved_7_18_SHIFT (7U) /*! UART1_RX_reserved_7_18 - reserved */ #define IOMUXD_UART1_RX_UART1_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_UART1_RX_reserved_7_18_SHIFT)) & IOMUXD_UART1_RX_UART1_RX_reserved_7_18_MASK) #define IOMUXD_UART1_RX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_UART1_RX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_UART1_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_RX_WAKEUP_CTRL_MASK) #define IOMUXD_UART1_RX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_UART1_RX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_UART1_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_RX_WAKEUP_MASK_MASK) #define IOMUXD_UART1_RX_lp_config_MASK (0x1800000U) #define IOMUXD_UART1_RX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_UART1_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_lp_config_SHIFT)) & IOMUXD_UART1_RX_lp_config_MASK) #define IOMUXD_UART1_RX_sw_config_MASK (0x6000000U) #define IOMUXD_UART1_RX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_UART1_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_sw_config_SHIFT)) & IOMUXD_UART1_RX_sw_config_MASK) #define IOMUXD_UART1_RX_mux_mode_MASK (0x38000000U) #define IOMUXD_UART1_RX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.UART1.RX * 0b001..LSIO.PWM1.OUT * 0b010..LSIO.GPT0.COMPARE * 0b011..LSIO.GPT1.CLK * 0b100..LSIO.GPIO0.IO22 */ #define IOMUXD_UART1_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_mux_mode_SHIFT)) & IOMUXD_UART1_RX_mux_mode_MASK) #define IOMUXD_UART1_RX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_UART1_RX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_UART1_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART1_RX_update_pad_ctl_MASK) #define IOMUXD_UART1_RX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_UART1_RX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_UART1_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_update_mux_mode_SHIFT)) & IOMUXD_UART1_RX_update_mux_mode_MASK) /*! @} */ /*! @name UART1_RTS_B - UART1_RTS_B */ /*! @{ */ #define IOMUXD_UART1_RTS_B_PDRV_MASK (0x1U) #define IOMUXD_UART1_RTS_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_UART1_RTS_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_PDRV_SHIFT)) & IOMUXD_UART1_RTS_B_PDRV_MASK) #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_SHIFT (1U) /*! UART1_RTS_B_reserved_1_4 - reserved */ #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_SHIFT)) & IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_MASK) #define IOMUXD_UART1_RTS_B_PULL_MASK (0x60U) #define IOMUXD_UART1_RTS_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_UART1_RTS_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_PULL_SHIFT)) & IOMUXD_UART1_RTS_B_PULL_MASK) #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_SHIFT (7U) /*! UART1_RTS_B_reserved_7_18 - reserved */ #define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_SHIFT)) & IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_MASK) #define IOMUXD_UART1_RTS_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_UART1_RTS_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_UART1_RTS_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_RTS_B_WAKEUP_CTRL_MASK) #define IOMUXD_UART1_RTS_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_UART1_RTS_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_UART1_RTS_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_RTS_B_WAKEUP_MASK_MASK) #define IOMUXD_UART1_RTS_B_lp_config_MASK (0x1800000U) #define IOMUXD_UART1_RTS_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_UART1_RTS_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_lp_config_SHIFT)) & IOMUXD_UART1_RTS_B_lp_config_MASK) #define IOMUXD_UART1_RTS_B_sw_config_MASK (0x6000000U) #define IOMUXD_UART1_RTS_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_UART1_RTS_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_sw_config_SHIFT)) & IOMUXD_UART1_RTS_B_sw_config_MASK) #define IOMUXD_UART1_RTS_B_mux_mode_MASK (0x38000000U) #define IOMUXD_UART1_RTS_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.UART1.RTS_B * 0b001..LSIO.PWM2.OUT * 0b010..ADMA.LCDIF.D16 * 0b011..LSIO.GPT1.CAPTURE * 0b100..LSIO.GPT0.CLK */ #define IOMUXD_UART1_RTS_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_mux_mode_SHIFT)) & IOMUXD_UART1_RTS_B_mux_mode_MASK) #define IOMUXD_UART1_RTS_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_UART1_RTS_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_UART1_RTS_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_update_pad_ctl_SHIFT)) & IOMUXD_UART1_RTS_B_update_pad_ctl_MASK) #define IOMUXD_UART1_RTS_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_UART1_RTS_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_UART1_RTS_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_update_mux_mode_SHIFT)) & IOMUXD_UART1_RTS_B_update_mux_mode_MASK) /*! @} */ /*! @name UART1_CTS_B - UART1_CTS_B */ /*! @{ */ #define IOMUXD_UART1_CTS_B_PDRV_MASK (0x1U) #define IOMUXD_UART1_CTS_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_UART1_CTS_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_PDRV_SHIFT)) & IOMUXD_UART1_CTS_B_PDRV_MASK) #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_SHIFT (1U) /*! UART1_CTS_B_reserved_1_4 - reserved */ #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_SHIFT)) & IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_MASK) #define IOMUXD_UART1_CTS_B_PULL_MASK (0x60U) #define IOMUXD_UART1_CTS_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_UART1_CTS_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_PULL_SHIFT)) & IOMUXD_UART1_CTS_B_PULL_MASK) #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_SHIFT (7U) /*! UART1_CTS_B_reserved_7_18 - reserved */ #define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_SHIFT)) & IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_MASK) #define IOMUXD_UART1_CTS_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_UART1_CTS_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_UART1_CTS_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_CTS_B_WAKEUP_CTRL_MASK) #define IOMUXD_UART1_CTS_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_UART1_CTS_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_UART1_CTS_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_CTS_B_WAKEUP_MASK_MASK) #define IOMUXD_UART1_CTS_B_lp_config_MASK (0x1800000U) #define IOMUXD_UART1_CTS_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_UART1_CTS_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_lp_config_SHIFT)) & IOMUXD_UART1_CTS_B_lp_config_MASK) #define IOMUXD_UART1_CTS_B_sw_config_MASK (0x6000000U) #define IOMUXD_UART1_CTS_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_UART1_CTS_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_sw_config_SHIFT)) & IOMUXD_UART1_CTS_B_sw_config_MASK) #define IOMUXD_UART1_CTS_B_mux_mode_MASK (0x38000000U) #define IOMUXD_UART1_CTS_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.UART1.CTS_B * 0b001..LSIO.PWM3.OUT * 0b010..ADMA.LCDIF.D17 * 0b011..LSIO.GPT1.COMPARE * 0b100..LSIO.GPIO0.IO24 */ #define IOMUXD_UART1_CTS_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_mux_mode_SHIFT)) & IOMUXD_UART1_CTS_B_mux_mode_MASK) #define IOMUXD_UART1_CTS_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_UART1_CTS_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_UART1_CTS_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_update_pad_ctl_SHIFT)) & IOMUXD_UART1_CTS_B_update_pad_ctl_MASK) #define IOMUXD_UART1_CTS_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_UART1_CTS_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_UART1_CTS_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_update_mux_mode_SHIFT)) & IOMUXD_UART1_CTS_B_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_1_4 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_SHIFT (0U) /*! SPDIF0_EXT_CLK - wakeup from SPDIF0_EXT_CLK */ #define IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_SHIFT (1U) /*! iomuxd_group_1_4_reserved_1_1 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_SHIFT (2U) /*! SPI3_SCK - wakeup from SPI3_SCK */ #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_SHIFT (3U) /*! SPI3_SDO - wakeup from SPI3_SDO */ #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_SHIFT (4U) /*! SPI3_SDI - wakeup from SPI3_SDI */ #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_SHIFT (5U) /*! SPI3_CS0 - wakeup from SPI3_CS0 */ #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_SHIFT (6U) /*! SPI3_CS1 - wakeup from SPI3_CS1 */ #define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_SHIFT (7U) /*! MCLK_IN1 - wakeup from MCLK_IN1 */ #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_SHIFT (8U) /*! MCLK_IN0 - wakeup from MCLK_IN0 */ #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_SHIFT (9U) /*! MCLK_OUT0 - wakeup from MCLK_OUT0 */ #define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_SHIFT (10U) /*! UART1_TX - wakeup from UART1_TX */ #define IOMUXD_IOMUXD_GROUP_1_4_UART1_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_SHIFT (11U) /*! UART1_RX - wakeup from UART1_RX */ #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_SHIFT (12U) /*! UART1_RTS_B - wakeup from UART1_RTS_B */ #define IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_MASK (0x2000U) #define IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_SHIFT (13U) /*! UART1_CTS_B - wakeup from UART1_CTS_B */ #define IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_MASK) #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_MASK (0xFFFFC000U) #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_SHIFT (14U) /*! iomuxd_group_1_4_reserved_14_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_MASK) /*! @} */ /*! @name SAI0_TXD - SAI0_TXD */ /*! @{ */ #define IOMUXD_SAI0_TXD_PDRV_MASK (0x1U) #define IOMUXD_SAI0_TXD_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SAI0_TXD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_PDRV_SHIFT)) & IOMUXD_SAI0_TXD_PDRV_MASK) #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_MASK (0x1EU) #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_SHIFT (1U) /*! SAI0_TXD_reserved_1_4 - reserved */ #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_SHIFT)) & IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_MASK) #define IOMUXD_SAI0_TXD_PULL_MASK (0x60U) #define IOMUXD_SAI0_TXD_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SAI0_TXD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_PULL_SHIFT)) & IOMUXD_SAI0_TXD_PULL_MASK) #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_SHIFT (7U) /*! SAI0_TXD_reserved_7_18 - reserved */ #define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_SHIFT)) & IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_MASK) #define IOMUXD_SAI0_TXD_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SAI0_TXD_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SAI0_TXD_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_TXD_WAKEUP_CTRL_MASK) #define IOMUXD_SAI0_TXD_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SAI0_TXD_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SAI0_TXD_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_TXD_WAKEUP_MASK_MASK) #define IOMUXD_SAI0_TXD_lp_config_MASK (0x1800000U) #define IOMUXD_SAI0_TXD_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SAI0_TXD_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_lp_config_SHIFT)) & IOMUXD_SAI0_TXD_lp_config_MASK) #define IOMUXD_SAI0_TXD_sw_config_MASK (0x6000000U) #define IOMUXD_SAI0_TXD_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SAI0_TXD_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_sw_config_SHIFT)) & IOMUXD_SAI0_TXD_sw_config_MASK) #define IOMUXD_SAI0_TXD_mux_mode_MASK (0x38000000U) #define IOMUXD_SAI0_TXD_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SAI0.TXD * 0b001..ADMA.SAI1.RXC * 0b010..ADMA.SPI1.SDO * 0b011..ADMA.LCDIF.D18 * 0b100..LSIO.GPIO0.IO25 */ #define IOMUXD_SAI0_TXD_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_mux_mode_SHIFT)) & IOMUXD_SAI0_TXD_mux_mode_MASK) #define IOMUXD_SAI0_TXD_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SAI0_TXD_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SAI0_TXD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_TXD_update_pad_ctl_MASK) #define IOMUXD_SAI0_TXD_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SAI0_TXD_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SAI0_TXD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_update_mux_mode_SHIFT)) & IOMUXD_SAI0_TXD_update_mux_mode_MASK) /*! @} */ /*! @name SAI0_TXC - SAI0_TXC */ /*! @{ */ #define IOMUXD_SAI0_TXC_PDRV_MASK (0x1U) #define IOMUXD_SAI0_TXC_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SAI0_TXC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_PDRV_SHIFT)) & IOMUXD_SAI0_TXC_PDRV_MASK) #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_MASK (0x1EU) #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_SHIFT (1U) /*! SAI0_TXC_reserved_1_4 - reserved */ #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_SHIFT)) & IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_MASK) #define IOMUXD_SAI0_TXC_PULL_MASK (0x60U) #define IOMUXD_SAI0_TXC_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SAI0_TXC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_PULL_SHIFT)) & IOMUXD_SAI0_TXC_PULL_MASK) #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_SHIFT (7U) /*! SAI0_TXC_reserved_7_18 - reserved */ #define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_SHIFT)) & IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_MASK) #define IOMUXD_SAI0_TXC_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SAI0_TXC_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SAI0_TXC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_TXC_WAKEUP_CTRL_MASK) #define IOMUXD_SAI0_TXC_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SAI0_TXC_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SAI0_TXC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_TXC_WAKEUP_MASK_MASK) #define IOMUXD_SAI0_TXC_lp_config_MASK (0x1800000U) #define IOMUXD_SAI0_TXC_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SAI0_TXC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_lp_config_SHIFT)) & IOMUXD_SAI0_TXC_lp_config_MASK) #define IOMUXD_SAI0_TXC_sw_config_MASK (0x6000000U) #define IOMUXD_SAI0_TXC_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SAI0_TXC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_sw_config_SHIFT)) & IOMUXD_SAI0_TXC_sw_config_MASK) #define IOMUXD_SAI0_TXC_mux_mode_MASK (0x38000000U) #define IOMUXD_SAI0_TXC_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SAI0.TXC * 0b001..ADMA.SAI1.TXD * 0b010..ADMA.SPI1.SDI * 0b011..ADMA.LCDIF.D19 * 0b100..LSIO.GPIO0.IO26 */ #define IOMUXD_SAI0_TXC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_mux_mode_SHIFT)) & IOMUXD_SAI0_TXC_mux_mode_MASK) #define IOMUXD_SAI0_TXC_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SAI0_TXC_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SAI0_TXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_TXC_update_pad_ctl_MASK) #define IOMUXD_SAI0_TXC_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SAI0_TXC_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SAI0_TXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_update_mux_mode_SHIFT)) & IOMUXD_SAI0_TXC_update_mux_mode_MASK) /*! @} */ /*! @name SAI0_RXD - SAI0_RXD */ /*! @{ */ #define IOMUXD_SAI0_RXD_PDRV_MASK (0x1U) #define IOMUXD_SAI0_RXD_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SAI0_RXD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_PDRV_SHIFT)) & IOMUXD_SAI0_RXD_PDRV_MASK) #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_MASK (0x1EU) #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_SHIFT (1U) /*! SAI0_RXD_reserved_1_4 - reserved */ #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_SHIFT)) & IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_MASK) #define IOMUXD_SAI0_RXD_PULL_MASK (0x60U) #define IOMUXD_SAI0_RXD_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SAI0_RXD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_PULL_SHIFT)) & IOMUXD_SAI0_RXD_PULL_MASK) #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_SHIFT (7U) /*! SAI0_RXD_reserved_7_18 - reserved */ #define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_SHIFT)) & IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_MASK) #define IOMUXD_SAI0_RXD_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SAI0_RXD_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SAI0_RXD_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_RXD_WAKEUP_CTRL_MASK) #define IOMUXD_SAI0_RXD_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SAI0_RXD_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SAI0_RXD_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_RXD_WAKEUP_MASK_MASK) #define IOMUXD_SAI0_RXD_lp_config_MASK (0x1800000U) #define IOMUXD_SAI0_RXD_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SAI0_RXD_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_lp_config_SHIFT)) & IOMUXD_SAI0_RXD_lp_config_MASK) #define IOMUXD_SAI0_RXD_sw_config_MASK (0x6000000U) #define IOMUXD_SAI0_RXD_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SAI0_RXD_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_sw_config_SHIFT)) & IOMUXD_SAI0_RXD_sw_config_MASK) #define IOMUXD_SAI0_RXD_mux_mode_MASK (0x38000000U) #define IOMUXD_SAI0_RXD_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SAI0.RXD * 0b001..ADMA.SAI1.RXFS * 0b010..ADMA.SPI1.CS0 * 0b011..ADMA.LCDIF.D20 * 0b100..LSIO.GPIO0.IO27 */ #define IOMUXD_SAI0_RXD_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_mux_mode_SHIFT)) & IOMUXD_SAI0_RXD_mux_mode_MASK) #define IOMUXD_SAI0_RXD_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SAI0_RXD_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SAI0_RXD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_RXD_update_pad_ctl_MASK) #define IOMUXD_SAI0_RXD_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SAI0_RXD_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SAI0_RXD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_update_mux_mode_SHIFT)) & IOMUXD_SAI0_RXD_update_mux_mode_MASK) /*! @} */ /*! @name SAI0_TXFS - SAI0_TXFS */ /*! @{ */ #define IOMUXD_SAI0_TXFS_PDRV_MASK (0x1U) #define IOMUXD_SAI0_TXFS_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SAI0_TXFS_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_PDRV_SHIFT)) & IOMUXD_SAI0_TXFS_PDRV_MASK) #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_MASK (0x1EU) #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_SHIFT (1U) /*! SAI0_TXFS_reserved_1_4 - reserved */ #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_SHIFT)) & IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_MASK) #define IOMUXD_SAI0_TXFS_PULL_MASK (0x60U) #define IOMUXD_SAI0_TXFS_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SAI0_TXFS_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_PULL_SHIFT)) & IOMUXD_SAI0_TXFS_PULL_MASK) #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_SHIFT (7U) /*! SAI0_TXFS_reserved_7_18 - reserved */ #define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_SHIFT)) & IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_MASK) #define IOMUXD_SAI0_TXFS_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SAI0_TXFS_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SAI0_TXFS_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_TXFS_WAKEUP_CTRL_MASK) #define IOMUXD_SAI0_TXFS_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SAI0_TXFS_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SAI0_TXFS_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_TXFS_WAKEUP_MASK_MASK) #define IOMUXD_SAI0_TXFS_lp_config_MASK (0x1800000U) #define IOMUXD_SAI0_TXFS_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SAI0_TXFS_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_lp_config_SHIFT)) & IOMUXD_SAI0_TXFS_lp_config_MASK) #define IOMUXD_SAI0_TXFS_sw_config_MASK (0x6000000U) #define IOMUXD_SAI0_TXFS_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SAI0_TXFS_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_sw_config_SHIFT)) & IOMUXD_SAI0_TXFS_sw_config_MASK) #define IOMUXD_SAI0_TXFS_mux_mode_MASK (0x38000000U) #define IOMUXD_SAI0_TXFS_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SAI0.TXFS * 0b001..ADMA.SPI2.CS1 * 0b010..ADMA.SPI1.SCK * 0b100..LSIO.GPIO0.IO28 */ #define IOMUXD_SAI0_TXFS_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_mux_mode_SHIFT)) & IOMUXD_SAI0_TXFS_mux_mode_MASK) #define IOMUXD_SAI0_TXFS_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SAI0_TXFS_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SAI0_TXFS_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_TXFS_update_pad_ctl_MASK) #define IOMUXD_SAI0_TXFS_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SAI0_TXFS_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SAI0_TXFS_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_update_mux_mode_SHIFT)) & IOMUXD_SAI0_TXFS_update_mux_mode_MASK) /*! @} */ /*! @name SAI1_RXD - SAI1_RXD */ /*! @{ */ #define IOMUXD_SAI1_RXD_PDRV_MASK (0x1U) #define IOMUXD_SAI1_RXD_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SAI1_RXD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_PDRV_SHIFT)) & IOMUXD_SAI1_RXD_PDRV_MASK) #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_MASK (0x1EU) #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_SHIFT (1U) /*! SAI1_RXD_reserved_1_4 - reserved */ #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_MASK) #define IOMUXD_SAI1_RXD_PULL_MASK (0x60U) #define IOMUXD_SAI1_RXD_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SAI1_RXD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_PULL_SHIFT)) & IOMUXD_SAI1_RXD_PULL_MASK) #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_SHIFT (7U) /*! SAI1_RXD_reserved_7_18 - reserved */ #define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_MASK) #define IOMUXD_SAI1_RXD_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SAI1_RXD_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SAI1_RXD_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXD_WAKEUP_CTRL_MASK) #define IOMUXD_SAI1_RXD_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SAI1_RXD_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SAI1_RXD_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXD_WAKEUP_MASK_MASK) #define IOMUXD_SAI1_RXD_lp_config_MASK (0x1800000U) #define IOMUXD_SAI1_RXD_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SAI1_RXD_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_lp_config_SHIFT)) & IOMUXD_SAI1_RXD_lp_config_MASK) #define IOMUXD_SAI1_RXD_sw_config_MASK (0x6000000U) #define IOMUXD_SAI1_RXD_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SAI1_RXD_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_sw_config_SHIFT)) & IOMUXD_SAI1_RXD_sw_config_MASK) #define IOMUXD_SAI1_RXD_mux_mode_MASK (0x38000000U) #define IOMUXD_SAI1_RXD_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SAI1.RXD * 0b001..ADMA.SAI0.RXFS * 0b010..ADMA.SPI1.CS1 * 0b011..ADMA.LCDIF.D21 * 0b100..LSIO.GPIO0.IO29 */ #define IOMUXD_SAI1_RXD_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_mux_mode_SHIFT)) & IOMUXD_SAI1_RXD_mux_mode_MASK) #define IOMUXD_SAI1_RXD_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SAI1_RXD_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SAI1_RXD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXD_update_pad_ctl_MASK) #define IOMUXD_SAI1_RXD_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SAI1_RXD_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SAI1_RXD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXD_update_mux_mode_MASK) /*! @} */ /*! @name SAI1_RXC - SAI1_RXC */ /*! @{ */ #define IOMUXD_SAI1_RXC_PDRV_MASK (0x1U) #define IOMUXD_SAI1_RXC_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SAI1_RXC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_PDRV_SHIFT)) & IOMUXD_SAI1_RXC_PDRV_MASK) #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_MASK (0x1EU) #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_SHIFT (1U) /*! SAI1_RXC_reserved_1_4 - reserved */ #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_MASK) #define IOMUXD_SAI1_RXC_PULL_MASK (0x60U) #define IOMUXD_SAI1_RXC_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SAI1_RXC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_PULL_SHIFT)) & IOMUXD_SAI1_RXC_PULL_MASK) #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_SHIFT (7U) /*! SAI1_RXC_reserved_7_18 - reserved */ #define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_MASK) #define IOMUXD_SAI1_RXC_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SAI1_RXC_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SAI1_RXC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXC_WAKEUP_CTRL_MASK) #define IOMUXD_SAI1_RXC_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SAI1_RXC_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SAI1_RXC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXC_WAKEUP_MASK_MASK) #define IOMUXD_SAI1_RXC_lp_config_MASK (0x1800000U) #define IOMUXD_SAI1_RXC_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SAI1_RXC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_lp_config_SHIFT)) & IOMUXD_SAI1_RXC_lp_config_MASK) #define IOMUXD_SAI1_RXC_sw_config_MASK (0x6000000U) #define IOMUXD_SAI1_RXC_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SAI1_RXC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_sw_config_SHIFT)) & IOMUXD_SAI1_RXC_sw_config_MASK) #define IOMUXD_SAI1_RXC_mux_mode_MASK (0x38000000U) #define IOMUXD_SAI1_RXC_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SAI1.RXC * 0b001..ADMA.SAI1.TXC * 0b011..ADMA.LCDIF.D22 * 0b100..LSIO.GPIO0.IO30 */ #define IOMUXD_SAI1_RXC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_mux_mode_SHIFT)) & IOMUXD_SAI1_RXC_mux_mode_MASK) #define IOMUXD_SAI1_RXC_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SAI1_RXC_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SAI1_RXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXC_update_pad_ctl_MASK) #define IOMUXD_SAI1_RXC_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SAI1_RXC_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SAI1_RXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXC_update_mux_mode_MASK) /*! @} */ /*! @name SAI1_RXFS - SAI1_RXFS */ /*! @{ */ #define IOMUXD_SAI1_RXFS_PDRV_MASK (0x1U) #define IOMUXD_SAI1_RXFS_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SAI1_RXFS_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_PDRV_SHIFT)) & IOMUXD_SAI1_RXFS_PDRV_MASK) #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_MASK (0x1EU) #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_SHIFT (1U) /*! SAI1_RXFS_reserved_1_4 - reserved */ #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_MASK) #define IOMUXD_SAI1_RXFS_PULL_MASK (0x60U) #define IOMUXD_SAI1_RXFS_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SAI1_RXFS_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_PULL_SHIFT)) & IOMUXD_SAI1_RXFS_PULL_MASK) #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_SHIFT (7U) /*! SAI1_RXFS_reserved_7_18 - reserved */ #define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_MASK) #define IOMUXD_SAI1_RXFS_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SAI1_RXFS_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SAI1_RXFS_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXFS_WAKEUP_CTRL_MASK) #define IOMUXD_SAI1_RXFS_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SAI1_RXFS_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SAI1_RXFS_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXFS_WAKEUP_MASK_MASK) #define IOMUXD_SAI1_RXFS_lp_config_MASK (0x1800000U) #define IOMUXD_SAI1_RXFS_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SAI1_RXFS_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_lp_config_SHIFT)) & IOMUXD_SAI1_RXFS_lp_config_MASK) #define IOMUXD_SAI1_RXFS_sw_config_MASK (0x6000000U) #define IOMUXD_SAI1_RXFS_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SAI1_RXFS_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_sw_config_SHIFT)) & IOMUXD_SAI1_RXFS_sw_config_MASK) #define IOMUXD_SAI1_RXFS_mux_mode_MASK (0x38000000U) #define IOMUXD_SAI1_RXFS_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SAI1.RXFS * 0b001..ADMA.SAI1.TXFS * 0b011..ADMA.LCDIF.D23 * 0b100..LSIO.GPIO0.IO31 */ #define IOMUXD_SAI1_RXFS_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_mux_mode_SHIFT)) & IOMUXD_SAI1_RXFS_mux_mode_MASK) #define IOMUXD_SAI1_RXFS_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SAI1_RXFS_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SAI1_RXFS_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXFS_update_pad_ctl_MASK) #define IOMUXD_SAI1_RXFS_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SAI1_RXFS_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SAI1_RXFS_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXFS_update_mux_mode_MASK) /*! @} */ /*! @name SPI2_CS0 - SPI2_CS0 */ /*! @{ */ #define IOMUXD_SPI2_CS0_PDRV_MASK (0x1U) #define IOMUXD_SPI2_CS0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI2_CS0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_PDRV_SHIFT)) & IOMUXD_SPI2_CS0_PDRV_MASK) #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_SHIFT (1U) /*! SPI2_CS0_reserved_1_4 - reserved */ #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_MASK) #define IOMUXD_SPI2_CS0_PULL_MASK (0x60U) #define IOMUXD_SPI2_CS0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI2_CS0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_PULL_SHIFT)) & IOMUXD_SPI2_CS0_PULL_MASK) #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_SHIFT (7U) /*! SPI2_CS0_reserved_7_18 - reserved */ #define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_MASK) #define IOMUXD_SPI2_CS0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI2_CS0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI2_CS0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_CS0_WAKEUP_CTRL_MASK) #define IOMUXD_SPI2_CS0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI2_CS0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI2_CS0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_CS0_WAKEUP_MASK_MASK) #define IOMUXD_SPI2_CS0_lp_config_MASK (0x1800000U) #define IOMUXD_SPI2_CS0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI2_CS0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_lp_config_SHIFT)) & IOMUXD_SPI2_CS0_lp_config_MASK) #define IOMUXD_SPI2_CS0_sw_config_MASK (0x6000000U) #define IOMUXD_SPI2_CS0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI2_CS0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_sw_config_SHIFT)) & IOMUXD_SPI2_CS0_sw_config_MASK) #define IOMUXD_SPI2_CS0_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI2_CS0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI2.CS0 * 0b100..LSIO.GPIO1.IO00 */ #define IOMUXD_SPI2_CS0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_mux_mode_SHIFT)) & IOMUXD_SPI2_CS0_mux_mode_MASK) #define IOMUXD_SPI2_CS0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI2_CS0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI2_CS0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_CS0_update_pad_ctl_MASK) #define IOMUXD_SPI2_CS0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI2_CS0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI2_CS0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI2_CS0_update_mux_mode_MASK) /*! @} */ /*! @name SPI2_SDO - SPI2_SDO */ /*! @{ */ #define IOMUXD_SPI2_SDO_PDRV_MASK (0x1U) #define IOMUXD_SPI2_SDO_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI2_SDO_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_PDRV_SHIFT)) & IOMUXD_SPI2_SDO_PDRV_MASK) #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_SHIFT (1U) /*! SPI2_SDO_reserved_1_4 - reserved */ #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_MASK) #define IOMUXD_SPI2_SDO_PULL_MASK (0x60U) #define IOMUXD_SPI2_SDO_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI2_SDO_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_PULL_SHIFT)) & IOMUXD_SPI2_SDO_PULL_MASK) #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_SHIFT (7U) /*! SPI2_SDO_reserved_7_18 - reserved */ #define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_MASK) #define IOMUXD_SPI2_SDO_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI2_SDO_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI2_SDO_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SDO_WAKEUP_CTRL_MASK) #define IOMUXD_SPI2_SDO_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI2_SDO_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI2_SDO_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SDO_WAKEUP_MASK_MASK) #define IOMUXD_SPI2_SDO_lp_config_MASK (0x1800000U) #define IOMUXD_SPI2_SDO_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI2_SDO_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_lp_config_SHIFT)) & IOMUXD_SPI2_SDO_lp_config_MASK) #define IOMUXD_SPI2_SDO_sw_config_MASK (0x6000000U) #define IOMUXD_SPI2_SDO_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI2_SDO_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_sw_config_SHIFT)) & IOMUXD_SPI2_SDO_sw_config_MASK) #define IOMUXD_SPI2_SDO_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI2_SDO_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI2.SDO * 0b100..LSIO.GPIO1.IO01 */ #define IOMUXD_SPI2_SDO_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_mux_mode_SHIFT)) & IOMUXD_SPI2_SDO_mux_mode_MASK) #define IOMUXD_SPI2_SDO_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI2_SDO_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI2_SDO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SDO_update_pad_ctl_MASK) #define IOMUXD_SPI2_SDO_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI2_SDO_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI2_SDO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SDO_update_mux_mode_MASK) /*! @} */ /*! @name SPI2_SDI - SPI2_SDI */ /*! @{ */ #define IOMUXD_SPI2_SDI_PDRV_MASK (0x1U) #define IOMUXD_SPI2_SDI_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI2_SDI_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_PDRV_SHIFT)) & IOMUXD_SPI2_SDI_PDRV_MASK) #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_SHIFT (1U) /*! SPI2_SDI_reserved_1_4 - reserved */ #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_MASK) #define IOMUXD_SPI2_SDI_PULL_MASK (0x60U) #define IOMUXD_SPI2_SDI_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI2_SDI_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_PULL_SHIFT)) & IOMUXD_SPI2_SDI_PULL_MASK) #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_SHIFT (7U) /*! SPI2_SDI_reserved_7_18 - reserved */ #define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_MASK) #define IOMUXD_SPI2_SDI_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI2_SDI_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI2_SDI_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SDI_WAKEUP_CTRL_MASK) #define IOMUXD_SPI2_SDI_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI2_SDI_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI2_SDI_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SDI_WAKEUP_MASK_MASK) #define IOMUXD_SPI2_SDI_lp_config_MASK (0x1800000U) #define IOMUXD_SPI2_SDI_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI2_SDI_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_lp_config_SHIFT)) & IOMUXD_SPI2_SDI_lp_config_MASK) #define IOMUXD_SPI2_SDI_sw_config_MASK (0x6000000U) #define IOMUXD_SPI2_SDI_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI2_SDI_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_sw_config_SHIFT)) & IOMUXD_SPI2_SDI_sw_config_MASK) #define IOMUXD_SPI2_SDI_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI2_SDI_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI2.SDI * 0b100..LSIO.GPIO1.IO02 */ #define IOMUXD_SPI2_SDI_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_mux_mode_SHIFT)) & IOMUXD_SPI2_SDI_mux_mode_MASK) #define IOMUXD_SPI2_SDI_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI2_SDI_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI2_SDI_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SDI_update_pad_ctl_MASK) #define IOMUXD_SPI2_SDI_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI2_SDI_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI2_SDI_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SDI_update_mux_mode_MASK) /*! @} */ /*! @name SPI2_SCK - SPI2_SCK */ /*! @{ */ #define IOMUXD_SPI2_SCK_PDRV_MASK (0x1U) #define IOMUXD_SPI2_SCK_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI2_SCK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_PDRV_SHIFT)) & IOMUXD_SPI2_SCK_PDRV_MASK) #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_SHIFT (1U) /*! SPI2_SCK_reserved_1_4 - reserved */ #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_MASK) #define IOMUXD_SPI2_SCK_PULL_MASK (0x60U) #define IOMUXD_SPI2_SCK_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI2_SCK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_PULL_SHIFT)) & IOMUXD_SPI2_SCK_PULL_MASK) #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_SHIFT (7U) /*! SPI2_SCK_reserved_7_18 - reserved */ #define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_MASK) #define IOMUXD_SPI2_SCK_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI2_SCK_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI2_SCK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SCK_WAKEUP_CTRL_MASK) #define IOMUXD_SPI2_SCK_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI2_SCK_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI2_SCK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SCK_WAKEUP_MASK_MASK) #define IOMUXD_SPI2_SCK_lp_config_MASK (0x1800000U) #define IOMUXD_SPI2_SCK_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI2_SCK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_lp_config_SHIFT)) & IOMUXD_SPI2_SCK_lp_config_MASK) #define IOMUXD_SPI2_SCK_sw_config_MASK (0x6000000U) #define IOMUXD_SPI2_SCK_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI2_SCK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_sw_config_SHIFT)) & IOMUXD_SPI2_SCK_sw_config_MASK) #define IOMUXD_SPI2_SCK_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI2_SCK_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI2.SCK * 0b100..LSIO.GPIO1.IO03 */ #define IOMUXD_SPI2_SCK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_mux_mode_SHIFT)) & IOMUXD_SPI2_SCK_mux_mode_MASK) #define IOMUXD_SPI2_SCK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI2_SCK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI2_SCK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SCK_update_pad_ctl_MASK) #define IOMUXD_SPI2_SCK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI2_SCK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI2_SCK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SCK_update_mux_mode_MASK) /*! @} */ /*! @name SPI0_SCK - SPI0_SCK */ /*! @{ */ #define IOMUXD_SPI0_SCK_PDRV_MASK (0x1U) #define IOMUXD_SPI0_SCK_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI0_SCK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_PDRV_SHIFT)) & IOMUXD_SPI0_SCK_PDRV_MASK) #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_SHIFT (1U) /*! SPI0_SCK_reserved_1_4 - reserved */ #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_MASK) #define IOMUXD_SPI0_SCK_PULL_MASK (0x60U) #define IOMUXD_SPI0_SCK_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI0_SCK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_PULL_SHIFT)) & IOMUXD_SPI0_SCK_PULL_MASK) #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_SHIFT (7U) /*! SPI0_SCK_reserved_7_18 - reserved */ #define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_MASK) #define IOMUXD_SPI0_SCK_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI0_SCK_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI0_SCK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SCK_WAKEUP_CTRL_MASK) #define IOMUXD_SPI0_SCK_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI0_SCK_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI0_SCK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SCK_WAKEUP_MASK_MASK) #define IOMUXD_SPI0_SCK_lp_config_MASK (0x1800000U) #define IOMUXD_SPI0_SCK_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI0_SCK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_lp_config_SHIFT)) & IOMUXD_SPI0_SCK_lp_config_MASK) #define IOMUXD_SPI0_SCK_sw_config_MASK (0x6000000U) #define IOMUXD_SPI0_SCK_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI0_SCK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_sw_config_SHIFT)) & IOMUXD_SPI0_SCK_sw_config_MASK) #define IOMUXD_SPI0_SCK_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI0_SCK_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI0.SCK * 0b001..ADMA.SAI0.TXC * 0b010..M40.I2C0.SCL * 0b011..M40.GPIO0.IO00 * 0b100..LSIO.GPIO1.IO04 */ #define IOMUXD_SPI0_SCK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_mux_mode_SHIFT)) & IOMUXD_SPI0_SCK_mux_mode_MASK) #define IOMUXD_SPI0_SCK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI0_SCK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI0_SCK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SCK_update_pad_ctl_MASK) #define IOMUXD_SPI0_SCK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI0_SCK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI0_SCK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SCK_update_mux_mode_MASK) /*! @} */ /*! @name SPI0_SDI - SPI0_SDI */ /*! @{ */ #define IOMUXD_SPI0_SDI_PDRV_MASK (0x1U) #define IOMUXD_SPI0_SDI_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI0_SDI_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_PDRV_SHIFT)) & IOMUXD_SPI0_SDI_PDRV_MASK) #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_SHIFT (1U) /*! SPI0_SDI_reserved_1_4 - reserved */ #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_MASK) #define IOMUXD_SPI0_SDI_PULL_MASK (0x60U) #define IOMUXD_SPI0_SDI_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI0_SDI_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_PULL_SHIFT)) & IOMUXD_SPI0_SDI_PULL_MASK) #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_SHIFT (7U) /*! SPI0_SDI_reserved_7_18 - reserved */ #define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_MASK) #define IOMUXD_SPI0_SDI_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI0_SDI_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI0_SDI_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SDI_WAKEUP_CTRL_MASK) #define IOMUXD_SPI0_SDI_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI0_SDI_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI0_SDI_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SDI_WAKEUP_MASK_MASK) #define IOMUXD_SPI0_SDI_lp_config_MASK (0x1800000U) #define IOMUXD_SPI0_SDI_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI0_SDI_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_lp_config_SHIFT)) & IOMUXD_SPI0_SDI_lp_config_MASK) #define IOMUXD_SPI0_SDI_sw_config_MASK (0x6000000U) #define IOMUXD_SPI0_SDI_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI0_SDI_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_sw_config_SHIFT)) & IOMUXD_SPI0_SDI_sw_config_MASK) #define IOMUXD_SPI0_SDI_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI0_SDI_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI0.SDI * 0b001..ADMA.SAI0.TXD * 0b010..M40.TPM0.CH0 * 0b011..M40.GPIO0.IO02 * 0b100..LSIO.GPIO1.IO05 */ #define IOMUXD_SPI0_SDI_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_mux_mode_SHIFT)) & IOMUXD_SPI0_SDI_mux_mode_MASK) #define IOMUXD_SPI0_SDI_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI0_SDI_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI0_SDI_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SDI_update_pad_ctl_MASK) #define IOMUXD_SPI0_SDI_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI0_SDI_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI0_SDI_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SDI_update_mux_mode_MASK) /*! @} */ /*! @name SPI0_SDO - SPI0_SDO */ /*! @{ */ #define IOMUXD_SPI0_SDO_PDRV_MASK (0x1U) #define IOMUXD_SPI0_SDO_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI0_SDO_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_PDRV_SHIFT)) & IOMUXD_SPI0_SDO_PDRV_MASK) #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_SHIFT (1U) /*! SPI0_SDO_reserved_1_4 - reserved */ #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_MASK) #define IOMUXD_SPI0_SDO_PULL_MASK (0x60U) #define IOMUXD_SPI0_SDO_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI0_SDO_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_PULL_SHIFT)) & IOMUXD_SPI0_SDO_PULL_MASK) #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_SHIFT (7U) /*! SPI0_SDO_reserved_7_18 - reserved */ #define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_MASK) #define IOMUXD_SPI0_SDO_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI0_SDO_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI0_SDO_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SDO_WAKEUP_CTRL_MASK) #define IOMUXD_SPI0_SDO_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI0_SDO_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI0_SDO_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SDO_WAKEUP_MASK_MASK) #define IOMUXD_SPI0_SDO_lp_config_MASK (0x1800000U) #define IOMUXD_SPI0_SDO_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI0_SDO_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_lp_config_SHIFT)) & IOMUXD_SPI0_SDO_lp_config_MASK) #define IOMUXD_SPI0_SDO_sw_config_MASK (0x6000000U) #define IOMUXD_SPI0_SDO_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI0_SDO_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_sw_config_SHIFT)) & IOMUXD_SPI0_SDO_sw_config_MASK) #define IOMUXD_SPI0_SDO_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI0_SDO_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI0.SDO * 0b001..ADMA.SAI0.TXFS * 0b010..M40.I2C0.SDA * 0b011..M40.GPIO0.IO01 * 0b100..LSIO.GPIO1.IO06 */ #define IOMUXD_SPI0_SDO_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_mux_mode_SHIFT)) & IOMUXD_SPI0_SDO_mux_mode_MASK) #define IOMUXD_SPI0_SDO_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI0_SDO_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI0_SDO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SDO_update_pad_ctl_MASK) #define IOMUXD_SPI0_SDO_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI0_SDO_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI0_SDO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SDO_update_mux_mode_MASK) /*! @} */ /*! @name SPI0_CS1 - SPI0_CS1 */ /*! @{ */ #define IOMUXD_SPI0_CS1_PDRV_MASK (0x1U) #define IOMUXD_SPI0_CS1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI0_CS1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_PDRV_SHIFT)) & IOMUXD_SPI0_CS1_PDRV_MASK) #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_SHIFT (1U) /*! SPI0_CS1_reserved_1_4 - reserved */ #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_SHIFT)) & IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_MASK) #define IOMUXD_SPI0_CS1_PULL_MASK (0x60U) #define IOMUXD_SPI0_CS1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI0_CS1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_PULL_SHIFT)) & IOMUXD_SPI0_CS1_PULL_MASK) #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_SHIFT (7U) /*! SPI0_CS1_reserved_7_18 - reserved */ #define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_SHIFT)) & IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_MASK) #define IOMUXD_SPI0_CS1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI0_CS1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI0_CS1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_CS1_WAKEUP_CTRL_MASK) #define IOMUXD_SPI0_CS1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI0_CS1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI0_CS1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_CS1_WAKEUP_MASK_MASK) #define IOMUXD_SPI0_CS1_lp_config_MASK (0x1800000U) #define IOMUXD_SPI0_CS1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI0_CS1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_lp_config_SHIFT)) & IOMUXD_SPI0_CS1_lp_config_MASK) #define IOMUXD_SPI0_CS1_sw_config_MASK (0x6000000U) #define IOMUXD_SPI0_CS1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI0_CS1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_sw_config_SHIFT)) & IOMUXD_SPI0_CS1_sw_config_MASK) #define IOMUXD_SPI0_CS1_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI0_CS1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI0.CS1 * 0b001..ADMA.SAI0.RXC * 0b010..ADMA.SAI1.TXD * 0b011..ADMA.LCD_PWM0.OUT * 0b100..LSIO.GPIO1.IO07 */ #define IOMUXD_SPI0_CS1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_mux_mode_SHIFT)) & IOMUXD_SPI0_CS1_mux_mode_MASK) #define IOMUXD_SPI0_CS1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI0_CS1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI0_CS1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_CS1_update_pad_ctl_MASK) #define IOMUXD_SPI0_CS1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI0_CS1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI0_CS1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_update_mux_mode_SHIFT)) & IOMUXD_SPI0_CS1_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_2_0 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_SHIFT (0U) /*! SAI0_TXD - wakeup from SAI0_TXD */ #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_SHIFT (1U) /*! SAI0_TXC - wakeup from SAI0_TXC */ #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_SHIFT (2U) /*! SAI0_RXD - wakeup from SAI0_RXD */ #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_SHIFT (3U) /*! SAI0_TXFS - wakeup from SAI0_TXFS */ #define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_SHIFT (4U) /*! SAI1_RXD - wakeup from SAI1_RXD */ #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_SHIFT (5U) /*! SAI1_RXC - wakeup from SAI1_RXC */ #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_SHIFT (6U) /*! SAI1_RXFS - wakeup from SAI1_RXFS */ #define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_SHIFT (7U) /*! SPI2_CS0 - wakeup from SPI2_CS0 */ #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_SHIFT (8U) /*! SPI2_SDO - wakeup from SPI2_SDO */ #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_SHIFT (9U) /*! SPI2_SDI - wakeup from SPI2_SDI */ #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_SHIFT (10U) /*! SPI2_SCK - wakeup from SPI2_SCK */ #define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_SHIFT (11U) /*! SPI0_SCK - wakeup from SPI0_SCK */ #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_SHIFT (12U) /*! SPI0_SDI - wakeup from SPI0_SDI */ #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_MASK (0x2000U) #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_SHIFT (13U) /*! SPI0_SDO - wakeup from SPI0_SDO */ #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_MASK (0x4000U) #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_SHIFT (14U) /*! SPI0_CS1 - wakeup from SPI0_CS1 */ #define IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_MASK) #define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_MASK (0xFFFF8000U) #define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_SHIFT (15U) /*! iomuxd_group_2_0_reserved_15_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_MASK) /*! @} */ /*! @name SPI0_CS0 - SPI0_CS0 */ /*! @{ */ #define IOMUXD_SPI0_CS0_PDRV_MASK (0x1U) #define IOMUXD_SPI0_CS0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_SPI0_CS0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_PDRV_SHIFT)) & IOMUXD_SPI0_CS0_PDRV_MASK) #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_MASK (0x1EU) #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_SHIFT (1U) /*! SPI0_CS0_reserved_1_4 - reserved */ #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_MASK) #define IOMUXD_SPI0_CS0_PULL_MASK (0x60U) #define IOMUXD_SPI0_CS0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_SPI0_CS0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_PULL_SHIFT)) & IOMUXD_SPI0_CS0_PULL_MASK) #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_SHIFT (7U) /*! SPI0_CS0_reserved_7_18 - reserved */ #define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_MASK) #define IOMUXD_SPI0_CS0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SPI0_CS0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SPI0_CS0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_CS0_WAKEUP_CTRL_MASK) #define IOMUXD_SPI0_CS0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SPI0_CS0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SPI0_CS0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_CS0_WAKEUP_MASK_MASK) #define IOMUXD_SPI0_CS0_lp_config_MASK (0x1800000U) #define IOMUXD_SPI0_CS0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SPI0_CS0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_lp_config_SHIFT)) & IOMUXD_SPI0_CS0_lp_config_MASK) #define IOMUXD_SPI0_CS0_sw_config_MASK (0x6000000U) #define IOMUXD_SPI0_CS0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SPI0_CS0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_sw_config_SHIFT)) & IOMUXD_SPI0_CS0_sw_config_MASK) #define IOMUXD_SPI0_CS0_mux_mode_MASK (0x38000000U) #define IOMUXD_SPI0_CS0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.SPI0.CS0 * 0b001..ADMA.SAI0.RXD * 0b010..M40.TPM0.CH1 * 0b011..M40.GPIO0.IO03 * 0b100..LSIO.GPIO1.IO08 */ #define IOMUXD_SPI0_CS0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_mux_mode_SHIFT)) & IOMUXD_SPI0_CS0_mux_mode_MASK) #define IOMUXD_SPI0_CS0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SPI0_CS0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SPI0_CS0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_CS0_update_pad_ctl_MASK) #define IOMUXD_SPI0_CS0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SPI0_CS0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SPI0_CS0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI0_CS0_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_MASK) /*! @} */ /*! @name ADC_IN1 - ADC_IN1 */ /*! @{ */ #define IOMUXD_ADC_IN1_DSE_MASK (0x7U) #define IOMUXD_ADC_IN1_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_ADC_IN1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_DSE_SHIFT)) & IOMUXD_ADC_IN1_DSE_MASK) #define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_MASK (0x18U) #define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_SHIFT (3U) /*! ADC_IN1_reserved_3_4 - reserved */ #define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_MASK) #define IOMUXD_ADC_IN1_PULL_MASK (0x60U) #define IOMUXD_ADC_IN1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_ADC_IN1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_PULL_SHIFT)) & IOMUXD_ADC_IN1_PULL_MASK) #define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_SHIFT (7U) /*! ADC_IN1_reserved_7_18 - reserved */ #define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_MASK) #define IOMUXD_ADC_IN1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ADC_IN1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ADC_IN1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN1_WAKEUP_CTRL_MASK) #define IOMUXD_ADC_IN1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ADC_IN1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ADC_IN1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN1_WAKEUP_MASK_MASK) #define IOMUXD_ADC_IN1_lp_config_MASK (0x1800000U) #define IOMUXD_ADC_IN1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ADC_IN1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_lp_config_SHIFT)) & IOMUXD_ADC_IN1_lp_config_MASK) #define IOMUXD_ADC_IN1_sw_config_MASK (0x6000000U) #define IOMUXD_ADC_IN1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ADC_IN1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_sw_config_SHIFT)) & IOMUXD_ADC_IN1_sw_config_MASK) #define IOMUXD_ADC_IN1_mux_mode_MASK (0x38000000U) #define IOMUXD_ADC_IN1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ADC.IN1 * 0b001..M40.I2C0.SDA * 0b010..M40.GPIO0.IO01 * 0b100..LSIO.GPIO1.IO09 */ #define IOMUXD_ADC_IN1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_mux_mode_SHIFT)) & IOMUXD_ADC_IN1_mux_mode_MASK) #define IOMUXD_ADC_IN1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ADC_IN1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ADC_IN1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN1_update_pad_ctl_MASK) #define IOMUXD_ADC_IN1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ADC_IN1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ADC_IN1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN1_update_mux_mode_MASK) /*! @} */ /*! @name ADC_IN0 - ADC_IN0 */ /*! @{ */ #define IOMUXD_ADC_IN0_DSE_MASK (0x7U) #define IOMUXD_ADC_IN0_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_ADC_IN0_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_DSE_SHIFT)) & IOMUXD_ADC_IN0_DSE_MASK) #define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_MASK (0x18U) #define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_SHIFT (3U) /*! ADC_IN0_reserved_3_4 - reserved */ #define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_MASK) #define IOMUXD_ADC_IN0_PULL_MASK (0x60U) #define IOMUXD_ADC_IN0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_ADC_IN0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_PULL_SHIFT)) & IOMUXD_ADC_IN0_PULL_MASK) #define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_SHIFT (7U) /*! ADC_IN0_reserved_7_18 - reserved */ #define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_MASK) #define IOMUXD_ADC_IN0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ADC_IN0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ADC_IN0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN0_WAKEUP_CTRL_MASK) #define IOMUXD_ADC_IN0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ADC_IN0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ADC_IN0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN0_WAKEUP_MASK_MASK) #define IOMUXD_ADC_IN0_lp_config_MASK (0x1800000U) #define IOMUXD_ADC_IN0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ADC_IN0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_lp_config_SHIFT)) & IOMUXD_ADC_IN0_lp_config_MASK) #define IOMUXD_ADC_IN0_sw_config_MASK (0x6000000U) #define IOMUXD_ADC_IN0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ADC_IN0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_sw_config_SHIFT)) & IOMUXD_ADC_IN0_sw_config_MASK) #define IOMUXD_ADC_IN0_mux_mode_MASK (0x38000000U) #define IOMUXD_ADC_IN0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ADC.IN0 * 0b001..M40.I2C0.SCL * 0b010..M40.GPIO0.IO00 * 0b100..LSIO.GPIO1.IO10 */ #define IOMUXD_ADC_IN0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_mux_mode_SHIFT)) & IOMUXD_ADC_IN0_mux_mode_MASK) #define IOMUXD_ADC_IN0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ADC_IN0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ADC_IN0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN0_update_pad_ctl_MASK) #define IOMUXD_ADC_IN0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ADC_IN0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ADC_IN0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN0_update_mux_mode_MASK) /*! @} */ /*! @name ADC_IN3 - ADC_IN3 */ /*! @{ */ #define IOMUXD_ADC_IN3_DSE_MASK (0x7U) #define IOMUXD_ADC_IN3_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_ADC_IN3_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_DSE_SHIFT)) & IOMUXD_ADC_IN3_DSE_MASK) #define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_MASK (0x18U) #define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_SHIFT (3U) /*! ADC_IN3_reserved_3_4 - reserved */ #define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_MASK) #define IOMUXD_ADC_IN3_PULL_MASK (0x60U) #define IOMUXD_ADC_IN3_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_ADC_IN3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_PULL_SHIFT)) & IOMUXD_ADC_IN3_PULL_MASK) #define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_SHIFT (7U) /*! ADC_IN3_reserved_7_18 - reserved */ #define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_MASK) #define IOMUXD_ADC_IN3_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ADC_IN3_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ADC_IN3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN3_WAKEUP_CTRL_MASK) #define IOMUXD_ADC_IN3_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ADC_IN3_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ADC_IN3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN3_WAKEUP_MASK_MASK) #define IOMUXD_ADC_IN3_lp_config_MASK (0x1800000U) #define IOMUXD_ADC_IN3_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ADC_IN3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_lp_config_SHIFT)) & IOMUXD_ADC_IN3_lp_config_MASK) #define IOMUXD_ADC_IN3_sw_config_MASK (0x6000000U) #define IOMUXD_ADC_IN3_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ADC_IN3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_sw_config_SHIFT)) & IOMUXD_ADC_IN3_sw_config_MASK) #define IOMUXD_ADC_IN3_mux_mode_MASK (0x38000000U) #define IOMUXD_ADC_IN3_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ADC.IN3 * 0b001..M40.UART0.TX * 0b010..M40.GPIO0.IO03 * 0b011..ADMA.ACM.MCLK_OUT0 * 0b100..LSIO.GPIO1.IO11 */ #define IOMUXD_ADC_IN3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_mux_mode_SHIFT)) & IOMUXD_ADC_IN3_mux_mode_MASK) #define IOMUXD_ADC_IN3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ADC_IN3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ADC_IN3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN3_update_pad_ctl_MASK) #define IOMUXD_ADC_IN3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ADC_IN3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ADC_IN3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN3_update_mux_mode_MASK) /*! @} */ /*! @name ADC_IN2 - ADC_IN2 */ /*! @{ */ #define IOMUXD_ADC_IN2_DSE_MASK (0x7U) #define IOMUXD_ADC_IN2_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_ADC_IN2_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_DSE_SHIFT)) & IOMUXD_ADC_IN2_DSE_MASK) #define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_MASK (0x18U) #define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_SHIFT (3U) /*! ADC_IN2_reserved_3_4 - reserved */ #define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_MASK) #define IOMUXD_ADC_IN2_PULL_MASK (0x60U) #define IOMUXD_ADC_IN2_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_ADC_IN2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_PULL_SHIFT)) & IOMUXD_ADC_IN2_PULL_MASK) #define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_SHIFT (7U) /*! ADC_IN2_reserved_7_18 - reserved */ #define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_MASK) #define IOMUXD_ADC_IN2_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ADC_IN2_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ADC_IN2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN2_WAKEUP_CTRL_MASK) #define IOMUXD_ADC_IN2_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ADC_IN2_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ADC_IN2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN2_WAKEUP_MASK_MASK) #define IOMUXD_ADC_IN2_lp_config_MASK (0x1800000U) #define IOMUXD_ADC_IN2_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ADC_IN2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_lp_config_SHIFT)) & IOMUXD_ADC_IN2_lp_config_MASK) #define IOMUXD_ADC_IN2_sw_config_MASK (0x6000000U) #define IOMUXD_ADC_IN2_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ADC_IN2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_sw_config_SHIFT)) & IOMUXD_ADC_IN2_sw_config_MASK) #define IOMUXD_ADC_IN2_mux_mode_MASK (0x38000000U) #define IOMUXD_ADC_IN2_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ADC.IN2 * 0b001..M40.UART0.RX * 0b010..M40.GPIO0.IO02 * 0b011..ADMA.ACM.MCLK_IN0 * 0b100..LSIO.GPIO1.IO12 */ #define IOMUXD_ADC_IN2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_mux_mode_SHIFT)) & IOMUXD_ADC_IN2_mux_mode_MASK) #define IOMUXD_ADC_IN2_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ADC_IN2_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ADC_IN2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN2_update_pad_ctl_MASK) #define IOMUXD_ADC_IN2_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ADC_IN2_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ADC_IN2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN2_update_mux_mode_MASK) /*! @} */ /*! @name ADC_IN5 - ADC_IN5 */ /*! @{ */ #define IOMUXD_ADC_IN5_DSE_MASK (0x7U) #define IOMUXD_ADC_IN5_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_ADC_IN5_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_DSE_SHIFT)) & IOMUXD_ADC_IN5_DSE_MASK) #define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_MASK (0x18U) #define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_SHIFT (3U) /*! ADC_IN5_reserved_3_4 - reserved */ #define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_MASK) #define IOMUXD_ADC_IN5_PULL_MASK (0x60U) #define IOMUXD_ADC_IN5_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_ADC_IN5_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_PULL_SHIFT)) & IOMUXD_ADC_IN5_PULL_MASK) #define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_SHIFT (7U) /*! ADC_IN5_reserved_7_18 - reserved */ #define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_MASK) #define IOMUXD_ADC_IN5_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ADC_IN5_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ADC_IN5_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN5_WAKEUP_CTRL_MASK) #define IOMUXD_ADC_IN5_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ADC_IN5_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ADC_IN5_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN5_WAKEUP_MASK_MASK) #define IOMUXD_ADC_IN5_lp_config_MASK (0x1800000U) #define IOMUXD_ADC_IN5_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ADC_IN5_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_lp_config_SHIFT)) & IOMUXD_ADC_IN5_lp_config_MASK) #define IOMUXD_ADC_IN5_sw_config_MASK (0x6000000U) #define IOMUXD_ADC_IN5_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ADC_IN5_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_sw_config_SHIFT)) & IOMUXD_ADC_IN5_sw_config_MASK) #define IOMUXD_ADC_IN5_mux_mode_MASK (0x38000000U) #define IOMUXD_ADC_IN5_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ADC.IN5 * 0b001..M40.TPM0.CH1 * 0b010..M40.GPIO0.IO05 * 0b100..LSIO.GPIO1.IO13 */ #define IOMUXD_ADC_IN5_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_mux_mode_SHIFT)) & IOMUXD_ADC_IN5_mux_mode_MASK) #define IOMUXD_ADC_IN5_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ADC_IN5_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ADC_IN5_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN5_update_pad_ctl_MASK) #define IOMUXD_ADC_IN5_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ADC_IN5_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ADC_IN5_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN5_update_mux_mode_MASK) /*! @} */ /*! @name ADC_IN4 - ADC_IN4 */ /*! @{ */ #define IOMUXD_ADC_IN4_DSE_MASK (0x7U) #define IOMUXD_ADC_IN4_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_ADC_IN4_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_DSE_SHIFT)) & IOMUXD_ADC_IN4_DSE_MASK) #define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_MASK (0x18U) #define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_SHIFT (3U) /*! ADC_IN4_reserved_3_4 - reserved */ #define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_MASK) #define IOMUXD_ADC_IN4_PULL_MASK (0x60U) #define IOMUXD_ADC_IN4_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_ADC_IN4_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_PULL_SHIFT)) & IOMUXD_ADC_IN4_PULL_MASK) #define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_SHIFT (7U) /*! ADC_IN4_reserved_7_18 - reserved */ #define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_MASK) #define IOMUXD_ADC_IN4_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_ADC_IN4_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_ADC_IN4_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN4_WAKEUP_CTRL_MASK) #define IOMUXD_ADC_IN4_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_ADC_IN4_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_ADC_IN4_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN4_WAKEUP_MASK_MASK) #define IOMUXD_ADC_IN4_lp_config_MASK (0x1800000U) #define IOMUXD_ADC_IN4_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_ADC_IN4_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_lp_config_SHIFT)) & IOMUXD_ADC_IN4_lp_config_MASK) #define IOMUXD_ADC_IN4_sw_config_MASK (0x6000000U) #define IOMUXD_ADC_IN4_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_ADC_IN4_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_sw_config_SHIFT)) & IOMUXD_ADC_IN4_sw_config_MASK) #define IOMUXD_ADC_IN4_mux_mode_MASK (0x38000000U) #define IOMUXD_ADC_IN4_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.ADC.IN4 * 0b001..M40.TPM0.CH0 * 0b010..M40.GPIO0.IO04 * 0b100..LSIO.GPIO1.IO14 */ #define IOMUXD_ADC_IN4_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_mux_mode_SHIFT)) & IOMUXD_ADC_IN4_mux_mode_MASK) #define IOMUXD_ADC_IN4_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_ADC_IN4_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_ADC_IN4_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN4_update_pad_ctl_MASK) #define IOMUXD_ADC_IN4_update_mux_mode_MASK (0x80000000U) #define IOMUXD_ADC_IN4_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_ADC_IN4_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN4_update_mux_mode_MASK) /*! @} */ /*! @name FLEXCAN0_RX - FLEXCAN0_RX */ /*! @{ */ #define IOMUXD_FLEXCAN0_RX_PDRV_MASK (0x1U) #define IOMUXD_FLEXCAN0_RX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_FLEXCAN0_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN0_RX_PDRV_MASK) #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_MASK (0x1EU) #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_SHIFT (1U) /*! FLEXCAN0_RX_reserved_1_4 - reserved */ #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_MASK) #define IOMUXD_FLEXCAN0_RX_PULL_MASK (0x60U) #define IOMUXD_FLEXCAN0_RX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_FLEXCAN0_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN0_RX_PULL_MASK) #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_SHIFT (7U) /*! FLEXCAN0_RX_reserved_7_18 - reserved */ #define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_MASK) #define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_MASK) #define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_MASK) #define IOMUXD_FLEXCAN0_RX_lp_config_MASK (0x1800000U) #define IOMUXD_FLEXCAN0_RX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_FLEXCAN0_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN0_RX_lp_config_MASK) #define IOMUXD_FLEXCAN0_RX_sw_config_MASK (0x6000000U) #define IOMUXD_FLEXCAN0_RX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_FLEXCAN0_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN0_RX_sw_config_MASK) #define IOMUXD_FLEXCAN0_RX_mux_mode_MASK (0x38000000U) #define IOMUXD_FLEXCAN0_RX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.FLEXCAN0.RX * 0b001..ADMA.SAI2.RXC * 0b010..ADMA.UART0.RTS_B * 0b011..ADMA.SAI1.TXC * 0b100..LSIO.GPIO1.IO15 */ #define IOMUXD_FLEXCAN0_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_RX_mux_mode_MASK) #define IOMUXD_FLEXCAN0_RX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_FLEXCAN0_RX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_FLEXCAN0_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN0_RX_update_pad_ctl_MASK) #define IOMUXD_FLEXCAN0_RX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_FLEXCAN0_RX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_FLEXCAN0_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_RX_update_mux_mode_MASK) /*! @} */ /*! @name FLEXCAN0_TX - FLEXCAN0_TX */ /*! @{ */ #define IOMUXD_FLEXCAN0_TX_PDRV_MASK (0x1U) #define IOMUXD_FLEXCAN0_TX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_FLEXCAN0_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN0_TX_PDRV_MASK) #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_MASK (0x1EU) #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_SHIFT (1U) /*! FLEXCAN0_TX_reserved_1_4 - reserved */ #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_MASK) #define IOMUXD_FLEXCAN0_TX_PULL_MASK (0x60U) #define IOMUXD_FLEXCAN0_TX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_FLEXCAN0_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN0_TX_PULL_MASK) #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_SHIFT (7U) /*! FLEXCAN0_TX_reserved_7_18 - reserved */ #define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_MASK) #define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_MASK) #define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_MASK) #define IOMUXD_FLEXCAN0_TX_lp_config_MASK (0x1800000U) #define IOMUXD_FLEXCAN0_TX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_FLEXCAN0_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN0_TX_lp_config_MASK) #define IOMUXD_FLEXCAN0_TX_sw_config_MASK (0x6000000U) #define IOMUXD_FLEXCAN0_TX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_FLEXCAN0_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN0_TX_sw_config_MASK) #define IOMUXD_FLEXCAN0_TX_mux_mode_MASK (0x38000000U) #define IOMUXD_FLEXCAN0_TX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.FLEXCAN0.TX * 0b001..ADMA.SAI2.RXD * 0b010..ADMA.UART0.CTS_B * 0b011..ADMA.SAI1.TXFS * 0b100..LSIO.GPIO1.IO16 */ #define IOMUXD_FLEXCAN0_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_TX_mux_mode_MASK) #define IOMUXD_FLEXCAN0_TX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_FLEXCAN0_TX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_FLEXCAN0_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN0_TX_update_pad_ctl_MASK) #define IOMUXD_FLEXCAN0_TX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_FLEXCAN0_TX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_FLEXCAN0_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_TX_update_mux_mode_MASK) /*! @} */ /*! @name FLEXCAN1_RX - FLEXCAN1_RX */ /*! @{ */ #define IOMUXD_FLEXCAN1_RX_PDRV_MASK (0x1U) #define IOMUXD_FLEXCAN1_RX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_FLEXCAN1_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN1_RX_PDRV_MASK) #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_MASK (0x1EU) #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_SHIFT (1U) /*! FLEXCAN1_RX_reserved_1_4 - reserved */ #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_MASK) #define IOMUXD_FLEXCAN1_RX_PULL_MASK (0x60U) #define IOMUXD_FLEXCAN1_RX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_FLEXCAN1_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN1_RX_PULL_MASK) #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_SHIFT (7U) /*! FLEXCAN1_RX_reserved_7_18 - reserved */ #define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_MASK) #define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_MASK) #define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_MASK) #define IOMUXD_FLEXCAN1_RX_lp_config_MASK (0x1800000U) #define IOMUXD_FLEXCAN1_RX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_FLEXCAN1_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN1_RX_lp_config_MASK) #define IOMUXD_FLEXCAN1_RX_sw_config_MASK (0x6000000U) #define IOMUXD_FLEXCAN1_RX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_FLEXCAN1_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN1_RX_sw_config_MASK) #define IOMUXD_FLEXCAN1_RX_mux_mode_MASK (0x38000000U) #define IOMUXD_FLEXCAN1_RX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.FLEXCAN1.RX * 0b001..ADMA.SAI2.RXFS * 0b010..ADMA.FTM.CH2 * 0b011..ADMA.SAI1.TXD * 0b100..LSIO.GPIO1.IO17 */ #define IOMUXD_FLEXCAN1_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_RX_mux_mode_MASK) #define IOMUXD_FLEXCAN1_RX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_FLEXCAN1_RX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_FLEXCAN1_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN1_RX_update_pad_ctl_MASK) #define IOMUXD_FLEXCAN1_RX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_FLEXCAN1_RX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_FLEXCAN1_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_RX_update_mux_mode_MASK) /*! @} */ /*! @name FLEXCAN1_TX - FLEXCAN1_TX */ /*! @{ */ #define IOMUXD_FLEXCAN1_TX_PDRV_MASK (0x1U) #define IOMUXD_FLEXCAN1_TX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_FLEXCAN1_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN1_TX_PDRV_MASK) #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_MASK (0x1EU) #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_SHIFT (1U) /*! FLEXCAN1_TX_reserved_1_4 - reserved */ #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_MASK) #define IOMUXD_FLEXCAN1_TX_PULL_MASK (0x60U) #define IOMUXD_FLEXCAN1_TX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_FLEXCAN1_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN1_TX_PULL_MASK) #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_SHIFT (7U) /*! FLEXCAN1_TX_reserved_7_18 - reserved */ #define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_MASK) #define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_MASK) #define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_MASK) #define IOMUXD_FLEXCAN1_TX_lp_config_MASK (0x1800000U) #define IOMUXD_FLEXCAN1_TX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_FLEXCAN1_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN1_TX_lp_config_MASK) #define IOMUXD_FLEXCAN1_TX_sw_config_MASK (0x6000000U) #define IOMUXD_FLEXCAN1_TX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_FLEXCAN1_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN1_TX_sw_config_MASK) #define IOMUXD_FLEXCAN1_TX_mux_mode_MASK (0x38000000U) #define IOMUXD_FLEXCAN1_TX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.FLEXCAN1.TX * 0b001..ADMA.SAI3.RXC * 0b010..ADMA.DMA0.REQ_IN0 * 0b011..ADMA.SAI1.RXD * 0b100..LSIO.GPIO1.IO18 */ #define IOMUXD_FLEXCAN1_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_TX_mux_mode_MASK) #define IOMUXD_FLEXCAN1_TX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_FLEXCAN1_TX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_FLEXCAN1_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN1_TX_update_pad_ctl_MASK) #define IOMUXD_FLEXCAN1_TX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_FLEXCAN1_TX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_FLEXCAN1_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_TX_update_mux_mode_MASK) /*! @} */ /*! @name FLEXCAN2_RX - FLEXCAN2_RX */ /*! @{ */ #define IOMUXD_FLEXCAN2_RX_PDRV_MASK (0x1U) #define IOMUXD_FLEXCAN2_RX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_FLEXCAN2_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN2_RX_PDRV_MASK) #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_MASK (0x1EU) #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_SHIFT (1U) /*! FLEXCAN2_RX_reserved_1_4 - reserved */ #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_MASK) #define IOMUXD_FLEXCAN2_RX_PULL_MASK (0x60U) #define IOMUXD_FLEXCAN2_RX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_FLEXCAN2_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN2_RX_PULL_MASK) #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_SHIFT (7U) /*! FLEXCAN2_RX_reserved_7_18 - reserved */ #define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_MASK) #define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_MASK) #define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_MASK) #define IOMUXD_FLEXCAN2_RX_lp_config_MASK (0x1800000U) #define IOMUXD_FLEXCAN2_RX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_FLEXCAN2_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN2_RX_lp_config_MASK) #define IOMUXD_FLEXCAN2_RX_sw_config_MASK (0x6000000U) #define IOMUXD_FLEXCAN2_RX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_FLEXCAN2_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN2_RX_sw_config_MASK) #define IOMUXD_FLEXCAN2_RX_mux_mode_MASK (0x38000000U) #define IOMUXD_FLEXCAN2_RX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.FLEXCAN2.RX * 0b001..ADMA.SAI3.RXD * 0b010..ADMA.UART3.RX * 0b011..ADMA.SAI1.RXFS * 0b100..LSIO.GPIO1.IO19 */ #define IOMUXD_FLEXCAN2_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_RX_mux_mode_MASK) #define IOMUXD_FLEXCAN2_RX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_FLEXCAN2_RX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_FLEXCAN2_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN2_RX_update_pad_ctl_MASK) #define IOMUXD_FLEXCAN2_RX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_FLEXCAN2_RX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_FLEXCAN2_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_RX_update_mux_mode_MASK) /*! @} */ /*! @name FLEXCAN2_TX - FLEXCAN2_TX */ /*! @{ */ #define IOMUXD_FLEXCAN2_TX_PDRV_MASK (0x1U) #define IOMUXD_FLEXCAN2_TX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_FLEXCAN2_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN2_TX_PDRV_MASK) #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_MASK (0x1EU) #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_SHIFT (1U) /*! FLEXCAN2_TX_reserved_1_4 - reserved */ #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_MASK) #define IOMUXD_FLEXCAN2_TX_PULL_MASK (0x60U) #define IOMUXD_FLEXCAN2_TX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_FLEXCAN2_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN2_TX_PULL_MASK) #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_SHIFT (7U) /*! FLEXCAN2_TX_reserved_7_18 - reserved */ #define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_MASK) #define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_MASK) #define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_MASK) #define IOMUXD_FLEXCAN2_TX_lp_config_MASK (0x1800000U) #define IOMUXD_FLEXCAN2_TX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_FLEXCAN2_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN2_TX_lp_config_MASK) #define IOMUXD_FLEXCAN2_TX_sw_config_MASK (0x6000000U) #define IOMUXD_FLEXCAN2_TX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_FLEXCAN2_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN2_TX_sw_config_MASK) #define IOMUXD_FLEXCAN2_TX_mux_mode_MASK (0x38000000U) #define IOMUXD_FLEXCAN2_TX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.FLEXCAN2.TX * 0b001..ADMA.SAI3.RXFS * 0b010..ADMA.UART3.TX * 0b011..ADMA.SAI1.RXC * 0b100..LSIO.GPIO1.IO20 */ #define IOMUXD_FLEXCAN2_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_TX_mux_mode_MASK) #define IOMUXD_FLEXCAN2_TX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_FLEXCAN2_TX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_FLEXCAN2_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN2_TX_update_pad_ctl_MASK) #define IOMUXD_FLEXCAN2_TX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_FLEXCAN2_TX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_FLEXCAN2_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_TX_update_mux_mode_MASK) /*! @} */ /*! @name UART0_RX - UART0_RX */ /*! @{ */ #define IOMUXD_UART0_RX_PDRV_MASK (0x1U) #define IOMUXD_UART0_RX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_UART0_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_PDRV_SHIFT)) & IOMUXD_UART0_RX_PDRV_MASK) #define IOMUXD_UART0_RX_UART0_RX_reserved_1_4_MASK (0x1EU) #define IOMUXD_UART0_RX_UART0_RX_reserved_1_4_SHIFT (1U) /*! UART0_RX_reserved_1_4 - reserved */ #define IOMUXD_UART0_RX_UART0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_UART0_RX_reserved_1_4_SHIFT)) & IOMUXD_UART0_RX_UART0_RX_reserved_1_4_MASK) #define IOMUXD_UART0_RX_PULL_MASK (0x60U) #define IOMUXD_UART0_RX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_UART0_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_PULL_SHIFT)) & IOMUXD_UART0_RX_PULL_MASK) #define IOMUXD_UART0_RX_UART0_RX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_UART0_RX_UART0_RX_reserved_7_18_SHIFT (7U) /*! UART0_RX_reserved_7_18 - reserved */ #define IOMUXD_UART0_RX_UART0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_UART0_RX_reserved_7_18_SHIFT)) & IOMUXD_UART0_RX_UART0_RX_reserved_7_18_MASK) #define IOMUXD_UART0_RX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_UART0_RX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_UART0_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART0_RX_WAKEUP_CTRL_MASK) #define IOMUXD_UART0_RX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_UART0_RX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_UART0_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART0_RX_WAKEUP_MASK_MASK) #define IOMUXD_UART0_RX_lp_config_MASK (0x1800000U) #define IOMUXD_UART0_RX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_UART0_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_lp_config_SHIFT)) & IOMUXD_UART0_RX_lp_config_MASK) #define IOMUXD_UART0_RX_sw_config_MASK (0x6000000U) #define IOMUXD_UART0_RX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_UART0_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_sw_config_SHIFT)) & IOMUXD_UART0_RX_sw_config_MASK) #define IOMUXD_UART0_RX_mux_mode_MASK (0x38000000U) #define IOMUXD_UART0_RX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.UART0.RX * 0b001..ADMA.MQS.R * 0b010..ADMA.FLEXCAN0.RX * 0b011..SCU.UART0.RX * 0b100..LSIO.GPIO1.IO21 */ #define IOMUXD_UART0_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_mux_mode_SHIFT)) & IOMUXD_UART0_RX_mux_mode_MASK) #define IOMUXD_UART0_RX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_UART0_RX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_UART0_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART0_RX_update_pad_ctl_MASK) #define IOMUXD_UART0_RX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_UART0_RX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_UART0_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_update_mux_mode_SHIFT)) & IOMUXD_UART0_RX_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_2_1 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_SHIFT (0U) /*! SPI0_CS0 - wakeup from SPI0_CS0 */ #define IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_SHIFT (1U) /*! iomuxd_group_2_1_reserved_1_1 - reserved */ #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_SHIFT (2U) /*! ADC_IN1 - wakeup from ADC_IN1 */ #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_SHIFT (3U) /*! ADC_IN0 - wakeup from ADC_IN0 */ #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_SHIFT (4U) /*! ADC_IN3 - wakeup from ADC_IN3 */ #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_SHIFT (5U) /*! ADC_IN2 - wakeup from ADC_IN2 */ #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_SHIFT (6U) /*! ADC_IN5 - wakeup from ADC_IN5 */ #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_SHIFT (7U) /*! ADC_IN4 - wakeup from ADC_IN4 */ #define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_SHIFT (8U) /*! FLEXCAN0_RX - wakeup from FLEXCAN0_RX */ #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_SHIFT (9U) /*! FLEXCAN0_TX - wakeup from FLEXCAN0_TX */ #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_SHIFT (10U) /*! FLEXCAN1_RX - wakeup from FLEXCAN1_RX */ #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_SHIFT (11U) /*! FLEXCAN1_TX - wakeup from FLEXCAN1_TX */ #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_SHIFT (12U) /*! FLEXCAN2_RX - wakeup from FLEXCAN2_RX */ #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_MASK (0x2000U) #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_SHIFT (13U) /*! FLEXCAN2_TX - wakeup from FLEXCAN2_TX */ #define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_MASK (0x4000U) #define IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_SHIFT (14U) /*! UART0_RX - wakeup from UART0_RX */ #define IOMUXD_IOMUXD_GROUP_2_1_UART0_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_MASK) #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_MASK (0xFFFF8000U) #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_SHIFT (15U) /*! iomuxd_group_2_1_reserved_15_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_MASK) /*! @} */ /*! @name UART0_TX - UART0_TX */ /*! @{ */ #define IOMUXD_UART0_TX_PDRV_MASK (0x1U) #define IOMUXD_UART0_TX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_UART0_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_PDRV_SHIFT)) & IOMUXD_UART0_TX_PDRV_MASK) #define IOMUXD_UART0_TX_UART0_TX_reserved_1_4_MASK (0x1EU) #define IOMUXD_UART0_TX_UART0_TX_reserved_1_4_SHIFT (1U) /*! UART0_TX_reserved_1_4 - reserved */ #define IOMUXD_UART0_TX_UART0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_UART0_TX_reserved_1_4_SHIFT)) & IOMUXD_UART0_TX_UART0_TX_reserved_1_4_MASK) #define IOMUXD_UART0_TX_PULL_MASK (0x60U) #define IOMUXD_UART0_TX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_UART0_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_PULL_SHIFT)) & IOMUXD_UART0_TX_PULL_MASK) #define IOMUXD_UART0_TX_UART0_TX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_UART0_TX_UART0_TX_reserved_7_18_SHIFT (7U) /*! UART0_TX_reserved_7_18 - reserved */ #define IOMUXD_UART0_TX_UART0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_UART0_TX_reserved_7_18_SHIFT)) & IOMUXD_UART0_TX_UART0_TX_reserved_7_18_MASK) #define IOMUXD_UART0_TX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_UART0_TX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_UART0_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART0_TX_WAKEUP_CTRL_MASK) #define IOMUXD_UART0_TX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_UART0_TX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_UART0_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART0_TX_WAKEUP_MASK_MASK) #define IOMUXD_UART0_TX_lp_config_MASK (0x1800000U) #define IOMUXD_UART0_TX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_UART0_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_lp_config_SHIFT)) & IOMUXD_UART0_TX_lp_config_MASK) #define IOMUXD_UART0_TX_sw_config_MASK (0x6000000U) #define IOMUXD_UART0_TX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_UART0_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_sw_config_SHIFT)) & IOMUXD_UART0_TX_sw_config_MASK) #define IOMUXD_UART0_TX_mux_mode_MASK (0x38000000U) #define IOMUXD_UART0_TX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.UART0.TX * 0b001..ADMA.MQS.L * 0b010..ADMA.FLEXCAN0.TX * 0b011..SCU.UART0.TX * 0b100..LSIO.GPIO1.IO22 */ #define IOMUXD_UART0_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_mux_mode_SHIFT)) & IOMUXD_UART0_TX_mux_mode_MASK) #define IOMUXD_UART0_TX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_UART0_TX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_UART0_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART0_TX_update_pad_ctl_MASK) #define IOMUXD_UART0_TX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_UART0_TX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_UART0_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_update_mux_mode_SHIFT)) & IOMUXD_UART0_TX_update_mux_mode_MASK) /*! @} */ /*! @name UART2_TX - UART2_TX */ /*! @{ */ #define IOMUXD_UART2_TX_PDRV_MASK (0x1U) #define IOMUXD_UART2_TX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_UART2_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_PDRV_SHIFT)) & IOMUXD_UART2_TX_PDRV_MASK) #define IOMUXD_UART2_TX_UART2_TX_reserved_1_4_MASK (0x1EU) #define IOMUXD_UART2_TX_UART2_TX_reserved_1_4_SHIFT (1U) /*! UART2_TX_reserved_1_4 - reserved */ #define IOMUXD_UART2_TX_UART2_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_UART2_TX_reserved_1_4_SHIFT)) & IOMUXD_UART2_TX_UART2_TX_reserved_1_4_MASK) #define IOMUXD_UART2_TX_PULL_MASK (0x60U) #define IOMUXD_UART2_TX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_UART2_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_PULL_SHIFT)) & IOMUXD_UART2_TX_PULL_MASK) #define IOMUXD_UART2_TX_UART2_TX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_UART2_TX_UART2_TX_reserved_7_18_SHIFT (7U) /*! UART2_TX_reserved_7_18 - reserved */ #define IOMUXD_UART2_TX_UART2_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_UART2_TX_reserved_7_18_SHIFT)) & IOMUXD_UART2_TX_UART2_TX_reserved_7_18_MASK) #define IOMUXD_UART2_TX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_UART2_TX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_UART2_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART2_TX_WAKEUP_CTRL_MASK) #define IOMUXD_UART2_TX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_UART2_TX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_UART2_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART2_TX_WAKEUP_MASK_MASK) #define IOMUXD_UART2_TX_lp_config_MASK (0x1800000U) #define IOMUXD_UART2_TX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_UART2_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_lp_config_SHIFT)) & IOMUXD_UART2_TX_lp_config_MASK) #define IOMUXD_UART2_TX_sw_config_MASK (0x6000000U) #define IOMUXD_UART2_TX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_UART2_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_sw_config_SHIFT)) & IOMUXD_UART2_TX_sw_config_MASK) #define IOMUXD_UART2_TX_mux_mode_MASK (0x38000000U) #define IOMUXD_UART2_TX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.UART2.TX * 0b001..ADMA.FTM.CH1 * 0b010..ADMA.FLEXCAN1.TX * 0b100..LSIO.GPIO1.IO23 */ #define IOMUXD_UART2_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_mux_mode_SHIFT)) & IOMUXD_UART2_TX_mux_mode_MASK) #define IOMUXD_UART2_TX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_UART2_TX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_UART2_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART2_TX_update_pad_ctl_MASK) #define IOMUXD_UART2_TX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_UART2_TX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_UART2_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_update_mux_mode_SHIFT)) & IOMUXD_UART2_TX_update_mux_mode_MASK) /*! @} */ /*! @name UART2_RX - UART2_RX */ /*! @{ */ #define IOMUXD_UART2_RX_PDRV_MASK (0x1U) #define IOMUXD_UART2_RX_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_UART2_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_PDRV_SHIFT)) & IOMUXD_UART2_RX_PDRV_MASK) #define IOMUXD_UART2_RX_UART2_RX_reserved_1_4_MASK (0x1EU) #define IOMUXD_UART2_RX_UART2_RX_reserved_1_4_SHIFT (1U) /*! UART2_RX_reserved_1_4 - reserved */ #define IOMUXD_UART2_RX_UART2_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_UART2_RX_reserved_1_4_SHIFT)) & IOMUXD_UART2_RX_UART2_RX_reserved_1_4_MASK) #define IOMUXD_UART2_RX_PULL_MASK (0x60U) #define IOMUXD_UART2_RX_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_UART2_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_PULL_SHIFT)) & IOMUXD_UART2_RX_PULL_MASK) #define IOMUXD_UART2_RX_UART2_RX_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_UART2_RX_UART2_RX_reserved_7_18_SHIFT (7U) /*! UART2_RX_reserved_7_18 - reserved */ #define IOMUXD_UART2_RX_UART2_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_UART2_RX_reserved_7_18_SHIFT)) & IOMUXD_UART2_RX_UART2_RX_reserved_7_18_MASK) #define IOMUXD_UART2_RX_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_UART2_RX_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_UART2_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART2_RX_WAKEUP_CTRL_MASK) #define IOMUXD_UART2_RX_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_UART2_RX_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_UART2_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART2_RX_WAKEUP_MASK_MASK) #define IOMUXD_UART2_RX_lp_config_MASK (0x1800000U) #define IOMUXD_UART2_RX_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_UART2_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_lp_config_SHIFT)) & IOMUXD_UART2_RX_lp_config_MASK) #define IOMUXD_UART2_RX_sw_config_MASK (0x6000000U) #define IOMUXD_UART2_RX_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_UART2_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_sw_config_SHIFT)) & IOMUXD_UART2_RX_sw_config_MASK) #define IOMUXD_UART2_RX_mux_mode_MASK (0x38000000U) #define IOMUXD_UART2_RX_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..ADMA.UART2.RX * 0b001..ADMA.FTM.CH0 * 0b010..ADMA.FLEXCAN1.RX * 0b100..LSIO.GPIO1.IO24 */ #define IOMUXD_UART2_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_mux_mode_SHIFT)) & IOMUXD_UART2_RX_mux_mode_MASK) #define IOMUXD_UART2_RX_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_UART2_RX_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_UART2_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART2_RX_update_pad_ctl_MASK) #define IOMUXD_UART2_RX_update_mux_mode_MASK (0x80000000U) #define IOMUXD_UART2_RX_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_UART2_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_update_mux_mode_SHIFT)) & IOMUXD_UART2_RX_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_DSI0_I2C0_SCL - MIPI_DSI0_I2C0_SCL */ /*! @{ */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_MASK (0x1U) #define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_MASK (0x1EU) #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_SHIFT (1U) /*! MIPI_DSI0_I2C0_SCL_reserved_1_4 - reserved */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_MASK (0x60U) #define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_SHIFT (7U) /*! MIPI_DSI0_I2C0_SCL_reserved_7_18 - reserved */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_DSI0.I2C0.SCL * 0b001..MIPI_DSI1.GPIO0.IO02 * 0b100..LSIO.GPIO1.IO25 */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_DSI0_I2C0_SDA - MIPI_DSI0_I2C0_SDA */ /*! @{ */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_MASK (0x1U) #define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_MASK (0x1EU) #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_SHIFT (1U) /*! MIPI_DSI0_I2C0_SDA_reserved_1_4 - reserved */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_MASK (0x60U) #define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_SHIFT (7U) /*! MIPI_DSI0_I2C0_SDA_reserved_7_18 - reserved */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_DSI0.I2C0.SDA * 0b001..MIPI_DSI1.GPIO0.IO03 * 0b100..LSIO.GPIO1.IO26 */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_MASK) #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_DSI0_GPIO0_00 - MIPI_DSI0_GPIO0_00 */ /*! @{ */ #define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_MASK (0x1U) #define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_MASK (0x1EU) #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_SHIFT (1U) /*! MIPI_DSI0_GPIO0_00_reserved_1_4 - reserved */ #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_00_PULL_MASK (0x60U) #define IOMUXD_MIPI_DSI0_GPIO0_00_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MIPI_DSI0_GPIO0_00_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_PULL_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_SHIFT (7U) /*! MIPI_DSI0_GPIO0_00_reserved_7_18 - reserved */ #define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_DSI0.GPIO0.IO00 * 0b001..ADMA.I2C1.SCL * 0b010..MIPI_DSI0.PWM0.OUT * 0b100..LSIO.GPIO1.IO27 */ #define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_DSI0_GPIO0_01 - MIPI_DSI0_GPIO0_01 */ /*! @{ */ #define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_MASK (0x1U) #define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_MASK (0x1EU) #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_SHIFT (1U) /*! MIPI_DSI0_GPIO0_01_reserved_1_4 - reserved */ #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_01_PULL_MASK (0x60U) #define IOMUXD_MIPI_DSI0_GPIO0_01_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MIPI_DSI0_GPIO0_01_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_PULL_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_SHIFT (7U) /*! MIPI_DSI0_GPIO0_01_reserved_7_18 - reserved */ #define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_DSI0.GPIO0.IO01 * 0b001..ADMA.I2C1.SDA * 0b100..LSIO.GPIO1.IO28 */ #define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_MASK) #define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_DSI1_I2C0_SCL - MIPI_DSI1_I2C0_SCL */ /*! @{ */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_MASK (0x1U) #define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_MASK (0x1EU) #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_SHIFT (1U) /*! MIPI_DSI1_I2C0_SCL_reserved_1_4 - reserved */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_MASK (0x60U) #define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_SHIFT (7U) /*! MIPI_DSI1_I2C0_SCL_reserved_7_18 - reserved */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_DSI1.I2C0.SCL * 0b001..MIPI_DSI0.GPIO0.IO02 * 0b100..LSIO.GPIO1.IO29 */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_DSI1_I2C0_SDA - MIPI_DSI1_I2C0_SDA */ /*! @{ */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_MASK (0x1U) #define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_MASK (0x1EU) #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_SHIFT (1U) /*! MIPI_DSI1_I2C0_SDA_reserved_1_4 - reserved */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_MASK (0x60U) #define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_SHIFT (7U) /*! MIPI_DSI1_I2C0_SDA_reserved_7_18 - reserved */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_DSI1.I2C0.SDA * 0b001..MIPI_DSI0.GPIO0.IO03 * 0b100..LSIO.GPIO1.IO30 */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_MASK) #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_DSI1_GPIO0_00 - MIPI_DSI1_GPIO0_00 */ /*! @{ */ #define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_MASK (0x1U) #define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_MASK (0x1EU) #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_SHIFT (1U) /*! MIPI_DSI1_GPIO0_00_reserved_1_4 - reserved */ #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_00_PULL_MASK (0x60U) #define IOMUXD_MIPI_DSI1_GPIO0_00_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MIPI_DSI1_GPIO0_00_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_PULL_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_SHIFT (7U) /*! MIPI_DSI1_GPIO0_00_reserved_7_18 - reserved */ #define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_DSI1.GPIO0.IO00 * 0b001..ADMA.I2C2.SCL * 0b010..MIPI_DSI1.PWM0.OUT * 0b100..LSIO.GPIO1.IO31 */ #define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_DSI1_GPIO0_01 - MIPI_DSI1_GPIO0_01 */ /*! @{ */ #define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_MASK (0x1U) #define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_MASK (0x1EU) #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_SHIFT (1U) /*! MIPI_DSI1_GPIO0_01_reserved_1_4 - reserved */ #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_01_PULL_MASK (0x60U) #define IOMUXD_MIPI_DSI1_GPIO0_01_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_MIPI_DSI1_GPIO0_01_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_PULL_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_SHIFT (7U) /*! MIPI_DSI1_GPIO0_01_reserved_7_18 - reserved */ #define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_DSI1.GPIO0.IO01 * 0b001..ADMA.I2C2.SDA * 0b100..LSIO.GPIO2.IO00 */ #define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_MASK) #define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO - IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_MASK) /*! @} */ /*! @name SCU_WDOG_OUT - SCU_WDOG_OUT */ /*! @{ */ #define IOMUXD_SCU_WDOG_OUT_DSE_MASK (0x7U) #define IOMUXD_SCU_WDOG_OUT_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_SCU_WDOG_OUT_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_DSE_SHIFT)) & IOMUXD_SCU_WDOG_OUT_DSE_MASK) #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_MASK (0x18U) #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_SHIFT (3U) /*! SCU_WDOG_OUT_reserved_3_4 - reserved */ #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_SHIFT)) & IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_MASK) #define IOMUXD_SCU_WDOG_OUT_PULL_MASK (0x60U) #define IOMUXD_SCU_WDOG_OUT_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_SCU_WDOG_OUT_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_PULL_SHIFT)) & IOMUXD_SCU_WDOG_OUT_PULL_MASK) #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_SHIFT (7U) /*! SCU_WDOG_OUT_reserved_7_18 - reserved */ #define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_SHIFT)) & IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_MASK) #define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_MASK) #define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_MASK) #define IOMUXD_SCU_WDOG_OUT_lp_config_MASK (0x1800000U) #define IOMUXD_SCU_WDOG_OUT_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SCU_WDOG_OUT_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_lp_config_SHIFT)) & IOMUXD_SCU_WDOG_OUT_lp_config_MASK) #define IOMUXD_SCU_WDOG_OUT_sw_config_MASK (0x6000000U) #define IOMUXD_SCU_WDOG_OUT_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SCU_WDOG_OUT_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_sw_config_SHIFT)) & IOMUXD_SCU_WDOG_OUT_sw_config_MASK) #define IOMUXD_SCU_WDOG_OUT_mux_mode_MASK (0x38000000U) #define IOMUXD_SCU_WDOG_OUT_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b001..SCU.WDOG0.WDOG_OUT */ #define IOMUXD_SCU_WDOG_OUT_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_mux_mode_SHIFT)) & IOMUXD_SCU_WDOG_OUT_mux_mode_MASK) #define IOMUXD_SCU_WDOG_OUT_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SCU_WDOG_OUT_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SCU_WDOG_OUT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_update_pad_ctl_SHIFT)) & IOMUXD_SCU_WDOG_OUT_update_pad_ctl_MASK) #define IOMUXD_SCU_WDOG_OUT_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SCU_WDOG_OUT_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SCU_WDOG_OUT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_update_mux_mode_SHIFT)) & IOMUXD_SCU_WDOG_OUT_update_mux_mode_MASK) /*! @} */ /*! @name PMIC_I2C_SCL - PMIC_I2C_SCL */ /*! @{ */ #define IOMUXD_PMIC_I2C_SCL_DSE_MASK (0x7U) #define IOMUXD_PMIC_I2C_SCL_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_PMIC_I2C_SCL_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_DSE_SHIFT)) & IOMUXD_PMIC_I2C_SCL_DSE_MASK) #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_MASK (0x18U) #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_SHIFT (3U) /*! PMIC_I2C_SCL_reserved_3_4 - reserved */ #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_MASK) #define IOMUXD_PMIC_I2C_SCL_PULL_MASK (0x60U) #define IOMUXD_PMIC_I2C_SCL_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_PMIC_I2C_SCL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PULL_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PULL_MASK) #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_SHIFT (7U) /*! PMIC_I2C_SCL_reserved_7_18 - reserved */ #define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_MASK) #define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_MASK) #define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_MASK) #define IOMUXD_PMIC_I2C_SCL_lp_config_MASK (0x1800000U) #define IOMUXD_PMIC_I2C_SCL_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_PMIC_I2C_SCL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_lp_config_SHIFT)) & IOMUXD_PMIC_I2C_SCL_lp_config_MASK) #define IOMUXD_PMIC_I2C_SCL_sw_config_MASK (0x6000000U) #define IOMUXD_PMIC_I2C_SCL_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_PMIC_I2C_SCL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_sw_config_SHIFT)) & IOMUXD_PMIC_I2C_SCL_sw_config_MASK) #define IOMUXD_PMIC_I2C_SCL_mux_mode_MASK (0x38000000U) #define IOMUXD_PMIC_I2C_SCL_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..SCU.PMIC_I2C.SCL * 0b001..SCU.GPIO0.IOXX_PMIC_A35_ON * 0b100..LSIO.GPIO2.IO01 */ #define IOMUXD_PMIC_I2C_SCL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SCL_mux_mode_MASK) #define IOMUXD_PMIC_I2C_SCL_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_PMIC_I2C_SCL_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_PMIC_I2C_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_I2C_SCL_update_pad_ctl_MASK) #define IOMUXD_PMIC_I2C_SCL_update_mux_mode_MASK (0x80000000U) #define IOMUXD_PMIC_I2C_SCL_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_PMIC_I2C_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_update_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SCL_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_2_2 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_SHIFT (0U) /*! UART0_TX - wakeup from UART0_TX */ #define IOMUXD_IOMUXD_GROUP_2_2_UART0_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_SHIFT (1U) /*! UART2_TX - wakeup from UART2_TX */ #define IOMUXD_IOMUXD_GROUP_2_2_UART2_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_SHIFT (2U) /*! UART2_RX - wakeup from UART2_RX */ #define IOMUXD_IOMUXD_GROUP_2_2_UART2_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_SHIFT (3U) /*! iomuxd_group_2_2_reserved_3_3 - reserved */ #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_SHIFT (4U) /*! MIPI_DSI0_I2C0_SCL - wakeup from MIPI_DSI0_I2C0_SCL */ #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_SHIFT (5U) /*! MIPI_DSI0_I2C0_SDA - wakeup from MIPI_DSI0_I2C0_SDA */ #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_SHIFT (6U) /*! MIPI_DSI0_GPIO0_00 - wakeup from MIPI_DSI0_GPIO0_00 */ #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_SHIFT (7U) /*! MIPI_DSI0_GPIO0_01 - wakeup from MIPI_DSI0_GPIO0_01 */ #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_SHIFT (8U) /*! MIPI_DSI1_I2C0_SCL - wakeup from MIPI_DSI1_I2C0_SCL */ #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_SHIFT (9U) /*! MIPI_DSI1_I2C0_SDA - wakeup from MIPI_DSI1_I2C0_SDA */ #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_SHIFT (10U) /*! MIPI_DSI1_GPIO0_00 - wakeup from MIPI_DSI1_GPIO0_00 */ #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_SHIFT (11U) /*! MIPI_DSI1_GPIO0_01 - wakeup from MIPI_DSI1_GPIO0_01 */ #define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_SHIFT (12U) /*! iomuxd_group_2_2_reserved_12_12 - reserved */ #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_MASK (0x2000U) #define IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_SHIFT (13U) /*! SCU_WDOG_OUT - wakeup from SCU_WDOG_OUT */ #define IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_MASK (0x4000U) #define IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_SHIFT (14U) /*! PMIC_I2C_SCL - wakeup from PMIC_I2C_SCL */ #define IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_MASK) #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_MASK (0xFFFF8000U) #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_SHIFT (15U) /*! iomuxd_group_2_2_reserved_15_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_MASK) /*! @} */ /*! @name PMIC_I2C_SDA - PMIC_I2C_SDA */ /*! @{ */ #define IOMUXD_PMIC_I2C_SDA_DSE_MASK (0x7U) #define IOMUXD_PMIC_I2C_SDA_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_PMIC_I2C_SDA_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_DSE_SHIFT)) & IOMUXD_PMIC_I2C_SDA_DSE_MASK) #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_MASK (0x18U) #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_SHIFT (3U) /*! PMIC_I2C_SDA_reserved_3_4 - reserved */ #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_MASK) #define IOMUXD_PMIC_I2C_SDA_PULL_MASK (0x60U) #define IOMUXD_PMIC_I2C_SDA_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_PMIC_I2C_SDA_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PULL_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PULL_MASK) #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_SHIFT (7U) /*! PMIC_I2C_SDA_reserved_7_18 - reserved */ #define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_MASK) #define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_MASK) #define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_MASK) #define IOMUXD_PMIC_I2C_SDA_lp_config_MASK (0x1800000U) #define IOMUXD_PMIC_I2C_SDA_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_PMIC_I2C_SDA_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_lp_config_SHIFT)) & IOMUXD_PMIC_I2C_SDA_lp_config_MASK) #define IOMUXD_PMIC_I2C_SDA_sw_config_MASK (0x6000000U) #define IOMUXD_PMIC_I2C_SDA_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_PMIC_I2C_SDA_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_sw_config_SHIFT)) & IOMUXD_PMIC_I2C_SDA_sw_config_MASK) #define IOMUXD_PMIC_I2C_SDA_mux_mode_MASK (0x38000000U) #define IOMUXD_PMIC_I2C_SDA_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..SCU.PMIC_I2C.SDA * 0b001..SCU.GPIO0.IOXX_PMIC_GPU_ON * 0b100..LSIO.GPIO2.IO02 */ #define IOMUXD_PMIC_I2C_SDA_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SDA_mux_mode_MASK) #define IOMUXD_PMIC_I2C_SDA_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_PMIC_I2C_SDA_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_PMIC_I2C_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_I2C_SDA_update_pad_ctl_MASK) #define IOMUXD_PMIC_I2C_SDA_update_mux_mode_MASK (0x80000000U) #define IOMUXD_PMIC_I2C_SDA_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_PMIC_I2C_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_update_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SDA_update_mux_mode_MASK) /*! @} */ /*! @name PMIC_INT_B - PMIC_INT_B */ /*! @{ */ #define IOMUXD_PMIC_INT_B_DSE_MASK (0x7U) #define IOMUXD_PMIC_INT_B_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_PMIC_INT_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_DSE_SHIFT)) & IOMUXD_PMIC_INT_B_DSE_MASK) #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_MASK (0x18U) #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_SHIFT (3U) /*! PMIC_INT_B_reserved_3_4 - reserved */ #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_SHIFT)) & IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_MASK) #define IOMUXD_PMIC_INT_B_PULL_MASK (0x60U) #define IOMUXD_PMIC_INT_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_PMIC_INT_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PULL_SHIFT)) & IOMUXD_PMIC_INT_B_PULL_MASK) #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_SHIFT (7U) /*! PMIC_INT_B_reserved_7_18 - reserved */ #define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_SHIFT)) & IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_MASK) #define IOMUXD_PMIC_INT_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_PMIC_INT_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_PMIC_INT_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_INT_B_WAKEUP_CTRL_MASK) #define IOMUXD_PMIC_INT_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_PMIC_INT_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_PMIC_INT_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_INT_B_WAKEUP_MASK_MASK) #define IOMUXD_PMIC_INT_B_lp_config_MASK (0x1800000U) #define IOMUXD_PMIC_INT_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_PMIC_INT_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_lp_config_SHIFT)) & IOMUXD_PMIC_INT_B_lp_config_MASK) #define IOMUXD_PMIC_INT_B_sw_config_MASK (0x6000000U) #define IOMUXD_PMIC_INT_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_PMIC_INT_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_sw_config_SHIFT)) & IOMUXD_PMIC_INT_B_sw_config_MASK) #define IOMUXD_PMIC_INT_B_mux_mode_MASK (0x38000000U) #define IOMUXD_PMIC_INT_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..SCU.DSC.PMIC_INT_B */ #define IOMUXD_PMIC_INT_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_mux_mode_SHIFT)) & IOMUXD_PMIC_INT_B_mux_mode_MASK) #define IOMUXD_PMIC_INT_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_PMIC_INT_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_PMIC_INT_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_INT_B_update_pad_ctl_MASK) #define IOMUXD_PMIC_INT_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_PMIC_INT_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_PMIC_INT_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_update_mux_mode_SHIFT)) & IOMUXD_PMIC_INT_B_update_mux_mode_MASK) /*! @} */ /*! @name SCU_GPIO0_00 - SCU_GPIO0_00 */ /*! @{ */ #define IOMUXD_SCU_GPIO0_00_DSE_MASK (0x7U) #define IOMUXD_SCU_GPIO0_00_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_SCU_GPIO0_00_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_00_DSE_MASK) #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_MASK (0x18U) #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_SHIFT (3U) /*! SCU_GPIO0_00_reserved_3_4 - reserved */ #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_MASK) #define IOMUXD_SCU_GPIO0_00_PULL_MASK (0x60U) #define IOMUXD_SCU_GPIO0_00_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_SCU_GPIO0_00_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_00_PULL_MASK) #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_SHIFT (7U) /*! SCU_GPIO0_00_reserved_7_18 - reserved */ #define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_MASK) #define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_MASK) #define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_MASK) #define IOMUXD_SCU_GPIO0_00_lp_config_MASK (0x1800000U) #define IOMUXD_SCU_GPIO0_00_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SCU_GPIO0_00_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_00_lp_config_MASK) #define IOMUXD_SCU_GPIO0_00_sw_config_MASK (0x6000000U) #define IOMUXD_SCU_GPIO0_00_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SCU_GPIO0_00_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_00_sw_config_MASK) #define IOMUXD_SCU_GPIO0_00_mux_mode_MASK (0x38000000U) #define IOMUXD_SCU_GPIO0_00_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..SCU.GPIO0.IO00 * 0b001..SCU.UART0.RX * 0b010..M40.UART0.RX * 0b011..ADMA.UART3.RX * 0b100..LSIO.GPIO2.IO03 */ #define IOMUXD_SCU_GPIO0_00_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_00_mux_mode_MASK) #define IOMUXD_SCU_GPIO0_00_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SCU_GPIO0_00_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SCU_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_00_update_pad_ctl_MASK) #define IOMUXD_SCU_GPIO0_00_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SCU_GPIO0_00_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SCU_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_00_update_mux_mode_MASK) /*! @} */ /*! @name SCU_GPIO0_01 - SCU_GPIO0_01 */ /*! @{ */ #define IOMUXD_SCU_GPIO0_01_DSE_MASK (0x7U) #define IOMUXD_SCU_GPIO0_01_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_SCU_GPIO0_01_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_01_DSE_MASK) #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_MASK (0x18U) #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_SHIFT (3U) /*! SCU_GPIO0_01_reserved_3_4 - reserved */ #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_MASK) #define IOMUXD_SCU_GPIO0_01_PULL_MASK (0x60U) #define IOMUXD_SCU_GPIO0_01_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_SCU_GPIO0_01_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_01_PULL_MASK) #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_SHIFT (7U) /*! SCU_GPIO0_01_reserved_7_18 - reserved */ #define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_MASK) #define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_MASK) #define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_MASK) #define IOMUXD_SCU_GPIO0_01_lp_config_MASK (0x1800000U) #define IOMUXD_SCU_GPIO0_01_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SCU_GPIO0_01_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_01_lp_config_MASK) #define IOMUXD_SCU_GPIO0_01_sw_config_MASK (0x6000000U) #define IOMUXD_SCU_GPIO0_01_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SCU_GPIO0_01_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_01_sw_config_MASK) #define IOMUXD_SCU_GPIO0_01_mux_mode_MASK (0x38000000U) #define IOMUXD_SCU_GPIO0_01_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..SCU.GPIO0.IO01 * 0b001..SCU.UART0.TX * 0b010..M40.UART0.TX * 0b011..ADMA.UART3.TX * 0b100..SCU.WDOG0.WDOG_OUT */ #define IOMUXD_SCU_GPIO0_01_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_01_mux_mode_MASK) #define IOMUXD_SCU_GPIO0_01_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SCU_GPIO0_01_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SCU_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_01_update_pad_ctl_MASK) #define IOMUXD_SCU_GPIO0_01_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SCU_GPIO0_01_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SCU_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_01_update_mux_mode_MASK) /*! @} */ /*! @name SCU_PMIC_STANDBY - SCU_PMIC_STANDBY */ /*! @{ */ #define IOMUXD_SCU_PMIC_STANDBY_DSE_MASK (0x7U) #define IOMUXD_SCU_PMIC_STANDBY_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_SCU_PMIC_STANDBY_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_DSE_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_DSE_MASK) #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_MASK (0x18U) #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_SHIFT (3U) /*! SCU_PMIC_STANDBY_reserved_3_4 - reserved */ #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_MASK) #define IOMUXD_SCU_PMIC_STANDBY_PULL_MASK (0x60U) #define IOMUXD_SCU_PMIC_STANDBY_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_SCU_PMIC_STANDBY_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_PULL_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_PULL_MASK) #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_SHIFT (7U) /*! SCU_PMIC_STANDBY_reserved_7_18 - reserved */ #define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_MASK) #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_MASK) #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_MASK) #define IOMUXD_SCU_PMIC_STANDBY_lp_config_MASK (0x1800000U) #define IOMUXD_SCU_PMIC_STANDBY_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SCU_PMIC_STANDBY_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_lp_config_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_lp_config_MASK) #define IOMUXD_SCU_PMIC_STANDBY_sw_config_MASK (0x6000000U) #define IOMUXD_SCU_PMIC_STANDBY_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SCU_PMIC_STANDBY_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_sw_config_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_sw_config_MASK) #define IOMUXD_SCU_PMIC_STANDBY_mux_mode_MASK (0x38000000U) #define IOMUXD_SCU_PMIC_STANDBY_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..SCU.DSC.PMIC_STANDBY */ #define IOMUXD_SCU_PMIC_STANDBY_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_mux_mode_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_mux_mode_MASK) #define IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_MASK) #define IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SCU_PMIC_STANDBY_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_MASK) /*! @} */ /*! @name SCU_BOOT_MODE0 - SCU_BOOT_MODE0 */ /*! @{ */ #define IOMUXD_SCU_BOOT_MODE0_DSE_MASK (0x7U) #define IOMUXD_SCU_BOOT_MODE0_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_SCU_BOOT_MODE0_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_DSE_MASK) #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_MASK (0x18U) #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_SHIFT (3U) /*! SCU_BOOT_MODE0_reserved_3_4 - reserved */ #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_MASK) #define IOMUXD_SCU_BOOT_MODE0_PULL_MASK (0x60U) #define IOMUXD_SCU_BOOT_MODE0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_SCU_BOOT_MODE0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_PULL_MASK) #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_SHIFT (7U) /*! SCU_BOOT_MODE0_reserved_7_18 - reserved */ #define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_MASK) #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_MASK) #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_MASK) #define IOMUXD_SCU_BOOT_MODE0_lp_config_MASK (0x1800000U) #define IOMUXD_SCU_BOOT_MODE0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SCU_BOOT_MODE0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_lp_config_MASK) #define IOMUXD_SCU_BOOT_MODE0_sw_config_MASK (0x6000000U) #define IOMUXD_SCU_BOOT_MODE0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SCU_BOOT_MODE0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_sw_config_MASK) #define IOMUXD_SCU_BOOT_MODE0_mux_mode_MASK (0x38000000U) #define IOMUXD_SCU_BOOT_MODE0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..SCU.DSC.BOOT_MODE0 */ #define IOMUXD_SCU_BOOT_MODE0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_mux_mode_MASK) #define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_MASK) #define IOMUXD_SCU_BOOT_MODE0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SCU_BOOT_MODE0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SCU_BOOT_MODE0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_update_mux_mode_MASK) /*! @} */ /*! @name SCU_BOOT_MODE1 - SCU_BOOT_MODE1 */ /*! @{ */ #define IOMUXD_SCU_BOOT_MODE1_DSE_MASK (0x7U) #define IOMUXD_SCU_BOOT_MODE1_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_SCU_BOOT_MODE1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_DSE_MASK) #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_MASK (0x18U) #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_SHIFT (3U) /*! SCU_BOOT_MODE1_reserved_3_4 - reserved */ #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_MASK) #define IOMUXD_SCU_BOOT_MODE1_PULL_MASK (0x60U) #define IOMUXD_SCU_BOOT_MODE1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_SCU_BOOT_MODE1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_PULL_MASK) #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_SHIFT (7U) /*! SCU_BOOT_MODE1_reserved_7_18 - reserved */ #define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_MASK) #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_MASK) #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_MASK) #define IOMUXD_SCU_BOOT_MODE1_lp_config_MASK (0x1800000U) #define IOMUXD_SCU_BOOT_MODE1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SCU_BOOT_MODE1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_lp_config_MASK) #define IOMUXD_SCU_BOOT_MODE1_sw_config_MASK (0x6000000U) #define IOMUXD_SCU_BOOT_MODE1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SCU_BOOT_MODE1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_sw_config_MASK) #define IOMUXD_SCU_BOOT_MODE1_mux_mode_MASK (0x38000000U) #define IOMUXD_SCU_BOOT_MODE1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..SCU.DSC.BOOT_MODE1 */ #define IOMUXD_SCU_BOOT_MODE1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_mux_mode_MASK) #define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_MASK) #define IOMUXD_SCU_BOOT_MODE1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SCU_BOOT_MODE1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SCU_BOOT_MODE1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_update_mux_mode_MASK) /*! @} */ /*! @name SCU_BOOT_MODE2 - SCU_BOOT_MODE2 */ /*! @{ */ #define IOMUXD_SCU_BOOT_MODE2_DSE_MASK (0x7U) #define IOMUXD_SCU_BOOT_MODE2_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_SCU_BOOT_MODE2_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_DSE_MASK) #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_MASK (0x18U) #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_SHIFT (3U) /*! SCU_BOOT_MODE2_reserved_3_4 - reserved */ #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_MASK) #define IOMUXD_SCU_BOOT_MODE2_PULL_MASK (0x60U) #define IOMUXD_SCU_BOOT_MODE2_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_SCU_BOOT_MODE2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_PULL_MASK) #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_SHIFT (7U) /*! SCU_BOOT_MODE2_reserved_7_18 - reserved */ #define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_MASK) #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_MASK) #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_MASK) #define IOMUXD_SCU_BOOT_MODE2_lp_config_MASK (0x1800000U) #define IOMUXD_SCU_BOOT_MODE2_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SCU_BOOT_MODE2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_lp_config_MASK) #define IOMUXD_SCU_BOOT_MODE2_sw_config_MASK (0x6000000U) #define IOMUXD_SCU_BOOT_MODE2_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SCU_BOOT_MODE2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_sw_config_MASK) #define IOMUXD_SCU_BOOT_MODE2_mux_mode_MASK (0x38000000U) #define IOMUXD_SCU_BOOT_MODE2_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..SCU.DSC.BOOT_MODE2 * 0b001..SCU.PMIC_I2C.SDA */ #define IOMUXD_SCU_BOOT_MODE2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_mux_mode_MASK) #define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_MASK) #define IOMUXD_SCU_BOOT_MODE2_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SCU_BOOT_MODE2_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SCU_BOOT_MODE2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_update_mux_mode_MASK) /*! @} */ /*! @name SCU_BOOT_MODE3 - SCU_BOOT_MODE3 */ /*! @{ */ #define IOMUXD_SCU_BOOT_MODE3_DSE_MASK (0x7U) #define IOMUXD_SCU_BOOT_MODE3_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_SCU_BOOT_MODE3_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_DSE_MASK) #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_MASK (0x18U) #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_SHIFT (3U) /*! SCU_BOOT_MODE3_reserved_3_4 - reserved */ #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_MASK) #define IOMUXD_SCU_BOOT_MODE3_PULL_MASK (0x60U) #define IOMUXD_SCU_BOOT_MODE3_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_SCU_BOOT_MODE3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_PULL_MASK) #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_SHIFT (7U) /*! SCU_BOOT_MODE3_reserved_7_18 - reserved */ #define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_MASK) #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_MASK) #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_MASK) #define IOMUXD_SCU_BOOT_MODE3_lp_config_MASK (0x1800000U) #define IOMUXD_SCU_BOOT_MODE3_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_SCU_BOOT_MODE3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_lp_config_MASK) #define IOMUXD_SCU_BOOT_MODE3_sw_config_MASK (0x6000000U) #define IOMUXD_SCU_BOOT_MODE3_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_SCU_BOOT_MODE3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_sw_config_MASK) #define IOMUXD_SCU_BOOT_MODE3_mux_mode_MASK (0x38000000U) #define IOMUXD_SCU_BOOT_MODE3_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..SCU.DSC.BOOT_MODE3 * 0b001..SCU.PMIC_I2C.SCL * 0b011..SCU.DSC.RTC_CLOCK_OUTPUT_32K */ #define IOMUXD_SCU_BOOT_MODE3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_mux_mode_MASK) #define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_MASK) #define IOMUXD_SCU_BOOT_MODE3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_SCU_BOOT_MODE3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_SCU_BOOT_MODE3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_update_mux_mode_MASK) /*! @} */ /*! @name CSI_DIG_D00 - CSI_DIG_D00 */ /*! @{ */ #define IOMUXD_CSI_DIG_D00_PDRV_MASK (0x1U) #define IOMUXD_CSI_DIG_D00_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_DIG_D00_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D00_PDRV_MASK) #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_SHIFT (1U) /*! CSI_DIG_D00_reserved_1_4 - reserved */ #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_MASK) #define IOMUXD_CSI_DIG_D00_PULL_MASK (0x60U) #define IOMUXD_CSI_DIG_D00_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_DIG_D00_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_PULL_SHIFT)) & IOMUXD_CSI_DIG_D00_PULL_MASK) #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_SHIFT (7U) /*! CSI_DIG_D00_reserved_7_18 - reserved */ #define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_MASK) #define IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_DIG_D00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_DIG_D00_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_DIG_D00_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_DIG_D00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D00_WAKEUP_MASK_MASK) #define IOMUXD_CSI_DIG_D00_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_DIG_D00_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_DIG_D00_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D00_lp_config_MASK) #define IOMUXD_CSI_DIG_D00_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_DIG_D00_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_DIG_D00_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D00_sw_config_MASK) #define IOMUXD_CSI_DIG_D00_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_DIG_D00_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.D02 * 0b010..ADMA.SAI0.RXC */ #define IOMUXD_CSI_DIG_D00_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D00_mux_mode_MASK) #define IOMUXD_CSI_DIG_D00_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_DIG_D00_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_DIG_D00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D00_update_pad_ctl_MASK) #define IOMUXD_CSI_DIG_D00_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_DIG_D00_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_DIG_D00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D00_update_mux_mode_MASK) /*! @} */ /*! @name CSI_DIG_D01 - CSI_DIG_D01 */ /*! @{ */ #define IOMUXD_CSI_DIG_D01_PDRV_MASK (0x1U) #define IOMUXD_CSI_DIG_D01_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_DIG_D01_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D01_PDRV_MASK) #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_SHIFT (1U) /*! CSI_DIG_D01_reserved_1_4 - reserved */ #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_MASK) #define IOMUXD_CSI_DIG_D01_PULL_MASK (0x60U) #define IOMUXD_CSI_DIG_D01_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_DIG_D01_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_PULL_SHIFT)) & IOMUXD_CSI_DIG_D01_PULL_MASK) #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_SHIFT (7U) /*! CSI_DIG_D01_reserved_7_18 - reserved */ #define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_MASK) #define IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_DIG_D01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_DIG_D01_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_DIG_D01_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_DIG_D01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D01_WAKEUP_MASK_MASK) #define IOMUXD_CSI_DIG_D01_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_DIG_D01_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_DIG_D01_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D01_lp_config_MASK) #define IOMUXD_CSI_DIG_D01_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_DIG_D01_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_DIG_D01_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D01_sw_config_MASK) #define IOMUXD_CSI_DIG_D01_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_DIG_D01_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.D03 * 0b010..ADMA.SAI0.RXD */ #define IOMUXD_CSI_DIG_D01_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D01_mux_mode_MASK) #define IOMUXD_CSI_DIG_D01_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_DIG_D01_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_DIG_D01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D01_update_pad_ctl_MASK) #define IOMUXD_CSI_DIG_D01_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_DIG_D01_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_DIG_D01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D01_update_mux_mode_MASK) /*! @} */ /*! @name CSI_DIG_D02 - CSI_DIG_D02 */ /*! @{ */ #define IOMUXD_CSI_DIG_D02_PDRV_MASK (0x1U) #define IOMUXD_CSI_DIG_D02_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_DIG_D02_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D02_PDRV_MASK) #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_SHIFT (1U) /*! CSI_DIG_D02_reserved_1_4 - reserved */ #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_MASK) #define IOMUXD_CSI_DIG_D02_PULL_MASK (0x60U) #define IOMUXD_CSI_DIG_D02_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_DIG_D02_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_PULL_SHIFT)) & IOMUXD_CSI_DIG_D02_PULL_MASK) #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_SHIFT (7U) /*! CSI_DIG_D02_reserved_7_18 - reserved */ #define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_MASK) #define IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_DIG_D02_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_DIG_D02_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_DIG_D02_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_DIG_D02_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D02_WAKEUP_MASK_MASK) #define IOMUXD_CSI_DIG_D02_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_DIG_D02_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_DIG_D02_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D02_lp_config_MASK) #define IOMUXD_CSI_DIG_D02_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_DIG_D02_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_DIG_D02_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D02_sw_config_MASK) #define IOMUXD_CSI_DIG_D02_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_DIG_D02_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.D04 * 0b010..ADMA.SAI0.RXFS */ #define IOMUXD_CSI_DIG_D02_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D02_mux_mode_MASK) #define IOMUXD_CSI_DIG_D02_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_DIG_D02_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_DIG_D02_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D02_update_pad_ctl_MASK) #define IOMUXD_CSI_DIG_D02_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_DIG_D02_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_DIG_D02_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D02_update_mux_mode_MASK) /*! @} */ /*! @name CSI_DIG_D03 - CSI_DIG_D03 */ /*! @{ */ #define IOMUXD_CSI_DIG_D03_PDRV_MASK (0x1U) #define IOMUXD_CSI_DIG_D03_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_DIG_D03_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D03_PDRV_MASK) #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_SHIFT (1U) /*! CSI_DIG_D03_reserved_1_4 - reserved */ #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_MASK) #define IOMUXD_CSI_DIG_D03_PULL_MASK (0x60U) #define IOMUXD_CSI_DIG_D03_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_DIG_D03_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_PULL_SHIFT)) & IOMUXD_CSI_DIG_D03_PULL_MASK) #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_SHIFT (7U) /*! CSI_DIG_D03_reserved_7_18 - reserved */ #define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_MASK) #define IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_DIG_D03_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_DIG_D03_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_DIG_D03_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_DIG_D03_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D03_WAKEUP_MASK_MASK) #define IOMUXD_CSI_DIG_D03_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_DIG_D03_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_DIG_D03_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D03_lp_config_MASK) #define IOMUXD_CSI_DIG_D03_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_DIG_D03_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_DIG_D03_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D03_sw_config_MASK) #define IOMUXD_CSI_DIG_D03_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_DIG_D03_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.D05 * 0b010..ADMA.SAI2.RXC */ #define IOMUXD_CSI_DIG_D03_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D03_mux_mode_MASK) #define IOMUXD_CSI_DIG_D03_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_DIG_D03_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_DIG_D03_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D03_update_pad_ctl_MASK) #define IOMUXD_CSI_DIG_D03_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_DIG_D03_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_DIG_D03_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D03_update_mux_mode_MASK) /*! @} */ /*! @name CSI_DIG_D04 - CSI_DIG_D04 */ /*! @{ */ #define IOMUXD_CSI_DIG_D04_PDRV_MASK (0x1U) #define IOMUXD_CSI_DIG_D04_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_DIG_D04_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D04_PDRV_MASK) #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_SHIFT (1U) /*! CSI_DIG_D04_reserved_1_4 - reserved */ #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_MASK) #define IOMUXD_CSI_DIG_D04_PULL_MASK (0x60U) #define IOMUXD_CSI_DIG_D04_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_DIG_D04_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_PULL_SHIFT)) & IOMUXD_CSI_DIG_D04_PULL_MASK) #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_SHIFT (7U) /*! CSI_DIG_D04_reserved_7_18 - reserved */ #define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_MASK) #define IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_DIG_D04_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_DIG_D04_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_DIG_D04_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_DIG_D04_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D04_WAKEUP_MASK_MASK) #define IOMUXD_CSI_DIG_D04_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_DIG_D04_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_DIG_D04_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D04_lp_config_MASK) #define IOMUXD_CSI_DIG_D04_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_DIG_D04_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_DIG_D04_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D04_sw_config_MASK) #define IOMUXD_CSI_DIG_D04_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_DIG_D04_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.D06 * 0b010..ADMA.SAI2.RXD */ #define IOMUXD_CSI_DIG_D04_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D04_mux_mode_MASK) #define IOMUXD_CSI_DIG_D04_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_DIG_D04_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_DIG_D04_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D04_update_pad_ctl_MASK) #define IOMUXD_CSI_DIG_D04_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_DIG_D04_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_DIG_D04_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D04_update_mux_mode_MASK) /*! @} */ /*! @name CSI_DIG_D05 - CSI_DIG_D05 */ /*! @{ */ #define IOMUXD_CSI_DIG_D05_PDRV_MASK (0x1U) #define IOMUXD_CSI_DIG_D05_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_DIG_D05_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D05_PDRV_MASK) #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_SHIFT (1U) /*! CSI_DIG_D05_reserved_1_4 - reserved */ #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_MASK) #define IOMUXD_CSI_DIG_D05_PULL_MASK (0x60U) #define IOMUXD_CSI_DIG_D05_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_DIG_D05_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_PULL_SHIFT)) & IOMUXD_CSI_DIG_D05_PULL_MASK) #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_SHIFT (7U) /*! CSI_DIG_D05_reserved_7_18 - reserved */ #define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_MASK) #define IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_DIG_D05_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_DIG_D05_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_DIG_D05_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_DIG_D05_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D05_WAKEUP_MASK_MASK) #define IOMUXD_CSI_DIG_D05_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_DIG_D05_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_DIG_D05_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D05_lp_config_MASK) #define IOMUXD_CSI_DIG_D05_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_DIG_D05_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_DIG_D05_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D05_sw_config_MASK) #define IOMUXD_CSI_DIG_D05_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_DIG_D05_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.D07 * 0b010..ADMA.SAI2.RXFS */ #define IOMUXD_CSI_DIG_D05_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D05_mux_mode_MASK) #define IOMUXD_CSI_DIG_D05_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_DIG_D05_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_DIG_D05_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D05_update_pad_ctl_MASK) #define IOMUXD_CSI_DIG_D05_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_DIG_D05_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_DIG_D05_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D05_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_2_3 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_SHIFT (0U) /*! PMIC_I2C_SDA - wakeup from PMIC_I2C_SDA */ #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_SHIFT (1U) /*! PMIC_INT_B - wakeup from PMIC_INT_B */ #define IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_SHIFT (2U) /*! SCU_GPIO0_00 - wakeup from SCU_GPIO0_00 */ #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_SHIFT (3U) /*! SCU_GPIO0_01 - wakeup from SCU_GPIO0_01 */ #define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_SHIFT (4U) /*! SCU_PMIC_STANDBY - wakeup from SCU_PMIC_STANDBY */ #define IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_SHIFT (5U) /*! SCU_BOOT_MODE0 - wakeup from SCU_BOOT_MODE0 */ #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_SHIFT (6U) /*! SCU_BOOT_MODE1 - wakeup from SCU_BOOT_MODE1 */ #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_SHIFT (7U) /*! SCU_BOOT_MODE2 - wakeup from SCU_BOOT_MODE2 */ #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_SHIFT (8U) /*! SCU_BOOT_MODE3 - wakeup from SCU_BOOT_MODE3 */ #define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_SHIFT (9U) /*! CSI_DIG_D00 - wakeup from CSI_DIG_D00 */ #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_SHIFT (10U) /*! CSI_DIG_D01 - wakeup from CSI_DIG_D01 */ #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_SHIFT (11U) /*! CSI_DIG_D02 - wakeup from CSI_DIG_D02 */ #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_SHIFT (12U) /*! CSI_DIG_D03 - wakeup from CSI_DIG_D03 */ #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_MASK (0x2000U) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_SHIFT (13U) /*! CSI_DIG_D04 - wakeup from CSI_DIG_D04 */ #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_MASK (0x4000U) #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_SHIFT (14U) /*! CSI_DIG_D05 - wakeup from CSI_DIG_D05 */ #define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_MASK) #define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_MASK (0xFFFF8000U) #define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_SHIFT (15U) /*! iomuxd_group_2_3_reserved_15_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_MASK) /*! @} */ /*! @name CSI_DIG_D06 - CSI_DIG_D06 */ /*! @{ */ #define IOMUXD_CSI_DIG_D06_PDRV_MASK (0x1U) #define IOMUXD_CSI_DIG_D06_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_DIG_D06_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D06_PDRV_MASK) #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_SHIFT (1U) /*! CSI_DIG_D06_reserved_1_4 - reserved */ #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_MASK) #define IOMUXD_CSI_DIG_D06_PULL_MASK (0x60U) #define IOMUXD_CSI_DIG_D06_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_DIG_D06_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_PULL_SHIFT)) & IOMUXD_CSI_DIG_D06_PULL_MASK) #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_SHIFT (7U) /*! CSI_DIG_D06_reserved_7_18 - reserved */ #define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_MASK) #define IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_DIG_D06_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_DIG_D06_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_DIG_D06_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_DIG_D06_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D06_WAKEUP_MASK_MASK) #define IOMUXD_CSI_DIG_D06_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_DIG_D06_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_DIG_D06_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D06_lp_config_MASK) #define IOMUXD_CSI_DIG_D06_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_DIG_D06_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_DIG_D06_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D06_sw_config_MASK) #define IOMUXD_CSI_DIG_D06_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_DIG_D06_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.D08 * 0b010..ADMA.SAI3.RXC */ #define IOMUXD_CSI_DIG_D06_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D06_mux_mode_MASK) #define IOMUXD_CSI_DIG_D06_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_DIG_D06_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_DIG_D06_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D06_update_pad_ctl_MASK) #define IOMUXD_CSI_DIG_D06_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_DIG_D06_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_DIG_D06_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D06_update_mux_mode_MASK) /*! @} */ /*! @name CSI_DIG_D07 - CSI_DIG_D07 */ /*! @{ */ #define IOMUXD_CSI_DIG_D07_PDRV_MASK (0x1U) #define IOMUXD_CSI_DIG_D07_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_DIG_D07_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D07_PDRV_MASK) #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_SHIFT (1U) /*! CSI_DIG_D07_reserved_1_4 - reserved */ #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_MASK) #define IOMUXD_CSI_DIG_D07_PULL_MASK (0x60U) #define IOMUXD_CSI_DIG_D07_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_DIG_D07_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_PULL_SHIFT)) & IOMUXD_CSI_DIG_D07_PULL_MASK) #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_SHIFT (7U) /*! CSI_DIG_D07_reserved_7_18 - reserved */ #define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_MASK) #define IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_DIG_D07_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_DIG_D07_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_DIG_D07_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_DIG_D07_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D07_WAKEUP_MASK_MASK) #define IOMUXD_CSI_DIG_D07_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_DIG_D07_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_DIG_D07_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D07_lp_config_MASK) #define IOMUXD_CSI_DIG_D07_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_DIG_D07_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_DIG_D07_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D07_sw_config_MASK) #define IOMUXD_CSI_DIG_D07_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_DIG_D07_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.D09 * 0b010..ADMA.SAI3.RXD */ #define IOMUXD_CSI_DIG_D07_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D07_mux_mode_MASK) #define IOMUXD_CSI_DIG_D07_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_DIG_D07_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_DIG_D07_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D07_update_pad_ctl_MASK) #define IOMUXD_CSI_DIG_D07_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_DIG_D07_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_DIG_D07_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D07_update_mux_mode_MASK) /*! @} */ /*! @name CSI_DIG_HSYNC - CSI_DIG_HSYNC */ /*! @{ */ #define IOMUXD_CSI_DIG_HSYNC_PDRV_MASK (0x1U) #define IOMUXD_CSI_DIG_HSYNC_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_DIG_HSYNC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_PDRV_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_PDRV_MASK) #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_SHIFT (1U) /*! CSI_DIG_HSYNC_reserved_1_4 - reserved */ #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_MASK) #define IOMUXD_CSI_DIG_HSYNC_PULL_MASK (0x60U) #define IOMUXD_CSI_DIG_HSYNC_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_DIG_HSYNC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_PULL_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_PULL_MASK) #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_SHIFT (7U) /*! CSI_DIG_HSYNC_reserved_7_18 - reserved */ #define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_MASK) #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_MASK) #define IOMUXD_CSI_DIG_HSYNC_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_DIG_HSYNC_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_DIG_HSYNC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_lp_config_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_lp_config_MASK) #define IOMUXD_CSI_DIG_HSYNC_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_DIG_HSYNC_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_DIG_HSYNC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_sw_config_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_sw_config_MASK) #define IOMUXD_CSI_DIG_HSYNC_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_DIG_HSYNC_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.HSYNC * 0b001..CI_PI.D00 * 0b010..ADMA.SAI3.RXFS */ #define IOMUXD_CSI_DIG_HSYNC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_mux_mode_MASK) #define IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_DIG_HSYNC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_MASK) #define IOMUXD_CSI_DIG_HSYNC_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_DIG_HSYNC_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_DIG_HSYNC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_update_mux_mode_MASK) /*! @} */ /*! @name CSI_DIG_VSYNC - CSI_DIG_VSYNC */ /*! @{ */ #define IOMUXD_CSI_DIG_VSYNC_PDRV_MASK (0x1U) #define IOMUXD_CSI_DIG_VSYNC_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_DIG_VSYNC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_PDRV_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_PDRV_MASK) #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_SHIFT (1U) /*! CSI_DIG_VSYNC_reserved_1_4 - reserved */ #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_MASK) #define IOMUXD_CSI_DIG_VSYNC_PULL_MASK (0x60U) #define IOMUXD_CSI_DIG_VSYNC_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_DIG_VSYNC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_PULL_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_PULL_MASK) #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_SHIFT (7U) /*! CSI_DIG_VSYNC_reserved_7_18 - reserved */ #define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_MASK) #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_MASK) #define IOMUXD_CSI_DIG_VSYNC_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_DIG_VSYNC_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_DIG_VSYNC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_lp_config_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_lp_config_MASK) #define IOMUXD_CSI_DIG_VSYNC_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_DIG_VSYNC_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_DIG_VSYNC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_sw_config_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_sw_config_MASK) #define IOMUXD_CSI_DIG_VSYNC_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_DIG_VSYNC_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.VSYNC * 0b001..CI_PI.D01 */ #define IOMUXD_CSI_DIG_VSYNC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_mux_mode_MASK) #define IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_DIG_VSYNC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_MASK) #define IOMUXD_CSI_DIG_VSYNC_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_DIG_VSYNC_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_DIG_VSYNC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_update_mux_mode_MASK) /*! @} */ /*! @name CSI_PCLK - CSI_PCLK */ /*! @{ */ #define IOMUXD_CSI_PCLK_PDRV_MASK (0x1U) #define IOMUXD_CSI_PCLK_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_PCLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_PDRV_SHIFT)) & IOMUXD_CSI_PCLK_PDRV_MASK) #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_SHIFT (1U) /*! CSI_PCLK_reserved_1_4 - reserved */ #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_SHIFT)) & IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_MASK) #define IOMUXD_CSI_PCLK_PULL_MASK (0x60U) #define IOMUXD_CSI_PCLK_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_PCLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_PULL_SHIFT)) & IOMUXD_CSI_PCLK_PULL_MASK) #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_SHIFT (7U) /*! CSI_PCLK_reserved_7_18 - reserved */ #define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_SHIFT)) & IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_MASK) #define IOMUXD_CSI_PCLK_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_PCLK_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_PCLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_PCLK_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_PCLK_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_PCLK_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_PCLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_PCLK_WAKEUP_MASK_MASK) #define IOMUXD_CSI_PCLK_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_PCLK_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_PCLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_lp_config_SHIFT)) & IOMUXD_CSI_PCLK_lp_config_MASK) #define IOMUXD_CSI_PCLK_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_PCLK_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_PCLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_sw_config_SHIFT)) & IOMUXD_CSI_PCLK_sw_config_MASK) #define IOMUXD_CSI_PCLK_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_PCLK_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.PCLK * 0b001..MIPI_CSI0.I2C0.SCL * 0b011..ADMA.SPI1.SCK * 0b100..LSIO.GPIO3.IO00 */ #define IOMUXD_CSI_PCLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_mux_mode_SHIFT)) & IOMUXD_CSI_PCLK_mux_mode_MASK) #define IOMUXD_CSI_PCLK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_PCLK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_PCLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_update_pad_ctl_SHIFT)) & IOMUXD_CSI_PCLK_update_pad_ctl_MASK) #define IOMUXD_CSI_PCLK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_PCLK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_PCLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_update_mux_mode_SHIFT)) & IOMUXD_CSI_PCLK_update_mux_mode_MASK) /*! @} */ /*! @name CSI_MCLK - CSI_MCLK */ /*! @{ */ #define IOMUXD_CSI_MCLK_PDRV_MASK (0x1U) #define IOMUXD_CSI_MCLK_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_MCLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_PDRV_SHIFT)) & IOMUXD_CSI_MCLK_PDRV_MASK) #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_SHIFT (1U) /*! CSI_MCLK_reserved_1_4 - reserved */ #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_SHIFT)) & IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_MASK) #define IOMUXD_CSI_MCLK_PULL_MASK (0x60U) #define IOMUXD_CSI_MCLK_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_MCLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_PULL_SHIFT)) & IOMUXD_CSI_MCLK_PULL_MASK) #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_SHIFT (7U) /*! CSI_MCLK_reserved_7_18 - reserved */ #define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_SHIFT)) & IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_MASK) #define IOMUXD_CSI_MCLK_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_MCLK_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_MCLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_MCLK_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_MCLK_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_MCLK_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_MCLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_MCLK_WAKEUP_MASK_MASK) #define IOMUXD_CSI_MCLK_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_MCLK_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_MCLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_lp_config_SHIFT)) & IOMUXD_CSI_MCLK_lp_config_MASK) #define IOMUXD_CSI_MCLK_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_MCLK_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_MCLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_sw_config_SHIFT)) & IOMUXD_CSI_MCLK_sw_config_MASK) #define IOMUXD_CSI_MCLK_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_MCLK_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.MCLK * 0b001..MIPI_CSI0.I2C0.SDA * 0b011..ADMA.SPI1.SDO * 0b100..LSIO.GPIO3.IO01 */ #define IOMUXD_CSI_MCLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_mux_mode_SHIFT)) & IOMUXD_CSI_MCLK_mux_mode_MASK) #define IOMUXD_CSI_MCLK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_MCLK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_MCLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_update_pad_ctl_SHIFT)) & IOMUXD_CSI_MCLK_update_pad_ctl_MASK) #define IOMUXD_CSI_MCLK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_MCLK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_MCLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_update_mux_mode_SHIFT)) & IOMUXD_CSI_MCLK_update_mux_mode_MASK) /*! @} */ /*! @name CSI_EN - CSI_EN */ /*! @{ */ #define IOMUXD_CSI_EN_PDRV_MASK (0x1U) #define IOMUXD_CSI_EN_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_EN_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_PDRV_SHIFT)) & IOMUXD_CSI_EN_PDRV_MASK) #define IOMUXD_CSI_EN_CSI_EN_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_EN_CSI_EN_reserved_1_4_SHIFT (1U) /*! CSI_EN_reserved_1_4 - reserved */ #define IOMUXD_CSI_EN_CSI_EN_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_CSI_EN_reserved_1_4_SHIFT)) & IOMUXD_CSI_EN_CSI_EN_reserved_1_4_MASK) #define IOMUXD_CSI_EN_PULL_MASK (0x60U) #define IOMUXD_CSI_EN_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_EN_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_PULL_SHIFT)) & IOMUXD_CSI_EN_PULL_MASK) #define IOMUXD_CSI_EN_CSI_EN_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_EN_CSI_EN_reserved_7_18_SHIFT (7U) /*! CSI_EN_reserved_7_18 - reserved */ #define IOMUXD_CSI_EN_CSI_EN_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_CSI_EN_reserved_7_18_SHIFT)) & IOMUXD_CSI_EN_CSI_EN_reserved_7_18_MASK) #define IOMUXD_CSI_EN_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_EN_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_EN_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_EN_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_EN_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_EN_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_EN_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_EN_WAKEUP_MASK_MASK) #define IOMUXD_CSI_EN_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_EN_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_EN_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_lp_config_SHIFT)) & IOMUXD_CSI_EN_lp_config_MASK) #define IOMUXD_CSI_EN_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_EN_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_EN_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_sw_config_SHIFT)) & IOMUXD_CSI_EN_sw_config_MASK) #define IOMUXD_CSI_EN_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_EN_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.EN * 0b001..CI_PI.I2C.SCL * 0b010..ADMA.I2C3.SCL * 0b011..ADMA.SPI1.SDI * 0b100..LSIO.GPIO3.IO02 */ #define IOMUXD_CSI_EN_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_mux_mode_SHIFT)) & IOMUXD_CSI_EN_mux_mode_MASK) #define IOMUXD_CSI_EN_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_EN_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_EN_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_update_pad_ctl_SHIFT)) & IOMUXD_CSI_EN_update_pad_ctl_MASK) #define IOMUXD_CSI_EN_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_EN_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_EN_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_update_mux_mode_SHIFT)) & IOMUXD_CSI_EN_update_mux_mode_MASK) /*! @} */ /*! @name CSI_RESET - CSI_RESET */ /*! @{ */ #define IOMUXD_CSI_RESET_PDRV_MASK (0x1U) #define IOMUXD_CSI_RESET_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_CSI_RESET_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_PDRV_SHIFT)) & IOMUXD_CSI_RESET_PDRV_MASK) #define IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_MASK (0x1EU) #define IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_SHIFT (1U) /*! CSI_RESET_reserved_1_4 - reserved */ #define IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_SHIFT)) & IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_MASK) #define IOMUXD_CSI_RESET_PULL_MASK (0x60U) #define IOMUXD_CSI_RESET_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_CSI_RESET_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_PULL_SHIFT)) & IOMUXD_CSI_RESET_PULL_MASK) #define IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_SHIFT (7U) /*! CSI_RESET_reserved_7_18 - reserved */ #define IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_SHIFT)) & IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_MASK) #define IOMUXD_CSI_RESET_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_CSI_RESET_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_CSI_RESET_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_RESET_WAKEUP_CTRL_MASK) #define IOMUXD_CSI_RESET_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_CSI_RESET_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_CSI_RESET_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_RESET_WAKEUP_MASK_MASK) #define IOMUXD_CSI_RESET_lp_config_MASK (0x1800000U) #define IOMUXD_CSI_RESET_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_CSI_RESET_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_lp_config_SHIFT)) & IOMUXD_CSI_RESET_lp_config_MASK) #define IOMUXD_CSI_RESET_sw_config_MASK (0x6000000U) #define IOMUXD_CSI_RESET_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_CSI_RESET_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_sw_config_SHIFT)) & IOMUXD_CSI_RESET_sw_config_MASK) #define IOMUXD_CSI_RESET_mux_mode_MASK (0x38000000U) #define IOMUXD_CSI_RESET_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..CI_PI.RESET * 0b001..CI_PI.I2C.SDA * 0b010..ADMA.I2C3.SDA * 0b011..ADMA.SPI1.CS0 * 0b100..LSIO.GPIO3.IO03 */ #define IOMUXD_CSI_RESET_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_mux_mode_SHIFT)) & IOMUXD_CSI_RESET_mux_mode_MASK) #define IOMUXD_CSI_RESET_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_CSI_RESET_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_CSI_RESET_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_update_pad_ctl_SHIFT)) & IOMUXD_CSI_RESET_update_pad_ctl_MASK) #define IOMUXD_CSI_RESET_update_mux_mode_MASK (0x80000000U) #define IOMUXD_CSI_RESET_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_CSI_RESET_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_update_mux_mode_SHIFT)) & IOMUXD_CSI_RESET_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_CSI0_MCLK_OUT - MIPI_CSI0_MCLK_OUT */ /*! @{ */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_MASK (0x7U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_MASK) #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_MASK (0x18U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_SHIFT (3U) /*! MIPI_CSI0_MCLK_OUT_reserved_3_4 - reserved */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_MASK) #define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_MASK (0x60U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_MASK) #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_SHIFT (7U) /*! MIPI_CSI0_MCLK_OUT_reserved_7_18 - reserved */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_MASK) #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_MASK) #define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_MASK) #define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_CSI0.ACM.MCLK_OUT * 0b100..LSIO.GPIO3.IO04 */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_MASK) #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_MASK) #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_CSI0_I2C0_SCL - MIPI_CSI0_I2C0_SCL */ /*! @{ */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_MASK (0x7U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_MASK (0x18U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_SHIFT (3U) /*! MIPI_CSI0_I2C0_SCL_reserved_3_4 - reserved */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_MASK (0x60U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_SHIFT (7U) /*! MIPI_CSI0_I2C0_SCL_reserved_7_18 - reserved */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_CSI0.I2C0.SCL * 0b001..MIPI_CSI0.GPIO0.IO02 * 0b100..LSIO.GPIO3.IO05 */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_CSI0_I2C0_SDA - MIPI_CSI0_I2C0_SDA */ /*! @{ */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_MASK (0x7U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_MASK (0x18U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_SHIFT (3U) /*! MIPI_CSI0_I2C0_SDA_reserved_3_4 - reserved */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_MASK (0x60U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_SHIFT (7U) /*! MIPI_CSI0_I2C0_SDA_reserved_7_18 - reserved */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_CSI0.I2C0.SDA * 0b001..MIPI_CSI0.GPIO0.IO03 * 0b100..LSIO.GPIO3.IO06 */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_MASK) #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_CSI0_GPIO0_01 - MIPI_CSI0_GPIO0_01 */ /*! @{ */ #define IOMUXD_MIPI_CSI0_GPIO0_01_DSE_MASK (0x7U) #define IOMUXD_MIPI_CSI0_GPIO0_01_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_MIPI_CSI0_GPIO0_01_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_DSE_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_MASK (0x18U) #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_SHIFT (3U) /*! MIPI_CSI0_GPIO0_01_reserved_3_4 - reserved */ #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_01_PULL_MASK (0x60U) #define IOMUXD_MIPI_CSI0_GPIO0_01_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_MIPI_CSI0_GPIO0_01_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_PULL_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_SHIFT (7U) /*! MIPI_CSI0_GPIO0_01_reserved_7_18 - reserved */ #define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_CSI0.GPIO0.IO01 * 0b001..ADMA.I2C0.SDA * 0b100..LSIO.GPIO3.IO07 */ #define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_MASK) /*! @} */ /*! @name MIPI_CSI0_GPIO0_00 - MIPI_CSI0_GPIO0_00 */ /*! @{ */ #define IOMUXD_MIPI_CSI0_GPIO0_00_DSE_MASK (0x7U) #define IOMUXD_MIPI_CSI0_GPIO0_00_DSE_SHIFT (0U) /*! DSE - Drive * 0b001..Drive select 2mA * 0b011..Drive select 6mA * 0b111..High Speed * 0b110..Drive select 12mA * 0b010..Drive select 4mA * 0b100..Drive select 8mA * 0b000..Drive select 1mA * 0b101..Drive select 10mA */ #define IOMUXD_MIPI_CSI0_GPIO0_00_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_DSE_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_MASK (0x18U) #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_SHIFT (3U) /*! MIPI_CSI0_GPIO0_00_reserved_3_4 - reserved */ #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_00_PULL_MASK (0x60U) #define IOMUXD_MIPI_CSI0_GPIO0_00_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b00..Bus-Keeper * 0b10..pull down * 0b01..pull up * 0b11..No Pull */ #define IOMUXD_MIPI_CSI0_GPIO0_00_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_PULL_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_SHIFT (7U) /*! MIPI_CSI0_GPIO0_00_reserved_7_18 - reserved */ #define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_MASK (0x1800000U) #define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_MASK (0x6000000U) #define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_MASK (0x38000000U) #define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..MIPI_CSI0.GPIO0.IO00 * 0b001..ADMA.I2C0.SCL * 0b100..LSIO.GPIO3.IO08 */ #define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_MASK) #define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_MASK (0x80000000U) #define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_2_4 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_SHIFT (0U) /*! CSI_DIG_D06 - wakeup from CSI_DIG_D06 */ #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_SHIFT (1U) /*! CSI_DIG_D07 - wakeup from CSI_DIG_D07 */ #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_SHIFT (2U) /*! CSI_DIG_HSYNC - wakeup from CSI_DIG_HSYNC */ #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_SHIFT (3U) /*! CSI_DIG_VSYNC - wakeup from CSI_DIG_VSYNC */ #define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_SHIFT (4U) /*! CSI_PCLK - wakeup from CSI_PCLK */ #define IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_SHIFT (5U) /*! CSI_MCLK - wakeup from CSI_MCLK */ #define IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_SHIFT (6U) /*! CSI_EN - wakeup from CSI_EN */ #define IOMUXD_IOMUXD_GROUP_2_4_CSI_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_SHIFT (7U) /*! CSI_RESET - wakeup from CSI_RESET */ #define IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_SHIFT (8U) /*! iomuxd_group_2_4_reserved_8_8 - reserved */ #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_SHIFT (9U) /*! MIPI_CSI0_MCLK_OUT - wakeup from MIPI_CSI0_MCLK_OUT */ #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_SHIFT (10U) /*! MIPI_CSI0_I2C0_SCL - wakeup from MIPI_CSI0_I2C0_SCL */ #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_SHIFT (11U) /*! MIPI_CSI0_I2C0_SDA - wakeup from MIPI_CSI0_I2C0_SDA */ #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_SHIFT (12U) /*! MIPI_CSI0_GPIO0_01 - wakeup from MIPI_CSI0_GPIO0_01 */ #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_MASK (0x2000U) #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_SHIFT (13U) /*! MIPI_CSI0_GPIO0_00 - wakeup from MIPI_CSI0_GPIO0_00 */ #define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_MASK) #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_MASK (0xFFFFC000U) #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_SHIFT (14U) /*! iomuxd_group_2_4_reserved_14_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_MASK) /*! @} */ /*! @name QSPI0A_DATA0 - QSPI0A_DATA0 */ /*! @{ */ #define IOMUXD_QSPI0A_DATA0_PDRV_MASK (0x1U) #define IOMUXD_QSPI0A_DATA0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0A_DATA0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA0_PDRV_MASK) #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_SHIFT (1U) /*! QSPI0A_DATA0_reserved_1_4 - reserved */ #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_MASK) #define IOMUXD_QSPI0A_DATA0_PULL_MASK (0x60U) #define IOMUXD_QSPI0A_DATA0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0A_DATA0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA0_PULL_MASK) #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_SHIFT (7U) /*! QSPI0A_DATA0_reserved_7_18 - reserved */ #define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_MASK) #define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0A_DATA0_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0A_DATA0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0A_DATA0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA0_lp_config_MASK) #define IOMUXD_QSPI0A_DATA0_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0A_DATA0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0A_DATA0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA0_sw_config_MASK) #define IOMUXD_QSPI0A_DATA0_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0A_DATA0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0A.DATA0 * 0b100..LSIO.GPIO3.IO09 */ #define IOMUXD_QSPI0A_DATA0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA0_mux_mode_MASK) #define IOMUXD_QSPI0A_DATA0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0A_DATA0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0A_DATA0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA0_update_pad_ctl_MASK) #define IOMUXD_QSPI0A_DATA0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0A_DATA0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0A_DATA0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA0_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0A_DATA1 - QSPI0A_DATA1 */ /*! @{ */ #define IOMUXD_QSPI0A_DATA1_PDRV_MASK (0x1U) #define IOMUXD_QSPI0A_DATA1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0A_DATA1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA1_PDRV_MASK) #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_SHIFT (1U) /*! QSPI0A_DATA1_reserved_1_4 - reserved */ #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_MASK) #define IOMUXD_QSPI0A_DATA1_PULL_MASK (0x60U) #define IOMUXD_QSPI0A_DATA1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0A_DATA1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA1_PULL_MASK) #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_SHIFT (7U) /*! QSPI0A_DATA1_reserved_7_18 - reserved */ #define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_MASK) #define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0A_DATA1_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0A_DATA1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0A_DATA1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA1_lp_config_MASK) #define IOMUXD_QSPI0A_DATA1_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0A_DATA1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0A_DATA1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA1_sw_config_MASK) #define IOMUXD_QSPI0A_DATA1_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0A_DATA1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0A.DATA1 * 0b100..LSIO.GPIO3.IO10 */ #define IOMUXD_QSPI0A_DATA1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA1_mux_mode_MASK) #define IOMUXD_QSPI0A_DATA1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0A_DATA1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0A_DATA1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA1_update_pad_ctl_MASK) #define IOMUXD_QSPI0A_DATA1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0A_DATA1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0A_DATA1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA1_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0A_DATA2 - QSPI0A_DATA2 */ /*! @{ */ #define IOMUXD_QSPI0A_DATA2_PDRV_MASK (0x1U) #define IOMUXD_QSPI0A_DATA2_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0A_DATA2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA2_PDRV_MASK) #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_SHIFT (1U) /*! QSPI0A_DATA2_reserved_1_4 - reserved */ #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_MASK) #define IOMUXD_QSPI0A_DATA2_PULL_MASK (0x60U) #define IOMUXD_QSPI0A_DATA2_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0A_DATA2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA2_PULL_MASK) #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_SHIFT (7U) /*! QSPI0A_DATA2_reserved_7_18 - reserved */ #define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_MASK) #define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0A_DATA2_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0A_DATA2_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0A_DATA2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA2_lp_config_MASK) #define IOMUXD_QSPI0A_DATA2_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0A_DATA2_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0A_DATA2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA2_sw_config_MASK) #define IOMUXD_QSPI0A_DATA2_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0A_DATA2_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0A.DATA2 * 0b100..LSIO.GPIO3.IO11 */ #define IOMUXD_QSPI0A_DATA2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA2_mux_mode_MASK) #define IOMUXD_QSPI0A_DATA2_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0A_DATA2_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0A_DATA2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA2_update_pad_ctl_MASK) #define IOMUXD_QSPI0A_DATA2_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0A_DATA2_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0A_DATA2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA2_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0A_DATA3 - QSPI0A_DATA3 */ /*! @{ */ #define IOMUXD_QSPI0A_DATA3_PDRV_MASK (0x1U) #define IOMUXD_QSPI0A_DATA3_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0A_DATA3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA3_PDRV_MASK) #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_SHIFT (1U) /*! QSPI0A_DATA3_reserved_1_4 - reserved */ #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_MASK) #define IOMUXD_QSPI0A_DATA3_PULL_MASK (0x60U) #define IOMUXD_QSPI0A_DATA3_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0A_DATA3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA3_PULL_MASK) #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_SHIFT (7U) /*! QSPI0A_DATA3_reserved_7_18 - reserved */ #define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_MASK) #define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0A_DATA3_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0A_DATA3_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0A_DATA3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA3_lp_config_MASK) #define IOMUXD_QSPI0A_DATA3_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0A_DATA3_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0A_DATA3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA3_sw_config_MASK) #define IOMUXD_QSPI0A_DATA3_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0A_DATA3_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0A.DATA3 * 0b100..LSIO.GPIO3.IO12 */ #define IOMUXD_QSPI0A_DATA3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA3_mux_mode_MASK) #define IOMUXD_QSPI0A_DATA3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0A_DATA3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0A_DATA3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA3_update_pad_ctl_MASK) #define IOMUXD_QSPI0A_DATA3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0A_DATA3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0A_DATA3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA3_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0A_DQS - QSPI0A_DQS */ /*! @{ */ #define IOMUXD_QSPI0A_DQS_PDRV_MASK (0x1U) #define IOMUXD_QSPI0A_DQS_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0A_DQS_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_PDRV_SHIFT)) & IOMUXD_QSPI0A_DQS_PDRV_MASK) #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_SHIFT (1U) /*! QSPI0A_DQS_reserved_1_4 - reserved */ #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_MASK) #define IOMUXD_QSPI0A_DQS_PULL_MASK (0x60U) #define IOMUXD_QSPI0A_DQS_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0A_DQS_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_PULL_SHIFT)) & IOMUXD_QSPI0A_DQS_PULL_MASK) #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_SHIFT (7U) /*! QSPI0A_DQS_reserved_7_18 - reserved */ #define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_MASK) #define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0A_DQS_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0A_DQS_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0A_DQS_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DQS_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0A_DQS_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0A_DQS_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0A_DQS_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_lp_config_SHIFT)) & IOMUXD_QSPI0A_DQS_lp_config_MASK) #define IOMUXD_QSPI0A_DQS_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0A_DQS_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0A_DQS_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_sw_config_SHIFT)) & IOMUXD_QSPI0A_DQS_sw_config_MASK) #define IOMUXD_QSPI0A_DQS_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0A_DQS_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0A.DQS * 0b100..LSIO.GPIO3.IO13 */ #define IOMUXD_QSPI0A_DQS_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DQS_mux_mode_MASK) #define IOMUXD_QSPI0A_DQS_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0A_DQS_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0A_DQS_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DQS_update_pad_ctl_MASK) #define IOMUXD_QSPI0A_DQS_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0A_DQS_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0A_DQS_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DQS_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0A_SS0_B - QSPI0A_SS0_B */ /*! @{ */ #define IOMUXD_QSPI0A_SS0_B_PDRV_MASK (0x1U) #define IOMUXD_QSPI0A_SS0_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0A_SS0_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_PDRV_SHIFT)) & IOMUXD_QSPI0A_SS0_B_PDRV_MASK) #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_SHIFT (1U) /*! QSPI0A_SS0_B_reserved_1_4 - reserved */ #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_MASK) #define IOMUXD_QSPI0A_SS0_B_PULL_MASK (0x60U) #define IOMUXD_QSPI0A_SS0_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0A_SS0_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_PULL_SHIFT)) & IOMUXD_QSPI0A_SS0_B_PULL_MASK) #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_SHIFT (7U) /*! QSPI0A_SS0_B_reserved_7_18 - reserved */ #define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_MASK) #define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0A_SS0_B_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0A_SS0_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0A_SS0_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_lp_config_SHIFT)) & IOMUXD_QSPI0A_SS0_B_lp_config_MASK) #define IOMUXD_QSPI0A_SS0_B_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0A_SS0_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0A_SS0_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_sw_config_SHIFT)) & IOMUXD_QSPI0A_SS0_B_sw_config_MASK) #define IOMUXD_QSPI0A_SS0_B_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0A_SS0_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0A.SS0_B * 0b100..LSIO.GPIO3.IO14 */ #define IOMUXD_QSPI0A_SS0_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS0_B_mux_mode_MASK) #define IOMUXD_QSPI0A_SS0_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0A_SS0_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0A_SS0_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SS0_B_update_pad_ctl_MASK) #define IOMUXD_QSPI0A_SS0_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0A_SS0_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0A_SS0_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS0_B_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0A_SS1_B - QSPI0A_SS1_B */ /*! @{ */ #define IOMUXD_QSPI0A_SS1_B_PDRV_MASK (0x1U) #define IOMUXD_QSPI0A_SS1_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0A_SS1_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI0A_SS1_B_PDRV_MASK) #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_SHIFT (1U) /*! QSPI0A_SS1_B_reserved_1_4 - reserved */ #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_MASK) #define IOMUXD_QSPI0A_SS1_B_PULL_MASK (0x60U) #define IOMUXD_QSPI0A_SS1_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0A_SS1_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_PULL_SHIFT)) & IOMUXD_QSPI0A_SS1_B_PULL_MASK) #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_SHIFT (7U) /*! QSPI0A_SS1_B_reserved_7_18 - reserved */ #define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_MASK) #define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0A_SS1_B_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0A_SS1_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0A_SS1_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_lp_config_SHIFT)) & IOMUXD_QSPI0A_SS1_B_lp_config_MASK) #define IOMUXD_QSPI0A_SS1_B_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0A_SS1_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0A_SS1_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_sw_config_SHIFT)) & IOMUXD_QSPI0A_SS1_B_sw_config_MASK) #define IOMUXD_QSPI0A_SS1_B_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0A_SS1_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0A.SS1_B * 0b100..LSIO.GPIO3.IO15 */ #define IOMUXD_QSPI0A_SS1_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS1_B_mux_mode_MASK) #define IOMUXD_QSPI0A_SS1_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0A_SS1_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0A_SS1_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SS1_B_update_pad_ctl_MASK) #define IOMUXD_QSPI0A_SS1_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0A_SS1_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0A_SS1_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS1_B_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0A_SCLK - QSPI0A_SCLK */ /*! @{ */ #define IOMUXD_QSPI0A_SCLK_PDRV_MASK (0x1U) #define IOMUXD_QSPI0A_SCLK_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0A_SCLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_PDRV_SHIFT)) & IOMUXD_QSPI0A_SCLK_PDRV_MASK) #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_SHIFT (1U) /*! QSPI0A_SCLK_reserved_1_4 - reserved */ #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_MASK) #define IOMUXD_QSPI0A_SCLK_PULL_MASK (0x60U) #define IOMUXD_QSPI0A_SCLK_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0A_SCLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_PULL_SHIFT)) & IOMUXD_QSPI0A_SCLK_PULL_MASK) #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_SHIFT (7U) /*! QSPI0A_SCLK_reserved_7_18 - reserved */ #define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_MASK) #define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0A_SCLK_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0A_SCLK_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0A_SCLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_lp_config_SHIFT)) & IOMUXD_QSPI0A_SCLK_lp_config_MASK) #define IOMUXD_QSPI0A_SCLK_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0A_SCLK_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0A_SCLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_sw_config_SHIFT)) & IOMUXD_QSPI0A_SCLK_sw_config_MASK) #define IOMUXD_QSPI0A_SCLK_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0A_SCLK_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0A.SCLK * 0b100..LSIO.GPIO3.IO16 */ #define IOMUXD_QSPI0A_SCLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SCLK_mux_mode_MASK) #define IOMUXD_QSPI0A_SCLK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0A_SCLK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0A_SCLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SCLK_update_pad_ctl_MASK) #define IOMUXD_QSPI0A_SCLK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0A_SCLK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0A_SCLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SCLK_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A - IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0B_SCLK - QSPI0B_SCLK */ /*! @{ */ #define IOMUXD_QSPI0B_SCLK_PDRV_MASK (0x1U) #define IOMUXD_QSPI0B_SCLK_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0B_SCLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_PDRV_SHIFT)) & IOMUXD_QSPI0B_SCLK_PDRV_MASK) #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_SHIFT (1U) /*! QSPI0B_SCLK_reserved_1_4 - reserved */ #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_MASK) #define IOMUXD_QSPI0B_SCLK_PULL_MASK (0x60U) #define IOMUXD_QSPI0B_SCLK_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0B_SCLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_PULL_SHIFT)) & IOMUXD_QSPI0B_SCLK_PULL_MASK) #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_SHIFT (7U) /*! QSPI0B_SCLK_reserved_7_18 - reserved */ #define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_MASK) #define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0B_SCLK_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0B_SCLK_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0B_SCLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_lp_config_SHIFT)) & IOMUXD_QSPI0B_SCLK_lp_config_MASK) #define IOMUXD_QSPI0B_SCLK_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0B_SCLK_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0B_SCLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_sw_config_SHIFT)) & IOMUXD_QSPI0B_SCLK_sw_config_MASK) #define IOMUXD_QSPI0B_SCLK_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0B_SCLK_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0B.SCLK * 0b001..LSIO.QSPI1A.SCLK * 0b010..LSIO.KPP0.COL0 * 0b100..LSIO.GPIO3.IO17 */ #define IOMUXD_QSPI0B_SCLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SCLK_mux_mode_MASK) #define IOMUXD_QSPI0B_SCLK_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0B_SCLK_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0B_SCLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SCLK_update_pad_ctl_MASK) #define IOMUXD_QSPI0B_SCLK_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0B_SCLK_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0B_SCLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SCLK_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0B_DATA0 - QSPI0B_DATA0 */ /*! @{ */ #define IOMUXD_QSPI0B_DATA0_PDRV_MASK (0x1U) #define IOMUXD_QSPI0B_DATA0_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0B_DATA0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA0_PDRV_MASK) #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_SHIFT (1U) /*! QSPI0B_DATA0_reserved_1_4 - reserved */ #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_MASK) #define IOMUXD_QSPI0B_DATA0_PULL_MASK (0x60U) #define IOMUXD_QSPI0B_DATA0_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0B_DATA0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA0_PULL_MASK) #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_SHIFT (7U) /*! QSPI0B_DATA0_reserved_7_18 - reserved */ #define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_MASK) #define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0B_DATA0_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0B_DATA0_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0B_DATA0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA0_lp_config_MASK) #define IOMUXD_QSPI0B_DATA0_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0B_DATA0_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0B_DATA0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA0_sw_config_MASK) #define IOMUXD_QSPI0B_DATA0_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0B_DATA0_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0B.DATA0 * 0b001..LSIO.QSPI1A.DATA0 * 0b010..LSIO.KPP0.COL1 * 0b100..LSIO.GPIO3.IO18 */ #define IOMUXD_QSPI0B_DATA0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA0_mux_mode_MASK) #define IOMUXD_QSPI0B_DATA0_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0B_DATA0_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0B_DATA0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA0_update_pad_ctl_MASK) #define IOMUXD_QSPI0B_DATA0_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0B_DATA0_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0B_DATA0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA0_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0B_DATA1 - QSPI0B_DATA1 */ /*! @{ */ #define IOMUXD_QSPI0B_DATA1_PDRV_MASK (0x1U) #define IOMUXD_QSPI0B_DATA1_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0B_DATA1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA1_PDRV_MASK) #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_SHIFT (1U) /*! QSPI0B_DATA1_reserved_1_4 - reserved */ #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_MASK) #define IOMUXD_QSPI0B_DATA1_PULL_MASK (0x60U) #define IOMUXD_QSPI0B_DATA1_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0B_DATA1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA1_PULL_MASK) #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_SHIFT (7U) /*! QSPI0B_DATA1_reserved_7_18 - reserved */ #define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_MASK) #define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0B_DATA1_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0B_DATA1_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0B_DATA1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA1_lp_config_MASK) #define IOMUXD_QSPI0B_DATA1_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0B_DATA1_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0B_DATA1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA1_sw_config_MASK) #define IOMUXD_QSPI0B_DATA1_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0B_DATA1_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0B.DATA1 * 0b001..LSIO.QSPI1A.DATA1 * 0b010..LSIO.KPP0.COL2 * 0b100..LSIO.GPIO3.IO19 */ #define IOMUXD_QSPI0B_DATA1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA1_mux_mode_MASK) #define IOMUXD_QSPI0B_DATA1_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0B_DATA1_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0B_DATA1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA1_update_pad_ctl_MASK) #define IOMUXD_QSPI0B_DATA1_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0B_DATA1_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0B_DATA1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA1_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0B_DATA2 - QSPI0B_DATA2 */ /*! @{ */ #define IOMUXD_QSPI0B_DATA2_PDRV_MASK (0x1U) #define IOMUXD_QSPI0B_DATA2_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0B_DATA2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA2_PDRV_MASK) #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_SHIFT (1U) /*! QSPI0B_DATA2_reserved_1_4 - reserved */ #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_MASK) #define IOMUXD_QSPI0B_DATA2_PULL_MASK (0x60U) #define IOMUXD_QSPI0B_DATA2_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0B_DATA2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA2_PULL_MASK) #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_SHIFT (7U) /*! QSPI0B_DATA2_reserved_7_18 - reserved */ #define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_MASK) #define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0B_DATA2_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0B_DATA2_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0B_DATA2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA2_lp_config_MASK) #define IOMUXD_QSPI0B_DATA2_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0B_DATA2_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0B_DATA2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA2_sw_config_MASK) #define IOMUXD_QSPI0B_DATA2_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0B_DATA2_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0B.DATA2 * 0b001..LSIO.QSPI1A.DATA2 * 0b010..LSIO.KPP0.COL3 * 0b100..LSIO.GPIO3.IO20 */ #define IOMUXD_QSPI0B_DATA2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA2_mux_mode_MASK) #define IOMUXD_QSPI0B_DATA2_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0B_DATA2_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0B_DATA2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA2_update_pad_ctl_MASK) #define IOMUXD_QSPI0B_DATA2_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0B_DATA2_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0B_DATA2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA2_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0B_DATA3 - QSPI0B_DATA3 */ /*! @{ */ #define IOMUXD_QSPI0B_DATA3_PDRV_MASK (0x1U) #define IOMUXD_QSPI0B_DATA3_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0B_DATA3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA3_PDRV_MASK) #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_SHIFT (1U) /*! QSPI0B_DATA3_reserved_1_4 - reserved */ #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_MASK) #define IOMUXD_QSPI0B_DATA3_PULL_MASK (0x60U) #define IOMUXD_QSPI0B_DATA3_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0B_DATA3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA3_PULL_MASK) #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_SHIFT (7U) /*! QSPI0B_DATA3_reserved_7_18 - reserved */ #define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_MASK) #define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0B_DATA3_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0B_DATA3_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0B_DATA3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA3_lp_config_MASK) #define IOMUXD_QSPI0B_DATA3_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0B_DATA3_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0B_DATA3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA3_sw_config_MASK) #define IOMUXD_QSPI0B_DATA3_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0B_DATA3_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0B.DATA3 * 0b001..LSIO.QSPI1A.DATA3 * 0b010..LSIO.KPP0.ROW0 * 0b100..LSIO.GPIO3.IO21 */ #define IOMUXD_QSPI0B_DATA3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA3_mux_mode_MASK) #define IOMUXD_QSPI0B_DATA3_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0B_DATA3_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0B_DATA3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA3_update_pad_ctl_MASK) #define IOMUXD_QSPI0B_DATA3_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0B_DATA3_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0B_DATA3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA3_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0B_DQS - QSPI0B_DQS */ /*! @{ */ #define IOMUXD_QSPI0B_DQS_PDRV_MASK (0x1U) #define IOMUXD_QSPI0B_DQS_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0B_DQS_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_PDRV_SHIFT)) & IOMUXD_QSPI0B_DQS_PDRV_MASK) #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_SHIFT (1U) /*! QSPI0B_DQS_reserved_1_4 - reserved */ #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_MASK) #define IOMUXD_QSPI0B_DQS_PULL_MASK (0x60U) #define IOMUXD_QSPI0B_DQS_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0B_DQS_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_PULL_SHIFT)) & IOMUXD_QSPI0B_DQS_PULL_MASK) #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_SHIFT (7U) /*! QSPI0B_DQS_reserved_7_18 - reserved */ #define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_MASK) #define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0B_DQS_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0B_DQS_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0B_DQS_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DQS_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0B_DQS_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0B_DQS_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0B_DQS_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_lp_config_SHIFT)) & IOMUXD_QSPI0B_DQS_lp_config_MASK) #define IOMUXD_QSPI0B_DQS_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0B_DQS_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0B_DQS_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_sw_config_SHIFT)) & IOMUXD_QSPI0B_DQS_sw_config_MASK) #define IOMUXD_QSPI0B_DQS_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0B_DQS_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0B.DQS * 0b001..LSIO.QSPI1A.DQS * 0b010..LSIO.KPP0.ROW1 * 0b100..LSIO.GPIO3.IO22 */ #define IOMUXD_QSPI0B_DQS_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DQS_mux_mode_MASK) #define IOMUXD_QSPI0B_DQS_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0B_DQS_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0B_DQS_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DQS_update_pad_ctl_MASK) #define IOMUXD_QSPI0B_DQS_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0B_DQS_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0B_DQS_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DQS_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_3_0 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_SHIFT (0U) /*! QSPI0A_DATA0 - wakeup from QSPI0A_DATA0 */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_SHIFT (1U) /*! QSPI0A_DATA1 - wakeup from QSPI0A_DATA1 */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_MASK (0x4U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_SHIFT (2U) /*! QSPI0A_DATA2 - wakeup from QSPI0A_DATA2 */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_MASK (0x8U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_SHIFT (3U) /*! QSPI0A_DATA3 - wakeup from QSPI0A_DATA3 */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_MASK (0x10U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_SHIFT (4U) /*! QSPI0A_DQS - wakeup from QSPI0A_DQS */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_MASK (0x20U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_SHIFT (5U) /*! QSPI0A_SS0_B - wakeup from QSPI0A_SS0_B */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_MASK (0x40U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_SHIFT (6U) /*! QSPI0A_SS1_B - wakeup from QSPI0A_SS1_B */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_MASK (0x80U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_SHIFT (7U) /*! QSPI0A_SCLK - wakeup from QSPI0A_SCLK */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_MASK (0x100U) #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_SHIFT (8U) /*! iomuxd_group_3_0_reserved_8_8 - reserved */ #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_MASK (0x200U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_SHIFT (9U) /*! QSPI0B_SCLK - wakeup from QSPI0B_SCLK */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_MASK (0x400U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_SHIFT (10U) /*! QSPI0B_DATA0 - wakeup from QSPI0B_DATA0 */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_MASK (0x800U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_SHIFT (11U) /*! QSPI0B_DATA1 - wakeup from QSPI0B_DATA1 */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_MASK (0x1000U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_SHIFT (12U) /*! QSPI0B_DATA2 - wakeup from QSPI0B_DATA2 */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_MASK (0x2000U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_SHIFT (13U) /*! QSPI0B_DATA3 - wakeup from QSPI0B_DATA3 */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_MASK (0x4000U) #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_SHIFT (14U) /*! QSPI0B_DQS - wakeup from QSPI0B_DQS */ #define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_MASK) #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_MASK (0xFFFF8000U) #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_SHIFT (15U) /*! iomuxd_group_3_0_reserved_15_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_MASK) /*! @} */ /*! @name QSPI0B_SS0_B - QSPI0B_SS0_B */ /*! @{ */ #define IOMUXD_QSPI0B_SS0_B_PDRV_MASK (0x1U) #define IOMUXD_QSPI0B_SS0_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0B_SS0_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_PDRV_SHIFT)) & IOMUXD_QSPI0B_SS0_B_PDRV_MASK) #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_SHIFT (1U) /*! QSPI0B_SS0_B_reserved_1_4 - reserved */ #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_MASK) #define IOMUXD_QSPI0B_SS0_B_PULL_MASK (0x60U) #define IOMUXD_QSPI0B_SS0_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0B_SS0_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_PULL_SHIFT)) & IOMUXD_QSPI0B_SS0_B_PULL_MASK) #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_SHIFT (7U) /*! QSPI0B_SS0_B_reserved_7_18 - reserved */ #define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_MASK) #define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0B_SS0_B_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0B_SS0_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0B_SS0_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_lp_config_SHIFT)) & IOMUXD_QSPI0B_SS0_B_lp_config_MASK) #define IOMUXD_QSPI0B_SS0_B_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0B_SS0_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0B_SS0_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_sw_config_SHIFT)) & IOMUXD_QSPI0B_SS0_B_sw_config_MASK) #define IOMUXD_QSPI0B_SS0_B_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0B_SS0_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0B.SS0_B * 0b001..LSIO.QSPI1A.SS0_B * 0b010..LSIO.KPP0.ROW2 * 0b100..LSIO.GPIO3.IO23 */ #define IOMUXD_QSPI0B_SS0_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS0_B_mux_mode_MASK) #define IOMUXD_QSPI0B_SS0_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0B_SS0_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0B_SS0_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SS0_B_update_pad_ctl_MASK) #define IOMUXD_QSPI0B_SS0_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0B_SS0_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0B_SS0_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS0_B_update_mux_mode_MASK) /*! @} */ /*! @name QSPI0B_SS1_B - QSPI0B_SS1_B */ /*! @{ */ #define IOMUXD_QSPI0B_SS1_B_PDRV_MASK (0x1U) #define IOMUXD_QSPI0B_SS1_B_PDRV_SHIFT (0U) /*! PDRV - Drive * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications */ #define IOMUXD_QSPI0B_SS1_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI0B_SS1_B_PDRV_MASK) #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_MASK (0x1EU) #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_SHIFT (1U) /*! QSPI0B_SS1_B_reserved_1_4 - reserved */ #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_MASK) #define IOMUXD_QSPI0B_SS1_B_PULL_MASK (0x60U) #define IOMUXD_QSPI0B_SS1_B_PULL_SHIFT (5U) /*! PULL - Pull Down Pull Up * 0b10..pull down * 0b01..pull up * 0b00..Prohibited * 0b11..pull disabled */ #define IOMUXD_QSPI0B_SS1_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_PULL_SHIFT)) & IOMUXD_QSPI0B_SS1_B_PULL_MASK) #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_MASK (0x7FF80U) #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_SHIFT (7U) /*! QSPI0B_SS1_B_reserved_7_18 - reserved */ #define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_MASK) #define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_MASK (0x380000U) #define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_SHIFT (19U) /*! WAKEUP_CTRL - wakeup control * 0b000..OFF * 0b001..RESAMPLE * 0b100..LOW * 0b111..HIGH * 0b110..RISE * 0b101..FALL */ #define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_MASK) #define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_MASK (0x400000U) #define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_SHIFT (22U) /*! WAKEUP_MASK - wakeup mask */ #define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_MASK) #define IOMUXD_QSPI0B_SS1_B_lp_config_MASK (0x1800000U) #define IOMUXD_QSPI0B_SS1_B_lp_config_SHIFT (23U) /*! lp_config - lower power configuration * 0b01..EARLY_ISO * 0b10..LATE_ISO * 0b11..LATCH * 0b00..PASS */ #define IOMUXD_QSPI0B_SS1_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_lp_config_SHIFT)) & IOMUXD_QSPI0B_SS1_B_lp_config_MASK) #define IOMUXD_QSPI0B_SS1_B_sw_config_MASK (0x6000000U) #define IOMUXD_QSPI0B_SS1_B_sw_config_SHIFT (25U) /*! sw_config - output and input configuration * 0b01..OPEN_DRAIN * 0b10..OPEN_DRAIN_INPUT * 0b11..INOUT * 0b00..DEFAULT */ #define IOMUXD_QSPI0B_SS1_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_sw_config_SHIFT)) & IOMUXD_QSPI0B_SS1_B_sw_config_MASK) #define IOMUXD_QSPI0B_SS1_B_mux_mode_MASK (0x38000000U) #define IOMUXD_QSPI0B_SS1_B_mux_mode_SHIFT (27U) /*! mux_mode - mux_mode * 0b000..LSIO.QSPI0B.SS1_B * 0b001..LSIO.QSPI1A.SS1_B * 0b010..LSIO.KPP0.ROW3 * 0b100..LSIO.GPIO3.IO24 */ #define IOMUXD_QSPI0B_SS1_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS1_B_mux_mode_MASK) #define IOMUXD_QSPI0B_SS1_B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_QSPI0B_SS1_B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_QSPI0B_SS1_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SS1_B_update_pad_ctl_MASK) #define IOMUXD_QSPI0B_SS1_B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_QSPI0B_SS1_B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_QSPI0B_SS1_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS1_B_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B - IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B */ /*! @{ */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_MASK (0x7U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_SHIFT (0U) /*! COMP - COMP * 0b010..Fixed code mode * 0b100..High impedance mode * 0b110..Read mode * 0b000..Normal Mode * 0b001..Freeze Mode */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_MASK (0x8U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_SHIFT (3U) /*! FASTFRZ_EN - FASTFRZ_EN * 0b1..FASTFRZ signal is driven by output of subsystem * 0b0..FASTFRZ signal is gated to 0 */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_MASK (0x10U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_SHIFT (4U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_MASK (0x1E0U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_SHIFT (5U) /*! RASRCP - RASRCP * 0b0101..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_MASK (0x1E00U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_SHIFT (9U) /*! RASRCN - RASRCN * 0b1010..Reset Value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_MASK (0x2000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_SHIFT (13U) /*! SELECT_NASRC - SELECT_NASRC * 0b1..NASRCN value * 0b0..NASRCP value */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_MASK (0x4000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_SHIFT (14U) /*! COMPOK - COMPOK * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode * 0b1..compensation cell in Normal mode and tracking PVT */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_MASK (0x78000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_SHIFT (15U) /*! READ_NASRC - READ_NASRC * 0b0000..READ Only */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_MASK (0x780000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_SHIFT (19U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_MASK (0x1800000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_SHIFT (23U) /*! SLEEP - SLEEP * 0b11..Force into sleep mode * 0b00..NO * 0b01..EARLY * 0b10..LATE */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_MASK (0x3E000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_SHIFT (25U) /*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29 - reserved */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_MASK (0x40000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_SHIFT (30U) /*! update_pad_ctl - update lock for pad control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_MASK) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_MASK (0x80000000U) #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_SHIFT (31U) /*! update_mux_mode - update lock for mux control */ #define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_MASK) /*! @} */ /*! @name IOMUXD_GROUP_3_1 - na */ /*! @{ */ #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_MASK (0x1U) #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_SHIFT (0U) /*! QSPI0B_SS0_B - wakeup from QSPI0B_SS0_B */ #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_MASK) #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_MASK (0x2U) #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_SHIFT (1U) /*! QSPI0B_SS1_B - wakeup from QSPI0B_SS1_B */ #define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_MASK) #define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_MASK (0xFFFFFFFCU) #define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_SHIFT (2U) /*! iomuxd_group_3_1_reserved_2_31 - reserved */ #define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_MASK) /*! @} */ /*! * @} */ /* end of group IOMUXD_Register_Masks */ /* IOMUXD - Peripheral instance base addresses */ /** Peripheral IOMUXD base address */ #define IOMUXD_BASE (0x33F80000u) /** Peripheral IOMUXD base pointer */ #define IOMUXD ((IOMUXD_Type *)IOMUXD_BASE) /** Array initializer of IOMUXD peripheral base addresses */ #define IOMUXD_BASE_ADDRS { IOMUXD_BASE } /** Array initializer of IOMUXD peripheral base pointers */ #define IOMUXD_BASE_PTRS { IOMUXD } /*! * @} */ /* end of group IOMUXD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IRIS_MVPL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IRIS_MVPL_Peripheral_Access_Layer IRIS_MVPL Peripheral Access Layer * @{ */ /** IRIS_MVPL - Register Layout Typedef */ typedef struct { __IO uint32_t IPIDENTIFIER; /**< IP Identifier for this SEERIS derivate., offset: 0x0 */ uint8_t RESERVED_0[60]; __I uint32_t COMCTRL_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x40 */ __I uint32_t COMCTRL_LOCKSTATUS; /**< Protection status of this address block., offset: 0x44 */ __IO uint32_t COMCTRL_USERINTERRUPTMASK0; /**< Interrupt UserMask register 0, offset: 0x48 */ __IO uint32_t COMCTRL_USERINTERRUPTMASK1; /**< Interrupt UserMask register 1, offset: 0x4C */ __I uint32_t COMCTRL_INTERRUPTENABLE0; /**< Interrupt Enable register 0, offset: 0x50 */ __I uint32_t COMCTRL_INTERRUPTENABLE1; /**< Interrupt Enable register 1, offset: 0x54 */ __O uint32_t COMCTRL_INTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x58 */ __O uint32_t COMCTRL_INTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x5C */ __O uint32_t COMCTRL_INTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x60 */ __O uint32_t COMCTRL_INTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x64 */ __I uint32_t COMCTRL_INTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x68 */ __I uint32_t COMCTRL_INTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x6C */ uint8_t RESERVED_1[16]; __I uint32_t USERINTERRUPTENABLE0; /**< Interrupt Enable register 0 for user mode access, offset: 0x80 */ __I uint32_t USERINTERRUPTENABLE1; /**< Interrupt Enable register 1 for user mode access, offset: 0x84 */ __O uint32_t USERINTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x88 */ __O uint32_t USERINTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x8C */ __O uint32_t USERINTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x90 */ __O uint32_t USERINTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x94 */ __I uint32_t USERINTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x98 */ __I uint32_t USERINTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x9C */ uint8_t RESERVED_2[96]; __IO uint32_t GENERALPURPOSE; /**< General purpose config memory, offset: 0x100 */ uint8_t RESERVED_3[764]; __I uint32_t CMDSEQ_HIF; /**< Command input buffer, offset: 0x400 */ uint8_t RESERVED_4[252]; __I uint32_t CMDSEQ_LOCKUNLOCKHIF; /**< Register to change the protection status of this address block., offset: 0x500 */ __I uint32_t CMDSEQ_LOCKSTATUSHIF; /**< Protection status of this address block., offset: 0x504 */ uint8_t RESERVED_5[120]; __I uint32_t CMDSEQ_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x580 */ __I uint32_t CMDSEQ_LOCKSTATUS; /**< Protection status of this address block., offset: 0x584 */ __IO uint32_t CMDSEQ_BUFFERADDRESS; /**< Command buffer address register, offset: 0x588 */ __IO uint32_t CMDSEQ_BUFFERSIZE; /**< Command buffer size register, offset: 0x58C */ __IO uint32_t CMDSEQ_WATERMARKCONTROL; /**< Watermark Control register, offset: 0x590 */ __O uint32_t CMDSEQ_CONTROL; /**< Control register, offset: 0x594 */ __I uint32_t CMDSEQ_STATUS; /**< Status register, offset: 0x598 */ __IO uint32_t CMDSEQ_PREFETCHWINDOWSTART; /**< PrefetchWindowStart register, offset: 0x59C */ __IO uint32_t CMDSEQ_PREFETCHWINDOWEND; /**< PrefetchWindowEnd register, offset: 0x5A0 */ uint8_t RESERVED_6[604]; __I uint32_t SAFETYLOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x800 */ __I uint32_t SAFETYLOCKSTATUS; /**< Protection status of this address block., offset: 0x804 */ __IO uint32_t STORE9_SAFETYMASK; /**< Safety mask for store9, offset: 0x808 */ __IO uint32_t EXTDST0_SAFETYMASK; /**< Safety mask for extdst0, offset: 0x80C */ __IO uint32_t EXTDST4_SAFETYMASK; /**< Safety mask for extdst4, offset: 0x810 */ __IO uint32_t EXTDST1_SAFETYMASK; /**< Safety mask for extdst1, offset: 0x814 */ __IO uint32_t EXTDST5_SAFETYMASK; /**< Safety mask for extdst5, offset: 0x818 */ uint8_t RESERVED_7[4]; __I uint32_t FETCHDECODE32_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x820 */ __I uint32_t FETCHDECODE32_LOCKSTATUS; /**< Protection status of this address block., offset: 0x824 */ __IO uint32_t FETCHDECODE_DYNAMIC; /**< Dynamic pixel engine configuration for fetchdecode9, offset: 0x828 */ __I uint32_t FETCHDECODE_STATUS; /**< Status information for pixel engine configuration of fetchdecode9, offset: 0x82C */ uint8_t RESERVED_8[16]; __I uint32_t FETCHWARP64_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x840 */ __I uint32_t FETCHWARP64_LOCKSTATUS; /**< Protection status of this address block., offset: 0x844 */ __IO uint32_t FETCHWARP64_DYNAMIC; /**< Dynamic pixel engine configuration for fetchwarp9, offset: 0x848 */ __I uint32_t FETCHWARP64_STATUS; /**< Status information for pixel engine configuration of fetchwarp9, offset: 0x84C */ __I uint32_t FETCHECO80_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x850 */ __I uint32_t FETCHECO80_LOCKSTATUS; /**< Protection status of this address block., offset: 0x854 */ __I uint32_t FETCHECO_STATUS; /**< Status information for pixel engine configuration of fetcheco9, offset: 0x858 */ uint8_t RESERVED_9[4]; __I uint32_t ROP_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x860 */ __I uint32_t ROP_LOCKSTATUS; /**< Protection status of this address block., offset: 0x864 */ __IO uint32_t ROP_DYNAMIC; /**< Dynamic pixel engine configuration for rop9, offset: 0x868 */ __I uint32_t ROP_STATUS; /**< Status information for pixel engine configuration of rop9, offset: 0x86C */ uint8_t RESERVED_10[16]; __I uint32_t CLUT_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x880 */ __I uint32_t CLUT_LOCKSTATUS; /**< Protection status of this address block., offset: 0x884 */ __IO uint32_t CLUT_DYNAMIC; /**< Dynamic pixel engine configuration for clut9, offset: 0x888 */ __I uint32_t CLUT_STATUS; /**< Status information for pixel engine configuration of clut9, offset: 0x88C */ uint8_t RESERVED_11[16]; __I uint32_t MATRIX160_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8A0 */ __I uint32_t MATRIX160_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8A4 */ __IO uint32_t MATRIX_DYNAMIC; /**< Dynamic pixel engine configuration for matrix9, offset: 0x8A8 */ __I uint32_t MATRIX_STATUS; /**< Status information for pixel engine configuration of matrix9, offset: 0x8AC */ uint8_t RESERVED_12[16]; __I uint32_t HSCALER192_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8C0 */ __I uint32_t HSCALER192_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8C4 */ __IO uint32_t HSCALER_DYNAMIC; /**< Dynamic pixel engine configuration for hscaler9, offset: 0x8C8 */ __I uint32_t HSCALER_STATUS; /**< Status information for pixel engine configuration of hscaler9, offset: 0x8CC */ uint8_t RESERVED_13[16]; __I uint32_t VSCALER224_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8E0 */ __I uint32_t VSCALER224_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8E4 */ __IO uint32_t VSCALER_DYNAMIC; /**< Dynamic pixel engine configuration for vscaler9, offset: 0x8E8 */ __I uint32_t VSCALER_STATUS; /**< Status information for pixel engine configuration of vscaler9, offset: 0x8EC */ uint8_t RESERVED_14[16]; __I uint32_t FILTER_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x900 */ __I uint32_t FILTER_LOCKSTATUS; /**< Protection status of this address block., offset: 0x904 */ __IO uint32_t FILTER_DYNAMIC; /**< Dynamic pixel engine configuration for filter9, offset: 0x908 */ __I uint32_t FILTER_STATUS; /**< Status information for pixel engine configuration of filter9, offset: 0x90C */ uint8_t RESERVED_15[16]; __I uint32_t BLITBLEND_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x920 */ __I uint32_t BLITBLEND_LOCKSTATUS; /**< Protection status of this address block., offset: 0x924 */ __IO uint32_t BLITBLEND_DYNAMIC; /**< Dynamic pixel engine configuration for blitblend9, offset: 0x928 */ __I uint32_t BLITBLEND_STATUS; /**< Status information for pixel engine configuration of blitblend9, offset: 0x92C */ uint8_t RESERVED_16[16]; __I uint32_t STORE_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x940 */ __I uint32_t STORE_LOCKSTATUS; /**< Protection status of this address block., offset: 0x944 */ __IO uint32_t STORE9_STATIC; /**< Static pixel engine configuration for store9, offset: 0x948 */ __IO uint32_t STORE_DYNAMIC; /**< Dynamic pixel engine configuration for store9, offset: 0x94C */ __I uint32_t STORE9_REQUEST; /**< ShadowLoadRequest register for endpoint store9, offset: 0x950 */ __O uint32_t STORE9_TRIGGER; /**< Trigger bits for pixel engine configuration of store9, offset: 0x954 */ __I uint32_t STORE_STATUS; /**< Status information for pixel engine configuration of store9, offset: 0x958 */ uint8_t RESERVED_17[4]; __I uint32_t CONSTFRAME352_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x960 */ __I uint32_t CONSTFRAME352_LOCKSTATUS; /**< Protection status of this address block., offset: 0x964 */ __I uint32_t CONSTFRAME352_STATUS; /**< Status information for pixel engine configuration of constframe0, offset: 0x968 */ uint8_t RESERVED_18[20]; __I uint32_t EXTDST384_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x980 */ __I uint32_t EXTDST384_LOCKSTATUS; /**< Protection status of this address block., offset: 0x984 */ __IO uint32_t EXTDST384_STATIC; /**< Static pixel engine configuration for extdst0, offset: 0x988 */ __IO uint32_t EXTDST384_DYNAMIC; /**< Dynamic pixel engine configuration for extdst0, offset: 0x98C */ __I uint32_t EXTDST384_REQUEST; /**< ShadowLoadRequest register for endpoint extdst0, offset: 0x990 */ __O uint32_t EXTDST384_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst0, offset: 0x994 */ __I uint32_t EXTDST384_STATUS; /**< Status information for pixel engine configuration of extdst0, offset: 0x998 */ uint8_t RESERVED_19[4]; __I uint32_t CONSTFRAME416_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9A0 */ __I uint32_t CONSTFRAME416_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9A4 */ __I uint32_t CONSTFRAME416_STATUS; /**< Status information for pixel engine configuration of constframe4, offset: 0x9A8 */ uint8_t RESERVED_20[20]; __I uint32_t EXTDST448_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9C0 */ __I uint32_t EXTDST448_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9C4 */ __IO uint32_t EXTDST448_STATIC; /**< Static pixel engine configuration for extdst4, offset: 0x9C8 */ __IO uint32_t EXTDST448_DYNAMIC; /**< Dynamic pixel engine configuration for extdst4, offset: 0x9CC */ __I uint32_t EXTDST448_REQUEST; /**< ShadowLoadRequest register for endpoint extdst4, offset: 0x9D0 */ __O uint32_t EXTDST448_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst4, offset: 0x9D4 */ __I uint32_t EXTDST448_STATUS; /**< Status information for pixel engine configuration of extdst4, offset: 0x9D8 */ uint8_t RESERVED_21[4]; __I uint32_t CONSTFRAME480_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9E0 */ __I uint32_t CONSTFRAME480_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9E4 */ __I uint32_t CONSTFRAME480_STATUS; /**< Status information for pixel engine configuration of constframe1, offset: 0x9E8 */ uint8_t RESERVED_22[20]; __I uint32_t EXTDST512_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA00 */ __I uint32_t EXTDST512_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA04 */ __IO uint32_t EXTDST1_STATIC; /**< Static pixel engine configuration for extdst1, offset: 0xA08 */ __IO uint32_t EXTDST1_DYNAMIC; /**< Dynamic pixel engine configuration for extdst1, offset: 0xA0C */ __I uint32_t EXTDST1_REQUEST; /**< ShadowLoadRequest register for endpoint extdst1, offset: 0xA10 */ __O uint32_t EXTDST1_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst1, offset: 0xA14 */ __I uint32_t EXTDST512_STATUS; /**< Status information for pixel engine configuration of extdst1, offset: 0xA18 */ uint8_t RESERVED_23[4]; __I uint32_t CONSTFRAME_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA20 */ __I uint32_t CONSTFRAME_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA24 */ __I uint32_t CONSTFRAME_STATUS; /**< Status information for pixel engine configuration of constframe5, offset: 0xA28 */ uint8_t RESERVED_24[20]; __I uint32_t EXTDST544_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA40 */ __I uint32_t EXTDST544_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA44 */ __IO uint32_t EXTDST5_STATIC; /**< Static pixel engine configuration for extdst5, offset: 0xA48 */ __IO uint32_t EXTDST5_DYNAMIC; /**< Dynamic pixel engine configuration for extdst5, offset: 0xA4C */ __I uint32_t EXTDST5_REQUEST; /**< ShadowLoadRequest register for endpoint extdst5, offset: 0xA50 */ __O uint32_t EXTDST5_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst5, offset: 0xA54 */ __I uint32_t EXTDST544_STATUS; /**< Status information for pixel engine configuration of extdst5, offset: 0xA58 */ uint8_t RESERVED_25[4]; __I uint32_t FETCHWARP608_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA60 */ __I uint32_t FETCHWARP608_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA64 */ __IO uint32_t FETCHWARP608_DYNAMIC; /**< Dynamic pixel engine configuration for fetchwarp2, offset: 0xA68 */ __I uint32_t FETCHWARP608_STATUS; /**< Status information for pixel engine configuration of fetchwarp2, offset: 0xA6C */ __I uint32_t FETCHECO624_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA70 */ __I uint32_t FETCHECO624_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA74 */ __I uint32_t FETCHECO2_STATUS; /**< Status information for pixel engine configuration of fetcheco2, offset: 0xA78 */ uint8_t RESERVED_26[4]; __I uint32_t FETCHDECODE0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA80 */ __I uint32_t FETCHDECODE0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA84 */ __IO uint32_t FETCHDECODE0_DYNAMIC; /**< Dynamic pixel engine configuration for fetchdecode0, offset: 0xA88 */ __I uint32_t FETCHDECODE0_STATUS; /**< Status information for pixel engine configuration of fetchdecode0, offset: 0xA8C */ __I uint32_t FETCHECO656_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA90 */ __I uint32_t FETCHECO656_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA94 */ __I uint32_t FETCHECO0_STATUS; /**< Status information for pixel engine configuration of fetcheco0, offset: 0xA98 */ uint8_t RESERVED_27[4]; __I uint32_t FETCHDECODE672_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xAA0 */ __I uint32_t FETCHDECODE672_LOCKSTATUS; /**< Protection status of this address block., offset: 0xAA4 */ __IO uint32_t FETCHDECODE1_DYNAMIC; /**< Dynamic pixel engine configuration for fetchdecode1, offset: 0xAA8 */ __I uint32_t FETCHDECODE1_STATUS; /**< Status information for pixel engine configuration of fetchdecode1, offset: 0xAAC */ __I uint32_t FETCHECO688_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xAB0 */ __I uint32_t FETCHECO688_LOCKSTATUS; /**< Protection status of this address block., offset: 0xAB4 */ __I uint32_t FETCHECO1_STATUS; /**< Status information for pixel engine configuration of fetcheco1, offset: 0xAB8 */ uint8_t RESERVED_28[4]; __I uint32_t FETCHLAYER704_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xAC0 */ __I uint32_t FETCHLAYER704_LOCKSTATUS; /**< Protection status of this address block., offset: 0xAC4 */ __I uint32_t FETCHLAYER704_STATUS; /**< Status information for pixel engine configuration of fetchlayer0, offset: 0xAC8 */ uint8_t RESERVED_29[20]; __I uint32_t MATRIX736_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xAE0 */ __I uint32_t MATRIX736_LOCKSTATUS; /**< Protection status of this address block., offset: 0xAE4 */ __IO uint32_t MATRIX4_DYNAMIC; /**< Dynamic pixel engine configuration for matrix4, offset: 0xAE8 */ __I uint32_t MATRIX4_STATUS; /**< Status information for pixel engine configuration of matrix4, offset: 0xAEC */ uint8_t RESERVED_30[16]; __I uint32_t HSCALER768_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB00 */ __I uint32_t HSCALER768_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB04 */ __IO uint32_t HSCALER4_DYNAMIC; /**< Dynamic pixel engine configuration for hscaler4, offset: 0xB08 */ __I uint32_t HSCALER4_STATUS; /**< Status information for pixel engine configuration of hscaler4, offset: 0xB0C */ uint8_t RESERVED_31[16]; __I uint32_t VSCALER800_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB20 */ __I uint32_t VSCALER800_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB24 */ __IO uint32_t VSCALER4_DYNAMIC; /**< Dynamic pixel engine configuration for vscaler4, offset: 0xB28 */ __I uint32_t VSCALER4_STATUS; /**< Status information for pixel engine configuration of vscaler4, offset: 0xB2C */ uint8_t RESERVED_32[16]; __I uint32_t MATRIX832_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB40 */ __I uint32_t MATRIX832_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB44 */ __IO uint32_t MATRIX5_DYNAMIC; /**< Dynamic pixel engine configuration for matrix5, offset: 0xB48 */ __I uint32_t MATRIX5_STATUS; /**< Status information for pixel engine configuration of matrix5, offset: 0xB4C */ uint8_t RESERVED_33[16]; __I uint32_t HSCALER864_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB60 */ __I uint32_t HSCALER864_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB64 */ __IO uint32_t HSCALER5_DYNAMIC; /**< Dynamic pixel engine configuration for hscaler5, offset: 0xB68 */ __I uint32_t HSCALER5_STATUS; /**< Status information for pixel engine configuration of hscaler5, offset: 0xB6C */ uint8_t RESERVED_34[16]; __I uint32_t VSCALER896_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB80 */ __I uint32_t VSCALER896_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB84 */ __IO uint32_t VSCALER5_DYNAMIC; /**< Dynamic pixel engine configuration for vscaler5, offset: 0xB88 */ __I uint32_t VSCALER5_STATUS; /**< Status information for pixel engine configuration of vscaler5, offset: 0xB8C */ uint8_t RESERVED_35[16]; __I uint32_t LAYERBLEND928_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xBA0 */ __I uint32_t LAYERBLEND928_LOCKSTATUS; /**< Protection status of this address block., offset: 0xBA4 */ __IO uint32_t LAYERBLEND0_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend0, offset: 0xBA8 */ __I uint32_t LAYERBLEND0_STATUS; /**< Status information for pixel engine configuration of layerblend0, offset: 0xBAC */ uint8_t RESERVED_36[16]; __I uint32_t LAYERBLEND960_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xBC0 */ __I uint32_t LAYERBLEND960_LOCKSTATUS; /**< Protection status of this address block., offset: 0xBC4 */ __IO uint32_t LAYERBLEND1_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend1, offset: 0xBC8 */ __I uint32_t LAYERBLEND1_STATUS; /**< Status information for pixel engine configuration of layerblend1, offset: 0xBCC */ uint8_t RESERVED_37[16]; __I uint32_t LAYERBLEND992_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xBE0 */ __I uint32_t LAYERBLEND99_LOCKSTATUS; /**< Protection status of this address block., offset: 0xBE4 */ __IO uint32_t LAYERBLEND2_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend2, offset: 0xBE8 */ __I uint32_t LAYERBLEND2_STATUS; /**< Status information for pixel engine configuration of layerblend2, offset: 0xBEC */ uint8_t RESERVED_38[16]; __I uint32_t LAYERBLEND1024_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xC00 */ __I uint32_t LAYERBLEND1024_LOCKSTATUS; /**< Protection status of this address block., offset: 0xC04 */ __IO uint32_t LAYERBLEND3_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend3, offset: 0xC08 */ __I uint32_t LAYERBLEND3_STATUS; /**< Status information for pixel engine configuration of layerblend3, offset: 0xC0C */ uint8_t RESERVED_39[1008]; __I uint32_t FETCHDECODE_LOCKUNLOCK_1; /**< Register to change the protection status of this address block., offset: 0x1000 */ __I uint32_t FETCHDECODE_LOCKSTATUS_1; /**< Protection status of this address block., offset: 0x1004 */ __IO uint32_t FETCHDECODE_STATICCONTRO_1L; /**< Common static control options., offset: 0x1008 */ __IO uint32_t FETCHDECODE_BURSTBUFFERMANAGEMENT_1; /**< AXI interface buffer management register, offset: 0x100C */ __IO uint32_t FETCHDECODE_RINGBUFSTARTADDR0_1; /**< Ring buffer setup for layer 0., offset: 0x1010 */ __IO uint32_t FETCHDECODE_RINGBUFWRAPADDR0_1; /**< Ring buffer setup for layer 0., offset: 0x1014 */ __IO uint32_t FETCHDECODE_FRAMEPROPERTIES0_1; /**< Frame property setup for layer 0., offset: 0x1018 */ __IO uint32_t FETCHDECODE_BASEADDRESS0_1; /**< Source buffer base address of layer 0., offset: 0x101C */ __IO uint32_t FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1; /**< Source buffer attributes for layer 0., offset: 0x1020 */ __IO uint32_t FETCHDECODE_SOURCEBUFFERDIMENSION0_1; /**< Source buffer dimension of layer 0., offset: 0x1024 */ __IO uint32_t FETCHDECODE_COLORCOMPONENTBITS0_1; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x1028 */ __IO uint32_t FETCHDECODE_COLORCOMPONENTSHIFT0_1; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x102C */ __IO uint32_t FETCHDECODE_LAYEROFFSET0_1; /**< Position of layer 0 within the destination frame., offset: 0x1030 */ __IO uint32_t FETCHDECODE_CLIPWINDOWOFFSET0_1; /**< Clip window position for layer 0., offset: 0x1034 */ __IO uint32_t FETCHDECODE_CLIPWINDOWDIMENSIONS0_1; /**< Clip window size for layer 0., offset: 0x1038 */ __IO uint32_t FETCHDECODE_CONSTANTCOLOR0_1; /**< Constant color for layer 0., offset: 0x103C */ __IO uint32_t FETCHDECODE_LAYERPROPERTY0_1; /**< Common properties of layer 0., offset: 0x1040 */ __IO uint32_t FETCHDECODE_FRAMEDIMENSIONS_1; /**< Output frame dimension., offset: 0x1044 */ __IO uint32_t FETCHDECODE_FRAMERESAMPLING_1; /**< Resampling options for output frame., offset: 0x1048 */ __IO uint32_t FETCHDECODE_DECODECONTROL_1; /**< Control options for RLAD decompression., offset: 0x104C */ __IO uint32_t FETCHDECODE_SOURCEBUFFERLENGTH_1; /**< Source buffer length for compressed data., offset: 0x1050 */ __IO uint32_t FETCHDECODE_CONTROL_1; /**< Shared common control settings for all layers., offset: 0x1054 */ __O uint32_t FETCHDECODE_CONTROLTRIGGER_1; /**< Shadow load trigger., offset: 0x1058 */ __O uint32_t FETCHDECODE_START_1; /**< Frame start trigger., offset: 0x105C */ __I uint32_t FETCHDECODE_FETCHTYPE_1; /**< Fetch unit type., offset: 0x1060 */ __IO uint32_t FETCHDECODE_DECODERSTATUS_1; /**< Status information of the RLAD decoder., offset: 0x1064 */ __I uint32_t FETCHDECODE_READADDRESS0_1; /**< Ring buffer synchronization for layer 0., offset: 0x1068 */ __I uint32_t FETCHDECODE_BURSTBUFFERPROPERTIES_1; /**< Burst buffer properties., offset: 0x106C */ __IO uint32_t FETCHDECODE_STATUS_1; /**< Status informations., offset: 0x1070 */ __I uint32_t FETCHDECODE_HIDDENSTATUS_1; /**< Hidden status informations., offset: 0x1074 */ uint8_t RESERVED_40[904]; __IO uint32_t COLORPALETTE_1; /**< Color palette look up table., offset: 0x1400 */ uint8_t RESERVED_41[1020]; __I uint32_t FETCHWARP9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1800 */ __I uint32_t FETCHWARP9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1804 */ __IO uint32_t FETCHWARP9_STATICCONTROL; /**< Common static control options., offset: 0x1808 */ __IO uint32_t FETCHWARP9_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x180C */ __IO uint32_t FETCHWARP9_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x1810 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x1814 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x1818 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x181C */ __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x1820 */ __IO uint32_t FETCHWARP9_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x1824 */ __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x1828 */ __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x182C */ __IO uint32_t FETCHWARP9_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x1830 */ __IO uint32_t FETCHWARP9_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x1834 */ __IO uint32_t FETCHWARP9_BASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x1838 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0x183C */ __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1,, offset: 0x1840 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS1; /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0x1844 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT1; /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0x1848 */ __IO uint32_t FETCHWARP9_LAYEROFFSET1; /**< Position of layer 1 within the destination frame., offset: 0x184C */ __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET1; /**< Clip window position for layer 1., offset: 0x1850 */ __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS1; /**< Clip window size for layer 1., offset: 0x1854 */ __IO uint32_t FETCHWARP9_CONSTANTCOLOR1; /**< Constant color for layer 1., offset: 0x1858 */ __IO uint32_t FETCHWARP9_LAYERPROPERTY1; /**< Common properties of layer 1., offset: 0x185C */ __IO uint32_t FETCHWARP9_BASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x1860 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0x1864 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION2; /**< Source buffer dimension of layer 2., offset: 0x1868 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS2; /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0x186C */ __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT2; /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0x1870 */ __IO uint32_t FETCHWARP9_LAYEROFFSET2; /**< Position of layer 2 within the destination frame., offset: 0x1874 */ __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET2; /**< Clip window position for layer 2., offset: 0x1878 */ __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS2; /**< Clip window size for layer 2., offset: 0x187C */ __IO uint32_t FETCHWARP9_CONSTANTCOLOR2; /**< Constant color for layer 2., offset: 0x1880 */ __IO uint32_t FETCHWARP9_LAYERPROPERTY2; /**< Common properties of layer 2., offset: 0x1884 */ __IO uint32_t FETCHWARP9_BASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x1888 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0x188C */ __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION3; /**< Source buffer dimension of layer 3., offset: 0x1890 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS3; /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0x1894 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT3; /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0x1898 */ __IO uint32_t FETCHWARP9_LAYEROFFSET3; /**< Position of layer 3 within the destination frame., offset: 0x189C */ __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET3; /**< Clip window position for layer 3., offset: 0x18A0 */ __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS3; /**< Clip window size for layer 3., offset: 0x18A4 */ __IO uint32_t FETCHWARP9_CONSTANTCOLOR3; /**< Constant color for layer 3., offset: 0x18A8 */ __IO uint32_t FETCHWARP9_LAYERPROPERTY3; /**< Common properties of layer 3., offset: 0x18AC */ __IO uint32_t FETCHWARP9_BASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x18B0 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0x18B4 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION4; /**< Source buffer dimension of layer 4., offset: 0x18B8 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS4; /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0x18BC */ __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT4; /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0x18C0 */ __IO uint32_t FETCHWARP9_LAYEROFFSET4; /**< Position of layer 4 within the destination frame., offset: 0x18C4 */ __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET4; /**< Clip window position for layer 4., offset: 0x18C8 */ __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS4; /**< Clip window size for layer 4., offset: 0x18CC */ __IO uint32_t FETCHWARP9_CONSTANTCOLOR4; /**< Constant color for layer 4., offset: 0x18D0 */ __IO uint32_t FETCHWARP9_LAYERPROPERTY4; /**< Common properties of layer 4., offset: 0x18D4 */ __IO uint32_t FETCHWARP9_BASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x18D8 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0x18DC */ __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION5; /**< Source buffer dimension of layer 5., offset: 0x18E0 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS5; /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0x18E4 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT5; /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0x18E8 */ __IO uint32_t FETCHWARP9_LAYEROFFSET5; /**< Position of layer 5 within the destination frame., offset: 0x18EC */ __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET5; /**< Clip window position for layer 5., offset: 0x18F0 */ __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS5; /**< Clip window size for layer 5., offset: 0x18F4 */ __IO uint32_t FETCHWARP9_CONSTANTCOLOR5; /**< Constant color for layer 5., offset: 0x18F8 */ __IO uint32_t FETCHWARP9_LAYERPROPERTY5; /**< Common properties of layer 5., offset: 0x18FC */ __IO uint32_t FETCHWARP9_BASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x1900 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0x1904 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION6; /**< Source buffer dimension of layer 6., offset: 0x1908 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS6; /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0x190C */ __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT6; /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0x1910 */ __IO uint32_t FETCHWARP9_LAYEROFFSET6; /**< Position of layer 1 within the destination frame., offset: 0x1914 */ __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET6; /**< Clip window position for layer 6., offset: 0x1918 */ __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS6; /**< Clip window size for layer 6., offset: 0x191C */ __IO uint32_t FETCHWARP9_CONSTANTCOLOR6; /**< Constant color for layer 6., offset: 0x1920 */ __IO uint32_t FETCHWARP9_LAYERPROPERTY6; /**< Common properties of layer 6., offset: 0x1924 */ __IO uint32_t FETCHWARP9_BASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x1928 */ __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES7; /**< Source buffer stride for layer 7., offset: 0x192C */ __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION7; /**< Source buffer dimension of layer 7., offset: 0x1930 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS7; /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0x1934 */ __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT7; /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0x1938 */ __IO uint32_t FETCHWARP9_LAYEROFFSET7; /**< Position of layer 7 within the destination frame., offset: 0x193C */ __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET7; /**< Clip window position for layer 7., offset: 0x1940 */ __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS7; /**< Clip window size for layer 7., offset: 0x1944 */ __IO uint32_t FETCHWARP9_CONSTANTCOLOR7; /**< Constant color for layer 7., offset: 0x1948 */ __IO uint32_t FETCHWARP9_LAYERPROPERTY7; /**< Common properties of layer 7., offset: 0x194C */ __IO uint32_t FETCHWARP9_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x1950 */ __IO uint32_t FETCHWARP9_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x1954 */ __IO uint32_t FETCHWARP9_WARPCONTROL; /**< Warping control options., offset: 0x1958 */ __IO uint32_t FETCHWARP9_ARBSTARTX; /**< Start value X for arbitrary warping., offset: 0x195C */ __IO uint32_t FETCHWARP9_ARBSTARTY; /**< Start value Y for arbitrary warping., offset: 0x1960 */ __IO uint32_t FETCHWARP9_ARBDELTA; /**< Start values for delta incrementation of arbitrary warping., offset: 0x1964 */ __IO uint32_t FETCHWARP9_FIRPOSITIONS; /**< FIR sequence control register., offset: 0x1968 */ __IO uint32_t FETCHWARP9_FIRCOEFFICIENTS; /**< FIR coefficients register., offset: 0x196C */ __IO uint32_t FETCHWARP9_CONTROL; /**< Shared common control settings for all layers., offset: 0x1970 */ __I uint32_t FETCHWARP9_TRIGGERENABLE; /**< Shadow load enable flags for all layers., offset: 0x1974 */ __O uint32_t FETCHWARP9_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x1978 */ __O uint32_t FETCHWARP9_START; /**< Frame start trigger., offset: 0x197C */ __I uint32_t FETCHWARP9_FETCHTYPE; /**< Fetch unit type., offset: 0x1980 */ __I uint32_t FETCHWARP9_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x1984 */ __IO uint32_t FETCHWARP9_STATUS; /**< Status informations., offset: 0x1988 */ __I uint32_t FETCHWARP9_HIDDENSTATUS; /**< Hidden status informations., offset: 0x198C */ uint8_t RESERVED_42[624]; __I uint32_t FETCHECO9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1C00 */ __I uint32_t FETCHECO9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1C04 */ __IO uint32_t FETCHECO9_STATICCONTROL; /**< Common static control options., offset: 0x1C08 */ __IO uint32_t FETCHECO9_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x1C0C */ __IO uint32_t FETCHECO9_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x1C10 */ __IO uint32_t FETCHECO9_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x1C14 */ __IO uint32_t FETCHECO9_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x1C18 */ __IO uint32_t FETCHECO9_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x1C1C */ __IO uint32_t FETCHECO9_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x1C20 */ __IO uint32_t FETCHECO9_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x1C24 */ __IO uint32_t FETCHECO9_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x1C28 */ __IO uint32_t FETCHECO9_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x1C2C */ __IO uint32_t FETCHECO9_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x1C30 */ __IO uint32_t FETCHECO9_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x1C34 */ __IO uint32_t FETCHECO9_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x1C38 */ __IO uint32_t FETCHECO9_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x1C3C */ __IO uint32_t FETCHECO9_CONTROL; /**< Shared common control settings for all layers., offset: 0x1C40 */ __O uint32_t FETCHECO9_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x1C44 */ __O uint32_t FETCHECO9_START; /**< Frame start trigger., offset: 0x1C48 */ __I uint32_t FETCHECO9_FETCHTYPE; /**< Fetch unit type., offset: 0x1C4C */ __I uint32_t FETCHECO9_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x1C50 */ __I uint32_t FETCHECO9_HIDDENSTATUS; /**< Hidden status informations., offset: 0x1C54 */ uint8_t RESERVED_43[936]; __I uint32_t ROP9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2000 */ __I uint32_t ROP9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x2004 */ __IO uint32_t ROP9_STATICCONTROL; /**< Raster Operation static control register, offset: 0x2008 */ __IO uint32_t ROP9_CONTROL; /**< Raster Operation control register, offset: 0x200C */ __IO uint32_t ROP9_RASTEROPERATIONINDICES; /**< ROP operation indices, offset: 0x2010 */ __I uint32_t ROP9_PRIMCONTROLWORD; /**< Value of last received primary control word, offset: 0x2014 */ __I uint32_t ROP9_SECCONTROLWORD; /**< Value of last received secondary control word, offset: 0x2018 */ __I uint32_t ROP9_TERTCONTROLWORD; /**< Value of last received tertiary control word, offset: 0x201C */ uint8_t RESERVED_44[992]; __I uint32_t CLUT9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2400 */ __I uint32_t CLUT9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x2404 */ __IO uint32_t CLUT9_STATICCONTROL; /**< CLUT static control register, offset: 0x2408 */ __IO uint32_t CLUT9_UNSHADOWEDCONTROL; /**< CLUT unshadowed control register, offset: 0x240C */ __IO uint32_t CLUT9_CONTROL; /**< CLUT control register, offset: 0x2410 */ __IO uint32_t CLUT9_STATUS; /**< CLUT status register, offset: 0x2414 */ __I uint32_t CLUT9_LASTCONTROLWORD; /**< Value of last received control word, for debugging, offset: 0x2418 */ uint8_t RESERVED_45[996]; __IO uint32_t CLUT9_LUT; /**< Look Up Table, offset: 0x2800 */ uint8_t RESERVED_46[1020]; __I uint32_t MATRIX9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2C00 */ __I uint32_t MATRIX9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x2C04 */ __IO uint32_t MATRIX9_STATICCONTROL; /**< Color Matrix static control register, offset: 0x2C08 */ __IO uint32_t MATRIX9_CONTROL; /**< Color Matrix control register, offset: 0x2C0C */ __IO uint32_t MATRIX9_RED0; /**< Matrix values for calculation of the red output value., offset: 0x2C10 */ __IO uint32_t MATRIX9_RED1; /**< Matrix values for calculation of the red output value., offset: 0x2C14 */ __IO uint32_t MATRIX9_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0x2C18 */ __IO uint32_t MATRIX9_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0x2C1C */ __IO uint32_t MATRIX9_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0x2C20 */ __IO uint32_t MATRIX9_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0x2C24 */ __IO uint32_t MATRIX9_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0x2C28 */ __IO uint32_t MATRIX9_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0x2C2C */ __IO uint32_t MATRIX9_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0x2C30 */ __IO uint32_t MATRIX9_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0x2C34 */ __I uint32_t MATRIX9_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0x2C38 */ uint8_t RESERVED_47[964]; __I uint32_t HSCALER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3000 */ __I uint32_t HSCALER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x3004 */ __IO uint32_t HSCALER9_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x3008 */ __IO uint32_t HSCALER9_SETUP1; /**< Phase interpolator setup., offset: 0x300C */ __IO uint32_t HSCALER9_SETUP2; /**< Phase interpolator setup., offset: 0x3010 */ __IO uint32_t HSCALER9_CONTROL; /**< Scaler operation control., offset: 0x3014 */ uint8_t RESERVED_48[1000]; __I uint32_t VSCALER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3400 */ __I uint32_t VSCALER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x3404 */ __IO uint32_t VSCALER9_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x3408 */ __IO uint32_t VSCALER9_SETUP1; /**< Phase interpolator setup., offset: 0x340C */ __IO uint32_t VSCALER9_SETUP2; /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0x3410 */ __IO uint32_t VSCALER9_SETUP3; /**< Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0., offset: 0x3414 */ __IO uint32_t VSCALER9_SETUP4; /**< Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1., offset: 0x3418 */ __IO uint32_t VSCALER9_SETUP5; /**< Phase interpolator setup, selected if input and output field polarity is 1., offset: 0x341C */ __IO uint32_t VSCALER9_CONTROL; /**< Scaler operation control., offset: 0x3420 */ uint8_t RESERVED_49[988]; __I uint32_t FILTER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3800 */ __I uint32_t FILTER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x3804 */ __IO uint32_t FILTER9_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x3808 */ __IO uint32_t FILTER9_CONTROL; /**< Filter operation main control., offset: 0x380C */ __IO uint32_t FILTER9_FIR_CONTROL; /**< FIR filter operation control., offset: 0x3810 */ __IO uint32_t FILTER9_COEFFICIENTS0; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3814 */ __IO uint32_t FILTER9_COEFFICIENTS1; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3818 */ __IO uint32_t FILTER9_COEFFICIENTS2; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x381C */ __IO uint32_t FILTER9_COEFFICIENTS3; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3820 */ __IO uint32_t FILTER9_COEFFICIENTS4; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3824 */ __IO uint32_t FILTER9_COEFFICIENTS5; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3828 */ __IO uint32_t FILTER9_COEFFICIENTS6; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x382C */ uint8_t RESERVED_50[976]; __I uint32_t BLITBLEND9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3C00 */ __I uint32_t BLITBLEND9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x3C04 */ __IO uint32_t BLITBLEND9_STATICCONTROL; /**< BlitBlend static control register, offset: 0x3C08 */ __IO uint32_t BLITBLEND9_CONTROL; /**< BlitBlend control register, offset: 0x3C0C */ __IO uint32_t BLITBLEND9_NEUTRALBORDER; /**< Neutral border setup register, offset: 0x3C10 */ __IO uint32_t BLITBLEND9_CONSTANTCOLOR; /**< Constant color register, offset: 0x3C14 */ __IO uint32_t BLITBLEND9_COLORREDBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x3C18 */ __IO uint32_t BLITBLEND9_COLORGREENBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x3C1C */ __IO uint32_t BLITBLEND9_COLORBLUEBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x3C20 */ __IO uint32_t BLITBLEND9_ALPHABLENDFUNCTION; /**< Open GL alpha blending factors, offset: 0x3C24 */ __IO uint32_t BLITBLEND9_BLENDMODE1; /**< Open GL and Open VG blending modes for colors red and green, offset: 0x3C28 */ __IO uint32_t BLITBLEND9_BLENDMODE2; /**< Open GL and Open VG blending modes for color blue and alpha, offset: 0x3C2C */ __IO uint32_t BLITBLEND9_DIRECTSETUP; /**< Direct Control of the BlitBlend Datapath multiplexers, do not change, offset: 0x3C30 */ __I uint32_t BLITBLEND9_PRIMCONTROLWORD; /**< Value of last received primary control word, offset: 0x3C34 */ __I uint32_t BLITBLEND9_SECCONTROLWORD; /**< Value of last received secondary control word, offset: 0x3C38 */ uint8_t RESERVED_51[964]; __I uint32_t STORE9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x4000 */ __I uint32_t STORE9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x4004 */ __IO uint32_t STORE9_STATICCONTROL; /**< Store unit static control register., offset: 0x4008 */ __IO uint32_t STORE9_BURSTBUFFERMANAGEMENT; /**< Burst Buffer setup register., offset: 0x400C */ __IO uint32_t STORE9_RINGBUFSTARTADDR; /**< Ring buffer setup for destination., offset: 0x4010 */ __IO uint32_t STORE9_RINGBUFWRAPADDR; /**< Ring buffer setup for destination., offset: 0x4014 */ __IO uint32_t STORE9_BASEADDRESS; /**< Destination buffer base address., offset: 0x4018 */ __IO uint32_t STORE9_DESTINATIONBUFFERATTRIBUTES; /**< Destination buffer attributes., offset: 0x401C */ __IO uint32_t STORE9_DESTINATIONBUFFERDIMENSION; /**< Destination buffer dimension., offset: 0x4020 */ __IO uint32_t STORE9_FRAMEOFFSET; /**< Offset between destination frame and buffer., offset: 0x4024 */ __IO uint32_t STORE9_COLORCOMPONENTBITS; /**< Color component size of destination buffer, offset: 0x4028 */ __IO uint32_t STORE9_COLORCOMPONENTSHIFT; /**< Color component offset of destination buffer., offset: 0x402C */ __IO uint32_t STORE9_CONTROL; /**< Store unit dynamic control register, offset: 0x4030 */ __IO uint32_t STORE9_ENCODECONTROL; /**< Control options for RLAD compression., offset: 0x4034 */ __IO uint32_t STORE9_DESTINATIONBUFFERLENGTH; /**< Destination buffer length for compressed data., offset: 0x4038 */ __O uint32_t STORE9_START; /**< Store unit start register, offset: 0x403C */ __IO uint32_t STORE9_ENCODERSTATUS; /**< Status information of the RLAD encoder., offset: 0x4040 */ __I uint32_t STORE9_WRITEADDRESS; /**< Ring buffer synchronization., offset: 0x4044 */ __I uint32_t STORE9_FRAMEPROPERTIES; /**< Ring buffer synchronization., offset: 0x4048 */ __I uint32_t STORE9_BURSTBUFFERPROPERTIES; /**< Burst Buffer Property register, offset: 0x404C */ __I uint32_t STORE9_LASTCONTROLWORD; /**< Shows the last control word received, offset: 0x4050 */ __I uint32_t STORE9_PERFCOUNTER; /**< Performance counter result, offset: 0x4054 */ __IO uint32_t STORE9_STATUS; /**< Shows status information, offset: 0x4058 */ uint8_t RESERVED_52[932]; __I uint32_t CONSTFRAME0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x4400 */ __I uint32_t CONSTFRAME0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x4404 */ __IO uint32_t CONSTFRAME0_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x4408 */ __IO uint32_t CONSTFRAME0_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x440C */ __IO uint32_t CONSTFRAME0_CONSTANTCOLOR; /**< Color of output frame., offset: 0x4410 */ __O uint32_t CONSTFRAME0_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x4414 */ __O uint32_t CONSTFRAME0_START; /**< ConstFrame unit start register, offset: 0x4418 */ __I uint32_t CONSTFRAME0_STATUS; /**< Shows status information, offset: 0x441C */ uint8_t RESERVED_53[992]; __I uint32_t EXTDST0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x4800 */ __I uint32_t EXTDST0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x4804 */ __IO uint32_t EXTDST0_STATICCONTROL; /**< External Destination static control register, offset: 0x4808 */ __IO uint32_t EXTDST0_CONTROL; /**< External Destination shadowed control register, offset: 0x480C */ __O uint32_t EXTDST0_SOFTWAREKICK; /**< External Destination software kick, offset: 0x4810 */ __IO uint32_t EXTDST0_STATUS; /**< External Destination Unit current status, offset: 0x4814 */ __I uint32_t EXTDST0_CONTROLWORD; /**< Value of last received control word, offset: 0x4818 */ __I uint32_t EXTDST0_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x481C */ __I uint32_t EXTDST0_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x4820 */ __I uint32_t EXTDST0_PERFCOUNTER; /**< Performance counter result, offset: 0x4824 */ uint8_t RESERVED_54[984]; __I uint32_t CONSTFRAME4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x4C00 */ __I uint32_t CONSTFRAME4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x4C04 */ __IO uint32_t CONSTFRAME4_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x4C08 */ __IO uint32_t CONSTFRAME4_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x4C0C */ __IO uint32_t CONSTFRAME4_CONSTANTCOLOR; /**< Color of output frame., offset: 0x4C10 */ __O uint32_t CONSTFRAME4_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x4C14 */ __O uint32_t CONSTFRAME4_START; /**< ConstFrame unit start register, offset: 0x4C18 */ __I uint32_t CONSTFRAME4_STATUS; /**< Shows status information, offset: 0x4C1C */ uint8_t RESERVED_55[992]; __I uint32_t EXTDST4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x5000 */ __I uint32_t EXTDST4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x5004 */ __IO uint32_t EXTDST4_STATICCONTROL; /**< External Destination static control register, offset: 0x5008 */ __IO uint32_t EXTDST4_CONTROL; /**< External Destination shadowed control register, offset: 0x500C */ __O uint32_t EXTDST4_SOFTWAREKICK; /**< External Destination software kick, offset: 0x5010 */ __IO uint32_t EXTDST4_STATUS; /**< External Destination Unit current status, offset: 0x5014 */ __I uint32_t EXTDST4_CONTROLWORD; /**< Value of last received control word, offset: 0x5018 */ __I uint32_t EXTDST4_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x501C */ __I uint32_t EXTDST4_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x5020 */ __I uint32_t EXTDST4_PERFCOUNTER; /**< Performance counter result, offset: 0x5024 */ uint8_t RESERVED_56[984]; __I uint32_t CONSTFRAME1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x5400 */ __I uint32_t CONSTFRAME1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x5404 */ __IO uint32_t CONSTFRAME1_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x5408 */ __IO uint32_t CONSTFRAME1_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x540C */ __IO uint32_t CONSTFRAME1_CONSTANTCOLOR; /**< Color of output frame., offset: 0x5410 */ __O uint32_t CONSTFRAME1_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x5414 */ __O uint32_t CONSTFRAME1_START; /**< ConstFrame unit start register, offset: 0x5418 */ __I uint32_t CONSTFRAME1_STATUS; /**< Shows status information, offset: 0x541C */ uint8_t RESERVED_57[992]; __I uint32_t EXTDST1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x5800 */ __I uint32_t EXTDST1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x5804 */ __IO uint32_t EXTDST1_STATICCONTROL; /**< External Destination static control register, offset: 0x5808 */ __IO uint32_t EXTDST1_CONTROL; /**< External Destination shadowed control register, offset: 0x580C */ __O uint32_t EXTDST1_SOFTWAREKICK; /**< External Destination software kick, offset: 0x5810 */ __IO uint32_t EXTDST1_STATUS; /**< External Destination Unit current status, offset: 0x5814 */ __I uint32_t EXTDST1_CONTROLWORD; /**< Value of last received control word, offset: 0x5818 */ __I uint32_t EXTDST1_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x581C */ __I uint32_t EXTDST1_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x5820 */ __I uint32_t EXTDST1_PERFCOUNTER; /**< Performance counter result, offset: 0x5824 */ uint8_t RESERVED_58[984]; __I uint32_t CONSTFRAME5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x5C00 */ __I uint32_t CONSTFRAME5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x5C04 */ __IO uint32_t CONSTFRAME5_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x5C08 */ __IO uint32_t CONSTFRAME5_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x5C0C */ __IO uint32_t CONSTFRAME5_CONSTANTCOLOR; /**< Color of output frame., offset: 0x5C10 */ __O uint32_t CONSTFRAME5_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x5C14 */ __O uint32_t CONSTFRAME5_START; /**< ConstFrame unit start register, offset: 0x5C18 */ __I uint32_t CONSTFRAME5_STATUS; /**< Shows status information, offset: 0x5C1C */ uint8_t RESERVED_59[992]; __I uint32_t EXTDST5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x6000 */ __I uint32_t EXTDST5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x6004 */ __IO uint32_t EXTDST5_STATICCONTROL; /**< External Destination static control register, offset: 0x6008 */ __IO uint32_t EXTDST5_CONTROL; /**< External Destination shadowed control register, offset: 0x600C */ __O uint32_t EXTDST5_SOFTWAREKICK; /**< External Destination software kick, offset: 0x6010 */ __IO uint32_t EXTDST5_STATUS; /**< External Destination Unit current status, offset: 0x6014 */ __I uint32_t EXTDST5_CONTROLWORD; /**< Value of last received control word, offset: 0x6018 */ __I uint32_t EXTDST5_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x601C */ __I uint32_t EXTDST5_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x6020 */ __I uint32_t EXTDST5_PERFCOUNTER; /**< Performance counter result, offset: 0x6024 */ uint8_t RESERVED_60[984]; __I uint32_t FETCHWARP2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x6400 */ __I uint32_t FETCHWARP2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x6404 */ __IO uint32_t FETCHWARP2_STATICCONTROL; /**< Common static control options., offset: 0x6408 */ __IO uint32_t FETCHWARP2_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x640C */ __IO uint32_t FETCHWARP2_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x6410 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x6414 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x6418 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x641C */ __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x6420 */ __IO uint32_t FETCHWARP2_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x6424 */ __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x6428 */ __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x642C */ __IO uint32_t FETCHWARP2_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x6430 */ __IO uint32_t FETCHWARP2_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x6434 */ __IO uint32_t FETCHWARP2_BASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x6438 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0x643C */ __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1,, offset: 0x6440 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS1; /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0x6444 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT1; /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0x6448 */ __IO uint32_t FETCHWARP2_LAYEROFFSET1; /**< Position of layer 1 within the destination frame., offset: 0x644C */ __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET1; /**< Clip window position for layer 1., offset: 0x6450 */ __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS1; /**< Clip window size for layer 1., offset: 0x6454 */ __IO uint32_t FETCHWARP2_CONSTANTCOLOR1; /**< Constant color for layer 1., offset: 0x6458 */ __IO uint32_t FETCHWARP2_LAYERPROPERTY1; /**< Common properties of layer 1., offset: 0x645C */ __IO uint32_t FETCHWARP2_BASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x6460 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0x6464 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION2; /**< Source buffer dimension of layer 2., offset: 0x6468 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS2; /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0x646C */ __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT2; /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0x6470 */ __IO uint32_t FETCHWARP2_LAYEROFFSET2; /**< Position of layer 2 within the destination frame., offset: 0x6474 */ __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET2; /**< Clip window position for layer 2., offset: 0x6478 */ __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS2; /**< Clip window size for layer 2., offset: 0x647C */ __IO uint32_t FETCHWARP2_CONSTANTCOLOR2; /**< Constant color for layer 2., offset: 0x6480 */ __IO uint32_t FETCHWARP2_LAYERPROPERTY2; /**< Common properties of layer 2., offset: 0x6484 */ __IO uint32_t FETCHWARP2_BASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x6488 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0x648C */ __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION3; /**< Source buffer dimension of layer 3., offset: 0x6490 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS3; /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0x6494 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT3; /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0x6498 */ __IO uint32_t FETCHWARP2_LAYEROFFSET3; /**< Position of layer 3 within the destination frame., offset: 0x649C */ __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET3; /**< Clip window position for layer 3., offset: 0x64A0 */ __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS3; /**< Clip window size for layer 3., offset: 0x64A4 */ __IO uint32_t FETCHWARP2_CONSTANTCOLOR3; /**< Constant color for layer 3., offset: 0x64A8 */ __IO uint32_t FETCHWARP2_LAYERPROPERTY3; /**< Common properties of layer 3., offset: 0x64AC */ __IO uint32_t FETCHWARP2_BASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x64B0 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0x64B4 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION4; /**< Source buffer dimension of layer 4., offset: 0x64B8 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS4; /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0x64BC */ __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT4; /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0x64C0 */ __IO uint32_t FETCHWARP2_LAYEROFFSET4; /**< Position of layer 4 within the destination frame., offset: 0x64C4 */ __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET4; /**< Clip window position for layer 4., offset: 0x64C8 */ __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS4; /**< Clip window size for layer 4., offset: 0x64CC */ __IO uint32_t FETCHWARP2_CONSTANTCOLOR4; /**< Constant color for layer 4., offset: 0x64D0 */ __IO uint32_t FETCHWARP2_LAYERPROPERTY4; /**< Common properties of layer 4., offset: 0x64D4 */ __IO uint32_t FETCHWARP2_BASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x64D8 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0x64DC */ __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION5; /**< Source buffer dimension of layer 5., offset: 0x64E0 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS5; /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0x64E4 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT5; /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0x64E8 */ __IO uint32_t FETCHWARP2_LAYEROFFSET5; /**< Position of layer 5 within the destination frame., offset: 0x64EC */ __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET5; /**< Clip window position for layer 5., offset: 0x64F0 */ __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS5; /**< Clip window size for layer 5., offset: 0x64F4 */ __IO uint32_t FETCHWARP2_CONSTANTCOLOR5; /**< Constant color for layer 5., offset: 0x64F8 */ __IO uint32_t FETCHWARP2_LAYERPROPERTY5; /**< Common properties of layer 5., offset: 0x64FC */ __IO uint32_t FETCHWARP2_BASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x6500 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0x6504 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION6; /**< Source buffer dimension of layer 6., offset: 0x6508 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS6; /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0x650C */ __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT6; /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0x6510 */ __IO uint32_t FETCHWARP2_LAYEROFFSET6; /**< Position of layer 1 within the destination frame., offset: 0x6514 */ __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET6; /**< Clip window position for layer 6., offset: 0x6518 */ __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS6; /**< Clip window size for layer 6., offset: 0x651C */ __IO uint32_t FETCHWARP2_CONSTANTCOLOR6; /**< Constant color for layer 6., offset: 0x6520 */ __IO uint32_t FETCHWARP2_LAYERPROPERTY6; /**< Common properties of layer 6., offset: 0x6524 */ __IO uint32_t FETCHWARP2_BASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x6528 */ __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES7; /**< Source buffer stride for layer 7., offset: 0x652C */ __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION7; /**< Source buffer dimension of layer 7., offset: 0x6530 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS7; /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0x6534 */ __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT7; /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0x6538 */ __IO uint32_t FETCHWARP2_LAYEROFFSET7; /**< Position of layer 7 within the destination frame., offset: 0x653C */ __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET7; /**< Clip window position for layer 7., offset: 0x6540 */ __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS7; /**< Clip window size for layer 7., offset: 0x6544 */ __IO uint32_t FETCHWARP2_CONSTANTCOLOR7; /**< Constant color for layer 7., offset: 0x6548 */ __IO uint32_t FETCHWARP2_LAYERPROPERTY7; /**< Common properties of layer 7., offset: 0x654C */ __IO uint32_t FETCHWARP2_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x6550 */ __IO uint32_t FETCHWARP2_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x6554 */ __IO uint32_t FETCHWARP2_WARPCONTROL; /**< Warping control options., offset: 0x6558 */ __IO uint32_t FETCHWARP2_ARBSTARTX; /**< Start value X for arbitrary warping., offset: 0x655C */ __IO uint32_t FETCHWARP2_ARBSTARTY; /**< Start value Y for arbitrary warping., offset: 0x6560 */ __IO uint32_t FETCHWARP2_ARBDELTA; /**< Start values for delta incrementation of arbitrary warping., offset: 0x6564 */ __IO uint32_t FETCHWARP2_FIRPOSITIONS; /**< FIR sequence control register., offset: 0x6568 */ __IO uint32_t FETCHWARP2_FIRCOEFFICIENTS; /**< FIR coefficients register., offset: 0x656C */ __IO uint32_t FETCHWARP2_CONTROL; /**< Shared common control settings for all layers., offset: 0x6570 */ __I uint32_t FETCHWARP2_TRIGGERENABLE; /**< Shadow load enable flags for all layers., offset: 0x6574 */ __O uint32_t FETCHWARP2_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x6578 */ __O uint32_t FETCHWARP2_START; /**< Frame start trigger., offset: 0x657C */ __I uint32_t FETCHWARP2_FETCHTYPE; /**< Fetch unit type., offset: 0x6580 */ __I uint32_t FETCHWARP2_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x6584 */ __IO uint32_t FETCHWARP2_STATUS; /**< Status informations., offset: 0x6588 */ __I uint32_t FETCHWARP2_HIDDENSTATUS; /**< Hidden status informations., offset: 0x658C */ uint8_t RESERVED_61[624]; __I uint32_t FETCHECO2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x6800 */ __I uint32_t FETCHECO2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x6804 */ __IO uint32_t FETCHECO2_STATICCONTROL; /**< Common static control options., offset: 0x6808 */ __IO uint32_t FETCHECO2_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x680C */ __IO uint32_t FETCHECO2_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x6810 */ __IO uint32_t FETCHECO2_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x6814 */ __IO uint32_t FETCHECO2_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x6818 */ __IO uint32_t FETCHECO2_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x681C */ __IO uint32_t FETCHECO2_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x6820 */ __IO uint32_t FETCHECO2_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x6824 */ __IO uint32_t FETCHECO2_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x6828 */ __IO uint32_t FETCHECO2_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x682C */ __IO uint32_t FETCHECO2_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x6830 */ __IO uint32_t FETCHECO2_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x6834 */ __IO uint32_t FETCHECO2_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x6838 */ __IO uint32_t FETCHECO2_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x683C */ __IO uint32_t FETCHECO2_CONTROL; /**< Shared common control settings for all layers., offset: 0x6840 */ __O uint32_t FETCHECO2_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x6844 */ __O uint32_t FETCHECO2_START; /**< Frame start trigger., offset: 0x6848 */ __I uint32_t FETCHECO2_FETCHTYPE; /**< Fetch unit type., offset: 0x684C */ __I uint32_t FETCHECO2_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x6850 */ __I uint32_t FETCHECO2_HIDDENSTATUS; /**< Hidden status informations., offset: 0x6854 */ uint8_t RESERVED_62[936]; __I uint32_t FETCHDECODE_LOCKUNLOCK_4; /**< Register to change the protection status of this address block., offset: 0x6C00 */ __I uint32_t FETCHDECODE_LOCKSTATUS_4; /**< Protection status of this address block., offset: 0x6C04 */ __IO uint32_t FETCHDECODE_STATICCONTRO_4L; /**< Common static control options., offset: 0x6C08 */ __IO uint32_t FETCHDECODE_BURSTBUFFERMANAGEMENT_4; /**< AXI interface buffer management register, offset: 0x6C0C */ __IO uint32_t FETCHDECODE_RINGBUFSTARTADDR0_4; /**< Ring buffer setup for layer 0., offset: 0x6C10 */ __IO uint32_t FETCHDECODE_RINGBUFWRAPADDR0_4; /**< Ring buffer setup for layer 0., offset: 0x6C14 */ __IO uint32_t FETCHDECODE_FRAMEPROPERTIES0_4; /**< Frame property setup for layer 0., offset: 0x6C18 */ __IO uint32_t FETCHDECODE_BASEADDRESS0_4; /**< Source buffer base address of layer 0., offset: 0x6C1C */ __IO uint32_t FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4; /**< Source buffer attributes for layer 0., offset: 0x6C20 */ __IO uint32_t FETCHDECODE_SOURCEBUFFERDIMENSION0_4; /**< Source buffer dimension of layer 0., offset: 0x6C24 */ __IO uint32_t FETCHDECODE_COLORCOMPONENTBITS0_4; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x6C28 */ __IO uint32_t FETCHDECODE_COLORCOMPONENTSHIFT0_4; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x6C2C */ __IO uint32_t FETCHDECODE_LAYEROFFSET0_4; /**< Position of layer 0 within the destination frame., offset: 0x6C30 */ __IO uint32_t FETCHDECODE_CLIPWINDOWOFFSET0_4; /**< Clip window position for layer 0., offset: 0x6C34 */ __IO uint32_t FETCHDECODE_CLIPWINDOWDIMENSIONS0_4; /**< Clip window size for layer 0., offset: 0x6C38 */ __IO uint32_t FETCHDECODE_CONSTANTCOLOR0_4; /**< Constant color for layer 0., offset: 0x6C3C */ __IO uint32_t FETCHDECODE_LAYERPROPERTY0_4; /**< Common properties of layer 0., offset: 0x6C40 */ __IO uint32_t FETCHDECODE_FRAMEDIMENSIONS_4; /**< Output frame dimension., offset: 0x6C44 */ __IO uint32_t FETCHDECODE_FRAMERESAMPLING_4; /**< Resampling options for output frame., offset: 0x6C48 */ __IO uint32_t FETCHDECODE_DECODECONTROL_4; /**< Control options for RLAD decompression., offset: 0x6C4C */ __IO uint32_t FETCHDECODE_SOURCEBUFFERLENGTH_4; /**< Source buffer length for compressed data., offset: 0x6C50 */ __IO uint32_t FETCHDECODE_CONTROL_4; /**< Shared common control settings for all layers., offset: 0x6C54 */ __O uint32_t FETCHDECODE_CONTROLTRIGGER_4; /**< Shadow load trigger., offset: 0x6C58 */ __O uint32_t FETCHDECODE_START_4; /**< Frame start trigger., offset: 0x6C5C */ __I uint32_t FETCHDECODE_FETCHTYPE_4; /**< Fetch unit type., offset: 0x6C60 */ __IO uint32_t FETCHDECODE_DECODERSTATUS_4; /**< Status information of the RLAD decoder., offset: 0x6C64 */ __I uint32_t FETCHDECODE_READADDRESS0_4; /**< Ring buffer synchronization for layer 0., offset: 0x6C68 */ __I uint32_t FETCHDECODE_BURSTBUFFERPROPERTIES_4; /**< Burst buffer properties., offset: 0x6C6C */ __IO uint32_t FETCHDECODE_STATUS_4; /**< Status informations., offset: 0x6C70 */ __I uint32_t FETCHDECODE_HIDDENSTATUS_4; /**< Hidden status informations., offset: 0x6C74 */ uint8_t RESERVED_63[904]; __IO uint32_t COLORPALETTE_4; /**< Color palette look up table., offset: 0x7000 */ uint8_t RESERVED_64[1020]; __I uint32_t FETCHECO0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x7400 */ __I uint32_t FETCHECO0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x7404 */ __IO uint32_t FETCHECO0_STATICCONTROL; /**< Common static control options., offset: 0x7408 */ __IO uint32_t FETCHECO0_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x740C */ __IO uint32_t FETCHECO0_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x7410 */ __IO uint32_t FETCHECO0_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x7414 */ __IO uint32_t FETCHECO0_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x7418 */ __IO uint32_t FETCHECO0_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x741C */ __IO uint32_t FETCHECO0_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x7420 */ __IO uint32_t FETCHECO0_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x7424 */ __IO uint32_t FETCHECO0_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x7428 */ __IO uint32_t FETCHECO0_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x742C */ __IO uint32_t FETCHECO0_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x7430 */ __IO uint32_t FETCHECO0_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x7434 */ __IO uint32_t FETCHECO0_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x7438 */ __IO uint32_t FETCHECO0_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x743C */ __IO uint32_t FETCHECO0_CONTROL; /**< Shared common control settings for all layers., offset: 0x7440 */ __O uint32_t FETCHECO0_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x7444 */ __O uint32_t FETCHECO0_START; /**< Frame start trigger., offset: 0x7448 */ __I uint32_t FETCHECO0_FETCHTYPE; /**< Fetch unit type., offset: 0x744C */ __I uint32_t FETCHECO0_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x7450 */ __I uint32_t FETCHECO0_HIDDENSTATUS; /**< Hidden status informations., offset: 0x7454 */ uint8_t RESERVED_65[936]; __I uint32_t FETCHDECODE_LOCKUNLOCK_7; /**< Register to change the protection status of this address block., offset: 0x7800 */ __I uint32_t FETCHDECODE_LOCKSTATUS_7; /**< Protection status of this address block., offset: 0x7804 */ __IO uint32_t FETCHDECODE_STATICCONTRO_7L; /**< Common static control options., offset: 0x7808 */ __IO uint32_t FETCHDECODE_BURSTBUFFERMANAGEMENT_7; /**< AXI interface buffer management register, offset: 0x780C */ __IO uint32_t FETCHDECODE_RINGBUFSTARTADDR0_7; /**< Ring buffer setup for layer 0., offset: 0x7810 */ __IO uint32_t FETCHDECODE_RINGBUFWRAPADDR0_7; /**< Ring buffer setup for layer 0., offset: 0x7814 */ __IO uint32_t FETCHDECODE_FRAMEPROPERTIES0_7; /**< Frame property setup for layer 0., offset: 0x7818 */ __IO uint32_t FETCHDECODE_BASEADDRESS0_7; /**< Source buffer base address of layer 0., offset: 0x781C */ __IO uint32_t FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7; /**< Source buffer attributes for layer 0., offset: 0x7820 */ __IO uint32_t FETCHDECODE_SOURCEBUFFERDIMENSION0_7; /**< Source buffer dimension of layer 0., offset: 0x7824 */ __IO uint32_t FETCHDECODE_COLORCOMPONENTBITS0_7; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x7828 */ __IO uint32_t FETCHDECODE_COLORCOMPONENTSHIFT0_7; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x782C */ __IO uint32_t FETCHDECODE_LAYEROFFSET0_7; /**< Position of layer 0 within the destination frame., offset: 0x7830 */ __IO uint32_t FETCHDECODE_CLIPWINDOWOFFSET0_7; /**< Clip window position for layer 0., offset: 0x7834 */ __IO uint32_t FETCHDECODE_CLIPWINDOWDIMENSIONS0_7; /**< Clip window size for layer 0., offset: 0x7838 */ __IO uint32_t FETCHDECODE_CONSTANTCOLOR0_7; /**< Constant color for layer 0., offset: 0x783C */ __IO uint32_t FETCHDECODE_LAYERPROPERTY0_7; /**< Common properties of layer 0., offset: 0x7840 */ __IO uint32_t FETCHDECODE_FRAMEDIMENSIONS_7; /**< Output frame dimension., offset: 0x7844 */ __IO uint32_t FETCHDECODE_FRAMERESAMPLING_7; /**< Resampling options for output frame., offset: 0x7848 */ __IO uint32_t FETCHDECODE_DECODECONTROL_7; /**< Control options for RLAD decompression., offset: 0x784C */ __IO uint32_t FETCHDECODE_SOURCEBUFFERLENGTH_7; /**< Source buffer length for compressed data., offset: 0x7850 */ __IO uint32_t FETCHDECODE_CONTROL_7; /**< Shared common control settings for all layers., offset: 0x7854 */ __O uint32_t FETCHDECODE_CONTROLTRIGGER_7; /**< Shadow load trigger., offset: 0x7858 */ __O uint32_t FETCHDECODE_START_7; /**< Frame start trigger., offset: 0x785C */ __I uint32_t FETCHDECODE_FETCHTYPE_7; /**< Fetch unit type., offset: 0x7860 */ __IO uint32_t FETCHDECODE_DECODERSTATUS_7; /**< Status information of the RLAD decoder., offset: 0x7864 */ __I uint32_t FETCHDECODE_READADDRESS0_7; /**< Ring buffer synchronization for layer 0., offset: 0x7868 */ __I uint32_t FETCHDECODE_BURSTBUFFERPROPERTIES_7; /**< Burst buffer properties., offset: 0x786C */ __IO uint32_t FETCHDECODE_STATUS_7; /**< Status informations., offset: 0x7870 */ __I uint32_t FETCHDECODE_HIDDENSTATUS_7; /**< Hidden status informations., offset: 0x7874 */ uint8_t RESERVED_66[904]; __IO uint32_t COLORPALETTE_7; /**< Color palette look up table., offset: 0x7C00 */ uint8_t RESERVED_67[1020]; __I uint32_t FETCHECO1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8000 */ __I uint32_t FETCHECO1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8004 */ __IO uint32_t FETCHECO1_STATICCONTROL; /**< Common static control options., offset: 0x8008 */ __IO uint32_t FETCHECO1_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x800C */ __IO uint32_t FETCHECO1_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x8010 */ __IO uint32_t FETCHECO1_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x8014 */ __IO uint32_t FETCHECO1_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x8018 */ __IO uint32_t FETCHECO1_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x801C */ __IO uint32_t FETCHECO1_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x8020 */ __IO uint32_t FETCHECO1_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x8024 */ __IO uint32_t FETCHECO1_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x8028 */ __IO uint32_t FETCHECO1_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x802C */ __IO uint32_t FETCHECO1_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x8030 */ __IO uint32_t FETCHECO1_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x8034 */ __IO uint32_t FETCHECO1_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x8038 */ __IO uint32_t FETCHECO1_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x803C */ __IO uint32_t FETCHECO1_CONTROL; /**< Shared common control settings for all layers., offset: 0x8040 */ __O uint32_t FETCHECO1_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x8044 */ __O uint32_t FETCHECO1_START; /**< Frame start trigger., offset: 0x8048 */ __I uint32_t FETCHECO1_FETCHTYPE; /**< Fetch unit type., offset: 0x804C */ __I uint32_t FETCHECO1_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x8050 */ __I uint32_t FETCHECO1_HIDDENSTATUS; /**< Hidden status informations., offset: 0x8054 */ uint8_t RESERVED_68[936]; __I uint32_t FETCHLAYER0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8400 */ __I uint32_t FETCHLAYER0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8404 */ __IO uint32_t FETCHLAYER0_STATICCONTROL; /**< Common static control options., offset: 0x8408 */ __IO uint32_t FETCHLAYER0_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x840C */ __IO uint32_t FETCHLAYER0_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x8410 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x8414 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x8418 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x841C */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x8420 */ __IO uint32_t FETCHLAYER0_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x8424 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x8428 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x842C */ __IO uint32_t FETCHLAYER0_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x8430 */ __IO uint32_t FETCHLAYER0_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x8434 */ __IO uint32_t FETCHLAYER0_BASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x8438 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0x843C */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1,, offset: 0x8440 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS1; /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0x8444 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT1; /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0x8448 */ __IO uint32_t FETCHLAYER0_LAYEROFFSET1; /**< Position of layer 1 within the destination frame., offset: 0x844C */ __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET1; /**< Clip window position for layer 1., offset: 0x8450 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS1; /**< Clip window size for layer 1., offset: 0x8454 */ __IO uint32_t FETCHLAYER0_CONSTANTCOLOR1; /**< Constant color for layer 1., offset: 0x8458 */ __IO uint32_t FETCHLAYER0_LAYERPROPERTY1; /**< Common properties of layer 1., offset: 0x845C */ __IO uint32_t FETCHLAYER0_BASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x8460 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0x8464 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION2; /**< Source buffer dimension of layer 2., offset: 0x8468 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS2; /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0x846C */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT2; /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0x8470 */ __IO uint32_t FETCHLAYER0_LAYEROFFSET2; /**< Position of layer 2 within the destination frame., offset: 0x8474 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET2; /**< Clip window position for layer 2., offset: 0x8478 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS2; /**< Clip window size for layer 2., offset: 0x847C */ __IO uint32_t FETCHLAYER0_CONSTANTCOLOR2; /**< Constant color for layer 2., offset: 0x8480 */ __IO uint32_t FETCHLAYER0_LAYERPROPERTY2; /**< Common properties of layer 2., offset: 0x8484 */ __IO uint32_t FETCHLAYER0_BASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x8488 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0x848C */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION3; /**< Source buffer dimension of layer 3., offset: 0x8490 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS3; /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0x8494 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT3; /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0x8498 */ __IO uint32_t FETCHLAYER0_LAYEROFFSET3; /**< Position of layer 3 within the destination frame., offset: 0x849C */ __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET3; /**< Clip window position for layer 3., offset: 0x84A0 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS3; /**< Clip window size for layer 3., offset: 0x84A4 */ __IO uint32_t FETCHLAYER0_CONSTANTCOLOR3; /**< Constant color for layer 3., offset: 0x84A8 */ __IO uint32_t FETCHLAYER0_LAYERPROPERTY3; /**< Common properties of layer 3., offset: 0x84AC */ __IO uint32_t FETCHLAYER0_BASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x84B0 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0x84B4 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION4; /**< Source buffer dimension of layer 4., offset: 0x84B8 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS4; /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0x84BC */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT4; /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0x84C0 */ __IO uint32_t FETCHLAYER0_LAYEROFFSET4; /**< Position of layer 4 within the destination frame., offset: 0x84C4 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET4; /**< Clip window position for layer 4., offset: 0x84C8 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS4; /**< Clip window size for layer 4., offset: 0x84CC */ __IO uint32_t FETCHLAYER0_CONSTANTCOLOR4; /**< Constant color for layer 4., offset: 0x84D0 */ __IO uint32_t FETCHLAYER0_LAYERPROPERTY4; /**< Common properties of layer 4., offset: 0x84D4 */ __IO uint32_t FETCHLAYER0_BASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x84D8 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0x84DC */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION5; /**< Source buffer dimension of layer 5., offset: 0x84E0 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS5; /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0x84E4 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT5; /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0x84E8 */ __IO uint32_t FETCHLAYER0_LAYEROFFSET5; /**< Position of layer 5 within the destination frame., offset: 0x84EC */ __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET5; /**< Clip window position for layer 5., offset: 0x84F0 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS5; /**< Clip window size for layer 5., offset: 0x84F4 */ __IO uint32_t FETCHLAYER0_CONSTANTCOLOR5; /**< Constant color for layer 5., offset: 0x84F8 */ __IO uint32_t FETCHLAYER0_LAYERPROPERTY5; /**< Common properties of layer 5., offset: 0x84FC */ __IO uint32_t FETCHLAYER0_BASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x8500 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0x8504 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION6; /**< Source buffer dimension of layer 6., offset: 0x8508 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS6; /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0x850C */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT6; /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0x8510 */ __IO uint32_t FETCHLAYER0_LAYEROFFSET6; /**< Position of layer 1 within the destination frame., offset: 0x8514 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET6; /**< Clip window position for layer 6., offset: 0x8518 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS6; /**< Clip window size for layer 6., offset: 0x851C */ __IO uint32_t FETCHLAYER0_CONSTANTCOLOR6; /**< Constant color for layer 6., offset: 0x8520 */ __IO uint32_t FETCHLAYER0_LAYERPROPERTY6; /**< Common properties of layer 6., offset: 0x8524 */ __IO uint32_t FETCHLAYER0_BASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x8528 */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES7; /**< Source buffer stride for layer 7., offset: 0x852C */ __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION7; /**< Source buffer dimension of layer 7., offset: 0x8530 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS7; /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0x8534 */ __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT7; /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0x8538 */ __IO uint32_t FETCHLAYER0_LAYEROFFSET7; /**< Position of layer 7 within the destination frame., offset: 0x853C */ __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET7; /**< Clip window position for layer 7., offset: 0x8540 */ __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS7; /**< Clip window size for layer 7., offset: 0x8544 */ __IO uint32_t FETCHLAYER0_CONSTANTCOLOR7; /**< Constant color for layer 7., offset: 0x8548 */ __IO uint32_t FETCHLAYER0_LAYERPROPERTY7; /**< Common properties of layer 7., offset: 0x854C */ __IO uint32_t FETCHLAYER0_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x8550 */ __IO uint32_t FETCHLAYER0_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x8554 */ __IO uint32_t FETCHLAYER0_CONTROL; /**< Shared common control settings for all layers., offset: 0x8558 */ __I uint32_t FETCHLAYER0_TRIGGERENABLE; /**< Shadow load enable flags for all layers., offset: 0x855C */ __O uint32_t FETCHLAYER0_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x8560 */ __O uint32_t FETCHLAYER0_START; /**< Frame start trigger., offset: 0x8564 */ __I uint32_t FETCHLAYER0_FETCHTYPE; /**< Fetch unit type., offset: 0x8568 */ __I uint32_t FETCHLAYER0_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x856C */ __IO uint32_t FETCHLAYER0_STATUS; /**< Status informations., offset: 0x8570 */ __I uint32_t FETCHLAYER0_HIDDENSTATUS; /**< Hidden status informations., offset: 0x8574 */ uint8_t RESERVED_69[648]; __IO uint32_t FETCHLAYER0_COLORPALETTE; /**< Color palette look up table., offset: 0x8800 */ uint8_t RESERVED_70[1020]; __I uint32_t MATRIX4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8C00 */ __I uint32_t MATRIX4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8C04 */ __IO uint32_t MATRIX4_STATICCONTROL; /**< Color Matrix static control register, offset: 0x8C08 */ __IO uint32_t MATRIX4_CONTROL; /**< Color Matrix control register, offset: 0x8C0C */ __IO uint32_t MATRIX4_RED0; /**< Matrix values for calculation of the red output value., offset: 0x8C10 */ __IO uint32_t MATRIX4_RED1; /**< Matrix values for calculation of the red output value., offset: 0x8C14 */ __IO uint32_t MATRIX4_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0x8C18 */ __IO uint32_t MATRIX4_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0x8C1C */ __IO uint32_t MATRIX4_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0x8C20 */ __IO uint32_t MATRIX4_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0x8C24 */ __IO uint32_t MATRIX4_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0x8C28 */ __IO uint32_t MATRIX4_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0x8C2C */ __IO uint32_t MATRIX4_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0x8C30 */ __IO uint32_t MATRIX4_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0x8C34 */ __I uint32_t MATRIX4_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0x8C38 */ uint8_t RESERVED_71[964]; __I uint32_t HSCALER4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9000 */ __I uint32_t HSCALER4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9004 */ __IO uint32_t HSCALER4_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x9008 */ __IO uint32_t HSCALER4_SETUP1; /**< Phase interpolator setup., offset: 0x900C */ __IO uint32_t HSCALER4_SETUP2; /**< Phase interpolator setup., offset: 0x9010 */ __IO uint32_t HSCALER4_CONTROL; /**< Scaler operation control., offset: 0x9014 */ uint8_t RESERVED_72[1000]; __I uint32_t VSCALER4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9400 */ __I uint32_t VSCALER4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9404 */ __IO uint32_t VSCALER4_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x9408 */ __IO uint32_t VSCALER4_SETUP1; /**< Phase interpolator setup., offset: 0x940C */ __IO uint32_t VSCALER4_SETUP2; /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0x9410 */ __IO uint32_t VSCALER4_SETUP3; /**< Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0., offset: 0x9414 */ __IO uint32_t VSCALER4_SETUP4; /**< Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1., offset: 0x9418 */ __IO uint32_t VSCALER4_SETUP5; /**< Phase interpolator setup, selected if input and output field polarity is 1., offset: 0x941C */ __IO uint32_t VSCALER4_CONTROL; /**< Scaler operation control., offset: 0x9420 */ uint8_t RESERVED_73[988]; __I uint32_t MATRIX5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9800 */ __I uint32_t MATRIX5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9804 */ __IO uint32_t MATRIX5_STATICCONTROL; /**< Color Matrix static control register, offset: 0x9808 */ __IO uint32_t MATRIX5_CONTROL; /**< Color Matrix control register, offset: 0x980C */ __IO uint32_t MATRIX5_RED0; /**< Matrix values for calculation of the red output value., offset: 0x9810 */ __IO uint32_t MATRIX5_RED1; /**< Matrix values for calculation of the red output value., offset: 0x9814 */ __IO uint32_t MATRIX5_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0x9818 */ __IO uint32_t MATRIX5_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0x981C */ __IO uint32_t MATRIX5_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0x9820 */ __IO uint32_t MATRIX5_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0x9824 */ __IO uint32_t MATRIX5_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0x9828 */ __IO uint32_t MATRIX5_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0x982C */ __IO uint32_t MATRIX5_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0x9830 */ __IO uint32_t MATRIX5_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0x9834 */ __I uint32_t MATRIX5_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0x9838 */ uint8_t RESERVED_74[964]; __I uint32_t HSCALER5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9C00 */ __I uint32_t HSCALER5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9C04 */ __IO uint32_t HSCALER5_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x9C08 */ __IO uint32_t HSCALER5_SETUP1; /**< Phase interpolator setup., offset: 0x9C0C */ __IO uint32_t HSCALER5_SETUP2; /**< Phase interpolator setup., offset: 0x9C10 */ __IO uint32_t HSCALER5_CONTROL; /**< Scaler operation control., offset: 0x9C14 */ uint8_t RESERVED_75[1000]; __I uint32_t VSCALER5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA000 */ __I uint32_t VSCALER5_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA004 */ __IO uint32_t VSCALER5_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0xA008 */ __IO uint32_t VSCALER5_SETUP1; /**< Phase interpolator setup., offset: 0xA00C */ __IO uint32_t VSCALER5_SETUP2; /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0xA010 */ __IO uint32_t VSCALER5_SETUP3; /**< Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0., offset: 0xA014 */ __IO uint32_t VSCALER5_SETUP4; /**< Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1., offset: 0xA018 */ __IO uint32_t VSCALER5_SETUP5; /**< Phase interpolator setup, selected if input and output field polarity is 1., offset: 0xA01C */ __IO uint32_t VSCALER5_CONTROL; /**< Scaler operation control., offset: 0xA020 */ uint8_t RESERVED_76[988]; __I uint32_t LAYERBLEND0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA400 */ __I uint32_t LAYERBLEND0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA404 */ __IO uint32_t LAYERBLEND0_STATICCONTROL; /**< Static control settings., offset: 0xA408 */ __IO uint32_t LAYERBLEND0_CONTROL; /**< Common control settings., offset: 0xA40C */ __IO uint32_t LAYERBLEND0_BLENDCONTROL; /**< Options for blend operations, offset: 0xA410 */ __IO uint32_t LAYERBLEND0_POSITION; /**< Position of secondary (overlay) input frame, offset: 0xA414 */ __I uint32_t LAYERBLEND0_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0xA418 */ __I uint32_t LAYERBLEND0_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xA41C */ uint8_t RESERVED_77[992]; __I uint32_t LAYERBLEND1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA800 */ __I uint32_t LAYERBLEND1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA804 */ __IO uint32_t LAYERBLEND1_STATICCONTROL; /**< Static control settings., offset: 0xA808 */ __IO uint32_t LAYERBLEND1_CONTROL; /**< Common control settings., offset: 0xA80C */ __IO uint32_t LAYERBLEND1_BLENDCONTROL; /**< Options for blend operations, offset: 0xA810 */ __IO uint32_t LAYERBLEND1_POSITION; /**< Position of secondary (overlay) input frame, offset: 0xA814 */ __I uint32_t LAYERBLEND1_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0xA818 */ __I uint32_t LAYERBLEND1_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xA81C */ uint8_t RESERVED_78[992]; __I uint32_t LAYERBLEND2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xAC00 */ __I uint32_t LAYERBLEND2_LOCKSTATUS; /**< Protection status of this address block., offset: 0xAC04 */ __IO uint32_t LAYERBLEND2_STATICCONTROL; /**< Static control settings., offset: 0xAC08 */ __IO uint32_t LAYERBLEND2_CONTROL; /**< Common control settings., offset: 0xAC0C */ __IO uint32_t LAYERBLEND2_BLENDCONTROL; /**< Options for blend operations, offset: 0xAC10 */ __IO uint32_t LAYERBLEND2_POSITION; /**< Position of secondary (overlay) input frame, offset: 0xAC14 */ __I uint32_t LAYERBLEND2_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0xAC18 */ __I uint32_t LAYERBLEND2_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xAC1C */ uint8_t RESERVED_79[992]; __I uint32_t LAYERBLEND3_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB000 */ __I uint32_t LAYERBLEND3_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB004 */ __IO uint32_t LAYERBLEND3_STATICCONTROL; /**< Static control settings., offset: 0xB008 */ __IO uint32_t LAYERBLEND3_CONTROL; /**< Common control settings., offset: 0xB00C */ __IO uint32_t LAYERBLEND3_BLENDCONTROL; /**< Options for blend operations, offset: 0xB010 */ __IO uint32_t LAYERBLEND3_POSITION; /**< Position of secondary (overlay) input frame, offset: 0xB014 */ __I uint32_t LAYERBLEND3_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0xB018 */ __I uint32_t LAYERBLEND3_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xB01C */ uint8_t RESERVED_80[992]; __I uint32_t LOCKUNLOCK0; /**< Register to change the protection status of this address block., offset: 0xB400 */ __I uint32_t LOCKSTATUS0; /**< Protection status of this address block., offset: 0xB404 */ __IO uint32_t CLOCKCTRL0; /**< No function in SEERIS-MVPL, internally hardwired to DIV1., offset: 0xB408 */ __IO uint32_t POLARITYCTRL0; /**< Polarity control for TCon#0 input and corresponding top-level output (TCon by-pass port)., offset: 0xB40C */ __IO uint32_t SRCSELECT0; /**< Tap selection for Signature (display stream 0). Disable framegen#0 for reprogramming., offset: 0xB410 */ uint8_t RESERVED_81[12]; __I uint32_t LOCKUNLOCK1; /**< Register to change the protection status of this address block., offset: 0xB420 */ __I uint32_t LOCKSTATUS1; /**< Protection status of this address block., offset: 0xB424 */ __IO uint32_t CLOCKCTRL1; /**< No function in SEERIS-MVPL, internally hardwired to DIV1., offset: 0xB428 */ __IO uint32_t POLARITYCTRL1; /**< Polarity control for TCon#1 input and corresponding top-level output (TCon by-pass port)., offset: 0xB42C */ __IO uint32_t SRCSELECT1; /**< Tap selection for Signature (display stream 1). Disable framegen#1 for reprogramming., offset: 0xB430 */ uint8_t RESERVED_82[972]; __I uint32_t FRAMEGEN0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB800 */ __I uint32_t FRAMEGEN0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB804 */ __IO uint32_t FRAMEGEN0_FGSTCTRL; /**< FrameGen Static Control Register, offset: 0xB808 */ __IO uint32_t FRAMEGEN0_HTCFG1; /**< FrameGen Horizontal Timing Config Register 1, offset: 0xB80C */ __IO uint32_t FRAMEGEN0_HTCFG2; /**< FrameGen Horizontal Timing Config Register 2, offset: 0xB810 */ __IO uint32_t FRAMEGEN0_VTCFG1; /**< FrameGen Vertical Timing Config Register 1, offset: 0xB814 */ __IO uint32_t FRAMEGEN0_VTCFG2; /**< FrameGen Vertical Timing Config Register 2, offset: 0xB818 */ __I uint32_t FRAMEGEN0_INT0CONFIG; /**< Coordinates of the trigger point for generation of the Int0 interrupt signal, offset: 0xB81C */ __I uint32_t FRAMEGEN0_INT1CONFIG; /**< Coordinates of the trigger point for generation of the Int1 interrupt signal, offset: 0xB820 */ __I uint32_t FRAMEGEN0_INT2CONFIG; /**< Coordinates of the trigger point for generation of the Int2 interrupt signal, offset: 0xB824 */ __I uint32_t FRAMEGEN0_INT3CONFIG; /**< Coordinates of the trigger point for generation of the Int3 interrupt signal, offset: 0xB828 */ __IO uint32_t FRAMEGEN0_PKICKCONFIG; /**< Coordinates of the trigger point for generation of the primary kick signal, offset: 0xB82C */ __IO uint32_t FRAMEGEN0_SKICKCONFIG; /**< Coordinates of the trigger point for generation of the secondary kick signal, offset: 0xB830 */ __IO uint32_t FRAMEGEN0_SECSTATCONFIG; /**< Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register., offset: 0xB834 */ __IO uint32_t FRAMEGEN0_FGSRCR1; /**< FrameGen Skew Regulation Control Register 1., offset: 0xB838 */ __IO uint32_t FRAMEGEN0_FGSRCR2; /**< FrameGen Skew Regulation Control Register 2, offset: 0xB83C */ __IO uint32_t FRAMEGEN0_FGSRCR3; /**< FrameGen Skew Regulation Control Register 3, offset: 0xB840 */ __IO uint32_t FRAMEGEN0_FGSRCR4; /**< FrameGen Skew Regulation Control Register 4, offset: 0xB844 */ __IO uint32_t FRAMEGEN0_FGSRCR5; /**< FrameGen Skew Regulation Control Register 5, offset: 0xB848 */ __IO uint32_t FRAMEGEN0_FGSRCR6; /**< FrameGen Skew Regulation Control Register 6, offset: 0xB84C */ __IO uint32_t FRAMEGEN0_FGKSDR; /**< FrameGen Kick System Debug Register, offset: 0xB850 */ __IO uint32_t FRAMEGEN0_PACFG; /**< FrameGen Primary Area Config Register 1 (shadowed), offset: 0xB854 */ __IO uint32_t FRAMEGEN0_SACFG; /**< FrameGen Secondary Area Config Register 1 (shadowed), offset: 0xB858 */ __IO uint32_t FRAMEGEN0_FGINCTRL; /**< FrameGen Input Control Register (shadowed), offset: 0xB85C */ __IO uint32_t FRAMEGEN0_FGINCTRLPANIC; /**< FrameGen Input Control Panic Register (shadowed), offset: 0xB860 */ __IO uint32_t FRAMEGEN0_FGCCR; /**< FrameGen Constant Color Register (shadowed), offset: 0xB864 */ __IO uint32_t FRAMEGEN0_FGENABLE; /**< FrameGen Enable Register, offset: 0xB868 */ __O uint32_t FRAMEGEN0_FGSLR; /**< FrameGen Shadow Load Register, offset: 0xB86C */ __I uint32_t FRAMEGEN0_FGENSTS; /**< FrameGen Enable Status Register, offset: 0xB870 */ __I uint32_t FRAMEGEN0_FGTIMESTAMP; /**< Time stamp status., offset: 0xB874 */ __I uint32_t FRAMEGEN0_FGCHSTAT; /**< FrameGen Channel Status Register, offset: 0xB878 */ __O uint32_t FRAMEGEN0_FGCHSTATCLR; /**< FrameGen Channel Status Clear Register, offset: 0xB87C */ __I uint32_t FRAMEGEN0_FGSKEWMON; /**< FrameGen Skew Monitor Register for Secondary Channel Skew Control, offset: 0xB880 */ __I uint32_t FRAMEGEN0_FGSFIFOMIN; /**< FrameGen Secondary FIFO Min Fill Register, offset: 0xB884 */ __I uint32_t FRAMEGEN0_FGSFIFOMAX; /**< FrameGen Secondary FIFO Max Fill Register, offset: 0xB888 */ __O uint32_t FRAMEGEN0_FGSFIFOFILLCLR; /**< FrameGen Secondary FIFO Fill Clear Register, offset: 0xB88C */ __I uint32_t FRAMEGEN0_FGSREPD; /**< FrameGen Skew Regulation ExtraPolation Debug Register, offset: 0xB890 */ __I uint32_t FRAMEGEN0_FGSRFTD; /**< FrameGen Skew Regulation Frame Total Debug Register, offset: 0xB894 */ uint8_t RESERVED_83[872]; __I uint32_t MATRIX0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xBC00 */ __I uint32_t MATRIX0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xBC04 */ __IO uint32_t MATRIX0_STATICCONTROL; /**< Color Matrix static control register, offset: 0xBC08 */ __IO uint32_t MATRIX0_CONTROL; /**< Color Matrix control register, offset: 0xBC0C */ __IO uint32_t MATRIX0_RED0; /**< Matrix values for calculation of the red output value., offset: 0xBC10 */ __IO uint32_t MATRIX0_RED1; /**< Matrix values for calculation of the red output value., offset: 0xBC14 */ __IO uint32_t MATRIX0_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0xBC18 */ __IO uint32_t MATRIX0_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0xBC1C */ __IO uint32_t MATRIX0_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0xBC20 */ __IO uint32_t MATRIX0_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0xBC24 */ __IO uint32_t MATRIX0_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0xBC28 */ __IO uint32_t MATRIX0_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0xBC2C */ __IO uint32_t MATRIX0_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0xBC30 */ __IO uint32_t MATRIX0_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0xBC34 */ __I uint32_t MATRIX0_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0xBC38 */ uint8_t RESERVED_84[964]; __I uint32_t GAMMACOR0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xC000 */ __I uint32_t GAMMACOR0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xC004 */ __IO uint32_t GAMMACOR0_STATICCONTROL; /**< Static control settings., offset: 0xC008 */ __I uint32_t GAMMACOR0_LUTSTART; /**< Start values for look-up table programming., offset: 0xC00C */ __I uint32_t GAMMACOR0_LUTDELTAS; /**< Delta values for look-up table programming., offset: 0xC010 */ __IO uint32_t GAMMACOR0_CONTROL; /**< Dynamic control settings., offset: 0xC014 */ __IO uint32_t GAMMACOR0_STATUS; /**< Internal status bits., offset: 0xC018 */ __I uint32_t GAMMACOR0_LASTCONTROLWORD; /**< Value of last received control word., offset: 0xC01C */ uint8_t RESERVED_85[992]; __I uint32_t DITHER0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xC400 */ __I uint32_t DITHER0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xC404 */ __IO uint32_t DITHER0_CONTROL; /**< Dither Unit common control., offset: 0xC408 */ __IO uint32_t DITHER0_DITHERCONTROL; /**< Dither Unit processing control., offset: 0xC40C */ __I uint32_t DITHER0_RELEASE; /**< Dither Unit release., offset: 0xC410 */ uint8_t RESERVED_86[1004]; __I uint32_t TCON0_SSQCNTS; /**< The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field, offset: 0xC800 */ uint8_t RESERVED_87[1020]; __I uint32_t TCON0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xCC00 */ __I uint32_t TCON0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xCC04 */ __IO uint32_t TCON0_SSQCYCLE; /**< This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles, offset: 0xCC08 */ __IO uint32_t TCON0_SWRESET; /**< TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document Note: 1/ if tsig[11] pulse=n*pixel_period, (n-1)*0xFF will be blent between ResetWordStart and ResetWordEnd into miniLVDS stream Note: 2/ if( EnResetWord=0) Reset-Pulse (ResetWordStart,ResetWordEnd) won't be blent into miniLVDS stream. Pixels will be transfered unchanged, offset: 0xCC0C */ __IO uint32_t TCON0_CTRL; /**< TCON Control register, offset: 0xCC10 */ __IO uint32_t RSDSINVCTRL; /**< Controls inversion of output polarity when connected IO cells operate in RSDS mode, offset: 0xCC14 */ __IO uint32_t TCON0_MAPBIT3_0; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3, offset: 0xCC18 */ __IO uint32_t TCON0_MAPBIT7_4; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7, offset: 0xCC1C */ __IO uint32_t TCON0_MAPBIT11_8; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11, offset: 0xCC20 */ __IO uint32_t TCON0_MAPBIT15_12; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15, offset: 0xCC24 */ __IO uint32_t TCON0_MAPBIT19_16; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19, offset: 0xCC28 */ __IO uint32_t TCON0_MAPBIT23_20; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23, offset: 0xCC2C */ __IO uint32_t TCON0_MAPBIT27_24; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27, offset: 0xCC30 */ __IO uint32_t TCON0_MAPBIT31_28; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31, offset: 0xCC34 */ __IO uint32_t TCON0_MAPBIT34_32; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34, offset: 0xCC38 */ __IO uint32_t TCON0_MAPBIT3_0_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 2nd channel, offset: 0xCC3C */ __IO uint32_t TCON0_MAPBIT7_4_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 2nd channel, offset: 0xCC40 */ __IO uint32_t TCON0_MAPBIT11_8_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 2nd channel, offset: 0xCC44 */ __IO uint32_t TCON0_MAPBIT15_12_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 2nd channel, offset: 0xCC48 */ __IO uint32_t TCON0_MAPBIT19_16_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 2nd channel, offset: 0xCC4C */ __IO uint32_t TCON0_MAPBIT23_20_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 2nd channel, offset: 0xCC50 */ __IO uint32_t TCON0_MAPBIT27_24_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 2nd channel, offset: 0xCC54 */ __IO uint32_t TCON0_MAPBIT31_28_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 2nd channel, offset: 0xCC58 */ __IO uint32_t TCON0_MAPBIT34_32_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 2nd channel, offset: 0xCC5C */ __IO uint32_t TCON0_SPG0POSON; /**< Sync pulse generator 0, 'Switch on' position, offset: 0xCC60 */ __IO uint32_t TCON0_SPG0MASKON; /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0, offset: 0xCC64 */ __IO uint32_t TCON0_SPG0POSOFF; /**< Sync pulse generator 0, 'Switch off' position, offset: 0xCC68 */ __IO uint32_t TCON0_SPG0MASKOFF; /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0, offset: 0xCC6C */ __IO uint32_t TCON0_SPG1POSON; /**< Sync pulse generator 1, 'Switch on' position, offset: 0xCC70 */ __IO uint32_t TCON0_SPG1MASKON; /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1, offset: 0xCC74 */ __IO uint32_t TCON0_SPG1POSOFF; /**< Sync pulse generator 1, 'Switch off' position, offset: 0xCC78 */ __IO uint32_t TCON0_SPG1MASKOFF; /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1, offset: 0xCC7C */ __IO uint32_t TCON0_SPG2POSON; /**< Sync pulse generator 2, 'Switch on' position, offset: 0xCC80 */ __IO uint32_t TCON0_SPG2MASKON; /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2, offset: 0xCC84 */ __IO uint32_t TCON0_SPG2POSOFF; /**< Sync pulse generator 2, 'Switch off' position, offset: 0xCC88 */ __IO uint32_t TCON0_SPG2MASKOFF; /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2, offset: 0xCC8C */ __IO uint32_t TCON0_SPG3POSON; /**< Sync pulse generator 3, 'Switch on' position, offset: 0xCC90 */ __IO uint32_t TCON0_SPG3MASKON; /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3, offset: 0xCC94 */ __IO uint32_t TCON0_SPG3POSOFF; /**< Sync pulse generator 3, 'Switch off' position, offset: 0xCC98 */ __IO uint32_t TCON0_SPG3MASKOFF; /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3, offset: 0xCC9C */ __IO uint32_t TCON0_SPG4POSON; /**< Sync pulse generator 4, 'Switch on' position, offset: 0xCCA0 */ __IO uint32_t TCON0_SPG4MASKON; /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4, offset: 0xCCA4 */ __IO uint32_t TCON0_SPG4POSOFF; /**< Sync pulse generator 4, 'Switch off' position, offset: 0xCCA8 */ __IO uint32_t TCON0_SPG4MASKOFF; /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4, offset: 0xCCAC */ __IO uint32_t TCON0_SPG5POSON; /**< Sync pulse generator 5, 'Switch on' position, offset: 0xCCB0 */ __IO uint32_t TCON0_SPG5MASKON; /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5, offset: 0xCCB4 */ __IO uint32_t TCON0_SPG5POSOFF; /**< Sync pulse generator 5, 'Switch off' position, offset: 0xCCB8 */ __IO uint32_t TCON0_SPG5MASKOFF; /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5, offset: 0xCCBC */ __IO uint32_t TCON0_SPG6POSON; /**< Sync pulse generator 6, 'Switch on' position, offset: 0xCCC0 */ __IO uint32_t TCON0_SPG6MASKON; /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6, offset: 0xCCC4 */ __IO uint32_t TCON0_SPG6POSOFF; /**< Sync pulse generator 6, 'Switch off' position, offset: 0xCCC8 */ __IO uint32_t TCON0_SPG6MASKOFF; /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6, offset: 0xCCCC */ __IO uint32_t TCON0_SPG7POSON; /**< Sync pulse generator 7, 'Switch on' position, offset: 0xCCD0 */ __IO uint32_t TCON0_SPG7MASKON; /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7, offset: 0xCCD4 */ __IO uint32_t TCON0_SPG7POSOFF; /**< Sync pulse generator 7, 'Switch off' position, offset: 0xCCD8 */ __IO uint32_t TCON0_SPG7MASKOFF; /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7, offset: 0xCCDC */ __IO uint32_t TCON0_SPG8POSON; /**< Sync pulse generator 8, 'Switch on' position, offset: 0xCCE0 */ __IO uint32_t TCON0_SPG8MASKON; /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8, offset: 0xCCE4 */ __IO uint32_t TCON0_SPG8POSOFF; /**< Sync pulse generator 8, 'Switch off' position, offset: 0xCCE8 */ __IO uint32_t TCON0_SPG8MASKOFF; /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8, offset: 0xCCEC */ __IO uint32_t TCON0_SPG9POSON; /**< Sync pulse generator 9, 'Switch on' position, offset: 0xCCF0 */ __IO uint32_t TCON0_SPG9MASKON; /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9, offset: 0xCCF4 */ __IO uint32_t TCON0_SPG9POSOFF; /**< Sync pulse generator 9, 'Switch off' position, offset: 0xCCF8 */ __IO uint32_t TCON0_SPG9MASKOFF; /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9, offset: 0xCCFC */ __IO uint32_t TCON0_SPG10POSON; /**< Sync pulse generator 10, 'Switch on' position, offset: 0xCD00 */ __IO uint32_t TCON0_SPG10MASKON; /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10, offset: 0xCD04 */ __IO uint32_t TCON0_SPG10POSOFF; /**< Sync pulse generator 10, 'Switch off' position, offset: 0xCD08 */ __IO uint32_t TCON0_SPG10MASKOFF; /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10, offset: 0xCD0C */ __IO uint32_t TCON0_SPG11POSON; /**< Sync pulse generator 11, 'Switch on' position, offset: 0xCD10 */ __IO uint32_t TCON0_SPG11MASKON; /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11, offset: 0xCD14 */ __IO uint32_t TCON0_SPG11POSOFF; /**< Sync pulse generator 11, 'Switch off' position, offset: 0xCD18 */ __IO uint32_t TCON0_SPG11MASKOFF; /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11, offset: 0xCD1C */ __IO uint32_t TCON0_SMX0SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD20 */ __IO uint32_t TCON0_SMX0FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD24 */ __IO uint32_t TCON0_SMX1SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD28 */ __IO uint32_t TCON0_SMX1FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD2C */ __IO uint32_t TCON0_SMX2SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD30 */ __IO uint32_t TCON0_SMX2FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD34 */ __IO uint32_t TCON0_SMX3SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD38 */ __IO uint32_t TCON0_SMX3FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD3C */ __IO uint32_t TCON0_SMX4SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD40 */ __IO uint32_t TCON0_SMX4FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD44 */ __IO uint32_t TCON0_SMX5SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD48 */ __IO uint32_t TCON0_SMX5FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD4C */ __IO uint32_t TCON0_SMX6SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD50 */ __IO uint32_t TCON0_SMX6FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD54 */ __IO uint32_t TCON0_SMX7SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD58 */ __IO uint32_t TCON0_SMX7FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD5C */ __IO uint32_t TCON0_SMX8SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD60 */ __IO uint32_t TCON0_SMX8FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD64 */ __IO uint32_t TCON0_SMX9SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD68 */ __IO uint32_t TCON0_SMX9FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD6C */ __IO uint32_t TCON0_SMX10SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD70 */ __IO uint32_t TCON0_SMX10FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD74 */ __IO uint32_t TCON0_SMX11SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD78 */ __IO uint32_t TCON0_SMX11FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD7C */ __O uint32_t TCON0_RESET_OVER_UNFERFLOW; /**< reset status overflow and underflow of both dual channel fifos, offset: 0xCD80 */ __I uint32_t TCON0_DUAL_DEBUG; /**< Status of fifo during dual channel operation. They are only available in Split Mode For Debug only, offset: 0xCD84 */ uint8_t RESERVED_88[632]; __I uint32_t SIG0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xD000 */ __I uint32_t SIG0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xD004 */ __IO uint32_t SIG0_STATICCONTROL; /**< Global configuration shared by all evaluation windows., offset: 0xD008 */ __IO uint32_t SIG0_PANICCOLOR; /**< Overlay color for evaluation windows in panic mode., offset: 0xD00C */ __IO uint32_t SIG0_EVALCONTROL0; /**< Control settings for evaluation window 0., offset: 0xD010 */ __IO uint32_t SIG0_EVALUPPERLEFT0; /**< Upper left corner of evaluation window 0., offset: 0xD014 */ __IO uint32_t SIG0_EVALLOWERRIGHT0; /**< Lower right corner of evaluation window 0., offset: 0xD018 */ __IO uint32_t SIG0_SIGCRCREDREF0; /**< Reference signature of red channel for evaluation window 0., offset: 0xD01C */ __IO uint32_t SIG0_SIGCRCGREENREF0; /**< Reference signature of green channel for evaluation window 0., offset: 0xD020 */ __IO uint32_t SIG0_SIGCRCBLUEREF0; /**< Reference signature of blue channel for evaluation window 0., offset: 0xD024 */ __I uint32_t SIG0_SIGCRCRED0; /**< Measured signature of red channel for evaluation window 0., offset: 0xD028 */ __I uint32_t SIG0_SIGCRCGREEN0; /**< Measured signature of green channel for evaluation window 0., offset: 0xD02C */ __I uint32_t SIG0_SIGCRCBLUE0; /**< Measured signature of blue channel for evaluation window 0., offset: 0xD030 */ __IO uint32_t SIG0_EVALCONTROL1; /**< Control settings for evaluation window 1., offset: 0xD034 */ __IO uint32_t SIG0_EVALUPPERLEFT1; /**< Upper left corner of evaluation window 1., offset: 0xD038 */ __IO uint32_t SIG0_EVALLOWERRIGHT1; /**< Lower right corner of evaluation window 1., offset: 0xD03C */ __IO uint32_t SIG0_SIGCRCREDREF1; /**< Reference signature of red channel for evaluation window 1., offset: 0xD040 */ __IO uint32_t SIG0_SIGCRCGREENREF1; /**< Reference signature of green channel for evaluation window 1., offset: 0xD044 */ __IO uint32_t SIG0_SIGCRCBLUEREF1; /**< Reference signature of blue channel for evaluation window 1., offset: 0xD048 */ __I uint32_t SIG0_SIGCRCRED1; /**< Measured signature of red channel for evaluation window 1., offset: 0xD04C */ __I uint32_t SIG0_SIGCRCGREEN1; /**< Measured signature of green channel for evaluation window 1., offset: 0xD050 */ __I uint32_t SIG0_SIGCRCBLUE1; /**< Measured signature of blue channel for evaluation window 1., offset: 0xD054 */ __IO uint32_t SIG0_EVALCONTROL2; /**< Control settings for evaluation window 2., offset: 0xD058 */ __IO uint32_t SIG0_EVALUPPERLEFT2; /**< Upper left corner of evaluation window 2., offset: 0xD05C */ __IO uint32_t SIG0_EVALLOWERRIGHT2; /**< Lower right corner of evaluation window 2., offset: 0xD060 */ __IO uint32_t SIG0_SIGCRCREDREF2; /**< Reference signature of red channel for evaluation window 2., offset: 0xD064 */ __IO uint32_t SIG0_SIGCRCGREENREF2; /**< Reference signature of green channel for evaluation window 2., offset: 0xD068 */ __IO uint32_t SIG0_SIGCRCBLUEREF2; /**< Reference signature of blue channel for evaluation window 2., offset: 0xD06C */ __I uint32_t SIG0_SIGCRCRED2; /**< Measured signature of red channel for evaluation window 2., offset: 0xD070 */ __I uint32_t SIG0_SIGCRCGREEN2; /**< Measured signature of green channel for evaluation window 2., offset: 0xD074 */ __I uint32_t SIG0_SIGCRCBLUE2; /**< Measured signature of blue channel for evaluation window 2., offset: 0xD078 */ __IO uint32_t SIG0_EVALCONTROL3; /**< Control settings for evaluation window 3., offset: 0xD07C */ __IO uint32_t SIG0_EVALUPPERLEFT3; /**< Upper left corner of evaluation window 3., offset: 0xD080 */ __IO uint32_t SIG0_EVALLOWERRIGHT3; /**< Lower right corner of evaluation window 3., offset: 0xD084 */ __IO uint32_t SIG0_SIGCRCREDREF3; /**< Reference signature of red channel for evaluation window 3., offset: 0xD088 */ __IO uint32_t SIG0_SIGCRCGREENREF3; /**< Reference signature of green channel for evaluation window 3., offset: 0xD08C */ __IO uint32_t SIG0_SIGCRCBLUEREF3; /**< Reference signature of blue channel for evaluation window 3., offset: 0xD090 */ __I uint32_t SIG0_SIGCRCRED3; /**< Measured signature of red channel for evaluation window 3., offset: 0xD094 */ __I uint32_t SIG0_SIGCRCGREEN3; /**< Measured signature of green channel for evaluation window 3., offset: 0xD098 */ __I uint32_t SIG0_SIGCRCBLUE3; /**< Measured signature of blue channel for evaluation window 3., offset: 0xD09C */ __IO uint32_t SIG0_EVALCONTROL4; /**< Control settings for evaluation window 4., offset: 0xD0A0 */ __IO uint32_t SIG0_EVALUPPERLEFT4; /**< Upper left corner of evaluation window 4., offset: 0xD0A4 */ __IO uint32_t SIG0_EVALLOWERRIGHT4; /**< Lower right corner of evaluation window 4., offset: 0xD0A8 */ __IO uint32_t SIG0_SIGCRCREDREF4; /**< Reference signature of red channel for evaluation window 4., offset: 0xD0AC */ __IO uint32_t SIG0_SIGCRCGREENREF4; /**< Reference signature of green channel for evaluation window 4., offset: 0xD0B0 */ __IO uint32_t SIG0_SIGCRCBLUEREF4; /**< Reference signature of blue channel for evaluation window 4., offset: 0xD0B4 */ __I uint32_t SIG0_SIGCRCRED4; /**< Measured signature of red channel for evaluation window 4., offset: 0xD0B8 */ __I uint32_t SIG0_SIGCRCGREEN4; /**< Measured signature of green channel for evaluation window 4., offset: 0xD0BC */ __I uint32_t SIG0_SIGCRCBLUE4; /**< Measured signature of blue channel for evaluation window 4., offset: 0xD0C0 */ __IO uint32_t SIG0_EVALCONTROL5; /**< Control settings for evaluation window 5., offset: 0xD0C4 */ __IO uint32_t SIG0_EVALUPPERLEFT5; /**< Upper left corner of evaluation window 5., offset: 0xD0C8 */ __IO uint32_t SIG0_EVALLOWERRIGHT5; /**< Lower right corner of evaluation window 5., offset: 0xD0CC */ __IO uint32_t SIG0_SIGCRCREDREF5; /**< Reference signature of red channel for evaluation window 5., offset: 0xD0D0 */ __IO uint32_t SIG0_SIGCRCGREENREF5; /**< Reference signature of green channel for evaluation window 5., offset: 0xD0D4 */ __IO uint32_t SIG0_SIGCRCBLUEREF5; /**< Reference signature of blue channel for evaluation window 5., offset: 0xD0D8 */ __I uint32_t SIG0_SIGCRCRED5; /**< Measured signature of red channel for evaluation window 5., offset: 0xD0DC */ __I uint32_t SIG0_SIGCRCGREEN5; /**< Measured signature of green channel for evaluation window 5., offset: 0xD0E0 */ __I uint32_t SIG0_SIGCRCBLUE5; /**< Measured signature of blue channel for evaluation window 5., offset: 0xD0E4 */ __IO uint32_t SIG0_EVALCONTROL6; /**< Control settings for evaluation window 6., offset: 0xD0E8 */ __IO uint32_t SIG0_EVALUPPERLEFT6; /**< Upper left corner of evaluation window 6., offset: 0xD0EC */ __IO uint32_t SIG0_EVALLOWERRIGHT6; /**< Lower right corner of evaluation window 6., offset: 0xD0F0 */ __IO uint32_t SIG0_SIGCRCREDREF6; /**< Reference signature of red channel for evaluation window 6., offset: 0xD0F4 */ __IO uint32_t SIG0_SIGCRCGREENREF6; /**< Reference signature of green channel for evaluation window 6., offset: 0xD0F8 */ __IO uint32_t SIG0_SIGCRCBLUEREF6; /**< Reference signature of blue channel for evaluation window 6., offset: 0xD0FC */ __I uint32_t SIG0_SIGCRCRED6; /**< Measured signature of red channel for evaluation window 6., offset: 0xD100 */ __I uint32_t SIG0_SIGCRCGREEN6; /**< Measured signature of green channel for evaluation window 6., offset: 0xD104 */ __I uint32_t SIG0_SIGCRCBLUE6; /**< Measured signature of blue channel for evaluation window 6., offset: 0xD108 */ __IO uint32_t SIG0_EVALCONTROL7; /**< Control settings for evaluation window 7., offset: 0xD10C */ __IO uint32_t SIG0_EVALUPPERLEFT7; /**< Upper left corner of evaluation window 7., offset: 0xD110 */ __IO uint32_t SIG0_EVALLOWERRIGHT7; /**< Lower right corner of evaluation window 7., offset: 0xD114 */ __IO uint32_t SIG0_SIGCRCREDREF7; /**< Reference signature of red channel for evaluation window 7., offset: 0xD118 */ __IO uint32_t SIG0_SIGCRCGREENREF7; /**< Reference signature of green channel for evaluation window 7., offset: 0xD11C */ __IO uint32_t SIG0_SIGCRCBLUEREF7; /**< Reference signature of blue channel for evaluation window 7., offset: 0xD120 */ __I uint32_t SIG0_SIGCRCRED7; /**< Measured signature of red channel for evaluation window 7., offset: 0xD124 */ __I uint32_t SIG0_SIGCRCGREEN7; /**< Measured signature of green channel for evaluation window 7., offset: 0xD128 */ __I uint32_t SIG0_SIGCRCBLUE7; /**< Measured signature of blue channel for evaluation window 7., offset: 0xD12C */ __I uint32_t SIG0_SHADOWLOAD; /**< Shadow load control register., offset: 0xD130 */ __IO uint32_t SIG0_CONTINUOUSMODE; /**< Signature operation mode control., offset: 0xD134 */ __O uint32_t SIG0_SOFTWAREKICK; /**< Signature measurement trigger., offset: 0xD138 */ __I uint32_t SIG0_STATUS; /**< Module status., offset: 0xD13C */ uint8_t RESERVED_89[704]; __I uint32_t FRAMEGEN1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xD400 */ __I uint32_t FRAMEGEN1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xD404 */ __IO uint32_t FRAMEGEN1_FGSTCTRL; /**< FrameGen Static Control Register, offset: 0xD408 */ __IO uint32_t FRAMEGEN1_HTCFG1; /**< FrameGen Horizontal Timing Config Register 1, offset: 0xD40C */ __IO uint32_t FRAMEGEN1_HTCFG2; /**< FrameGen Horizontal Timing Config Register 2, offset: 0xD410 */ __IO uint32_t FRAMEGEN1_VTCFG1; /**< FrameGen Vertical Timing Config Register 1, offset: 0xD414 */ __IO uint32_t FRAMEGEN1_VTCFG2; /**< FrameGen Vertical Timing Config Register 2, offset: 0xD418 */ __I uint32_t FRAMEGEN1_INT0CONFIG; /**< Coordinates of the trigger point for generation of the Int0 interrupt signal, offset: 0xD41C */ __I uint32_t FRAMEGEN1_INT1CONFIG; /**< Coordinates of the trigger point for generation of the Int1 interrupt signal, offset: 0xD420 */ __I uint32_t FRAMEGEN1_INT2CONFIG; /**< Coordinates of the trigger point for generation of the Int2 interrupt signal, offset: 0xD424 */ __I uint32_t FRAMEGEN1_INT3CONFIG; /**< Coordinates of the trigger point for generation of the Int3 interrupt signal, offset: 0xD428 */ __IO uint32_t FRAMEGEN1_PKICKCONFIG; /**< Coordinates of the trigger point for generation of the primary kick signal, offset: 0xD42C */ __IO uint32_t FRAMEGEN1_SKICKCONFIG; /**< Coordinates of the trigger point for generation of the secondary kick signal, offset: 0xD430 */ __IO uint32_t FRAMEGEN1_SECSTATCONFIG; /**< Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register., offset: 0xD434 */ __IO uint32_t FRAMEGEN1_FGSRCR1; /**< FrameGen Skew Regulation Control Register 1., offset: 0xD438 */ __IO uint32_t FRAMEGEN1_FGSRCR2; /**< FrameGen Skew Regulation Control Register 2, offset: 0xD43C */ __IO uint32_t FRAMEGEN1_FGSRCR3; /**< FrameGen Skew Regulation Control Register 3, offset: 0xD440 */ __IO uint32_t FRAMEGEN1_FGSRCR4; /**< FrameGen Skew Regulation Control Register 4, offset: 0xD444 */ __IO uint32_t FRAMEGEN1_FGSRCR5; /**< FrameGen Skew Regulation Control Register 5, offset: 0xD448 */ __IO uint32_t FRAMEGEN1_FGSRCR6; /**< FrameGen Skew Regulation Control Register 6, offset: 0xD44C */ __IO uint32_t FRAMEGEN1_FGKSDR; /**< FrameGen Kick System Debug Register, offset: 0xD450 */ __IO uint32_t FRAMEGEN1_PACFG; /**< FrameGen Primary Area Config Register 1 (shadowed), offset: 0xD454 */ __IO uint32_t FRAMEGEN1_SACFG; /**< FrameGen Secondary Area Config Register 1 (shadowed), offset: 0xD458 */ __IO uint32_t FRAMEGEN1_FGINCTRL; /**< FrameGen Input Control Register (shadowed), offset: 0xD45C */ __IO uint32_t FRAMEGEN1_FGINCTRLPANIC; /**< FrameGen Input Control Panic Register (shadowed), offset: 0xD460 */ __IO uint32_t FRAMEGEN1_FGCCR; /**< FrameGen Constant Color Register (shadowed), offset: 0xD464 */ __IO uint32_t FRAMEGEN1_FGENABLE; /**< FrameGen Enable Register, offset: 0xD468 */ __O uint32_t FRAMEGEN1_FGSLR; /**< FrameGen Shadow Load Register, offset: 0xD46C */ __I uint32_t FRAMEGEN1_FGENSTS; /**< FrameGen Enable Status Register, offset: 0xD470 */ __I uint32_t FRAMEGEN1_FGTIMESTAMP; /**< Time stamp status., offset: 0xD474 */ __I uint32_t FRAMEGEN1_FGCHSTAT; /**< FrameGen Channel Status Register, offset: 0xD478 */ __O uint32_t FRAMEGEN1_FGCHSTATCLR; /**< FrameGen Channel Status Clear Register, offset: 0xD47C */ __I uint32_t FRAMEGEN1_FGSKEWMON; /**< FrameGen Skew Monitor Register for Secondary Channel Skew Control, offset: 0xD480 */ __I uint32_t FRAMEGEN1_FGSFIFOMIN; /**< FrameGen Secondary FIFO Min Fill Register, offset: 0xD484 */ __I uint32_t FRAMEGEN1_FGSFIFOMAX; /**< FrameGen Secondary FIFO Max Fill Register, offset: 0xD488 */ __O uint32_t FRAMEGEN1_FGSFIFOFILLCLR; /**< FrameGen Secondary FIFO Fill Clear Register, offset: 0xD48C */ __I uint32_t FRAMEGEN1_FGSREPD; /**< FrameGen Skew Regulation ExtraPolation Debug Register, offset: 0xD490 */ __I uint32_t FRAMEGEN1_FGSRFTD; /**< FrameGen Skew Regulation Frame Total Debug Register, offset: 0xD494 */ uint8_t RESERVED_90[872]; __I uint32_t MATRIX1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xD800 */ __I uint32_t MATRIX1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xD804 */ __IO uint32_t MATRIX1_STATICCONTROL; /**< Color Matrix static control register, offset: 0xD808 */ __IO uint32_t MATRIX1_CONTROL; /**< Color Matrix control register, offset: 0xD80C */ __IO uint32_t MATRIX1_RED0; /**< Matrix values for calculation of the red output value., offset: 0xD810 */ __IO uint32_t MATRIX1_RED1; /**< Matrix values for calculation of the red output value., offset: 0xD814 */ __IO uint32_t MATRIX1_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0xD818 */ __IO uint32_t MATRIX1_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0xD81C */ __IO uint32_t MATRIX1_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0xD820 */ __IO uint32_t MATRIX1_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0xD824 */ __IO uint32_t MATRIX1_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0xD828 */ __IO uint32_t MATRIX1_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0xD82C */ __IO uint32_t MATRIX1_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0xD830 */ __IO uint32_t MATRIX1_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0xD834 */ __I uint32_t MATRIX1_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0xD838 */ uint8_t RESERVED_91[964]; __I uint32_t GAMMACOR1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xDC00 */ __I uint32_t GAMMACOR1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xDC04 */ __IO uint32_t GAMMACOR1_STATICCONTROL; /**< Static control settings., offset: 0xDC08 */ __I uint32_t GAMMACOR1_LUTSTART; /**< Start values for look-up table programming., offset: 0xDC0C */ __I uint32_t GAMMACOR1_LUTDELTAS; /**< Delta values for look-up table programming., offset: 0xDC10 */ __IO uint32_t GAMMACOR1_CONTROL; /**< Dynamic control settings., offset: 0xDC14 */ __IO uint32_t GAMMACOR1_STATUS; /**< Internal status bits., offset: 0xDC18 */ __I uint32_t GAMMACOR1_LASTCONTROLWORD; /**< Value of last received control word., offset: 0xDC1C */ uint8_t RESERVED_92[992]; __I uint32_t DITHER1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xE000 */ __I uint32_t DITHER1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xE004 */ __IO uint32_t DITHER1_CONTROL; /**< Dither Unit common control., offset: 0xE008 */ __IO uint32_t DITHER1_DITHERCONTROL; /**< Dither Unit processing control., offset: 0xE00C */ __I uint32_t DITHER1_RELEASE; /**< Dither Unit release., offset: 0xE010 */ uint8_t RESERVED_93[2028]; __I uint32_t TCON1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xE800 */ __I uint32_t TCON1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xE804 */ __IO uint32_t TCON1_SSQCYCLE; /**< This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles, offset: 0xE808 */ __IO uint32_t TCON1_SWRESET; /**< TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document Note: 1/ if tsig[11] pulse=n*pixel_period, (n-1)*0xFF will be blent between ResetWordStart and ResetWordEnd into miniLVDS stream Note: 2/ if( EnResetWord=0) Reset-Pulse (ResetWordStart,ResetWordEnd) won't be blent into miniLVDS stream. Pixels will be transfered unchanged, offset: 0xE80C */ __IO uint32_t TCON1_CTRL; /**< TCON Control register, offset: 0xE810 */ __IO uint32_t TCON1_RSDSINVCTRL; /**< Controls inversion of output polarity when connected IO cells operate in RSDS mode, offset: 0xE814 */ __IO uint32_t TCON1_MAPBIT3_0; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3, offset: 0xE818 */ __IO uint32_t TCON1_MAPBIT7_4; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7, offset: 0xE81C */ __IO uint32_t TCON1_MAPBIT11_8; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11, offset: 0xE820 */ __IO uint32_t TCON1_MAPBIT15_12; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15, offset: 0xE824 */ __IO uint32_t TCON1_MAPBIT19_16; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19, offset: 0xE828 */ __IO uint32_t TCON1_MAPBIT23_20; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23, offset: 0xE82C */ __IO uint32_t TCON1_MAPBIT27_24; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27, offset: 0xE830 */ __IO uint32_t TCON1_MAPBIT31_28; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31, offset: 0xE834 */ __IO uint32_t TCON1_MAPBIT34_32; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34, offset: 0xE838 */ __IO uint32_t TCON1_MAPBIT3_0_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 2nd channel, offset: 0xE83C */ __IO uint32_t TCON1_MAPBIT7_4_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 2nd channel, offset: 0xE840 */ __IO uint32_t TCON1_MAPBIT11_8_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 2nd channel, offset: 0xE844 */ __IO uint32_t TCON1_MAPBIT15_12_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 2nd channel, offset: 0xE848 */ __IO uint32_t TCON1_MAPBIT19_16_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 2nd channel, offset: 0xE84C */ __IO uint32_t TCON1_MAPBIT23_20_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 2nd channel, offset: 0xE850 */ __IO uint32_t TCON1_MAPBIT27_24_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 2nd channel, offset: 0xE854 */ __IO uint32_t TCON1_MAPBIT31_28_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 2nd channel, offset: 0xE858 */ __IO uint32_t TCON1_MAPBIT34_32_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 2nd channel, offset: 0xE85C */ __IO uint32_t TCON1_SPG0POSON; /**< Sync pulse generator 0, 'Switch on' position, offset: 0xE860 */ __IO uint32_t TCON1_SPG0MASKON; /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0, offset: 0xE864 */ __IO uint32_t TCON1_SPG0POSOFF; /**< Sync pulse generator 0, 'Switch off' position, offset: 0xE868 */ __IO uint32_t TCON1_SPG0MASKOFF; /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0, offset: 0xE86C */ __IO uint32_t TCON1_SPG1POSON; /**< Sync pulse generator 1, 'Switch on' position, offset: 0xE870 */ __IO uint32_t TCON1_SPG1MASKON; /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1, offset: 0xE874 */ __IO uint32_t TCON1_SPG1POSOFF; /**< Sync pulse generator 1, 'Switch off' position, offset: 0xE878 */ __IO uint32_t TCON1_SPG1MASKOFF; /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1, offset: 0xE87C */ __IO uint32_t TCON1_SPG2POSON; /**< Sync pulse generator 2, 'Switch on' position, offset: 0xE880 */ __IO uint32_t TCON1_SPG2MASKON; /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2, offset: 0xE884 */ __IO uint32_t TCON1_SPG2POSOFF; /**< Sync pulse generator 2, 'Switch off' position, offset: 0xE888 */ __IO uint32_t TCON1_SPG2MASKOFF; /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2, offset: 0xE88C */ __IO uint32_t TCON1_SPG3POSON; /**< Sync pulse generator 3, 'Switch on' position, offset: 0xE890 */ __IO uint32_t TCON1_SPG3MASKON; /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3, offset: 0xE894 */ __IO uint32_t TCON1_SPG3POSOFF; /**< Sync pulse generator 3, 'Switch off' position, offset: 0xE898 */ __IO uint32_t TCON1_SPG3MASKOFF; /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3, offset: 0xE89C */ __IO uint32_t TCON1_SPG4POSON; /**< Sync pulse generator 4, 'Switch on' position, offset: 0xE8A0 */ __IO uint32_t TCON1_SPG4MASKON; /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4, offset: 0xE8A4 */ __IO uint32_t TCON1_SPG4POSOFF; /**< Sync pulse generator 4, 'Switch off' position, offset: 0xE8A8 */ __IO uint32_t TCON1_SPG4MASKOFF; /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4, offset: 0xE8AC */ __IO uint32_t TCON1_SPG5POSON; /**< Sync pulse generator 5, 'Switch on' position, offset: 0xE8B0 */ __IO uint32_t TCON1_SPG5MASKON; /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5, offset: 0xE8B4 */ __IO uint32_t TCON1_SPG5POSOFF; /**< Sync pulse generator 5, 'Switch off' position, offset: 0xE8B8 */ __IO uint32_t TCON1_SPG5MASKOFF; /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5, offset: 0xE8BC */ __IO uint32_t TCON1_SPG6POSON; /**< Sync pulse generator 6, 'Switch on' position, offset: 0xE8C0 */ __IO uint32_t TCON1_SPG6MASKON; /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6, offset: 0xE8C4 */ __IO uint32_t TCON1_SPG6POSOFF; /**< Sync pulse generator 6, 'Switch off' position, offset: 0xE8C8 */ __IO uint32_t TCON1_SPG6MASKOFF; /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6, offset: 0xE8CC */ __IO uint32_t TCON1_SPG7POSON; /**< Sync pulse generator 7, 'Switch on' position, offset: 0xE8D0 */ __IO uint32_t TCON1_SPG7MASKON; /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7, offset: 0xE8D4 */ __IO uint32_t TCON1_SPG7POSOFF; /**< Sync pulse generator 7, 'Switch off' position, offset: 0xE8D8 */ __IO uint32_t TCON1_SPG7MASKOFF; /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7, offset: 0xE8DC */ __IO uint32_t TCON1_SPG8POSON; /**< Sync pulse generator 8, 'Switch on' position, offset: 0xE8E0 */ __IO uint32_t TCON1_SPG8MASKON; /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8, offset: 0xE8E4 */ __IO uint32_t TCON1_SPG8POSOFF; /**< Sync pulse generator 8, 'Switch off' position, offset: 0xE8E8 */ __IO uint32_t TCON1_SPG8MASKOFF; /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8, offset: 0xE8EC */ __IO uint32_t TCON1_SPG9POSON; /**< Sync pulse generator 9, 'Switch on' position, offset: 0xE8F0 */ __IO uint32_t TCON1_SPG9MASKON; /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9, offset: 0xE8F4 */ __IO uint32_t TCON1_SPG9POSOFF; /**< Sync pulse generator 9, 'Switch off' position, offset: 0xE8F8 */ __IO uint32_t TCON1_SPG9MASKOFF; /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9, offset: 0xE8FC */ __IO uint32_t TCON1_SPG10POSON; /**< Sync pulse generator 10, 'Switch on' position, offset: 0xE900 */ __IO uint32_t TCON1_SPG10MASKON; /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10, offset: 0xE904 */ __IO uint32_t TCON1_SPG10POSOFF; /**< Sync pulse generator 10, 'Switch off' position, offset: 0xE908 */ __IO uint32_t TCON1_SPG10MASKOFF; /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10, offset: 0xE90C */ __IO uint32_t TCON1_SPG11POSON; /**< Sync pulse generator 11, 'Switch on' position, offset: 0xE910 */ __IO uint32_t TCON1_SPG11MASKON; /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11, offset: 0xE914 */ __IO uint32_t TCON1_SPG11POSOFF; /**< Sync pulse generator 11, 'Switch off' position, offset: 0xE918 */ __IO uint32_t TCON1_SPG11MASKOFF; /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11, offset: 0xE91C */ __IO uint32_t TCON1_SMX0SIGS; /**< Selection of input signals of sync mixer, offset: 0xE920 */ __IO uint32_t TCON1_SMX0FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE924 */ __IO uint32_t TCON1_SMX1SIGS; /**< Selection of input signals of sync mixer, offset: 0xE928 */ __IO uint32_t TCON1_SMX1FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE92C */ __IO uint32_t TCON1_SMX2SIGS; /**< Selection of input signals of sync mixer, offset: 0xE930 */ __IO uint32_t TCON1_SMX2FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE934 */ __IO uint32_t TCON1_SMX3SIGS; /**< Selection of input signals of sync mixer, offset: 0xE938 */ __IO uint32_t TCON1_SMX3FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE93C */ __IO uint32_t TCON1_SMX4SIGS; /**< Selection of input signals of sync mixer, offset: 0xE940 */ __IO uint32_t TCON1_SMX4FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE944 */ __IO uint32_t TCON1_SMX5SIGS; /**< Selection of input signals of sync mixer, offset: 0xE948 */ __IO uint32_t TCON1_SMX5FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE94C */ __IO uint32_t TCON1_SMX6SIGS; /**< Selection of input signals of sync mixer, offset: 0xE950 */ __IO uint32_t TCON1_SMX6FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE954 */ __IO uint32_t TCON1_SMX7SIGS; /**< Selection of input signals of sync mixer, offset: 0xE958 */ __IO uint32_t TCON1_SMX7FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE95C */ __IO uint32_t TCON1_SMX8SIGS; /**< Selection of input signals of sync mixer, offset: 0xE960 */ __IO uint32_t TCON1_SMX8FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE964 */ __IO uint32_t TCON1_SMX9SIGS; /**< Selection of input signals of sync mixer, offset: 0xE968 */ __IO uint32_t TCON1_SMX9FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE96C */ __IO uint32_t TCON1_SMX10SIGS; /**< Selection of input signals of sync mixer, offset: 0xE970 */ __IO uint32_t TCON1_SMX10FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE974 */ __IO uint32_t TCON1_SMX11SIGS; /**< Selection of input signals of sync mixer, offset: 0xE978 */ __IO uint32_t TCON1_SMX11FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE97C */ __O uint32_t TCON1_RESET_OVER_UNFERFLOW; /**< reset status overflow and underflow of both dual channel fifos, offset: 0xE980 */ __I uint32_t TCON1_DUAL_DEBUG; /**< Status of fifo during dual channel operation. They are only available in Split Mode For Debug only, offset: 0xE984 */ uint8_t RESERVED_94[632]; __I uint32_t SIG1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xEC00 */ __I uint32_t SIG1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xEC04 */ __IO uint32_t SIG1_STATICCONTROL; /**< Global configuration shared by all evaluation windows., offset: 0xEC08 */ __IO uint32_t SIG1_PANICCOLOR; /**< Overlay color for evaluation windows in panic mode., offset: 0xEC0C */ __IO uint32_t SIG1_EVALCONTROL0; /**< Control settings for evaluation window 0., offset: 0xEC10 */ __IO uint32_t SIG1_EVALUPPERLEFT0; /**< Upper left corner of evaluation window 0., offset: 0xEC14 */ __IO uint32_t SIG1_EVALLOWERRIGHT0; /**< Lower right corner of evaluation window 0., offset: 0xEC18 */ __IO uint32_t SIG1_SIGCRCREDREF0; /**< Reference signature of red channel for evaluation window 0., offset: 0xEC1C */ __IO uint32_t SIG1_SIGCRCGREENREF0; /**< Reference signature of green channel for evaluation window 0., offset: 0xEC20 */ __IO uint32_t SIG1_SIGCRCBLUEREF0; /**< Reference signature of blue channel for evaluation window 0., offset: 0xEC24 */ __I uint32_t SIG1_SIGCRCRED0; /**< Measured signature of red channel for evaluation window 0., offset: 0xEC28 */ __I uint32_t SIG1_SIGCRCGREEN0; /**< Measured signature of green channel for evaluation window 0., offset: 0xEC2C */ __I uint32_t SIG1_SIGCRCBLUE0; /**< Measured signature of blue channel for evaluation window 0., offset: 0xEC30 */ __IO uint32_t SIG1_EVALCONTROL1; /**< Control settings for evaluation window 1., offset: 0xEC34 */ __IO uint32_t SIG1_EVALUPPERLEFT1; /**< Upper left corner of evaluation window 1., offset: 0xEC38 */ __IO uint32_t SIG1_EVALLOWERRIGHT1; /**< Lower right corner of evaluation window 1., offset: 0xEC3C */ __IO uint32_t SIG1_SIGCRCREDREF1; /**< Reference signature of red channel for evaluation window 1., offset: 0xEC40 */ __IO uint32_t SIG1_SIGCRCGREENREF1; /**< Reference signature of green channel for evaluation window 1., offset: 0xEC44 */ __IO uint32_t SIG1_SIGCRCBLUEREF1; /**< Reference signature of blue channel for evaluation window 1., offset: 0xEC48 */ __I uint32_t SIG1_SIGCRCRED1; /**< Measured signature of red channel for evaluation window 1., offset: 0xEC4C */ __I uint32_t SIG1_SIGCRCGREEN1; /**< Measured signature of green channel for evaluation window 1., offset: 0xEC50 */ __I uint32_t SIG1_SIGCRCBLUE1; /**< Measured signature of blue channel for evaluation window 1., offset: 0xEC54 */ __IO uint32_t SIG1_EVALCONTROL2; /**< Control settings for evaluation window 2., offset: 0xEC58 */ __IO uint32_t SIG1_EVALUPPERLEFT2; /**< Upper left corner of evaluation window 2., offset: 0xEC5C */ __IO uint32_t SIG1_EVALLOWERRIGHT2; /**< Lower right corner of evaluation window 2., offset: 0xEC60 */ __IO uint32_t SIG1_SIGCRCREDREF2; /**< Reference signature of red channel for evaluation window 2., offset: 0xEC64 */ __IO uint32_t SIG1_SIGCRCGREENREF2; /**< Reference signature of green channel for evaluation window 2., offset: 0xEC68 */ __IO uint32_t SIG1_SIGCRCBLUEREF2; /**< Reference signature of blue channel for evaluation window 2., offset: 0xEC6C */ __I uint32_t SIG1_SIGCRCRED2; /**< Measured signature of red channel for evaluation window 2., offset: 0xEC70 */ __I uint32_t SIG1_SIGCRCGREEN2; /**< Measured signature of green channel for evaluation window 2., offset: 0xEC74 */ __I uint32_t SIG1_SIGCRCBLUE2; /**< Measured signature of blue channel for evaluation window 2., offset: 0xEC78 */ __IO uint32_t SIG1_EVALCONTROL3; /**< Control settings for evaluation window 3., offset: 0xEC7C */ __IO uint32_t SIG1_EVALUPPERLEFT3; /**< Upper left corner of evaluation window 3., offset: 0xEC80 */ __IO uint32_t SIG1_EVALLOWERRIGHT3; /**< Lower right corner of evaluation window 3., offset: 0xEC84 */ __IO uint32_t SIG1_SIGCRCREDREF3; /**< Reference signature of red channel for evaluation window 3., offset: 0xEC88 */ __IO uint32_t SIG1_SIGCRCGREENREF3; /**< Reference signature of green channel for evaluation window 3., offset: 0xEC8C */ __IO uint32_t SIG1_SIGCRCBLUEREF3; /**< Reference signature of blue channel for evaluation window 3., offset: 0xEC90 */ __I uint32_t SIG1_SIGCRCRED3; /**< Measured signature of red channel for evaluation window 3., offset: 0xEC94 */ __I uint32_t SIG1_SIGCRCGREEN3; /**< Measured signature of green channel for evaluation window 3., offset: 0xEC98 */ __I uint32_t SIG1_SIGCRCBLUE3; /**< Measured signature of blue channel for evaluation window 3., offset: 0xEC9C */ __IO uint32_t SIG1_EVALCONTROL4; /**< Control settings for evaluation window 4., offset: 0xECA0 */ __IO uint32_t SIG1_EVALUPPERLEFT4; /**< Upper left corner of evaluation window 4., offset: 0xECA4 */ __IO uint32_t SIG1_EVALLOWERRIGHT4; /**< Lower right corner of evaluation window 4., offset: 0xECA8 */ __IO uint32_t SIG1_SIGCRCREDREF4; /**< Reference signature of red channel for evaluation window 4., offset: 0xECAC */ __IO uint32_t SIG1_SIGCRCGREENREF4; /**< Reference signature of green channel for evaluation window 4., offset: 0xECB0 */ __IO uint32_t SIG1_SIGCRCBLUEREF4; /**< Reference signature of blue channel for evaluation window 4., offset: 0xECB4 */ __I uint32_t SIG1_SIGCRCRED4; /**< Measured signature of red channel for evaluation window 4., offset: 0xECB8 */ __I uint32_t SIG1_SIGCRCGREEN4; /**< Measured signature of green channel for evaluation window 4., offset: 0xECBC */ __I uint32_t SIG1_SIGCRCBLUE4; /**< Measured signature of blue channel for evaluation window 4., offset: 0xECC0 */ __IO uint32_t SIG1_EVALCONTROL5; /**< Control settings for evaluation window 5., offset: 0xECC4 */ __IO uint32_t SIG1_EVALUPPERLEFT5; /**< Upper left corner of evaluation window 5., offset: 0xECC8 */ __IO uint32_t SIG1_EVALLOWERRIGHT5; /**< Lower right corner of evaluation window 5., offset: 0xECCC */ __IO uint32_t SIG1_SIGCRCREDREF5; /**< Reference signature of red channel for evaluation window 5., offset: 0xECD0 */ __IO uint32_t SIG1_SIGCRCGREENREF5; /**< Reference signature of green channel for evaluation window 5., offset: 0xECD4 */ __IO uint32_t SIG1_SIGCRCBLUEREF5; /**< Reference signature of blue channel for evaluation window 5., offset: 0xECD8 */ __I uint32_t SIG1_SIGCRCRED5; /**< Measured signature of red channel for evaluation window 5., offset: 0xECDC */ __I uint32_t SIG1_SIGCRCGREEN5; /**< Measured signature of green channel for evaluation window 5., offset: 0xECE0 */ __I uint32_t SIG1_SIGCRCBLUE5; /**< Measured signature of blue channel for evaluation window 5., offset: 0xECE4 */ __IO uint32_t SIG1_EVALCONTROL6; /**< Control settings for evaluation window 6., offset: 0xECE8 */ __IO uint32_t SIG1_EVALUPPERLEFT6; /**< Upper left corner of evaluation window 6., offset: 0xECEC */ __IO uint32_t SIG1_EVALLOWERRIGHT6; /**< Lower right corner of evaluation window 6., offset: 0xECF0 */ __IO uint32_t SIG1_SIGCRCREDREF6; /**< Reference signature of red channel for evaluation window 6., offset: 0xECF4 */ __IO uint32_t SIG1_SIGCRCGREENREF6; /**< Reference signature of green channel for evaluation window 6., offset: 0xECF8 */ __IO uint32_t SIG1_SIGCRCBLUEREF6; /**< Reference signature of blue channel for evaluation window 6., offset: 0xECFC */ __I uint32_t SIG1_SIGCRCRED6; /**< Measured signature of red channel for evaluation window 6., offset: 0xED00 */ __I uint32_t SIG1_SIGCRCGREEN6; /**< Measured signature of green channel for evaluation window 6., offset: 0xED04 */ __I uint32_t SIG1_SIGCRCBLUE6; /**< Measured signature of blue channel for evaluation window 6., offset: 0xED08 */ __IO uint32_t SIG1_EVALCONTROL7; /**< Control settings for evaluation window 7., offset: 0xED0C */ __IO uint32_t SIG1_EVALUPPERLEFT7; /**< Upper left corner of evaluation window 7., offset: 0xED10 */ __IO uint32_t SIG1_EVALLOWERRIGHT7; /**< Lower right corner of evaluation window 7., offset: 0xED14 */ __IO uint32_t SIG1_SIGCRCREDREF7; /**< Reference signature of red channel for evaluation window 7., offset: 0xED18 */ __IO uint32_t SIG1_SIGCRCGREENREF7; /**< Reference signature of green channel for evaluation window 7., offset: 0xED1C */ __IO uint32_t SIG1_SIGCRCBLUEREF7; /**< Reference signature of blue channel for evaluation window 7., offset: 0xED20 */ __I uint32_t SIG1_SIGCRCRED7; /**< Measured signature of red channel for evaluation window 7., offset: 0xED24 */ __I uint32_t SIG1_SIGCRCGREEN7; /**< Measured signature of green channel for evaluation window 7., offset: 0xED28 */ __I uint32_t SIG1_SIGCRCBLUE7; /**< Measured signature of blue channel for evaluation window 7., offset: 0xED2C */ __I uint32_t SIG1_SHADOWLOAD; /**< Shadow load control register., offset: 0xED30 */ __IO uint32_t SIG1_CONTINUOUSMODE; /**< Signature operation mode control., offset: 0xED34 */ __O uint32_t SIG1_SOFTWAREKICK; /**< Signature measurement trigger., offset: 0xED38 */ __I uint32_t SIG1_STATUS; /**< Module status., offset: 0xED3C */ uint8_t RESERVED_95[704]; __IO uint32_t CONTROL; /**< Measurement Control Register, offset: 0xF000 */ __IO uint32_t TIMER; /**< Timer Register, offset: 0xF004 */ __IO uint32_t MEASUREMENTTIMECONTROL; /**< Timer Control Register, offset: 0xF008 */ __I uint32_t SW_TAG; /**< Software Tag Register, offset: 0xF00C */ __I uint32_t MEASUREMENTTIME; /**< Measurement Time Register, offset: 0xF010 */ __I uint32_t GLOBAL_COUNTER; /**< Global Counter Register, offset: 0xF014 */ __IO uint32_t MU00_SWITCH; /**< Measurement Unit 0 Source Select Register, offset: 0xF018 */ __I uint32_t MU00_DATA_COUNTER; /**< Measurement Unit 0 Data Cycle Counter, offset: 0xF01C */ __I uint32_t MU00_BUSY_COUNTER; /**< Measurement Unit 0 Busy Cycle Counter, offset: 0xF020 */ __I uint32_t MU00_TRANSFER_COUNTER; /**< Measurement Unit 0 Transfer Counter, offset: 0xF024 */ __I uint32_t MU00_ADDRBUSY_COUNTER; /**< Measurement Unit 0 Address Busy Cycle Counter, offset: 0xF028 */ __I uint32_t MU00_LATENCY_COUNTER; /**< Measurement Unit 0 Latency Counter, offset: 0xF02C */ __IO uint32_t MU01_SWITCH; /**< Measurement Unit 1 Source Select Register, offset: 0xF030 */ __I uint32_t MU01_DATA_COUNTER; /**< Measurement Unit 1 Data Cycle Counter, offset: 0xF034 */ __I uint32_t MU01_BUSY_COUNTER; /**< Measurement Unit 1 Busy Cycle Counter, offset: 0xF038 */ __I uint32_t MU01_TRANSFER_COUNTER; /**< Measurement Unit 1 Transfer Counter, offset: 0xF03C */ __I uint32_t MU01_ADDRBUSY_COUNTER; /**< Measurement Unit 1 Address Busy Cycle Counter, offset: 0xF040 */ __I uint32_t MU01_LATENCY_COUNTER; /**< Measurement Unit 1 Latency Counter, offset: 0xF044 */ __IO uint32_t MU02_SWITCH; /**< Measurement Unit 2 Source Select Register, offset: 0xF048 */ __I uint32_t MU02_DATA_COUNTER; /**< Measurement Unit 2 Data Cycle Counter, offset: 0xF04C */ __I uint32_t MU02_BUSY_COUNTER; /**< Measurement Unit 2 Busy Cycle Counter, offset: 0xF050 */ __I uint32_t MU02_TRANSFER_COUNTER; /**< Measurement Unit 2 Transfer Counter, offset: 0xF054 */ __I uint32_t MU02_ADDRBUSY_COUNTER; /**< Measurement Unit 2 Address Busy Cycle Counter, offset: 0xF058 */ __I uint32_t MU02_LATENCY_COUNTER; /**< Measurement Unit 2 Latency Counter, offset: 0xF05C */ __IO uint32_t MU03_SWITCH; /**< Measurement Unit 3 Source Select Register, offset: 0xF060 */ __I uint32_t MU03_DATA_COUNTER; /**< Measurement Unit 3 Data Cycle Counter, offset: 0xF064 */ __I uint32_t MU03_BUSY_COUNTER; /**< Measurement Unit 3 Busy Cycle Counter, offset: 0xF068 */ __I uint32_t MU03_TRANSFER_COUNTER; /**< Measurement Unit 3 Transfer Counter, offset: 0xF06C */ __I uint32_t MU03_ADDRBUSY_COUNTER; /**< Measurement Unit 3 Address Busy Cycle Counter, offset: 0xF070 */ __I uint32_t MU03_LATENCY_COUNTER; /**< Measurement Unit 3 Latency Counter, offset: 0xF074 */ __IO uint32_t MU04_SWITCH; /**< Measurement Unit 4 Source Select Register, offset: 0xF078 */ __I uint32_t MU04_DATA_COUNTER; /**< Measurement Unit 4 Data Cycle Counter, offset: 0xF07C */ __I uint32_t MU04_BUSY_COUNTER; /**< Measurement Unit 4 Busy Cycle Counter, offset: 0xF080 */ __I uint32_t MU04_TRANSFER_COUNTER; /**< Measurement Unit 4 Transfer Counter, offset: 0xF084 */ __I uint32_t MU04_ADDRBUSY_COUNTER; /**< Measurement Unit 4 Address Busy Cycle Counter, offset: 0xF088 */ __I uint32_t MU04_LATENCY_COUNTER; /**< Measurement Unit 4 Latency Counter, offset: 0xF08C */ uint8_t RESERVED_96[55152]; __I uint32_t TCON1_SSQCNTS; /**< The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field, offset: 0x1C800 */ } IRIS_MVPL_Type; /* ---------------------------------------------------------------------------- -- IRIS_MVPL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IRIS_MVPL_Register_Masks IRIS_MVPL Register Masks * @{ */ /*! @name IPIDENTIFIER - IP Identifier for this SEERIS derivate. */ /*! @{ */ #define IRIS_MVPL_IPIDENTIFIER_DesignDeliveryID_MASK (0xF0U) #define IRIS_MVPL_IPIDENTIFIER_DesignDeliveryID_SHIFT (4U) /*! DesignDeliveryID - Design delivery ID (increased with each official delivery when maturity keeps the same). */ #define IRIS_MVPL_IPIDENTIFIER_DesignDeliveryID(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_DesignDeliveryID_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_DesignDeliveryID_MASK) #define IRIS_MVPL_IPIDENTIFIER_DesignMaturityLevel_MASK (0xF00U) #define IRIS_MVPL_IPIDENTIFIER_DesignMaturityLevel_SHIFT (8U) /*! DesignMaturityLevel - Design maturity level (corresponds to status at time of IP delivery, Fujitsu internal development stages) * 0b0001..Pre feasibility study. * 0b0010..Feasibility study. * 0b0011..Functionality complete. * 0b0100..Verification complete. */ #define IRIS_MVPL_IPIDENTIFIER_DesignMaturityLevel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_DesignMaturityLevel_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_DesignMaturityLevel_MASK) #define IRIS_MVPL_IPIDENTIFIER_IPEvolution_MASK (0xF000U) #define IRIS_MVPL_IPIDENTIFIER_IPEvolution_SHIFT (12U) /*! IPEvolution - IP evolution (increased for functional spec changes only when feature set keeps the same) */ #define IRIS_MVPL_IPIDENTIFIER_IPEvolution(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_IPEvolution_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_IPEvolution_MASK) #define IRIS_MVPL_IPIDENTIFIER_IPFeatureSet_MASK (0xF0000U) #define IRIS_MVPL_IPIDENTIFIER_IPFeatureSet_SHIFT (16U) /*! IPFeatureSet - IP feature set (complexity of implemented features, e.g. availability of re-sampling filter etc) * 0b0001..Minimal functionality (Eco). * 0b0010..Reduced functionality (Light). * 0b0100..Advanced functionality (Plus). * 0b0101..Extensive functionality (eXtensive). */ #define IRIS_MVPL_IPIDENTIFIER_IPFeatureSet(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_IPFeatureSet_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_IPFeatureSet_MASK) #define IRIS_MVPL_IPIDENTIFIER_IPApplication_MASK (0xF00000U) #define IRIS_MVPL_IPIDENTIFIER_IPApplication_SHIFT (20U) /*! IPApplication - IP application * 0b0001..Blit Engine only. * 0b0010..Blit Engine and Display Controller. * 0b0011..Display Controller only (with direct capture). * 0b0100..Blit Engine, Display Controller (with direct capture), Capture Controller (buffered capture) and Drawing Engine. * 0b0101..Display Controller only. */ #define IRIS_MVPL_IPIDENTIFIER_IPApplication(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_IPApplication_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_IPApplication_MASK) #define IRIS_MVPL_IPIDENTIFIER_IPConfiguration_MASK (0xF000000U) #define IRIS_MVPL_IPIDENTIFIER_IPConfiguration_SHIFT (24U) /*! IPConfiguration - Ip configuration * 0b0001..Graphics core only (Module). * 0b0010..Subsystem including a graphics core (System). */ #define IRIS_MVPL_IPIDENTIFIER_IPConfiguration(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_IPConfiguration_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_IPConfiguration_MASK) #define IRIS_MVPL_IPIDENTIFIER_IPFamily_MASK (0xF0000000U) #define IRIS_MVPL_IPIDENTIFIER_IPFamily_SHIFT (28U) /*! IPFamily - IP family * 0b0000..Iris building block generation 2010. * 0b0001..Iris building block generation 2012. * 0b0010..Iris building block generation 2013. */ #define IRIS_MVPL_IPIDENTIFIER_IPFamily(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_IPFamily_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_IPFamily_MASK) /*! @} */ /*! @name COMCTRL_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name COMCTRL_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name COMCTRL_USERINTERRUPTMASK0 - Interrupt UserMask register 0 */ /*! @{ */ #define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_SHIFT (0U) /*! UserInterruptMask0 - UserMask vector for interrupts. Only interrupts that are set in this vector * can be accessed by the unprotected UserInterruptEnable0, UserInterruptPreset0 and * UserInterruptClear0 registers as well. */ #define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_MASK) /*! @} */ /*! @name COMCTRL_USERINTERRUPTMASK1 - Interrupt UserMask register 1 */ /*! @{ */ #define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_MASK (0x1FFFFU) #define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_SHIFT (0U) /*! UserInterruptMask1 - UserMask vector for interrupts. Only interrupts that are set in this vector * can be accessed by the unprotected UserInterruptEnable1, UserInterruptPreset1 and * UserInterruptClear1 registers as well. */ #define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_MASK) /*! @} */ /*! @name COMCTRL_INTERRUPTENABLE0 - Interrupt Enable register 0 */ /*! @{ */ #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT (0U) /*! InterruptEnable0 - Enable vector for interrupts. InterruptEnable0[n] is mapped to Interrupt (n + * 0) (1=enable, 0=disable). Please note that this enable vector does not affect the * InterruptStatus register fields and the cmdseq sysstatus vector. It only affects the interrupt outputs * going to higher hierarchies than SEERIS. */ #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK) /*! @} */ /*! @name COMCTRL_INTERRUPTENABLE1 - Interrupt Enable register 1 */ /*! @{ */ #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_MASK (0x1FFFFU) #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_SHIFT (0U) /*! InterruptEnable1 - Enable vector for interrupts. InterruptEnable1[n] is mapped to Interrupt (n + * 32) (1=enable, 0=disable). Please note that this enable vector does not affect the * InterruptStatus register fields and the cmdseq sysstatus vector. It only affects the interrupt outputs * going to higher hierarchies than SEERIS. */ #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_MASK) /*! @} */ /*! @name COMCTRL_INTERRUPTPRESET0 - Interrupt Preset register 0 */ /*! @{ */ #define IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_SHIFT (0U) /*! InterruptPreset0 - Preset vector for interrupts. InterruptPreset0[n] is mapped to Interrupt (n + * 0) (write 1 to bit [n] to set interrupt (n + 0)). */ #define IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_MASK) /*! @} */ /*! @name COMCTRL_INTERRUPTPRESET1 - Interrupt Preset register 1 */ /*! @{ */ #define IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_MASK (0x1FFFFU) #define IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_SHIFT (0U) /*! InterruptPreset1 - Preset vector for interrupts. InterruptPreset1[n] is mapped to Interrupt (n + * 32) (write 1 to bit [n] to set interrupt (n + 32)). */ #define IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_MASK) /*! @} */ /*! @name COMCTRL_INTERRUPTCLEAR0 - Interrupt Clear register 0 */ /*! @{ */ #define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_SHIFT (0U) /*! InterruptClear0 - Clear vector for interrupts. InterruptClear0[n] is mapped to Interrupt (n + 0) * (write 1 to bit [n] to clear interrupt (n + 0)). */ #define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_MASK) /*! @} */ /*! @name COMCTRL_INTERRUPTCLEAR1 - Interrupt Clear register 1 */ /*! @{ */ #define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_MASK (0x1FFFFU) #define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_SHIFT (0U) /*! InterruptClear1 - Clear vector for interrupts. InterruptClear1[n] is mapped to Interrupt (n + * 32) (write 1 to bit [n] to clear interrupt (n + 32)). */ #define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_MASK) /*! @} */ /*! @name COMCTRL_INTERRUPTSTATUS0 - Interrupt Status register 0 */ /*! @{ */ #define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_SHIFT (0U) /*! InterruptStatus0 - Status vector of interrupts. InterruptStatus0[n] is mapped to Interrupt (n + 0) (1=set, 0=not set). */ #define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_MASK) /*! @} */ /*! @name COMCTRL_INTERRUPTSTATUS1 - Interrupt Status register 1 */ /*! @{ */ #define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_MASK (0x1FFFFU) #define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_SHIFT (0U) /*! InterruptStatus1 - Status vector of interrupts. InterruptStatus1[n] is mapped to Interrupt (n + 32) (1=set, 0=not set). */ #define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_MASK) /*! @} */ /*! @name USERINTERRUPTENABLE0 - Interrupt Enable register 0 for user mode access */ /*! @{ */ #define IRIS_MVPL_USERINTERRUPTENABLE0_UserInterruptEnable0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_USERINTERRUPTENABLE0_UserInterruptEnable0_SHIFT (0U) /*! UserInterruptEnable0 - Same as InterruptEnable0, except only effective for bits which are set in UserInterruptMask0. */ #define IRIS_MVPL_USERINTERRUPTENABLE0_UserInterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTENABLE0_UserInterruptEnable0_SHIFT)) & IRIS_MVPL_USERINTERRUPTENABLE0_UserInterruptEnable0_MASK) /*! @} */ /*! @name USERINTERRUPTENABLE1 - Interrupt Enable register 1 for user mode access */ /*! @{ */ #define IRIS_MVPL_USERINTERRUPTENABLE1_UserInterruptEnable1_MASK (0x1FFFFU) #define IRIS_MVPL_USERINTERRUPTENABLE1_UserInterruptEnable1_SHIFT (0U) /*! UserInterruptEnable1 - Same as InterruptEnable1, except only effective for bits which are set in UserInterruptMask1. */ #define IRIS_MVPL_USERINTERRUPTENABLE1_UserInterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTENABLE1_UserInterruptEnable1_SHIFT)) & IRIS_MVPL_USERINTERRUPTENABLE1_UserInterruptEnable1_MASK) /*! @} */ /*! @name USERINTERRUPTPRESET0 - Interrupt Preset register 0 */ /*! @{ */ #define IRIS_MVPL_USERINTERRUPTPRESET0_UserInterruptPreset0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_USERINTERRUPTPRESET0_UserInterruptPreset0_SHIFT (0U) /*! UserInterruptPreset0 - Same as InterruptPreset0, except only effective for bits which are set in UserInterruptMask0. */ #define IRIS_MVPL_USERINTERRUPTPRESET0_UserInterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTPRESET0_UserInterruptPreset0_SHIFT)) & IRIS_MVPL_USERINTERRUPTPRESET0_UserInterruptPreset0_MASK) /*! @} */ /*! @name USERINTERRUPTPRESET1 - Interrupt Preset register 1 */ /*! @{ */ #define IRIS_MVPL_USERINTERRUPTPRESET1_UserInterruptPreset1_MASK (0x1FFFFU) #define IRIS_MVPL_USERINTERRUPTPRESET1_UserInterruptPreset1_SHIFT (0U) /*! UserInterruptPreset1 - Same as InterruptPreset1, except only effective for bits which are set in UserInterruptMask1. */ #define IRIS_MVPL_USERINTERRUPTPRESET1_UserInterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTPRESET1_UserInterruptPreset1_SHIFT)) & IRIS_MVPL_USERINTERRUPTPRESET1_UserInterruptPreset1_MASK) /*! @} */ /*! @name USERINTERRUPTCLEAR0 - Interrupt Clear register 0 */ /*! @{ */ #define IRIS_MVPL_USERINTERRUPTCLEAR0_UserInterruptClear0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_USERINTERRUPTCLEAR0_UserInterruptClear0_SHIFT (0U) /*! UserInterruptClear0 - Same as InterruptClear0, except only effective for bits which are set in UserInterruptMask0. */ #define IRIS_MVPL_USERINTERRUPTCLEAR0_UserInterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTCLEAR0_UserInterruptClear0_SHIFT)) & IRIS_MVPL_USERINTERRUPTCLEAR0_UserInterruptClear0_MASK) /*! @} */ /*! @name USERINTERRUPTCLEAR1 - Interrupt Clear register 1 */ /*! @{ */ #define IRIS_MVPL_USERINTERRUPTCLEAR1_UserInterruptClear1_MASK (0x1FFFFU) #define IRIS_MVPL_USERINTERRUPTCLEAR1_UserInterruptClear1_SHIFT (0U) /*! UserInterruptClear1 - Same as InterruptClear1, except only effective for bits which are set in UserInterruptMask1. */ #define IRIS_MVPL_USERINTERRUPTCLEAR1_UserInterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTCLEAR1_UserInterruptClear1_SHIFT)) & IRIS_MVPL_USERINTERRUPTCLEAR1_UserInterruptClear1_MASK) /*! @} */ /*! @name USERINTERRUPTSTATUS0 - Interrupt Status register 0 */ /*! @{ */ #define IRIS_MVPL_USERINTERRUPTSTATUS0_UserInterruptStatus0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_USERINTERRUPTSTATUS0_UserInterruptStatus0_SHIFT (0U) /*! UserInterruptStatus0 - Same as InterruptStatus0. */ #define IRIS_MVPL_USERINTERRUPTSTATUS0_UserInterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTSTATUS0_UserInterruptStatus0_SHIFT)) & IRIS_MVPL_USERINTERRUPTSTATUS0_UserInterruptStatus0_MASK) /*! @} */ /*! @name USERINTERRUPTSTATUS1 - Interrupt Status register 1 */ /*! @{ */ #define IRIS_MVPL_USERINTERRUPTSTATUS1_UserInterruptStatus1_MASK (0x1FFFFU) #define IRIS_MVPL_USERINTERRUPTSTATUS1_UserInterruptStatus1_SHIFT (0U) /*! UserInterruptStatus1 - Same as InterruptStatus1. */ #define IRIS_MVPL_USERINTERRUPTSTATUS1_UserInterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTSTATUS1_UserInterruptStatus1_SHIFT)) & IRIS_MVPL_USERINTERRUPTSTATUS1_UserInterruptStatus1_MASK) /*! @} */ /*! @name GENERALPURPOSE - General purpose config memory */ /*! @{ */ #define IRIS_MVPL_GENERALPURPOSE_GeneralPurpose_MASK (0xFFFFFFFFU) #define IRIS_MVPL_GENERALPURPOSE_GeneralPurpose_SHIFT (0U) /*! GeneralPurpose - General purpose config memory entry, does not have any function. */ #define IRIS_MVPL_GENERALPURPOSE_GeneralPurpose(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GENERALPURPOSE_GeneralPurpose_SHIFT)) & IRIS_MVPL_GENERALPURPOSE_GeneralPurpose_MASK) /*! @} */ /*! @name CMDSEQ_HIF - Command input buffer */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_SHIFT (0U) /*! CommandFIFO - Writing an instruction to this field will add it to the command FIFO. Reading always returns 0. */ #define IRIS_MVPL_CMDSEQ_HIF_CommandFIFO(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_SHIFT)) & IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_MASK) /*! @} */ /*! @name CMDSEQ_LOCKUNLOCKHIF - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_SHIFT (0U) /*! LockUnlockHIF - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_MASK) /*! @} */ /*! @name CMDSEQ_LOCKSTATUSHIF - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_MASK (0x1U) #define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_SHIFT (0U) /*! LockStatusHIF - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_MASK) #define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_MASK (0x10U) #define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_SHIFT (4U) /*! PrivilegeStatusHIF - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_MASK) #define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_MASK (0x100U) #define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_SHIFT (8U) /*! FreezeStatusHIF - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_MASK) /*! @} */ /*! @name CMDSEQ_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name CMDSEQ_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name CMDSEQ_BUFFERADDRESS - Command buffer address register */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_MASK (0x1U) #define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_SHIFT (0U) /*! Local - When enabled, a local buffer is used as command FIFO instead of the external one, which * is specified by 'Addr' and 'Size' fields. It has a size of 4 instructions only. */ #define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_SHIFT)) & IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_MASK) #define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_MASK (0xFFFFFFE0U) #define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_SHIFT (5U) /*! Addr - Command buffer base address. Must be 32 byte aligned. */ #define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_SHIFT)) & IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_MASK) /*! @} */ /*! @name CMDSEQ_BUFFERSIZE - Command buffer size register */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_MASK (0xFFF8U) #define IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_SHIFT (3U) /*! Size - Size of command buffer in multiples of 32 byte; a value of 0 is equal to 0x10000 */ #define IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_SHIFT)) & IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_MASK) /*! @} */ /*! @name CMDSEQ_WATERMARKCONTROL - Watermark Control register */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_MASK (0xFFFFU) #define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_SHIFT (0U) /*! LowWM - Low water mark */ #define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_SHIFT)) & IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_MASK) #define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_MASK (0xFFFF0000U) #define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_SHIFT (16U) /*! HighWM - High water mark */ #define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_SHIFT)) & IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_MASK) /*! @} */ /*! @name CMDSEQ_CONTROL - Control register */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_MASK (0x1U) #define IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_SHIFT (0U) /*! ClrAxiw - Clear axiwrite controller by writing a 1 */ #define IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_MASK) #define IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_MASK (0x4U) #define IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_SHIFT (2U) /*! ClrRbuf - Clear read prefetch buffer by writing a 1 */ #define IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_MASK) #define IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_MASK (0x8U) #define IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_SHIFT (3U) /*! ClrCmdBuf - Clear command buffer by writing a 1 */ #define IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_MASK) #define IRIS_MVPL_CMDSEQ_CONTROL_Clear_MASK (0x80000000U) #define IRIS_MVPL_CMDSEQ_CONTROL_Clear_SHIFT (31U) /*! Clear - Clear internal data pipelines and core state by writing a 1 */ #define IRIS_MVPL_CMDSEQ_CONTROL_Clear(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_Clear_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_Clear_MASK) /*! @} */ /*! @name CMDSEQ_STATUS - Status register */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_MASK (0x1FFFFU) #define IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_SHIFT (0U) /*! FIFOSpace - Available space in command FIFO in number of 32-bit words. */ #define IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_MASK) #define IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_MASK (0x1000000U) #define IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_SHIFT (24U) /*! FIFOEmpty - Command FIFO empty flag */ #define IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_MASK) #define IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_MASK (0x2000000U) #define IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_SHIFT (25U) /*! FIFOFull - Command FIFO full flag */ #define IRIS_MVPL_CMDSEQ_STATUS_FIFOFull(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_MASK) #define IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_MASK (0x4000000U) #define IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_SHIFT (26U) /*! FIFOWMState - Water mark state */ #define IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_MASK) #define IRIS_MVPL_CMDSEQ_STATUS_Watchdog_MASK (0x8000000U) #define IRIS_MVPL_CMDSEQ_STATUS_Watchdog_SHIFT (27U) /*! Watchdog - Watchdog expired */ #define IRIS_MVPL_CMDSEQ_STATUS_Watchdog(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_Watchdog_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_Watchdog_MASK) #define IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_MASK (0x10000000U) #define IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_SHIFT (28U) /*! ReadBusy - If this is 1 then the command sequencer AXI read path is not idle. */ #define IRIS_MVPL_CMDSEQ_STATUS_ReadBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_MASK) #define IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_MASK (0x20000000U) #define IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_SHIFT (29U) /*! WriteBusy - If this is 1 then the command sequencer write paths are not idle. */ #define IRIS_MVPL_CMDSEQ_STATUS_WriteBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_MASK) #define IRIS_MVPL_CMDSEQ_STATUS_Idle_MASK (0x40000000U) #define IRIS_MVPL_CMDSEQ_STATUS_Idle_SHIFT (30U) /*! Idle - Command sequencer is in IDLE state */ #define IRIS_MVPL_CMDSEQ_STATUS_Idle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_Idle_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_Idle_MASK) #define IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_MASK (0x80000000U) #define IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_SHIFT (31U) /*! ErrorHalt - Execution stopped after illegal instruction */ #define IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_MASK) /*! @} */ /*! @name CMDSEQ_PREFETCHWINDOWSTART - PrefetchWindowStart register */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_MASK (0xFFFFFFFCU) #define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_SHIFT (2U) /*! PWStart - Start address of prefetch window */ #define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_SHIFT)) & IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_MASK) /*! @} */ /*! @name CMDSEQ_PREFETCHWINDOWEND - PrefetchWindowEnd register */ /*! @{ */ #define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_MASK (0xFFFFFFFCU) #define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_SHIFT (2U) /*! PWEnd - End address of prefetch window */ #define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_SHIFT)) & IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_MASK) /*! @} */ /*! @name SAFETYLOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_SAFETYLOCKUNLOCK_SafetyLockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SAFETYLOCKUNLOCK_SafetyLockUnlock_SHIFT (0U) /*! SafetyLockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_SAFETYLOCKUNLOCK_SafetyLockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SAFETYLOCKUNLOCK_SafetyLockUnlock_SHIFT)) & IRIS_MVPL_SAFETYLOCKUNLOCK_SafetyLockUnlock_MASK) /*! @} */ /*! @name SAFETYLOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyLockStatus_MASK (0x1U) #define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyLockStatus_SHIFT (0U) /*! SafetyLockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyLockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SAFETYLOCKSTATUS_SafetyLockStatus_SHIFT)) & IRIS_MVPL_SAFETYLOCKSTATUS_SafetyLockStatus_MASK) #define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_SHIFT (4U) /*! SafetyPrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyPrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_SHIFT)) & IRIS_MVPL_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_MASK) #define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyFreezeStatus_MASK (0x100U) #define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyFreezeStatus_SHIFT (8U) /*! SafetyFreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyFreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SAFETYLOCKSTATUS_SafetyFreezeStatus_SHIFT)) & IRIS_MVPL_SAFETYLOCKSTATUS_SafetyFreezeStatus_MASK) /*! @} */ /*! @name STORE9_SAFETYMASK - Safety mask for store9 */ /*! @{ */ #define IRIS_MVPL_STORE9_SAFETYMASK_store9_SafetyMask_MASK (0x7FFFFFFFU) #define IRIS_MVPL_STORE9_SAFETYMASK_store9_SafetyMask_SHIFT (0U) /*! store9_SafetyMask - Each bit in this field describes whether the corresponding processing unit * is allowed to be configured in a path leading to this endpoint (store9). 1 = allowed, 0 = * prohibited. */ #define IRIS_MVPL_STORE9_SAFETYMASK_store9_SafetyMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_SAFETYMASK_store9_SafetyMask_SHIFT)) & IRIS_MVPL_STORE9_SAFETYMASK_store9_SafetyMask_MASK) /*! @} */ /*! @name EXTDST0_SAFETYMASK - Safety mask for extdst0 */ /*! @{ */ #define IRIS_MVPL_EXTDST0_SAFETYMASK_extdst0_SafetyMask_MASK (0x7FFFFFFFU) #define IRIS_MVPL_EXTDST0_SAFETYMASK_extdst0_SafetyMask_SHIFT (0U) /*! extdst0_SafetyMask - Each bit in this field describes whether the corresponding processing unit * is allowed to be configured in a path leading to this endpoint (extdst0). 1 = allowed, 0 = * prohibited. */ #define IRIS_MVPL_EXTDST0_SAFETYMASK_extdst0_SafetyMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_SAFETYMASK_extdst0_SafetyMask_SHIFT)) & IRIS_MVPL_EXTDST0_SAFETYMASK_extdst0_SafetyMask_MASK) /*! @} */ /*! @name EXTDST4_SAFETYMASK - Safety mask for extdst4 */ /*! @{ */ #define IRIS_MVPL_EXTDST4_SAFETYMASK_extdst4_SafetyMask_MASK (0x7FFFFFFFU) #define IRIS_MVPL_EXTDST4_SAFETYMASK_extdst4_SafetyMask_SHIFT (0U) /*! extdst4_SafetyMask - Each bit in this field describes whether the corresponding processing unit * is allowed to be configured in a path leading to this endpoint (extdst4). 1 = allowed, 0 = * prohibited. */ #define IRIS_MVPL_EXTDST4_SAFETYMASK_extdst4_SafetyMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_SAFETYMASK_extdst4_SafetyMask_SHIFT)) & IRIS_MVPL_EXTDST4_SAFETYMASK_extdst4_SafetyMask_MASK) /*! @} */ /*! @name EXTDST1_SAFETYMASK - Safety mask for extdst1 */ /*! @{ */ #define IRIS_MVPL_EXTDST1_SAFETYMASK_extdst1_SafetyMask_MASK (0x7FFFFFFFU) #define IRIS_MVPL_EXTDST1_SAFETYMASK_extdst1_SafetyMask_SHIFT (0U) /*! extdst1_SafetyMask - Each bit in this field describes whether the corresponding processing unit * is allowed to be configured in a path leading to this endpoint (extdst1). 1 = allowed, 0 = * prohibited. */ #define IRIS_MVPL_EXTDST1_SAFETYMASK_extdst1_SafetyMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_SAFETYMASK_extdst1_SafetyMask_SHIFT)) & IRIS_MVPL_EXTDST1_SAFETYMASK_extdst1_SafetyMask_MASK) /*! @} */ /*! @name EXTDST5_SAFETYMASK - Safety mask for extdst5 */ /*! @{ */ #define IRIS_MVPL_EXTDST5_SAFETYMASK_extdst5_SafetyMask_MASK (0x7FFFFFFFU) #define IRIS_MVPL_EXTDST5_SAFETYMASK_extdst5_SafetyMask_SHIFT (0U) /*! extdst5_SafetyMask - Each bit in this field describes whether the corresponding processing unit * is allowed to be configured in a path leading to this endpoint (extdst5). 1 = allowed, 0 = * prohibited. */ #define IRIS_MVPL_EXTDST5_SAFETYMASK_extdst5_SafetyMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_SAFETYMASK_extdst5_SafetyMask_SHIFT)) & IRIS_MVPL_EXTDST5_SAFETYMASK_extdst5_SafetyMask_MASK) /*! @} */ /*! @name FETCHDECODE32_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE32_LOCKUNLOCK_fetchdecode_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE32_LOCKUNLOCK_fetchdecode_LockUnlock_SHIFT (0U) /*! fetchdecode_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHDECODE32_LOCKUNLOCK_fetchdecode_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE32_LOCKUNLOCK_fetchdecode_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE32_LOCKUNLOCK_fetchdecode_LockUnlock_MASK) /*! @} */ /*! @name FETCHDECODE32_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode_LockStatus_SHIFT (0U) /*! fetchdecode_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode_LockStatus_MASK) #define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_PrivilegeStatus_SHIFT (4U) /*! fetchdecode9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_FreezeStatus_SHIFT (8U) /*! fetchdecode9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_FreezeStatus_MASK) /*! @} */ /*! @name FETCHDECODE_DYNAMIC - Dynamic pixel engine configuration for fetchdecode9 */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_DYNAMIC_fetchdecode9_src_sel_MASK (0x3FU) #define IRIS_MVPL_FETCHDECODE_DYNAMIC_fetchdecode9_src_sel_SHIFT (0U) /*! fetchdecode9_src_sel - Selection of the source for the src input of the fetchdecode9 module * 0b000000..Unit fetchdecode9 input port src is disabled * 0b000010..Unit fetchdecode9 input port src is connected to output of unit fetchwarp9 * 0b000011..Unit fetchdecode9 input port src is connected to output of unit fetcheco9 */ #define IRIS_MVPL_FETCHDECODE_DYNAMIC_fetchdecode9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DYNAMIC_fetchdecode9_src_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE_DYNAMIC_fetchdecode9_src_sel_MASK) /*! @} */ /*! @name FETCHDECODE_STATUS - Status information for pixel engine configuration of fetchdecode9 */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_STATUS_fetchdecode9_sel_MASK (0x70000U) #define IRIS_MVPL_FETCHDECODE_STATUS_fetchdecode9_sel_SHIFT (16U) /*! fetchdecode9_sel - Status of the connection of the fetchdecode9 module * 0b000..fetchdecode9 module is not used * 0b001..fetchdecode9 module is used from store9 processing path * 0b010..fetchdecode9 module is used from extdst0 processing path * 0b011..fetchdecode9 module is used from extdst4 processing path * 0b100..fetchdecode9 module is used from extdst1 processing path * 0b101..fetchdecode9 module is used from extdst5 processing path */ #define IRIS_MVPL_FETCHDECODE_STATUS_fetchdecode9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATUS_fetchdecode9_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATUS_fetchdecode9_sel_MASK) /*! @} */ /*! @name FETCHWARP64_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP64_LOCKUNLOCK_fetchwarp_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP64_LOCKUNLOCK_fetchwarp_LockUnlock_SHIFT (0U) /*! fetchwarp_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHWARP64_LOCKUNLOCK_fetchwarp_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_LOCKUNLOCK_fetchwarp_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHWARP64_LOCKUNLOCK_fetchwarp_LockUnlock_MASK) /*! @} */ /*! @name FETCHWARP64_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp_LockStatus_SHIFT (0U) /*! fetchwarp_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp_LockStatus_SHIFT)) & IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp_LockStatus_MASK) #define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_PrivilegeStatus_SHIFT (4U) /*! fetchwarp9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_FreezeStatus_SHIFT (8U) /*! fetchwarp9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_FreezeStatus_MASK) /*! @} */ /*! @name FETCHWARP64_DYNAMIC - Dynamic pixel engine configuration for fetchwarp9 */ /*! @{ */ #define IRIS_MVPL_FETCHWARP64_DYNAMIC_fetchwarp9_src_sel_MASK (0x3FU) #define IRIS_MVPL_FETCHWARP64_DYNAMIC_fetchwarp9_src_sel_SHIFT (0U) /*! fetchwarp9_src_sel - Selection of the source for the src input of the fetchwarp9 module * 0b000000..Unit fetchwarp9 input port src is disabled * 0b000011..Unit fetchwarp9 input port src is connected to output of unit fetcheco9 */ #define IRIS_MVPL_FETCHWARP64_DYNAMIC_fetchwarp9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_DYNAMIC_fetchwarp9_src_sel_SHIFT)) & IRIS_MVPL_FETCHWARP64_DYNAMIC_fetchwarp9_src_sel_MASK) /*! @} */ /*! @name FETCHWARP64_STATUS - Status information for pixel engine configuration of fetchwarp9 */ /*! @{ */ #define IRIS_MVPL_FETCHWARP64_STATUS_fetchwarp9_sel_MASK (0x70000U) #define IRIS_MVPL_FETCHWARP64_STATUS_fetchwarp9_sel_SHIFT (16U) /*! fetchwarp9_sel - Status of the connection of the fetchwarp9 module * 0b000..fetchwarp9 module is not used * 0b001..fetchwarp9 module is used from store9 processing path * 0b010..fetchwarp9 module is used from extdst0 processing path * 0b011..fetchwarp9 module is used from extdst4 processing path * 0b100..fetchwarp9 module is used from extdst1 processing path * 0b101..fetchwarp9 module is used from extdst5 processing path */ #define IRIS_MVPL_FETCHWARP64_STATUS_fetchwarp9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_STATUS_fetchwarp9_sel_SHIFT)) & IRIS_MVPL_FETCHWARP64_STATUS_fetchwarp9_sel_MASK) /*! @} */ /*! @name FETCHECO80_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO80_LOCKUNLOCK_fetcheco_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO80_LOCKUNLOCK_fetcheco_LockUnlock_SHIFT (0U) /*! fetcheco_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHECO80_LOCKUNLOCK_fetcheco_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO80_LOCKUNLOCK_fetcheco_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO80_LOCKUNLOCK_fetcheco_LockUnlock_MASK) /*! @} */ /*! @name FETCHECO80_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco_LockStatus_SHIFT (0U) /*! fetcheco_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco_LockStatus_MASK) #define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_PrivilegeStatus_SHIFT (4U) /*! fetcheco9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_FreezeStatus_SHIFT (8U) /*! fetcheco9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_FreezeStatus_MASK) /*! @} */ /*! @name FETCHECO_STATUS - Status information for pixel engine configuration of fetcheco9 */ /*! @{ */ #define IRIS_MVPL_FETCHECO_STATUS_fetcheco9_sel_MASK (0x70000U) #define IRIS_MVPL_FETCHECO_STATUS_fetcheco9_sel_SHIFT (16U) /*! fetcheco9_sel - Status of the connection of the fetcheco9 module * 0b000..fetcheco9 module is not used * 0b001..fetcheco9 module is used from store9 processing path * 0b010..fetcheco9 module is used from extdst0 processing path * 0b011..fetcheco9 module is used from extdst4 processing path * 0b100..fetcheco9 module is used from extdst1 processing path * 0b101..fetcheco9 module is used from extdst5 processing path */ #define IRIS_MVPL_FETCHECO_STATUS_fetcheco9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO_STATUS_fetcheco9_sel_SHIFT)) & IRIS_MVPL_FETCHECO_STATUS_fetcheco9_sel_MASK) /*! @} */ /*! @name ROP_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_ROP_LOCKUNLOCK_rop_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_ROP_LOCKUNLOCK_rop_LockUnlock_SHIFT (0U) /*! rop_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_ROP_LOCKUNLOCK_rop_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_LOCKUNLOCK_rop_LockUnlock_SHIFT)) & IRIS_MVPL_ROP_LOCKUNLOCK_rop_LockUnlock_MASK) /*! @} */ /*! @name ROP_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_ROP_LOCKSTATUS_rop_LockStatus_MASK (0x1U) #define IRIS_MVPL_ROP_LOCKSTATUS_rop_LockStatus_SHIFT (0U) /*! rop_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_ROP_LOCKSTATUS_rop_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_LOCKSTATUS_rop_LockStatus_SHIFT)) & IRIS_MVPL_ROP_LOCKSTATUS_rop_LockStatus_MASK) #define IRIS_MVPL_ROP_LOCKSTATUS_rop9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_ROP_LOCKSTATUS_rop9_PrivilegeStatus_SHIFT (4U) /*! rop9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_ROP_LOCKSTATUS_rop9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_LOCKSTATUS_rop9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_ROP_LOCKSTATUS_rop9_PrivilegeStatus_MASK) #define IRIS_MVPL_ROP_LOCKSTATUS_rop9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_ROP_LOCKSTATUS_rop9_FreezeStatus_SHIFT (8U) /*! rop9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_ROP_LOCKSTATUS_rop9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_LOCKSTATUS_rop9_FreezeStatus_SHIFT)) & IRIS_MVPL_ROP_LOCKSTATUS_rop9_FreezeStatus_MASK) /*! @} */ /*! @name ROP_DYNAMIC - Dynamic pixel engine configuration for rop9 */ /*! @{ */ #define IRIS_MVPL_ROP_DYNAMIC_rop9_prim_sel_MASK (0x3FU) #define IRIS_MVPL_ROP_DYNAMIC_rop9_prim_sel_SHIFT (0U) /*! rop9_prim_sel - Selection of the source for the prim input of the rop9 module * 0b000000..Unit rop9 input port prim is disabled * 0b000001..Unit rop9 input port prim is connected to output of unit fetchdecode9 * 0b000010..Unit rop9 input port prim is connected to output of unit fetchwarp9 */ #define IRIS_MVPL_ROP_DYNAMIC_rop9_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_DYNAMIC_rop9_prim_sel_SHIFT)) & IRIS_MVPL_ROP_DYNAMIC_rop9_prim_sel_MASK) #define IRIS_MVPL_ROP_DYNAMIC_rop9_sec_sel_MASK (0x3F00U) #define IRIS_MVPL_ROP_DYNAMIC_rop9_sec_sel_SHIFT (8U) /*! rop9_sec_sel - Selection of the source for the sec input of the rop9 module * 0b000000..Unit rop9 input port sec is disabled * 0b000011..Unit rop9 input port sec is connected to output of unit fetcheco9 */ #define IRIS_MVPL_ROP_DYNAMIC_rop9_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_DYNAMIC_rop9_sec_sel_SHIFT)) & IRIS_MVPL_ROP_DYNAMIC_rop9_sec_sel_MASK) #define IRIS_MVPL_ROP_DYNAMIC_rop9_tert_sel_MASK (0x3F0000U) #define IRIS_MVPL_ROP_DYNAMIC_rop9_tert_sel_SHIFT (16U) /*! rop9_tert_sel - Selection of the source for the tert input of the rop9 module * 0b000000..Unit rop9 input port tert is disabled * 0b000001..Unit rop9 input port tert is connected to output of unit fetchdecode9 * 0b000010..Unit rop9 input port tert is connected to output of unit fetchwarp9 */ #define IRIS_MVPL_ROP_DYNAMIC_rop9_tert_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_DYNAMIC_rop9_tert_sel_SHIFT)) & IRIS_MVPL_ROP_DYNAMIC_rop9_tert_sel_MASK) #define IRIS_MVPL_ROP_DYNAMIC_rop9_clken_MASK (0x3000000U) #define IRIS_MVPL_ROP_DYNAMIC_rop9_clken_SHIFT (24U) /*! rop9_clken - Enable of rop9 clock (this setting has to be the same for all modules of one * processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for rop9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for rop9 is without gating */ #define IRIS_MVPL_ROP_DYNAMIC_rop9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_DYNAMIC_rop9_clken_SHIFT)) & IRIS_MVPL_ROP_DYNAMIC_rop9_clken_MASK) /*! @} */ /*! @name ROP_STATUS - Status information for pixel engine configuration of rop9 */ /*! @{ */ #define IRIS_MVPL_ROP_STATUS_rop9_sel_MASK (0x70000U) #define IRIS_MVPL_ROP_STATUS_rop9_sel_SHIFT (16U) /*! rop9_sel - Status of the connection of the rop9 module * 0b000..rop9 module is not used * 0b001..rop9 module is used from store9 processing path * 0b010..rop9 module is used from extdst0 processing path * 0b011..rop9 module is used from extdst4 processing path * 0b100..rop9 module is used from extdst1 processing path * 0b101..rop9 module is used from extdst5 processing path */ #define IRIS_MVPL_ROP_STATUS_rop9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_STATUS_rop9_sel_SHIFT)) & IRIS_MVPL_ROP_STATUS_rop9_sel_MASK) /*! @} */ /*! @name CLUT_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CLUT_LOCKUNLOCK_clut_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CLUT_LOCKUNLOCK_clut_LockUnlock_SHIFT (0U) /*! clut_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CLUT_LOCKUNLOCK_clut_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_LOCKUNLOCK_clut_LockUnlock_SHIFT)) & IRIS_MVPL_CLUT_LOCKUNLOCK_clut_LockUnlock_MASK) /*! @} */ /*! @name CLUT_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CLUT_LOCKSTATUS_clut_LockStatus_MASK (0x1U) #define IRIS_MVPL_CLUT_LOCKSTATUS_clut_LockStatus_SHIFT (0U) /*! clut_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CLUT_LOCKSTATUS_clut_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_LOCKSTATUS_clut_LockStatus_SHIFT)) & IRIS_MVPL_CLUT_LOCKSTATUS_clut_LockStatus_MASK) #define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_PrivilegeStatus_SHIFT (4U) /*! clut9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_LOCKSTATUS_clut9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CLUT_LOCKSTATUS_clut9_PrivilegeStatus_MASK) #define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_FreezeStatus_SHIFT (8U) /*! clut9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_LOCKSTATUS_clut9_FreezeStatus_SHIFT)) & IRIS_MVPL_CLUT_LOCKSTATUS_clut9_FreezeStatus_MASK) /*! @} */ /*! @name CLUT_DYNAMIC - Dynamic pixel engine configuration for clut9 */ /*! @{ */ #define IRIS_MVPL_CLUT_DYNAMIC_clut9_src_sel_MASK (0x3FU) #define IRIS_MVPL_CLUT_DYNAMIC_clut9_src_sel_SHIFT (0U) /*! clut9_src_sel - Selection of the source for the src input of the clut9 module * 0b000000..Unit clut9 input port src is disabled * 0b001010..Unit clut9 input port src is connected to output of unit blitblend9 * 0b000100..Unit clut9 input port src is connected to output of unit rop9 */ #define IRIS_MVPL_CLUT_DYNAMIC_clut9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_DYNAMIC_clut9_src_sel_SHIFT)) & IRIS_MVPL_CLUT_DYNAMIC_clut9_src_sel_MASK) /*! @} */ /*! @name CLUT_STATUS - Status information for pixel engine configuration of clut9 */ /*! @{ */ #define IRIS_MVPL_CLUT_STATUS_clut9_sel_MASK (0x70000U) #define IRIS_MVPL_CLUT_STATUS_clut9_sel_SHIFT (16U) /*! clut9_sel - Status of the connection of the clut9 module * 0b000..clut9 module is not used * 0b001..clut9 module is used from store9 processing path * 0b010..clut9 module is used from extdst0 processing path * 0b011..clut9 module is used from extdst4 processing path * 0b100..clut9 module is used from extdst1 processing path * 0b101..clut9 module is used from extdst5 processing path */ #define IRIS_MVPL_CLUT_STATUS_clut9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_STATUS_clut9_sel_SHIFT)) & IRIS_MVPL_CLUT_STATUS_clut9_sel_MASK) /*! @} */ /*! @name MATRIX160_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX160_LOCKUNLOCK_matrix_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX160_LOCKUNLOCK_matrix_LockUnlock_SHIFT (0U) /*! matrix_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_MATRIX160_LOCKUNLOCK_matrix_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX160_LOCKUNLOCK_matrix_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX160_LOCKUNLOCK_matrix_LockUnlock_MASK) /*! @} */ /*! @name MATRIX160_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix_LockStatus_MASK (0x1U) #define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix_LockStatus_SHIFT (0U) /*! matrix_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix_LockStatus_MASK) #define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_PrivilegeStatus_SHIFT (4U) /*! matrix9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_PrivilegeStatus_MASK) #define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_FreezeStatus_SHIFT (8U) /*! matrix9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_FreezeStatus_MASK) /*! @} */ /*! @name MATRIX_DYNAMIC - Dynamic pixel engine configuration for matrix9 */ /*! @{ */ #define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_src_sel_MASK (0x3FU) #define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_src_sel_SHIFT (0U) /*! matrix9_src_sel - Selection of the source for the src input of the matrix9 module * 0b000000..Unit matrix9 input port src is disabled * 0b001010..Unit matrix9 input port src is connected to output of unit blitblend9 * 0b000100..Unit matrix9 input port src is connected to output of unit rop9 * 0b000101..Unit matrix9 input port src is connected to output of unit clut9 */ #define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX_DYNAMIC_matrix9_src_sel_SHIFT)) & IRIS_MVPL_MATRIX_DYNAMIC_matrix9_src_sel_MASK) #define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_clken_MASK (0x3000000U) #define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_clken_SHIFT (24U) /*! matrix9_clken - Enable of matrix9 clock (this setting has to be the same for all modules of one * processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for matrix9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for matrix9 is without gating */ #define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX_DYNAMIC_matrix9_clken_SHIFT)) & IRIS_MVPL_MATRIX_DYNAMIC_matrix9_clken_MASK) /*! @} */ /*! @name MATRIX_STATUS - Status information for pixel engine configuration of matrix9 */ /*! @{ */ #define IRIS_MVPL_MATRIX_STATUS_matrix9_sel_MASK (0x70000U) #define IRIS_MVPL_MATRIX_STATUS_matrix9_sel_SHIFT (16U) /*! matrix9_sel - Status of the connection of the matrix9 module * 0b000..matrix9 module is not used * 0b001..matrix9 module is used from store9 processing path * 0b010..matrix9 module is used from extdst0 processing path * 0b011..matrix9 module is used from extdst4 processing path * 0b100..matrix9 module is used from extdst1 processing path * 0b101..matrix9 module is used from extdst5 processing path */ #define IRIS_MVPL_MATRIX_STATUS_matrix9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX_STATUS_matrix9_sel_SHIFT)) & IRIS_MVPL_MATRIX_STATUS_matrix9_sel_MASK) /*! @} */ /*! @name HSCALER192_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER192_LOCKUNLOCK_hscaler_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_HSCALER192_LOCKUNLOCK_hscaler_LockUnlock_SHIFT (0U) /*! hscaler_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_HSCALER192_LOCKUNLOCK_hscaler_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER192_LOCKUNLOCK_hscaler_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER192_LOCKUNLOCK_hscaler_LockUnlock_MASK) /*! @} */ /*! @name HSCALER192_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler_LockStatus_MASK (0x1U) #define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler_LockStatus_SHIFT (0U) /*! hscaler_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler_LockStatus_MASK) #define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_PrivilegeStatus_SHIFT (4U) /*! hscaler9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_PrivilegeStatus_MASK) #define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_FreezeStatus_SHIFT (8U) /*! hscaler9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_FreezeStatus_MASK) /*! @} */ /*! @name HSCALER_DYNAMIC - Dynamic pixel engine configuration for hscaler9 */ /*! @{ */ #define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_src_sel_MASK (0x3FU) #define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_src_sel_SHIFT (0U) /*! hscaler9_src_sel - Selection of the source for the src input of the hscaler9 module * 0b000000..Unit hscaler9 input port src is disabled * 0b000110..Unit hscaler9 input port src is connected to output of unit matrix9 * 0b001000..Unit hscaler9 input port src is connected to output of unit vscaler9 * 0b001001..Unit hscaler9 input port src is connected to output of unit filter9 */ #define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_src_sel_SHIFT)) & IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_src_sel_MASK) #define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_clken_MASK (0x3000000U) #define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_clken_SHIFT (24U) /*! hscaler9_clken - Enable of hscaler9 clock (this setting has to be the same for all modules of * one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for hscaler9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for hscaler9 is without gating */ #define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_clken_SHIFT)) & IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_clken_MASK) /*! @} */ /*! @name HSCALER_STATUS - Status information for pixel engine configuration of hscaler9 */ /*! @{ */ #define IRIS_MVPL_HSCALER_STATUS_hscaler9_sel_MASK (0x70000U) #define IRIS_MVPL_HSCALER_STATUS_hscaler9_sel_SHIFT (16U) /*! hscaler9_sel - Status of the connection of the hscaler9 module * 0b000..hscaler9 module is not used * 0b001..hscaler9 module is used from store9 processing path * 0b010..hscaler9 module is used from extdst0 processing path * 0b011..hscaler9 module is used from extdst4 processing path * 0b100..hscaler9 module is used from extdst1 processing path * 0b101..hscaler9 module is used from extdst5 processing path */ #define IRIS_MVPL_HSCALER_STATUS_hscaler9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER_STATUS_hscaler9_sel_SHIFT)) & IRIS_MVPL_HSCALER_STATUS_hscaler9_sel_MASK) /*! @} */ /*! @name VSCALER224_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER224_LOCKUNLOCK_vscaler_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_VSCALER224_LOCKUNLOCK_vscaler_LockUnlock_SHIFT (0U) /*! vscaler_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_VSCALER224_LOCKUNLOCK_vscaler_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER224_LOCKUNLOCK_vscaler_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER224_LOCKUNLOCK_vscaler_LockUnlock_MASK) /*! @} */ /*! @name VSCALER224_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler_LockStatus_MASK (0x1U) #define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler_LockStatus_SHIFT (0U) /*! vscaler_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler_LockStatus_MASK) #define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_PrivilegeStatus_SHIFT (4U) /*! vscaler9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_PrivilegeStatus_MASK) #define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_FreezeStatus_SHIFT (8U) /*! vscaler9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_FreezeStatus_MASK) /*! @} */ /*! @name VSCALER_DYNAMIC - Dynamic pixel engine configuration for vscaler9 */ /*! @{ */ #define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_src_sel_MASK (0x3FU) #define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_src_sel_SHIFT (0U) /*! vscaler9_src_sel - Selection of the source for the src input of the vscaler9 module * 0b000000..Unit vscaler9 input port src is disabled * 0b000110..Unit vscaler9 input port src is connected to output of unit matrix9 * 0b000111..Unit vscaler9 input port src is connected to output of unit hscaler9 */ #define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_src_sel_SHIFT)) & IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_src_sel_MASK) #define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_clken_MASK (0x3000000U) #define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_clken_SHIFT (24U) /*! vscaler9_clken - Enable of vscaler9 clock (this setting has to be the same for all modules of * one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for vscaler9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for vscaler9 is without gating */ #define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_clken_SHIFT)) & IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_clken_MASK) /*! @} */ /*! @name VSCALER_STATUS - Status information for pixel engine configuration of vscaler9 */ /*! @{ */ #define IRIS_MVPL_VSCALER_STATUS_vscaler9_sel_MASK (0x70000U) #define IRIS_MVPL_VSCALER_STATUS_vscaler9_sel_SHIFT (16U) /*! vscaler9_sel - Status of the connection of the vscaler9 module * 0b000..vscaler9 module is not used * 0b001..vscaler9 module is used from store9 processing path * 0b010..vscaler9 module is used from extdst0 processing path * 0b011..vscaler9 module is used from extdst4 processing path * 0b100..vscaler9 module is used from extdst1 processing path * 0b101..vscaler9 module is used from extdst5 processing path */ #define IRIS_MVPL_VSCALER_STATUS_vscaler9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER_STATUS_vscaler9_sel_SHIFT)) & IRIS_MVPL_VSCALER_STATUS_vscaler9_sel_MASK) /*! @} */ /*! @name FILTER_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FILTER_LOCKUNLOCK_filter_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FILTER_LOCKUNLOCK_filter_LockUnlock_SHIFT (0U) /*! filter_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FILTER_LOCKUNLOCK_filter_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_LOCKUNLOCK_filter_LockUnlock_SHIFT)) & IRIS_MVPL_FILTER_LOCKUNLOCK_filter_LockUnlock_MASK) /*! @} */ /*! @name FILTER_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FILTER_LOCKSTATUS_filter_LockStatus_MASK (0x1U) #define IRIS_MVPL_FILTER_LOCKSTATUS_filter_LockStatus_SHIFT (0U) /*! filter_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FILTER_LOCKSTATUS_filter_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_LOCKSTATUS_filter_LockStatus_SHIFT)) & IRIS_MVPL_FILTER_LOCKSTATUS_filter_LockStatus_MASK) #define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_PrivilegeStatus_SHIFT (4U) /*! filter9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_LOCKSTATUS_filter9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FILTER_LOCKSTATUS_filter9_PrivilegeStatus_MASK) #define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_FreezeStatus_SHIFT (8U) /*! filter9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_LOCKSTATUS_filter9_FreezeStatus_SHIFT)) & IRIS_MVPL_FILTER_LOCKSTATUS_filter9_FreezeStatus_MASK) /*! @} */ /*! @name FILTER_DYNAMIC - Dynamic pixel engine configuration for filter9 */ /*! @{ */ #define IRIS_MVPL_FILTER_DYNAMIC_filter9_src_sel_MASK (0x3FU) #define IRIS_MVPL_FILTER_DYNAMIC_filter9_src_sel_SHIFT (0U) /*! filter9_src_sel - Selection of the source for the src input of the filter9 module * 0b000000..Unit filter9 input port src is disabled * 0b000110..Unit filter9 input port src is connected to output of unit matrix9 * 0b000111..Unit filter9 input port src is connected to output of unit hscaler9 */ #define IRIS_MVPL_FILTER_DYNAMIC_filter9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_DYNAMIC_filter9_src_sel_SHIFT)) & IRIS_MVPL_FILTER_DYNAMIC_filter9_src_sel_MASK) #define IRIS_MVPL_FILTER_DYNAMIC_filter9_clken_MASK (0x3000000U) #define IRIS_MVPL_FILTER_DYNAMIC_filter9_clken_SHIFT (24U) /*! filter9_clken - Enable of filter9 clock (this setting has to be the same for all modules of one * processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for filter9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for filter9 is without gating */ #define IRIS_MVPL_FILTER_DYNAMIC_filter9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_DYNAMIC_filter9_clken_SHIFT)) & IRIS_MVPL_FILTER_DYNAMIC_filter9_clken_MASK) /*! @} */ /*! @name FILTER_STATUS - Status information for pixel engine configuration of filter9 */ /*! @{ */ #define IRIS_MVPL_FILTER_STATUS_filter9_sel_MASK (0x70000U) #define IRIS_MVPL_FILTER_STATUS_filter9_sel_SHIFT (16U) /*! filter9_sel - Status of the connection of the filter9 module * 0b000..filter9 module is not used * 0b001..filter9 module is used from store9 processing path * 0b010..filter9 module is used from extdst0 processing path * 0b011..filter9 module is used from extdst4 processing path * 0b100..filter9 module is used from extdst1 processing path * 0b101..filter9 module is used from extdst5 processing path */ #define IRIS_MVPL_FILTER_STATUS_filter9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_STATUS_filter9_sel_SHIFT)) & IRIS_MVPL_FILTER_STATUS_filter9_sel_MASK) /*! @} */ /*! @name BLITBLEND_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_BLITBLEND_LOCKUNLOCK_blitblend_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_BLITBLEND_LOCKUNLOCK_blitblend_LockUnlock_SHIFT (0U) /*! blitblend_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_BLITBLEND_LOCKUNLOCK_blitblend_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_LOCKUNLOCK_blitblend_LockUnlock_SHIFT)) & IRIS_MVPL_BLITBLEND_LOCKUNLOCK_blitblend_LockUnlock_MASK) /*! @} */ /*! @name BLITBLEND_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend_LockStatus_MASK (0x1U) #define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend_LockStatus_SHIFT (0U) /*! blitblend_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend_LockStatus_SHIFT)) & IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend_LockStatus_MASK) #define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_PrivilegeStatus_SHIFT (4U) /*! blitblend9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_PrivilegeStatus_MASK) #define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_FreezeStatus_SHIFT (8U) /*! blitblend9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_FreezeStatus_SHIFT)) & IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_FreezeStatus_MASK) /*! @} */ /*! @name BLITBLEND_DYNAMIC - Dynamic pixel engine configuration for blitblend9 */ /*! @{ */ #define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_prim_sel_MASK (0x3FU) #define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_prim_sel_SHIFT (0U) /*! blitblend9_prim_sel - Selection of the source for the prim input of the blitblend9 module * 0b000000..Unit blitblend9 input port prim is disabled * 0b000100..Unit blitblend9 input port prim is connected to output of unit rop9 * 0b000111..Unit blitblend9 input port prim is connected to output of unit hscaler9 * 0b001000..Unit blitblend9 input port prim is connected to output of unit vscaler9 * 0b001001..Unit blitblend9 input port prim is connected to output of unit filter9 */ #define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_prim_sel_SHIFT)) & IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_prim_sel_MASK) #define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_sec_sel_MASK (0x3F00U) #define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_sec_sel_SHIFT (8U) /*! blitblend9_sec_sel - Selection of the source for the sec input of the blitblend9 module * 0b000000..Unit blitblend9 input port sec is disabled * 0b000001..Unit blitblend9 input port sec is connected to output of unit fetchdecode9 * 0b000010..Unit blitblend9 input port sec is connected to output of unit fetchwarp9 */ #define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_sec_sel_SHIFT)) & IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_sec_sel_MASK) #define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_clken_MASK (0x3000000U) #define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_clken_SHIFT (24U) /*! blitblend9_clken - Enable of blitblend9 clock (this setting has to be the same for all modules * of one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for blitblend9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for blitblend9 is without gating */ #define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_clken_SHIFT)) & IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_clken_MASK) /*! @} */ /*! @name BLITBLEND_STATUS - Status information for pixel engine configuration of blitblend9 */ /*! @{ */ #define IRIS_MVPL_BLITBLEND_STATUS_blitblend9_sel_MASK (0x70000U) #define IRIS_MVPL_BLITBLEND_STATUS_blitblend9_sel_SHIFT (16U) /*! blitblend9_sel - Status of the connection of the blitblend9 module * 0b000..blitblend9 module is not used * 0b001..blitblend9 module is used from store9 processing path * 0b010..blitblend9 module is used from extdst0 processing path * 0b011..blitblend9 module is used from extdst4 processing path * 0b100..blitblend9 module is used from extdst1 processing path * 0b101..blitblend9 module is used from extdst5 processing path */ #define IRIS_MVPL_BLITBLEND_STATUS_blitblend9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_STATUS_blitblend9_sel_SHIFT)) & IRIS_MVPL_BLITBLEND_STATUS_blitblend9_sel_MASK) /*! @} */ /*! @name STORE_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_STORE_LOCKUNLOCK_store_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_STORE_LOCKUNLOCK_store_LockUnlock_SHIFT (0U) /*! store_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_STORE_LOCKUNLOCK_store_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_LOCKUNLOCK_store_LockUnlock_SHIFT)) & IRIS_MVPL_STORE_LOCKUNLOCK_store_LockUnlock_MASK) /*! @} */ /*! @name STORE_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_STORE_LOCKSTATUS_store_LockStatus_MASK (0x1U) #define IRIS_MVPL_STORE_LOCKSTATUS_store_LockStatus_SHIFT (0U) /*! store_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_STORE_LOCKSTATUS_store_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_LOCKSTATUS_store_LockStatus_SHIFT)) & IRIS_MVPL_STORE_LOCKSTATUS_store_LockStatus_MASK) #define IRIS_MVPL_STORE_LOCKSTATUS_store9_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_STORE_LOCKSTATUS_store9_PrivilegeStatus_SHIFT (4U) /*! store9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_STORE_LOCKSTATUS_store9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_LOCKSTATUS_store9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_STORE_LOCKSTATUS_store9_PrivilegeStatus_MASK) #define IRIS_MVPL_STORE_LOCKSTATUS_store9_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_STORE_LOCKSTATUS_store9_FreezeStatus_SHIFT (8U) /*! store9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_STORE_LOCKSTATUS_store9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_LOCKSTATUS_store9_FreezeStatus_SHIFT)) & IRIS_MVPL_STORE_LOCKSTATUS_store9_FreezeStatus_MASK) /*! @} */ /*! @name STORE9_STATIC - Static pixel engine configuration for store9 */ /*! @{ */ #define IRIS_MVPL_STORE9_STATIC_store9_ShdEn_MASK (0x1U) #define IRIS_MVPL_STORE9_STATIC_store9_ShdEn_SHIFT (0U) /*! store9_ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for * pixelbus configuration of pipeline with endpoint store9. */ #define IRIS_MVPL_STORE9_STATIC_store9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATIC_store9_ShdEn_SHIFT)) & IRIS_MVPL_STORE9_STATIC_store9_ShdEn_MASK) #define IRIS_MVPL_STORE9_STATIC_store9_powerdown_MASK (0x10U) #define IRIS_MVPL_STORE9_STATIC_store9_powerdown_SHIFT (4U) /*! store9_powerdown - Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the store9 endpoint. */ #define IRIS_MVPL_STORE9_STATIC_store9_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATIC_store9_powerdown_SHIFT)) & IRIS_MVPL_STORE9_STATIC_store9_powerdown_MASK) #define IRIS_MVPL_STORE9_STATIC_store9_Sync_Mode_MASK (0x100U) #define IRIS_MVPL_STORE9_STATIC_store9_Sync_Mode_SHIFT (8U) /*! store9_Sync_Mode - Synchronization mode for store9 pipeline endpoint synchronizer * 0b0..Reconfig pipeline after explicit trigger * 0b1..Reconfig pipeline after every kick when idle */ #define IRIS_MVPL_STORE9_STATIC_store9_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATIC_store9_Sync_Mode_SHIFT)) & IRIS_MVPL_STORE9_STATIC_store9_Sync_Mode_MASK) #define IRIS_MVPL_STORE9_STATIC_store9_SW_Reset_MASK (0x800U) #define IRIS_MVPL_STORE9_STATIC_store9_SW_Reset_SHIFT (11U) /*! store9_SW_Reset - Software reset for store9 synchronizer, for debug purposes only * 0b0..Normal Operation * 0b1..Software Reset */ #define IRIS_MVPL_STORE9_STATIC_store9_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATIC_store9_SW_Reset_SHIFT)) & IRIS_MVPL_STORE9_STATIC_store9_SW_Reset_MASK) #define IRIS_MVPL_STORE9_STATIC_store9_div_MASK (0xFF0000U) #define IRIS_MVPL_STORE9_STATIC_store9_div_SHIFT (16U) /*! store9_div - store9 clock dividing factor (ratio is register_value/128, values above 128 are * reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled * submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets * the clock at full speed. */ #define IRIS_MVPL_STORE9_STATIC_store9_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATIC_store9_div_SHIFT)) & IRIS_MVPL_STORE9_STATIC_store9_div_MASK) /*! @} */ /*! @name STORE_DYNAMIC - Dynamic pixel engine configuration for store9 */ /*! @{ */ #define IRIS_MVPL_STORE_DYNAMIC_store9_src_sel_MASK (0x3FU) #define IRIS_MVPL_STORE_DYNAMIC_store9_src_sel_SHIFT (0U) /*! store9_src_sel - Selection of the source for the src input of the store9 module * 0b000000..Unit store9 input port src is disabled * 0b000001..Unit store9 input port src is connected to output of unit fetchdecode9 * 0b001010..Unit store9 input port src is connected to output of unit blitblend9 * 0b000010..Unit store9 input port src is connected to output of unit fetchwarp9 * 0b000111..Unit store9 input port src is connected to output of unit hscaler9 * 0b001000..Unit store9 input port src is connected to output of unit vscaler9 * 0b001001..Unit store9 input port src is connected to output of unit filter9 */ #define IRIS_MVPL_STORE_DYNAMIC_store9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_DYNAMIC_store9_src_sel_SHIFT)) & IRIS_MVPL_STORE_DYNAMIC_store9_src_sel_MASK) /*! @} */ /*! @name STORE9_REQUEST - ShadowLoadRequest register for endpoint store9 */ /*! @{ */ #define IRIS_MVPL_STORE9_REQUEST_store9_sel_ShdLdReq_MASK (0x1U) #define IRIS_MVPL_STORE9_REQUEST_store9_sel_ShdLdReq_SHIFT (0U) /*! store9_sel_ShdLdReq - Shadow load request flag for destination store9. */ #define IRIS_MVPL_STORE9_REQUEST_store9_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_REQUEST_store9_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_STORE9_REQUEST_store9_sel_ShdLdReq_MASK) #define IRIS_MVPL_STORE9_REQUEST_store9_ShdLdReq_MASK (0x7FFEU) #define IRIS_MVPL_STORE9_REQUEST_store9_ShdLdReq_SHIFT (1U) /*! store9_ShdLdReq - Vector of shadow load request flag of all sources for destination store9. * Setting a bit has no effect if the source is currently in a different pipeline than the one of * destination store9. */ #define IRIS_MVPL_STORE9_REQUEST_store9_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_REQUEST_store9_ShdLdReq_SHIFT)) & IRIS_MVPL_STORE9_REQUEST_store9_ShdLdReq_MASK) /*! @} */ /*! @name STORE9_TRIGGER - Trigger bits for pixel engine configuration of store9 */ /*! @{ */ #define IRIS_MVPL_STORE9_TRIGGER_store9_Sync_Trigger_MASK (0x1U) #define IRIS_MVPL_STORE9_TRIGGER_store9_Sync_Trigger_SHIFT (0U) /*! store9_Sync_Trigger - Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint store9 */ #define IRIS_MVPL_STORE9_TRIGGER_store9_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_TRIGGER_store9_Sync_Trigger_SHIFT)) & IRIS_MVPL_STORE9_TRIGGER_store9_Sync_Trigger_MASK) #define IRIS_MVPL_STORE9_TRIGGER_store9_trigger_sequence_complete_MASK (0x10U) #define IRIS_MVPL_STORE9_TRIGGER_store9_trigger_sequence_complete_SHIFT (4U) /*! store9_trigger_sequence_complete - By writing a '1' to this register field, you can trigger the * store9 sequence complete interrupt that will occur as soon as the pipeline with the endpoint * store9 is empty. This interrupt will also occur if the pipeline is already empty when this * field is written. The interrupt will not occur if this field is not written. The interrupt will * occur exactly as often as this field is written, assuming that this field is not written again * until the interrupt has occured after a previous trigger. */ #define IRIS_MVPL_STORE9_TRIGGER_store9_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_TRIGGER_store9_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_STORE9_TRIGGER_store9_trigger_sequence_complete_MASK) /*! @} */ /*! @name STORE_STATUS - Status information for pixel engine configuration of store9 */ /*! @{ */ #define IRIS_MVPL_STORE_STATUS_store9_pipeline_status_MASK (0x3U) #define IRIS_MVPL_STORE_STATUS_store9_pipeline_status_SHIFT (0U) /*! store9_pipeline_status - Status of pipeline with endpoint store9 * 0b00..Pipeline with endpoint store9 is empty * 0b01..Pipeline with endpoint store9 is currently processing one operation * 0b10..Pipeline with endpoint store9 is currently processing one operation with a second one already kicked to be processed afterwards * 0b11..reserved */ #define IRIS_MVPL_STORE_STATUS_store9_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_STATUS_store9_pipeline_status_SHIFT)) & IRIS_MVPL_STORE_STATUS_store9_pipeline_status_MASK) #define IRIS_MVPL_STORE_STATUS_store9_sync_busy_MASK (0x100U) #define IRIS_MVPL_STORE_STATUS_store9_sync_busy_SHIFT (8U) /*! store9_sync_busy - Synchronization busy status of store9 endpoint * 0b0..store9 synchronizer is idle * 0b1..store9 synchronizer is busy */ #define IRIS_MVPL_STORE_STATUS_store9_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_STATUS_store9_sync_busy_SHIFT)) & IRIS_MVPL_STORE_STATUS_store9_sync_busy_MASK) /*! @} */ /*! @name CONSTFRAME352_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME352_LOCKUNLOCK_constframe0_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CONSTFRAME352_LOCKUNLOCK_constframe0_LockUnlock_SHIFT (0U) /*! constframe0_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CONSTFRAME352_LOCKUNLOCK_constframe0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME352_LOCKUNLOCK_constframe0_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME352_LOCKUNLOCK_constframe0_LockUnlock_MASK) /*! @} */ /*! @name CONSTFRAME352_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_LockStatus_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_LockStatus_SHIFT (0U) /*! constframe0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_LockStatus_MASK) #define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_PrivilegeStatus_SHIFT (4U) /*! constframe0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_PrivilegeStatus_MASK) #define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_FreezeStatus_SHIFT (8U) /*! constframe0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_FreezeStatus_MASK) /*! @} */ /*! @name CONSTFRAME352_STATUS - Status information for pixel engine configuration of constframe0 */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME352_STATUS_constframe0_sel_MASK (0x70000U) #define IRIS_MVPL_CONSTFRAME352_STATUS_constframe0_sel_SHIFT (16U) /*! constframe0_sel - Status of the connection of the constframe0 module * 0b000..constframe0 module is not used * 0b001..constframe0 module is used from store9 processing path * 0b010..constframe0 module is used from extdst0 processing path * 0b011..constframe0 module is used from extdst4 processing path * 0b100..constframe0 module is used from extdst1 processing path * 0b101..constframe0 module is used from extdst5 processing path */ #define IRIS_MVPL_CONSTFRAME352_STATUS_constframe0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME352_STATUS_constframe0_sel_SHIFT)) & IRIS_MVPL_CONSTFRAME352_STATUS_constframe0_sel_MASK) /*! @} */ /*! @name EXTDST384_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST384_LOCKUNLOCK_extdst0_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST384_LOCKUNLOCK_extdst0_LockUnlock_SHIFT (0U) /*! extdst0_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_EXTDST384_LOCKUNLOCK_extdst0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_LOCKUNLOCK_extdst0_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST384_LOCKUNLOCK_extdst0_LockUnlock_MASK) /*! @} */ /*! @name EXTDST384_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_LockStatus_MASK (0x1U) #define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_LockStatus_SHIFT (0U) /*! extdst0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_LockStatus_MASK) #define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_PrivilegeStatus_SHIFT (4U) /*! extdst0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_PrivilegeStatus_MASK) #define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_FreezeStatus_SHIFT (8U) /*! extdst0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_FreezeStatus_MASK) /*! @} */ /*! @name EXTDST384_STATIC - Static pixel engine configuration for extdst0 */ /*! @{ */ #define IRIS_MVPL_EXTDST384_STATIC_extdst0_ShdEn_MASK (0x1U) #define IRIS_MVPL_EXTDST384_STATIC_extdst0_ShdEn_SHIFT (0U) /*! extdst0_ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for * pixelbus configuration of pipeline with endpoint extdst0. */ #define IRIS_MVPL_EXTDST384_STATIC_extdst0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATIC_extdst0_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST384_STATIC_extdst0_ShdEn_MASK) #define IRIS_MVPL_EXTDST384_STATIC_extdst0_powerdown_MASK (0x10U) #define IRIS_MVPL_EXTDST384_STATIC_extdst0_powerdown_SHIFT (4U) /*! extdst0_powerdown - Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst0 endpoint. */ #define IRIS_MVPL_EXTDST384_STATIC_extdst0_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATIC_extdst0_powerdown_SHIFT)) & IRIS_MVPL_EXTDST384_STATIC_extdst0_powerdown_MASK) #define IRIS_MVPL_EXTDST384_STATIC_extdst0_Sync_Mode_MASK (0x100U) #define IRIS_MVPL_EXTDST384_STATIC_extdst0_Sync_Mode_SHIFT (8U) /*! extdst0_Sync_Mode - Synchronization mode for extdst0 pipeline endpoint synchronizer * 0b0..Reconfig pipeline after explicit trigger * 0b1..Reconfig pipeline after every kick when idle */ #define IRIS_MVPL_EXTDST384_STATIC_extdst0_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATIC_extdst0_Sync_Mode_SHIFT)) & IRIS_MVPL_EXTDST384_STATIC_extdst0_Sync_Mode_MASK) #define IRIS_MVPL_EXTDST384_STATIC_extdst0_SW_Reset_MASK (0x800U) #define IRIS_MVPL_EXTDST384_STATIC_extdst0_SW_Reset_SHIFT (11U) /*! extdst0_SW_Reset - Software reset for extdst0 synchronizer, for debug purposes only * 0b0..Normal Operation * 0b1..Software Reset */ #define IRIS_MVPL_EXTDST384_STATIC_extdst0_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATIC_extdst0_SW_Reset_SHIFT)) & IRIS_MVPL_EXTDST384_STATIC_extdst0_SW_Reset_MASK) #define IRIS_MVPL_EXTDST384_STATIC_extdst0_div_MASK (0xFF0000U) #define IRIS_MVPL_EXTDST384_STATIC_extdst0_div_SHIFT (16U) /*! extdst0_div - extdst0 clock dividing factor (ratio is register_value/128, values above 128 are * reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled * submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets * the clock at full speed. */ #define IRIS_MVPL_EXTDST384_STATIC_extdst0_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATIC_extdst0_div_SHIFT)) & IRIS_MVPL_EXTDST384_STATIC_extdst0_div_MASK) /*! @} */ /*! @name EXTDST384_DYNAMIC - Dynamic pixel engine configuration for extdst0 */ /*! @{ */ #define IRIS_MVPL_EXTDST384_DYNAMIC_extdst0_src_sel_MASK (0x3FU) #define IRIS_MVPL_EXTDST384_DYNAMIC_extdst0_src_sel_SHIFT (0U) /*! extdst0_src_sel - Selection of the source for the src input of the extdst0 module * 0b000000..Unit extdst0 input port src is disabled * 0b001010..Unit extdst0 input port src is connected to output of unit blitblend9 * 0b001100..Unit extdst0 input port src is connected to output of unit constframe0 * 0b001110..Unit extdst0 input port src is connected to output of unit constframe4 * 0b000000..Unit extdst0 input port src is connected to output of unit constframe1 * 0b010010..Unit extdst0 input port src is connected to output of unit constframe5 * 0b011011..Unit extdst0 input port src is connected to output of unit matrix4 * 0b011100..Unit extdst0 input port src is connected to output of unit hscaler4 * 0b011101..Unit extdst0 input port src is connected to output of unit vscaler4 * 0b011110..Unit extdst0 input port src is connected to output of unit matrix5 * 0b011111..Unit extdst0 input port src is connected to output of unit hscaler5 * 0b100000..Unit extdst0 input port src is connected to output of unit vscaler5 * 0b100001..Unit extdst0 input port src is connected to output of unit layerblend0 * 0b100010..Unit extdst0 input port src is connected to output of unit layerblend1 * 0b100011..Unit extdst0 input port src is connected to output of unit layerblend2 * 0b100100..Unit extdst0 input port src is connected to output of unit layerblend3 */ #define IRIS_MVPL_EXTDST384_DYNAMIC_extdst0_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_DYNAMIC_extdst0_src_sel_SHIFT)) & IRIS_MVPL_EXTDST384_DYNAMIC_extdst0_src_sel_MASK) /*! @} */ /*! @name EXTDST384_REQUEST - ShadowLoadRequest register for endpoint extdst0 */ /*! @{ */ #define IRIS_MVPL_EXTDST384_REQUEST_extdst0_sel_ShdLdReq_MASK (0x1U) #define IRIS_MVPL_EXTDST384_REQUEST_extdst0_sel_ShdLdReq_SHIFT (0U) /*! extdst0_sel_ShdLdReq - Shadow load request flag for destination extdst0. */ #define IRIS_MVPL_EXTDST384_REQUEST_extdst0_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_REQUEST_extdst0_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST384_REQUEST_extdst0_sel_ShdLdReq_MASK) #define IRIS_MVPL_EXTDST384_REQUEST_extdst0_ShdLdReq_MASK (0x7FFEU) #define IRIS_MVPL_EXTDST384_REQUEST_extdst0_ShdLdReq_SHIFT (1U) /*! extdst0_ShdLdReq - Vector of shadow load request flag of all sources for destination extdst0. * Setting a bit has no effect if the source is currently in a different pipeline than the one of * destination extdst0. */ #define IRIS_MVPL_EXTDST384_REQUEST_extdst0_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_REQUEST_extdst0_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST384_REQUEST_extdst0_ShdLdReq_MASK) /*! @} */ /*! @name EXTDST384_TRIGGER - Trigger bits for pixel engine configuration of extdst0 */ /*! @{ */ #define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_Sync_Trigger_MASK (0x1U) #define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_Sync_Trigger_SHIFT (0U) /*! extdst0_Sync_Trigger - Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst0 */ #define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_TRIGGER_extdst0_Sync_Trigger_SHIFT)) & IRIS_MVPL_EXTDST384_TRIGGER_extdst0_Sync_Trigger_MASK) #define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_trigger_sequence_complete_MASK (0x10U) #define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_trigger_sequence_complete_SHIFT (4U) /*! extdst0_trigger_sequence_complete - By writing a '1' to this register field, you can trigger the * extdst0 sequence complete interrupt that will occur as soon as the pipeline with the endpoint * extdst0 is empty. This interrupt will also occur if the pipeline is already empty when this * field is written. The interrupt will not occur if this field is not written. The interrupt will * occur exactly as often as this field is written, assuming that this field is not written * again until the interrupt has occured after a previous trigger. */ #define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_TRIGGER_extdst0_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_EXTDST384_TRIGGER_extdst0_trigger_sequence_complete_MASK) /*! @} */ /*! @name EXTDST384_STATUS - Status information for pixel engine configuration of extdst0 */ /*! @{ */ #define IRIS_MVPL_EXTDST384_STATUS_extdst0_pipeline_status_MASK (0x3U) #define IRIS_MVPL_EXTDST384_STATUS_extdst0_pipeline_status_SHIFT (0U) /*! extdst0_pipeline_status - Status of pipeline with endpoint extdst0 * 0b00..Pipeline with endpoint extdst0 is empty * 0b01..Pipeline with endpoint extdst0 is currently processing one operation * 0b10..Pipeline with endpoint extdst0 is currently processing one operation with a second one already kicked to be processed afterwards * 0b11..reserved */ #define IRIS_MVPL_EXTDST384_STATUS_extdst0_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATUS_extdst0_pipeline_status_SHIFT)) & IRIS_MVPL_EXTDST384_STATUS_extdst0_pipeline_status_MASK) #define IRIS_MVPL_EXTDST384_STATUS_extdst0_sync_busy_MASK (0x100U) #define IRIS_MVPL_EXTDST384_STATUS_extdst0_sync_busy_SHIFT (8U) /*! extdst0_sync_busy - Synchronization busy status of extdst0 endpoint * 0b0..extdst0 synchronizer is idle * 0b1..extdst0 synchronizer is busy */ #define IRIS_MVPL_EXTDST384_STATUS_extdst0_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATUS_extdst0_sync_busy_SHIFT)) & IRIS_MVPL_EXTDST384_STATUS_extdst0_sync_busy_MASK) /*! @} */ /*! @name CONSTFRAME416_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME416_LOCKUNLOCK_constframe4_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CONSTFRAME416_LOCKUNLOCK_constframe4_LockUnlock_SHIFT (0U) /*! constframe4_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CONSTFRAME416_LOCKUNLOCK_constframe4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME416_LOCKUNLOCK_constframe4_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME416_LOCKUNLOCK_constframe4_LockUnlock_MASK) /*! @} */ /*! @name CONSTFRAME416_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_LockStatus_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_LockStatus_SHIFT (0U) /*! constframe4_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_LockStatus_MASK) #define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_PrivilegeStatus_SHIFT (4U) /*! constframe4_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_PrivilegeStatus_MASK) #define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_FreezeStatus_SHIFT (8U) /*! constframe4_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_FreezeStatus_MASK) /*! @} */ /*! @name CONSTFRAME416_STATUS - Status information for pixel engine configuration of constframe4 */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME416_STATUS_constframe4_sel_MASK (0x70000U) #define IRIS_MVPL_CONSTFRAME416_STATUS_constframe4_sel_SHIFT (16U) /*! constframe4_sel - Status of the connection of the constframe4 module * 0b000..constframe4 module is not used * 0b001..constframe4 module is used from store9 processing path * 0b010..constframe4 module is used from extdst0 processing path * 0b011..constframe4 module is used from extdst4 processing path * 0b100..constframe4 module is used from extdst1 processing path * 0b101..constframe4 module is used from extdst5 processing path */ #define IRIS_MVPL_CONSTFRAME416_STATUS_constframe4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME416_STATUS_constframe4_sel_SHIFT)) & IRIS_MVPL_CONSTFRAME416_STATUS_constframe4_sel_MASK) /*! @} */ /*! @name EXTDST448_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST448_LOCKUNLOCK_extdst4_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST448_LOCKUNLOCK_extdst4_LockUnlock_SHIFT (0U) /*! extdst4_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_EXTDST448_LOCKUNLOCK_extdst4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_LOCKUNLOCK_extdst4_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST448_LOCKUNLOCK_extdst4_LockUnlock_MASK) /*! @} */ /*! @name EXTDST448_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_LockStatus_MASK (0x1U) #define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_LockStatus_SHIFT (0U) /*! extdst4_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_LockStatus_MASK) #define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_PrivilegeStatus_SHIFT (4U) /*! extdst4_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_PrivilegeStatus_MASK) #define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_FreezeStatus_SHIFT (8U) /*! extdst4_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_FreezeStatus_MASK) /*! @} */ /*! @name EXTDST448_STATIC - Static pixel engine configuration for extdst4 */ /*! @{ */ #define IRIS_MVPL_EXTDST448_STATIC_extdst4_ShdEn_MASK (0x1U) #define IRIS_MVPL_EXTDST448_STATIC_extdst4_ShdEn_SHIFT (0U) /*! extdst4_ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for * pixelbus configuration of pipeline with endpoint extdst4. */ #define IRIS_MVPL_EXTDST448_STATIC_extdst4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATIC_extdst4_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST448_STATIC_extdst4_ShdEn_MASK) #define IRIS_MVPL_EXTDST448_STATIC_extdst4_powerdown_MASK (0x10U) #define IRIS_MVPL_EXTDST448_STATIC_extdst4_powerdown_SHIFT (4U) /*! extdst4_powerdown - Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst4 endpoint. */ #define IRIS_MVPL_EXTDST448_STATIC_extdst4_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATIC_extdst4_powerdown_SHIFT)) & IRIS_MVPL_EXTDST448_STATIC_extdst4_powerdown_MASK) #define IRIS_MVPL_EXTDST448_STATIC_extdst4_Sync_Mode_MASK (0x100U) #define IRIS_MVPL_EXTDST448_STATIC_extdst4_Sync_Mode_SHIFT (8U) /*! extdst4_Sync_Mode - Synchronization mode for extdst4 pipeline endpoint synchronizer * 0b0..Reconfig pipeline after explicit trigger * 0b1..Reconfig pipeline after every kick when idle */ #define IRIS_MVPL_EXTDST448_STATIC_extdst4_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATIC_extdst4_Sync_Mode_SHIFT)) & IRIS_MVPL_EXTDST448_STATIC_extdst4_Sync_Mode_MASK) #define IRIS_MVPL_EXTDST448_STATIC_extdst4_SW_Reset_MASK (0x800U) #define IRIS_MVPL_EXTDST448_STATIC_extdst4_SW_Reset_SHIFT (11U) /*! extdst4_SW_Reset - Software reset for extdst4 synchronizer, for debug purposes only * 0b0..Normal Operation * 0b1..Software Reset */ #define IRIS_MVPL_EXTDST448_STATIC_extdst4_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATIC_extdst4_SW_Reset_SHIFT)) & IRIS_MVPL_EXTDST448_STATIC_extdst4_SW_Reset_MASK) #define IRIS_MVPL_EXTDST448_STATIC_extdst4_div_MASK (0xFF0000U) #define IRIS_MVPL_EXTDST448_STATIC_extdst4_div_SHIFT (16U) /*! extdst4_div - extdst4 clock dividing factor (ratio is register_value/128, values above 128 are * reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled * submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets * the clock at full speed. */ #define IRIS_MVPL_EXTDST448_STATIC_extdst4_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATIC_extdst4_div_SHIFT)) & IRIS_MVPL_EXTDST448_STATIC_extdst4_div_MASK) /*! @} */ /*! @name EXTDST448_DYNAMIC - Dynamic pixel engine configuration for extdst4 */ /*! @{ */ #define IRIS_MVPL_EXTDST448_DYNAMIC_extdst4_src_sel_MASK (0x3FU) #define IRIS_MVPL_EXTDST448_DYNAMIC_extdst4_src_sel_SHIFT (0U) /*! extdst4_src_sel - Selection of the source for the src input of the extdst4 module * 0b000000..Unit extdst4 input port src is disabled * 0b001010..Unit extdst4 input port src is connected to output of unit blitblend9 * 0b001100..Unit extdst4 input port src is connected to output of unit constframe0 * 0b001110..Unit extdst4 input port src is connected to output of unit constframe4 * 0b000000..Unit extdst4 input port src is connected to output of unit constframe1 * 0b010010..Unit extdst4 input port src is connected to output of unit constframe5 * 0b011011..Unit extdst4 input port src is connected to output of unit matrix4 * 0b011100..Unit extdst4 input port src is connected to output of unit hscaler4 * 0b011101..Unit extdst4 input port src is connected to output of unit vscaler4 * 0b011110..Unit extdst4 input port src is connected to output of unit matrix5 * 0b011111..Unit extdst4 input port src is connected to output of unit hscaler5 * 0b100000..Unit extdst4 input port src is connected to output of unit vscaler5 * 0b100001..Unit extdst4 input port src is connected to output of unit layerblend0 * 0b100010..Unit extdst4 input port src is connected to output of unit layerblend1 * 0b100011..Unit extdst4 input port src is connected to output of unit layerblend2 * 0b100100..Unit extdst4 input port src is connected to output of unit layerblend3 */ #define IRIS_MVPL_EXTDST448_DYNAMIC_extdst4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_DYNAMIC_extdst4_src_sel_SHIFT)) & IRIS_MVPL_EXTDST448_DYNAMIC_extdst4_src_sel_MASK) /*! @} */ /*! @name EXTDST448_REQUEST - ShadowLoadRequest register for endpoint extdst4 */ /*! @{ */ #define IRIS_MVPL_EXTDST448_REQUEST_extdst4_sel_ShdLdReq_MASK (0x1U) #define IRIS_MVPL_EXTDST448_REQUEST_extdst4_sel_ShdLdReq_SHIFT (0U) /*! extdst4_sel_ShdLdReq - Shadow load request flag for destination extdst4. */ #define IRIS_MVPL_EXTDST448_REQUEST_extdst4_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_REQUEST_extdst4_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST448_REQUEST_extdst4_sel_ShdLdReq_MASK) #define IRIS_MVPL_EXTDST448_REQUEST_extdst4_ShdLdReq_MASK (0x7FFEU) #define IRIS_MVPL_EXTDST448_REQUEST_extdst4_ShdLdReq_SHIFT (1U) /*! extdst4_ShdLdReq - Vector of shadow load request flag of all sources for destination extdst4. * Setting a bit has no effect if the source is currently in a different pipeline than the one of * destination extdst4. */ #define IRIS_MVPL_EXTDST448_REQUEST_extdst4_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_REQUEST_extdst4_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST448_REQUEST_extdst4_ShdLdReq_MASK) /*! @} */ /*! @name EXTDST448_TRIGGER - Trigger bits for pixel engine configuration of extdst4 */ /*! @{ */ #define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_Sync_Trigger_MASK (0x1U) #define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_Sync_Trigger_SHIFT (0U) /*! extdst4_Sync_Trigger - Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst4 */ #define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_TRIGGER_extdst4_Sync_Trigger_SHIFT)) & IRIS_MVPL_EXTDST448_TRIGGER_extdst4_Sync_Trigger_MASK) #define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_trigger_sequence_complete_MASK (0x10U) #define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_trigger_sequence_complete_SHIFT (4U) /*! extdst4_trigger_sequence_complete - By writing a '1' to this register field, you can trigger the * extdst4 sequence complete interrupt that will occur as soon as the pipeline with the endpoint * extdst4 is empty. This interrupt will also occur if the pipeline is already empty when this * field is written. The interrupt will not occur if this field is not written. The interrupt will * occur exactly as often as this field is written, assuming that this field is not written * again until the interrupt has occured after a previous trigger. */ #define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_TRIGGER_extdst4_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_EXTDST448_TRIGGER_extdst4_trigger_sequence_complete_MASK) /*! @} */ /*! @name EXTDST448_STATUS - Status information for pixel engine configuration of extdst4 */ /*! @{ */ #define IRIS_MVPL_EXTDST448_STATUS_extdst4_pipeline_status_MASK (0x3U) #define IRIS_MVPL_EXTDST448_STATUS_extdst4_pipeline_status_SHIFT (0U) /*! extdst4_pipeline_status - Status of pipeline with endpoint extdst4 * 0b00..Pipeline with endpoint extdst4 is empty * 0b01..Pipeline with endpoint extdst4 is currently processing one operation * 0b10..Pipeline with endpoint extdst4 is currently processing one operation with a second one already kicked to be processed afterwards * 0b11..reserved */ #define IRIS_MVPL_EXTDST448_STATUS_extdst4_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATUS_extdst4_pipeline_status_SHIFT)) & IRIS_MVPL_EXTDST448_STATUS_extdst4_pipeline_status_MASK) #define IRIS_MVPL_EXTDST448_STATUS_extdst4_sync_busy_MASK (0x100U) #define IRIS_MVPL_EXTDST448_STATUS_extdst4_sync_busy_SHIFT (8U) /*! extdst4_sync_busy - Synchronization busy status of extdst4 endpoint * 0b0..extdst4 synchronizer is idle * 0b1..extdst4 synchronizer is busy */ #define IRIS_MVPL_EXTDST448_STATUS_extdst4_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATUS_extdst4_sync_busy_SHIFT)) & IRIS_MVPL_EXTDST448_STATUS_extdst4_sync_busy_MASK) /*! @} */ /*! @name CONSTFRAME480_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME480_LOCKUNLOCK_constframe1_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CONSTFRAME480_LOCKUNLOCK_constframe1_LockUnlock_SHIFT (0U) /*! constframe1_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CONSTFRAME480_LOCKUNLOCK_constframe1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME480_LOCKUNLOCK_constframe1_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME480_LOCKUNLOCK_constframe1_LockUnlock_MASK) /*! @} */ /*! @name CONSTFRAME480_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_LockStatus_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_LockStatus_SHIFT (0U) /*! constframe1_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_LockStatus_MASK) #define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_PrivilegeStatus_SHIFT (4U) /*! constframe1_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_PrivilegeStatus_MASK) #define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_FreezeStatus_SHIFT (8U) /*! constframe1_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_FreezeStatus_MASK) /*! @} */ /*! @name CONSTFRAME480_STATUS - Status information for pixel engine configuration of constframe1 */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME480_STATUS_constframe1_sel_MASK (0x70000U) #define IRIS_MVPL_CONSTFRAME480_STATUS_constframe1_sel_SHIFT (16U) /*! constframe1_sel - Status of the connection of the constframe1 module * 0b000..constframe1 module is not used * 0b001..constframe1 module is used from store9 processing path * 0b010..constframe1 module is used from extdst0 processing path * 0b011..constframe1 module is used from extdst4 processing path * 0b100..constframe1 module is used from extdst1 processing path * 0b101..constframe1 module is used from extdst5 processing path */ #define IRIS_MVPL_CONSTFRAME480_STATUS_constframe1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME480_STATUS_constframe1_sel_SHIFT)) & IRIS_MVPL_CONSTFRAME480_STATUS_constframe1_sel_MASK) /*! @} */ /*! @name EXTDST512_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST512_LOCKUNLOCK_extdst1_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST512_LOCKUNLOCK_extdst1_LockUnlock_SHIFT (0U) /*! extdst1_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_EXTDST512_LOCKUNLOCK_extdst1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_LOCKUNLOCK_extdst1_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST512_LOCKUNLOCK_extdst1_LockUnlock_MASK) /*! @} */ /*! @name EXTDST512_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_LockStatus_MASK (0x1U) #define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_LockStatus_SHIFT (0U) /*! extdst1_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_LockStatus_MASK) #define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_PrivilegeStatus_SHIFT (4U) /*! extdst1_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_PrivilegeStatus_MASK) #define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_FreezeStatus_SHIFT (8U) /*! extdst1_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_FreezeStatus_MASK) /*! @} */ /*! @name EXTDST1_STATIC - Static pixel engine configuration for extdst1 */ /*! @{ */ #define IRIS_MVPL_EXTDST1_STATIC_extdst1_ShdEn_MASK (0x1U) #define IRIS_MVPL_EXTDST1_STATIC_extdst1_ShdEn_SHIFT (0U) /*! extdst1_ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for * pixelbus configuration of pipeline with endpoint extdst1. */ #define IRIS_MVPL_EXTDST1_STATIC_extdst1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATIC_extdst1_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST1_STATIC_extdst1_ShdEn_MASK) #define IRIS_MVPL_EXTDST1_STATIC_extdst1_powerdown_MASK (0x10U) #define IRIS_MVPL_EXTDST1_STATIC_extdst1_powerdown_SHIFT (4U) /*! extdst1_powerdown - Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst1 endpoint. */ #define IRIS_MVPL_EXTDST1_STATIC_extdst1_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATIC_extdst1_powerdown_SHIFT)) & IRIS_MVPL_EXTDST1_STATIC_extdst1_powerdown_MASK) #define IRIS_MVPL_EXTDST1_STATIC_extdst1_Sync_Mode_MASK (0x100U) #define IRIS_MVPL_EXTDST1_STATIC_extdst1_Sync_Mode_SHIFT (8U) /*! extdst1_Sync_Mode - Synchronization mode for extdst1 pipeline endpoint synchronizer * 0b0..Reconfig pipeline after explicit trigger * 0b1..Reconfig pipeline after every kick when idle */ #define IRIS_MVPL_EXTDST1_STATIC_extdst1_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATIC_extdst1_Sync_Mode_SHIFT)) & IRIS_MVPL_EXTDST1_STATIC_extdst1_Sync_Mode_MASK) #define IRIS_MVPL_EXTDST1_STATIC_extdst1_SW_Reset_MASK (0x800U) #define IRIS_MVPL_EXTDST1_STATIC_extdst1_SW_Reset_SHIFT (11U) /*! extdst1_SW_Reset - Software reset for extdst1 synchronizer, for debug purposes only * 0b0..Normal Operation * 0b1..Software Reset */ #define IRIS_MVPL_EXTDST1_STATIC_extdst1_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATIC_extdst1_SW_Reset_SHIFT)) & IRIS_MVPL_EXTDST1_STATIC_extdst1_SW_Reset_MASK) #define IRIS_MVPL_EXTDST1_STATIC_extdst1_div_MASK (0xFF0000U) #define IRIS_MVPL_EXTDST1_STATIC_extdst1_div_SHIFT (16U) /*! extdst1_div - extdst1 clock dividing factor (ratio is register_value/128, values above 128 are * reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled * submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets * the clock at full speed. */ #define IRIS_MVPL_EXTDST1_STATIC_extdst1_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATIC_extdst1_div_SHIFT)) & IRIS_MVPL_EXTDST1_STATIC_extdst1_div_MASK) /*! @} */ /*! @name EXTDST1_DYNAMIC - Dynamic pixel engine configuration for extdst1 */ /*! @{ */ #define IRIS_MVPL_EXTDST1_DYNAMIC_extdst1_src_sel_MASK (0x3FU) #define IRIS_MVPL_EXTDST1_DYNAMIC_extdst1_src_sel_SHIFT (0U) /*! extdst1_src_sel - Selection of the source for the src input of the extdst1 module * 0b000000..Unit extdst1 input port src is disabled * 0b001010..Unit extdst1 input port src is connected to output of unit blitblend9 * 0b001100..Unit extdst1 input port src is connected to output of unit constframe0 * 0b001110..Unit extdst1 input port src is connected to output of unit constframe4 * 0b000000..Unit extdst1 input port src is connected to output of unit constframe1 * 0b010010..Unit extdst1 input port src is connected to output of unit constframe5 * 0b011011..Unit extdst1 input port src is connected to output of unit matrix4 * 0b011100..Unit extdst1 input port src is connected to output of unit hscaler4 * 0b011101..Unit extdst1 input port src is connected to output of unit vscaler4 * 0b011110..Unit extdst1 input port src is connected to output of unit matrix5 * 0b011111..Unit extdst1 input port src is connected to output of unit hscaler5 * 0b100000..Unit extdst1 input port src is connected to output of unit vscaler5 * 0b100001..Unit extdst1 input port src is connected to output of unit layerblend0 * 0b100010..Unit extdst1 input port src is connected to output of unit layerblend1 * 0b100011..Unit extdst1 input port src is connected to output of unit layerblend2 * 0b100100..Unit extdst1 input port src is connected to output of unit layerblend3 */ #define IRIS_MVPL_EXTDST1_DYNAMIC_extdst1_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_DYNAMIC_extdst1_src_sel_SHIFT)) & IRIS_MVPL_EXTDST1_DYNAMIC_extdst1_src_sel_MASK) /*! @} */ /*! @name EXTDST1_REQUEST - ShadowLoadRequest register for endpoint extdst1 */ /*! @{ */ #define IRIS_MVPL_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_MASK (0x1U) #define IRIS_MVPL_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_SHIFT (0U) /*! extdst1_sel_ShdLdReq - Shadow load request flag for destination extdst1. */ #define IRIS_MVPL_EXTDST1_REQUEST_extdst1_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_MASK) #define IRIS_MVPL_EXTDST1_REQUEST_extdst1_ShdLdReq_MASK (0x7FFEU) #define IRIS_MVPL_EXTDST1_REQUEST_extdst1_ShdLdReq_SHIFT (1U) /*! extdst1_ShdLdReq - Vector of shadow load request flag of all sources for destination extdst1. * Setting a bit has no effect if the source is currently in a different pipeline than the one of * destination extdst1. */ #define IRIS_MVPL_EXTDST1_REQUEST_extdst1_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_REQUEST_extdst1_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST1_REQUEST_extdst1_ShdLdReq_MASK) /*! @} */ /*! @name EXTDST1_TRIGGER - Trigger bits for pixel engine configuration of extdst1 */ /*! @{ */ #define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_Sync_Trigger_MASK (0x1U) #define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_Sync_Trigger_SHIFT (0U) /*! extdst1_Sync_Trigger - Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst1 */ #define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_TRIGGER_extdst1_Sync_Trigger_SHIFT)) & IRIS_MVPL_EXTDST1_TRIGGER_extdst1_Sync_Trigger_MASK) #define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_MASK (0x10U) #define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_SHIFT (4U) /*! extdst1_trigger_sequence_complete - By writing a '1' to this register field, you can trigger the * extdst1 sequence complete interrupt that will occur as soon as the pipeline with the endpoint * extdst1 is empty. This interrupt will also occur if the pipeline is already empty when this * field is written. The interrupt will not occur if this field is not written. The interrupt will * occur exactly as often as this field is written, assuming that this field is not written * again until the interrupt has occured after a previous trigger. */ #define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_MASK) /*! @} */ /*! @name EXTDST512_STATUS - Status information for pixel engine configuration of extdst1 */ /*! @{ */ #define IRIS_MVPL_EXTDST512_STATUS_extdst1_pipeline_status_MASK (0x3U) #define IRIS_MVPL_EXTDST512_STATUS_extdst1_pipeline_status_SHIFT (0U) /*! extdst1_pipeline_status - Status of pipeline with endpoint extdst1 * 0b00..Pipeline with endpoint extdst1 is empty * 0b01..Pipeline with endpoint extdst1 is currently processing one operation * 0b10..Pipeline with endpoint extdst1 is currently processing one operation with a second one already kicked to be processed afterwards * 0b11..reserved */ #define IRIS_MVPL_EXTDST512_STATUS_extdst1_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_STATUS_extdst1_pipeline_status_SHIFT)) & IRIS_MVPL_EXTDST512_STATUS_extdst1_pipeline_status_MASK) #define IRIS_MVPL_EXTDST512_STATUS_extdst1_sync_busy_MASK (0x100U) #define IRIS_MVPL_EXTDST512_STATUS_extdst1_sync_busy_SHIFT (8U) /*! extdst1_sync_busy - Synchronization busy status of extdst1 endpoint * 0b0..extdst1 synchronizer is idle * 0b1..extdst1 synchronizer is busy */ #define IRIS_MVPL_EXTDST512_STATUS_extdst1_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_STATUS_extdst1_sync_busy_SHIFT)) & IRIS_MVPL_EXTDST512_STATUS_extdst1_sync_busy_MASK) /*! @} */ /*! @name CONSTFRAME_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME_LOCKUNLOCK_constframe5_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CONSTFRAME_LOCKUNLOCK_constframe5_LockUnlock_SHIFT (0U) /*! constframe5_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CONSTFRAME_LOCKUNLOCK_constframe5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME_LOCKUNLOCK_constframe5_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME_LOCKUNLOCK_constframe5_LockUnlock_MASK) /*! @} */ /*! @name CONSTFRAME_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_LockStatus_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_LockStatus_SHIFT (0U) /*! constframe5_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_LockStatus_MASK) #define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_PrivilegeStatus_SHIFT (4U) /*! constframe5_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_PrivilegeStatus_MASK) #define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_FreezeStatus_SHIFT (8U) /*! constframe5_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_FreezeStatus_MASK) /*! @} */ /*! @name CONSTFRAME_STATUS - Status information for pixel engine configuration of constframe5 */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME_STATUS_constframe5_sel_MASK (0x70000U) #define IRIS_MVPL_CONSTFRAME_STATUS_constframe5_sel_SHIFT (16U) /*! constframe5_sel - Status of the connection of the constframe5 module * 0b000..constframe5 module is not used * 0b001..constframe5 module is used from store9 processing path * 0b010..constframe5 module is used from extdst0 processing path * 0b011..constframe5 module is used from extdst4 processing path * 0b100..constframe5 module is used from extdst1 processing path * 0b101..constframe5 module is used from extdst5 processing path */ #define IRIS_MVPL_CONSTFRAME_STATUS_constframe5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME_STATUS_constframe5_sel_SHIFT)) & IRIS_MVPL_CONSTFRAME_STATUS_constframe5_sel_MASK) /*! @} */ /*! @name EXTDST544_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST544_LOCKUNLOCK_extdst5_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST544_LOCKUNLOCK_extdst5_LockUnlock_SHIFT (0U) /*! extdst5_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_EXTDST544_LOCKUNLOCK_extdst5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_LOCKUNLOCK_extdst5_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST544_LOCKUNLOCK_extdst5_LockUnlock_MASK) /*! @} */ /*! @name EXTDST544_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_LockStatus_MASK (0x1U) #define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_LockStatus_SHIFT (0U) /*! extdst5_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_LockStatus_MASK) #define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_PrivilegeStatus_SHIFT (4U) /*! extdst5_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_PrivilegeStatus_MASK) #define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_FreezeStatus_SHIFT (8U) /*! extdst5_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_FreezeStatus_MASK) /*! @} */ /*! @name EXTDST5_STATIC - Static pixel engine configuration for extdst5 */ /*! @{ */ #define IRIS_MVPL_EXTDST5_STATIC_extdst5_ShdEn_MASK (0x1U) #define IRIS_MVPL_EXTDST5_STATIC_extdst5_ShdEn_SHIFT (0U) /*! extdst5_ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for * pixelbus configuration of pipeline with endpoint extdst5. */ #define IRIS_MVPL_EXTDST5_STATIC_extdst5_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATIC_extdst5_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST5_STATIC_extdst5_ShdEn_MASK) #define IRIS_MVPL_EXTDST5_STATIC_extdst5_powerdown_MASK (0x10U) #define IRIS_MVPL_EXTDST5_STATIC_extdst5_powerdown_SHIFT (4U) /*! extdst5_powerdown - Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst5 endpoint. */ #define IRIS_MVPL_EXTDST5_STATIC_extdst5_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATIC_extdst5_powerdown_SHIFT)) & IRIS_MVPL_EXTDST5_STATIC_extdst5_powerdown_MASK) #define IRIS_MVPL_EXTDST5_STATIC_extdst5_Sync_Mode_MASK (0x100U) #define IRIS_MVPL_EXTDST5_STATIC_extdst5_Sync_Mode_SHIFT (8U) /*! extdst5_Sync_Mode - Synchronization mode for extdst5 pipeline endpoint synchronizer * 0b0..Reconfig pipeline after explicit trigger * 0b1..Reconfig pipeline after every kick when idle */ #define IRIS_MVPL_EXTDST5_STATIC_extdst5_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATIC_extdst5_Sync_Mode_SHIFT)) & IRIS_MVPL_EXTDST5_STATIC_extdst5_Sync_Mode_MASK) #define IRIS_MVPL_EXTDST5_STATIC_extdst5_SW_Reset_MASK (0x800U) #define IRIS_MVPL_EXTDST5_STATIC_extdst5_SW_Reset_SHIFT (11U) /*! extdst5_SW_Reset - Software reset for extdst5 synchronizer, for debug purposes only * 0b0..Normal Operation * 0b1..Software Reset */ #define IRIS_MVPL_EXTDST5_STATIC_extdst5_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATIC_extdst5_SW_Reset_SHIFT)) & IRIS_MVPL_EXTDST5_STATIC_extdst5_SW_Reset_MASK) #define IRIS_MVPL_EXTDST5_STATIC_extdst5_div_MASK (0xFF0000U) #define IRIS_MVPL_EXTDST5_STATIC_extdst5_div_SHIFT (16U) /*! extdst5_div - extdst5 clock dividing factor (ratio is register_value/128, values above 128 are * reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled * submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets * the clock at full speed. */ #define IRIS_MVPL_EXTDST5_STATIC_extdst5_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATIC_extdst5_div_SHIFT)) & IRIS_MVPL_EXTDST5_STATIC_extdst5_div_MASK) /*! @} */ /*! @name EXTDST5_DYNAMIC - Dynamic pixel engine configuration for extdst5 */ /*! @{ */ #define IRIS_MVPL_EXTDST5_DYNAMIC_extdst5_src_sel_MASK (0x3FU) #define IRIS_MVPL_EXTDST5_DYNAMIC_extdst5_src_sel_SHIFT (0U) /*! extdst5_src_sel - Selection of the source for the src input of the extdst5 module * 0b000000..Unit extdst5 input port src is disabled * 0b001010..Unit extdst5 input port src is connected to output of unit blitblend9 * 0b001100..Unit extdst5 input port src is connected to output of unit constframe0 * 0b001110..Unit extdst5 input port src is connected to output of unit constframe4 * 0b000000..Unit extdst5 input port src is connected to output of unit constframe1 * 0b010010..Unit extdst5 input port src is connected to output of unit constframe5 * 0b011011..Unit extdst5 input port src is connected to output of unit matrix4 * 0b011100..Unit extdst5 input port src is connected to output of unit hscaler4 * 0b011101..Unit extdst5 input port src is connected to output of unit vscaler4 * 0b011110..Unit extdst5 input port src is connected to output of unit matrix5 * 0b011111..Unit extdst5 input port src is connected to output of unit hscaler5 * 0b100000..Unit extdst5 input port src is connected to output of unit vscaler5 * 0b100001..Unit extdst5 input port src is connected to output of unit layerblend0 * 0b100010..Unit extdst5 input port src is connected to output of unit layerblend1 * 0b100011..Unit extdst5 input port src is connected to output of unit layerblend2 * 0b100100..Unit extdst5 input port src is connected to output of unit layerblend3 */ #define IRIS_MVPL_EXTDST5_DYNAMIC_extdst5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_DYNAMIC_extdst5_src_sel_SHIFT)) & IRIS_MVPL_EXTDST5_DYNAMIC_extdst5_src_sel_MASK) /*! @} */ /*! @name EXTDST5_REQUEST - ShadowLoadRequest register for endpoint extdst5 */ /*! @{ */ #define IRIS_MVPL_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_MASK (0x1U) #define IRIS_MVPL_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_SHIFT (0U) /*! extdst5_sel_ShdLdReq - Shadow load request flag for destination extdst5. */ #define IRIS_MVPL_EXTDST5_REQUEST_extdst5_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_MASK) #define IRIS_MVPL_EXTDST5_REQUEST_extdst5_ShdLdReq_MASK (0x7FFEU) #define IRIS_MVPL_EXTDST5_REQUEST_extdst5_ShdLdReq_SHIFT (1U) /*! extdst5_ShdLdReq - Vector of shadow load request flag of all sources for destination extdst5. * Setting a bit has no effect if the source is currently in a different pipeline than the one of * destination extdst5. */ #define IRIS_MVPL_EXTDST5_REQUEST_extdst5_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_REQUEST_extdst5_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST5_REQUEST_extdst5_ShdLdReq_MASK) /*! @} */ /*! @name EXTDST5_TRIGGER - Trigger bits for pixel engine configuration of extdst5 */ /*! @{ */ #define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_Sync_Trigger_MASK (0x1U) #define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_Sync_Trigger_SHIFT (0U) /*! extdst5_Sync_Trigger - Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst5 */ #define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_TRIGGER_extdst5_Sync_Trigger_SHIFT)) & IRIS_MVPL_EXTDST5_TRIGGER_extdst5_Sync_Trigger_MASK) #define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_MASK (0x10U) #define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_SHIFT (4U) /*! extdst5_trigger_sequence_complete - By writing a '1' to this register field, you can trigger the * extdst5 sequence complete interrupt that will occur as soon as the pipeline with the endpoint * extdst5 is empty. This interrupt will also occur if the pipeline is already empty when this * field is written. The interrupt will not occur if this field is not written. The interrupt will * occur exactly as often as this field is written, assuming that this field is not written * again until the interrupt has occured after a previous trigger. */ #define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_MASK) /*! @} */ /*! @name EXTDST544_STATUS - Status information for pixel engine configuration of extdst5 */ /*! @{ */ #define IRIS_MVPL_EXTDST544_STATUS_extdst5_pipeline_status_MASK (0x3U) #define IRIS_MVPL_EXTDST544_STATUS_extdst5_pipeline_status_SHIFT (0U) /*! extdst5_pipeline_status - Status of pipeline with endpoint extdst5 * 0b00..Pipeline with endpoint extdst5 is empty * 0b01..Pipeline with endpoint extdst5 is currently processing one operation * 0b10..Pipeline with endpoint extdst5 is currently processing one operation with a second one already kicked to be processed afterwards * 0b11..reserved */ #define IRIS_MVPL_EXTDST544_STATUS_extdst5_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_STATUS_extdst5_pipeline_status_SHIFT)) & IRIS_MVPL_EXTDST544_STATUS_extdst5_pipeline_status_MASK) #define IRIS_MVPL_EXTDST544_STATUS_extdst5_sync_busy_MASK (0x100U) #define IRIS_MVPL_EXTDST544_STATUS_extdst5_sync_busy_SHIFT (8U) /*! extdst5_sync_busy - Synchronization busy status of extdst5 endpoint * 0b0..extdst5 synchronizer is idle * 0b1..extdst5 synchronizer is busy */ #define IRIS_MVPL_EXTDST544_STATUS_extdst5_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_STATUS_extdst5_sync_busy_SHIFT)) & IRIS_MVPL_EXTDST544_STATUS_extdst5_sync_busy_MASK) /*! @} */ /*! @name FETCHWARP608_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP608_LOCKUNLOCK_fetchwarp2_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP608_LOCKUNLOCK_fetchwarp2_LockUnlock_SHIFT (0U) /*! fetchwarp2_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHWARP608_LOCKUNLOCK_fetchwarp2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_LOCKUNLOCK_fetchwarp2_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHWARP608_LOCKUNLOCK_fetchwarp2_LockUnlock_MASK) /*! @} */ /*! @name FETCHWARP608_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_LockStatus_SHIFT (0U) /*! fetchwarp2_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_LockStatus_SHIFT)) & IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_LockStatus_MASK) #define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_PrivilegeStatus_SHIFT (4U) /*! fetchwarp2_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_FreezeStatus_SHIFT (8U) /*! fetchwarp2_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_FreezeStatus_MASK) /*! @} */ /*! @name FETCHWARP608_DYNAMIC - Dynamic pixel engine configuration for fetchwarp2 */ /*! @{ */ #define IRIS_MVPL_FETCHWARP608_DYNAMIC_fetchwarp2_src_sel_MASK (0x3FU) #define IRIS_MVPL_FETCHWARP608_DYNAMIC_fetchwarp2_src_sel_SHIFT (0U) /*! fetchwarp2_src_sel - Selection of the source for the src input of the fetchwarp2 module * 0b000000..Unit fetchwarp2 input port src is disabled * 0b010101..Unit fetchwarp2 input port src is connected to output of unit fetcheco2 */ #define IRIS_MVPL_FETCHWARP608_DYNAMIC_fetchwarp2_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_DYNAMIC_fetchwarp2_src_sel_SHIFT)) & IRIS_MVPL_FETCHWARP608_DYNAMIC_fetchwarp2_src_sel_MASK) /*! @} */ /*! @name FETCHWARP608_STATUS - Status information for pixel engine configuration of fetchwarp2 */ /*! @{ */ #define IRIS_MVPL_FETCHWARP608_STATUS_fetchwarp2_sel_MASK (0x70000U) #define IRIS_MVPL_FETCHWARP608_STATUS_fetchwarp2_sel_SHIFT (16U) /*! fetchwarp2_sel - Status of the connection of the fetchwarp2 module * 0b000..fetchwarp2 module is not used * 0b001..fetchwarp2 module is used from store9 processing path * 0b010..fetchwarp2 module is used from extdst0 processing path * 0b011..fetchwarp2 module is used from extdst4 processing path * 0b100..fetchwarp2 module is used from extdst1 processing path * 0b101..fetchwarp2 module is used from extdst5 processing path */ #define IRIS_MVPL_FETCHWARP608_STATUS_fetchwarp2_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_STATUS_fetchwarp2_sel_SHIFT)) & IRIS_MVPL_FETCHWARP608_STATUS_fetchwarp2_sel_MASK) /*! @} */ /*! @name FETCHECO624_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO624_LOCKUNLOCK_fetcheco2_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO624_LOCKUNLOCK_fetcheco2_LockUnlock_SHIFT (0U) /*! fetcheco2_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHECO624_LOCKUNLOCK_fetcheco2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO624_LOCKUNLOCK_fetcheco2_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO624_LOCKUNLOCK_fetcheco2_LockUnlock_MASK) /*! @} */ /*! @name FETCHECO624_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_LockStatus_SHIFT (0U) /*! fetcheco2_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_LockStatus_MASK) #define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_PrivilegeStatus_SHIFT (4U) /*! fetcheco2_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_FreezeStatus_SHIFT (8U) /*! fetcheco2_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_FreezeStatus_MASK) /*! @} */ /*! @name FETCHECO2_STATUS - Status information for pixel engine configuration of fetcheco2 */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_STATUS_fetcheco2_sel_MASK (0x70000U) #define IRIS_MVPL_FETCHECO2_STATUS_fetcheco2_sel_SHIFT (16U) /*! fetcheco2_sel - Status of the connection of the fetcheco2 module * 0b000..fetcheco2 module is not used * 0b001..fetcheco2 module is used from store9 processing path * 0b010..fetcheco2 module is used from extdst0 processing path * 0b011..fetcheco2 module is used from extdst4 processing path * 0b100..fetcheco2 module is used from extdst1 processing path * 0b101..fetcheco2 module is used from extdst5 processing path */ #define IRIS_MVPL_FETCHECO2_STATUS_fetcheco2_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_STATUS_fetcheco2_sel_SHIFT)) & IRIS_MVPL_FETCHECO2_STATUS_fetcheco2_sel_MASK) /*! @} */ /*! @name FETCHDECODE0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_SHIFT (0U) /*! fetchdecode0_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_MASK) /*! @} */ /*! @name FETCHDECODE0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_SHIFT (0U) /*! fetchdecode0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_MASK) #define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_SHIFT (4U) /*! fetchdecode0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_SHIFT (8U) /*! fetchdecode0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_MASK) /*! @} */ /*! @name FETCHDECODE0_DYNAMIC - Dynamic pixel engine configuration for fetchdecode0 */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_MASK (0x3FU) #define IRIS_MVPL_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_SHIFT (0U) /*! fetchdecode0_src_sel - Selection of the source for the src input of the fetchdecode0 module * 0b000000..Unit fetchdecode0 input port src is disabled * 0b010100..Unit fetchdecode0 input port src is connected to output of unit fetchwarp2 * 0b010111..Unit fetchdecode0 input port src is connected to output of unit fetcheco0 * 0b011000..Unit fetchdecode0 input port src is connected to output of unit fetchdecode1 */ #define IRIS_MVPL_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_MASK) /*! @} */ /*! @name FETCHDECODE0_STATUS - Status information for pixel engine configuration of fetchdecode0 */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE0_STATUS_fetchdecode0_sel_MASK (0x70000U) #define IRIS_MVPL_FETCHDECODE0_STATUS_fetchdecode0_sel_SHIFT (16U) /*! fetchdecode0_sel - Status of the connection of the fetchdecode0 module * 0b000..fetchdecode0 module is not used * 0b001..fetchdecode0 module is used from store9 processing path * 0b010..fetchdecode0 module is used from extdst0 processing path * 0b011..fetchdecode0 module is used from extdst4 processing path * 0b100..fetchdecode0 module is used from extdst1 processing path * 0b101..fetchdecode0 module is used from extdst5 processing path */ #define IRIS_MVPL_FETCHDECODE0_STATUS_fetchdecode0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_STATUS_fetchdecode0_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE0_STATUS_fetchdecode0_sel_MASK) /*! @} */ /*! @name FETCHECO656_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO656_LOCKUNLOCK_fetcheco0_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO656_LOCKUNLOCK_fetcheco0_LockUnlock_SHIFT (0U) /*! fetcheco0_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHECO656_LOCKUNLOCK_fetcheco0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO656_LOCKUNLOCK_fetcheco0_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO656_LOCKUNLOCK_fetcheco0_LockUnlock_MASK) /*! @} */ /*! @name FETCHECO656_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_LockStatus_SHIFT (0U) /*! fetcheco0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_LockStatus_MASK) #define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_PrivilegeStatus_SHIFT (4U) /*! fetcheco0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_FreezeStatus_SHIFT (8U) /*! fetcheco0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_FreezeStatus_MASK) /*! @} */ /*! @name FETCHECO0_STATUS - Status information for pixel engine configuration of fetcheco0 */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_STATUS_fetcheco0_sel_MASK (0x70000U) #define IRIS_MVPL_FETCHECO0_STATUS_fetcheco0_sel_SHIFT (16U) /*! fetcheco0_sel - Status of the connection of the fetcheco0 module * 0b000..fetcheco0 module is not used * 0b001..fetcheco0 module is used from store9 processing path * 0b010..fetcheco0 module is used from extdst0 processing path * 0b011..fetcheco0 module is used from extdst4 processing path * 0b100..fetcheco0 module is used from extdst1 processing path * 0b101..fetcheco0 module is used from extdst5 processing path */ #define IRIS_MVPL_FETCHECO0_STATUS_fetcheco0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_STATUS_fetcheco0_sel_SHIFT)) & IRIS_MVPL_FETCHECO0_STATUS_fetcheco0_sel_MASK) /*! @} */ /*! @name FETCHDECODE672_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE672_LOCKUNLOCK_fetchdecode1_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE672_LOCKUNLOCK_fetchdecode1_LockUnlock_SHIFT (0U) /*! fetchdecode1_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHDECODE672_LOCKUNLOCK_fetchdecode1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE672_LOCKUNLOCK_fetchdecode1_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE672_LOCKUNLOCK_fetchdecode1_LockUnlock_MASK) /*! @} */ /*! @name FETCHDECODE672_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_LockStatus_SHIFT (0U) /*! fetchdecode1_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_LockStatus_MASK) #define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_PrivilegeStatus_SHIFT (4U) /*! fetchdecode1_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_FreezeStatus_SHIFT (8U) /*! fetchdecode1_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_FreezeStatus_MASK) /*! @} */ /*! @name FETCHDECODE1_DYNAMIC - Dynamic pixel engine configuration for fetchdecode1 */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_MASK (0x3FU) #define IRIS_MVPL_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_SHIFT (0U) /*! fetchdecode1_src_sel - Selection of the source for the src input of the fetchdecode1 module * 0b000000..Unit fetchdecode1 input port src is disabled * 0b010100..Unit fetchdecode1 input port src is connected to output of unit fetchwarp2 * 0b010110..Unit fetchdecode1 input port src is connected to output of unit fetchdecode0 * 0b011001..Unit fetchdecode1 input port src is connected to output of unit fetcheco1 */ #define IRIS_MVPL_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_MASK) /*! @} */ /*! @name FETCHDECODE1_STATUS - Status information for pixel engine configuration of fetchdecode1 */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE1_STATUS_fetchdecode1_sel_MASK (0x70000U) #define IRIS_MVPL_FETCHDECODE1_STATUS_fetchdecode1_sel_SHIFT (16U) /*! fetchdecode1_sel - Status of the connection of the fetchdecode1 module * 0b000..fetchdecode1 module is not used * 0b001..fetchdecode1 module is used from store9 processing path * 0b010..fetchdecode1 module is used from extdst0 processing path * 0b011..fetchdecode1 module is used from extdst4 processing path * 0b100..fetchdecode1 module is used from extdst1 processing path * 0b101..fetchdecode1 module is used from extdst5 processing path */ #define IRIS_MVPL_FETCHDECODE1_STATUS_fetchdecode1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_STATUS_fetchdecode1_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE1_STATUS_fetchdecode1_sel_MASK) /*! @} */ /*! @name FETCHECO688_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO688_LOCKUNLOCK_fetcheco1_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO688_LOCKUNLOCK_fetcheco1_LockUnlock_SHIFT (0U) /*! fetcheco1_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHECO688_LOCKUNLOCK_fetcheco1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO688_LOCKUNLOCK_fetcheco1_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO688_LOCKUNLOCK_fetcheco1_LockUnlock_MASK) /*! @} */ /*! @name FETCHECO688_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_LockStatus_SHIFT (0U) /*! fetcheco1_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_LockStatus_MASK) #define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_PrivilegeStatus_SHIFT (4U) /*! fetcheco1_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_FreezeStatus_SHIFT (8U) /*! fetcheco1_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_FreezeStatus_MASK) /*! @} */ /*! @name FETCHECO1_STATUS - Status information for pixel engine configuration of fetcheco1 */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_STATUS_fetcheco1_sel_MASK (0x70000U) #define IRIS_MVPL_FETCHECO1_STATUS_fetcheco1_sel_SHIFT (16U) /*! fetcheco1_sel - Status of the connection of the fetcheco1 module * 0b000..fetcheco1 module is not used * 0b001..fetcheco1 module is used from store9 processing path * 0b010..fetcheco1 module is used from extdst0 processing path * 0b011..fetcheco1 module is used from extdst4 processing path * 0b100..fetcheco1 module is used from extdst1 processing path * 0b101..fetcheco1 module is used from extdst5 processing path */ #define IRIS_MVPL_FETCHECO1_STATUS_fetcheco1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_STATUS_fetcheco1_sel_SHIFT)) & IRIS_MVPL_FETCHECO1_STATUS_fetcheco1_sel_MASK) /*! @} */ /*! @name FETCHLAYER704_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER704_LOCKUNLOCK_fetchlayer0_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHLAYER704_LOCKUNLOCK_fetchlayer0_LockUnlock_SHIFT (0U) /*! fetchlayer0_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHLAYER704_LOCKUNLOCK_fetchlayer0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER704_LOCKUNLOCK_fetchlayer0_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHLAYER704_LOCKUNLOCK_fetchlayer0_LockUnlock_MASK) /*! @} */ /*! @name FETCHLAYER704_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_LockStatus_SHIFT (0U) /*! fetchlayer0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_LockStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_LockStatus_MASK) #define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_PrivilegeStatus_SHIFT (4U) /*! fetchlayer0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_FreezeStatus_SHIFT (8U) /*! fetchlayer0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_FreezeStatus_MASK) /*! @} */ /*! @name FETCHLAYER704_STATUS - Status information for pixel engine configuration of fetchlayer0 */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER704_STATUS_fetchlayer0_sel_MASK (0x70000U) #define IRIS_MVPL_FETCHLAYER704_STATUS_fetchlayer0_sel_SHIFT (16U) /*! fetchlayer0_sel - Status of the connection of the fetchlayer0 module * 0b000..fetchlayer0 module is not used * 0b001..fetchlayer0 module is used from store9 processing path * 0b010..fetchlayer0 module is used from extdst0 processing path * 0b011..fetchlayer0 module is used from extdst4 processing path * 0b100..fetchlayer0 module is used from extdst1 processing path * 0b101..fetchlayer0 module is used from extdst5 processing path */ #define IRIS_MVPL_FETCHLAYER704_STATUS_fetchlayer0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER704_STATUS_fetchlayer0_sel_SHIFT)) & IRIS_MVPL_FETCHLAYER704_STATUS_fetchlayer0_sel_MASK) /*! @} */ /*! @name MATRIX736_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX736_LOCKUNLOCK_matrix4_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX736_LOCKUNLOCK_matrix4_LockUnlock_SHIFT (0U) /*! matrix4_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_MATRIX736_LOCKUNLOCK_matrix4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX736_LOCKUNLOCK_matrix4_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX736_LOCKUNLOCK_matrix4_LockUnlock_MASK) /*! @} */ /*! @name MATRIX736_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_LockStatus_MASK (0x1U) #define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_LockStatus_SHIFT (0U) /*! matrix4_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_LockStatus_MASK) #define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_PrivilegeStatus_SHIFT (4U) /*! matrix4_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_PrivilegeStatus_MASK) #define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_FreezeStatus_SHIFT (8U) /*! matrix4_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_FreezeStatus_MASK) /*! @} */ /*! @name MATRIX4_DYNAMIC - Dynamic pixel engine configuration for matrix4 */ /*! @{ */ #define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_src_sel_MASK (0x3FU) #define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_src_sel_SHIFT (0U) /*! matrix4_src_sel - Selection of the source for the src input of the matrix4 module * 0b000000..Unit matrix4 input port src is disabled * 0b001010..Unit matrix4 input port src is connected to output of unit blitblend9 * 0b010110..Unit matrix4 input port src is connected to output of unit fetchdecode0 */ #define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_src_sel_SHIFT)) & IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_src_sel_MASK) #define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_clken_MASK (0x3000000U) #define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_clken_SHIFT (24U) /*! matrix4_clken - Enable of matrix4 clock (this setting has to be the same for all modules of one * processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for matrix4 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for matrix4 is without gating */ #define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_clken_SHIFT)) & IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_clken_MASK) /*! @} */ /*! @name MATRIX4_STATUS - Status information for pixel engine configuration of matrix4 */ /*! @{ */ #define IRIS_MVPL_MATRIX4_STATUS_matrix4_sel_MASK (0x70000U) #define IRIS_MVPL_MATRIX4_STATUS_matrix4_sel_SHIFT (16U) /*! matrix4_sel - Status of the connection of the matrix4 module * 0b000..matrix4 module is not used * 0b001..matrix4 module is used from store9 processing path * 0b010..matrix4 module is used from extdst0 processing path * 0b011..matrix4 module is used from extdst4 processing path * 0b100..matrix4 module is used from extdst1 processing path * 0b101..matrix4 module is used from extdst5 processing path */ #define IRIS_MVPL_MATRIX4_STATUS_matrix4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_STATUS_matrix4_sel_SHIFT)) & IRIS_MVPL_MATRIX4_STATUS_matrix4_sel_MASK) /*! @} */ /*! @name HSCALER768_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER768_LOCKUNLOCK_hscaler4_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_HSCALER768_LOCKUNLOCK_hscaler4_LockUnlock_SHIFT (0U) /*! hscaler4_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_HSCALER768_LOCKUNLOCK_hscaler4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER768_LOCKUNLOCK_hscaler4_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER768_LOCKUNLOCK_hscaler4_LockUnlock_MASK) /*! @} */ /*! @name HSCALER768_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_LockStatus_MASK (0x1U) #define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_LockStatus_SHIFT (0U) /*! hscaler4_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_LockStatus_MASK) #define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_PrivilegeStatus_SHIFT (4U) /*! hscaler4_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_PrivilegeStatus_MASK) #define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_FreezeStatus_SHIFT (8U) /*! hscaler4_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_FreezeStatus_MASK) /*! @} */ /*! @name HSCALER4_DYNAMIC - Dynamic pixel engine configuration for hscaler4 */ /*! @{ */ #define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_src_sel_MASK (0x3FU) #define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_src_sel_SHIFT (0U) /*! hscaler4_src_sel - Selection of the source for the src input of the hscaler4 module * 0b000000..Unit hscaler4 input port src is disabled * 0b010110..Unit hscaler4 input port src is connected to output of unit fetchdecode0 * 0b011011..Unit hscaler4 input port src is connected to output of unit matrix4 * 0b011101..Unit hscaler4 input port src is connected to output of unit vscaler4 */ #define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_src_sel_SHIFT)) & IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_src_sel_MASK) #define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_clken_MASK (0x3000000U) #define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_clken_SHIFT (24U) /*! hscaler4_clken - Enable of hscaler4 clock (this setting has to be the same for all modules of * one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for hscaler4 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for hscaler4 is without gating */ #define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_clken_SHIFT)) & IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_clken_MASK) /*! @} */ /*! @name HSCALER4_STATUS - Status information for pixel engine configuration of hscaler4 */ /*! @{ */ #define IRIS_MVPL_HSCALER4_STATUS_hscaler4_sel_MASK (0x70000U) #define IRIS_MVPL_HSCALER4_STATUS_hscaler4_sel_SHIFT (16U) /*! hscaler4_sel - Status of the connection of the hscaler4 module * 0b000..hscaler4 module is not used * 0b001..hscaler4 module is used from store9 processing path * 0b010..hscaler4 module is used from extdst0 processing path * 0b011..hscaler4 module is used from extdst4 processing path * 0b100..hscaler4 module is used from extdst1 processing path * 0b101..hscaler4 module is used from extdst5 processing path */ #define IRIS_MVPL_HSCALER4_STATUS_hscaler4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_STATUS_hscaler4_sel_SHIFT)) & IRIS_MVPL_HSCALER4_STATUS_hscaler4_sel_MASK) /*! @} */ /*! @name VSCALER800_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER800_LOCKUNLOCK_vscaler4_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_VSCALER800_LOCKUNLOCK_vscaler4_LockUnlock_SHIFT (0U) /*! vscaler4_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_VSCALER800_LOCKUNLOCK_vscaler4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER800_LOCKUNLOCK_vscaler4_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER800_LOCKUNLOCK_vscaler4_LockUnlock_MASK) /*! @} */ /*! @name VSCALER800_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_LockStatus_MASK (0x1U) #define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_LockStatus_SHIFT (0U) /*! vscaler4_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_LockStatus_MASK) #define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_PrivilegeStatus_SHIFT (4U) /*! vscaler4_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_PrivilegeStatus_MASK) #define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_FreezeStatus_SHIFT (8U) /*! vscaler4_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_FreezeStatus_MASK) /*! @} */ /*! @name VSCALER4_DYNAMIC - Dynamic pixel engine configuration for vscaler4 */ /*! @{ */ #define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_src_sel_MASK (0x3FU) #define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_src_sel_SHIFT (0U) /*! vscaler4_src_sel - Selection of the source for the src input of the vscaler4 module * 0b000000..Unit vscaler4 input port src is disabled * 0b010110..Unit vscaler4 input port src is connected to output of unit fetchdecode0 * 0b011011..Unit vscaler4 input port src is connected to output of unit matrix4 * 0b011100..Unit vscaler4 input port src is connected to output of unit hscaler4 */ #define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_src_sel_SHIFT)) & IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_src_sel_MASK) #define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_clken_MASK (0x3000000U) #define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_clken_SHIFT (24U) /*! vscaler4_clken - Enable of vscaler4 clock (this setting has to be the same for all modules of * one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for vscaler4 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for vscaler4 is without gating */ #define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_clken_SHIFT)) & IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_clken_MASK) /*! @} */ /*! @name VSCALER4_STATUS - Status information for pixel engine configuration of vscaler4 */ /*! @{ */ #define IRIS_MVPL_VSCALER4_STATUS_vscaler4_sel_MASK (0x70000U) #define IRIS_MVPL_VSCALER4_STATUS_vscaler4_sel_SHIFT (16U) /*! vscaler4_sel - Status of the connection of the vscaler4 module * 0b000..vscaler4 module is not used * 0b001..vscaler4 module is used from store9 processing path * 0b010..vscaler4 module is used from extdst0 processing path * 0b011..vscaler4 module is used from extdst4 processing path * 0b100..vscaler4 module is used from extdst1 processing path * 0b101..vscaler4 module is used from extdst5 processing path */ #define IRIS_MVPL_VSCALER4_STATUS_vscaler4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_STATUS_vscaler4_sel_SHIFT)) & IRIS_MVPL_VSCALER4_STATUS_vscaler4_sel_MASK) /*! @} */ /*! @name MATRIX832_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX832_LOCKUNLOCK_matrix5_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX832_LOCKUNLOCK_matrix5_LockUnlock_SHIFT (0U) /*! matrix5_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_MATRIX832_LOCKUNLOCK_matrix5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX832_LOCKUNLOCK_matrix5_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX832_LOCKUNLOCK_matrix5_LockUnlock_MASK) /*! @} */ /*! @name MATRIX832_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_LockStatus_MASK (0x1U) #define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_LockStatus_SHIFT (0U) /*! matrix5_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_LockStatus_MASK) #define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_PrivilegeStatus_SHIFT (4U) /*! matrix5_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_PrivilegeStatus_MASK) #define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_FreezeStatus_SHIFT (8U) /*! matrix5_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_FreezeStatus_MASK) /*! @} */ /*! @name MATRIX5_DYNAMIC - Dynamic pixel engine configuration for matrix5 */ /*! @{ */ #define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_src_sel_MASK (0x3FU) #define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_src_sel_SHIFT (0U) /*! matrix5_src_sel - Selection of the source for the src input of the matrix5 module * 0b000000..Unit matrix5 input port src is disabled * 0b001010..Unit matrix5 input port src is connected to output of unit blitblend9 * 0b011000..Unit matrix5 input port src is connected to output of unit fetchdecode1 */ #define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_src_sel_SHIFT)) & IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_src_sel_MASK) #define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_clken_MASK (0x3000000U) #define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_clken_SHIFT (24U) /*! matrix5_clken - Enable of matrix5 clock (this setting has to be the same for all modules of one * processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for matrix5 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for matrix5 is without gating */ #define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_clken_SHIFT)) & IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_clken_MASK) /*! @} */ /*! @name MATRIX5_STATUS - Status information for pixel engine configuration of matrix5 */ /*! @{ */ #define IRIS_MVPL_MATRIX5_STATUS_matrix5_sel_MASK (0x70000U) #define IRIS_MVPL_MATRIX5_STATUS_matrix5_sel_SHIFT (16U) /*! matrix5_sel - Status of the connection of the matrix5 module * 0b000..matrix5 module is not used * 0b001..matrix5 module is used from store9 processing path * 0b010..matrix5 module is used from extdst0 processing path * 0b011..matrix5 module is used from extdst4 processing path * 0b100..matrix5 module is used from extdst1 processing path * 0b101..matrix5 module is used from extdst5 processing path */ #define IRIS_MVPL_MATRIX5_STATUS_matrix5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_STATUS_matrix5_sel_SHIFT)) & IRIS_MVPL_MATRIX5_STATUS_matrix5_sel_MASK) /*! @} */ /*! @name HSCALER864_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER864_LOCKUNLOCK_hscaler5_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_HSCALER864_LOCKUNLOCK_hscaler5_LockUnlock_SHIFT (0U) /*! hscaler5_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_HSCALER864_LOCKUNLOCK_hscaler5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER864_LOCKUNLOCK_hscaler5_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER864_LOCKUNLOCK_hscaler5_LockUnlock_MASK) /*! @} */ /*! @name HSCALER864_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_LockStatus_MASK (0x1U) #define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_LockStatus_SHIFT (0U) /*! hscaler5_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_LockStatus_MASK) #define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_PrivilegeStatus_SHIFT (4U) /*! hscaler5_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_PrivilegeStatus_MASK) #define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_FreezeStatus_SHIFT (8U) /*! hscaler5_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_FreezeStatus_MASK) /*! @} */ /*! @name HSCALER5_DYNAMIC - Dynamic pixel engine configuration for hscaler5 */ /*! @{ */ #define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_src_sel_MASK (0x3FU) #define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_src_sel_SHIFT (0U) /*! hscaler5_src_sel - Selection of the source for the src input of the hscaler5 module * 0b000000..Unit hscaler5 input port src is disabled * 0b011000..Unit hscaler5 input port src is connected to output of unit fetchdecode1 * 0b011110..Unit hscaler5 input port src is connected to output of unit matrix5 * 0b100000..Unit hscaler5 input port src is connected to output of unit vscaler5 */ #define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_src_sel_SHIFT)) & IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_src_sel_MASK) #define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_clken_MASK (0x3000000U) #define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_clken_SHIFT (24U) /*! hscaler5_clken - Enable of hscaler5 clock (this setting has to be the same for all modules of * one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for hscaler5 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for hscaler5 is without gating */ #define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_clken_SHIFT)) & IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_clken_MASK) /*! @} */ /*! @name HSCALER5_STATUS - Status information for pixel engine configuration of hscaler5 */ /*! @{ */ #define IRIS_MVPL_HSCALER5_STATUS_hscaler5_sel_MASK (0x70000U) #define IRIS_MVPL_HSCALER5_STATUS_hscaler5_sel_SHIFT (16U) /*! hscaler5_sel - Status of the connection of the hscaler5 module * 0b000..hscaler5 module is not used * 0b001..hscaler5 module is used from store9 processing path * 0b010..hscaler5 module is used from extdst0 processing path * 0b011..hscaler5 module is used from extdst4 processing path * 0b100..hscaler5 module is used from extdst1 processing path * 0b101..hscaler5 module is used from extdst5 processing path */ #define IRIS_MVPL_HSCALER5_STATUS_hscaler5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_STATUS_hscaler5_sel_SHIFT)) & IRIS_MVPL_HSCALER5_STATUS_hscaler5_sel_MASK) /*! @} */ /*! @name VSCALER896_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER896_LOCKUNLOCK_vscaler5_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_VSCALER896_LOCKUNLOCK_vscaler5_LockUnlock_SHIFT (0U) /*! vscaler5_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_VSCALER896_LOCKUNLOCK_vscaler5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER896_LOCKUNLOCK_vscaler5_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER896_LOCKUNLOCK_vscaler5_LockUnlock_MASK) /*! @} */ /*! @name VSCALER896_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_LockStatus_MASK (0x1U) #define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_LockStatus_SHIFT (0U) /*! vscaler5_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_LockStatus_MASK) #define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_PrivilegeStatus_SHIFT (4U) /*! vscaler5_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_PrivilegeStatus_MASK) #define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_FreezeStatus_SHIFT (8U) /*! vscaler5_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_FreezeStatus_MASK) /*! @} */ /*! @name VSCALER5_DYNAMIC - Dynamic pixel engine configuration for vscaler5 */ /*! @{ */ #define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_src_sel_MASK (0x3FU) #define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_src_sel_SHIFT (0U) /*! vscaler5_src_sel - Selection of the source for the src input of the vscaler5 module * 0b000000..Unit vscaler5 input port src is disabled * 0b011000..Unit vscaler5 input port src is connected to output of unit fetchdecode1 * 0b011110..Unit vscaler5 input port src is connected to output of unit matrix5 * 0b011111..Unit vscaler5 input port src is connected to output of unit hscaler5 */ #define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_src_sel_SHIFT)) & IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_src_sel_MASK) #define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_clken_MASK (0x3000000U) #define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_clken_SHIFT (24U) /*! vscaler5_clken - Enable of vscaler5 clock (this setting has to be the same for all modules of * one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for vscaler5 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for vscaler5 is without gating */ #define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_clken_SHIFT)) & IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_clken_MASK) /*! @} */ /*! @name VSCALER5_STATUS - Status information for pixel engine configuration of vscaler5 */ /*! @{ */ #define IRIS_MVPL_VSCALER5_STATUS_vscaler5_sel_MASK (0x70000U) #define IRIS_MVPL_VSCALER5_STATUS_vscaler5_sel_SHIFT (16U) /*! vscaler5_sel - Status of the connection of the vscaler5 module * 0b000..vscaler5 module is not used * 0b001..vscaler5 module is used from store9 processing path * 0b010..vscaler5 module is used from extdst0 processing path * 0b011..vscaler5 module is used from extdst4 processing path * 0b100..vscaler5 module is used from extdst1 processing path * 0b101..vscaler5 module is used from extdst5 processing path */ #define IRIS_MVPL_VSCALER5_STATUS_vscaler5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_STATUS_vscaler5_sel_SHIFT)) & IRIS_MVPL_VSCALER5_STATUS_vscaler5_sel_MASK) /*! @} */ /*! @name LAYERBLEND928_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND928_LOCKUNLOCK_layerblend0_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND928_LOCKUNLOCK_layerblend0_LockUnlock_SHIFT (0U) /*! layerblend0_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_LAYERBLEND928_LOCKUNLOCK_layerblend0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND928_LOCKUNLOCK_layerblend0_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND928_LOCKUNLOCK_layerblend0_LockUnlock_MASK) /*! @} */ /*! @name LAYERBLEND928_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_LockStatus_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_LockStatus_SHIFT (0U) /*! layerblend0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_LockStatus_MASK) #define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_PrivilegeStatus_SHIFT (4U) /*! layerblend0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_PrivilegeStatus_MASK) #define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_FreezeStatus_SHIFT (8U) /*! layerblend0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_FreezeStatus_MASK) /*! @} */ /*! @name LAYERBLEND0_DYNAMIC - Dynamic pixel engine configuration for layerblend0 */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_MASK (0x3FU) #define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_SHIFT (0U) /*! layerblend0_prim_sel - Selection of the source for the prim input of the layerblend0 module * 0b000000..Unit layerblend0 input port prim is disabled * 0b001010..Unit layerblend0 input port prim is connected to output of unit blitblend9 * 0b001100..Unit layerblend0 input port prim is connected to output of unit constframe0 * 0b001110..Unit layerblend0 input port prim is connected to output of unit constframe4 * 0b000000..Unit layerblend0 input port prim is connected to output of unit constframe1 * 0b010010..Unit layerblend0 input port prim is connected to output of unit constframe5 * 0b011011..Unit layerblend0 input port prim is connected to output of unit matrix4 * 0b011100..Unit layerblend0 input port prim is connected to output of unit hscaler4 * 0b011101..Unit layerblend0 input port prim is connected to output of unit vscaler4 * 0b011110..Unit layerblend0 input port prim is connected to output of unit matrix5 * 0b011111..Unit layerblend0 input port prim is connected to output of unit hscaler5 * 0b100000..Unit layerblend0 input port prim is connected to output of unit vscaler5 */ #define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_MASK) #define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_MASK (0x3F00U) #define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_SHIFT (8U) /*! layerblend0_sec_sel - Selection of the source for the sec input of the layerblend0 module * 0b000000..Unit layerblend0 input port sec is disabled * 0b010100..Unit layerblend0 input port sec is connected to output of unit fetchwarp2 * 0b010110..Unit layerblend0 input port sec is connected to output of unit fetchdecode0 * 0b011000..Unit layerblend0 input port sec is connected to output of unit fetchdecode1 * 0b011010..Unit layerblend0 input port sec is connected to output of unit fetchlayer0 * 0b011011..Unit layerblend0 input port sec is connected to output of unit matrix4 * 0b011100..Unit layerblend0 input port sec is connected to output of unit hscaler4 * 0b011101..Unit layerblend0 input port sec is connected to output of unit vscaler4 * 0b011110..Unit layerblend0 input port sec is connected to output of unit matrix5 * 0b011111..Unit layerblend0 input port sec is connected to output of unit hscaler5 * 0b100000..Unit layerblend0 input port sec is connected to output of unit vscaler5 */ #define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_MASK) #define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_clken_MASK (0x3000000U) #define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_clken_SHIFT (24U) /*! layerblend0_clken - Enable of layerblend0 clock (this setting has to be the same for all modules * of one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for layerblend0 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for layerblend0 is without gating */ #define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_clken_SHIFT)) & IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_clken_MASK) /*! @} */ /*! @name LAYERBLEND0_STATUS - Status information for pixel engine configuration of layerblend0 */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND0_STATUS_layerblend0_sel_MASK (0x70000U) #define IRIS_MVPL_LAYERBLEND0_STATUS_layerblend0_sel_SHIFT (16U) /*! layerblend0_sel - Status of the connection of the layerblend0 module * 0b000..layerblend0 module is not used * 0b001..layerblend0 module is used from store9 processing path * 0b010..layerblend0 module is used from extdst0 processing path * 0b011..layerblend0 module is used from extdst4 processing path * 0b100..layerblend0 module is used from extdst1 processing path * 0b101..layerblend0 module is used from extdst5 processing path */ #define IRIS_MVPL_LAYERBLEND0_STATUS_layerblend0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_STATUS_layerblend0_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND0_STATUS_layerblend0_sel_MASK) /*! @} */ /*! @name LAYERBLEND960_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND960_LOCKUNLOCK_layerblend1_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND960_LOCKUNLOCK_layerblend1_LockUnlock_SHIFT (0U) /*! layerblend1_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_LAYERBLEND960_LOCKUNLOCK_layerblend1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND960_LOCKUNLOCK_layerblend1_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND960_LOCKUNLOCK_layerblend1_LockUnlock_MASK) /*! @} */ /*! @name LAYERBLEND960_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_LockStatus_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_LockStatus_SHIFT (0U) /*! layerblend1_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_LockStatus_MASK) #define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_PrivilegeStatus_SHIFT (4U) /*! layerblend1_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_PrivilegeStatus_MASK) #define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_FreezeStatus_SHIFT (8U) /*! layerblend1_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_FreezeStatus_MASK) /*! @} */ /*! @name LAYERBLEND1_DYNAMIC - Dynamic pixel engine configuration for layerblend1 */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_MASK (0x3FU) #define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_SHIFT (0U) /*! layerblend1_prim_sel - Selection of the source for the prim input of the layerblend1 module * 0b000000..Unit layerblend1 input port prim is disabled * 0b001010..Unit layerblend1 input port prim is connected to output of unit blitblend9 * 0b001100..Unit layerblend1 input port prim is connected to output of unit constframe0 * 0b001110..Unit layerblend1 input port prim is connected to output of unit constframe4 * 0b000000..Unit layerblend1 input port prim is connected to output of unit constframe1 * 0b010010..Unit layerblend1 input port prim is connected to output of unit constframe5 * 0b011011..Unit layerblend1 input port prim is connected to output of unit matrix4 * 0b011100..Unit layerblend1 input port prim is connected to output of unit hscaler4 * 0b011101..Unit layerblend1 input port prim is connected to output of unit vscaler4 * 0b011110..Unit layerblend1 input port prim is connected to output of unit matrix5 * 0b011111..Unit layerblend1 input port prim is connected to output of unit hscaler5 * 0b100000..Unit layerblend1 input port prim is connected to output of unit vscaler5 * 0b100001..Unit layerblend1 input port prim is connected to output of unit layerblend0 */ #define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_MASK) #define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_MASK (0x3F00U) #define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_SHIFT (8U) /*! layerblend1_sec_sel - Selection of the source for the sec input of the layerblend1 module * 0b000000..Unit layerblend1 input port sec is disabled * 0b010100..Unit layerblend1 input port sec is connected to output of unit fetchwarp2 * 0b010110..Unit layerblend1 input port sec is connected to output of unit fetchdecode0 * 0b011000..Unit layerblend1 input port sec is connected to output of unit fetchdecode1 * 0b011010..Unit layerblend1 input port sec is connected to output of unit fetchlayer0 * 0b011011..Unit layerblend1 input port sec is connected to output of unit matrix4 * 0b011100..Unit layerblend1 input port sec is connected to output of unit hscaler4 * 0b011101..Unit layerblend1 input port sec is connected to output of unit vscaler4 * 0b011110..Unit layerblend1 input port sec is connected to output of unit matrix5 * 0b011111..Unit layerblend1 input port sec is connected to output of unit hscaler5 * 0b100000..Unit layerblend1 input port sec is connected to output of unit vscaler5 */ #define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_MASK) #define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_clken_MASK (0x3000000U) #define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_clken_SHIFT (24U) /*! layerblend1_clken - Enable of layerblend1 clock (this setting has to be the same for all modules * of one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for layerblend1 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for layerblend1 is without gating */ #define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_clken_SHIFT)) & IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_clken_MASK) /*! @} */ /*! @name LAYERBLEND1_STATUS - Status information for pixel engine configuration of layerblend1 */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1_STATUS_layerblend1_sel_MASK (0x70000U) #define IRIS_MVPL_LAYERBLEND1_STATUS_layerblend1_sel_SHIFT (16U) /*! layerblend1_sel - Status of the connection of the layerblend1 module * 0b000..layerblend1 module is not used * 0b001..layerblend1 module is used from store9 processing path * 0b010..layerblend1 module is used from extdst0 processing path * 0b011..layerblend1 module is used from extdst4 processing path * 0b100..layerblend1 module is used from extdst1 processing path * 0b101..layerblend1 module is used from extdst5 processing path */ #define IRIS_MVPL_LAYERBLEND1_STATUS_layerblend1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_STATUS_layerblend1_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND1_STATUS_layerblend1_sel_MASK) /*! @} */ /*! @name LAYERBLEND992_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND992_LOCKUNLOCK_layerblend2_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND992_LOCKUNLOCK_layerblend2_LockUnlock_SHIFT (0U) /*! layerblend2_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_LAYERBLEND992_LOCKUNLOCK_layerblend2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND992_LOCKUNLOCK_layerblend2_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND992_LOCKUNLOCK_layerblend2_LockUnlock_MASK) /*! @} */ /*! @name LAYERBLEND99_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_LockStatus_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_LockStatus_SHIFT (0U) /*! layerblend2_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_LockStatus_MASK) #define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_PrivilegeStatus_SHIFT (4U) /*! layerblend2_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_PrivilegeStatus_MASK) #define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_FreezeStatus_SHIFT (8U) /*! layerblend2_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_FreezeStatus_MASK) /*! @} */ /*! @name LAYERBLEND2_DYNAMIC - Dynamic pixel engine configuration for layerblend2 */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_MASK (0x3FU) #define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_SHIFT (0U) /*! layerblend2_prim_sel - Selection of the source for the prim input of the layerblend2 module * 0b000000..Unit layerblend2 input port prim is disabled * 0b001010..Unit layerblend2 input port prim is connected to output of unit blitblend9 * 0b001100..Unit layerblend2 input port prim is connected to output of unit constframe0 * 0b001110..Unit layerblend2 input port prim is connected to output of unit constframe4 * 0b000000..Unit layerblend2 input port prim is connected to output of unit constframe1 * 0b010010..Unit layerblend2 input port prim is connected to output of unit constframe5 * 0b011011..Unit layerblend2 input port prim is connected to output of unit matrix4 * 0b011100..Unit layerblend2 input port prim is connected to output of unit hscaler4 * 0b011101..Unit layerblend2 input port prim is connected to output of unit vscaler4 * 0b011110..Unit layerblend2 input port prim is connected to output of unit matrix5 * 0b011111..Unit layerblend2 input port prim is connected to output of unit hscaler5 * 0b100000..Unit layerblend2 input port prim is connected to output of unit vscaler5 * 0b100001..Unit layerblend2 input port prim is connected to output of unit layerblend0 * 0b100010..Unit layerblend2 input port prim is connected to output of unit layerblend1 */ #define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_MASK) #define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_MASK (0x3F00U) #define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_SHIFT (8U) /*! layerblend2_sec_sel - Selection of the source for the sec input of the layerblend2 module * 0b000000..Unit layerblend2 input port sec is disabled * 0b010100..Unit layerblend2 input port sec is connected to output of unit fetchwarp2 * 0b010110..Unit layerblend2 input port sec is connected to output of unit fetchdecode0 * 0b011000..Unit layerblend2 input port sec is connected to output of unit fetchdecode1 * 0b011010..Unit layerblend2 input port sec is connected to output of unit fetchlayer0 * 0b011011..Unit layerblend2 input port sec is connected to output of unit matrix4 * 0b011100..Unit layerblend2 input port sec is connected to output of unit hscaler4 * 0b011101..Unit layerblend2 input port sec is connected to output of unit vscaler4 * 0b011110..Unit layerblend2 input port sec is connected to output of unit matrix5 * 0b011111..Unit layerblend2 input port sec is connected to output of unit hscaler5 * 0b100000..Unit layerblend2 input port sec is connected to output of unit vscaler5 */ #define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_MASK) #define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_clken_MASK (0x3000000U) #define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_clken_SHIFT (24U) /*! layerblend2_clken - Enable of layerblend2 clock (this setting has to be the same for all modules * of one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for layerblend2 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for layerblend2 is without gating */ #define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_clken_SHIFT)) & IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_clken_MASK) /*! @} */ /*! @name LAYERBLEND2_STATUS - Status information for pixel engine configuration of layerblend2 */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND2_STATUS_layerblend2_sel_MASK (0x70000U) #define IRIS_MVPL_LAYERBLEND2_STATUS_layerblend2_sel_SHIFT (16U) /*! layerblend2_sel - Status of the connection of the layerblend2 module * 0b000..layerblend2 module is not used * 0b001..layerblend2 module is used from store9 processing path * 0b010..layerblend2 module is used from extdst0 processing path * 0b011..layerblend2 module is used from extdst4 processing path * 0b100..layerblend2 module is used from extdst1 processing path * 0b101..layerblend2 module is used from extdst5 processing path */ #define IRIS_MVPL_LAYERBLEND2_STATUS_layerblend2_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_STATUS_layerblend2_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND2_STATUS_layerblend2_sel_MASK) /*! @} */ /*! @name LAYERBLEND1024_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1024_LOCKUNLOCK_layerblend3_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND1024_LOCKUNLOCK_layerblend3_LockUnlock_SHIFT (0U) /*! layerblend3_LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_LAYERBLEND1024_LOCKUNLOCK_layerblend3_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1024_LOCKUNLOCK_layerblend3_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND1024_LOCKUNLOCK_layerblend3_LockUnlock_MASK) /*! @} */ /*! @name LAYERBLEND1024_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_LockStatus_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_LockStatus_SHIFT (0U) /*! layerblend3_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_LockStatus_MASK) #define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_PrivilegeStatus_SHIFT (4U) /*! layerblend3_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_PrivilegeStatus_MASK) #define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_FreezeStatus_SHIFT (8U) /*! layerblend3_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_FreezeStatus_MASK) /*! @} */ /*! @name LAYERBLEND3_DYNAMIC - Dynamic pixel engine configuration for layerblend3 */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_MASK (0x3FU) #define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_SHIFT (0U) /*! layerblend3_prim_sel - Selection of the source for the prim input of the layerblend3 module * 0b000000..Unit layerblend3 input port prim is disabled * 0b001010..Unit layerblend3 input port prim is connected to output of unit blitblend9 * 0b001100..Unit layerblend3 input port prim is connected to output of unit constframe0 * 0b001110..Unit layerblend3 input port prim is connected to output of unit constframe4 * 0b000000..Unit layerblend3 input port prim is connected to output of unit constframe1 * 0b010010..Unit layerblend3 input port prim is connected to output of unit constframe5 * 0b011011..Unit layerblend3 input port prim is connected to output of unit matrix4 * 0b011100..Unit layerblend3 input port prim is connected to output of unit hscaler4 * 0b011101..Unit layerblend3 input port prim is connected to output of unit vscaler4 * 0b011110..Unit layerblend3 input port prim is connected to output of unit matrix5 * 0b011111..Unit layerblend3 input port prim is connected to output of unit hscaler5 * 0b100000..Unit layerblend3 input port prim is connected to output of unit vscaler5 * 0b100001..Unit layerblend3 input port prim is connected to output of unit layerblend0 * 0b100010..Unit layerblend3 input port prim is connected to output of unit layerblend1 * 0b100011..Unit layerblend3 input port prim is connected to output of unit layerblend2 */ #define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_MASK) #define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_MASK (0x3F00U) #define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_SHIFT (8U) /*! layerblend3_sec_sel - Selection of the source for the sec input of the layerblend3 module * 0b000000..Unit layerblend3 input port sec is disabled * 0b010100..Unit layerblend3 input port sec is connected to output of unit fetchwarp2 * 0b010110..Unit layerblend3 input port sec is connected to output of unit fetchdecode0 * 0b011000..Unit layerblend3 input port sec is connected to output of unit fetchdecode1 * 0b011010..Unit layerblend3 input port sec is connected to output of unit fetchlayer0 * 0b011011..Unit layerblend3 input port sec is connected to output of unit matrix4 * 0b011100..Unit layerblend3 input port sec is connected to output of unit hscaler4 * 0b011101..Unit layerblend3 input port sec is connected to output of unit vscaler4 * 0b011110..Unit layerblend3 input port sec is connected to output of unit matrix5 * 0b011111..Unit layerblend3 input port sec is connected to output of unit hscaler5 * 0b100000..Unit layerblend3 input port sec is connected to output of unit vscaler5 */ #define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_MASK) #define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_clken_MASK (0x3000000U) #define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_clken_SHIFT (24U) /*! layerblend3_clken - Enable of layerblend3 clock (this setting has to be the same for all modules * of one processing pipeline). If a submodule is enabled and FULL is used, then the register * [endpoint_name]_clk must be set to 0x80. * 0b00..Clock for layerblend3 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for layerblend3 is without gating */ #define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_clken_SHIFT)) & IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_clken_MASK) /*! @} */ /*! @name LAYERBLEND3_STATUS - Status information for pixel engine configuration of layerblend3 */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND3_STATUS_layerblend3_sel_MASK (0x70000U) #define IRIS_MVPL_LAYERBLEND3_STATUS_layerblend3_sel_SHIFT (16U) /*! layerblend3_sel - Status of the connection of the layerblend3 module * 0b000..layerblend3 module is not used * 0b001..layerblend3 module is used from store9 processing path * 0b010..layerblend3 module is used from extdst0 processing path * 0b011..layerblend3 module is used from extdst4 processing path * 0b100..layerblend3 module is used from extdst1 processing path * 0b101..layerblend3 module is used from extdst5 processing path */ #define IRIS_MVPL_LAYERBLEND3_STATUS_layerblend3_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_STATUS_layerblend3_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND3_STATUS_layerblend3_sel_MASK) /*! @} */ /*! @name FETCHDECODE_LOCKUNLOCK_1 - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_1_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_1_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_1_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_1_LockUnlock_MASK) /*! @} */ /*! @name FETCHDECODE_LOCKSTATUS_1 - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_LockStatus_MASK) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_FreezeStatus_MASK) /*! @} */ /*! @name FETCHDECODE_STATICCONTRO_1L - Common static control options. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_ShdEn_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_ShdEn_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_ShdEn_MASK) #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_BaseAddressAutoUpdate_MASK (0xFF0000U) #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_BaseAddressAutoUpdate_SHIFT (16U) /*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded * from shadow at start of each frame. This update is then executed independently from other RWS * type fields. ShdEn must be enabled for this mode. */ #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_BaseAddressAutoUpdate_MASK) /*! @} */ /*! @name FETCHDECODE_BURSTBUFFERMANAGEMENT_1 - AXI interface buffer management register */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetNumBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetNumBuffers_SHIFT (0U) /*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of * 2. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetNumBuffers_MASK) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of * two may be specified as burst length. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_LineMode_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_LineMode_SHIFT (31U) /*! LineMode - Fetch buffer cache control. * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_LineMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_LineMode_MASK) /*! @} */ /*! @name FETCHDECODE_RINGBUFSTARTADDR0_1 - Ring buffer setup for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_1_RingBufStartAddr0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_1_RingBufStartAddr0_SHIFT (0U) /*! RingBufStartAddr0 - Start address of the ring buffer. Must be aligned to SetBurstLength x 8 bytes. */ #define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_1_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_1_RingBufStartAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_1_RingBufStartAddr0_MASK) /*! @} */ /*! @name FETCHDECODE_RINGBUFWRAPADDR0_1 - Ring buffer setup for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_1_RingBufWrapAddr0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_1_RingBufWrapAddr0_SHIFT (0U) /*! RingBufWrapAddr0 - End address of the ring buffer (last byte of the buffer plus one). */ #define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_1_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_1_RingBufWrapAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_1_RingBufWrapAddr0_MASK) /*! @} */ /*! @name FETCHDECODE_FRAMEPROPERTIES0_1 - Frame property setup for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_1_FieldId0_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_1_FieldId0_SHIFT (0U) /*! FieldId0 - Field identifier that is generated for subsequent units (0 = progressive frame or * interlaced field with even line indices, 1 = odd field). */ #define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_1_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_1_FieldId0_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_1_FieldId0_MASK) /*! @} */ /*! @name FETCHDECODE_BASEADDRESS0_1 - Source buffer base address of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_1_BaseAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_1_BaseAddress0_SHIFT (0U) /*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit * BaseAddress[0] has to be 0. */ #define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_1_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BASEADDRESS0_1_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE_BASEADDRESS0_1_BaseAddress0_MASK) /*! @} */ /*! @name FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1 - Source buffer attributes for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_Stride0_MASK (0xFFFFU) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_Stride0_SHIFT (0U) /*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel * width of 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_Stride0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_Stride0_MASK) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_BitsPerPixel0_MASK (0x3F0000U) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_BitsPerPixel0_SHIFT (16U) /*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or * 32. Exception: FetchEco does not support 18 and 24. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_BitsPerPixel0_MASK) /*! @} */ /*! @name FETCHDECODE_SOURCEBUFFERDIMENSION0_1 - Source buffer dimension of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineWidth0_SHIFT (0U) /*! LineWidth0 - Width of the source buffer of the layer in pixels minus one. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineWidth0_MASK) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineCount0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineCount0_SHIFT (16U) /*! LineCount0 - Number of lines of the source buffer of the layer minus one. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineCount0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineCount0_MASK) /*! @} */ /*! @name FETCHDECODE_COLORCOMPONENTBITS0_1 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsAlpha0_MASK (0xFU) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsAlpha0_SHIFT (0U) /*! ComponentBitsAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsAlpha0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsBlue0_MASK (0xF00U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsBlue0_SHIFT (8U) /*! ComponentBitsBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsBlue0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsGreen0_MASK (0xF0000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsGreen0_SHIFT (16U) /*! ComponentBitsGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsGreen0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsRed0_MASK (0xF000000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsRed0_SHIFT (24U) /*! ComponentBitsRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsRed0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ITUFormat0_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ITUFormat0_SHIFT (31U) /*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This * is compliant to ITU 656 standard. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ITUFormat0_MASK) /*! @} */ /*! @name FETCHDECODE_COLORCOMPONENTSHIFT0_1 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftAlpha0_MASK (0x1FU) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftAlpha0_SHIFT (0U) /*! ComponentShiftAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftAlpha0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftBlue0_MASK (0x1F00U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftBlue0_SHIFT (8U) /*! ComponentShiftBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftBlue0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftGreen0_MASK (0x1F0000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftGreen0_SHIFT (16U) /*! ComponentShiftGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftGreen0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftRed0_MASK (0x1F000000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftRed0_SHIFT (24U) /*! ComponentShiftRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftRed0_MASK) /*! @} */ /*! @name FETCHDECODE_LAYEROFFSET0_1 - Position of layer 0 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerXOffset0_SHIFT (0U) /*! LayerXOffset0 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerXOffset0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerYOffset0_SHIFT (16U) /*! LayerYOffset0 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerYOffset0_MASK) /*! @} */ /*! @name FETCHDECODE_CLIPWINDOWOFFSET0_1 - Clip window position for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowXOffset0_SHIFT (0U) /*! ClipWindowXOffset0 - Horizontal position (X). */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowXOffset0_MASK) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowYOffset0_SHIFT (16U) /*! ClipWindowYOffset0 - Vertical position (Y). */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowYOffset0_MASK) /*! @} */ /*! @name FETCHDECODE_CLIPWINDOWDIMENSIONS0_1 - Clip window size for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowWidth0_SHIFT (0U) /*! ClipWindowWidth0 - Width. */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowWidth0_MASK) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowHeight0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowHeight0_SHIFT (16U) /*! ClipWindowHeight0 - Height. */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowHeight0_MASK) /*! @} */ /*! @name FETCHDECODE_CONSTANTCOLOR0_1 - Constant color for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantAlpha0_MASK (0xFFU) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantAlpha0_SHIFT (0U) /*! ConstantAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantAlpha0_MASK) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantBlue0_MASK (0xFF00U) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantBlue0_SHIFT (8U) /*! ConstantBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantBlue0_MASK) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantGreen0_MASK (0xFF0000U) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantGreen0_SHIFT (16U) /*! ConstantGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantGreen0_MASK) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantRed0_MASK (0xFF000000U) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantRed0_SHIFT (24U) /*! ConstantRed0 - Red and Y (luma). */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantRed0_MASK) /*! @} */ /*! @name FETCHDECODE_LAYERPROPERTY0_1 - Common properties of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PaletteEnable0_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PaletteEnable0_SHIFT (0U) /*! PaletteEnable0 - Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower * bits of the lookup index are read from memory (PaletteIdxWidth), upper bits are set to index * of this layer. Palette output is extended by upper bits of index word read from memory (e.g. * to store alpha together with index). Result is mapped to color channels according to * ColorComponentBits/Shift settings. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PaletteEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_TileMode0_MASK (0x30U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_TileMode0_SHIFT (4U) /*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) * takes precedence if a pixel becomes subject to both tiling and clipping. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_TileMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_TileMode0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaSrcEnable0_MASK (0x100U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaSrcEnable0_SHIFT (8U) /*! AlphaSrcEnable0 - Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaConstEnable0_MASK (0x200U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaConstEnable0_SHIFT (9U) /*! AlphaConstEnable0 - Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaMaskEnable0_MASK (0x400U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaMaskEnable0_SHIFT (10U) /*! AlphaMaskEnable0 - Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaMaskEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaTransEnable0_MASK (0x800U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaTransEnable0_SHIFT (11U) /*! AlphaTransEnable0 - Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaSrcEnable0_MASK (0x1000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaSrcEnable0_SHIFT (12U) /*! RGBAlphaSrcEnable0 - Value 1 enables source alpha (stored together with color component in the * source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaConstEnable0_MASK (0x2000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaConstEnable0_SHIFT (13U) /*! RGBAlphaConstEnable0 - Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaMaskEnable0_MASK (0x4000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaMaskEnable0_SHIFT (14U) /*! RGBAlphaMaskEnable0 - Value 1 enables mask alpha (read by another Fetch unit from a separate * alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be * enabled for this field to have effect. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaMaskEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaTransEnable0_MASK (0x8000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaTransEnable0_SHIFT (15U) /*! RGBAlphaTransEnable0 - Value 1 enables transparent alpha (0 or 1 depending on RGB matching * ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PremulConstRGB0_MASK (0x10000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PremulConstRGB0_SHIFT (16U) /*! PremulConstRGB0 - When enabled (value 1) the values given by ConstantRed/Green/Blue are used * instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no * effect then. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PremulConstRGB0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_YUVConversionMode0_MASK (0x60000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_YUVConversionMode0_SHIFT (17U) /*! YUVConversionMode0 - Enables different kind of YUV to RGB conversions. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_YUVConversionMode0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_GammaRemoveEnable0_MASK (0x100000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_GammaRemoveEnable0_SHIFT (20U) /*! GammaRemoveEnable0 - Value 1 enables the stage to remove a gamma from RGB components. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_GammaRemoveEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_ClipWindowEnable0_MASK (0x40000000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_ClipWindowEnable0_SHIFT (30U) /*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip * window get the clip color, pixels inside the source or tiling color. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_ClipWindowEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_SourceBufferEnable0_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_SourceBufferEnable0_SHIFT (31U) /*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling * color is used only (TileMode TILE_PAD not allowed). */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_SourceBufferEnable0_MASK) /*! @} */ /*! @name FETCHDECODE_FRAMEDIMENSIONS_1 - Output frame dimension. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width minus one. */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameWidth_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height minus one. */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameHeight_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). If enabled, InputSelect must be set to INACTIVE. */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_EmptyFrame_MASK) /*! @} */ /*! @name FETCHDECODE_FRAMERESAMPLING_1 - Resampling options for output frame. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartX_MASK (0x3FU) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartX_SHIFT (0U) /*! StartX - X coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartX_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartX_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartY_MASK (0xFC0U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartY_SHIFT (6U) /*! StartY - Y coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartY_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartY_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaX_MASK (0x3F000U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaX_SHIFT (12U) /*! DeltaX - Increment of X coordinate for horizontal step in destination frame. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaX_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaX_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaY_MASK (0xFC0000U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaY_SHIFT (18U) /*! DeltaY - Increment of Y coordinate for vertical step in destination frame. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaY_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaY_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_SwapDirection_MASK (0x1000000U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_SwapDirection_SHIFT (24U) /*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied * for horizontal and DeltaX for vertical step on destination frame. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_SwapDirection_MASK) /*! @} */ /*! @name FETCHDECODE_DECODECONTROL_1 - Control options for RLAD decompression. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_CompressionMode_MASK (0x3U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_CompressionMode_SHIFT (0U) /*! CompressionMode - Algorithm that the encoder used for compression. * 0b00..Run-Length Adaptive Dithering (lossy compression). * 0b01..Run-Length Adaptive Dithering (lossy compression; uniform package size). * 0b10..Run-Length Adaptive (lossless compression). * 0b11..Standard Run-Length. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_CompressionMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_CompressionMode_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADEndianness_MASK (0x8000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADEndianness_SHIFT (15U) /*! RLADEndianness - Changes endianness of decoder for RL mode, does not affect any other CompressionModes * 0b0..Big endian format * 0b1..Little endian format */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADEndianness(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADEndianness_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADEndianness_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsRed_MASK (0xF0000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsRed_SHIFT (16U) /*! RLADCompBitsRed - Maximum for average number of bits per compressed pixel for Red or Y (luma) * channel. This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsRed_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsGreen_MASK (0xF00000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsGreen_SHIFT (20U) /*! RLADCompBitsGreen - Maximum for average number of bits per compressed pixel for Green or U * (chroma) channel. This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsGreen_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsBlue_MASK (0xF000000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsBlue_SHIFT (24U) /*! RLADCompBitsBlue - Maximum for average number of bits per compressed pixel for Blue or V * (chroma) channel. This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsBlue_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsAlpha_MASK (0xF0000000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsAlpha_SHIFT (28U) /*! RLADCompBitsAlpha - Maximum for average number of bits per compressed pixel for Alpha channel. * This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsAlpha_MASK) /*! @} */ /*! @name FETCHDECODE_SOURCEBUFFERLENGTH_1 - Source buffer length for compressed data. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_1_RLEWords_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_1_RLEWords_SHIFT (0U) /*! RLEWords - Number of 32-bit words minus one that are required to decode the run length encoded source buffer. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_1_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_1_RLEWords_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_1_RLEWords_MASK) /*! @} */ /*! @name FETCHDECODE_CONTROL_1 - Shared common control settings for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CONTROL_1_RasterMode_MASK (0x7U) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_RasterMode_SHIFT (0U) /*! RasterMode - Selects a method how to generate source buffer sample points. * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot/RotL only] Arbitrary warping (filter is active). Coordinates are read from frame * input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_1_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_RasterMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_RasterMode_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_InputSelect_MASK (0x18U) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_InputSelect_SHIFT (3U) /*! InputSelect - Selects function for the frame input port. * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define IRIS_MVPL_FETCHDECODE_CONTROL_1_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_InputSelect_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_InputSelect_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_YUV422UpsamplingMode_MASK (0x20U) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_YUV422UpsamplingMode_SHIFT (5U) /*! YUV422UpsamplingMode - Selects a method for horizontal up-sampling of YUV 4:2:2/4:2:0 input data. * 0b0..Replicate mode for interspersed samples (UV samples between Y samples). * 0b1..Interpolate mode for coaligned samples (UV samples at Y sample positions). */ #define IRIS_MVPL_FETCHDECODE_CONTROL_1_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_YUV422UpsamplingMode_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_RawPixel_MASK (0x80U) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_RawPixel_SHIFT (7U) /*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced * for all layers by fixed values that allow passing the pixel data read from memory unchanged * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color * are deactived. Skip and Tile pixels are not affected by this setting. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_1_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_RawPixel_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_RawPixel_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_PaletteIdxWidth_MASK (0x700U) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_PaletteIdxWidth_SHIFT (8U) /*! PaletteIdxWidth - Number minus one of least significant bits of pixel data read from the source * buffer that are used as index value for color palette look-up. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_1_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_PaletteIdxWidth_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_ClipColor_MASK (0x10000U) #define IRIS_MVPL_FETCHDECODE_CONTROL_1_ClipColor_SHIFT (16U) /*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer. * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_1_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_ClipColor_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_ClipColor_MASK) /*! @} */ /*! @name FETCHDECODE_CONTROLTRIGGER_1 - Shadow load trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_1_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_1_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_1_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_1_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_1_ShdTokGen_MASK) /*! @} */ /*! @name FETCHDECODE_START_1 - Frame start trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_START_1_Start_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_START_1_Start_SHIFT (0U) /*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only). */ #define IRIS_MVPL_FETCHDECODE_START_1_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_START_1_Start_SHIFT)) & IRIS_MVPL_FETCHDECODE_START_1_Start_MASK) /*! @} */ /*! @name FETCHDECODE_FETCHTYPE_1 - Fetch unit type. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FETCHTYPE_1_FetchType_MASK (0xFU) #define IRIS_MVPL_FETCHDECODE_FETCHTYPE_1_FetchType_SHIFT (0U) /*! FetchType - This field can be used to determine what kind of fetch unit this is. * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. */ #define IRIS_MVPL_FETCHDECODE_FETCHTYPE_1_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FETCHTYPE_1_FetchType_SHIFT)) & IRIS_MVPL_FETCHDECODE_FETCHTYPE_1_FetchType_MASK) /*! @} */ /*! @name FETCHDECODE_DECODERSTATUS_1 - Status information of the RLAD decoder. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooSmall_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooSmall_SHIFT (0U) /*! BufferTooSmall - The buffer size given by RLEWords is too small. No complete output frame could be decoded. */ #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooSmall_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooSmall_MASK) #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooLarge_MASK (0x2U) #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooLarge_SHIFT (1U) /*! BufferTooLarge - The buffer size given by RLEWords is too large. A complete output frame could * be decoded, but more data was read than necessary. */ #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooLarge(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooLarge_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooLarge_MASK) /*! @} */ /*! @name FETCHDECODE_READADDRESS0_1 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_READADDRESS0_1_ReadAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_READADDRESS0_1_ReadAddress0_SHIFT (0U) /*! ReadAddress0 - Last burst address that was read from the layer's source buffer. */ #define IRIS_MVPL_FETCHDECODE_READADDRESS0_1_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_READADDRESS0_1_ReadAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE_READADDRESS0_1_ReadAddress0_MASK) /*! @} */ /*! @name FETCHDECODE_BURSTBUFFERPROPERTIES_1 - Burst buffer properties. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_ManagedBurstBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_ManagedBurstBuffers_SHIFT (0U) /*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_ManagedBurstBuffers_MASK) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_BurstLengthForMaxBuffers_MASK (0x1F00U) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_BurstLengthForMaxBuffers_SHIFT (8U) /*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name FETCHDECODE_STATUS_1 - Status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_STATUS_1_WriteTimeout_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_STATUS_1_WriteTimeout_SHIFT (0U) /*! WriteTimeout - Timeout detected when writing to the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHDECODE_STATUS_1_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATUS_1_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATUS_1_WriteTimeout_MASK) #define IRIS_MVPL_FETCHDECODE_STATUS_1_ReadTimeout_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE_STATUS_1_ReadTimeout_SHIFT (4U) /*! ReadTimeout - Timeout detected when reading from the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHDECODE_STATUS_1_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATUS_1_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATUS_1_ReadTimeout_MASK) /*! @} */ /*! @name FETCHDECODE_HIDDENSTATUS_1 - Hidden status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBusy_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBusy_SHIFT (0U) /*! StatusBusy - Fetch unit is busy. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBusy_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBuffersIdle_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusRequest_MASK (0x20U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusRequest_SHIFT (5U) /*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusRequest_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusComplete_MASK (0x40U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusComplete_SHIFT (6U) /*! StatusComplete - Fetch unit completed all requested AXI transfers. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusComplete_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_ShadowStatus_MASK (0xFF00U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_ShadowStatus_SHIFT (8U) /*! ShadowStatus - Shadow load status for all layers (layer index = bit index). */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_ShadowStatus_MASK) /*! @} */ /*! @name COLORPALETTE_1 - Color palette look up table. */ /*! @{ */ #define IRIS_MVPL_COLORPALETTE_1_ColorPalette_MASK (0xFFFFFFU) #define IRIS_MVPL_COLORPALETTE_1_ColorPalette_SHIFT (0U) /*! ColorPalette - Entry of the color palette look-up table */ #define IRIS_MVPL_COLORPALETTE_1_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COLORPALETTE_1_ColorPalette_SHIFT)) & IRIS_MVPL_COLORPALETTE_1_ColorPalette_MASK) /*! @} */ /*! @name FETCHWARP9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP9_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHWARP9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHWARP9_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name FETCHWARP9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHWARP9_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP9_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP9_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name FETCHWARP9_STATICCONTROL - Common static control options. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_FETCHWARP9_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U) /*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded * from shadow at start of each frame. This update is then executed independently from other RWS * type fields. ShdEn must be enabled for this mode. */ #define IRIS_MVPL_FETCHWARP9_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHWARP9_STATICCONTROL_BaseAddressAutoUpdate_MASK) #define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdLdReqSticky_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdLdReqSticky_SHIFT (24U) /*! ShdLdReqSticky - Shadow load request flags for each layer (always load). See description of * register TriggerEnable for further information. */ #define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdLdReqSticky(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdLdReqSticky_SHIFT)) & IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdLdReqSticky_MASK) /*! @} */ /*! @name FETCHWARP9_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U) /*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of * 2. */ #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK) #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of * two may be specified as burst length. */ #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK) #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U) /*! LineMode - Fetch buffer cache control. * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_LineMode_MASK) /*! @} */ /*! @name FETCHWARP9_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP9_BASEADDRESS0_BaseAddress0_SHIFT (0U) /*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit * BaseAddress[0] has to be 0. */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS0_BaseAddress0_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U) /*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel * width of 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U) /*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or * 32. Exception: FetchEco does not support 18 and 24. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U) /*! LineWidth0 - Width of the source buffer of the layer in pixels minus one. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U) /*! LineCount0 - Number of lines of the source buffer of the layer minus one. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineCount0_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U) /*! ComponentBitsAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U) /*! ComponentBitsBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U) /*! ComponentBitsGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U) /*! ComponentBitsRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U) /*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This * is compliant to ITU 656 standard. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ITUFormat0_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U) /*! ComponentShiftAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U) /*! ComponentShiftBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U) /*! ComponentShiftGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U) /*! ComponentShiftRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK) /*! @} */ /*! @name FETCHWARP9_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerXOffset0_SHIFT (0U) /*! LayerXOffset0 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerXOffset0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerYOffset0_SHIFT (16U) /*! LayerYOffset0 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerYOffset0_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U) /*! ClipWindowXOffset0 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U) /*! ClipWindowYOffset0 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U) /*! ClipWindowWidth0 - Width. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U) /*! ClipWindowHeight0 - Height. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK) /*! @} */ /*! @name FETCHWARP9_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U) /*! ConstantAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantAlpha0_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U) /*! ConstantBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantBlue0_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U) /*! ConstantGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantGreen0_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U) /*! ConstantRed0 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantRed0_MASK) /*! @} */ /*! @name FETCHWARP9_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_TileMode0_MASK (0x30U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_TileMode0_SHIFT (4U) /*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) * takes precedence if a pixel becomes subject to both tiling and clipping. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_TileMode0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U) /*! AlphaSrcEnable0 - Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U) /*! AlphaConstEnable0 - Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaMaskEnable0_MASK (0x400U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT (10U) /*! AlphaMaskEnable0 - Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaMaskEnable0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U) /*! AlphaTransEnable0 - Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U) /*! RGBAlphaSrcEnable0 - Value 1 enables source alpha (stored together with color component in the * source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U) /*! RGBAlphaConstEnable0 - Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT (14U) /*! RGBAlphaMaskEnable0 - Value 1 enables mask alpha (read by another Fetch unit from a separate * alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be * enabled for this field to have effect. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U) /*! RGBAlphaTransEnable0 - Value 1 enables transparent alpha (0 or 1 depending on RGB matching * ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U) /*! PremulConstRGB0 - When enabled (value 1) the values given by ConstantRed/Green/Blue are used * instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no * effect then. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_PremulConstRGB0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U) /*! YUVConversionMode0 - Enables different kind of YUV to RGB conversions. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_YUVConversionMode0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U) /*! GammaRemoveEnable0 - Value 1 enables the stage to remove a gamma from RGB components. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_GammaRemoveEnable0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U) /*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip * window get the clip color, pixels inside the source or tiling color. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_ClipWindowEnable0_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U) /*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling * color is used only (TileMode TILE_PAD not allowed). */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_SourceBufferEnable0_MASK) /*! @} */ /*! @name FETCHWARP9_BASEADDRESS1 - Source buffer base address of layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS1_BaseAddress1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP9_BASEADDRESS1_BaseAddress1_SHIFT (0U) /*! BaseAddress1 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS1_BaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS1_BaseAddress1_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS1_BaseAddress1_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES1 - Source buffer attributes for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_Stride1_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT (0U) /*! Stride1 - See Stride0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_Stride1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_Stride1_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT (16U) /*! BitsPerPixel1 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERDIMENSION1 - Source buffer dimensions of layer 1, */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineWidth1_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT (0U) /*! LineWidth1 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineWidth1_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineCount1_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT (16U) /*! LineCount1 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineCount1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineCount1_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTBITS1 - Size of color components for RGB, YUV and index formats (layer 1). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK (0xFU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT (0U) /*! ComponentBitsAlpha1 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT (8U) /*! ComponentBitsBlue1 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT (16U) /*! ComponentBitsGreen1 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT (24U) /*! ComponentBitsRed1 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ITUFormat1_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ITUFormat1_SHIFT (31U) /*! ITUFormat1 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ITUFormat1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ITUFormat1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ITUFormat1_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTSHIFT1 - Bit position of color components for RGB, YUV and index formats (layer 1). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT (0U) /*! ComponentShiftAlpha1 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT (8U) /*! ComponentShiftBlue1 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT (16U) /*! ComponentShiftGreen1 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT (24U) /*! ComponentShiftRed1 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK) /*! @} */ /*! @name FETCHWARP9_LAYEROFFSET1 - Position of layer 1 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerXOffset1_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerXOffset1_SHIFT (0U) /*! LayerXOffset1 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerXOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerXOffset1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerYOffset1_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerYOffset1_SHIFT (16U) /*! LayerYOffset1 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerYOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerYOffset1_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWOFFSET1 - Clip window position for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT (0U) /*! ClipWindowXOffset1 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT (16U) /*! ClipWindowYOffset1 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS1 - Clip window size for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT (0U) /*! ClipWindowWidth1 - Width. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT (16U) /*! ClipWindowHeight1 - Height. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK) /*! @} */ /*! @name FETCHWARP9_CONSTANTCOLOR1 - Constant color for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantAlpha1_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantAlpha1_SHIFT (0U) /*! ConstantAlpha1 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantAlpha1_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantBlue1_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantBlue1_SHIFT (8U) /*! ConstantBlue1 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantBlue1_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantGreen1_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantGreen1_SHIFT (16U) /*! ConstantGreen1 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantGreen1_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantRed1_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantRed1_SHIFT (24U) /*! ConstantRed1 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantRed1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantRed1_MASK) /*! @} */ /*! @name FETCHWARP9_LAYERPROPERTY1 - Common properties of layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_TileMode1_MASK (0x30U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_TileMode1_SHIFT (4U) /*! TileMode1 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_TileMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_TileMode1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_TileMode1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaSrcEnable1_MASK (0x100U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT (8U) /*! AlphaSrcEnable1 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaSrcEnable1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaConstEnable1_MASK (0x200U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaConstEnable1_SHIFT (9U) /*! AlphaConstEnable1 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaConstEnable1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaMaskEnable1_MASK (0x400U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaMaskEnable1_SHIFT (10U) /*! AlphaMaskEnable1 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaMaskEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaMaskEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaMaskEnable1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaTransEnable1_MASK (0x800U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaTransEnable1_SHIFT (11U) /*! AlphaTransEnable1 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaTransEnable1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT (12U) /*! RGBAlphaSrcEnable1 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT (13U) /*! RGBAlphaConstEnable1 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaMaskEnable1_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaMaskEnable1_SHIFT (14U) /*! RGBAlphaMaskEnable1 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaMaskEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaMaskEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaMaskEnable1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT (15U) /*! RGBAlphaTransEnable1 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_PremulConstRGB1_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_PremulConstRGB1_SHIFT (16U) /*! PremulConstRGB1 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_PremulConstRGB1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_PremulConstRGB1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_PremulConstRGB1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_YUVConversionMode1_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_YUVConversionMode1_SHIFT (17U) /*! YUVConversionMode1 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_YUVConversionMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_YUVConversionMode1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_YUVConversionMode1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_GammaRemoveEnable1_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT (20U) /*! GammaRemoveEnable1 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_GammaRemoveEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_GammaRemoveEnable1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_ClipWindowEnable1_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_ClipWindowEnable1_SHIFT (30U) /*! ClipWindowEnable1 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_ClipWindowEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_ClipWindowEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_ClipWindowEnable1_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_SourceBufferEnable1_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_SourceBufferEnable1_SHIFT (31U) /*! SourceBufferEnable1 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_SourceBufferEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_SourceBufferEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_SourceBufferEnable1_MASK) /*! @} */ /*! @name FETCHWARP9_BASEADDRESS2 - Source buffer base address of layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS2_BaseAddress2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP9_BASEADDRESS2_BaseAddress2_SHIFT (0U) /*! BaseAddress2 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS2_BaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS2_BaseAddress2_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS2_BaseAddress2_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES2 - Source buffer attributes for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_Stride2_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT (0U) /*! Stride2 - See Stride0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_Stride2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_Stride2_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT (16U) /*! BitsPerPixel2 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERDIMENSION2 - Source buffer dimension of layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineWidth2_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT (0U) /*! LineWidth2 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineWidth2_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineCount2_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT (16U) /*! LineCount2 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineCount2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineCount2_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTBITS2 - Size of color components for RGB, YUV and index formats (layer 2). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK (0xFU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT (0U) /*! ComponentBitsAlpha2 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT (8U) /*! ComponentBitsBlue2 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT (16U) /*! ComponentBitsGreen2 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT (24U) /*! ComponentBitsRed2 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ITUFormat2_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ITUFormat2_SHIFT (31U) /*! ITUFormat2 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ITUFormat2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ITUFormat2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ITUFormat2_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTSHIFT2 - Bit position of color components for RGB, YUV and index formats (layer 2). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT (0U) /*! ComponentShiftAlpha2 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT (8U) /*! ComponentShiftBlue2 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT (16U) /*! ComponentShiftGreen2 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT (24U) /*! ComponentShiftRed2 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK) /*! @} */ /*! @name FETCHWARP9_LAYEROFFSET2 - Position of layer 2 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerXOffset2_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerXOffset2_SHIFT (0U) /*! LayerXOffset2 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerXOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerXOffset2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerYOffset2_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerYOffset2_SHIFT (16U) /*! LayerYOffset2 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerYOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerYOffset2_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWOFFSET2 - Clip window position for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT (0U) /*! ClipWindowXOffset2 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT (16U) /*! ClipWindowYOffset2 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS2 - Clip window size for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT (0U) /*! ClipWindowWidth2 - Width. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT (16U) /*! ClipWindowHeight2 - Height. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK) /*! @} */ /*! @name FETCHWARP9_CONSTANTCOLOR2 - Constant color for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantAlpha2_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantAlpha2_SHIFT (0U) /*! ConstantAlpha2 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantAlpha2_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantBlue2_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantBlue2_SHIFT (8U) /*! ConstantBlue2 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantBlue2_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantGreen2_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantGreen2_SHIFT (16U) /*! ConstantGreen2 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantGreen2_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantRed2_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantRed2_SHIFT (24U) /*! ConstantRed2 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantRed2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantRed2_MASK) /*! @} */ /*! @name FETCHWARP9_LAYERPROPERTY2 - Common properties of layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_TileMode2_MASK (0x30U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_TileMode2_SHIFT (4U) /*! TileMode2 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_TileMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_TileMode2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_TileMode2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaSrcEnable2_MASK (0x100U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT (8U) /*! AlphaSrcEnable2 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaSrcEnable2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaConstEnable2_MASK (0x200U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaConstEnable2_SHIFT (9U) /*! AlphaConstEnable2 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaConstEnable2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaMaskEnable2_MASK (0x400U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaMaskEnable2_SHIFT (10U) /*! AlphaMaskEnable2 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaMaskEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaMaskEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaMaskEnable2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaTransEnable2_MASK (0x800U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaTransEnable2_SHIFT (11U) /*! AlphaTransEnable2 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaTransEnable2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT (12U) /*! RGBAlphaSrcEnable2 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT (13U) /*! RGBAlphaConstEnable2 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaMaskEnable2_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaMaskEnable2_SHIFT (14U) /*! RGBAlphaMaskEnable2 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaMaskEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaMaskEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaMaskEnable2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT (15U) /*! RGBAlphaTransEnable2 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_PremulConstRGB2_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_PremulConstRGB2_SHIFT (16U) /*! PremulConstRGB2 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_PremulConstRGB2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_PremulConstRGB2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_PremulConstRGB2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_YUVConversionMode2_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_YUVConversionMode2_SHIFT (17U) /*! YUVConversionMode2 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_YUVConversionMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_YUVConversionMode2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_YUVConversionMode2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_GammaRemoveEnable2_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT (20U) /*! GammaRemoveEnable2 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_GammaRemoveEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_GammaRemoveEnable2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_ClipWindowEnable2_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_ClipWindowEnable2_SHIFT (30U) /*! ClipWindowEnable2 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_ClipWindowEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_ClipWindowEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_ClipWindowEnable2_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_SourceBufferEnable2_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_SourceBufferEnable2_SHIFT (31U) /*! SourceBufferEnable2 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_SourceBufferEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_SourceBufferEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_SourceBufferEnable2_MASK) /*! @} */ /*! @name FETCHWARP9_BASEADDRESS3 - Source buffer base address of layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS3_BaseAddress3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP9_BASEADDRESS3_BaseAddress3_SHIFT (0U) /*! BaseAddress3 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS3_BaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS3_BaseAddress3_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS3_BaseAddress3_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES3 - Source buffer attributes for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_Stride3_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT (0U) /*! Stride3 - See Stride0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_Stride3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_Stride3_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT (16U) /*! BitsPerPixel3 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERDIMENSION3 - Source buffer dimension of layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineWidth3_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT (0U) /*! LineWidth3 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineWidth3_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineCount3_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT (16U) /*! LineCount3 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineCount3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineCount3_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTBITS3 - Size of color components for RGB, YUV and index formats (layer 3). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK (0xFU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT (0U) /*! ComponentBitsAlpha3 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT (8U) /*! ComponentBitsBlue3 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT (16U) /*! ComponentBitsGreen3 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT (24U) /*! ComponentBitsRed3 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ITUFormat3_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ITUFormat3_SHIFT (31U) /*! ITUFormat3 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ITUFormat3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ITUFormat3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ITUFormat3_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTSHIFT3 - Bit position of color components for RGB, YUV and index formats (layer 3). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT (0U) /*! ComponentShiftAlpha3 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT (8U) /*! ComponentShiftBlue3 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT (16U) /*! ComponentShiftGreen3 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT (24U) /*! ComponentShiftRed3 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK) /*! @} */ /*! @name FETCHWARP9_LAYEROFFSET3 - Position of layer 3 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerXOffset3_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerXOffset3_SHIFT (0U) /*! LayerXOffset3 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerXOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerXOffset3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerYOffset3_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerYOffset3_SHIFT (16U) /*! LayerYOffset3 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerYOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerYOffset3_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWOFFSET3 - Clip window position for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT (0U) /*! ClipWindowXOffset3 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT (16U) /*! ClipWindowYOffset3 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS3 - Clip window size for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT (0U) /*! ClipWindowWidth3 - Width. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT (16U) /*! ClipWindowHeight3 - Height. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK) /*! @} */ /*! @name FETCHWARP9_CONSTANTCOLOR3 - Constant color for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantAlpha3_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantAlpha3_SHIFT (0U) /*! ConstantAlpha3 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantAlpha3_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantBlue3_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantBlue3_SHIFT (8U) /*! ConstantBlue3 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantBlue3_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantGreen3_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantGreen3_SHIFT (16U) /*! ConstantGreen3 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantGreen3_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantRed3_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantRed3_SHIFT (24U) /*! ConstantRed3 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantRed3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantRed3_MASK) /*! @} */ /*! @name FETCHWARP9_LAYERPROPERTY3 - Common properties of layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_TileMode3_MASK (0x30U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_TileMode3_SHIFT (4U) /*! TileMode3 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_TileMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_TileMode3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_TileMode3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaSrcEnable3_MASK (0x100U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT (8U) /*! AlphaSrcEnable3 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaSrcEnable3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaConstEnable3_MASK (0x200U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaConstEnable3_SHIFT (9U) /*! AlphaConstEnable3 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaConstEnable3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaMaskEnable3_MASK (0x400U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaMaskEnable3_SHIFT (10U) /*! AlphaMaskEnable3 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaMaskEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaMaskEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaMaskEnable3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaTransEnable3_MASK (0x800U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaTransEnable3_SHIFT (11U) /*! AlphaTransEnable3 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaTransEnable3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT (12U) /*! RGBAlphaSrcEnable3 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT (13U) /*! RGBAlphaConstEnable3 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaMaskEnable3_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaMaskEnable3_SHIFT (14U) /*! RGBAlphaMaskEnable3 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaMaskEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaMaskEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaMaskEnable3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT (15U) /*! RGBAlphaTransEnable3 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_PremulConstRGB3_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_PremulConstRGB3_SHIFT (16U) /*! PremulConstRGB3 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_PremulConstRGB3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_PremulConstRGB3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_PremulConstRGB3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_YUVConversionMode3_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_YUVConversionMode3_SHIFT (17U) /*! YUVConversionMode3 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_YUVConversionMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_YUVConversionMode3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_YUVConversionMode3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_GammaRemoveEnable3_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT (20U) /*! GammaRemoveEnable3 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_GammaRemoveEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_GammaRemoveEnable3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_ClipWindowEnable3_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_ClipWindowEnable3_SHIFT (30U) /*! ClipWindowEnable3 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_ClipWindowEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_ClipWindowEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_ClipWindowEnable3_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_SourceBufferEnable3_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_SourceBufferEnable3_SHIFT (31U) /*! SourceBufferEnable3 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_SourceBufferEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_SourceBufferEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_SourceBufferEnable3_MASK) /*! @} */ /*! @name FETCHWARP9_BASEADDRESS4 - Source buffer base address of layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS4_BaseAddress4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP9_BASEADDRESS4_BaseAddress4_SHIFT (0U) /*! BaseAddress4 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS4_BaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS4_BaseAddress4_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS4_BaseAddress4_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES4 - Source buffer attributes for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_Stride4_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT (0U) /*! Stride4 - See Stride0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_Stride4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_Stride4_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT (16U) /*! BitsPerPixel4 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERDIMENSION4 - Source buffer dimension of layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineWidth4_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT (0U) /*! LineWidth4 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineWidth4_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineCount4_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT (16U) /*! LineCount4 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineCount4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineCount4_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTBITS4 - Size of color components for RGB, YUV and index formats (layer 4). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK (0xFU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT (0U) /*! ComponentBitsAlpha4 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT (8U) /*! ComponentBitsBlue4 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT (16U) /*! ComponentBitsGreen4 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT (24U) /*! ComponentBitsRed4 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ITUFormat4_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ITUFormat4_SHIFT (31U) /*! ITUFormat4 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ITUFormat4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ITUFormat4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ITUFormat4_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTSHIFT4 - Bit position of color components for RGB, YUV and index formats (layer 4). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT (0U) /*! ComponentShiftAlpha4 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT (8U) /*! ComponentShiftBlue4 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT (16U) /*! ComponentShiftGreen4 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT (24U) /*! ComponentShiftRed4 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK) /*! @} */ /*! @name FETCHWARP9_LAYEROFFSET4 - Position of layer 4 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerXOffset4_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerXOffset4_SHIFT (0U) /*! LayerXOffset4 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerXOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerXOffset4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerYOffset4_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerYOffset4_SHIFT (16U) /*! LayerYOffset4 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerYOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerYOffset4_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWOFFSET4 - Clip window position for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT (0U) /*! ClipWindowXOffset4 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT (16U) /*! ClipWindowYOffset4 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS4 - Clip window size for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT (0U) /*! ClipWindowWidth4 - Width. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT (16U) /*! ClipWindowHeight4 - Height. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK) /*! @} */ /*! @name FETCHWARP9_CONSTANTCOLOR4 - Constant color for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantAlpha4_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantAlpha4_SHIFT (0U) /*! ConstantAlpha4 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantAlpha4_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantBlue4_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantBlue4_SHIFT (8U) /*! ConstantBlue4 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantBlue4_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantGreen4_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantGreen4_SHIFT (16U) /*! ConstantGreen4 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantGreen4_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantRed4_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantRed4_SHIFT (24U) /*! ConstantRed4 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantRed4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantRed4_MASK) /*! @} */ /*! @name FETCHWARP9_LAYERPROPERTY4 - Common properties of layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_TileMode4_MASK (0x30U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_TileMode4_SHIFT (4U) /*! TileMode4 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_TileMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_TileMode4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_TileMode4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaSrcEnable4_MASK (0x100U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT (8U) /*! AlphaSrcEnable4 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaSrcEnable4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaConstEnable4_MASK (0x200U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaConstEnable4_SHIFT (9U) /*! AlphaConstEnable4 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaConstEnable4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaMaskEnable4_MASK (0x400U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaMaskEnable4_SHIFT (10U) /*! AlphaMaskEnable4 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaMaskEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaMaskEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaMaskEnable4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaTransEnable4_MASK (0x800U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaTransEnable4_SHIFT (11U) /*! AlphaTransEnable4 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaTransEnable4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT (12U) /*! RGBAlphaSrcEnable4 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT (13U) /*! RGBAlphaConstEnable4 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaMaskEnable4_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaMaskEnable4_SHIFT (14U) /*! RGBAlphaMaskEnable4 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaMaskEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaMaskEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaMaskEnable4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT (15U) /*! RGBAlphaTransEnable4 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_PremulConstRGB4_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_PremulConstRGB4_SHIFT (16U) /*! PremulConstRGB4 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_PremulConstRGB4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_PremulConstRGB4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_PremulConstRGB4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_YUVConversionMode4_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_YUVConversionMode4_SHIFT (17U) /*! YUVConversionMode4 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_YUVConversionMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_YUVConversionMode4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_YUVConversionMode4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_GammaRemoveEnable4_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT (20U) /*! GammaRemoveEnable4 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_GammaRemoveEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_GammaRemoveEnable4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_ClipWindowEnable4_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_ClipWindowEnable4_SHIFT (30U) /*! ClipWindowEnable4 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_ClipWindowEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_ClipWindowEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_ClipWindowEnable4_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_SourceBufferEnable4_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_SourceBufferEnable4_SHIFT (31U) /*! SourceBufferEnable4 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_SourceBufferEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_SourceBufferEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_SourceBufferEnable4_MASK) /*! @} */ /*! @name FETCHWARP9_BASEADDRESS5 - Source buffer base address of layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS5_BaseAddress5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP9_BASEADDRESS5_BaseAddress5_SHIFT (0U) /*! BaseAddress5 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS5_BaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS5_BaseAddress5_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS5_BaseAddress5_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES5 - Source buffer attributes for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_Stride5_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT (0U) /*! Stride5 - See Stride0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_Stride5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_Stride5_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT (16U) /*! BitsPerPixel5 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERDIMENSION5 - Source buffer dimension of layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineWidth5_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT (0U) /*! LineWidth5 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineWidth5_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineCount5_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT (16U) /*! LineCount5 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineCount5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineCount5_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTBITS5 - Size of color components for RGB, YUV and index formats (layer 5). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK (0xFU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT (0U) /*! ComponentBitsAlpha5 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT (8U) /*! ComponentBitsBlue5 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT (16U) /*! ComponentBitsGreen5 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT (24U) /*! ComponentBitsRed5 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ITUFormat5_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ITUFormat5_SHIFT (31U) /*! ITUFormat5 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ITUFormat5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ITUFormat5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ITUFormat5_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTSHIFT5 - Bit position of color components for RGB, YUV and index formats (layer 5). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT (0U) /*! ComponentShiftAlpha5 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT (8U) /*! ComponentShiftBlue5 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT (16U) /*! ComponentShiftGreen5 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT (24U) /*! ComponentShiftRed5 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK) /*! @} */ /*! @name FETCHWARP9_LAYEROFFSET5 - Position of layer 5 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerXOffset5_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerXOffset5_SHIFT (0U) /*! LayerXOffset5 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerXOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerXOffset5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerYOffset5_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerYOffset5_SHIFT (16U) /*! LayerYOffset5 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerYOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerYOffset5_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWOFFSET5 - Clip window position for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT (0U) /*! ClipWindowXOffset5 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT (16U) /*! ClipWindowYOffset5 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS5 - Clip window size for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT (0U) /*! ClipWindowWidth5 - Width. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT (16U) /*! ClipWindowHeight5 - Height. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK) /*! @} */ /*! @name FETCHWARP9_CONSTANTCOLOR5 - Constant color for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantAlpha5_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantAlpha5_SHIFT (0U) /*! ConstantAlpha5 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantAlpha5_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantBlue5_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantBlue5_SHIFT (8U) /*! ConstantBlue5 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantBlue5_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantGreen5_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantGreen5_SHIFT (16U) /*! ConstantGreen5 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantGreen5_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantRed5_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantRed5_SHIFT (24U) /*! ConstantRed5 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantRed5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantRed5_MASK) /*! @} */ /*! @name FETCHWARP9_LAYERPROPERTY5 - Common properties of layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_TileMode5_MASK (0x30U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_TileMode5_SHIFT (4U) /*! TileMode5 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_TileMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_TileMode5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_TileMode5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaSrcEnable5_MASK (0x100U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT (8U) /*! AlphaSrcEnable5 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaSrcEnable5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaConstEnable5_MASK (0x200U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaConstEnable5_SHIFT (9U) /*! AlphaConstEnable5 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaConstEnable5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaMaskEnable5_MASK (0x400U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaMaskEnable5_SHIFT (10U) /*! AlphaMaskEnable5 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaMaskEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaMaskEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaMaskEnable5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaTransEnable5_MASK (0x800U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaTransEnable5_SHIFT (11U) /*! AlphaTransEnable5 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaTransEnable5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT (12U) /*! RGBAlphaSrcEnable5 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT (13U) /*! RGBAlphaConstEnable5 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaMaskEnable5_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaMaskEnable5_SHIFT (14U) /*! RGBAlphaMaskEnable5 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaMaskEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaMaskEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaMaskEnable5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT (15U) /*! RGBAlphaTransEnable5 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_PremulConstRGB5_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_PremulConstRGB5_SHIFT (16U) /*! PremulConstRGB5 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_PremulConstRGB5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_PremulConstRGB5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_PremulConstRGB5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_YUVConversionMode5_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_YUVConversionMode5_SHIFT (17U) /*! YUVConversionMode5 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_YUVConversionMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_YUVConversionMode5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_YUVConversionMode5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_GammaRemoveEnable5_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT (20U) /*! GammaRemoveEnable5 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_GammaRemoveEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_GammaRemoveEnable5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_ClipWindowEnable5_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_ClipWindowEnable5_SHIFT (30U) /*! ClipWindowEnable5 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_ClipWindowEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_ClipWindowEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_ClipWindowEnable5_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_SourceBufferEnable5_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_SourceBufferEnable5_SHIFT (31U) /*! SourceBufferEnable5 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_SourceBufferEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_SourceBufferEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_SourceBufferEnable5_MASK) /*! @} */ /*! @name FETCHWARP9_BASEADDRESS6 - Source buffer base address of layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS6_BaseAddress6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP9_BASEADDRESS6_BaseAddress6_SHIFT (0U) /*! BaseAddress6 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS6_BaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS6_BaseAddress6_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS6_BaseAddress6_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES6 - Source buffer attributes for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_Stride6_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT (0U) /*! Stride6 - See Stride0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_Stride6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_Stride6_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT (16U) /*! BitsPerPixel6 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERDIMENSION6 - Source buffer dimension of layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineWidth6_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT (0U) /*! LineWidth6 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineWidth6_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineCount6_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT (16U) /*! LineCount6 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineCount6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineCount6_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTBITS6 - Size of color components for RGB, YUV and index formats (layer 6). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK (0xFU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT (0U) /*! ComponentBitsAlpha6 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT (8U) /*! ComponentBitsBlue6 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT (16U) /*! ComponentBitsGreen6 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT (24U) /*! ComponentBitsRed6 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ITUFormat6_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ITUFormat6_SHIFT (31U) /*! ITUFormat6 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ITUFormat6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ITUFormat6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ITUFormat6_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTSHIFT6 - Bit position of color components for RGB, YUV and index formats (layer 6). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT (0U) /*! ComponentShiftAlpha6 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT (8U) /*! ComponentShiftBlue6 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT (16U) /*! ComponentShiftGreen6 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT (24U) /*! ComponentShiftRed6 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK) /*! @} */ /*! @name FETCHWARP9_LAYEROFFSET6 - Position of layer 1 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerXOffset6_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerXOffset6_SHIFT (0U) /*! LayerXOffset6 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerXOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerXOffset6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerYOffset6_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerYOffset6_SHIFT (16U) /*! LayerYOffset6 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerYOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerYOffset6_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWOFFSET6 - Clip window position for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT (0U) /*! ClipWindowXOffset6 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT (16U) /*! ClipWindowYOffset6 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS6 - Clip window size for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT (0U) /*! ClipWindowWidth6 - Width. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT (16U) /*! ClipWindowHeight6 - Height. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK) /*! @} */ /*! @name FETCHWARP9_CONSTANTCOLOR6 - Constant color for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantAlpha6_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantAlpha6_SHIFT (0U) /*! ConstantAlpha6 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantAlpha6_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantBlue6_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantBlue6_SHIFT (8U) /*! ConstantBlue6 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantBlue6_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantGreen6_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantGreen6_SHIFT (16U) /*! ConstantGreen6 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantGreen6_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantRed6_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantRed6_SHIFT (24U) /*! ConstantRed6 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantRed6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantRed6_MASK) /*! @} */ /*! @name FETCHWARP9_LAYERPROPERTY6 - Common properties of layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_TileMode6_MASK (0x30U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_TileMode6_SHIFT (4U) /*! TileMode6 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_TileMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_TileMode6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_TileMode6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaSrcEnable6_MASK (0x100U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT (8U) /*! AlphaSrcEnable6 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaSrcEnable6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaConstEnable6_MASK (0x200U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaConstEnable6_SHIFT (9U) /*! AlphaConstEnable6 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaConstEnable6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaMaskEnable6_MASK (0x400U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaMaskEnable6_SHIFT (10U) /*! AlphaMaskEnable6 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaMaskEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaMaskEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaMaskEnable6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaTransEnable6_MASK (0x800U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaTransEnable6_SHIFT (11U) /*! AlphaTransEnable6 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaTransEnable6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT (12U) /*! RGBAlphaSrcEnable6 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT (13U) /*! RGBAlphaConstEnable6 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaMaskEnable6_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaMaskEnable6_SHIFT (14U) /*! RGBAlphaMaskEnable6 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaMaskEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaMaskEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaMaskEnable6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT (15U) /*! RGBAlphaTransEnable6 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_PremulConstRGB6_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_PremulConstRGB6_SHIFT (16U) /*! PremulConstRGB6 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_PremulConstRGB6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_PremulConstRGB6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_PremulConstRGB6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_YUVConversionMode6_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_YUVConversionMode6_SHIFT (17U) /*! YUVConversionMode6 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_YUVConversionMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_YUVConversionMode6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_YUVConversionMode6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_GammaRemoveEnable6_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT (20U) /*! GammaRemoveEnable6 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_GammaRemoveEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_GammaRemoveEnable6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_ClipWindowEnable6_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_ClipWindowEnable6_SHIFT (30U) /*! ClipWindowEnable6 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_ClipWindowEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_ClipWindowEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_ClipWindowEnable6_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_SourceBufferEnable6_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_SourceBufferEnable6_SHIFT (31U) /*! SourceBufferEnable6 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_SourceBufferEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_SourceBufferEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_SourceBufferEnable6_MASK) /*! @} */ /*! @name FETCHWARP9_BASEADDRESS7 - Source buffer base address of layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS7_BaseAddress7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP9_BASEADDRESS7_BaseAddress7_SHIFT (0U) /*! BaseAddress7 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP9_BASEADDRESS7_BaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS7_BaseAddress7_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS7_BaseAddress7_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES7 - Source buffer stride for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_Stride7_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT (0U) /*! Stride7 - See Stride0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_Stride7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_Stride7_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT (16U) /*! BitsPerPixel7 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK) /*! @} */ /*! @name FETCHWARP9_SOURCEBUFFERDIMENSION7 - Source buffer dimension of layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineWidth7_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT (0U) /*! LineWidth7 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineWidth7_MASK) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineCount7_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT (16U) /*! LineCount7 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineCount7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineCount7_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTBITS7 - Size of color components for RGB, YUV and index formats (layer 7). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK (0xFU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT (0U) /*! ComponentBitsAlpha7 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT (8U) /*! ComponentBitsBlue7 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT (16U) /*! ComponentBitsGreen7 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT (24U) /*! ComponentBitsRed7 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ITUFormat7_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ITUFormat7_SHIFT (31U) /*! ITUFormat7 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ITUFormat7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ITUFormat7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ITUFormat7_MASK) /*! @} */ /*! @name FETCHWARP9_COLORCOMPONENTSHIFT7 - Bit position of color components for RGB, YUV and index formats (layer 7). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT (0U) /*! ComponentShiftAlpha7 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT (8U) /*! ComponentShiftBlue7 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT (16U) /*! ComponentShiftGreen7 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT (24U) /*! ComponentShiftRed7 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK) /*! @} */ /*! @name FETCHWARP9_LAYEROFFSET7 - Position of layer 7 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerXOffset7_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerXOffset7_SHIFT (0U) /*! LayerXOffset7 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerXOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerXOffset7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerYOffset7_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerYOffset7_SHIFT (16U) /*! LayerYOffset7 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerYOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerYOffset7_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWOFFSET7 - Clip window position for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT (0U) /*! ClipWindowXOffset7 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT (16U) /*! ClipWindowYOffset7 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK) /*! @} */ /*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS7 - Clip window size for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT (0U) /*! ClipWindowWidth7 - Width. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT (16U) /*! ClipWindowHeight7 - Height. */ #define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK) /*! @} */ /*! @name FETCHWARP9_CONSTANTCOLOR7 - Constant color for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantAlpha7_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantAlpha7_SHIFT (0U) /*! ConstantAlpha7 - Alpha. */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantAlpha7_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantBlue7_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantBlue7_SHIFT (8U) /*! ConstantBlue7 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantBlue7_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantGreen7_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantGreen7_SHIFT (16U) /*! ConstantGreen7 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantGreen7_MASK) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantRed7_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantRed7_SHIFT (24U) /*! ConstantRed7 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantRed7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantRed7_MASK) /*! @} */ /*! @name FETCHWARP9_LAYERPROPERTY7 - Common properties of layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_TileMode7_MASK (0x30U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_TileMode7_SHIFT (4U) /*! TileMode7 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_TileMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_TileMode7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_TileMode7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaSrcEnable7_MASK (0x100U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT (8U) /*! AlphaSrcEnable7 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaSrcEnable7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaConstEnable7_MASK (0x200U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaConstEnable7_SHIFT (9U) /*! AlphaConstEnable7 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaConstEnable7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaMaskEnable7_MASK (0x400U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaMaskEnable7_SHIFT (10U) /*! AlphaMaskEnable7 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaMaskEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaMaskEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaMaskEnable7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaTransEnable7_MASK (0x800U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaTransEnable7_SHIFT (11U) /*! AlphaTransEnable7 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaTransEnable7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT (12U) /*! RGBAlphaSrcEnable7 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT (13U) /*! RGBAlphaConstEnable7 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaMaskEnable7_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaMaskEnable7_SHIFT (14U) /*! RGBAlphaMaskEnable7 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaMaskEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaMaskEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaMaskEnable7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT (15U) /*! RGBAlphaTransEnable7 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_PremulConstRGB7_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_PremulConstRGB7_SHIFT (16U) /*! PremulConstRGB7 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_PremulConstRGB7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_PremulConstRGB7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_PremulConstRGB7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_YUVConversionMode7_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_YUVConversionMode7_SHIFT (17U) /*! YUVConversionMode7 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_YUVConversionMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_YUVConversionMode7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_YUVConversionMode7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_GammaRemoveEnable7_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT (20U) /*! GammaRemoveEnable7 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_GammaRemoveEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_GammaRemoveEnable7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_ClipWindowEnable7_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_ClipWindowEnable7_SHIFT (30U) /*! ClipWindowEnable7 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_ClipWindowEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_ClipWindowEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_ClipWindowEnable7_MASK) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_SourceBufferEnable7_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_SourceBufferEnable7_SHIFT (31U) /*! SourceBufferEnable7 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_SourceBufferEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_SourceBufferEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_SourceBufferEnable7_MASK) /*! @} */ /*! @name FETCHWARP9_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width minus one. */ #define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height minus one. */ #define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). If enabled, InputSelect must be set to INACTIVE. */ #define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name FETCHWARP9_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartX_MASK (0x3FU) #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartX_SHIFT (0U) /*! StartX - X coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartX_MASK) #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartY_MASK (0xFC0U) #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartY_SHIFT (6U) /*! StartY - Y coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartY_MASK) #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaX_MASK (0x3F000U) #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaX_SHIFT (12U) /*! DeltaX - Increment of X coordinate for horizontal step in destination frame. */ #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaX_MASK) #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U) #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaY_SHIFT (18U) /*! DeltaY - Increment of Y coordinate for vertical step in destination frame. */ #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaY_MASK) #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U) #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_SwapDirection_SHIFT (24U) /*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied * for horizontal and DeltaX for vertical step on destination frame. */ #define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_SwapDirection_MASK) /*! @} */ /*! @name FETCHWARP9_WARPCONTROL - Warping control options. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpBitsPerPixel_MASK (0x3FU) #define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpBitsPerPixel_SHIFT (0U) /*! WarpBitsPerPixel - Number of bits per pixel in the coordinate layer, which is read by another Fetch unit. Has to be 1, 2, 4, 8, 16 or 32. */ #define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpBitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpBitsPerPixel_SHIFT)) & IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpBitsPerPixel_MASK) #define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpCoordinateMode_MASK (0x300U) #define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpCoordinateMode_SHIFT (8U) /*! WarpCoordinateMode - Content of pixel data in the coordinate layer. * 0b00..x and y (sample points). * 0b01..dx and dy (vectors between adjacent sample points). * 0b10..ddx and ddy (deltas between adjacent vectors). */ #define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpCoordinateMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpCoordinateMode_SHIFT)) & IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpCoordinateMode_MASK) #define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpSymmetricOffset_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpSymmetricOffset_SHIFT (12U) /*! WarpSymmetricOffset - Value 1 enables symmetric range for negative and positive coordinate * values by adding an offset of +0.03125 internally to all coordinate input values. Recommended for * small coordinate formats in DD_PNT mode. */ #define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpSymmetricOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpSymmetricOffset_SHIFT)) & IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpSymmetricOffset_MASK) /*! @} */ /*! @name FETCHWARP9_ARBSTARTX - Start value X for arbitrary warping. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_ARBSTARTX_ArbStartX_MASK (0x1FFFFFU) #define IRIS_MVPL_FETCHWARP9_ARBSTARTX_ArbStartX_SHIFT (0U) /*! ArbStartX - Start point for sample-point interpolation (X coordinate). Given in signed 16.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP9_ARBSTARTX_ArbStartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBSTARTX_ArbStartX_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBSTARTX_ArbStartX_MASK) /*! @} */ /*! @name FETCHWARP9_ARBSTARTY - Start value Y for arbitrary warping. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_ARBSTARTY_ArbStartY_MASK (0x1FFFFFU) #define IRIS_MVPL_FETCHWARP9_ARBSTARTY_ArbStartY_SHIFT (0U) /*! ArbStartY - Start point for sample-point interpolation (Y coordinate). Given in signed 16.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP9_ARBSTARTY_ArbStartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBSTARTY_ArbStartY_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBSTARTY_ArbStartY_MASK) /*! @} */ /*! @name FETCHWARP9_ARBDELTA - Start values for delta incrementation of arbitrary warping. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXX_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXX_SHIFT (0U) /*! ArbDeltaXX - X coordinate of vector between first and second sample point. Given in signed 3.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXX_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXX_MASK) #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXY_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXY_SHIFT (8U) /*! ArbDeltaXY - Y coordinate of vector between first and second sample point. Given in signed 3.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXY_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXY_MASK) #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYX_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYX_SHIFT (16U) /*! ArbDeltaYX - X coordinate of vector between start and first sample point. Given in signed 3.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYX_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYX_MASK) #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYY_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYY_SHIFT (24U) /*! ArbDeltaYY - Y coordinate of vector between start and first sample point. Given in signed 3.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYY_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYY_MASK) /*! @} */ /*! @name FETCHWARP9_FIRPOSITIONS - FIR sequence control register. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR0Position_MASK (0xFU) #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR0Position_SHIFT (0U) /*! FIR0Position - Position of first pixel. */ #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR0Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR0Position_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR0Position_MASK) #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR1Position_MASK (0xF0U) #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR1Position_SHIFT (4U) /*! FIR1Position - Position of second pixel. */ #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR1Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR1Position_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR1Position_MASK) #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR2Position_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR2Position_SHIFT (8U) /*! FIR2Position - Position of third pixel. */ #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR2Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR2Position_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR2Position_MASK) #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR3Position_MASK (0xF000U) #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR3Position_SHIFT (12U) /*! FIR3Position - Position of fourth pixel. */ #define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR3Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR3Position_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR3Position_MASK) /*! @} */ /*! @name FETCHWARP9_FIRCOEFFICIENTS - FIR coefficients register. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR0Coefficient_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR0Coefficient_SHIFT (0U) /*! FIR0Coefficient - First coefficient. */ #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR0Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR0Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR0Coefficient_MASK) #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR1Coefficient_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR1Coefficient_SHIFT (8U) /*! FIR1Coefficient - Second coefficient. */ #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR1Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR1Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR1Coefficient_MASK) #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR2Coefficient_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR2Coefficient_SHIFT (16U) /*! FIR2Coefficient - Third coefficient. */ #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR2Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR2Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR2Coefficient_MASK) #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR3Coefficient_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR3Coefficient_SHIFT (24U) /*! FIR3Coefficient - Fourth coefficient. */ #define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR3Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR3Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR3Coefficient_MASK) /*! @} */ /*! @name FETCHWARP9_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CONTROL_RasterMode_MASK (0x7U) #define IRIS_MVPL_FETCHWARP9_CONTROL_RasterMode_SHIFT (0U) /*! RasterMode - Selects a method how to generate source buffer sample points. * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot/RotL only] Arbitrary warping (filter is active). Coordinates are read from frame * input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ #define IRIS_MVPL_FETCHWARP9_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_RasterMode_MASK) #define IRIS_MVPL_FETCHWARP9_CONTROL_InputSelect_MASK (0x18U) #define IRIS_MVPL_FETCHWARP9_CONTROL_InputSelect_SHIFT (3U) /*! InputSelect - Selects function for the frame input port. * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define IRIS_MVPL_FETCHWARP9_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_InputSelect_MASK) #define IRIS_MVPL_FETCHWARP9_CONTROL_RawPixel_MASK (0x80U) #define IRIS_MVPL_FETCHWARP9_CONTROL_RawPixel_SHIFT (7U) /*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced * for all layers by fixed values that allow passing the pixel data read from memory unchanged * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color * are deactived. Skip and Tile pixels are not affected by this setting. */ #define IRIS_MVPL_FETCHWARP9_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_RawPixel_MASK) #define IRIS_MVPL_FETCHWARP9_CONTROL_ClipColor_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP9_CONTROL_ClipColor_SHIFT (16U) /*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer. * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define IRIS_MVPL_FETCHWARP9_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_ClipColor_MASK) #define IRIS_MVPL_FETCHWARP9_CONTROL_ClipLayer_MASK (0xE0000U) #define IRIS_MVPL_FETCHWARP9_CONTROL_ClipLayer_SHIFT (17U) /*! ClipLayer - Index of the layer which is used to fill the clipping area of the frame layout when * ClipColor is set to LAYER. The selected layer must be enabled (LayerEnable). */ #define IRIS_MVPL_FETCHWARP9_CONTROL_ClipLayer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_ClipLayer_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_ClipLayer_MASK) #define IRIS_MVPL_FETCHWARP9_CONTROL_FilterMode_MASK (0x700000U) #define IRIS_MVPL_FETCHWARP9_CONTROL_FilterMode_SHIFT (20U) /*! FilterMode - Use this to select between nearest and bilinear filtering. Only has an effect if * rastermode == ARBITRARY or rastermode == PERSPECTIVE or rastermode == AFFINE. * 0b000..Chooses pixel closest to sample point * 0b001..Calculates result from 4 pixels closest to sample point * 0b010..FIR mode with 2 programmable pixel positions and coefficients * 0b011..FIR mode with 4 programmable pixel positions and coefficients * 0b100..Calculates result from 2 pixels closest to the sample point and on the same line */ #define IRIS_MVPL_FETCHWARP9_CONTROL_FilterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_FilterMode_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_FilterMode_MASK) /*! @} */ /*! @name FETCHWARP9_TRIGGERENABLE - Shadow load enable flags for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_TRIGGERENABLE_ShdLdReq_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_TRIGGERENABLE_ShdLdReq_SHIFT (0U) /*! ShdLdReq - Shadow load request flags for each layer (one time load). */ #define IRIS_MVPL_FETCHWARP9_TRIGGERENABLE_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_TRIGGERENABLE_ShdLdReq_SHIFT)) & IRIS_MVPL_FETCHWARP9_TRIGGERENABLE_ShdLdReq_MASK) /*! @} */ /*! @name FETCHWARP9_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FETCHWARP9_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_FETCHWARP9_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name FETCHWARP9_START - Frame start trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_START_Start_MASK (0x1U) #define IRIS_MVPL_FETCHWARP9_START_Start_SHIFT (0U) /*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only). */ #define IRIS_MVPL_FETCHWARP9_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_START_Start_SHIFT)) & IRIS_MVPL_FETCHWARP9_START_Start_MASK) /*! @} */ /*! @name FETCHWARP9_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_FETCHTYPE_FetchType_MASK (0xFU) #define IRIS_MVPL_FETCHWARP9_FETCHTYPE_FetchType_SHIFT (0U) /*! FetchType - This field can be used to determine what kind of fetch unit this is. * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. */ #define IRIS_MVPL_FETCHWARP9_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHWARP9_FETCHTYPE_FetchType_MASK) /*! @} */ /*! @name FETCHWARP9_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U) /*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface. */ #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK) #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U) /*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. */ #define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name FETCHWARP9_STATUS - Status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_STATUS_WriteTimeout_MASK (0x1U) #define IRIS_MVPL_FETCHWARP9_STATUS_WriteTimeout_SHIFT (0U) /*! WriteTimeout - Timeout detected when writing to the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHWARP9_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHWARP9_STATUS_WriteTimeout_MASK) #define IRIS_MVPL_FETCHWARP9_STATUS_ReadTimeout_MASK (0x10U) #define IRIS_MVPL_FETCHWARP9_STATUS_ReadTimeout_SHIFT (4U) /*! ReadTimeout - Timeout detected when reading from the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHWARP9_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHWARP9_STATUS_ReadTimeout_MASK) /*! @} */ /*! @name FETCHWARP9_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Fetch unit is busy. */ #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBusy_MASK) #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle. */ #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBuffersIdle_MASK) #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusRequest_MASK (0x20U) #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusRequest_SHIFT (5U) /*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge. */ #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusRequest_MASK) #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusComplete_MASK (0x40U) #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusComplete_SHIFT (6U) /*! StatusComplete - Fetch unit completed all requested AXI transfers. */ #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusComplete_MASK) #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_ShadowStatus_SHIFT (8U) /*! ShadowStatus - Shadow load status for all layers (layer index = bit index). */ #define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_ShadowStatus_MASK) /*! @} */ /*! @name FETCHECO9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name FETCHECO9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name FETCHECO9_STATICCONTROL - Common static control options. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U) #define IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U) /*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded * from shadow at start of each frame. This update is then executed independently from other RWS * type fields. ShdEn must be enabled for this mode. */ #define IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_MASK) /*! @} */ /*! @name FETCHECO9_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U) /*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of * 2. */ #define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK) #define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of * two may be specified as burst length. */ #define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK) #define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U) /*! LineMode - Fetch buffer cache control. * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_MASK) /*! @} */ /*! @name FETCHECO9_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_SHIFT (0U) /*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit * BaseAddress[0] has to be 0. */ #define IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_MASK) /*! @} */ /*! @name FETCHECO9_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU) #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U) /*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel * width of 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK) #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U) #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U) /*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or * 32. Exception: FetchEco does not support 18 and 24. */ #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK) /*! @} */ /*! @name FETCHECO9_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U) /*! LineWidth0 - Width of the source buffer of the layer in pixels minus one. */ #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK) #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U) /*! LineCount0 - Number of lines of the source buffer of the layer minus one. */ #define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_MASK) /*! @} */ /*! @name FETCHECO9_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U) /*! ComponentBitsAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U) /*! ComponentBitsBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U) /*! ComponentBitsGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U) /*! ComponentBitsRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U) /*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This * is compliant to ITU 656 standard. */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_MASK) /*! @} */ /*! @name FETCHECO9_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U) /*! ComponentShiftAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U) /*! ComponentShiftBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U) /*! ComponentShiftGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U) #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U) /*! ComponentShiftRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK) /*! @} */ /*! @name FETCHECO9_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_SHIFT (0U) /*! LayerXOffset0 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_MASK) #define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_SHIFT (16U) /*! LayerYOffset0 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_MASK) /*! @} */ /*! @name FETCHECO9_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U) /*! ClipWindowXOffset0 - Horizontal position (X). */ #define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK) #define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U) /*! ClipWindowYOffset0 - Vertical position (Y). */ #define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK) /*! @} */ /*! @name FETCHECO9_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U) /*! ClipWindowWidth0 - Width. */ #define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK) #define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U) /*! ClipWindowHeight0 - Height. */ #define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK) /*! @} */ /*! @name FETCHECO9_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU) #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U) /*! ConstantAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_MASK) #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U) #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U) /*! ConstantBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_MASK) #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U) #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U) /*! ConstantGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_MASK) #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U) #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U) /*! ConstantRed0 - Red and Y (luma). */ #define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_MASK) /*! @} */ /*! @name FETCHECO9_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_MASK (0x30U) #define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_SHIFT (4U) /*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) * takes precedence if a pixel becomes subject to both tiling and clipping. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_MASK) #define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U) #define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U) /*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip * window get the clip color, pixels inside the source or tiling color. */ #define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_MASK) #define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U) /*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling * color is used only (TileMode TILE_PAD not allowed). */ #define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_MASK) /*! @} */ /*! @name FETCHECO9_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width minus one. */ #define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height minus one. */ #define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). If enabled, InputSelect must be set to INACTIVE. */ #define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name FETCHECO9_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_MASK (0x3FU) #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_SHIFT (0U) /*! StartX - X coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_MASK) #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_MASK (0xFC0U) #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_SHIFT (6U) /*! StartY - Y coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_MASK) #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_MASK (0x3F000U) #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_SHIFT (12U) /*! DeltaX - Increment of X coordinate for horizontal step in destination frame. */ #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_MASK) #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U) #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_SHIFT (18U) /*! DeltaY - Increment of Y coordinate for vertical step in destination frame. */ #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_MASK) #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U) #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_SHIFT (24U) /*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied * for horizontal and DeltaX for vertical step on destination frame. */ #define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_MASK) /*! @} */ /*! @name FETCHECO9_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_MASK (0x80U) #define IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_SHIFT (7U) /*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced * for all layers by fixed values that allow passing the pixel data read from memory unchanged * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color * are deactived. Skip and Tile pixels are not affected by this setting. */ #define IRIS_MVPL_FETCHECO9_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_MASK) #define IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_MASK (0x10000U) #define IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_SHIFT (16U) /*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer. * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define IRIS_MVPL_FETCHECO9_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_MASK) /*! @} */ /*! @name FETCHECO9_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name FETCHECO9_START - Frame start trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_START_Start_MASK (0x1U) #define IRIS_MVPL_FETCHECO9_START_Start_SHIFT (0U) /*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only). */ #define IRIS_MVPL_FETCHECO9_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_START_Start_SHIFT)) & IRIS_MVPL_FETCHECO9_START_Start_MASK) /*! @} */ /*! @name FETCHECO9_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_MASK (0xFU) #define IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_SHIFT (0U) /*! FetchType - This field can be used to determine what kind of fetch unit this is. * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. */ #define IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_MASK) /*! @} */ /*! @name FETCHECO9_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U) /*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface. */ #define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK) #define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U) /*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. */ #define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name FETCHECO9_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Fetch unit is busy. */ #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_MASK) #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle. */ #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_MASK) #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_MASK (0x20U) #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_SHIFT (5U) /*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge. */ #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_MASK) #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_MASK (0x40U) #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_SHIFT (6U) /*! StatusComplete - Fetch unit completed all requested AXI transfers. */ #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_MASK) #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U) #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_SHIFT (8U) /*! ShadowStatus - Shadow load status for all layers (layer index = bit index). */ #define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_MASK) /*! @} */ /*! @name ROP9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name ROP9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name ROP9_STATICCONTROL - Raster Operation static control register */ /*! @{ */ #define IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_ROP9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name ROP9_CONTROL - Raster Operation control register */ /*! @{ */ #define IRIS_MVPL_ROP9_CONTROL_Mode_MASK (0x1U) #define IRIS_MVPL_ROP9_CONTROL_Mode_SHIFT (0U) /*! Mode - Operation mode for rop * 0b0..Neutral mode * 0b1..Normal Operation */ #define IRIS_MVPL_ROP9_CONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_Mode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_Mode_MASK) #define IRIS_MVPL_ROP9_CONTROL_AlphaMode_MASK (0x10U) #define IRIS_MVPL_ROP9_CONTROL_AlphaMode_SHIFT (4U) /*! AlphaMode - Selects the mode for the alpha component channel, has no effect in NEUTRAL mode * 0b0..Normal raster operation mode, using the operation index * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1 */ #define IRIS_MVPL_ROP9_CONTROL_AlphaMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_AlphaMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_AlphaMode_MASK) #define IRIS_MVPL_ROP9_CONTROL_BlueMode_MASK (0x20U) #define IRIS_MVPL_ROP9_CONTROL_BlueMode_SHIFT (5U) /*! BlueMode - Selects the mode for the blue component channel, has no effect in NEUTRAL mode * 0b0..Normal raster operation mode, using the operation index * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1 */ #define IRIS_MVPL_ROP9_CONTROL_BlueMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_BlueMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_BlueMode_MASK) #define IRIS_MVPL_ROP9_CONTROL_GreenMode_MASK (0x40U) #define IRIS_MVPL_ROP9_CONTROL_GreenMode_SHIFT (6U) /*! GreenMode - Selects the mode for the green component channel, has no effect in NEUTRAL mode * 0b0..Normal raster operation mode, using the operation index * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1 */ #define IRIS_MVPL_ROP9_CONTROL_GreenMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_GreenMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_GreenMode_MASK) #define IRIS_MVPL_ROP9_CONTROL_RedMode_MASK (0x80U) #define IRIS_MVPL_ROP9_CONTROL_RedMode_SHIFT (7U) /*! RedMode - Selects the mode for the red component channel, has no effect in NEUTRAL mode * 0b0..Normal raster operation mode, using the operation index * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1 */ #define IRIS_MVPL_ROP9_CONTROL_RedMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_RedMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_RedMode_MASK) #define IRIS_MVPL_ROP9_CONTROL_PrimDiv2_MASK (0x100U) #define IRIS_MVPL_ROP9_CONTROL_PrimDiv2_SHIFT (8U) /*! PrimDiv2 - Selects whether to divide the primary input color components by two or not for ADD * mode. This field has no effect on a color component in ROP mode. * 0b0..No change to input * 0b1..Input is divided by two/shift to the right by one */ #define IRIS_MVPL_ROP9_CONTROL_PrimDiv2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_PrimDiv2_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_PrimDiv2_MASK) #define IRIS_MVPL_ROP9_CONTROL_SecDiv2_MASK (0x200U) #define IRIS_MVPL_ROP9_CONTROL_SecDiv2_SHIFT (9U) /*! SecDiv2 - Selects whether to divide the secondary input color components by two or not for ADD * mode. This field has no effect on a color component in ROP mode. * 0b0..No change to input * 0b1..Input is divided by two/shift to the right by one */ #define IRIS_MVPL_ROP9_CONTROL_SecDiv2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_SecDiv2_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_SecDiv2_MASK) #define IRIS_MVPL_ROP9_CONTROL_TertDiv2_MASK (0x400U) #define IRIS_MVPL_ROP9_CONTROL_TertDiv2_SHIFT (10U) /*! TertDiv2 - Selects whether to divide the tertiary input color components by two or not for ADD * mode. This field has no effect on a color component in ROP mode. * 0b0..No change to input * 0b1..Input is divided by two/shift to the right by one */ #define IRIS_MVPL_ROP9_CONTROL_TertDiv2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_TertDiv2_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_TertDiv2_MASK) /*! @} */ /*! @name ROP9_RASTEROPERATIONINDICES - ROP operation indices */ /*! @{ */ #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_MASK (0xFFU) #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_SHIFT (0U) /*! OpIndexAlpha - Alpha operation index */ #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_MASK) #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_MASK (0xFF00U) #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_SHIFT (8U) /*! OpIndexBlue - Blue operation index */ #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_MASK) #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_MASK (0xFF0000U) #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_SHIFT (16U) /*! OpIndexGreen - Green operation index */ #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_MASK) #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_MASK (0xFF000000U) #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_SHIFT (24U) /*! OpIndexRed - Red operation index */ #define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_MASK) /*! @} */ /*! @name ROP9_PRIMCONTROLWORD - Value of last received primary control word */ /*! @{ */ #define IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_SHIFT (0U) /*! P_VAL - Value of last received control word on the primary input. If a 39 bit pixel channel is * connected, the mapping is as follows: p_val[31:0] = { data[37:22], data[19:12], data[9:2] }. * For debug purposes only, read when stable only, otherwise read data might be corrupted. */ #define IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_MASK) /*! @} */ /*! @name ROP9_SECCONTROLWORD - Value of last received secondary control word */ /*! @{ */ #define IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_SHIFT (0U) /*! S_VAL - Value of last received control word on the secondary input. If a 39 bit pixel channel is * connected, the mapping is as follows: s_val[31:0] = { data[37:22], data[19:12], data[9:2] }. * For debug purposes only, read when stable only, otherwise read data might be corrupted. */ #define IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_MASK) /*! @} */ /*! @name ROP9_TERTCONTROLWORD - Value of last received tertiary control word */ /*! @{ */ #define IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_SHIFT (0U) /*! T_VAL - Value of last received control word on the tertiary input. If a 39 bit pixel channel is * connected, the mapping is as follows: t_val[31:0] = { data[37:22], data[19:12], data[9:2] }. * For debug purposes only, read when stable only, otherwise read data might be corrupted. */ #define IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_SHIFT)) & IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_MASK) /*! @} */ /*! @name CLUT9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name CLUT9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name CLUT9_STATICCONTROL - CLUT static control register */ /*! @{ */ #define IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name CLUT9_UNSHADOWEDCONTROL - CLUT unshadowed control register */ /*! @{ */ #define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_MASK (0x1U) #define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_SHIFT (0U) /*! B_EN - Write enable for writing the blue color LUT entry from the host (allows writing a single * color entry without a read-modify-write cycle) * 0b0..disable * 0b1..enable */ #define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_SHIFT)) & IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_MASK) #define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_MASK (0x2U) #define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_SHIFT (1U) /*! G_EN - Write enable for writing the green color LUT entry from the host (allows writing a single * color entry without a read-modify-write cycle) * 0b0..disable * 0b1..enable */ #define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_SHIFT)) & IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_MASK) #define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_MASK (0x4U) #define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_SHIFT (2U) /*! R_EN - Write enable for writing the red color LUT entry from the host (allows writing a single * color entry without a read-modify-write cycle) * 0b0..disable * 0b1..enable */ #define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_SHIFT)) & IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_MASK) /*! @} */ /*! @name CLUT9_CONTROL - CLUT control register */ /*! @{ */ #define IRIS_MVPL_CLUT9_CONTROL_MODE_MASK (0x3U) #define IRIS_MVPL_CLUT9_CONTROL_MODE_SHIFT (0U) /*! MODE - Operation mode for color lookup table * 0b00..module in neutral mode, input data is bypassed to the output * 0b01..module in color lookup mode (LUT holds a 10bit color value for CLut derivate and 8bit color value for CLutL derivate for each input color) * 0b10..module in 10bit color index table mode (LUT holds a 3x10bit color value for derivate CLut and 3x8bit * color value for CLUTL derivate, indexed with the red input color) * 0b11..module in RGBA color index table mode (LUT holds a 3x8bit color value and a 6bit alpha value for CLut * derivate and 3x6bit color value and 6bit alpha value for CLutL derivate, indexed with the red input color) */ #define IRIS_MVPL_CLUT9_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_MODE_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_MODE_MASK) #define IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_MASK (0x10U) #define IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_SHIFT (4U) /*! COL_8BIT - Color (red, green, blue) output bitwidth select * 0b0..color is 10bit output * 0b1..color is 8bit output (dithering of internal 10bit value) */ #define IRIS_MVPL_CLUT9_CONTROL_COL_8BIT(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_MASK) #define IRIS_MVPL_CLUT9_CONTROL_AlphaMask_MASK (0x20U) #define IRIS_MVPL_CLUT9_CONTROL_AlphaMask_SHIFT (5U) /*! AlphaMask - Enables the alpha mask mode. This mode disables lookup for all pixels with an alpha * component smaller or greater/equal than 128. They are bypassed unchanged. * 0b0..Alpha mask mode disabled * 0b1..Alpha mask mode enabled */ #define IRIS_MVPL_CLUT9_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_AlphaMask_MASK) #define IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_MASK (0x40U) #define IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_SHIFT (6U) /*! AlphaInvert - Chooses whether to disable lookup for alpha components smaller or greater/equal * than 128. For this field to have an effect AlphaMask must be set to ENABLE. * 0b0..Disable computation for alpha smaller than 128 * 0b1..Disable computation for alpha greater than or equal to 128 */ #define IRIS_MVPL_CLUT9_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_MASK) #define IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_MASK (0xF00U) #define IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_SHIFT (8U) /*! IDX_BITS - Number of msb bits of the red color input used for the LUT index input */ #define IRIS_MVPL_CLUT9_CONTROL_IDX_BITS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_MASK) /*! @} */ /*! @name CLUT9_STATUS - CLUT status register */ /*! @{ */ #define IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_MASK (0x1U) #define IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_SHIFT (0U) /*! WRITE_TIMEOUT - Timeout detected when writing to the LUT */ #define IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_SHIFT)) & IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_MASK) #define IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_MASK (0x10U) #define IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_SHIFT (4U) /*! READ_TIMEOUT - Timeout detected when reading from the LUT */ #define IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_SHIFT)) & IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_MASK) /*! @} */ /*! @name CLUT9_LASTCONTROLWORD - Value of last received control word, for debugging */ /*! @{ */ #define IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_SHIFT (0U) /*! L_VAL - Value of last received control word. For debug purposes only, read when stable only, * otherwise read data might be corrupted. */ #define IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_MASK) /*! @} */ /*! @name CLUT9_LUT - Look Up Table */ /*! @{ */ #define IRIS_MVPL_CLUT9_LUT_BLUE_MASK (0x3FFU) #define IRIS_MVPL_CLUT9_LUT_BLUE_SHIFT (0U) /*! BLUE - Blue component */ #define IRIS_MVPL_CLUT9_LUT_BLUE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LUT_BLUE_SHIFT)) & IRIS_MVPL_CLUT9_LUT_BLUE_MASK) #define IRIS_MVPL_CLUT9_LUT_GREEN_MASK (0xFFC00U) #define IRIS_MVPL_CLUT9_LUT_GREEN_SHIFT (10U) /*! GREEN - Green component */ #define IRIS_MVPL_CLUT9_LUT_GREEN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LUT_GREEN_SHIFT)) & IRIS_MVPL_CLUT9_LUT_GREEN_MASK) #define IRIS_MVPL_CLUT9_LUT_RED_MASK (0x3FF00000U) #define IRIS_MVPL_CLUT9_LUT_RED_SHIFT (20U) /*! RED - Red component */ #define IRIS_MVPL_CLUT9_LUT_RED(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LUT_RED_SHIFT)) & IRIS_MVPL_CLUT9_LUT_RED_MASK) /*! @} */ /*! @name MATRIX9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name MATRIX9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name MATRIX9_STATICCONTROL - Color Matrix static control register */ /*! @{ */ #define IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name MATRIX9_CONTROL - Color Matrix control register */ /*! @{ */ #define IRIS_MVPL_MATRIX9_CONTROL_MODE_MASK (0x3U) #define IRIS_MVPL_MATRIX9_CONTROL_MODE_SHIFT (0U) /*! MODE - Operation mode for color matrix * 0b00..Module in neutral mode, input data is bypassed * 0b01..Module in matrix mode, input data is multiplied with matrix values * 0b10..Module in alpha pre-multiplication mode, input color is multiplied with input alpha * 0b11..Reserved, do not use */ #define IRIS_MVPL_MATRIX9_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX9_CONTROL_MODE_MASK) #define IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_MASK (0x10U) #define IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_SHIFT (4U) /*! AlphaMask - Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value * smaller than 0.5 are by-passed unchanged. */ #define IRIS_MVPL_MATRIX9_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_MASK) #define IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_MASK (0x20U) #define IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_SHIFT (5U) /*! AlphaInvert - Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha * value greater or equal 0.5 are by-passed). */ #define IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_MASK) /*! @} */ /*! @name MATRIX9_RED0 - Matrix values for calculation of the red output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_RED0_A11_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX9_RED0_A11_SHIFT (0U) /*! A11 - Value for red input. */ #define IRIS_MVPL_MATRIX9_RED0_A11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX9_RED0_A11_MASK) #define IRIS_MVPL_MATRIX9_RED0_A12_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX9_RED0_A12_SHIFT (16U) /*! A12 - Value for green input. */ #define IRIS_MVPL_MATRIX9_RED0_A12(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX9_RED0_A12_MASK) /*! @} */ /*! @name MATRIX9_RED1 - Matrix values for calculation of the red output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_RED1_A13_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX9_RED1_A13_SHIFT (0U) /*! A13 - Value for blue input. */ #define IRIS_MVPL_MATRIX9_RED1_A13(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX9_RED1_A13_MASK) #define IRIS_MVPL_MATRIX9_RED1_A14_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX9_RED1_A14_SHIFT (16U) /*! A14 - Value for alpha input. */ #define IRIS_MVPL_MATRIX9_RED1_A14(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX9_RED1_A14_MASK) /*! @} */ /*! @name MATRIX9_GREEN0 - Matrix values for calculation of the green output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_GREEN0_A21_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX9_GREEN0_A21_SHIFT (0U) /*! A21 - Value for red input. */ #define IRIS_MVPL_MATRIX9_GREEN0_A21(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN0_A21_MASK) #define IRIS_MVPL_MATRIX9_GREEN0_A22_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX9_GREEN0_A22_SHIFT (16U) /*! A22 - Value for green input. */ #define IRIS_MVPL_MATRIX9_GREEN0_A22(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN0_A22_MASK) /*! @} */ /*! @name MATRIX9_GREEN1 - Matrix values for calculation of the green output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_GREEN1_A23_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX9_GREEN1_A23_SHIFT (0U) /*! A23 - Value for blue input. */ #define IRIS_MVPL_MATRIX9_GREEN1_A23(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN1_A23_MASK) #define IRIS_MVPL_MATRIX9_GREEN1_A24_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX9_GREEN1_A24_SHIFT (16U) /*! A24 - Value for alpha input. */ #define IRIS_MVPL_MATRIX9_GREEN1_A24(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN1_A24_MASK) /*! @} */ /*! @name MATRIX9_BLUE0 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_BLUE0_A31_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX9_BLUE0_A31_SHIFT (0U) /*! A31 - Value for red input. */ #define IRIS_MVPL_MATRIX9_BLUE0_A31(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE0_A31_MASK) #define IRIS_MVPL_MATRIX9_BLUE0_A32_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX9_BLUE0_A32_SHIFT (16U) /*! A32 - Value for green input. */ #define IRIS_MVPL_MATRIX9_BLUE0_A32(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE0_A32_MASK) /*! @} */ /*! @name MATRIX9_BLUE1 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_BLUE1_A33_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX9_BLUE1_A33_SHIFT (0U) /*! A33 - Value for blue input. */ #define IRIS_MVPL_MATRIX9_BLUE1_A33(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE1_A33_MASK) #define IRIS_MVPL_MATRIX9_BLUE1_A34_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX9_BLUE1_A34_SHIFT (16U) /*! A34 - Value for alpha input. */ #define IRIS_MVPL_MATRIX9_BLUE1_A34(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE1_A34_MASK) /*! @} */ /*! @name MATRIX9_ALPHA0 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_ALPHA0_A41_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX9_ALPHA0_A41_SHIFT (0U) /*! A41 - Value for red input. */ #define IRIS_MVPL_MATRIX9_ALPHA0_A41(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA0_A41_MASK) #define IRIS_MVPL_MATRIX9_ALPHA0_A42_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX9_ALPHA0_A42_SHIFT (16U) /*! A42 - Value for green input. */ #define IRIS_MVPL_MATRIX9_ALPHA0_A42(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA0_A42_MASK) /*! @} */ /*! @name MATRIX9_ALPHA1 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_ALPHA1_A43_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX9_ALPHA1_A43_SHIFT (0U) /*! A43 - Value for blue input. */ #define IRIS_MVPL_MATRIX9_ALPHA1_A43(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA1_A43_MASK) #define IRIS_MVPL_MATRIX9_ALPHA1_A44_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX9_ALPHA1_A44_SHIFT (16U) /*! A44 - Value for alpha input. */ #define IRIS_MVPL_MATRIX9_ALPHA1_A44(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA1_A44_MASK) /*! @} */ /*! @name MATRIX9_OFFSETVECTOR0 - Offset vectors for red and green output. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_SHIFT (0U) /*! C1 - Red output offset. */ #define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_MASK) #define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_SHIFT (16U) /*! C2 - Green output offset. */ #define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_MASK) /*! @} */ /*! @name MATRIX9_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_SHIFT (0U) /*! C3 - Blue output offset. */ #define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_MASK) #define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_SHIFT (16U) /*! C4 - Alpha output offset. Note that the 8-bit alpha input is up-scaled to 10-bit, before the * matrix and this offset is applied, and down-scaled to 8-bit for output afterwards. */ #define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_MASK) /*! @} */ /*! @name MATRIX9_LASTCONTROLWORD - Value of last received control word, for debugging. */ /*! @{ */ #define IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_SHIFT (0U) /*! L_VAL - Value of last received control word. For debug purposes only, read when stable only, * otherwise read data might be corrupted. */ #define IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_MASK) /*! @} */ /*! @name HSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name HSCALER9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name HSCALER9_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Shadow enable for RWS type configuration fields (0 = write-through, 1 = shadows enabled) */ #define IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name HSCALER9_SETUP1 - Phase interpolator setup. */ /*! @{ */ #define IRIS_MVPL_HSCALER9_SETUP1_scale_factor_MASK (0xFFFFFU) #define IRIS_MVPL_HSCALER9_SETUP1_scale_factor_SHIFT (0U) /*! scale_factor - Scale factor (unsigned fix-point 1.19). Must be greater 0.0 and less or equal * 1.0. If scale_mode is UPSCALE then the inverse scale factor must be programmed. */ #define IRIS_MVPL_HSCALER9_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_HSCALER9_SETUP1_scale_factor_MASK) /*! @} */ /*! @name HSCALER9_SETUP2 - Phase interpolator setup. */ /*! @{ */ #define IRIS_MVPL_HSCALER9_SETUP2_phase_offset_MASK (0x1FFFFFU) #define IRIS_MVPL_HSCALER9_SETUP2_phase_offset_SHIFT (0U) /*! phase_offset - Phase shift (signed fix-point 2.19). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the right, a positive one to the left. */ #define IRIS_MVPL_HSCALER9_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_HSCALER9_SETUP2_phase_offset_MASK) /*! @} */ /*! @name HSCALER9_CONTROL - Scaler operation control. */ /*! @{ */ #define IRIS_MVPL_HSCALER9_CONTROL_mode_MASK (0x1U) #define IRIS_MVPL_HSCALER9_CONTROL_mode_SHIFT (0U) /*! mode - Switches scaler on/off in datapath. * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored. * 0b1..Scaler is active. */ #define IRIS_MVPL_HSCALER9_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_mode_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_mode_MASK) #define IRIS_MVPL_HSCALER9_CONTROL_scale_mode_MASK (0x10U) #define IRIS_MVPL_HSCALER9_CONTROL_scale_mode_SHIFT (4U) /*! scale_mode - Scale mode. * 0b0..Down-scaling (output size less or equal input size). * 0b1..Up-scaling (output size greater or equal input size) */ #define IRIS_MVPL_HSCALER9_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_scale_mode_MASK) #define IRIS_MVPL_HSCALER9_CONTROL_filter_mode_MASK (0x100U) #define IRIS_MVPL_HSCALER9_CONTROL_filter_mode_SHIFT (8U) /*! filter_mode - Selects scaling filter algorithm. * 0b0..Nearest filter (point-sampling) * 0b1..Box filter (linear) */ #define IRIS_MVPL_HSCALER9_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_filter_mode_MASK) #define IRIS_MVPL_HSCALER9_CONTROL_output_size_MASK (0x3FFF0000U) #define IRIS_MVPL_HSCALER9_CONTROL_output_size_SHIFT (16U) /*! output_size - Number of output pixel per input line. Value must be one less than actual number of pixels. */ #define IRIS_MVPL_HSCALER9_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_output_size_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_output_size_MASK) /*! @} */ /*! @name VSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name VSCALER9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name VSCALER9_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Shadow enable for RWS type configuration fields (0 = write-through, 1 = shadows enabled) */ #define IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name VSCALER9_SETUP1 - Phase interpolator setup. */ /*! @{ */ #define IRIS_MVPL_VSCALER9_SETUP1_scale_factor_MASK (0xFFFFFU) #define IRIS_MVPL_VSCALER9_SETUP1_scale_factor_SHIFT (0U) /*! scale_factor - Scale factor (unsigned fix-point 1.19). Must be greater 0.0 and less or equal * 1.0. If scale_mode is UPSCALE then the inverse scale factor must be programmed. */ #define IRIS_MVPL_VSCALER9_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP1_scale_factor_MASK) /*! @} */ /*! @name VSCALER9_SETUP2 - Phase interpolator setup, selected if input and output field polarity is 0. */ /*! @{ */ #define IRIS_MVPL_VSCALER9_SETUP2_phase_offset_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER9_SETUP2_phase_offset_SHIFT (0U) /*! phase_offset - Phase shift (signed fix-point 2.19). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the top. */ #define IRIS_MVPL_VSCALER9_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP2_phase_offset_MASK) /*! @} */ /*! @name VSCALER9_SETUP3 - Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0. */ /*! @{ */ #define IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_SHIFT (0U) /*! phase_offset1 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the * top. */ #define IRIS_MVPL_VSCALER9_SETUP3_phase_offset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_MASK) /*! @} */ /*! @name VSCALER9_SETUP4 - Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1. */ /*! @{ */ #define IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_SHIFT (0U) /*! phase_offset2 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the * top. */ #define IRIS_MVPL_VSCALER9_SETUP4_phase_offset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_MASK) /*! @} */ /*! @name VSCALER9_SETUP5 - Phase interpolator setup, selected if input and output field polarity is 1. */ /*! @{ */ #define IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_SHIFT (0U) /*! phase_offset3 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the * top. */ #define IRIS_MVPL_VSCALER9_SETUP5_phase_offset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_MASK) /*! @} */ /*! @name VSCALER9_CONTROL - Scaler operation control. */ /*! @{ */ #define IRIS_MVPL_VSCALER9_CONTROL_mode_MASK (0x1U) #define IRIS_MVPL_VSCALER9_CONTROL_mode_SHIFT (0U) /*! mode - Operation mode. * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored. * 0b1..Scaler is active. */ #define IRIS_MVPL_VSCALER9_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_mode_MASK) #define IRIS_MVPL_VSCALER9_CONTROL_scale_mode_MASK (0x10U) #define IRIS_MVPL_VSCALER9_CONTROL_scale_mode_SHIFT (4U) /*! scale_mode - Operation mode. * 0b0..Down-scaling (output size less or equal input size). * 0b1..Up-scaling (output size greater or equal input size). */ #define IRIS_MVPL_VSCALER9_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_scale_mode_MASK) #define IRIS_MVPL_VSCALER9_CONTROL_filter_mode_MASK (0x100U) #define IRIS_MVPL_VSCALER9_CONTROL_filter_mode_SHIFT (8U) /*! filter_mode - Scaling filter. * 0b0..Nearest filter (point-sampling) * 0b1..Box filter (linear) */ #define IRIS_MVPL_VSCALER9_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_filter_mode_MASK) #define IRIS_MVPL_VSCALER9_CONTROL_field_mode_MASK (0x3000U) #define IRIS_MVPL_VSCALER9_CONTROL_field_mode_SHIFT (12U) /*! field_mode - Controls generation of output field polarity. Has no effect in NEUTRAL mode. * 0b00..Constant 0 indicates frame or top field. * 0b01..Constant 1 indicates bottom field. * 0b10..Output field polarity is taken from input field polarity. * 0b11..Output field polarity toggles, starting with 0 after reset. */ #define IRIS_MVPL_VSCALER9_CONTROL_field_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_field_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_field_mode_MASK) #define IRIS_MVPL_VSCALER9_CONTROL_output_size_MASK (0x3FFF0000U) #define IRIS_MVPL_VSCALER9_CONTROL_output_size_SHIFT (16U) /*! output_size - Number of output lines per input frame. Value must be one less than actual number of pixels. */ #define IRIS_MVPL_VSCALER9_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_output_size_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_output_size_MASK) /*! @} */ /*! @name FILTER9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name FILTER9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name FILTER9_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - If ShdEn==1 shadow registers are loaded when indicated by hardware signal ( a command * signal in the data stream at frame start ). If ShdEn==0 shadow registers are loaded each frame * start. */ #define IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name FILTER9_CONTROL - Filter operation main control. */ /*! @{ */ #define IRIS_MVPL_FILTER9_CONTROL_mode_MASK (0x1U) #define IRIS_MVPL_FILTER9_CONTROL_mode_SHIFT (0U) /*! mode - The filter can be by-passed or switched by mode field. * 0b0..Neutral mode. Pixels by-pass the filter, all other settings are ignored. * 0b1..Filter is active. */ #define IRIS_MVPL_FILTER9_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_mode_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_mode_MASK) #define IRIS_MVPL_FILTER9_CONTROL_tile_mode_MASK (0x30U) #define IRIS_MVPL_FILTER9_CONTROL_tile_mode_SHIFT (4U) /*! tile_mode - Selects how filter samples outside the input frame are treated. * 0b00..Samples outside the frame are padded with the last valid border pixels. * 0b01..Samples outside the frame are treated as zero pixel value. * 0b10..Applies tile mode PAD to RGB channels and tile mode ZERO to alpha channel. */ #define IRIS_MVPL_FILTER9_CONTROL_tile_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_tile_mode_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_tile_mode_MASK) #define IRIS_MVPL_FILTER9_CONTROL_filter_mode_MASK (0xFFFF00U) #define IRIS_MVPL_FILTER9_CONTROL_filter_mode_SHIFT (8U) /*! filter_mode - Filter mode of operation is controlled by filter_mode field. * 0b0000000001010101..FIR filter 5x5 window. */ #define IRIS_MVPL_FILTER9_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_filter_mode_MASK) #define IRIS_MVPL_FILTER9_CONTROL_buffer_format_MASK (0x30000000U) #define IRIS_MVPL_FILTER9_CONTROL_buffer_format_SHIFT (28U) /*! buffer_format - Selects the pixel storage format for the line buffers. * 0b00..RGB888 format. Alpha is not filtered but set to constant value 255. * 0b01..RGBA5658 format. Alpha is filtered. * 0b10..RGBA8888 format. Alpha is filtered. The filter window is limited to 5x4. * 0b11..RGBA10.10.10.8 format. Alpha is filtered. The filter window is limited to 5x3. */ #define IRIS_MVPL_FILTER9_CONTROL_buffer_format(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_buffer_format_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_buffer_format_MASK) /*! @} */ /*! @name FILTER9_FIR_CONTROL - FIR filter operation control. */ /*! @{ */ #define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_MASK (0xFU) #define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_SHIFT (0U) /*! FIR_component_select - Bit 3 enables R or Y component for filtering, bit 2 G or U, bit 1 B or V * and bit 0 alpha component. Disabled components are by-passed. */ #define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_SHIFT)) & IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_MASK) #define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_MASK (0xF00U) #define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_SHIFT (8U) /*! FIR_exponent - FIR product sum is divided by 2**FIR_exponent and rounded. */ #define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_SHIFT)) & IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_MASK) /*! @} */ /*! @name FILTER9_COEFFICIENTS0 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_MASK (0xFFU) #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_SHIFT (0U) /*! coeff0_0 - Coefficient[0][0]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_MASK (0xFF00U) #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_SHIFT (8U) /*! coeff1_0 - Coefficient[1][0]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_MASK (0xFF0000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_SHIFT (16U) /*! coeff2_0 - Coefficient[2][0]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_MASK (0xFF000000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_SHIFT (24U) /*! coeff3_0 - Coefficient[3][0]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_MASK) /*! @} */ /*! @name FILTER9_COEFFICIENTS1 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_MASK (0xFFU) #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_SHIFT (0U) /*! coeff4_0 - Coefficient[4][0]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_MASK (0xFF00U) #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_SHIFT (8U) /*! coeff0_1 - Coefficient[0][1]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_MASK (0xFF0000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_SHIFT (16U) /*! coeff1_1 - Coefficient[1][1]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_MASK (0xFF000000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_SHIFT (24U) /*! coeff2_1 - Coefficient[2][1]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_MASK) /*! @} */ /*! @name FILTER9_COEFFICIENTS2 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_MASK (0xFFU) #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_SHIFT (0U) /*! coeff3_1 - Coefficient[3][1]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_MASK (0xFF00U) #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_SHIFT (8U) /*! coeff4_1 - Coefficient[4][1]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_MASK (0xFF0000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_SHIFT (16U) /*! coeff0_2 - Coefficient[0][2]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_MASK (0xFF000000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_SHIFT (24U) /*! coeff1_2 - Coefficient[1][2]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_MASK) /*! @} */ /*! @name FILTER9_COEFFICIENTS3 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_MASK (0xFFU) #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_SHIFT (0U) /*! coeff2_2 - Coefficient[2][2]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_MASK (0xFF00U) #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_SHIFT (8U) /*! coeff3_2 - Coefficient[3][2]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_MASK (0xFF0000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_SHIFT (16U) /*! coeff4_2 - Coefficient[4][2]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_MASK (0xFF000000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_SHIFT (24U) /*! coeff0_3 - Coefficient[0][3]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_MASK) /*! @} */ /*! @name FILTER9_COEFFICIENTS4 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_MASK (0xFFU) #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_SHIFT (0U) /*! coeff1_3 - Coefficient[1][3]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_MASK (0xFF00U) #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_SHIFT (8U) /*! coeff2_3 - Coefficient[2][3]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_MASK (0xFF0000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_SHIFT (16U) /*! coeff3_3 - Coefficient[3][3]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_MASK (0xFF000000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_SHIFT (24U) /*! coeff4_3 - Coefficient[4][3]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_MASK) /*! @} */ /*! @name FILTER9_COEFFICIENTS5 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_MASK (0xFFU) #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_SHIFT (0U) /*! coeff0_4 - Coefficient[0][4]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_MASK (0xFF00U) #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_SHIFT (8U) /*! coeff1_4 - Coefficient[1][4]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_MASK (0xFF0000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_SHIFT (16U) /*! coeff2_4 - Coefficient[2][4]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_MASK) #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_MASK (0xFF000000U) #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_SHIFT (24U) /*! coeff3_4 - Coefficient[3][4]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_MASK) /*! @} */ /*! @name FILTER9_COEFFICIENTS6 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_MASK (0xFFU) #define IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_SHIFT (0U) /*! coeff4_4 - Coefficient[4][4]. */ #define IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_MASK) /*! @} */ /*! @name BLITBLEND9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name BLITBLEND9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name BLITBLEND9_STATICCONTROL - BlitBlend static control register */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name BLITBLEND9_CONTROL - BlitBlend control register */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_CONTROL_Mode_MASK (0x1U) #define IRIS_MVPL_BLITBLEND9_CONTROL_Mode_SHIFT (0U) /*! Mode - Operation mode for BlitBlend * 0b0..Neutral mode, only route pixels and commands from primary input to output * 0b1..Normal Operation */ #define IRIS_MVPL_BLITBLEND9_CONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONTROL_Mode_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONTROL_Mode_MASK) /*! @} */ /*! @name BLITBLEND9_NEUTRALBORDER - Neutral border setup register */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_MASK (0x1U) #define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_SHIFT (0U) /*! NeutralBorderMode - Chooses whether to bypass primary or secondary input pixels * 0b0..Bypasses primary pixel * 0b1..Bypasses secondary pixel */ #define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_SHIFT)) & IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_MASK) #define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_MASK (0x700U) #define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_SHIFT (8U) /*! NeutralBorderLeft - Number of neutral left border pixels */ #define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_SHIFT)) & IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_MASK) #define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_MASK (0x7000U) #define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_SHIFT (12U) /*! NeutralBorderRight - Number of neutral right border pixels */ #define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_SHIFT)) & IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_MASK) /*! @} */ /*! @name BLITBLEND9_CONSTANTCOLOR - Constant color register */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU) #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U) /*! ConstantAlpha - Alpha. */ #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_MASK) #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U) #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_SHIFT (8U) /*! ConstantBlue - Blue and V (chroma). */ #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_MASK) #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U) #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_SHIFT (16U) /*! ConstantGreen - Green and U (chroma). */ #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_MASK) #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U) #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_SHIFT (24U) /*! ConstantRed - Red and Y (luma). */ #define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_MASK) /*! @} */ /*! @name BLITBLEND9_COLORREDBLENDFUNCTION - Open GL RGB blending factors */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_MASK (0xFFFFU) #define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_SHIFT (0U) /*! BlendFuncColorRedSrc - Red component source blend function * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_MASK) #define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_MASK (0xFFFF0000U) #define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_SHIFT (16U) /*! BlendFuncColorRedDst - Red component destination blend function * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_MASK) /*! @} */ /*! @name BLITBLEND9_COLORGREENBLENDFUNCTION - Open GL RGB blending factors */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_MASK (0xFFFFU) #define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_SHIFT (0U) /*! BlendFuncColorGreenSrc - Green component source blend function * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_MASK) #define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_MASK (0xFFFF0000U) #define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_SHIFT (16U) /*! BlendFuncColorGreenDst - Green component destination blend function * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_MASK) /*! @} */ /*! @name BLITBLEND9_COLORBLUEBLENDFUNCTION - Open GL RGB blending factors */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_MASK (0xFFFFU) #define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_SHIFT (0U) /*! BlendFuncColorBlueSrc - Blue component source blend function * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_MASK) #define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_MASK (0xFFFF0000U) #define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_SHIFT (16U) /*! BlendFuncColorBlueDst - Blue component destination blend function * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_MASK) /*! @} */ /*! @name BLITBLEND9_ALPHABLENDFUNCTION - Open GL alpha blending factors */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_MASK (0xFFFFU) #define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_SHIFT (0U) /*! BlendFuncAlphaSrc - Alpha component source blend function * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_MASK) #define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_MASK (0xFFFF0000U) #define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_SHIFT (16U) /*! BlendFuncAlphaDst - Alpha component destination blend function * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_MASK) /*! @} */ /*! @name BLITBLEND9_BLENDMODE1 - Open GL and Open VG blending modes for colors red and green */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_MASK (0xFFFFU) #define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_SHIFT (0U) /*! BlendModeColorRed - Red component blend mode * 0b1000000000000110.. * 0b1000000000000111.. * 0b1000000000001000.. * 0b1000000000001010.. * 0b1000000000001011.. * 0b0010000000000000.. * 0b0010000000000001.. * 0b0010000000000010.. * 0b0010000000000011.. * 0b0010000000000100.. * 0b0010000000000101.. * 0b0010000000000110.. * 0b0010000000000111.. * 0b0010000000001000.. * 0b0010000000001001.. */ #define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_MASK) #define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_MASK (0xFFFF0000U) #define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_SHIFT (16U) /*! BlendModeColorGreen - Green component blend mode * 0b1000000000000110.. * 0b1000000000000111.. * 0b1000000000001000.. * 0b1000000000001010.. * 0b1000000000001011.. * 0b0010000000000000.. * 0b0010000000000001.. * 0b0010000000000010.. * 0b0010000000000011.. * 0b0010000000000100.. * 0b0010000000000101.. * 0b0010000000000110.. * 0b0010000000000111.. * 0b0010000000001000.. * 0b0010000000001001.. */ #define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_MASK) /*! @} */ /*! @name BLITBLEND9_BLENDMODE2 - Open GL and Open VG blending modes for color blue and alpha */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_MASK (0xFFFFU) #define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_SHIFT (0U) /*! BlendModeColorBlue - Blue component blend mode * 0b1000000000000110.. * 0b1000000000000111.. * 0b1000000000001000.. * 0b1000000000001010.. * 0b1000000000001011.. * 0b0010000000000000.. * 0b0010000000000001.. * 0b0010000000000010.. * 0b0010000000000011.. * 0b0010000000000100.. * 0b0010000000000101.. * 0b0010000000000110.. * 0b0010000000000111.. * 0b0010000000001000.. * 0b0010000000001001.. */ #define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_MASK) #define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_MASK (0xFFFF0000U) #define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_SHIFT (16U) /*! BlendModeAlpha - Alpha component blend mode * 0b1000000000000110.. * 0b1000000000000111.. * 0b1000000000001000.. * 0b1000000000001010.. * 0b1000000000001011.. * 0b0010000000000000.. * 0b0010000000000001.. * 0b0010000000000010.. * 0b0010000000000011.. * 0b0010000000000100.. * 0b0010000000000101.. * 0b0010000000000110.. * 0b0010000000000111.. * 0b0010000000001000.. * 0b0010000000001001.. */ #define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_MASK) /*! @} */ /*! @name BLITBLEND9_DIRECTSETUP - Direct Control of the BlitBlend Datapath multiplexers, do not change */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_MASK (0x3FFU) #define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_SHIFT (0U) /*! ColorDebug - Sets the multiplexers of the color datapath directly, do not change */ #define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_SHIFT)) & IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_MASK) #define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_MASK (0x3FF0000U) #define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_SHIFT (16U) /*! AlphaDebug - Sets the multiplexers of the alpha datapath directly, do not change */ #define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_SHIFT)) & IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_MASK) /*! @} */ /*! @name BLITBLEND9_PRIMCONTROLWORD - Value of last received primary control word */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_SHIFT (0U) /*! P_VAL - Value of last received control word on primary input. If a 39 bit pixel channel is * connected, the mapping is as follows: p_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For * debug purposes only, read when stable only, otherwise read data might be corrupted. */ #define IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_MASK) /*! @} */ /*! @name BLITBLEND9_SECCONTROLWORD - Value of last received secondary control word */ /*! @{ */ #define IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_SHIFT (0U) /*! S_VAL - Value of last received control word on secondary input. If a 39 bit pixel channel is * connected, the mapping is as follows: s_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For * debug purposes only, read when stable only, otherwise read data might be corrupted. */ #define IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_MASK) /*! @} */ /*! @name STORE9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name STORE9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name STORE9_STATICCONTROL - Store unit static control register. */ /*! @{ */ #define IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_STORE9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_MASK (0x100U) #define IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (8U) /*! BaseAddressAutoUpdate - If enabled (value 1) the base address is automatically updated at the * start of each frame. This update is then executed independently of the ShdEn setting. When * disabled ShdEn controls the update of the base address operation register. */ #define IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_MASK) /*! @} */ /*! @name STORE9_BURSTBUFFERMANAGEMENT - Burst Buffer setup register. */ /*! @{ */ #define IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. Please * note that SetBurstLength has to be smaller or equal to MaxBurstLength. Only a power of two may * be specified as burst length. Please set this to at least 2 for 64bit pixels, otherwise * performance will suffer. */ #define IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK) /*! @} */ /*! @name STORE9_RINGBUFSTARTADDR - Ring buffer setup for destination. */ /*! @{ */ #define IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_MASK (0xFFFFFFFFU) #define IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_SHIFT (0U) /*! RingBufStartAddr - Start address of the ring buffer. Must be aligned to SetBurstLength x 8 bytes. */ #define IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_SHIFT)) & IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_MASK) /*! @} */ /*! @name STORE9_RINGBUFWRAPADDR - Ring buffer setup for destination. */ /*! @{ */ #define IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_MASK (0xFFFFFFFFU) #define IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_SHIFT (0U) /*! RingBufWrapAddr - End address of the ring buffer (last byte of the buffer plus one). */ #define IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_SHIFT)) & IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_MASK) /*! @} */ /*! @name STORE9_BASEADDRESS - Destination buffer base address. */ /*! @{ */ #define IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_MASK (0xFFFFFFFFU) #define IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_SHIFT (0U) /*! BaseAddress - Byte aligned start address of the destination buffer. For 32 bit pixels * BaseAddress[1:0] must be set 0 and for 16 bit pixels BaseAddress[0] must be set 0. */ #define IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_SHIFT)) & IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_MASK) /*! @} */ /*! @name STORE9_DESTINATIONBUFFERATTRIBUTES - Destination buffer attributes. */ /*! @{ */ #define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_MASK (0x1FFFFU) #define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_SHIFT (0U) /*! Stride - Destination buffer stride in bytes minus one, used for address generation. For a pixel * width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of * 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_MASK) #define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_MASK (0x7F000000U) #define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_SHIFT (24U) /*! BitsPerPixel - Size of a pixel in the destination buffer in bits. Has to be a power of two, 18 * or 24. When 64 bit is selected, input pixels are converted into a 32 bit value that is * replicated into low and high word of the 64 bit output. Set SetBurstLength at least to 2 in that case * to get best possible performance. */ #define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_MASK) /*! @} */ /*! @name STORE9_DESTINATIONBUFFERDIMENSION - Destination buffer dimension. */ /*! @{ */ #define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_MASK (0x3FFFU) #define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_SHIFT (0U) /*! LineWidth - Width of the destination buffer in pixels minus one. */ #define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_MASK) #define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_MASK (0x3FFF0000U) #define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_SHIFT (16U) /*! LineCount - Number of lines of the destination buffer in pixels minus one. */ #define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_MASK) /*! @} */ /*! @name STORE9_FRAMEOFFSET - Offset between destination frame and buffer. */ /*! @{ */ #define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_MASK (0x7FFFU) #define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_SHIFT (0U) /*! FrameXOffset - Horizontal offset (X). */ #define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_SHIFT)) & IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_MASK) #define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_MASK (0x7FFF0000U) #define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_SHIFT (16U) /*! FrameYOffset - Vertical offset (Y). */ #define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_SHIFT)) & IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_MASK) /*! @} */ /*! @name STORE9_COLORCOMPONENTBITS - Color component size of destination buffer */ /*! @{ */ #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK (0xFU) #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT (0U) /*! ComponentBitsAlpha - Alpha component bits. */ #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK) #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_MASK (0xF00U) #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT (8U) /*! ComponentBitsBlue - Blue/V component bits. */ #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_MASK) #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_MASK (0xF0000U) #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT (16U) /*! ComponentBitsGreen - Green/U component bits. */ #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_MASK) #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_MASK (0xF000000U) #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT (24U) /*! ComponentBitsRed - Red/Y component bits. */ #define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_MASK) /*! @} */ /*! @name STORE9_COLORCOMPONENTSHIFT - Color component offset of destination buffer. */ /*! @{ */ #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK (0x1FU) #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT (0U) /*! ComponentShiftAlpha - Alpha component shift. */ #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK) #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK (0x1F00U) #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT (8U) /*! ComponentShiftBlue - Blue/V component shift. */ #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK) #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK (0x1F0000U) #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT (16U) /*! ComponentShiftGreen - Green/U component shift. */ #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK) #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK (0x1F000000U) #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT (24U) /*! ComponentShiftRed - Red/Y component shift. */ #define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK) /*! @} */ /*! @name STORE9_CONTROL - Store unit dynamic control register */ /*! @{ */ #define IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_MASK (0x1U) #define IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_SHIFT (0U) /*! ColorDitherEnable - Controls whether spatial dithering (value 1) or LSB truncation (value 0) is * used when ComponentBitsRed/Green/Blue is smaller than 10 bits for Store derivate or 8 bit for * StoreL derivate. */ #define IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_MASK) #define IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_MASK (0x2U) #define IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_SHIFT (1U) /*! AlphaDitherEnable - Controls whether spatial dithering (value 1) or LSB truncation (value 0) is * used when ComponentBitsAlpha is smaller than 8 bits. */ #define IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_MASK) #define IRIS_MVPL_STORE9_CONTROL_DitherOffset_MASK (0xF0U) #define IRIS_MVPL_STORE9_CONTROL_DitherOffset_SHIFT (4U) /*! DitherOffset - Dither offset that is additionally applied to the spatial offset, which is * internally generated from the pixel position. Can be used by SW to generate image sequences with * temporal dithering. */ #define IRIS_MVPL_STORE9_CONTROL_DitherOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_DitherOffset_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_DitherOffset_MASK) #define IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_MASK (0x1000U) #define IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_SHIFT (12U) /*! GammaApplyEnable - Enable gamma conversion stage to apply gamma function. This gamma function * converts the pixel data from linear color space to non-linear color space before writing it to * AXI. */ #define IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_MASK) #define IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_MASK (0x30000U) #define IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_SHIFT (16U) /*! YUVConversionMode - Enables different kind of RGB to YUV conversions. * 0b00..No conversion. Input data must be RGB. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_STORE9_CONTROL_YUVConversionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_MASK) #define IRIS_MVPL_STORE9_CONTROL_RasterMode_MASK (0xC0000U) #define IRIS_MVPL_STORE9_CONTROL_RasterMode_SHIFT (18U) /*! RasterMode - Selects a method for destination buffer data from input pixels. * 0b00..RGBA or YUV 4:4:4 pixel buffer. * 0b01..[Store derivate only] Packed YUV 4:2:2 pixel buffer. Effect is that U samples are written for pixels * with even and V samples for odd column index only. So BitsPerPixel must be set to the size that a pair of YU * or YV has in memory (most typically 16 bits). All correlated widths and horizontal offsets must be even. * 0b10..[Store derivate only] RLAD compressed bit stream. */ #define IRIS_MVPL_STORE9_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_RasterMode_MASK) #define IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_MASK (0x300000U) #define IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_SHIFT (20U) /*! YUV422DownsamplingMode - Selects a method for horizontal down-sampling when RasterMode is YUV422. * 0b00..Nearest mode. Discards all odd samples, outputs even samples. * 0b01..Linear coaligned mode. 3 nearest UV samples are combined in linear filter to get one output sample. * 0b10..Linear interspersed mode. 2 nearest UV samples are combined in linear filter to get one output sample. */ #define IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_MASK) /*! @} */ /*! @name STORE9_ENCODECONTROL - Control options for RLAD compression. */ /*! @{ */ #define IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_MASK (0x1U) #define IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_SHIFT (0U) /*! CompressionMode - Algorithm to use for compression. * 0b0..Run-Length Adaptive Dithering (lossy compression). * 0b1..Run-Length Adaptive Dithering (lossy compression; uniform package size). */ #define IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_MASK) #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_MASK (0xF0000U) #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_SHIFT (16U) /*! RLADCompBitsRed - Maximum for average number of bits per compressed pixel for Red or Y (luma) channel. */ #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_MASK) #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_MASK (0xF00000U) #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_SHIFT (20U) /*! RLADCompBitsGreen - Maximum for average number of bits per compressed pixel for Green or U (chroma) channel. */ #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_MASK) #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_MASK (0xF000000U) #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_SHIFT (24U) /*! RLADCompBitsBlue - Maximum for average number of bits per compressed pixel for Blue or V (chroma) channel. */ #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_MASK) #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_MASK (0xF0000000U) #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_SHIFT (28U) /*! RLADCompBitsAlpha - Maximum for average number of bits per compressed pixel for Alpha channel. */ #define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_MASK) /*! @} */ /*! @name STORE9_DESTINATIONBUFFERLENGTH - Destination buffer length for compressed data. */ /*! @{ */ #define IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_MASK (0x1FFFFFFFU) #define IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_SHIFT (0U) /*! RLEWordsMax - Number of 32-bit words minus one that are reserved for the destination buffer in * case that RasterMode is ENCODE. The actual number used can be read from RLEWords field. */ #define IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_MASK) /*! @} */ /*! @name STORE9_START - Store unit start register */ /*! @{ */ #define IRIS_MVPL_STORE9_START_Start_MASK (0x1U) #define IRIS_MVPL_STORE9_START_Start_SHIFT (0U) /*! Start - Writing a one starts processing of the pixel engine. */ #define IRIS_MVPL_STORE9_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_START_Start_SHIFT)) & IRIS_MVPL_STORE9_START_Start_MASK) /*! @} */ /*! @name STORE9_ENCODERSTATUS - Status information of the RLAD encoder. */ /*! @{ */ #define IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_MASK (0x1FFFFFFFU) #define IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_SHIFT (0U) /*! RLEWords - Number of 32-bit words minus one that was used for the compressed buffer. */ #define IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_SHIFT)) & IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_MASK) #define IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_MASK (0x80000000U) #define IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_SHIFT (31U) /*! BufferTooSmall - The buffer size given by RLEWordsMax is too small. Not the complete input frame could be encoded. */ #define IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_SHIFT)) & IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_MASK) /*! @} */ /*! @name STORE9_WRITEADDRESS - Ring buffer synchronization. */ /*! @{ */ #define IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_MASK (0xFFFFFFFFU) #define IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_SHIFT (0U) /*! WriteAddress - Last burst address that was written to the destination buffer. */ #define IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_SHIFT)) & IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_MASK) /*! @} */ /*! @name STORE9_FRAMEPROPERTIES - Ring buffer synchronization. */ /*! @{ */ #define IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_MASK (0x1U) #define IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_SHIFT (0U) /*! FieldId - Field identifier for interlaced video streams (0/1 = even/odd line indices of * progressive frame). Status is updated with begin of a new field. */ #define IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_SHIFT)) & IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_MASK) /*! @} */ /*! @name STORE9_BURSTBUFFERPROPERTIES - Burst Buffer Property register */ /*! @{ */ #define IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_MASK (0x1F00U) #define IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_SHIFT (8U) /*! MaxBurstLength - Maximum Burst Length that can be configured. */ #define IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_SHIFT)) & IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_MASK) /*! @} */ /*! @name STORE9_LASTCONTROLWORD - Shows the last control word received */ /*! @{ */ #define IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_SHIFT (0U) /*! L_VAL - Shows the last control word received from the pixel engine. If a 39 bit pixel channel is * connected, the mapping is as follows: l_val[31:0] = { data[37:22], data[19:12], data[9:2] }. * For debug purposes only, read when stable only, otherwise read data might be corrupted. */ #define IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_MASK) /*! @} */ /*! @name STORE9_PERFCOUNTER - Performance counter result */ /*! @{ */ #define IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU) #define IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_SHIFT (0U) /*! PerfResult - Returns the performance counter value. Please note that a sw reset during a frame * can potentially produce invalid results in the first frame afterwards. For debug purposes only, * read when stable only, otherwise read data might be corrupted. */ #define IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_MASK) /*! @} */ /*! @name STORE9_STATUS - Shows status information */ /*! @{ */ #define IRIS_MVPL_STORE9_STATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_STORE9_STATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Store unit is busy */ #define IRIS_MVPL_STORE9_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusBusy_MASK) #define IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle */ #define IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_MASK) #define IRIS_MVPL_STORE9_STATUS_StatusRequest_MASK (0x20U) #define IRIS_MVPL_STORE9_STATUS_StatusRequest_SHIFT (5U) /*! StatusRequest - Store unit requesting on the AXI interface, waiting for acknowledge */ #define IRIS_MVPL_STORE9_STATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusRequest_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusRequest_MASK) #define IRIS_MVPL_STORE9_STATUS_StatusComplete_MASK (0x40U) #define IRIS_MVPL_STORE9_STATUS_StatusComplete_SHIFT (6U) /*! StatusComplete - Store unit completed all requested AXI transfers */ #define IRIS_MVPL_STORE9_STATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusComplete_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusComplete_MASK) #define IRIS_MVPL_STORE9_STATUS_PixelbusError_MASK (0x100U) #define IRIS_MVPL_STORE9_STATUS_PixelbusError_SHIFT (8U) /*! PixelbusError - A pixel bus error has occured. Write 1 to clear. */ #define IRIS_MVPL_STORE9_STATUS_PixelbusError(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_PixelbusError_SHIFT)) & IRIS_MVPL_STORE9_STATUS_PixelbusError_MASK) #define IRIS_MVPL_STORE9_STATUS_EncoderOverflow_MASK (0x10000U) #define IRIS_MVPL_STORE9_STATUS_EncoderOverflow_SHIFT (16U) /*! EncoderOverflow - An overflow error has occured in encoder. Write 1 to clear. */ #define IRIS_MVPL_STORE9_STATUS_EncoderOverflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_EncoderOverflow_SHIFT)) & IRIS_MVPL_STORE9_STATUS_EncoderOverflow_MASK) #define IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_MASK (0x20000U) #define IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_SHIFT (17U) /*! EncoderStallPixel - The encoder stalled input pixels during a frame. Write 1 to clear. */ #define IRIS_MVPL_STORE9_STATUS_EncoderStallPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_SHIFT)) & IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_MASK) /*! @} */ /*! @name CONSTFRAME0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name CONSTFRAME0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name CONSTFRAME0_STATICCONTROL - ConstFrame unit static control register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name CONSTFRAME0_FRAMEDIMENSIONS - Output frame dimensions. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width in pixels minus one. */ #define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height in pixels minus one. */ #define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). */ #define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name CONSTFRAME0_CONSTANTCOLOR - Color of output frame. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU) #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U) /*! ConstantAlpha - Alpha component. */ #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_MASK) #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U) #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_SHIFT (8U) /*! ConstantBlue - Blue component. */ #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_MASK) #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U) #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_SHIFT (16U) /*! ConstantGreen - Green component. */ #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_MASK) #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U) #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_SHIFT (24U) /*! ConstantRed - Red component. */ #define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_MASK) /*! @} */ /*! @name CONSTFRAME0_CONTROLTRIGGER - ConstFrame unit trigger register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name CONSTFRAME0_START - ConstFrame unit start register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME0_START_Start_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME0_START_Start_SHIFT (0U) /*! Start - Writing a one starts processing, it is recommended to use this for debug purposes only. */ #define IRIS_MVPL_CONSTFRAME0_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_START_Start_SHIFT)) & IRIS_MVPL_CONSTFRAME0_START_Start_MASK) /*! @} */ /*! @name CONSTFRAME0_STATUS - Shows status information */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Unit is busy. */ #define IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_MASK) #define IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_MASK (0x2U) #define IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_SHIFT (1U) /*! ShadowStatus - Shadow load status. 1 if shadow load has been triggered and not yet consumed, 0 * if shadow load is already consumed or has not yet been triggered. */ #define IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_MASK) /*! @} */ /*! @name EXTDST0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name EXTDST0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name EXTDST0_STATICCONTROL - External Destination static control register */ /*! @{ */ #define IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_MASK (0x100U) #define IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_SHIFT (8U) /*! KICK_MODE - Operation mode of generated kick signal * 0b0..kick generation by KICK field only * 0b1..kick signal from external allowed */ #define IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_SHIFT)) & IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_MASK) #define IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_MASK (0x1000U) #define IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_SHIFT (12U) /*! PerfCountMode - Value 1 enables performance counter mode, which does not generate an output * frame but processes input data as fast as possible instead. Can be used to determine the maximum * possible read-out performance of display buffers. */ #define IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_SHIFT)) & IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_MASK) /*! @} */ /*! @name EXTDST0_CONTROL - External Destination shadowed control register */ /*! @{ */ #define IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_MASK (0x1U) #define IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_SHIFT (0U) /*! GammaApplyEnable - Enable gamma conversion stage to apply gamma function. This gamma function * converts the pixel data from linear color space to non-linear color space before they are output. */ #define IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_MASK) /*! @} */ /*! @name EXTDST0_SOFTWAREKICK - External Destination software kick */ /*! @{ */ #define IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_MASK (0x1U) #define IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_SHIFT (0U) /*! KICK - Software kick, forces a kick signal independent of KICK_MODE. Write 1 to send kick. */ #define IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_SHIFT)) & IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_MASK) /*! @} */ /*! @name EXTDST0_STATUS - External Destination Unit current status */ /*! @{ */ #define IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_MASK (0x1U) #define IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_SHIFT (0U) /*! CNT_ERR_STS - Pixel count error */ #define IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_SHIFT)) & IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_MASK) /*! @} */ /*! @name EXTDST0_CONTROLWORD - Value of last received control word */ /*! @{ */ #define IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_SHIFT (0U) /*! CW_VAL - Value of last received control word */ #define IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_SHIFT)) & IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_MASK) /*! @} */ /*! @name EXTDST0_CURPIXELCNT - pixel count of currently running frame */ /*! @{ */ #define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_MASK (0xFFFFU) #define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_SHIFT (0U) /*! C_XVAL - value of horizontal pixel counter, internal counter counting from max-1 to 0 */ #define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_SHIFT)) & IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_MASK) #define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_MASK (0xFFFF0000U) #define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_SHIFT (16U) /*! C_YVAL - value of vertical line counter, internal counter counting from max-1 to 0 */ #define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_SHIFT)) & IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_MASK) /*! @} */ /*! @name EXTDST0_LASTPIXELCNT - pixel count between last two control words */ /*! @{ */ #define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_MASK (0xFFFFU) #define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_SHIFT (0U) /*! L_XVAL - value of horizontal pixel counter */ #define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_SHIFT)) & IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_MASK) #define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_MASK (0xFFFF0000U) #define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_SHIFT (16U) /*! L_YVAL - value of vertical line counter */ #define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_SHIFT)) & IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_MASK) /*! @} */ /*! @name EXTDST0_PERFCOUNTER - Performance counter result */ /*! @{ */ #define IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_SHIFT (0U) /*! PerfResult - Returns the performance counter value. Returns number of cycles of the last frame * on the input. To calculate the performance divide the known number of pixels of the frame by * this number. For debug purposes only, read when stable only, otherwise read data might be * corrupted. */ #define IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_MASK) /*! @} */ /*! @name CONSTFRAME4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name CONSTFRAME4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name CONSTFRAME4_STATICCONTROL - ConstFrame unit static control register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name CONSTFRAME4_FRAMEDIMENSIONS - Output frame dimensions. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width in pixels minus one. */ #define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height in pixels minus one. */ #define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). */ #define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name CONSTFRAME4_CONSTANTCOLOR - Color of output frame. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU) #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U) /*! ConstantAlpha - Alpha component. */ #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_MASK) #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U) #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_SHIFT (8U) /*! ConstantBlue - Blue component. */ #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_MASK) #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U) #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_SHIFT (16U) /*! ConstantGreen - Green component. */ #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_MASK) #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U) #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_SHIFT (24U) /*! ConstantRed - Red component. */ #define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_MASK) /*! @} */ /*! @name CONSTFRAME4_CONTROLTRIGGER - ConstFrame unit trigger register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name CONSTFRAME4_START - ConstFrame unit start register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME4_START_Start_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME4_START_Start_SHIFT (0U) /*! Start - Writing a one starts processing, it is recommended to use this for debug purposes only. */ #define IRIS_MVPL_CONSTFRAME4_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_START_Start_SHIFT)) & IRIS_MVPL_CONSTFRAME4_START_Start_MASK) /*! @} */ /*! @name CONSTFRAME4_STATUS - Shows status information */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Unit is busy. */ #define IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_MASK) #define IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_MASK (0x2U) #define IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_SHIFT (1U) /*! ShadowStatus - Shadow load status. 1 if shadow load has been triggered and not yet consumed, 0 * if shadow load is already consumed or has not yet been triggered. */ #define IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_MASK) /*! @} */ /*! @name EXTDST4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name EXTDST4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST4_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_EXTDST4_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_EXTDST4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST4_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_EXTDST4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_EXTDST4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_EXTDST4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST4_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_EXTDST4_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_EXTDST4_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_EXTDST4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST4_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name EXTDST4_STATICCONTROL - External Destination static control register */ /*! @{ */ #define IRIS_MVPL_EXTDST4_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_EXTDST4_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_EXTDST4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST4_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_EXTDST4_STATICCONTROL_KICK_MODE_MASK (0x100U) #define IRIS_MVPL_EXTDST4_STATICCONTROL_KICK_MODE_SHIFT (8U) /*! KICK_MODE - Operation mode of generated kick signal * 0b0..kick generation by KICK field only * 0b1..kick signal from external allowed */ #define IRIS_MVPL_EXTDST4_STATICCONTROL_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_STATICCONTROL_KICK_MODE_SHIFT)) & IRIS_MVPL_EXTDST4_STATICCONTROL_KICK_MODE_MASK) #define IRIS_MVPL_EXTDST4_STATICCONTROL_PerfCountMode_MASK (0x1000U) #define IRIS_MVPL_EXTDST4_STATICCONTROL_PerfCountMode_SHIFT (12U) /*! PerfCountMode - Value 1 enables performance counter mode, which does not generate an output * frame but processes input data as fast as possible instead. Can be used to determine the maximum * possible read-out performance of display buffers. */ #define IRIS_MVPL_EXTDST4_STATICCONTROL_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_STATICCONTROL_PerfCountMode_SHIFT)) & IRIS_MVPL_EXTDST4_STATICCONTROL_PerfCountMode_MASK) /*! @} */ /*! @name EXTDST4_CONTROL - External Destination shadowed control register */ /*! @{ */ #define IRIS_MVPL_EXTDST4_CONTROL_GammaApplyEnable_MASK (0x1U) #define IRIS_MVPL_EXTDST4_CONTROL_GammaApplyEnable_SHIFT (0U) /*! GammaApplyEnable - Enable gamma conversion stage to apply gamma function. This gamma function * converts the pixel data from linear color space to non-linear color space before they are output. */ #define IRIS_MVPL_EXTDST4_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_EXTDST4_CONTROL_GammaApplyEnable_MASK) /*! @} */ /*! @name EXTDST4_SOFTWAREKICK - External Destination software kick */ /*! @{ */ #define IRIS_MVPL_EXTDST4_SOFTWAREKICK_KICK_MASK (0x1U) #define IRIS_MVPL_EXTDST4_SOFTWAREKICK_KICK_SHIFT (0U) /*! KICK - Software kick, forces a kick signal independent of KICK_MODE. Write 1 to send kick. */ #define IRIS_MVPL_EXTDST4_SOFTWAREKICK_KICK(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_SOFTWAREKICK_KICK_SHIFT)) & IRIS_MVPL_EXTDST4_SOFTWAREKICK_KICK_MASK) /*! @} */ /*! @name EXTDST4_STATUS - External Destination Unit current status */ /*! @{ */ #define IRIS_MVPL_EXTDST4_STATUS_CNT_ERR_STS_MASK (0x1U) #define IRIS_MVPL_EXTDST4_STATUS_CNT_ERR_STS_SHIFT (0U) /*! CNT_ERR_STS - Pixel count error */ #define IRIS_MVPL_EXTDST4_STATUS_CNT_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_STATUS_CNT_ERR_STS_SHIFT)) & IRIS_MVPL_EXTDST4_STATUS_CNT_ERR_STS_MASK) /*! @} */ /*! @name EXTDST4_CONTROLWORD - Value of last received control word */ /*! @{ */ #define IRIS_MVPL_EXTDST4_CONTROLWORD_CW_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST4_CONTROLWORD_CW_VAL_SHIFT (0U) /*! CW_VAL - Value of last received control word */ #define IRIS_MVPL_EXTDST4_CONTROLWORD_CW_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_CONTROLWORD_CW_VAL_SHIFT)) & IRIS_MVPL_EXTDST4_CONTROLWORD_CW_VAL_MASK) /*! @} */ /*! @name EXTDST4_CURPIXELCNT - pixel count of currently running frame */ /*! @{ */ #define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_XVAL_MASK (0xFFFFU) #define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_XVAL_SHIFT (0U) /*! C_XVAL - value of horizontal pixel counter, internal counter counting from max-1 to 0 */ #define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_CURPIXELCNT_C_XVAL_SHIFT)) & IRIS_MVPL_EXTDST4_CURPIXELCNT_C_XVAL_MASK) #define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_YVAL_MASK (0xFFFF0000U) #define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_YVAL_SHIFT (16U) /*! C_YVAL - value of vertical line counter, internal counter counting from max-1 to 0 */ #define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_CURPIXELCNT_C_YVAL_SHIFT)) & IRIS_MVPL_EXTDST4_CURPIXELCNT_C_YVAL_MASK) /*! @} */ /*! @name EXTDST4_LASTPIXELCNT - pixel count between last two control words */ /*! @{ */ #define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_XVAL_MASK (0xFFFFU) #define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_XVAL_SHIFT (0U) /*! L_XVAL - value of horizontal pixel counter */ #define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_XVAL_SHIFT)) & IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_XVAL_MASK) #define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_YVAL_MASK (0xFFFF0000U) #define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_YVAL_SHIFT (16U) /*! L_YVAL - value of vertical line counter */ #define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_YVAL_SHIFT)) & IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_YVAL_MASK) /*! @} */ /*! @name EXTDST4_PERFCOUNTER - Performance counter result */ /*! @{ */ #define IRIS_MVPL_EXTDST4_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST4_PERFCOUNTER_PerfResult_SHIFT (0U) /*! PerfResult - Returns the performance counter value. Returns number of cycles of the last frame * on the input. To calculate the performance divide the known number of pixels of the frame by * this number. For debug purposes only, read when stable only, otherwise read data might be * corrupted. */ #define IRIS_MVPL_EXTDST4_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_EXTDST4_PERFCOUNTER_PerfResult_MASK) /*! @} */ /*! @name CONSTFRAME1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CONSTFRAME1_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CONSTFRAME1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME1_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name CONSTFRAME1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name CONSTFRAME1_STATICCONTROL - ConstFrame unit static control register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME1_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME1_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_CONSTFRAME1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CONSTFRAME1_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name CONSTFRAME1_FRAMEDIMENSIONS - Output frame dimensions. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width in pixels minus one. */ #define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height in pixels minus one. */ #define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). */ #define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name CONSTFRAME1_CONSTANTCOLOR - Color of output frame. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU) #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U) /*! ConstantAlpha - Alpha component. */ #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantAlpha_MASK) #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U) #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantBlue_SHIFT (8U) /*! ConstantBlue - Blue component. */ #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantBlue_MASK) #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U) #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantGreen_SHIFT (16U) /*! ConstantGreen - Green component. */ #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantGreen_MASK) #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U) #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantRed_SHIFT (24U) /*! ConstantRed - Red component. */ #define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantRed_MASK) /*! @} */ /*! @name CONSTFRAME1_CONTROLTRIGGER - ConstFrame unit trigger register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME1_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME1_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_CONSTFRAME1_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_CONSTFRAME1_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name CONSTFRAME1_START - ConstFrame unit start register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME1_START_Start_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME1_START_Start_SHIFT (0U) /*! Start - Writing a one starts processing, it is recommended to use this for debug purposes only. */ #define IRIS_MVPL_CONSTFRAME1_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_START_Start_SHIFT)) & IRIS_MVPL_CONSTFRAME1_START_Start_MASK) /*! @} */ /*! @name CONSTFRAME1_STATUS - Shows status information */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME1_STATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME1_STATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Unit is busy. */ #define IRIS_MVPL_CONSTFRAME1_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_CONSTFRAME1_STATUS_StatusBusy_MASK) #define IRIS_MVPL_CONSTFRAME1_STATUS_ShadowStatus_MASK (0x2U) #define IRIS_MVPL_CONSTFRAME1_STATUS_ShadowStatus_SHIFT (1U) /*! ShadowStatus - Shadow load status. 1 if shadow load has been triggered and not yet consumed, 0 * if shadow load is already consumed or has not yet been triggered. */ #define IRIS_MVPL_CONSTFRAME1_STATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_STATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME1_STATUS_ShadowStatus_MASK) /*! @} */ /*! @name EXTDST1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST1_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_EXTDST1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST1_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name EXTDST1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST1_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_EXTDST1_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_EXTDST1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST1_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_EXTDST1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_EXTDST1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_EXTDST1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST1_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_EXTDST1_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_EXTDST1_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_EXTDST1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST1_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name EXTDST1_STATICCONTROL - External Destination static control register */ /*! @{ */ #define IRIS_MVPL_EXTDST1_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_EXTDST1_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_EXTDST1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST1_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_EXTDST1_STATICCONTROL_KICK_MODE_MASK (0x100U) #define IRIS_MVPL_EXTDST1_STATICCONTROL_KICK_MODE_SHIFT (8U) /*! KICK_MODE - Operation mode of generated kick signal * 0b0..kick generation by KICK field only * 0b1..kick signal from external allowed */ #define IRIS_MVPL_EXTDST1_STATICCONTROL_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATICCONTROL_KICK_MODE_SHIFT)) & IRIS_MVPL_EXTDST1_STATICCONTROL_KICK_MODE_MASK) #define IRIS_MVPL_EXTDST1_STATICCONTROL_PerfCountMode_MASK (0x1000U) #define IRIS_MVPL_EXTDST1_STATICCONTROL_PerfCountMode_SHIFT (12U) /*! PerfCountMode - Value 1 enables performance counter mode, which does not generate an output * frame but processes input data as fast as possible instead. Can be used to determine the maximum * possible read-out performance of display buffers. */ #define IRIS_MVPL_EXTDST1_STATICCONTROL_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATICCONTROL_PerfCountMode_SHIFT)) & IRIS_MVPL_EXTDST1_STATICCONTROL_PerfCountMode_MASK) /*! @} */ /*! @name EXTDST1_CONTROL - External Destination shadowed control register */ /*! @{ */ #define IRIS_MVPL_EXTDST1_CONTROL_GammaApplyEnable_MASK (0x1U) #define IRIS_MVPL_EXTDST1_CONTROL_GammaApplyEnable_SHIFT (0U) /*! GammaApplyEnable - Enable gamma conversion stage to apply gamma function. This gamma function * converts the pixel data from linear color space to non-linear color space before they are output. */ #define IRIS_MVPL_EXTDST1_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_EXTDST1_CONTROL_GammaApplyEnable_MASK) /*! @} */ /*! @name EXTDST1_SOFTWAREKICK - External Destination software kick */ /*! @{ */ #define IRIS_MVPL_EXTDST1_SOFTWAREKICK_KICK_MASK (0x1U) #define IRIS_MVPL_EXTDST1_SOFTWAREKICK_KICK_SHIFT (0U) /*! KICK - Software kick, forces a kick signal independent of KICK_MODE. Write 1 to send kick. */ #define IRIS_MVPL_EXTDST1_SOFTWAREKICK_KICK(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_SOFTWAREKICK_KICK_SHIFT)) & IRIS_MVPL_EXTDST1_SOFTWAREKICK_KICK_MASK) /*! @} */ /*! @name EXTDST1_STATUS - External Destination Unit current status */ /*! @{ */ #define IRIS_MVPL_EXTDST1_STATUS_CNT_ERR_STS_MASK (0x1U) #define IRIS_MVPL_EXTDST1_STATUS_CNT_ERR_STS_SHIFT (0U) /*! CNT_ERR_STS - Pixel count error */ #define IRIS_MVPL_EXTDST1_STATUS_CNT_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATUS_CNT_ERR_STS_SHIFT)) & IRIS_MVPL_EXTDST1_STATUS_CNT_ERR_STS_MASK) /*! @} */ /*! @name EXTDST1_CONTROLWORD - Value of last received control word */ /*! @{ */ #define IRIS_MVPL_EXTDST1_CONTROLWORD_CW_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST1_CONTROLWORD_CW_VAL_SHIFT (0U) /*! CW_VAL - Value of last received control word */ #define IRIS_MVPL_EXTDST1_CONTROLWORD_CW_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_CONTROLWORD_CW_VAL_SHIFT)) & IRIS_MVPL_EXTDST1_CONTROLWORD_CW_VAL_MASK) /*! @} */ /*! @name EXTDST1_CURPIXELCNT - pixel count of currently running frame */ /*! @{ */ #define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_XVAL_MASK (0xFFFFU) #define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_XVAL_SHIFT (0U) /*! C_XVAL - value of horizontal pixel counter, internal counter counting from max-1 to 0 */ #define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_CURPIXELCNT_C_XVAL_SHIFT)) & IRIS_MVPL_EXTDST1_CURPIXELCNT_C_XVAL_MASK) #define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_YVAL_MASK (0xFFFF0000U) #define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_YVAL_SHIFT (16U) /*! C_YVAL - value of vertical line counter, internal counter counting from max-1 to 0 */ #define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_CURPIXELCNT_C_YVAL_SHIFT)) & IRIS_MVPL_EXTDST1_CURPIXELCNT_C_YVAL_MASK) /*! @} */ /*! @name EXTDST1_LASTPIXELCNT - pixel count between last two control words */ /*! @{ */ #define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_XVAL_MASK (0xFFFFU) #define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_XVAL_SHIFT (0U) /*! L_XVAL - value of horizontal pixel counter */ #define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_XVAL_SHIFT)) & IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_XVAL_MASK) #define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_YVAL_MASK (0xFFFF0000U) #define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_YVAL_SHIFT (16U) /*! L_YVAL - value of vertical line counter */ #define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_YVAL_SHIFT)) & IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_YVAL_MASK) /*! @} */ /*! @name EXTDST1_PERFCOUNTER - Performance counter result */ /*! @{ */ #define IRIS_MVPL_EXTDST1_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST1_PERFCOUNTER_PerfResult_SHIFT (0U) /*! PerfResult - Returns the performance counter value. Returns number of cycles of the last frame * on the input. To calculate the performance divide the known number of pixels of the frame by * this number. For debug purposes only, read when stable only, otherwise read data might be * corrupted. */ #define IRIS_MVPL_EXTDST1_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_EXTDST1_PERFCOUNTER_PerfResult_MASK) /*! @} */ /*! @name CONSTFRAME5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_CONSTFRAME5_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_CONSTFRAME5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME5_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name CONSTFRAME5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name CONSTFRAME5_STATICCONTROL - ConstFrame unit static control register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME5_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME5_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_CONSTFRAME5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CONSTFRAME5_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name CONSTFRAME5_FRAMEDIMENSIONS - Output frame dimensions. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width in pixels minus one. */ #define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height in pixels minus one. */ #define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). */ #define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name CONSTFRAME5_CONSTANTCOLOR - Color of output frame. */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU) #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U) /*! ConstantAlpha - Alpha component. */ #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantAlpha_MASK) #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U) #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantBlue_SHIFT (8U) /*! ConstantBlue - Blue component. */ #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantBlue_MASK) #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U) #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantGreen_SHIFT (16U) /*! ConstantGreen - Green component. */ #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantGreen_MASK) #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U) #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantRed_SHIFT (24U) /*! ConstantRed - Red component. */ #define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantRed_MASK) /*! @} */ /*! @name CONSTFRAME5_CONTROLTRIGGER - ConstFrame unit trigger register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME5_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME5_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_CONSTFRAME5_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_CONSTFRAME5_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name CONSTFRAME5_START - ConstFrame unit start register */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME5_START_Start_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME5_START_Start_SHIFT (0U) /*! Start - Writing a one starts processing, it is recommended to use this for debug purposes only. */ #define IRIS_MVPL_CONSTFRAME5_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_START_Start_SHIFT)) & IRIS_MVPL_CONSTFRAME5_START_Start_MASK) /*! @} */ /*! @name CONSTFRAME5_STATUS - Shows status information */ /*! @{ */ #define IRIS_MVPL_CONSTFRAME5_STATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_CONSTFRAME5_STATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Unit is busy. */ #define IRIS_MVPL_CONSTFRAME5_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_CONSTFRAME5_STATUS_StatusBusy_MASK) #define IRIS_MVPL_CONSTFRAME5_STATUS_ShadowStatus_MASK (0x2U) #define IRIS_MVPL_CONSTFRAME5_STATUS_ShadowStatus_SHIFT (1U) /*! ShadowStatus - Shadow load status. 1 if shadow load has been triggered and not yet consumed, 0 * if shadow load is already consumed or has not yet been triggered. */ #define IRIS_MVPL_CONSTFRAME5_STATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_STATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME5_STATUS_ShadowStatus_MASK) /*! @} */ /*! @name EXTDST5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST5_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_EXTDST5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST5_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name EXTDST5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_EXTDST5_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_EXTDST5_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_EXTDST5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST5_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_EXTDST5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_EXTDST5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_EXTDST5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST5_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_EXTDST5_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_EXTDST5_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_EXTDST5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST5_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name EXTDST5_STATICCONTROL - External Destination static control register */ /*! @{ */ #define IRIS_MVPL_EXTDST5_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_EXTDST5_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_EXTDST5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST5_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_EXTDST5_STATICCONTROL_KICK_MODE_MASK (0x100U) #define IRIS_MVPL_EXTDST5_STATICCONTROL_KICK_MODE_SHIFT (8U) /*! KICK_MODE - Operation mode of generated kick signal * 0b0..kick generation by KICK field only * 0b1..kick signal from external allowed */ #define IRIS_MVPL_EXTDST5_STATICCONTROL_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATICCONTROL_KICK_MODE_SHIFT)) & IRIS_MVPL_EXTDST5_STATICCONTROL_KICK_MODE_MASK) #define IRIS_MVPL_EXTDST5_STATICCONTROL_PerfCountMode_MASK (0x1000U) #define IRIS_MVPL_EXTDST5_STATICCONTROL_PerfCountMode_SHIFT (12U) /*! PerfCountMode - Value 1 enables performance counter mode, which does not generate an output * frame but processes input data as fast as possible instead. Can be used to determine the maximum * possible read-out performance of display buffers. */ #define IRIS_MVPL_EXTDST5_STATICCONTROL_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATICCONTROL_PerfCountMode_SHIFT)) & IRIS_MVPL_EXTDST5_STATICCONTROL_PerfCountMode_MASK) /*! @} */ /*! @name EXTDST5_CONTROL - External Destination shadowed control register */ /*! @{ */ #define IRIS_MVPL_EXTDST5_CONTROL_GammaApplyEnable_MASK (0x1U) #define IRIS_MVPL_EXTDST5_CONTROL_GammaApplyEnable_SHIFT (0U) /*! GammaApplyEnable - Enable gamma conversion stage to apply gamma function. This gamma function * converts the pixel data from linear color space to non-linear color space before they are output. */ #define IRIS_MVPL_EXTDST5_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_EXTDST5_CONTROL_GammaApplyEnable_MASK) /*! @} */ /*! @name EXTDST5_SOFTWAREKICK - External Destination software kick */ /*! @{ */ #define IRIS_MVPL_EXTDST5_SOFTWAREKICK_KICK_MASK (0x1U) #define IRIS_MVPL_EXTDST5_SOFTWAREKICK_KICK_SHIFT (0U) /*! KICK - Software kick, forces a kick signal independent of KICK_MODE. Write 1 to send kick. */ #define IRIS_MVPL_EXTDST5_SOFTWAREKICK_KICK(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_SOFTWAREKICK_KICK_SHIFT)) & IRIS_MVPL_EXTDST5_SOFTWAREKICK_KICK_MASK) /*! @} */ /*! @name EXTDST5_STATUS - External Destination Unit current status */ /*! @{ */ #define IRIS_MVPL_EXTDST5_STATUS_CNT_ERR_STS_MASK (0x1U) #define IRIS_MVPL_EXTDST5_STATUS_CNT_ERR_STS_SHIFT (0U) /*! CNT_ERR_STS - Pixel count error */ #define IRIS_MVPL_EXTDST5_STATUS_CNT_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATUS_CNT_ERR_STS_SHIFT)) & IRIS_MVPL_EXTDST5_STATUS_CNT_ERR_STS_MASK) /*! @} */ /*! @name EXTDST5_CONTROLWORD - Value of last received control word */ /*! @{ */ #define IRIS_MVPL_EXTDST5_CONTROLWORD_CW_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST5_CONTROLWORD_CW_VAL_SHIFT (0U) /*! CW_VAL - Value of last received control word */ #define IRIS_MVPL_EXTDST5_CONTROLWORD_CW_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_CONTROLWORD_CW_VAL_SHIFT)) & IRIS_MVPL_EXTDST5_CONTROLWORD_CW_VAL_MASK) /*! @} */ /*! @name EXTDST5_CURPIXELCNT - pixel count of currently running frame */ /*! @{ */ #define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_XVAL_MASK (0xFFFFU) #define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_XVAL_SHIFT (0U) /*! C_XVAL - value of horizontal pixel counter, internal counter counting from max-1 to 0 */ #define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_CURPIXELCNT_C_XVAL_SHIFT)) & IRIS_MVPL_EXTDST5_CURPIXELCNT_C_XVAL_MASK) #define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_YVAL_MASK (0xFFFF0000U) #define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_YVAL_SHIFT (16U) /*! C_YVAL - value of vertical line counter, internal counter counting from max-1 to 0 */ #define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_CURPIXELCNT_C_YVAL_SHIFT)) & IRIS_MVPL_EXTDST5_CURPIXELCNT_C_YVAL_MASK) /*! @} */ /*! @name EXTDST5_LASTPIXELCNT - pixel count between last two control words */ /*! @{ */ #define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_XVAL_MASK (0xFFFFU) #define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_XVAL_SHIFT (0U) /*! L_XVAL - value of horizontal pixel counter */ #define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_XVAL_SHIFT)) & IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_XVAL_MASK) #define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_YVAL_MASK (0xFFFF0000U) #define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_YVAL_SHIFT (16U) /*! L_YVAL - value of vertical line counter */ #define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_YVAL_SHIFT)) & IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_YVAL_MASK) /*! @} */ /*! @name EXTDST5_PERFCOUNTER - Performance counter result */ /*! @{ */ #define IRIS_MVPL_EXTDST5_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU) #define IRIS_MVPL_EXTDST5_PERFCOUNTER_PerfResult_SHIFT (0U) /*! PerfResult - Returns the performance counter value. Returns number of cycles of the last frame * on the input. To calculate the performance divide the known number of pixels of the frame by * this number. For debug purposes only, read when stable only, otherwise read data might be * corrupted. */ #define IRIS_MVPL_EXTDST5_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_EXTDST5_PERFCOUNTER_PerfResult_MASK) /*! @} */ /*! @name FETCHWARP2_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP2_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHWARP2_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHWARP2_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name FETCHWARP2_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHWARP2_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP2_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP2_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name FETCHWARP2_STATICCONTROL - Common static control options. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_FETCHWARP2_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U) /*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded * from shadow at start of each frame. This update is then executed independently from other RWS * type fields. ShdEn must be enabled for this mode. */ #define IRIS_MVPL_FETCHWARP2_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHWARP2_STATICCONTROL_BaseAddressAutoUpdate_MASK) #define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdLdReqSticky_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdLdReqSticky_SHIFT (24U) /*! ShdLdReqSticky - Shadow load request flags for each layer (always load). See description of * register TriggerEnable for further information. */ #define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdLdReqSticky(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdLdReqSticky_SHIFT)) & IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdLdReqSticky_MASK) /*! @} */ /*! @name FETCHWARP2_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U) /*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of * 2. */ #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK) #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of * two may be specified as burst length. */ #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK) #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U) /*! LineMode - Fetch buffer cache control. * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_LineMode_MASK) /*! @} */ /*! @name FETCHWARP2_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP2_BASEADDRESS0_BaseAddress0_SHIFT (0U) /*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit * BaseAddress[0] has to be 0. */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS0_BaseAddress0_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U) /*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel * width of 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_Stride0_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U) /*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or * 32. Exception: FetchEco does not support 18 and 24. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U) /*! LineWidth0 - Width of the source buffer of the layer in pixels minus one. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineWidth0_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U) /*! LineCount0 - Number of lines of the source buffer of the layer minus one. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineCount0_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U) /*! ComponentBitsAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U) /*! ComponentBitsBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U) /*! ComponentBitsGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U) /*! ComponentBitsRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U) /*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This * is compliant to ITU 656 standard. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ITUFormat0_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U) /*! ComponentShiftAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U) /*! ComponentShiftBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U) /*! ComponentShiftGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U) /*! ComponentShiftRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK) /*! @} */ /*! @name FETCHWARP2_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerXOffset0_SHIFT (0U) /*! LayerXOffset0 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerXOffset0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerYOffset0_SHIFT (16U) /*! LayerYOffset0 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerYOffset0_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U) /*! ClipWindowXOffset0 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U) /*! ClipWindowYOffset0 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U) /*! ClipWindowWidth0 - Width. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U) /*! ClipWindowHeight0 - Height. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK) /*! @} */ /*! @name FETCHWARP2_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U) /*! ConstantAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantAlpha0_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U) /*! ConstantBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantBlue0_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U) /*! ConstantGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantGreen0_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U) /*! ConstantRed0 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantRed0_MASK) /*! @} */ /*! @name FETCHWARP2_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_TileMode0_MASK (0x30U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_TileMode0_SHIFT (4U) /*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) * takes precedence if a pixel becomes subject to both tiling and clipping. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_TileMode0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U) /*! AlphaSrcEnable0 - Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U) /*! AlphaConstEnable0 - Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaMaskEnable0_MASK (0x400U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT (10U) /*! AlphaMaskEnable0 - Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaMaskEnable0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U) /*! AlphaTransEnable0 - Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U) /*! RGBAlphaSrcEnable0 - Value 1 enables source alpha (stored together with color component in the * source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U) /*! RGBAlphaConstEnable0 - Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT (14U) /*! RGBAlphaMaskEnable0 - Value 1 enables mask alpha (read by another Fetch unit from a separate * alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be * enabled for this field to have effect. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U) /*! RGBAlphaTransEnable0 - Value 1 enables transparent alpha (0 or 1 depending on RGB matching * ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U) /*! PremulConstRGB0 - When enabled (value 1) the values given by ConstantRed/Green/Blue are used * instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no * effect then. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_PremulConstRGB0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U) /*! YUVConversionMode0 - Enables different kind of YUV to RGB conversions. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_YUVConversionMode0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U) /*! GammaRemoveEnable0 - Value 1 enables the stage to remove a gamma from RGB components. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_GammaRemoveEnable0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U) /*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip * window get the clip color, pixels inside the source or tiling color. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_ClipWindowEnable0_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U) /*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling * color is used only (TileMode TILE_PAD not allowed). */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_SourceBufferEnable0_MASK) /*! @} */ /*! @name FETCHWARP2_BASEADDRESS1 - Source buffer base address of layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS1_BaseAddress1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP2_BASEADDRESS1_BaseAddress1_SHIFT (0U) /*! BaseAddress1 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS1_BaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS1_BaseAddress1_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS1_BaseAddress1_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES1 - Source buffer attributes for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_Stride1_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT (0U) /*! Stride1 - See Stride0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_Stride1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_Stride1_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT (16U) /*! BitsPerPixel1 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERDIMENSION1 - Source buffer dimensions of layer 1, */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineWidth1_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT (0U) /*! LineWidth1 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineWidth1_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineCount1_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT (16U) /*! LineCount1 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineCount1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineCount1_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTBITS1 - Size of color components for RGB, YUV and index formats (layer 1). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK (0xFU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT (0U) /*! ComponentBitsAlpha1 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT (8U) /*! ComponentBitsBlue1 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT (16U) /*! ComponentBitsGreen1 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT (24U) /*! ComponentBitsRed1 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ITUFormat1_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ITUFormat1_SHIFT (31U) /*! ITUFormat1 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ITUFormat1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ITUFormat1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ITUFormat1_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTSHIFT1 - Bit position of color components for RGB, YUV and index formats (layer 1). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT (0U) /*! ComponentShiftAlpha1 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT (8U) /*! ComponentShiftBlue1 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT (16U) /*! ComponentShiftGreen1 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT (24U) /*! ComponentShiftRed1 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK) /*! @} */ /*! @name FETCHWARP2_LAYEROFFSET1 - Position of layer 1 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerXOffset1_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerXOffset1_SHIFT (0U) /*! LayerXOffset1 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerXOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerXOffset1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerYOffset1_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerYOffset1_SHIFT (16U) /*! LayerYOffset1 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerYOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerYOffset1_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWOFFSET1 - Clip window position for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT (0U) /*! ClipWindowXOffset1 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT (16U) /*! ClipWindowYOffset1 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS1 - Clip window size for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT (0U) /*! ClipWindowWidth1 - Width. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT (16U) /*! ClipWindowHeight1 - Height. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK) /*! @} */ /*! @name FETCHWARP2_CONSTANTCOLOR1 - Constant color for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantAlpha1_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantAlpha1_SHIFT (0U) /*! ConstantAlpha1 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantAlpha1_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantBlue1_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantBlue1_SHIFT (8U) /*! ConstantBlue1 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantBlue1_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantGreen1_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantGreen1_SHIFT (16U) /*! ConstantGreen1 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantGreen1_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantRed1_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantRed1_SHIFT (24U) /*! ConstantRed1 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantRed1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantRed1_MASK) /*! @} */ /*! @name FETCHWARP2_LAYERPROPERTY1 - Common properties of layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_TileMode1_MASK (0x30U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_TileMode1_SHIFT (4U) /*! TileMode1 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_TileMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_TileMode1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_TileMode1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaSrcEnable1_MASK (0x100U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT (8U) /*! AlphaSrcEnable1 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaSrcEnable1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaConstEnable1_MASK (0x200U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaConstEnable1_SHIFT (9U) /*! AlphaConstEnable1 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaConstEnable1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaMaskEnable1_MASK (0x400U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaMaskEnable1_SHIFT (10U) /*! AlphaMaskEnable1 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaMaskEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaMaskEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaMaskEnable1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaTransEnable1_MASK (0x800U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaTransEnable1_SHIFT (11U) /*! AlphaTransEnable1 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaTransEnable1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT (12U) /*! RGBAlphaSrcEnable1 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT (13U) /*! RGBAlphaConstEnable1 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaMaskEnable1_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaMaskEnable1_SHIFT (14U) /*! RGBAlphaMaskEnable1 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaMaskEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaMaskEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaMaskEnable1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT (15U) /*! RGBAlphaTransEnable1 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_PremulConstRGB1_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_PremulConstRGB1_SHIFT (16U) /*! PremulConstRGB1 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_PremulConstRGB1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_PremulConstRGB1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_PremulConstRGB1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_YUVConversionMode1_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_YUVConversionMode1_SHIFT (17U) /*! YUVConversionMode1 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_YUVConversionMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_YUVConversionMode1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_YUVConversionMode1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_GammaRemoveEnable1_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT (20U) /*! GammaRemoveEnable1 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_GammaRemoveEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_GammaRemoveEnable1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_ClipWindowEnable1_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_ClipWindowEnable1_SHIFT (30U) /*! ClipWindowEnable1 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_ClipWindowEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_ClipWindowEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_ClipWindowEnable1_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_SourceBufferEnable1_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_SourceBufferEnable1_SHIFT (31U) /*! SourceBufferEnable1 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_SourceBufferEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_SourceBufferEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_SourceBufferEnable1_MASK) /*! @} */ /*! @name FETCHWARP2_BASEADDRESS2 - Source buffer base address of layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS2_BaseAddress2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP2_BASEADDRESS2_BaseAddress2_SHIFT (0U) /*! BaseAddress2 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS2_BaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS2_BaseAddress2_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS2_BaseAddress2_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES2 - Source buffer attributes for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_Stride2_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT (0U) /*! Stride2 - See Stride0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_Stride2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_Stride2_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT (16U) /*! BitsPerPixel2 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERDIMENSION2 - Source buffer dimension of layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineWidth2_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT (0U) /*! LineWidth2 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineWidth2_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineCount2_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT (16U) /*! LineCount2 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineCount2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineCount2_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTBITS2 - Size of color components for RGB, YUV and index formats (layer 2). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK (0xFU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT (0U) /*! ComponentBitsAlpha2 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT (8U) /*! ComponentBitsBlue2 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT (16U) /*! ComponentBitsGreen2 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT (24U) /*! ComponentBitsRed2 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ITUFormat2_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ITUFormat2_SHIFT (31U) /*! ITUFormat2 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ITUFormat2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ITUFormat2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ITUFormat2_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTSHIFT2 - Bit position of color components for RGB, YUV and index formats (layer 2). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT (0U) /*! ComponentShiftAlpha2 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT (8U) /*! ComponentShiftBlue2 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT (16U) /*! ComponentShiftGreen2 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT (24U) /*! ComponentShiftRed2 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK) /*! @} */ /*! @name FETCHWARP2_LAYEROFFSET2 - Position of layer 2 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerXOffset2_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerXOffset2_SHIFT (0U) /*! LayerXOffset2 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerXOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerXOffset2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerYOffset2_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerYOffset2_SHIFT (16U) /*! LayerYOffset2 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerYOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerYOffset2_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWOFFSET2 - Clip window position for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT (0U) /*! ClipWindowXOffset2 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT (16U) /*! ClipWindowYOffset2 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS2 - Clip window size for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT (0U) /*! ClipWindowWidth2 - Width. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT (16U) /*! ClipWindowHeight2 - Height. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK) /*! @} */ /*! @name FETCHWARP2_CONSTANTCOLOR2 - Constant color for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantAlpha2_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantAlpha2_SHIFT (0U) /*! ConstantAlpha2 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantAlpha2_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantBlue2_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantBlue2_SHIFT (8U) /*! ConstantBlue2 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantBlue2_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantGreen2_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantGreen2_SHIFT (16U) /*! ConstantGreen2 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantGreen2_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantRed2_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantRed2_SHIFT (24U) /*! ConstantRed2 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantRed2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantRed2_MASK) /*! @} */ /*! @name FETCHWARP2_LAYERPROPERTY2 - Common properties of layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_TileMode2_MASK (0x30U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_TileMode2_SHIFT (4U) /*! TileMode2 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_TileMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_TileMode2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_TileMode2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaSrcEnable2_MASK (0x100U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT (8U) /*! AlphaSrcEnable2 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaSrcEnable2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaConstEnable2_MASK (0x200U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaConstEnable2_SHIFT (9U) /*! AlphaConstEnable2 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaConstEnable2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaMaskEnable2_MASK (0x400U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaMaskEnable2_SHIFT (10U) /*! AlphaMaskEnable2 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaMaskEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaMaskEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaMaskEnable2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaTransEnable2_MASK (0x800U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaTransEnable2_SHIFT (11U) /*! AlphaTransEnable2 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaTransEnable2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT (12U) /*! RGBAlphaSrcEnable2 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT (13U) /*! RGBAlphaConstEnable2 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaMaskEnable2_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaMaskEnable2_SHIFT (14U) /*! RGBAlphaMaskEnable2 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaMaskEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaMaskEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaMaskEnable2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT (15U) /*! RGBAlphaTransEnable2 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_PremulConstRGB2_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_PremulConstRGB2_SHIFT (16U) /*! PremulConstRGB2 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_PremulConstRGB2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_PremulConstRGB2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_PremulConstRGB2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_YUVConversionMode2_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_YUVConversionMode2_SHIFT (17U) /*! YUVConversionMode2 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_YUVConversionMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_YUVConversionMode2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_YUVConversionMode2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_GammaRemoveEnable2_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT (20U) /*! GammaRemoveEnable2 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_GammaRemoveEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_GammaRemoveEnable2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_ClipWindowEnable2_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_ClipWindowEnable2_SHIFT (30U) /*! ClipWindowEnable2 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_ClipWindowEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_ClipWindowEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_ClipWindowEnable2_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_SourceBufferEnable2_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_SourceBufferEnable2_SHIFT (31U) /*! SourceBufferEnable2 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_SourceBufferEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_SourceBufferEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_SourceBufferEnable2_MASK) /*! @} */ /*! @name FETCHWARP2_BASEADDRESS3 - Source buffer base address of layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS3_BaseAddress3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP2_BASEADDRESS3_BaseAddress3_SHIFT (0U) /*! BaseAddress3 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS3_BaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS3_BaseAddress3_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS3_BaseAddress3_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES3 - Source buffer attributes for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_Stride3_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT (0U) /*! Stride3 - See Stride0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_Stride3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_Stride3_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT (16U) /*! BitsPerPixel3 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERDIMENSION3 - Source buffer dimension of layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineWidth3_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT (0U) /*! LineWidth3 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineWidth3_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineCount3_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT (16U) /*! LineCount3 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineCount3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineCount3_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTBITS3 - Size of color components for RGB, YUV and index formats (layer 3). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK (0xFU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT (0U) /*! ComponentBitsAlpha3 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT (8U) /*! ComponentBitsBlue3 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT (16U) /*! ComponentBitsGreen3 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT (24U) /*! ComponentBitsRed3 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ITUFormat3_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ITUFormat3_SHIFT (31U) /*! ITUFormat3 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ITUFormat3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ITUFormat3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ITUFormat3_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTSHIFT3 - Bit position of color components for RGB, YUV and index formats (layer 3). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT (0U) /*! ComponentShiftAlpha3 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT (8U) /*! ComponentShiftBlue3 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT (16U) /*! ComponentShiftGreen3 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT (24U) /*! ComponentShiftRed3 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK) /*! @} */ /*! @name FETCHWARP2_LAYEROFFSET3 - Position of layer 3 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerXOffset3_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerXOffset3_SHIFT (0U) /*! LayerXOffset3 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerXOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerXOffset3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerYOffset3_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerYOffset3_SHIFT (16U) /*! LayerYOffset3 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerYOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerYOffset3_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWOFFSET3 - Clip window position for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT (0U) /*! ClipWindowXOffset3 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT (16U) /*! ClipWindowYOffset3 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS3 - Clip window size for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT (0U) /*! ClipWindowWidth3 - Width. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT (16U) /*! ClipWindowHeight3 - Height. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK) /*! @} */ /*! @name FETCHWARP2_CONSTANTCOLOR3 - Constant color for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantAlpha3_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantAlpha3_SHIFT (0U) /*! ConstantAlpha3 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantAlpha3_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantBlue3_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantBlue3_SHIFT (8U) /*! ConstantBlue3 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantBlue3_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantGreen3_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantGreen3_SHIFT (16U) /*! ConstantGreen3 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantGreen3_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantRed3_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantRed3_SHIFT (24U) /*! ConstantRed3 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantRed3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantRed3_MASK) /*! @} */ /*! @name FETCHWARP2_LAYERPROPERTY3 - Common properties of layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_TileMode3_MASK (0x30U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_TileMode3_SHIFT (4U) /*! TileMode3 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_TileMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_TileMode3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_TileMode3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaSrcEnable3_MASK (0x100U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT (8U) /*! AlphaSrcEnable3 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaSrcEnable3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaConstEnable3_MASK (0x200U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaConstEnable3_SHIFT (9U) /*! AlphaConstEnable3 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaConstEnable3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaMaskEnable3_MASK (0x400U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaMaskEnable3_SHIFT (10U) /*! AlphaMaskEnable3 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaMaskEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaMaskEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaMaskEnable3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaTransEnable3_MASK (0x800U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaTransEnable3_SHIFT (11U) /*! AlphaTransEnable3 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaTransEnable3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT (12U) /*! RGBAlphaSrcEnable3 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT (13U) /*! RGBAlphaConstEnable3 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaMaskEnable3_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaMaskEnable3_SHIFT (14U) /*! RGBAlphaMaskEnable3 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaMaskEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaMaskEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaMaskEnable3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT (15U) /*! RGBAlphaTransEnable3 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_PremulConstRGB3_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_PremulConstRGB3_SHIFT (16U) /*! PremulConstRGB3 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_PremulConstRGB3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_PremulConstRGB3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_PremulConstRGB3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_YUVConversionMode3_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_YUVConversionMode3_SHIFT (17U) /*! YUVConversionMode3 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_YUVConversionMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_YUVConversionMode3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_YUVConversionMode3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_GammaRemoveEnable3_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT (20U) /*! GammaRemoveEnable3 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_GammaRemoveEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_GammaRemoveEnable3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_ClipWindowEnable3_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_ClipWindowEnable3_SHIFT (30U) /*! ClipWindowEnable3 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_ClipWindowEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_ClipWindowEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_ClipWindowEnable3_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_SourceBufferEnable3_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_SourceBufferEnable3_SHIFT (31U) /*! SourceBufferEnable3 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_SourceBufferEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_SourceBufferEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_SourceBufferEnable3_MASK) /*! @} */ /*! @name FETCHWARP2_BASEADDRESS4 - Source buffer base address of layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS4_BaseAddress4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP2_BASEADDRESS4_BaseAddress4_SHIFT (0U) /*! BaseAddress4 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS4_BaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS4_BaseAddress4_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS4_BaseAddress4_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES4 - Source buffer attributes for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_Stride4_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT (0U) /*! Stride4 - See Stride0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_Stride4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_Stride4_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT (16U) /*! BitsPerPixel4 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERDIMENSION4 - Source buffer dimension of layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineWidth4_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT (0U) /*! LineWidth4 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineWidth4_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineCount4_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT (16U) /*! LineCount4 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineCount4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineCount4_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTBITS4 - Size of color components for RGB, YUV and index formats (layer 4). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK (0xFU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT (0U) /*! ComponentBitsAlpha4 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT (8U) /*! ComponentBitsBlue4 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT (16U) /*! ComponentBitsGreen4 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT (24U) /*! ComponentBitsRed4 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ITUFormat4_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ITUFormat4_SHIFT (31U) /*! ITUFormat4 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ITUFormat4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ITUFormat4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ITUFormat4_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTSHIFT4 - Bit position of color components for RGB, YUV and index formats (layer 4). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT (0U) /*! ComponentShiftAlpha4 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT (8U) /*! ComponentShiftBlue4 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT (16U) /*! ComponentShiftGreen4 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT (24U) /*! ComponentShiftRed4 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK) /*! @} */ /*! @name FETCHWARP2_LAYEROFFSET4 - Position of layer 4 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerXOffset4_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerXOffset4_SHIFT (0U) /*! LayerXOffset4 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerXOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerXOffset4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerYOffset4_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerYOffset4_SHIFT (16U) /*! LayerYOffset4 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerYOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerYOffset4_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWOFFSET4 - Clip window position for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT (0U) /*! ClipWindowXOffset4 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT (16U) /*! ClipWindowYOffset4 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS4 - Clip window size for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT (0U) /*! ClipWindowWidth4 - Width. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT (16U) /*! ClipWindowHeight4 - Height. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK) /*! @} */ /*! @name FETCHWARP2_CONSTANTCOLOR4 - Constant color for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantAlpha4_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantAlpha4_SHIFT (0U) /*! ConstantAlpha4 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantAlpha4_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantBlue4_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantBlue4_SHIFT (8U) /*! ConstantBlue4 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantBlue4_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantGreen4_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantGreen4_SHIFT (16U) /*! ConstantGreen4 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantGreen4_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantRed4_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantRed4_SHIFT (24U) /*! ConstantRed4 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantRed4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantRed4_MASK) /*! @} */ /*! @name FETCHWARP2_LAYERPROPERTY4 - Common properties of layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_TileMode4_MASK (0x30U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_TileMode4_SHIFT (4U) /*! TileMode4 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_TileMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_TileMode4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_TileMode4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaSrcEnable4_MASK (0x100U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT (8U) /*! AlphaSrcEnable4 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaSrcEnable4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaConstEnable4_MASK (0x200U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaConstEnable4_SHIFT (9U) /*! AlphaConstEnable4 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaConstEnable4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaMaskEnable4_MASK (0x400U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaMaskEnable4_SHIFT (10U) /*! AlphaMaskEnable4 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaMaskEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaMaskEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaMaskEnable4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaTransEnable4_MASK (0x800U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaTransEnable4_SHIFT (11U) /*! AlphaTransEnable4 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaTransEnable4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT (12U) /*! RGBAlphaSrcEnable4 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT (13U) /*! RGBAlphaConstEnable4 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaMaskEnable4_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaMaskEnable4_SHIFT (14U) /*! RGBAlphaMaskEnable4 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaMaskEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaMaskEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaMaskEnable4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT (15U) /*! RGBAlphaTransEnable4 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_PremulConstRGB4_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_PremulConstRGB4_SHIFT (16U) /*! PremulConstRGB4 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_PremulConstRGB4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_PremulConstRGB4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_PremulConstRGB4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_YUVConversionMode4_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_YUVConversionMode4_SHIFT (17U) /*! YUVConversionMode4 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_YUVConversionMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_YUVConversionMode4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_YUVConversionMode4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_GammaRemoveEnable4_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT (20U) /*! GammaRemoveEnable4 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_GammaRemoveEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_GammaRemoveEnable4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_ClipWindowEnable4_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_ClipWindowEnable4_SHIFT (30U) /*! ClipWindowEnable4 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_ClipWindowEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_ClipWindowEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_ClipWindowEnable4_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_SourceBufferEnable4_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_SourceBufferEnable4_SHIFT (31U) /*! SourceBufferEnable4 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_SourceBufferEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_SourceBufferEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_SourceBufferEnable4_MASK) /*! @} */ /*! @name FETCHWARP2_BASEADDRESS5 - Source buffer base address of layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS5_BaseAddress5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP2_BASEADDRESS5_BaseAddress5_SHIFT (0U) /*! BaseAddress5 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS5_BaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS5_BaseAddress5_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS5_BaseAddress5_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES5 - Source buffer attributes for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_Stride5_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT (0U) /*! Stride5 - See Stride0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_Stride5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_Stride5_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT (16U) /*! BitsPerPixel5 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERDIMENSION5 - Source buffer dimension of layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineWidth5_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT (0U) /*! LineWidth5 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineWidth5_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineCount5_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT (16U) /*! LineCount5 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineCount5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineCount5_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTBITS5 - Size of color components for RGB, YUV and index formats (layer 5). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK (0xFU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT (0U) /*! ComponentBitsAlpha5 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT (8U) /*! ComponentBitsBlue5 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT (16U) /*! ComponentBitsGreen5 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT (24U) /*! ComponentBitsRed5 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ITUFormat5_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ITUFormat5_SHIFT (31U) /*! ITUFormat5 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ITUFormat5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ITUFormat5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ITUFormat5_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTSHIFT5 - Bit position of color components for RGB, YUV and index formats (layer 5). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT (0U) /*! ComponentShiftAlpha5 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT (8U) /*! ComponentShiftBlue5 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT (16U) /*! ComponentShiftGreen5 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT (24U) /*! ComponentShiftRed5 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK) /*! @} */ /*! @name FETCHWARP2_LAYEROFFSET5 - Position of layer 5 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerXOffset5_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerXOffset5_SHIFT (0U) /*! LayerXOffset5 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerXOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerXOffset5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerYOffset5_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerYOffset5_SHIFT (16U) /*! LayerYOffset5 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerYOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerYOffset5_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWOFFSET5 - Clip window position for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT (0U) /*! ClipWindowXOffset5 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT (16U) /*! ClipWindowYOffset5 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS5 - Clip window size for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT (0U) /*! ClipWindowWidth5 - Width. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT (16U) /*! ClipWindowHeight5 - Height. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK) /*! @} */ /*! @name FETCHWARP2_CONSTANTCOLOR5 - Constant color for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantAlpha5_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantAlpha5_SHIFT (0U) /*! ConstantAlpha5 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantAlpha5_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantBlue5_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantBlue5_SHIFT (8U) /*! ConstantBlue5 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantBlue5_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantGreen5_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantGreen5_SHIFT (16U) /*! ConstantGreen5 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantGreen5_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantRed5_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantRed5_SHIFT (24U) /*! ConstantRed5 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantRed5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantRed5_MASK) /*! @} */ /*! @name FETCHWARP2_LAYERPROPERTY5 - Common properties of layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_TileMode5_MASK (0x30U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_TileMode5_SHIFT (4U) /*! TileMode5 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_TileMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_TileMode5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_TileMode5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaSrcEnable5_MASK (0x100U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT (8U) /*! AlphaSrcEnable5 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaSrcEnable5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaConstEnable5_MASK (0x200U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaConstEnable5_SHIFT (9U) /*! AlphaConstEnable5 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaConstEnable5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaMaskEnable5_MASK (0x400U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaMaskEnable5_SHIFT (10U) /*! AlphaMaskEnable5 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaMaskEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaMaskEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaMaskEnable5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaTransEnable5_MASK (0x800U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaTransEnable5_SHIFT (11U) /*! AlphaTransEnable5 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaTransEnable5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT (12U) /*! RGBAlphaSrcEnable5 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT (13U) /*! RGBAlphaConstEnable5 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaMaskEnable5_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaMaskEnable5_SHIFT (14U) /*! RGBAlphaMaskEnable5 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaMaskEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaMaskEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaMaskEnable5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT (15U) /*! RGBAlphaTransEnable5 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_PremulConstRGB5_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_PremulConstRGB5_SHIFT (16U) /*! PremulConstRGB5 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_PremulConstRGB5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_PremulConstRGB5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_PremulConstRGB5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_YUVConversionMode5_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_YUVConversionMode5_SHIFT (17U) /*! YUVConversionMode5 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_YUVConversionMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_YUVConversionMode5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_YUVConversionMode5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_GammaRemoveEnable5_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT (20U) /*! GammaRemoveEnable5 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_GammaRemoveEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_GammaRemoveEnable5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_ClipWindowEnable5_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_ClipWindowEnable5_SHIFT (30U) /*! ClipWindowEnable5 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_ClipWindowEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_ClipWindowEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_ClipWindowEnable5_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_SourceBufferEnable5_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_SourceBufferEnable5_SHIFT (31U) /*! SourceBufferEnable5 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_SourceBufferEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_SourceBufferEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_SourceBufferEnable5_MASK) /*! @} */ /*! @name FETCHWARP2_BASEADDRESS6 - Source buffer base address of layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS6_BaseAddress6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP2_BASEADDRESS6_BaseAddress6_SHIFT (0U) /*! BaseAddress6 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS6_BaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS6_BaseAddress6_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS6_BaseAddress6_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES6 - Source buffer attributes for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_Stride6_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT (0U) /*! Stride6 - See Stride0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_Stride6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_Stride6_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT (16U) /*! BitsPerPixel6 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERDIMENSION6 - Source buffer dimension of layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineWidth6_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT (0U) /*! LineWidth6 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineWidth6_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineCount6_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT (16U) /*! LineCount6 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineCount6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineCount6_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTBITS6 - Size of color components for RGB, YUV and index formats (layer 6). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK (0xFU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT (0U) /*! ComponentBitsAlpha6 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT (8U) /*! ComponentBitsBlue6 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT (16U) /*! ComponentBitsGreen6 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT (24U) /*! ComponentBitsRed6 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ITUFormat6_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ITUFormat6_SHIFT (31U) /*! ITUFormat6 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ITUFormat6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ITUFormat6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ITUFormat6_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTSHIFT6 - Bit position of color components for RGB, YUV and index formats (layer 6). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT (0U) /*! ComponentShiftAlpha6 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT (8U) /*! ComponentShiftBlue6 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT (16U) /*! ComponentShiftGreen6 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT (24U) /*! ComponentShiftRed6 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK) /*! @} */ /*! @name FETCHWARP2_LAYEROFFSET6 - Position of layer 1 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerXOffset6_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerXOffset6_SHIFT (0U) /*! LayerXOffset6 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerXOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerXOffset6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerYOffset6_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerYOffset6_SHIFT (16U) /*! LayerYOffset6 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerYOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerYOffset6_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWOFFSET6 - Clip window position for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT (0U) /*! ClipWindowXOffset6 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT (16U) /*! ClipWindowYOffset6 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS6 - Clip window size for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT (0U) /*! ClipWindowWidth6 - Width. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT (16U) /*! ClipWindowHeight6 - Height. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK) /*! @} */ /*! @name FETCHWARP2_CONSTANTCOLOR6 - Constant color for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantAlpha6_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantAlpha6_SHIFT (0U) /*! ConstantAlpha6 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantAlpha6_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantBlue6_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantBlue6_SHIFT (8U) /*! ConstantBlue6 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantBlue6_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantGreen6_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantGreen6_SHIFT (16U) /*! ConstantGreen6 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantGreen6_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantRed6_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantRed6_SHIFT (24U) /*! ConstantRed6 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantRed6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantRed6_MASK) /*! @} */ /*! @name FETCHWARP2_LAYERPROPERTY6 - Common properties of layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_TileMode6_MASK (0x30U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_TileMode6_SHIFT (4U) /*! TileMode6 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_TileMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_TileMode6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_TileMode6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaSrcEnable6_MASK (0x100U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT (8U) /*! AlphaSrcEnable6 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaSrcEnable6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaConstEnable6_MASK (0x200U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaConstEnable6_SHIFT (9U) /*! AlphaConstEnable6 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaConstEnable6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaMaskEnable6_MASK (0x400U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaMaskEnable6_SHIFT (10U) /*! AlphaMaskEnable6 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaMaskEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaMaskEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaMaskEnable6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaTransEnable6_MASK (0x800U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaTransEnable6_SHIFT (11U) /*! AlphaTransEnable6 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaTransEnable6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT (12U) /*! RGBAlphaSrcEnable6 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT (13U) /*! RGBAlphaConstEnable6 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaMaskEnable6_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaMaskEnable6_SHIFT (14U) /*! RGBAlphaMaskEnable6 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaMaskEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaMaskEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaMaskEnable6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT (15U) /*! RGBAlphaTransEnable6 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_PremulConstRGB6_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_PremulConstRGB6_SHIFT (16U) /*! PremulConstRGB6 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_PremulConstRGB6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_PremulConstRGB6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_PremulConstRGB6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_YUVConversionMode6_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_YUVConversionMode6_SHIFT (17U) /*! YUVConversionMode6 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_YUVConversionMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_YUVConversionMode6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_YUVConversionMode6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_GammaRemoveEnable6_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT (20U) /*! GammaRemoveEnable6 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_GammaRemoveEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_GammaRemoveEnable6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_ClipWindowEnable6_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_ClipWindowEnable6_SHIFT (30U) /*! ClipWindowEnable6 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_ClipWindowEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_ClipWindowEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_ClipWindowEnable6_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_SourceBufferEnable6_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_SourceBufferEnable6_SHIFT (31U) /*! SourceBufferEnable6 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_SourceBufferEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_SourceBufferEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_SourceBufferEnable6_MASK) /*! @} */ /*! @name FETCHWARP2_BASEADDRESS7 - Source buffer base address of layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS7_BaseAddress7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHWARP2_BASEADDRESS7_BaseAddress7_SHIFT (0U) /*! BaseAddress7 - See BaseAddress0. */ #define IRIS_MVPL_FETCHWARP2_BASEADDRESS7_BaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS7_BaseAddress7_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS7_BaseAddress7_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES7 - Source buffer stride for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_Stride7_MASK (0xFFFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT (0U) /*! Stride7 - See Stride0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_Stride7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_Stride7_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK (0x3F0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT (16U) /*! BitsPerPixel7 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK) /*! @} */ /*! @name FETCHWARP2_SOURCEBUFFERDIMENSION7 - Source buffer dimension of layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineWidth7_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT (0U) /*! LineWidth7 - See LineWidth0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineWidth7_MASK) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineCount7_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT (16U) /*! LineCount7 - See LineCount0. */ #define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineCount7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineCount7_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTBITS7 - Size of color components for RGB, YUV and index formats (layer 7). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK (0xFU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT (0U) /*! ComponentBitsAlpha7 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT (8U) /*! ComponentBitsBlue7 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK (0xF0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT (16U) /*! ComponentBitsGreen7 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK (0xF000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT (24U) /*! ComponentBitsRed7 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ITUFormat7_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ITUFormat7_SHIFT (31U) /*! ITUFormat7 - See ITUFormat0. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ITUFormat7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ITUFormat7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ITUFormat7_MASK) /*! @} */ /*! @name FETCHWARP2_COLORCOMPONENTSHIFT7 - Bit position of color components for RGB, YUV and index formats (layer 7). */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK (0x1FU) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT (0U) /*! ComponentShiftAlpha7 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT (8U) /*! ComponentShiftBlue7 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK (0x1F0000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT (16U) /*! ComponentShiftGreen7 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK (0x1F000000U) #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT (24U) /*! ComponentShiftRed7 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK) /*! @} */ /*! @name FETCHWARP2_LAYEROFFSET7 - Position of layer 7 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerXOffset7_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerXOffset7_SHIFT (0U) /*! LayerXOffset7 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerXOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerXOffset7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerYOffset7_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerYOffset7_SHIFT (16U) /*! LayerYOffset7 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerYOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerYOffset7_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWOFFSET7 - Clip window position for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK (0x7FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT (0U) /*! ClipWindowXOffset7 - Horizontal position (X). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT (16U) /*! ClipWindowYOffset7 - Vertical position (Y). */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK) /*! @} */ /*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS7 - Clip window size for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT (0U) /*! ClipWindowWidth7 - Width. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT (16U) /*! ClipWindowHeight7 - Height. */ #define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK) /*! @} */ /*! @name FETCHWARP2_CONSTANTCOLOR7 - Constant color for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantAlpha7_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantAlpha7_SHIFT (0U) /*! ConstantAlpha7 - Alpha. */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantAlpha7_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantBlue7_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantBlue7_SHIFT (8U) /*! ConstantBlue7 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantBlue7_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantGreen7_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantGreen7_SHIFT (16U) /*! ConstantGreen7 - Green and U (chroma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantGreen7_MASK) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantRed7_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantRed7_SHIFT (24U) /*! ConstantRed7 - Red and Y (luma). */ #define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantRed7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantRed7_MASK) /*! @} */ /*! @name FETCHWARP2_LAYERPROPERTY7 - Common properties of layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_TileMode7_MASK (0x30U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_TileMode7_SHIFT (4U) /*! TileMode7 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_TileMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_TileMode7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_TileMode7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaSrcEnable7_MASK (0x100U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT (8U) /*! AlphaSrcEnable7 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaSrcEnable7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaConstEnable7_MASK (0x200U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaConstEnable7_SHIFT (9U) /*! AlphaConstEnable7 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaConstEnable7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaMaskEnable7_MASK (0x400U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaMaskEnable7_SHIFT (10U) /*! AlphaMaskEnable7 - See AlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaMaskEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaMaskEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaMaskEnable7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaTransEnable7_MASK (0x800U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaTransEnable7_SHIFT (11U) /*! AlphaTransEnable7 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaTransEnable7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT (12U) /*! RGBAlphaSrcEnable7 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK (0x2000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT (13U) /*! RGBAlphaConstEnable7 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaMaskEnable7_MASK (0x4000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaMaskEnable7_SHIFT (14U) /*! RGBAlphaMaskEnable7 - See RGBAlphaMaskSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaMaskEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaMaskEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaMaskEnable7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK (0x8000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT (15U) /*! RGBAlphaTransEnable7 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_PremulConstRGB7_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_PremulConstRGB7_SHIFT (16U) /*! PremulConstRGB7 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_PremulConstRGB7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_PremulConstRGB7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_PremulConstRGB7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_YUVConversionMode7_MASK (0x60000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_YUVConversionMode7_SHIFT (17U) /*! YUVConversionMode7 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_YUVConversionMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_YUVConversionMode7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_YUVConversionMode7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_GammaRemoveEnable7_MASK (0x100000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT (20U) /*! GammaRemoveEnable7 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_GammaRemoveEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_GammaRemoveEnable7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_ClipWindowEnable7_MASK (0x40000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_ClipWindowEnable7_SHIFT (30U) /*! ClipWindowEnable7 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_ClipWindowEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_ClipWindowEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_ClipWindowEnable7_MASK) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_SourceBufferEnable7_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_SourceBufferEnable7_SHIFT (31U) /*! SourceBufferEnable7 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_SourceBufferEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_SourceBufferEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_SourceBufferEnable7_MASK) /*! @} */ /*! @name FETCHWARP2_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width minus one. */ #define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height minus one. */ #define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). If enabled, InputSelect must be set to INACTIVE. */ #define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name FETCHWARP2_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartX_MASK (0x3FU) #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartX_SHIFT (0U) /*! StartX - X coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartX_MASK) #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartY_MASK (0xFC0U) #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartY_SHIFT (6U) /*! StartY - Y coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartY_MASK) #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaX_MASK (0x3F000U) #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaX_SHIFT (12U) /*! DeltaX - Increment of X coordinate for horizontal step in destination frame. */ #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaX_MASK) #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U) #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaY_SHIFT (18U) /*! DeltaY - Increment of Y coordinate for vertical step in destination frame. */ #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaY_MASK) #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U) #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_SwapDirection_SHIFT (24U) /*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied * for horizontal and DeltaX for vertical step on destination frame. */ #define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_SwapDirection_MASK) /*! @} */ /*! @name FETCHWARP2_WARPCONTROL - Warping control options. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpBitsPerPixel_MASK (0x3FU) #define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpBitsPerPixel_SHIFT (0U) /*! WarpBitsPerPixel - Number of bits per pixel in the coordinate layer, which is read by another Fetch unit. Has to be 1, 2, 4, 8, 16 or 32. */ #define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpBitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpBitsPerPixel_SHIFT)) & IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpBitsPerPixel_MASK) #define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpCoordinateMode_MASK (0x300U) #define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpCoordinateMode_SHIFT (8U) /*! WarpCoordinateMode - Content of pixel data in the coordinate layer. * 0b00..x and y (sample points). * 0b01..dx and dy (vectors between adjacent sample points). * 0b10..ddx and ddy (deltas between adjacent vectors). */ #define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpCoordinateMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpCoordinateMode_SHIFT)) & IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpCoordinateMode_MASK) #define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpSymmetricOffset_MASK (0x1000U) #define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpSymmetricOffset_SHIFT (12U) /*! WarpSymmetricOffset - Value 1 enables symmetric range for negative and positive coordinate * values by adding an offset of +0.03125 internally to all coordinate input values. Recommended for * small coordinate formats in DD_PNT mode. */ #define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpSymmetricOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpSymmetricOffset_SHIFT)) & IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpSymmetricOffset_MASK) /*! @} */ /*! @name FETCHWARP2_ARBSTARTX - Start value X for arbitrary warping. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_ARBSTARTX_ArbStartX_MASK (0x1FFFFFU) #define IRIS_MVPL_FETCHWARP2_ARBSTARTX_ArbStartX_SHIFT (0U) /*! ArbStartX - Start point for sample-point interpolation (X coordinate). Given in signed 16.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP2_ARBSTARTX_ArbStartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBSTARTX_ArbStartX_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBSTARTX_ArbStartX_MASK) /*! @} */ /*! @name FETCHWARP2_ARBSTARTY - Start value Y for arbitrary warping. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_ARBSTARTY_ArbStartY_MASK (0x1FFFFFU) #define IRIS_MVPL_FETCHWARP2_ARBSTARTY_ArbStartY_SHIFT (0U) /*! ArbStartY - Start point for sample-point interpolation (Y coordinate). Given in signed 16.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP2_ARBSTARTY_ArbStartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBSTARTY_ArbStartY_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBSTARTY_ArbStartY_MASK) /*! @} */ /*! @name FETCHWARP2_ARBDELTA - Start values for delta incrementation of arbitrary warping. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXX_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXX_SHIFT (0U) /*! ArbDeltaXX - X coordinate of vector between first and second sample point. Given in signed 3.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXX_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXX_MASK) #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXY_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXY_SHIFT (8U) /*! ArbDeltaXY - Y coordinate of vector between first and second sample point. Given in signed 3.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXY_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXY_MASK) #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYX_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYX_SHIFT (16U) /*! ArbDeltaYX - X coordinate of vector between start and first sample point. Given in signed 3.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYX_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYX_MASK) #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYY_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYY_SHIFT (24U) /*! ArbDeltaYY - Y coordinate of vector between start and first sample point. Given in signed 3.5 fix-point notation. */ #define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYY_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYY_MASK) /*! @} */ /*! @name FETCHWARP2_FIRPOSITIONS - FIR sequence control register. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR0Position_MASK (0xFU) #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR0Position_SHIFT (0U) /*! FIR0Position - Position of first pixel. */ #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR0Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR0Position_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR0Position_MASK) #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR1Position_MASK (0xF0U) #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR1Position_SHIFT (4U) /*! FIR1Position - Position of second pixel. */ #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR1Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR1Position_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR1Position_MASK) #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR2Position_MASK (0xF00U) #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR2Position_SHIFT (8U) /*! FIR2Position - Position of third pixel. */ #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR2Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR2Position_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR2Position_MASK) #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR3Position_MASK (0xF000U) #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR3Position_SHIFT (12U) /*! FIR3Position - Position of fourth pixel. */ #define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR3Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR3Position_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR3Position_MASK) /*! @} */ /*! @name FETCHWARP2_FIRCOEFFICIENTS - FIR coefficients register. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR0Coefficient_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR0Coefficient_SHIFT (0U) /*! FIR0Coefficient - First coefficient. */ #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR0Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR0Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR0Coefficient_MASK) #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR1Coefficient_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR1Coefficient_SHIFT (8U) /*! FIR1Coefficient - Second coefficient. */ #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR1Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR1Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR1Coefficient_MASK) #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR2Coefficient_MASK (0xFF0000U) #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR2Coefficient_SHIFT (16U) /*! FIR2Coefficient - Third coefficient. */ #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR2Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR2Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR2Coefficient_MASK) #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR3Coefficient_MASK (0xFF000000U) #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR3Coefficient_SHIFT (24U) /*! FIR3Coefficient - Fourth coefficient. */ #define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR3Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR3Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR3Coefficient_MASK) /*! @} */ /*! @name FETCHWARP2_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CONTROL_RasterMode_MASK (0x7U) #define IRIS_MVPL_FETCHWARP2_CONTROL_RasterMode_SHIFT (0U) /*! RasterMode - Selects a method how to generate source buffer sample points. * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot/RotL only] Arbitrary warping (filter is active). Coordinates are read from frame * input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ #define IRIS_MVPL_FETCHWARP2_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_RasterMode_MASK) #define IRIS_MVPL_FETCHWARP2_CONTROL_InputSelect_MASK (0x18U) #define IRIS_MVPL_FETCHWARP2_CONTROL_InputSelect_SHIFT (3U) /*! InputSelect - Selects function for the frame input port. * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define IRIS_MVPL_FETCHWARP2_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_InputSelect_MASK) #define IRIS_MVPL_FETCHWARP2_CONTROL_RawPixel_MASK (0x80U) #define IRIS_MVPL_FETCHWARP2_CONTROL_RawPixel_SHIFT (7U) /*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced * for all layers by fixed values that allow passing the pixel data read from memory unchanged * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color * are deactived. Skip and Tile pixels are not affected by this setting. */ #define IRIS_MVPL_FETCHWARP2_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_RawPixel_MASK) #define IRIS_MVPL_FETCHWARP2_CONTROL_ClipColor_MASK (0x10000U) #define IRIS_MVPL_FETCHWARP2_CONTROL_ClipColor_SHIFT (16U) /*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer. * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define IRIS_MVPL_FETCHWARP2_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_ClipColor_MASK) #define IRIS_MVPL_FETCHWARP2_CONTROL_ClipLayer_MASK (0xE0000U) #define IRIS_MVPL_FETCHWARP2_CONTROL_ClipLayer_SHIFT (17U) /*! ClipLayer - Index of the layer which is used to fill the clipping area of the frame layout when * ClipColor is set to LAYER. The selected layer must be enabled (LayerEnable). */ #define IRIS_MVPL_FETCHWARP2_CONTROL_ClipLayer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_ClipLayer_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_ClipLayer_MASK) #define IRIS_MVPL_FETCHWARP2_CONTROL_FilterMode_MASK (0x700000U) #define IRIS_MVPL_FETCHWARP2_CONTROL_FilterMode_SHIFT (20U) /*! FilterMode - Use this to select between nearest and bilinear filtering. Only has an effect if * rastermode == ARBITRARY or rastermode == PERSPECTIVE or rastermode == AFFINE. * 0b000..Chooses pixel closest to sample point * 0b001..Calculates result from 4 pixels closest to sample point * 0b010..FIR mode with 2 programmable pixel positions and coefficients * 0b011..FIR mode with 4 programmable pixel positions and coefficients * 0b100..Calculates result from 2 pixels closest to the sample point and on the same line */ #define IRIS_MVPL_FETCHWARP2_CONTROL_FilterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_FilterMode_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_FilterMode_MASK) /*! @} */ /*! @name FETCHWARP2_TRIGGERENABLE - Shadow load enable flags for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_TRIGGERENABLE_ShdLdReq_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_TRIGGERENABLE_ShdLdReq_SHIFT (0U) /*! ShdLdReq - Shadow load request flags for each layer (one time load). */ #define IRIS_MVPL_FETCHWARP2_TRIGGERENABLE_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_TRIGGERENABLE_ShdLdReq_SHIFT)) & IRIS_MVPL_FETCHWARP2_TRIGGERENABLE_ShdLdReq_MASK) /*! @} */ /*! @name FETCHWARP2_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FETCHWARP2_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_FETCHWARP2_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name FETCHWARP2_START - Frame start trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_START_Start_MASK (0x1U) #define IRIS_MVPL_FETCHWARP2_START_Start_SHIFT (0U) /*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only). */ #define IRIS_MVPL_FETCHWARP2_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_START_Start_SHIFT)) & IRIS_MVPL_FETCHWARP2_START_Start_MASK) /*! @} */ /*! @name FETCHWARP2_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_FETCHTYPE_FetchType_MASK (0xFU) #define IRIS_MVPL_FETCHWARP2_FETCHTYPE_FetchType_SHIFT (0U) /*! FetchType - This field can be used to determine what kind of fetch unit this is. * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. */ #define IRIS_MVPL_FETCHWARP2_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHWARP2_FETCHTYPE_FetchType_MASK) /*! @} */ /*! @name FETCHWARP2_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U) /*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface. */ #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK) #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U) #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U) /*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. */ #define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name FETCHWARP2_STATUS - Status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_STATUS_WriteTimeout_MASK (0x1U) #define IRIS_MVPL_FETCHWARP2_STATUS_WriteTimeout_SHIFT (0U) /*! WriteTimeout - Timeout detected when writing to the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHWARP2_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHWARP2_STATUS_WriteTimeout_MASK) #define IRIS_MVPL_FETCHWARP2_STATUS_ReadTimeout_MASK (0x10U) #define IRIS_MVPL_FETCHWARP2_STATUS_ReadTimeout_SHIFT (4U) /*! ReadTimeout - Timeout detected when reading from the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHWARP2_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHWARP2_STATUS_ReadTimeout_MASK) /*! @} */ /*! @name FETCHWARP2_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Fetch unit is busy. */ #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBusy_MASK) #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle. */ #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBuffersIdle_MASK) #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusRequest_MASK (0x20U) #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusRequest_SHIFT (5U) /*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge. */ #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusRequest_MASK) #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusComplete_MASK (0x40U) #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusComplete_SHIFT (6U) /*! StatusComplete - Fetch unit completed all requested AXI transfers. */ #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusComplete_MASK) #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U) #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_ShadowStatus_SHIFT (8U) /*! ShadowStatus - Shadow load status for all layers (layer index = bit index). */ #define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_ShadowStatus_MASK) /*! @} */ /*! @name FETCHECO2_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO2_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHECO2_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO2_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name FETCHECO2_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHECO2_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHECO2_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO2_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_FETCHECO2_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHECO2_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHECO2_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO2_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHECO2_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHECO2_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHECO2_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO2_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name FETCHECO2_STATICCONTROL - Common static control options. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_FETCHECO2_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_FETCHECO2_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHECO2_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_FETCHECO2_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U) #define IRIS_MVPL_FETCHECO2_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U) /*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded * from shadow at start of each frame. This update is then executed independently from other RWS * type fields. ShdEn must be enabled for this mode. */ #define IRIS_MVPL_FETCHECO2_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHECO2_STATICCONTROL_BaseAddressAutoUpdate_MASK) /*! @} */ /*! @name FETCHECO2_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U) /*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of * 2. */ #define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK) #define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of * two may be specified as burst length. */ #define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK) #define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U) /*! LineMode - Fetch buffer cache control. * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_LineMode_MASK) /*! @} */ /*! @name FETCHECO2_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO2_BASEADDRESS0_BaseAddress0_SHIFT (0U) /*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit * BaseAddress[0] has to be 0. */ #define IRIS_MVPL_FETCHECO2_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHECO2_BASEADDRESS0_BaseAddress0_MASK) /*! @} */ /*! @name FETCHECO2_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU) #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U) /*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel * width of 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_Stride0_MASK) #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U) #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U) /*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or * 32. Exception: FetchEco does not support 18 and 24. */ #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK) /*! @} */ /*! @name FETCHECO2_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U) /*! LineWidth0 - Width of the source buffer of the layer in pixels minus one. */ #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineWidth0_MASK) #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U) /*! LineCount0 - Number of lines of the source buffer of the layer minus one. */ #define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineCount0_MASK) /*! @} */ /*! @name FETCHECO2_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U) /*! ComponentBitsAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U) /*! ComponentBitsBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U) /*! ComponentBitsGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U) /*! ComponentBitsRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U) /*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This * is compliant to ITU 656 standard. */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ITUFormat0_MASK) /*! @} */ /*! @name FETCHECO2_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U) /*! ComponentShiftAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U) /*! ComponentShiftBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U) /*! ComponentShiftGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U) #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U) /*! ComponentShiftRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK) /*! @} */ /*! @name FETCHECO2_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerXOffset0_SHIFT (0U) /*! LayerXOffset0 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerXOffset0_MASK) #define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerYOffset0_SHIFT (16U) /*! LayerYOffset0 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerYOffset0_MASK) /*! @} */ /*! @name FETCHECO2_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U) /*! ClipWindowXOffset0 - Horizontal position (X). */ #define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK) #define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U) /*! ClipWindowYOffset0 - Vertical position (Y). */ #define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK) /*! @} */ /*! @name FETCHECO2_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U) /*! ClipWindowWidth0 - Width. */ #define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK) #define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U) /*! ClipWindowHeight0 - Height. */ #define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK) /*! @} */ /*! @name FETCHECO2_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU) #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U) /*! ConstantAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantAlpha0_MASK) #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U) #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U) /*! ConstantBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantBlue0_MASK) #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U) #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U) /*! ConstantGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantGreen0_MASK) #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U) #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U) /*! ConstantRed0 - Red and Y (luma). */ #define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantRed0_MASK) /*! @} */ /*! @name FETCHECO2_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_TileMode0_MASK (0x30U) #define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_TileMode0_SHIFT (4U) /*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) * takes precedence if a pixel becomes subject to both tiling and clipping. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_TileMode0_MASK) #define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U) #define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U) /*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip * window get the clip color, pixels inside the source or tiling color. */ #define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_ClipWindowEnable0_MASK) #define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U) /*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling * color is used only (TileMode TILE_PAD not allowed). */ #define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_SourceBufferEnable0_MASK) /*! @} */ /*! @name FETCHECO2_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width minus one. */ #define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height minus one. */ #define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). If enabled, InputSelect must be set to INACTIVE. */ #define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name FETCHECO2_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartX_MASK (0x3FU) #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartX_SHIFT (0U) /*! StartX - X coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartX_MASK) #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartY_MASK (0xFC0U) #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartY_SHIFT (6U) /*! StartY - Y coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartY_MASK) #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaX_MASK (0x3F000U) #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaX_SHIFT (12U) /*! DeltaX - Increment of X coordinate for horizontal step in destination frame. */ #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaX_MASK) #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U) #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaY_SHIFT (18U) /*! DeltaY - Increment of Y coordinate for vertical step in destination frame. */ #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaY_MASK) #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U) #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_SwapDirection_SHIFT (24U) /*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied * for horizontal and DeltaX for vertical step on destination frame. */ #define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_SwapDirection_MASK) /*! @} */ /*! @name FETCHECO2_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_CONTROL_RawPixel_MASK (0x80U) #define IRIS_MVPL_FETCHECO2_CONTROL_RawPixel_SHIFT (7U) /*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced * for all layers by fixed values that allow passing the pixel data read from memory unchanged * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color * are deactived. Skip and Tile pixels are not affected by this setting. */ #define IRIS_MVPL_FETCHECO2_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHECO2_CONTROL_RawPixel_MASK) #define IRIS_MVPL_FETCHECO2_CONTROL_ClipColor_MASK (0x10000U) #define IRIS_MVPL_FETCHECO2_CONTROL_ClipColor_SHIFT (16U) /*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer. * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define IRIS_MVPL_FETCHECO2_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHECO2_CONTROL_ClipColor_MASK) /*! @} */ /*! @name FETCHECO2_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FETCHECO2_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_FETCHECO2_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHECO2_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name FETCHECO2_START - Frame start trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_START_Start_MASK (0x1U) #define IRIS_MVPL_FETCHECO2_START_Start_SHIFT (0U) /*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only). */ #define IRIS_MVPL_FETCHECO2_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_START_Start_SHIFT)) & IRIS_MVPL_FETCHECO2_START_Start_MASK) /*! @} */ /*! @name FETCHECO2_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_FETCHTYPE_FetchType_MASK (0xFU) #define IRIS_MVPL_FETCHECO2_FETCHTYPE_FetchType_SHIFT (0U) /*! FetchType - This field can be used to determine what kind of fetch unit this is. * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. */ #define IRIS_MVPL_FETCHECO2_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHECO2_FETCHTYPE_FetchType_MASK) /*! @} */ /*! @name FETCHECO2_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U) /*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface. */ #define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK) #define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U) /*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. */ #define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name FETCHECO2_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Fetch unit is busy. */ #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBusy_MASK) #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle. */ #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBuffersIdle_MASK) #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusRequest_MASK (0x20U) #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusRequest_SHIFT (5U) /*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge. */ #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusRequest_MASK) #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusComplete_MASK (0x40U) #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusComplete_SHIFT (6U) /*! StatusComplete - Fetch unit completed all requested AXI transfers. */ #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusComplete_MASK) #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U) #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_ShadowStatus_SHIFT (8U) /*! ShadowStatus - Shadow load status for all layers (layer index = bit index). */ #define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHECO2_HIDDENSTATUS_ShadowStatus_MASK) /*! @} */ /*! @name FETCHDECODE_LOCKUNLOCK_4 - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_4_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_4_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_4_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_4_LockUnlock_MASK) /*! @} */ /*! @name FETCHDECODE_LOCKSTATUS_4 - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_LockStatus_MASK) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_4_FreezeStatus_MASK) /*! @} */ /*! @name FETCHDECODE_STATICCONTRO_4L - Common static control options. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_4L_ShdEn_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_4L_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_4L_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATICCONTRO_4L_ShdEn_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATICCONTRO_4L_ShdEn_MASK) #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_4L_BaseAddressAutoUpdate_MASK (0xFF0000U) #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_4L_BaseAddressAutoUpdate_SHIFT (16U) /*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded * from shadow at start of each frame. This update is then executed independently from other RWS * type fields. ShdEn must be enabled for this mode. */ #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_4L_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATICCONTRO_4L_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATICCONTRO_4L_BaseAddressAutoUpdate_MASK) /*! @} */ /*! @name FETCHDECODE_BURSTBUFFERMANAGEMENT_4 - AXI interface buffer management register */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_SetNumBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_SetNumBuffers_SHIFT (0U) /*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of * 2. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_SetNumBuffers_MASK) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of * two may be specified as burst length. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_SetBurstLength_MASK) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_LineMode_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_LineMode_SHIFT (31U) /*! LineMode - Fetch buffer cache control. * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_LineMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_4_LineMode_MASK) /*! @} */ /*! @name FETCHDECODE_RINGBUFSTARTADDR0_4 - Ring buffer setup for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_4_RingBufStartAddr0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_4_RingBufStartAddr0_SHIFT (0U) /*! RingBufStartAddr0 - Start address of the ring buffer. Must be aligned to SetBurstLength x 8 bytes. */ #define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_4_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_4_RingBufStartAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_4_RingBufStartAddr0_MASK) /*! @} */ /*! @name FETCHDECODE_RINGBUFWRAPADDR0_4 - Ring buffer setup for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_4_RingBufWrapAddr0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_4_RingBufWrapAddr0_SHIFT (0U) /*! RingBufWrapAddr0 - End address of the ring buffer (last byte of the buffer plus one). */ #define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_4_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_4_RingBufWrapAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_4_RingBufWrapAddr0_MASK) /*! @} */ /*! @name FETCHDECODE_FRAMEPROPERTIES0_4 - Frame property setup for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_4_FieldId0_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_4_FieldId0_SHIFT (0U) /*! FieldId0 - Field identifier that is generated for subsequent units (0 = progressive frame or * interlaced field with even line indices, 1 = odd field). */ #define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_4_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_4_FieldId0_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_4_FieldId0_MASK) /*! @} */ /*! @name FETCHDECODE_BASEADDRESS0_4 - Source buffer base address of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_4_BaseAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_4_BaseAddress0_SHIFT (0U) /*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit * BaseAddress[0] has to be 0. */ #define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_4_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BASEADDRESS0_4_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE_BASEADDRESS0_4_BaseAddress0_MASK) /*! @} */ /*! @name FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4 - Source buffer attributes for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4_Stride0_MASK (0xFFFFU) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4_Stride0_SHIFT (0U) /*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel * width of 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4_Stride0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4_Stride0_MASK) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4_BitsPerPixel0_MASK (0x3F0000U) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4_BitsPerPixel0_SHIFT (16U) /*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or * 32. Exception: FetchEco does not support 18 and 24. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4_BitsPerPixel0_MASK) /*! @} */ /*! @name FETCHDECODE_SOURCEBUFFERDIMENSION0_4 - Source buffer dimension of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_4_LineWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_4_LineWidth0_SHIFT (0U) /*! LineWidth0 - Width of the source buffer of the layer in pixels minus one. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_4_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_4_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_4_LineWidth0_MASK) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_4_LineCount0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_4_LineCount0_SHIFT (16U) /*! LineCount0 - Number of lines of the source buffer of the layer minus one. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_4_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_4_LineCount0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_4_LineCount0_MASK) /*! @} */ /*! @name FETCHDECODE_COLORCOMPONENTBITS0_4 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsAlpha0_MASK (0xFU) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsAlpha0_SHIFT (0U) /*! ComponentBitsAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsAlpha0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsBlue0_MASK (0xF00U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsBlue0_SHIFT (8U) /*! ComponentBitsBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsBlue0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsGreen0_MASK (0xF0000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsGreen0_SHIFT (16U) /*! ComponentBitsGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsGreen0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsRed0_MASK (0xF000000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsRed0_SHIFT (24U) /*! ComponentBitsRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ComponentBitsRed0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ITUFormat0_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ITUFormat0_SHIFT (31U) /*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This * is compliant to ITU 656 standard. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_4_ITUFormat0_MASK) /*! @} */ /*! @name FETCHDECODE_COLORCOMPONENTSHIFT0_4 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftAlpha0_MASK (0x1FU) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftAlpha0_SHIFT (0U) /*! ComponentShiftAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftAlpha0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftBlue0_MASK (0x1F00U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftBlue0_SHIFT (8U) /*! ComponentShiftBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftBlue0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftGreen0_MASK (0x1F0000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftGreen0_SHIFT (16U) /*! ComponentShiftGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftGreen0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftRed0_MASK (0x1F000000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftRed0_SHIFT (24U) /*! ComponentShiftRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_4_ComponentShiftRed0_MASK) /*! @} */ /*! @name FETCHDECODE_LAYEROFFSET0_4 - Position of layer 0 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_4_LayerXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_4_LayerXOffset0_SHIFT (0U) /*! LayerXOffset0 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_4_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_4_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_4_LayerXOffset0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_4_LayerYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_4_LayerYOffset0_SHIFT (16U) /*! LayerYOffset0 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_4_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_4_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_4_LayerYOffset0_MASK) /*! @} */ /*! @name FETCHDECODE_CLIPWINDOWOFFSET0_4 - Clip window position for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_4_ClipWindowXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_4_ClipWindowXOffset0_SHIFT (0U) /*! ClipWindowXOffset0 - Horizontal position (X). */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_4_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_4_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_4_ClipWindowXOffset0_MASK) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_4_ClipWindowYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_4_ClipWindowYOffset0_SHIFT (16U) /*! ClipWindowYOffset0 - Vertical position (Y). */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_4_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_4_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_4_ClipWindowYOffset0_MASK) /*! @} */ /*! @name FETCHDECODE_CLIPWINDOWDIMENSIONS0_4 - Clip window size for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_4_ClipWindowWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_4_ClipWindowWidth0_SHIFT (0U) /*! ClipWindowWidth0 - Width. */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_4_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_4_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_4_ClipWindowWidth0_MASK) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_4_ClipWindowHeight0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_4_ClipWindowHeight0_SHIFT (16U) /*! ClipWindowHeight0 - Height. */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_4_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_4_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_4_ClipWindowHeight0_MASK) /*! @} */ /*! @name FETCHDECODE_CONSTANTCOLOR0_4 - Constant color for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantAlpha0_MASK (0xFFU) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantAlpha0_SHIFT (0U) /*! ConstantAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantAlpha0_MASK) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantBlue0_MASK (0xFF00U) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantBlue0_SHIFT (8U) /*! ConstantBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantBlue0_MASK) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantGreen0_MASK (0xFF0000U) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantGreen0_SHIFT (16U) /*! ConstantGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantGreen0_MASK) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantRed0_MASK (0xFF000000U) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantRed0_SHIFT (24U) /*! ConstantRed0 - Red and Y (luma). */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_4_ConstantRed0_MASK) /*! @} */ /*! @name FETCHDECODE_LAYERPROPERTY0_4 - Common properties of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_PaletteEnable0_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_PaletteEnable0_SHIFT (0U) /*! PaletteEnable0 - Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower * bits of the lookup index are read from memory (PaletteIdxWidth), upper bits are set to index * of this layer. Palette output is extended by upper bits of index word read from memory (e.g. * to store alpha together with index). Result is mapped to color channels according to * ColorComponentBits/Shift settings. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_PaletteEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_TileMode0_MASK (0x30U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_TileMode0_SHIFT (4U) /*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) * takes precedence if a pixel becomes subject to both tiling and clipping. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_TileMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_TileMode0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaSrcEnable0_MASK (0x100U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaSrcEnable0_SHIFT (8U) /*! AlphaSrcEnable0 - Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaConstEnable0_MASK (0x200U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaConstEnable0_SHIFT (9U) /*! AlphaConstEnable0 - Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaMaskEnable0_MASK (0x400U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaMaskEnable0_SHIFT (10U) /*! AlphaMaskEnable0 - Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaMaskEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaTransEnable0_MASK (0x800U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaTransEnable0_SHIFT (11U) /*! AlphaTransEnable0 - Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_AlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaSrcEnable0_MASK (0x1000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaSrcEnable0_SHIFT (12U) /*! RGBAlphaSrcEnable0 - Value 1 enables source alpha (stored together with color component in the * source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaConstEnable0_MASK (0x2000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaConstEnable0_SHIFT (13U) /*! RGBAlphaConstEnable0 - Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaMaskEnable0_MASK (0x4000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaMaskEnable0_SHIFT (14U) /*! RGBAlphaMaskEnable0 - Value 1 enables mask alpha (read by another Fetch unit from a separate * alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be * enabled for this field to have effect. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaMaskEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaTransEnable0_MASK (0x8000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaTransEnable0_SHIFT (15U) /*! RGBAlphaTransEnable0 - Value 1 enables transparent alpha (0 or 1 depending on RGB matching * ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_RGBAlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_PremulConstRGB0_MASK (0x10000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_PremulConstRGB0_SHIFT (16U) /*! PremulConstRGB0 - When enabled (value 1) the values given by ConstantRed/Green/Blue are used * instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no * effect then. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_PremulConstRGB0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_YUVConversionMode0_MASK (0x60000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_YUVConversionMode0_SHIFT (17U) /*! YUVConversionMode0 - Enables different kind of YUV to RGB conversions. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_YUVConversionMode0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_GammaRemoveEnable0_MASK (0x100000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_GammaRemoveEnable0_SHIFT (20U) /*! GammaRemoveEnable0 - Value 1 enables the stage to remove a gamma from RGB components. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_GammaRemoveEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_ClipWindowEnable0_MASK (0x40000000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_ClipWindowEnable0_SHIFT (30U) /*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip * window get the clip color, pixels inside the source or tiling color. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_ClipWindowEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_SourceBufferEnable0_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_SourceBufferEnable0_SHIFT (31U) /*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling * color is used only (TileMode TILE_PAD not allowed). */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_4_SourceBufferEnable0_MASK) /*! @} */ /*! @name FETCHDECODE_FRAMEDIMENSIONS_4 - Output frame dimension. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width minus one. */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_FrameWidth_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height minus one. */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_FrameHeight_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). If enabled, InputSelect must be set to INACTIVE. */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_4_EmptyFrame_MASK) /*! @} */ /*! @name FETCHDECODE_FRAMERESAMPLING_4 - Resampling options for output frame. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_StartX_MASK (0x3FU) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_StartX_SHIFT (0U) /*! StartX - X coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_StartX_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_StartX_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_StartY_MASK (0xFC0U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_StartY_SHIFT (6U) /*! StartY - Y coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_StartY_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_StartY_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_DeltaX_MASK (0x3F000U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_DeltaX_SHIFT (12U) /*! DeltaX - Increment of X coordinate for horizontal step in destination frame. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_DeltaX_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_DeltaX_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_DeltaY_MASK (0xFC0000U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_DeltaY_SHIFT (18U) /*! DeltaY - Increment of Y coordinate for vertical step in destination frame. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_DeltaY_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_DeltaY_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_SwapDirection_MASK (0x1000000U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_SwapDirection_SHIFT (24U) /*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied * for horizontal and DeltaX for vertical step on destination frame. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_4_SwapDirection_MASK) /*! @} */ /*! @name FETCHDECODE_DECODECONTROL_4 - Control options for RLAD decompression. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_CompressionMode_MASK (0x3U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_CompressionMode_SHIFT (0U) /*! CompressionMode - Algorithm that the encoder used for compression. * 0b00..Run-Length Adaptive Dithering (lossy compression). * 0b01..Run-Length Adaptive Dithering (lossy compression; uniform package size). * 0b10..Run-Length Adaptive (lossless compression). * 0b11..Standard Run-Length. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_CompressionMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_CompressionMode_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADEndianness_MASK (0x8000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADEndianness_SHIFT (15U) /*! RLADEndianness - Changes endianness of decoder for RL mode, does not affect any other CompressionModes * 0b0..Big endian format * 0b1..Little endian format */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADEndianness(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADEndianness_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADEndianness_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsRed_MASK (0xF0000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsRed_SHIFT (16U) /*! RLADCompBitsRed - Maximum for average number of bits per compressed pixel for Red or Y (luma) * channel. This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsRed_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsGreen_MASK (0xF00000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsGreen_SHIFT (20U) /*! RLADCompBitsGreen - Maximum for average number of bits per compressed pixel for Green or U * (chroma) channel. This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsGreen_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsBlue_MASK (0xF000000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsBlue_SHIFT (24U) /*! RLADCompBitsBlue - Maximum for average number of bits per compressed pixel for Blue or V * (chroma) channel. This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsBlue_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsAlpha_MASK (0xF0000000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsAlpha_SHIFT (28U) /*! RLADCompBitsAlpha - Maximum for average number of bits per compressed pixel for Alpha channel. * This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_4_RLADCompBitsAlpha_MASK) /*! @} */ /*! @name FETCHDECODE_SOURCEBUFFERLENGTH_4 - Source buffer length for compressed data. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_4_RLEWords_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_4_RLEWords_SHIFT (0U) /*! RLEWords - Number of 32-bit words minus one that are required to decode the run length encoded source buffer. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_4_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_4_RLEWords_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_4_RLEWords_MASK) /*! @} */ /*! @name FETCHDECODE_CONTROL_4 - Shared common control settings for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CONTROL_4_RasterMode_MASK (0x7U) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_RasterMode_SHIFT (0U) /*! RasterMode - Selects a method how to generate source buffer sample points. * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot/RotL only] Arbitrary warping (filter is active). Coordinates are read from frame * input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_4_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_4_RasterMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_4_RasterMode_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_InputSelect_MASK (0x18U) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_InputSelect_SHIFT (3U) /*! InputSelect - Selects function for the frame input port. * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define IRIS_MVPL_FETCHDECODE_CONTROL_4_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_4_InputSelect_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_4_InputSelect_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_YUV422UpsamplingMode_MASK (0x20U) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_YUV422UpsamplingMode_SHIFT (5U) /*! YUV422UpsamplingMode - Selects a method for horizontal up-sampling of YUV 4:2:2/4:2:0 input data. * 0b0..Replicate mode for interspersed samples (UV samples between Y samples). * 0b1..Interpolate mode for coaligned samples (UV samples at Y sample positions). */ #define IRIS_MVPL_FETCHDECODE_CONTROL_4_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_4_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_4_YUV422UpsamplingMode_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_RawPixel_MASK (0x80U) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_RawPixel_SHIFT (7U) /*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced * for all layers by fixed values that allow passing the pixel data read from memory unchanged * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color * are deactived. Skip and Tile pixels are not affected by this setting. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_4_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_4_RawPixel_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_4_RawPixel_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_PaletteIdxWidth_MASK (0x700U) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_PaletteIdxWidth_SHIFT (8U) /*! PaletteIdxWidth - Number minus one of least significant bits of pixel data read from the source * buffer that are used as index value for color palette look-up. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_4_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_4_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_4_PaletteIdxWidth_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_ClipColor_MASK (0x10000U) #define IRIS_MVPL_FETCHDECODE_CONTROL_4_ClipColor_SHIFT (16U) /*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer. * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_4_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_4_ClipColor_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_4_ClipColor_MASK) /*! @} */ /*! @name FETCHDECODE_CONTROLTRIGGER_4 - Shadow load trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_4_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_4_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_4_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_4_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_4_ShdTokGen_MASK) /*! @} */ /*! @name FETCHDECODE_START_4 - Frame start trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_START_4_Start_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_START_4_Start_SHIFT (0U) /*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only). */ #define IRIS_MVPL_FETCHDECODE_START_4_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_START_4_Start_SHIFT)) & IRIS_MVPL_FETCHDECODE_START_4_Start_MASK) /*! @} */ /*! @name FETCHDECODE_FETCHTYPE_4 - Fetch unit type. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FETCHTYPE_4_FetchType_MASK (0xFU) #define IRIS_MVPL_FETCHDECODE_FETCHTYPE_4_FetchType_SHIFT (0U) /*! FetchType - This field can be used to determine what kind of fetch unit this is. * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. */ #define IRIS_MVPL_FETCHDECODE_FETCHTYPE_4_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FETCHTYPE_4_FetchType_SHIFT)) & IRIS_MVPL_FETCHDECODE_FETCHTYPE_4_FetchType_MASK) /*! @} */ /*! @name FETCHDECODE_DECODERSTATUS_4 - Status information of the RLAD decoder. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_4_BufferTooSmall_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_4_BufferTooSmall_SHIFT (0U) /*! BufferTooSmall - The buffer size given by RLEWords is too small. No complete output frame could be decoded. */ #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_4_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODERSTATUS_4_BufferTooSmall_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODERSTATUS_4_BufferTooSmall_MASK) #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_4_BufferTooLarge_MASK (0x2U) #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_4_BufferTooLarge_SHIFT (1U) /*! BufferTooLarge - The buffer size given by RLEWords is too large. A complete output frame could * be decoded, but more data was read than necessary. */ #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_4_BufferTooLarge(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODERSTATUS_4_BufferTooLarge_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODERSTATUS_4_BufferTooLarge_MASK) /*! @} */ /*! @name FETCHDECODE_READADDRESS0_4 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_READADDRESS0_4_ReadAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_READADDRESS0_4_ReadAddress0_SHIFT (0U) /*! ReadAddress0 - Last burst address that was read from the layer's source buffer. */ #define IRIS_MVPL_FETCHDECODE_READADDRESS0_4_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_READADDRESS0_4_ReadAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE_READADDRESS0_4_ReadAddress0_MASK) /*! @} */ /*! @name FETCHDECODE_BURSTBUFFERPROPERTIES_4 - Burst buffer properties. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_4_ManagedBurstBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_4_ManagedBurstBuffers_SHIFT (0U) /*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_4_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_4_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_4_ManagedBurstBuffers_MASK) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_4_BurstLengthForMaxBuffers_MASK (0x1F00U) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_4_BurstLengthForMaxBuffers_SHIFT (8U) /*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_4_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_4_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_4_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name FETCHDECODE_STATUS_4 - Status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_STATUS_4_WriteTimeout_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_STATUS_4_WriteTimeout_SHIFT (0U) /*! WriteTimeout - Timeout detected when writing to the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHDECODE_STATUS_4_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATUS_4_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATUS_4_WriteTimeout_MASK) #define IRIS_MVPL_FETCHDECODE_STATUS_4_ReadTimeout_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE_STATUS_4_ReadTimeout_SHIFT (4U) /*! ReadTimeout - Timeout detected when reading from the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHDECODE_STATUS_4_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATUS_4_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATUS_4_ReadTimeout_MASK) /*! @} */ /*! @name FETCHDECODE_HIDDENSTATUS_4 - Hidden status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusBusy_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusBusy_SHIFT (0U) /*! StatusBusy - Fetch unit is busy. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusBusy_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusBuffersIdle_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusRequest_MASK (0x20U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusRequest_SHIFT (5U) /*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusRequest_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusComplete_MASK (0x40U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusComplete_SHIFT (6U) /*! StatusComplete - Fetch unit completed all requested AXI transfers. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_StatusComplete_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_ShadowStatus_MASK (0xFF00U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_ShadowStatus_SHIFT (8U) /*! ShadowStatus - Shadow load status for all layers (layer index = bit index). */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_4_ShadowStatus_MASK) /*! @} */ /*! @name COLORPALETTE_4 - Color palette look up table. */ /*! @{ */ #define IRIS_MVPL_COLORPALETTE_4_ColorPalette_MASK (0xFFFFFFU) #define IRIS_MVPL_COLORPALETTE_4_ColorPalette_SHIFT (0U) /*! ColorPalette - Entry of the color palette look-up table */ #define IRIS_MVPL_COLORPALETTE_4_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COLORPALETTE_4_ColorPalette_SHIFT)) & IRIS_MVPL_COLORPALETTE_4_ColorPalette_MASK) /*! @} */ /*! @name FETCHECO0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHECO0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name FETCHECO0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHECO0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHECO0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_FETCHECO0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHECO0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHECO0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHECO0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHECO0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHECO0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name FETCHECO0_STATICCONTROL - Common static control options. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_FETCHECO0_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_FETCHECO0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHECO0_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_FETCHECO0_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U) #define IRIS_MVPL_FETCHECO0_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U) /*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded * from shadow at start of each frame. This update is then executed independently from other RWS * type fields. ShdEn must be enabled for this mode. */ #define IRIS_MVPL_FETCHECO0_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHECO0_STATICCONTROL_BaseAddressAutoUpdate_MASK) /*! @} */ /*! @name FETCHECO0_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U) /*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of * 2. */ #define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK) #define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of * two may be specified as burst length. */ #define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK) #define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U) /*! LineMode - Fetch buffer cache control. * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_LineMode_MASK) /*! @} */ /*! @name FETCHECO0_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO0_BASEADDRESS0_BaseAddress0_SHIFT (0U) /*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit * BaseAddress[0] has to be 0. */ #define IRIS_MVPL_FETCHECO0_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHECO0_BASEADDRESS0_BaseAddress0_MASK) /*! @} */ /*! @name FETCHECO0_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU) #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U) /*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel * width of 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_Stride0_MASK) #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U) #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U) /*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or * 32. Exception: FetchEco does not support 18 and 24. */ #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK) /*! @} */ /*! @name FETCHECO0_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U) /*! LineWidth0 - Width of the source buffer of the layer in pixels minus one. */ #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineWidth0_MASK) #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U) /*! LineCount0 - Number of lines of the source buffer of the layer minus one. */ #define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineCount0_MASK) /*! @} */ /*! @name FETCHECO0_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U) /*! ComponentBitsAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U) /*! ComponentBitsBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U) /*! ComponentBitsGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U) /*! ComponentBitsRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U) /*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This * is compliant to ITU 656 standard. */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ITUFormat0_MASK) /*! @} */ /*! @name FETCHECO0_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U) /*! ComponentShiftAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U) /*! ComponentShiftBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U) /*! ComponentShiftGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U) #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U) /*! ComponentShiftRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK) /*! @} */ /*! @name FETCHECO0_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerXOffset0_SHIFT (0U) /*! LayerXOffset0 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerXOffset0_MASK) #define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerYOffset0_SHIFT (16U) /*! LayerYOffset0 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerYOffset0_MASK) /*! @} */ /*! @name FETCHECO0_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U) /*! ClipWindowXOffset0 - Horizontal position (X). */ #define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK) #define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U) /*! ClipWindowYOffset0 - Vertical position (Y). */ #define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK) /*! @} */ /*! @name FETCHECO0_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U) /*! ClipWindowWidth0 - Width. */ #define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK) #define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U) /*! ClipWindowHeight0 - Height. */ #define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK) /*! @} */ /*! @name FETCHECO0_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU) #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U) /*! ConstantAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantAlpha0_MASK) #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U) #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U) /*! ConstantBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantBlue0_MASK) #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U) #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U) /*! ConstantGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantGreen0_MASK) #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U) #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U) /*! ConstantRed0 - Red and Y (luma). */ #define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantRed0_MASK) /*! @} */ /*! @name FETCHECO0_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_TileMode0_MASK (0x30U) #define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_TileMode0_SHIFT (4U) /*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) * takes precedence if a pixel becomes subject to both tiling and clipping. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_TileMode0_MASK) #define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U) #define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U) /*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip * window get the clip color, pixels inside the source or tiling color. */ #define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_ClipWindowEnable0_MASK) #define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U) /*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling * color is used only (TileMode TILE_PAD not allowed). */ #define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_SourceBufferEnable0_MASK) /*! @} */ /*! @name FETCHECO0_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width minus one. */ #define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height minus one. */ #define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). If enabled, InputSelect must be set to INACTIVE. */ #define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name FETCHECO0_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartX_MASK (0x3FU) #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartX_SHIFT (0U) /*! StartX - X coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartX_MASK) #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartY_MASK (0xFC0U) #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartY_SHIFT (6U) /*! StartY - Y coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartY_MASK) #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaX_MASK (0x3F000U) #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaX_SHIFT (12U) /*! DeltaX - Increment of X coordinate for horizontal step in destination frame. */ #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaX_MASK) #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U) #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaY_SHIFT (18U) /*! DeltaY - Increment of Y coordinate for vertical step in destination frame. */ #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaY_MASK) #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U) #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_SwapDirection_SHIFT (24U) /*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied * for horizontal and DeltaX for vertical step on destination frame. */ #define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_SwapDirection_MASK) /*! @} */ /*! @name FETCHECO0_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_CONTROL_RawPixel_MASK (0x80U) #define IRIS_MVPL_FETCHECO0_CONTROL_RawPixel_SHIFT (7U) /*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced * for all layers by fixed values that allow passing the pixel data read from memory unchanged * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color * are deactived. Skip and Tile pixels are not affected by this setting. */ #define IRIS_MVPL_FETCHECO0_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHECO0_CONTROL_RawPixel_MASK) #define IRIS_MVPL_FETCHECO0_CONTROL_ClipColor_MASK (0x10000U) #define IRIS_MVPL_FETCHECO0_CONTROL_ClipColor_SHIFT (16U) /*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer. * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define IRIS_MVPL_FETCHECO0_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHECO0_CONTROL_ClipColor_MASK) /*! @} */ /*! @name FETCHECO0_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FETCHECO0_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_FETCHECO0_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHECO0_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name FETCHECO0_START - Frame start trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_START_Start_MASK (0x1U) #define IRIS_MVPL_FETCHECO0_START_Start_SHIFT (0U) /*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only). */ #define IRIS_MVPL_FETCHECO0_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_START_Start_SHIFT)) & IRIS_MVPL_FETCHECO0_START_Start_MASK) /*! @} */ /*! @name FETCHECO0_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_FETCHTYPE_FetchType_MASK (0xFU) #define IRIS_MVPL_FETCHECO0_FETCHTYPE_FetchType_SHIFT (0U) /*! FetchType - This field can be used to determine what kind of fetch unit this is. * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. */ #define IRIS_MVPL_FETCHECO0_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHECO0_FETCHTYPE_FetchType_MASK) /*! @} */ /*! @name FETCHECO0_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U) /*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface. */ #define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK) #define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U) /*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. */ #define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name FETCHECO0_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Fetch unit is busy. */ #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBusy_MASK) #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle. */ #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBuffersIdle_MASK) #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusRequest_MASK (0x20U) #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusRequest_SHIFT (5U) /*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge. */ #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusRequest_MASK) #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusComplete_MASK (0x40U) #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusComplete_SHIFT (6U) /*! StatusComplete - Fetch unit completed all requested AXI transfers. */ #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusComplete_MASK) #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U) #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_ShadowStatus_SHIFT (8U) /*! ShadowStatus - Shadow load status for all layers (layer index = bit index). */ #define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHECO0_HIDDENSTATUS_ShadowStatus_MASK) /*! @} */ /*! @name FETCHDECODE_LOCKUNLOCK_7 - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_7_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_7_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_7_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_7_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_7_LockUnlock_MASK) /*! @} */ /*! @name FETCHDECODE_LOCKSTATUS_7 - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_LockStatus_MASK) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_7_FreezeStatus_MASK) /*! @} */ /*! @name FETCHDECODE_STATICCONTRO_7L - Common static control options. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_7L_ShdEn_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_7L_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_7L_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATICCONTRO_7L_ShdEn_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATICCONTRO_7L_ShdEn_MASK) #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_7L_BaseAddressAutoUpdate_MASK (0xFF0000U) #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_7L_BaseAddressAutoUpdate_SHIFT (16U) /*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded * from shadow at start of each frame. This update is then executed independently from other RWS * type fields. ShdEn must be enabled for this mode. */ #define IRIS_MVPL_FETCHDECODE_STATICCONTRO_7L_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATICCONTRO_7L_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATICCONTRO_7L_BaseAddressAutoUpdate_MASK) /*! @} */ /*! @name FETCHDECODE_BURSTBUFFERMANAGEMENT_7 - AXI interface buffer management register */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_SetNumBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_SetNumBuffers_SHIFT (0U) /*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of * 2. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_SetNumBuffers_MASK) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of * two may be specified as burst length. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_SetBurstLength_MASK) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_LineMode_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_LineMode_SHIFT (31U) /*! LineMode - Fetch buffer cache control. * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_LineMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_7_LineMode_MASK) /*! @} */ /*! @name FETCHDECODE_RINGBUFSTARTADDR0_7 - Ring buffer setup for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_7_RingBufStartAddr0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_7_RingBufStartAddr0_SHIFT (0U) /*! RingBufStartAddr0 - Start address of the ring buffer. Must be aligned to SetBurstLength x 8 bytes. */ #define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_7_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_7_RingBufStartAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_7_RingBufStartAddr0_MASK) /*! @} */ /*! @name FETCHDECODE_RINGBUFWRAPADDR0_7 - Ring buffer setup for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_7_RingBufWrapAddr0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_7_RingBufWrapAddr0_SHIFT (0U) /*! RingBufWrapAddr0 - End address of the ring buffer (last byte of the buffer plus one). */ #define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_7_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_7_RingBufWrapAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_7_RingBufWrapAddr0_MASK) /*! @} */ /*! @name FETCHDECODE_FRAMEPROPERTIES0_7 - Frame property setup for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_7_FieldId0_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_7_FieldId0_SHIFT (0U) /*! FieldId0 - Field identifier that is generated for subsequent units (0 = progressive frame or * interlaced field with even line indices, 1 = odd field). */ #define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_7_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_7_FieldId0_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_7_FieldId0_MASK) /*! @} */ /*! @name FETCHDECODE_BASEADDRESS0_7 - Source buffer base address of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_7_BaseAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_7_BaseAddress0_SHIFT (0U) /*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit * BaseAddress[0] has to be 0. */ #define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_7_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BASEADDRESS0_7_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE_BASEADDRESS0_7_BaseAddress0_MASK) /*! @} */ /*! @name FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7 - Source buffer attributes for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7_Stride0_MASK (0xFFFFU) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7_Stride0_SHIFT (0U) /*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel * width of 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7_Stride0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7_Stride0_MASK) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7_BitsPerPixel0_MASK (0x3F0000U) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7_BitsPerPixel0_SHIFT (16U) /*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or * 32. Exception: FetchEco does not support 18 and 24. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7_BitsPerPixel0_MASK) /*! @} */ /*! @name FETCHDECODE_SOURCEBUFFERDIMENSION0_7 - Source buffer dimension of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_7_LineWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_7_LineWidth0_SHIFT (0U) /*! LineWidth0 - Width of the source buffer of the layer in pixels minus one. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_7_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_7_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_7_LineWidth0_MASK) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_7_LineCount0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_7_LineCount0_SHIFT (16U) /*! LineCount0 - Number of lines of the source buffer of the layer minus one. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_7_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_7_LineCount0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_7_LineCount0_MASK) /*! @} */ /*! @name FETCHDECODE_COLORCOMPONENTBITS0_7 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsAlpha0_MASK (0xFU) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsAlpha0_SHIFT (0U) /*! ComponentBitsAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsAlpha0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsBlue0_MASK (0xF00U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsBlue0_SHIFT (8U) /*! ComponentBitsBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsBlue0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsGreen0_MASK (0xF0000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsGreen0_SHIFT (16U) /*! ComponentBitsGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsGreen0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsRed0_MASK (0xF000000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsRed0_SHIFT (24U) /*! ComponentBitsRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ComponentBitsRed0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ITUFormat0_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ITUFormat0_SHIFT (31U) /*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This * is compliant to ITU 656 standard. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_7_ITUFormat0_MASK) /*! @} */ /*! @name FETCHDECODE_COLORCOMPONENTSHIFT0_7 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftAlpha0_MASK (0x1FU) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftAlpha0_SHIFT (0U) /*! ComponentShiftAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftAlpha0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftBlue0_MASK (0x1F00U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftBlue0_SHIFT (8U) /*! ComponentShiftBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftBlue0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftGreen0_MASK (0x1F0000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftGreen0_SHIFT (16U) /*! ComponentShiftGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftGreen0_MASK) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftRed0_MASK (0x1F000000U) #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftRed0_SHIFT (24U) /*! ComponentShiftRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_7_ComponentShiftRed0_MASK) /*! @} */ /*! @name FETCHDECODE_LAYEROFFSET0_7 - Position of layer 0 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_7_LayerXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_7_LayerXOffset0_SHIFT (0U) /*! LayerXOffset0 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_7_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_7_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_7_LayerXOffset0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_7_LayerYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_7_LayerYOffset0_SHIFT (16U) /*! LayerYOffset0 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_7_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_7_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_7_LayerYOffset0_MASK) /*! @} */ /*! @name FETCHDECODE_CLIPWINDOWOFFSET0_7 - Clip window position for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_7_ClipWindowXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_7_ClipWindowXOffset0_SHIFT (0U) /*! ClipWindowXOffset0 - Horizontal position (X). */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_7_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_7_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_7_ClipWindowXOffset0_MASK) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_7_ClipWindowYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_7_ClipWindowYOffset0_SHIFT (16U) /*! ClipWindowYOffset0 - Vertical position (Y). */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_7_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_7_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_7_ClipWindowYOffset0_MASK) /*! @} */ /*! @name FETCHDECODE_CLIPWINDOWDIMENSIONS0_7 - Clip window size for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_7_ClipWindowWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_7_ClipWindowWidth0_SHIFT (0U) /*! ClipWindowWidth0 - Width. */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_7_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_7_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_7_ClipWindowWidth0_MASK) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_7_ClipWindowHeight0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_7_ClipWindowHeight0_SHIFT (16U) /*! ClipWindowHeight0 - Height. */ #define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_7_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_7_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_7_ClipWindowHeight0_MASK) /*! @} */ /*! @name FETCHDECODE_CONSTANTCOLOR0_7 - Constant color for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantAlpha0_MASK (0xFFU) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantAlpha0_SHIFT (0U) /*! ConstantAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantAlpha0_MASK) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantBlue0_MASK (0xFF00U) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantBlue0_SHIFT (8U) /*! ConstantBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantBlue0_MASK) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantGreen0_MASK (0xFF0000U) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantGreen0_SHIFT (16U) /*! ConstantGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantGreen0_MASK) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantRed0_MASK (0xFF000000U) #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantRed0_SHIFT (24U) /*! ConstantRed0 - Red and Y (luma). */ #define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_7_ConstantRed0_MASK) /*! @} */ /*! @name FETCHDECODE_LAYERPROPERTY0_7 - Common properties of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_PaletteEnable0_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_PaletteEnable0_SHIFT (0U) /*! PaletteEnable0 - Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower * bits of the lookup index are read from memory (PaletteIdxWidth), upper bits are set to index * of this layer. Palette output is extended by upper bits of index word read from memory (e.g. * to store alpha together with index). Result is mapped to color channels according to * ColorComponentBits/Shift settings. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_PaletteEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_TileMode0_MASK (0x30U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_TileMode0_SHIFT (4U) /*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) * takes precedence if a pixel becomes subject to both tiling and clipping. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_TileMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_TileMode0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaSrcEnable0_MASK (0x100U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaSrcEnable0_SHIFT (8U) /*! AlphaSrcEnable0 - Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaConstEnable0_MASK (0x200U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaConstEnable0_SHIFT (9U) /*! AlphaConstEnable0 - Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaMaskEnable0_MASK (0x400U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaMaskEnable0_SHIFT (10U) /*! AlphaMaskEnable0 - Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaMaskEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaTransEnable0_MASK (0x800U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaTransEnable0_SHIFT (11U) /*! AlphaTransEnable0 - Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_AlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaSrcEnable0_MASK (0x1000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaSrcEnable0_SHIFT (12U) /*! RGBAlphaSrcEnable0 - Value 1 enables source alpha (stored together with color component in the * source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaConstEnable0_MASK (0x2000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaConstEnable0_SHIFT (13U) /*! RGBAlphaConstEnable0 - Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaMaskEnable0_MASK (0x4000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaMaskEnable0_SHIFT (14U) /*! RGBAlphaMaskEnable0 - Value 1 enables mask alpha (read by another Fetch unit from a separate * alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be * enabled for this field to have effect. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaMaskEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaTransEnable0_MASK (0x8000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaTransEnable0_SHIFT (15U) /*! RGBAlphaTransEnable0 - Value 1 enables transparent alpha (0 or 1 depending on RGB matching * ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_RGBAlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_PremulConstRGB0_MASK (0x10000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_PremulConstRGB0_SHIFT (16U) /*! PremulConstRGB0 - When enabled (value 1) the values given by ConstantRed/Green/Blue are used * instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no * effect then. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_PremulConstRGB0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_YUVConversionMode0_MASK (0x60000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_YUVConversionMode0_SHIFT (17U) /*! YUVConversionMode0 - Enables different kind of YUV to RGB conversions. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_YUVConversionMode0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_GammaRemoveEnable0_MASK (0x100000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_GammaRemoveEnable0_SHIFT (20U) /*! GammaRemoveEnable0 - Value 1 enables the stage to remove a gamma from RGB components. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_GammaRemoveEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_ClipWindowEnable0_MASK (0x40000000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_ClipWindowEnable0_SHIFT (30U) /*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip * window get the clip color, pixels inside the source or tiling color. */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_ClipWindowEnable0_MASK) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_SourceBufferEnable0_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_SourceBufferEnable0_SHIFT (31U) /*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling * color is used only (TileMode TILE_PAD not allowed). */ #define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_7_SourceBufferEnable0_MASK) /*! @} */ /*! @name FETCHDECODE_FRAMEDIMENSIONS_7 - Output frame dimension. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width minus one. */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_FrameWidth_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height minus one. */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_FrameHeight_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). If enabled, InputSelect must be set to INACTIVE. */ #define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_7_EmptyFrame_MASK) /*! @} */ /*! @name FETCHDECODE_FRAMERESAMPLING_7 - Resampling options for output frame. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_StartX_MASK (0x3FU) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_StartX_SHIFT (0U) /*! StartX - X coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_StartX_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_StartX_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_StartY_MASK (0xFC0U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_StartY_SHIFT (6U) /*! StartY - Y coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_StartY_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_StartY_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_DeltaX_MASK (0x3F000U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_DeltaX_SHIFT (12U) /*! DeltaX - Increment of X coordinate for horizontal step in destination frame. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_DeltaX_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_DeltaX_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_DeltaY_MASK (0xFC0000U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_DeltaY_SHIFT (18U) /*! DeltaY - Increment of Y coordinate for vertical step in destination frame. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_DeltaY_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_DeltaY_MASK) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_SwapDirection_MASK (0x1000000U) #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_SwapDirection_SHIFT (24U) /*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied * for horizontal and DeltaX for vertical step on destination frame. */ #define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_7_SwapDirection_MASK) /*! @} */ /*! @name FETCHDECODE_DECODECONTROL_7 - Control options for RLAD decompression. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_CompressionMode_MASK (0x3U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_CompressionMode_SHIFT (0U) /*! CompressionMode - Algorithm that the encoder used for compression. * 0b00..Run-Length Adaptive Dithering (lossy compression). * 0b01..Run-Length Adaptive Dithering (lossy compression; uniform package size). * 0b10..Run-Length Adaptive (lossless compression). * 0b11..Standard Run-Length. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_CompressionMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_CompressionMode_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADEndianness_MASK (0x8000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADEndianness_SHIFT (15U) /*! RLADEndianness - Changes endianness of decoder for RL mode, does not affect any other CompressionModes * 0b0..Big endian format * 0b1..Little endian format */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADEndianness(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADEndianness_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADEndianness_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsRed_MASK (0xF0000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsRed_SHIFT (16U) /*! RLADCompBitsRed - Maximum for average number of bits per compressed pixel for Red or Y (luma) * channel. This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsRed_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsGreen_MASK (0xF00000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsGreen_SHIFT (20U) /*! RLADCompBitsGreen - Maximum for average number of bits per compressed pixel for Green or U * (chroma) channel. This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsGreen_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsBlue_MASK (0xF000000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsBlue_SHIFT (24U) /*! RLADCompBitsBlue - Maximum for average number of bits per compressed pixel for Blue or V * (chroma) channel. This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsBlue_MASK) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsAlpha_MASK (0xF0000000U) #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsAlpha_SHIFT (28U) /*! RLADCompBitsAlpha - Maximum for average number of bits per compressed pixel for Alpha channel. * This must match the corresponding encoder setting. */ #define IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_7_RLADCompBitsAlpha_MASK) /*! @} */ /*! @name FETCHDECODE_SOURCEBUFFERLENGTH_7 - Source buffer length for compressed data. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_7_RLEWords_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_7_RLEWords_SHIFT (0U) /*! RLEWords - Number of 32-bit words minus one that are required to decode the run length encoded source buffer. */ #define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_7_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_7_RLEWords_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_7_RLEWords_MASK) /*! @} */ /*! @name FETCHDECODE_CONTROL_7 - Shared common control settings for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CONTROL_7_RasterMode_MASK (0x7U) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_RasterMode_SHIFT (0U) /*! RasterMode - Selects a method how to generate source buffer sample points. * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot/RotL only] Arbitrary warping (filter is active). Coordinates are read from frame * input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_7_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_7_RasterMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_7_RasterMode_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_InputSelect_MASK (0x18U) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_InputSelect_SHIFT (3U) /*! InputSelect - Selects function for the frame input port. * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define IRIS_MVPL_FETCHDECODE_CONTROL_7_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_7_InputSelect_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_7_InputSelect_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_YUV422UpsamplingMode_MASK (0x20U) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_YUV422UpsamplingMode_SHIFT (5U) /*! YUV422UpsamplingMode - Selects a method for horizontal up-sampling of YUV 4:2:2/4:2:0 input data. * 0b0..Replicate mode for interspersed samples (UV samples between Y samples). * 0b1..Interpolate mode for coaligned samples (UV samples at Y sample positions). */ #define IRIS_MVPL_FETCHDECODE_CONTROL_7_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_7_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_7_YUV422UpsamplingMode_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_RawPixel_MASK (0x80U) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_RawPixel_SHIFT (7U) /*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced * for all layers by fixed values that allow passing the pixel data read from memory unchanged * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color * are deactived. Skip and Tile pixels are not affected by this setting. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_7_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_7_RawPixel_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_7_RawPixel_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_PaletteIdxWidth_MASK (0x700U) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_PaletteIdxWidth_SHIFT (8U) /*! PaletteIdxWidth - Number minus one of least significant bits of pixel data read from the source * buffer that are used as index value for color palette look-up. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_7_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_7_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_7_PaletteIdxWidth_MASK) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_ClipColor_MASK (0x10000U) #define IRIS_MVPL_FETCHDECODE_CONTROL_7_ClipColor_SHIFT (16U) /*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer. * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define IRIS_MVPL_FETCHDECODE_CONTROL_7_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_7_ClipColor_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_7_ClipColor_MASK) /*! @} */ /*! @name FETCHDECODE_CONTROLTRIGGER_7 - Shadow load trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_7_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_7_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_7_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_7_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_7_ShdTokGen_MASK) /*! @} */ /*! @name FETCHDECODE_START_7 - Frame start trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_START_7_Start_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_START_7_Start_SHIFT (0U) /*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only). */ #define IRIS_MVPL_FETCHDECODE_START_7_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_START_7_Start_SHIFT)) & IRIS_MVPL_FETCHDECODE_START_7_Start_MASK) /*! @} */ /*! @name FETCHDECODE_FETCHTYPE_7 - Fetch unit type. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_FETCHTYPE_7_FetchType_MASK (0xFU) #define IRIS_MVPL_FETCHDECODE_FETCHTYPE_7_FetchType_SHIFT (0U) /*! FetchType - This field can be used to determine what kind of fetch unit this is. * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. */ #define IRIS_MVPL_FETCHDECODE_FETCHTYPE_7_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FETCHTYPE_7_FetchType_SHIFT)) & IRIS_MVPL_FETCHDECODE_FETCHTYPE_7_FetchType_MASK) /*! @} */ /*! @name FETCHDECODE_DECODERSTATUS_7 - Status information of the RLAD decoder. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_7_BufferTooSmall_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_7_BufferTooSmall_SHIFT (0U) /*! BufferTooSmall - The buffer size given by RLEWords is too small. No complete output frame could be decoded. */ #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_7_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODERSTATUS_7_BufferTooSmall_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODERSTATUS_7_BufferTooSmall_MASK) #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_7_BufferTooLarge_MASK (0x2U) #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_7_BufferTooLarge_SHIFT (1U) /*! BufferTooLarge - The buffer size given by RLEWords is too large. A complete output frame could * be decoded, but more data was read than necessary. */ #define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_7_BufferTooLarge(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODERSTATUS_7_BufferTooLarge_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODERSTATUS_7_BufferTooLarge_MASK) /*! @} */ /*! @name FETCHDECODE_READADDRESS0_7 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_READADDRESS0_7_ReadAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHDECODE_READADDRESS0_7_ReadAddress0_SHIFT (0U) /*! ReadAddress0 - Last burst address that was read from the layer's source buffer. */ #define IRIS_MVPL_FETCHDECODE_READADDRESS0_7_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_READADDRESS0_7_ReadAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE_READADDRESS0_7_ReadAddress0_MASK) /*! @} */ /*! @name FETCHDECODE_BURSTBUFFERPROPERTIES_7 - Burst buffer properties. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_7_ManagedBurstBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_7_ManagedBurstBuffers_SHIFT (0U) /*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_7_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_7_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_7_ManagedBurstBuffers_MASK) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_7_BurstLengthForMaxBuffers_MASK (0x1F00U) #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_7_BurstLengthForMaxBuffers_SHIFT (8U) /*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. */ #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_7_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_7_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_7_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name FETCHDECODE_STATUS_7 - Status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_STATUS_7_WriteTimeout_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_STATUS_7_WriteTimeout_SHIFT (0U) /*! WriteTimeout - Timeout detected when writing to the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHDECODE_STATUS_7_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATUS_7_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATUS_7_WriteTimeout_MASK) #define IRIS_MVPL_FETCHDECODE_STATUS_7_ReadTimeout_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE_STATUS_7_ReadTimeout_SHIFT (4U) /*! ReadTimeout - Timeout detected when reading from the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHDECODE_STATUS_7_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATUS_7_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATUS_7_ReadTimeout_MASK) /*! @} */ /*! @name FETCHDECODE_HIDDENSTATUS_7 - Hidden status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusBusy_MASK (0x1U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusBusy_SHIFT (0U) /*! StatusBusy - Fetch unit is busy. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusBusy_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusBuffersIdle_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusRequest_MASK (0x20U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusRequest_SHIFT (5U) /*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusRequest_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusComplete_MASK (0x40U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusComplete_SHIFT (6U) /*! StatusComplete - Fetch unit completed all requested AXI transfers. */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_StatusComplete_MASK) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_ShadowStatus_MASK (0xFF00U) #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_ShadowStatus_SHIFT (8U) /*! ShadowStatus - Shadow load status for all layers (layer index = bit index). */ #define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_7_ShadowStatus_MASK) /*! @} */ /*! @name COLORPALETTE_7 - Color palette look up table. */ /*! @{ */ #define IRIS_MVPL_COLORPALETTE_7_ColorPalette_MASK (0xFFFFFFU) #define IRIS_MVPL_COLORPALETTE_7_ColorPalette_SHIFT (0U) /*! ColorPalette - Entry of the color palette look-up table */ #define IRIS_MVPL_COLORPALETTE_7_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COLORPALETTE_7_ColorPalette_SHIFT)) & IRIS_MVPL_COLORPALETTE_7_ColorPalette_MASK) /*! @} */ /*! @name FETCHECO1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO1_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHECO1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO1_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name FETCHECO1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHECO1_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHECO1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO1_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_FETCHECO1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHECO1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHECO1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO1_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHECO1_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHECO1_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHECO1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO1_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name FETCHECO1_STATICCONTROL - Common static control options. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_FETCHECO1_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_FETCHECO1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHECO1_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_FETCHECO1_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U) #define IRIS_MVPL_FETCHECO1_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U) /*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded * from shadow at start of each frame. This update is then executed independently from other RWS * type fields. ShdEn must be enabled for this mode. */ #define IRIS_MVPL_FETCHECO1_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHECO1_STATICCONTROL_BaseAddressAutoUpdate_MASK) /*! @} */ /*! @name FETCHECO1_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U) /*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of * 2. */ #define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK) #define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of * two may be specified as burst length. */ #define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK) #define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U) /*! LineMode - Fetch buffer cache control. * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_LineMode_MASK) /*! @} */ /*! @name FETCHECO1_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHECO1_BASEADDRESS0_BaseAddress0_SHIFT (0U) /*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit * BaseAddress[0] has to be 0. */ #define IRIS_MVPL_FETCHECO1_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHECO1_BASEADDRESS0_BaseAddress0_MASK) /*! @} */ /*! @name FETCHECO1_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU) #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U) /*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel * width of 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_Stride0_MASK) #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U) #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U) /*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or * 32. Exception: FetchEco does not support 18 and 24. */ #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK) /*! @} */ /*! @name FETCHECO1_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U) /*! LineWidth0 - Width of the source buffer of the layer in pixels minus one. */ #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineWidth0_MASK) #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U) /*! LineCount0 - Number of lines of the source buffer of the layer minus one. */ #define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineCount0_MASK) /*! @} */ /*! @name FETCHECO1_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U) /*! ComponentBitsAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U) /*! ComponentBitsBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U) /*! ComponentBitsGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U) /*! ComponentBitsRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U) /*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This * is compliant to ITU 656 standard. */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ITUFormat0_MASK) /*! @} */ /*! @name FETCHECO1_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U) /*! ComponentShiftAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U) /*! ComponentShiftBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U) /*! ComponentShiftGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U) #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U) /*! ComponentShiftRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK) /*! @} */ /*! @name FETCHECO1_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerXOffset0_SHIFT (0U) /*! LayerXOffset0 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerXOffset0_MASK) #define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerYOffset0_SHIFT (16U) /*! LayerYOffset0 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerYOffset0_MASK) /*! @} */ /*! @name FETCHECO1_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U) /*! ClipWindowXOffset0 - Horizontal position (X). */ #define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK) #define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U) /*! ClipWindowYOffset0 - Vertical position (Y). */ #define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK) /*! @} */ /*! @name FETCHECO1_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U) /*! ClipWindowWidth0 - Width. */ #define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK) #define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U) /*! ClipWindowHeight0 - Height. */ #define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK) /*! @} */ /*! @name FETCHECO1_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU) #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U) /*! ConstantAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantAlpha0_MASK) #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U) #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U) /*! ConstantBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantBlue0_MASK) #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U) #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U) /*! ConstantGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantGreen0_MASK) #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U) #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U) /*! ConstantRed0 - Red and Y (luma). */ #define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantRed0_MASK) /*! @} */ /*! @name FETCHECO1_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_TileMode0_MASK (0x30U) #define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_TileMode0_SHIFT (4U) /*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) * takes precedence if a pixel becomes subject to both tiling and clipping. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_TileMode0_MASK) #define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U) #define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U) /*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip * window get the clip color, pixels inside the source or tiling color. */ #define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_ClipWindowEnable0_MASK) #define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U) /*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling * color is used only (TileMode TILE_PAD not allowed). */ #define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_SourceBufferEnable0_MASK) /*! @} */ /*! @name FETCHECO1_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width minus one. */ #define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height minus one. */ #define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). If enabled, InputSelect must be set to INACTIVE. */ #define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name FETCHECO1_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartX_MASK (0x3FU) #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartX_SHIFT (0U) /*! StartX - X coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartX_MASK) #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartY_MASK (0xFC0U) #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartY_SHIFT (6U) /*! StartY - Y coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartY_MASK) #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaX_MASK (0x3F000U) #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaX_SHIFT (12U) /*! DeltaX - Increment of X coordinate for horizontal step in destination frame. */ #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaX_MASK) #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U) #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaY_SHIFT (18U) /*! DeltaY - Increment of Y coordinate for vertical step in destination frame. */ #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaY_MASK) #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U) #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_SwapDirection_SHIFT (24U) /*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied * for horizontal and DeltaX for vertical step on destination frame. */ #define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_SwapDirection_MASK) /*! @} */ /*! @name FETCHECO1_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_CONTROL_RawPixel_MASK (0x80U) #define IRIS_MVPL_FETCHECO1_CONTROL_RawPixel_SHIFT (7U) /*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced * for all layers by fixed values that allow passing the pixel data read from memory unchanged * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color * are deactived. Skip and Tile pixels are not affected by this setting. */ #define IRIS_MVPL_FETCHECO1_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHECO1_CONTROL_RawPixel_MASK) #define IRIS_MVPL_FETCHECO1_CONTROL_ClipColor_MASK (0x10000U) #define IRIS_MVPL_FETCHECO1_CONTROL_ClipColor_SHIFT (16U) /*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer. * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define IRIS_MVPL_FETCHECO1_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHECO1_CONTROL_ClipColor_MASK) /*! @} */ /*! @name FETCHECO1_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FETCHECO1_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_FETCHECO1_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHECO1_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name FETCHECO1_START - Frame start trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_START_Start_MASK (0x1U) #define IRIS_MVPL_FETCHECO1_START_Start_SHIFT (0U) /*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only). */ #define IRIS_MVPL_FETCHECO1_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_START_Start_SHIFT)) & IRIS_MVPL_FETCHECO1_START_Start_MASK) /*! @} */ /*! @name FETCHECO1_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_FETCHTYPE_FetchType_MASK (0xFU) #define IRIS_MVPL_FETCHECO1_FETCHTYPE_FetchType_SHIFT (0U) /*! FetchType - This field can be used to determine what kind of fetch unit this is. * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. */ #define IRIS_MVPL_FETCHECO1_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHECO1_FETCHTYPE_FetchType_MASK) /*! @} */ /*! @name FETCHECO1_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U) /*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface. */ #define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK) #define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U) #define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U) /*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. */ #define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name FETCHECO1_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Fetch unit is busy. */ #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBusy_MASK) #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle. */ #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBuffersIdle_MASK) #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusRequest_MASK (0x20U) #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusRequest_SHIFT (5U) /*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge. */ #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusRequest_MASK) #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusComplete_MASK (0x40U) #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusComplete_SHIFT (6U) /*! StatusComplete - Fetch unit completed all requested AXI transfers. */ #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusComplete_MASK) #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U) #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_ShadowStatus_SHIFT (8U) /*! ShadowStatus - Shadow load status for all layers (layer index = bit index). */ #define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHECO1_HIDDENSTATUS_ShadowStatus_MASK) /*! @} */ /*! @name FETCHLAYER0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHLAYER0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FETCHLAYER0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name FETCHLAYER0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name FETCHLAYER0_STATICCONTROL - Common static control options. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U) #define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U) /*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded * from shadow at start of each frame. This update is then executed independently from other RWS * type fields. ShdEn must be enabled for this mode. */ #define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHLAYER0_STATICCONTROL_BaseAddressAutoUpdate_MASK) #define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdLdReqSticky_MASK (0xFF000000U) #define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdLdReqSticky_SHIFT (24U) /*! ShdLdReqSticky - Shadow load request flags for each layer (always load). See description of * register TriggerEnable for further information. */ #define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdLdReqSticky(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdLdReqSticky_SHIFT)) & IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdLdReqSticky_MASK) /*! @} */ /*! @name FETCHLAYER0_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U) /*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of * 2. */ #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK) #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U) #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U) /*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers * * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of * two may be specified as burst length. */ #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK) #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U) /*! LineMode - Fetch buffer cache control. * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LineMode_MASK) /*! @} */ /*! @name FETCHLAYER0_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS0_BaseAddress0_SHIFT (0U) /*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit * BaseAddress[0] has to be 0. */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS0_BaseAddress0_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U) /*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel * width of 16 bit Stride has to be dividable by two and given minus one. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_Stride0_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U) /*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or * 32. Exception: FetchEco does not support 18 and 24. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U) /*! LineWidth0 - Width of the source buffer of the layer in pixels minus one. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineWidth0_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U) /*! LineCount0 - Number of lines of the source buffer of the layer minus one. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineCount0_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U) /*! ComponentBitsAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U) /*! ComponentBitsBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U) /*! ComponentBitsGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U) /*! ComponentBitsRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U) /*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This * is compliant to ITU 656 standard. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFormat0_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U) /*! ComponentShiftAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U) /*! ComponentShiftBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U) /*! ComponentShiftGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U) /*! ComponentShiftRed0 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerXOffset0_SHIFT (0U) /*! LayerXOffset0 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerXOffset0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerYOffset0_SHIFT (16U) /*! LayerYOffset0 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerYOffset0_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U) /*! ClipWindowXOffset0 - Horizontal position (X). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U) /*! ClipWindowYOffset0 - Vertical position (Y). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U) /*! ClipWindowWidth0 - Width. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U) /*! ClipWindowHeight0 - Height. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK) /*! @} */ /*! @name FETCHLAYER0_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U) /*! ConstantAlpha0 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantAlpha0_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U) /*! ConstantBlue0 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantBlue0_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U) /*! ConstantGreen0 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantGreen0_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U) /*! ConstantRed0 - Red and Y (luma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantRed0_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PaletteEnable0_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PaletteEnable0_SHIFT (0U) /*! PaletteEnable0 - Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower * bits of the lookup index are read from memory (PaletteIdxWidth), upper bits are set to index * of this layer. Palette output is extended by upper bits of index word read from memory (e.g. * to store alpha together with index). Result is mapped to color channels according to * ColorComponentBits/Shift settings. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PaletteEnable0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_TileMode0_MASK (0x30U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_TileMode0_SHIFT (4U) /*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0) * takes precedence if a pixel becomes subject to both tiling and clipping. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_TileMode0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U) /*! AlphaSrcEnable0 - Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U) /*! AlphaConstEnable0 - Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U) /*! AlphaTransEnable0 - Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U) /*! RGBAlphaSrcEnable0 - Value 1 enables source alpha (stored together with color component in the * source buffer) for RGB pre-multiply. When disabled source alpha is set to 1. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U) /*! RGBAlphaConstEnable0 - Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U) /*! RGBAlphaTransEnable0 - Value 1 enables transparent alpha (0 or 1 depending on RGB matching * ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U) /*! PremulConstRGB0 - When enabled (value 1) the values given by ConstantRed/Green/Blue are used * instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no * effect then. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PremulConstRGB0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U) /*! YUVConversionMode0 - Enables different kind of YUV to RGB conversions. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_YUVConversionMode0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U) /*! GammaRemoveEnable0 - Value 1 enables the stage to remove a gamma from RGB components. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_GammaRemoveEnable0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U) /*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip * window get the clip color, pixels inside the source or tiling color. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_ClipWindowEnable0_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U) /*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling * color is used only (TileMode TILE_PAD not allowed). */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_SourceBufferEnable0_MASK) /*! @} */ /*! @name FETCHLAYER0_BASEADDRESS1 - Source buffer base address of layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS1_BaseAddress1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS1_BaseAddress1_SHIFT (0U) /*! BaseAddress1 - See BaseAddress0. */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS1_BaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS1_BaseAddress1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS1_BaseAddress1_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES1 - Source buffer attributes for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_Stride1_MASK (0xFFFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT (0U) /*! Stride1 - See Stride0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_Stride1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_Stride1_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK (0x3F0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT (16U) /*! BitsPerPixel1 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION1 - Source buffer dimensions of layer 1, */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineWidth1_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT (0U) /*! LineWidth1 - See LineWidth0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineWidth1_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineCount1_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT (16U) /*! LineCount1 - See LineCount0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineCount1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineCount1_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTBITS1 - Size of color components for RGB, YUV and index formats (layer 1). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK (0xFU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT (0U) /*! ComponentBitsAlpha1 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK (0xF00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT (8U) /*! ComponentBitsBlue1 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK (0xF0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT (16U) /*! ComponentBitsGreen1 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK (0xF000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT (24U) /*! ComponentBitsRed1 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFormat1_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFormat1_SHIFT (31U) /*! ITUFormat1 - See ITUFormat0. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFormat1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFormat1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFormat1_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTSHIFT1 - Bit position of color components for RGB, YUV and index formats (layer 1). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK (0x1FU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT (0U) /*! ComponentShiftAlpha1 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK (0x1F00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT (8U) /*! ComponentShiftBlue1 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK (0x1F0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT (16U) /*! ComponentShiftGreen1 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK (0x1F000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT (24U) /*! ComponentShiftRed1 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYEROFFSET1 - Position of layer 1 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerXOffset1_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerXOffset1_SHIFT (0U) /*! LayerXOffset1 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerXOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerXOffset1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerYOffset1_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerYOffset1_SHIFT (16U) /*! LayerYOffset1 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerYOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerYOffset1_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWOFFSET1 - Clip window position for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT (0U) /*! ClipWindowXOffset1 - Horizontal position (X). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT (16U) /*! ClipWindowYOffset1 - Vertical position (Y). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS1 - Clip window size for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT (0U) /*! ClipWindowWidth1 - Width. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT (16U) /*! ClipWindowHeight1 - Height. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK) /*! @} */ /*! @name FETCHLAYER0_CONSTANTCOLOR1 - Constant color for layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantAlpha1_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantAlpha1_SHIFT (0U) /*! ConstantAlpha1 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantAlpha1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantAlpha1_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantBlue1_MASK (0xFF00U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantBlue1_SHIFT (8U) /*! ConstantBlue1 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantBlue1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantBlue1_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantGreen1_MASK (0xFF0000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantGreen1_SHIFT (16U) /*! ConstantGreen1 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantGreen1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantGreen1_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantRed1_MASK (0xFF000000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantRed1_SHIFT (24U) /*! ConstantRed1 - Red and Y (luma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantRed1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantRed1_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYERPROPERTY1 - Common properties of layer 1. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PaletteEnable1_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PaletteEnable1_SHIFT (0U) /*! PaletteEnable1 - See PaletteEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PaletteEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PaletteEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PaletteEnable1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_TileMode1_MASK (0x30U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_TileMode1_SHIFT (4U) /*! TileMode1 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_TileMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_TileMode1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_TileMode1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaSrcEnable1_MASK (0x100U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT (8U) /*! AlphaSrcEnable1 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaSrcEnable1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaConstEnable1_MASK (0x200U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaConstEnable1_SHIFT (9U) /*! AlphaConstEnable1 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaConstEnable1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaTransEnable1_MASK (0x800U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaTransEnable1_SHIFT (11U) /*! AlphaTransEnable1 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaTransEnable1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK (0x1000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT (12U) /*! RGBAlphaSrcEnable1 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK (0x2000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT (13U) /*! RGBAlphaConstEnable1 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK (0x8000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT (15U) /*! RGBAlphaTransEnable1 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PremulConstRGB1_MASK (0x10000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PremulConstRGB1_SHIFT (16U) /*! PremulConstRGB1 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PremulConstRGB1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PremulConstRGB1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PremulConstRGB1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_YUVConversionMode1_MASK (0x60000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_YUVConversionMode1_SHIFT (17U) /*! YUVConversionMode1 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_YUVConversionMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_YUVConversionMode1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_YUVConversionMode1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_GammaRemoveEnable1_MASK (0x100000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT (20U) /*! GammaRemoveEnable1 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_GammaRemoveEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_GammaRemoveEnable1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_ClipWindowEnable1_MASK (0x40000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_ClipWindowEnable1_SHIFT (30U) /*! ClipWindowEnable1 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_ClipWindowEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_ClipWindowEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_ClipWindowEnable1_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_SourceBufferEnable1_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_SourceBufferEnable1_SHIFT (31U) /*! SourceBufferEnable1 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_SourceBufferEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_SourceBufferEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_SourceBufferEnable1_MASK) /*! @} */ /*! @name FETCHLAYER0_BASEADDRESS2 - Source buffer base address of layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS2_BaseAddress2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS2_BaseAddress2_SHIFT (0U) /*! BaseAddress2 - See BaseAddress0. */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS2_BaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS2_BaseAddress2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS2_BaseAddress2_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES2 - Source buffer attributes for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_Stride2_MASK (0xFFFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT (0U) /*! Stride2 - See Stride0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_Stride2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_Stride2_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK (0x3F0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT (16U) /*! BitsPerPixel2 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION2 - Source buffer dimension of layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineWidth2_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT (0U) /*! LineWidth2 - See LineWidth0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineWidth2_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineCount2_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT (16U) /*! LineCount2 - See LineCount0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineCount2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineCount2_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTBITS2 - Size of color components for RGB, YUV and index formats (layer 2). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK (0xFU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT (0U) /*! ComponentBitsAlpha2 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK (0xF00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT (8U) /*! ComponentBitsBlue2 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK (0xF0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT (16U) /*! ComponentBitsGreen2 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK (0xF000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT (24U) /*! ComponentBitsRed2 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFormat2_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFormat2_SHIFT (31U) /*! ITUFormat2 - See ITUFormat0. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFormat2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFormat2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFormat2_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTSHIFT2 - Bit position of color components for RGB, YUV and index formats (layer 2). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK (0x1FU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT (0U) /*! ComponentShiftAlpha2 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK (0x1F00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT (8U) /*! ComponentShiftBlue2 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK (0x1F0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT (16U) /*! ComponentShiftGreen2 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK (0x1F000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT (24U) /*! ComponentShiftRed2 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYEROFFSET2 - Position of layer 2 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerXOffset2_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerXOffset2_SHIFT (0U) /*! LayerXOffset2 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerXOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerXOffset2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerYOffset2_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerYOffset2_SHIFT (16U) /*! LayerYOffset2 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerYOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerYOffset2_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWOFFSET2 - Clip window position for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT (0U) /*! ClipWindowXOffset2 - Horizontal position (X). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT (16U) /*! ClipWindowYOffset2 - Vertical position (Y). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS2 - Clip window size for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT (0U) /*! ClipWindowWidth2 - Width. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT (16U) /*! ClipWindowHeight2 - Height. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK) /*! @} */ /*! @name FETCHLAYER0_CONSTANTCOLOR2 - Constant color for layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantAlpha2_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantAlpha2_SHIFT (0U) /*! ConstantAlpha2 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantAlpha2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantAlpha2_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantBlue2_MASK (0xFF00U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantBlue2_SHIFT (8U) /*! ConstantBlue2 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantBlue2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantBlue2_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantGreen2_MASK (0xFF0000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantGreen2_SHIFT (16U) /*! ConstantGreen2 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantGreen2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantGreen2_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantRed2_MASK (0xFF000000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantRed2_SHIFT (24U) /*! ConstantRed2 - Red and Y (luma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantRed2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantRed2_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYERPROPERTY2 - Common properties of layer 2. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PaletteEnable2_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PaletteEnable2_SHIFT (0U) /*! PaletteEnable2 - See PaletteEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PaletteEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PaletteEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PaletteEnable2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_TileMode2_MASK (0x30U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_TileMode2_SHIFT (4U) /*! TileMode2 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_TileMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_TileMode2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_TileMode2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaSrcEnable2_MASK (0x100U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT (8U) /*! AlphaSrcEnable2 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaSrcEnable2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaConstEnable2_MASK (0x200U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaConstEnable2_SHIFT (9U) /*! AlphaConstEnable2 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaConstEnable2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaTransEnable2_MASK (0x800U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaTransEnable2_SHIFT (11U) /*! AlphaTransEnable2 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaTransEnable2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK (0x1000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT (12U) /*! RGBAlphaSrcEnable2 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK (0x2000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT (13U) /*! RGBAlphaConstEnable2 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK (0x8000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT (15U) /*! RGBAlphaTransEnable2 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PremulConstRGB2_MASK (0x10000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PremulConstRGB2_SHIFT (16U) /*! PremulConstRGB2 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PremulConstRGB2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PremulConstRGB2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PremulConstRGB2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_YUVConversionMode2_MASK (0x60000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_YUVConversionMode2_SHIFT (17U) /*! YUVConversionMode2 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_YUVConversionMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_YUVConversionMode2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_YUVConversionMode2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_GammaRemoveEnable2_MASK (0x100000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT (20U) /*! GammaRemoveEnable2 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_GammaRemoveEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_GammaRemoveEnable2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_ClipWindowEnable2_MASK (0x40000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_ClipWindowEnable2_SHIFT (30U) /*! ClipWindowEnable2 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_ClipWindowEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_ClipWindowEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_ClipWindowEnable2_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_SourceBufferEnable2_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_SourceBufferEnable2_SHIFT (31U) /*! SourceBufferEnable2 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_SourceBufferEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_SourceBufferEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_SourceBufferEnable2_MASK) /*! @} */ /*! @name FETCHLAYER0_BASEADDRESS3 - Source buffer base address of layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS3_BaseAddress3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS3_BaseAddress3_SHIFT (0U) /*! BaseAddress3 - See BaseAddress0. */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS3_BaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS3_BaseAddress3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS3_BaseAddress3_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES3 - Source buffer attributes for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_Stride3_MASK (0xFFFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT (0U) /*! Stride3 - See Stride0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_Stride3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_Stride3_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK (0x3F0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT (16U) /*! BitsPerPixel3 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION3 - Source buffer dimension of layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineWidth3_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT (0U) /*! LineWidth3 - See LineWidth0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineWidth3_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineCount3_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT (16U) /*! LineCount3 - See LineCount0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineCount3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineCount3_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTBITS3 - Size of color components for RGB, YUV and index formats (layer 3). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK (0xFU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT (0U) /*! ComponentBitsAlpha3 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK (0xF00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT (8U) /*! ComponentBitsBlue3 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK (0xF0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT (16U) /*! ComponentBitsGreen3 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK (0xF000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT (24U) /*! ComponentBitsRed3 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFormat3_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFormat3_SHIFT (31U) /*! ITUFormat3 - See ITUFormat0. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFormat3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFormat3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFormat3_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTSHIFT3 - Bit position of color components for RGB, YUV and index formats (layer 3). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK (0x1FU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT (0U) /*! ComponentShiftAlpha3 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK (0x1F00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT (8U) /*! ComponentShiftBlue3 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK (0x1F0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT (16U) /*! ComponentShiftGreen3 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK (0x1F000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT (24U) /*! ComponentShiftRed3 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYEROFFSET3 - Position of layer 3 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerXOffset3_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerXOffset3_SHIFT (0U) /*! LayerXOffset3 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerXOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerXOffset3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerYOffset3_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerYOffset3_SHIFT (16U) /*! LayerYOffset3 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerYOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerYOffset3_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWOFFSET3 - Clip window position for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT (0U) /*! ClipWindowXOffset3 - Horizontal position (X). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT (16U) /*! ClipWindowYOffset3 - Vertical position (Y). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS3 - Clip window size for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT (0U) /*! ClipWindowWidth3 - Width. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT (16U) /*! ClipWindowHeight3 - Height. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK) /*! @} */ /*! @name FETCHLAYER0_CONSTANTCOLOR3 - Constant color for layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantAlpha3_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantAlpha3_SHIFT (0U) /*! ConstantAlpha3 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantAlpha3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantAlpha3_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantBlue3_MASK (0xFF00U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantBlue3_SHIFT (8U) /*! ConstantBlue3 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantBlue3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantBlue3_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantGreen3_MASK (0xFF0000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantGreen3_SHIFT (16U) /*! ConstantGreen3 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantGreen3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantGreen3_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantRed3_MASK (0xFF000000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantRed3_SHIFT (24U) /*! ConstantRed3 - Red and Y (luma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantRed3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantRed3_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYERPROPERTY3 - Common properties of layer 3. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PaletteEnable3_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PaletteEnable3_SHIFT (0U) /*! PaletteEnable3 - See PaletteEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PaletteEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PaletteEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PaletteEnable3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_TileMode3_MASK (0x30U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_TileMode3_SHIFT (4U) /*! TileMode3 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_TileMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_TileMode3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_TileMode3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaSrcEnable3_MASK (0x100U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT (8U) /*! AlphaSrcEnable3 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaSrcEnable3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaConstEnable3_MASK (0x200U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaConstEnable3_SHIFT (9U) /*! AlphaConstEnable3 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaConstEnable3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaTransEnable3_MASK (0x800U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaTransEnable3_SHIFT (11U) /*! AlphaTransEnable3 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaTransEnable3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK (0x1000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT (12U) /*! RGBAlphaSrcEnable3 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK (0x2000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT (13U) /*! RGBAlphaConstEnable3 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK (0x8000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT (15U) /*! RGBAlphaTransEnable3 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PremulConstRGB3_MASK (0x10000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PremulConstRGB3_SHIFT (16U) /*! PremulConstRGB3 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PremulConstRGB3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PremulConstRGB3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PremulConstRGB3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_YUVConversionMode3_MASK (0x60000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_YUVConversionMode3_SHIFT (17U) /*! YUVConversionMode3 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_YUVConversionMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_YUVConversionMode3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_YUVConversionMode3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_GammaRemoveEnable3_MASK (0x100000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT (20U) /*! GammaRemoveEnable3 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_GammaRemoveEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_GammaRemoveEnable3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_ClipWindowEnable3_MASK (0x40000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_ClipWindowEnable3_SHIFT (30U) /*! ClipWindowEnable3 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_ClipWindowEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_ClipWindowEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_ClipWindowEnable3_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_SourceBufferEnable3_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_SourceBufferEnable3_SHIFT (31U) /*! SourceBufferEnable3 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_SourceBufferEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_SourceBufferEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_SourceBufferEnable3_MASK) /*! @} */ /*! @name FETCHLAYER0_BASEADDRESS4 - Source buffer base address of layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS4_BaseAddress4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS4_BaseAddress4_SHIFT (0U) /*! BaseAddress4 - See BaseAddress0. */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS4_BaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS4_BaseAddress4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS4_BaseAddress4_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES4 - Source buffer attributes for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_Stride4_MASK (0xFFFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT (0U) /*! Stride4 - See Stride0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_Stride4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_Stride4_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK (0x3F0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT (16U) /*! BitsPerPixel4 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION4 - Source buffer dimension of layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineWidth4_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT (0U) /*! LineWidth4 - See LineWidth0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineWidth4_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineCount4_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT (16U) /*! LineCount4 - See LineCount0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineCount4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineCount4_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTBITS4 - Size of color components for RGB, YUV and index formats (layer 4). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK (0xFU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT (0U) /*! ComponentBitsAlpha4 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK (0xF00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT (8U) /*! ComponentBitsBlue4 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK (0xF0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT (16U) /*! ComponentBitsGreen4 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK (0xF000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT (24U) /*! ComponentBitsRed4 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFormat4_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFormat4_SHIFT (31U) /*! ITUFormat4 - See ITUFormat0. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFormat4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFormat4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFormat4_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTSHIFT4 - Bit position of color components for RGB, YUV and index formats (layer 4). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK (0x1FU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT (0U) /*! ComponentShiftAlpha4 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK (0x1F00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT (8U) /*! ComponentShiftBlue4 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK (0x1F0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT (16U) /*! ComponentShiftGreen4 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK (0x1F000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT (24U) /*! ComponentShiftRed4 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYEROFFSET4 - Position of layer 4 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerXOffset4_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerXOffset4_SHIFT (0U) /*! LayerXOffset4 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerXOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerXOffset4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerYOffset4_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerYOffset4_SHIFT (16U) /*! LayerYOffset4 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerYOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerYOffset4_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWOFFSET4 - Clip window position for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT (0U) /*! ClipWindowXOffset4 - Horizontal position (X). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT (16U) /*! ClipWindowYOffset4 - Vertical position (Y). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS4 - Clip window size for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT (0U) /*! ClipWindowWidth4 - Width. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT (16U) /*! ClipWindowHeight4 - Height. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK) /*! @} */ /*! @name FETCHLAYER0_CONSTANTCOLOR4 - Constant color for layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantAlpha4_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantAlpha4_SHIFT (0U) /*! ConstantAlpha4 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantAlpha4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantAlpha4_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantBlue4_MASK (0xFF00U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantBlue4_SHIFT (8U) /*! ConstantBlue4 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantBlue4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantBlue4_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantGreen4_MASK (0xFF0000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantGreen4_SHIFT (16U) /*! ConstantGreen4 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantGreen4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantGreen4_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantRed4_MASK (0xFF000000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantRed4_SHIFT (24U) /*! ConstantRed4 - Red and Y (luma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantRed4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantRed4_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYERPROPERTY4 - Common properties of layer 4. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PaletteEnable4_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PaletteEnable4_SHIFT (0U) /*! PaletteEnable4 - See PaletteEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PaletteEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PaletteEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PaletteEnable4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_TileMode4_MASK (0x30U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_TileMode4_SHIFT (4U) /*! TileMode4 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_TileMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_TileMode4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_TileMode4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaSrcEnable4_MASK (0x100U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT (8U) /*! AlphaSrcEnable4 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaSrcEnable4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaConstEnable4_MASK (0x200U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaConstEnable4_SHIFT (9U) /*! AlphaConstEnable4 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaConstEnable4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaTransEnable4_MASK (0x800U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaTransEnable4_SHIFT (11U) /*! AlphaTransEnable4 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaTransEnable4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK (0x1000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT (12U) /*! RGBAlphaSrcEnable4 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK (0x2000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT (13U) /*! RGBAlphaConstEnable4 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK (0x8000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT (15U) /*! RGBAlphaTransEnable4 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PremulConstRGB4_MASK (0x10000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PremulConstRGB4_SHIFT (16U) /*! PremulConstRGB4 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PremulConstRGB4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PremulConstRGB4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PremulConstRGB4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_YUVConversionMode4_MASK (0x60000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_YUVConversionMode4_SHIFT (17U) /*! YUVConversionMode4 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_YUVConversionMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_YUVConversionMode4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_YUVConversionMode4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_GammaRemoveEnable4_MASK (0x100000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT (20U) /*! GammaRemoveEnable4 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_GammaRemoveEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_GammaRemoveEnable4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_ClipWindowEnable4_MASK (0x40000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_ClipWindowEnable4_SHIFT (30U) /*! ClipWindowEnable4 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_ClipWindowEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_ClipWindowEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_ClipWindowEnable4_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_SourceBufferEnable4_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_SourceBufferEnable4_SHIFT (31U) /*! SourceBufferEnable4 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_SourceBufferEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_SourceBufferEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_SourceBufferEnable4_MASK) /*! @} */ /*! @name FETCHLAYER0_BASEADDRESS5 - Source buffer base address of layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS5_BaseAddress5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS5_BaseAddress5_SHIFT (0U) /*! BaseAddress5 - See BaseAddress0. */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS5_BaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS5_BaseAddress5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS5_BaseAddress5_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES5 - Source buffer attributes for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_Stride5_MASK (0xFFFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT (0U) /*! Stride5 - See Stride0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_Stride5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_Stride5_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK (0x3F0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT (16U) /*! BitsPerPixel5 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION5 - Source buffer dimension of layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineWidth5_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT (0U) /*! LineWidth5 - See LineWidth0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineWidth5_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineCount5_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT (16U) /*! LineCount5 - See LineCount0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineCount5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineCount5_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTBITS5 - Size of color components for RGB, YUV and index formats (layer 5). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK (0xFU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT (0U) /*! ComponentBitsAlpha5 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK (0xF00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT (8U) /*! ComponentBitsBlue5 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK (0xF0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT (16U) /*! ComponentBitsGreen5 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK (0xF000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT (24U) /*! ComponentBitsRed5 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFormat5_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFormat5_SHIFT (31U) /*! ITUFormat5 - See ITUFormat0. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFormat5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFormat5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFormat5_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTSHIFT5 - Bit position of color components for RGB, YUV and index formats (layer 5). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK (0x1FU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT (0U) /*! ComponentShiftAlpha5 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK (0x1F00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT (8U) /*! ComponentShiftBlue5 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK (0x1F0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT (16U) /*! ComponentShiftGreen5 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK (0x1F000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT (24U) /*! ComponentShiftRed5 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYEROFFSET5 - Position of layer 5 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerXOffset5_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerXOffset5_SHIFT (0U) /*! LayerXOffset5 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerXOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerXOffset5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerYOffset5_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerYOffset5_SHIFT (16U) /*! LayerYOffset5 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerYOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerYOffset5_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWOFFSET5 - Clip window position for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT (0U) /*! ClipWindowXOffset5 - Horizontal position (X). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT (16U) /*! ClipWindowYOffset5 - Vertical position (Y). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS5 - Clip window size for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT (0U) /*! ClipWindowWidth5 - Width. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT (16U) /*! ClipWindowHeight5 - Height. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK) /*! @} */ /*! @name FETCHLAYER0_CONSTANTCOLOR5 - Constant color for layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantAlpha5_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantAlpha5_SHIFT (0U) /*! ConstantAlpha5 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantAlpha5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantAlpha5_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantBlue5_MASK (0xFF00U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantBlue5_SHIFT (8U) /*! ConstantBlue5 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantBlue5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantBlue5_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantGreen5_MASK (0xFF0000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantGreen5_SHIFT (16U) /*! ConstantGreen5 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantGreen5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantGreen5_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantRed5_MASK (0xFF000000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantRed5_SHIFT (24U) /*! ConstantRed5 - Red and Y (luma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantRed5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantRed5_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYERPROPERTY5 - Common properties of layer 5. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PaletteEnable5_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PaletteEnable5_SHIFT (0U) /*! PaletteEnable5 - See PaletteEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PaletteEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PaletteEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PaletteEnable5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_TileMode5_MASK (0x30U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_TileMode5_SHIFT (4U) /*! TileMode5 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_TileMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_TileMode5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_TileMode5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaSrcEnable5_MASK (0x100U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT (8U) /*! AlphaSrcEnable5 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaSrcEnable5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaConstEnable5_MASK (0x200U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaConstEnable5_SHIFT (9U) /*! AlphaConstEnable5 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaConstEnable5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaTransEnable5_MASK (0x800U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaTransEnable5_SHIFT (11U) /*! AlphaTransEnable5 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaTransEnable5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK (0x1000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT (12U) /*! RGBAlphaSrcEnable5 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK (0x2000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT (13U) /*! RGBAlphaConstEnable5 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK (0x8000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT (15U) /*! RGBAlphaTransEnable5 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PremulConstRGB5_MASK (0x10000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PremulConstRGB5_SHIFT (16U) /*! PremulConstRGB5 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PremulConstRGB5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PremulConstRGB5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PremulConstRGB5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_YUVConversionMode5_MASK (0x60000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_YUVConversionMode5_SHIFT (17U) /*! YUVConversionMode5 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_YUVConversionMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_YUVConversionMode5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_YUVConversionMode5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_GammaRemoveEnable5_MASK (0x100000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT (20U) /*! GammaRemoveEnable5 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_GammaRemoveEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_GammaRemoveEnable5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_ClipWindowEnable5_MASK (0x40000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_ClipWindowEnable5_SHIFT (30U) /*! ClipWindowEnable5 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_ClipWindowEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_ClipWindowEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_ClipWindowEnable5_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_SourceBufferEnable5_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_SourceBufferEnable5_SHIFT (31U) /*! SourceBufferEnable5 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_SourceBufferEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_SourceBufferEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_SourceBufferEnable5_MASK) /*! @} */ /*! @name FETCHLAYER0_BASEADDRESS6 - Source buffer base address of layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS6_BaseAddress6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS6_BaseAddress6_SHIFT (0U) /*! BaseAddress6 - See BaseAddress0. */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS6_BaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS6_BaseAddress6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS6_BaseAddress6_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES6 - Source buffer attributes for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_Stride6_MASK (0xFFFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT (0U) /*! Stride6 - See Stride0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_Stride6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_Stride6_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK (0x3F0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT (16U) /*! BitsPerPixel6 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION6 - Source buffer dimension of layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineWidth6_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT (0U) /*! LineWidth6 - See LineWidth0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineWidth6_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineCount6_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT (16U) /*! LineCount6 - See LineCount0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineCount6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineCount6_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTBITS6 - Size of color components for RGB, YUV and index formats (layer 6). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK (0xFU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT (0U) /*! ComponentBitsAlpha6 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK (0xF00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT (8U) /*! ComponentBitsBlue6 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK (0xF0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT (16U) /*! ComponentBitsGreen6 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK (0xF000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT (24U) /*! ComponentBitsRed6 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFormat6_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFormat6_SHIFT (31U) /*! ITUFormat6 - See ITUFormat0. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFormat6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFormat6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFormat6_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTSHIFT6 - Bit position of color components for RGB, YUV and index formats (layer 6). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK (0x1FU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT (0U) /*! ComponentShiftAlpha6 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK (0x1F00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT (8U) /*! ComponentShiftBlue6 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK (0x1F0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT (16U) /*! ComponentShiftGreen6 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK (0x1F000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT (24U) /*! ComponentShiftRed6 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYEROFFSET6 - Position of layer 1 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerXOffset6_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerXOffset6_SHIFT (0U) /*! LayerXOffset6 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerXOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerXOffset6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerYOffset6_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerYOffset6_SHIFT (16U) /*! LayerYOffset6 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerYOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerYOffset6_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWOFFSET6 - Clip window position for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT (0U) /*! ClipWindowXOffset6 - Horizontal position (X). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT (16U) /*! ClipWindowYOffset6 - Vertical position (Y). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS6 - Clip window size for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT (0U) /*! ClipWindowWidth6 - Width. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT (16U) /*! ClipWindowHeight6 - Height. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK) /*! @} */ /*! @name FETCHLAYER0_CONSTANTCOLOR6 - Constant color for layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantAlpha6_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantAlpha6_SHIFT (0U) /*! ConstantAlpha6 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantAlpha6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantAlpha6_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantBlue6_MASK (0xFF00U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantBlue6_SHIFT (8U) /*! ConstantBlue6 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantBlue6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantBlue6_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantGreen6_MASK (0xFF0000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantGreen6_SHIFT (16U) /*! ConstantGreen6 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantGreen6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantGreen6_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantRed6_MASK (0xFF000000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantRed6_SHIFT (24U) /*! ConstantRed6 - Red and Y (luma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantRed6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantRed6_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYERPROPERTY6 - Common properties of layer 6. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PaletteEnable6_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PaletteEnable6_SHIFT (0U) /*! PaletteEnable6 - See PaletteEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PaletteEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PaletteEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PaletteEnable6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_TileMode6_MASK (0x30U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_TileMode6_SHIFT (4U) /*! TileMode6 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_TileMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_TileMode6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_TileMode6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaSrcEnable6_MASK (0x100U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT (8U) /*! AlphaSrcEnable6 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaSrcEnable6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaConstEnable6_MASK (0x200U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaConstEnable6_SHIFT (9U) /*! AlphaConstEnable6 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaConstEnable6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaTransEnable6_MASK (0x800U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaTransEnable6_SHIFT (11U) /*! AlphaTransEnable6 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaTransEnable6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK (0x1000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT (12U) /*! RGBAlphaSrcEnable6 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK (0x2000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT (13U) /*! RGBAlphaConstEnable6 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK (0x8000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT (15U) /*! RGBAlphaTransEnable6 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PremulConstRGB6_MASK (0x10000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PremulConstRGB6_SHIFT (16U) /*! PremulConstRGB6 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PremulConstRGB6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PremulConstRGB6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PremulConstRGB6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_YUVConversionMode6_MASK (0x60000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_YUVConversionMode6_SHIFT (17U) /*! YUVConversionMode6 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_YUVConversionMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_YUVConversionMode6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_YUVConversionMode6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_GammaRemoveEnable6_MASK (0x100000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT (20U) /*! GammaRemoveEnable6 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_GammaRemoveEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_GammaRemoveEnable6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_ClipWindowEnable6_MASK (0x40000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_ClipWindowEnable6_SHIFT (30U) /*! ClipWindowEnable6 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_ClipWindowEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_ClipWindowEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_ClipWindowEnable6_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_SourceBufferEnable6_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_SourceBufferEnable6_SHIFT (31U) /*! SourceBufferEnable6 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_SourceBufferEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_SourceBufferEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_SourceBufferEnable6_MASK) /*! @} */ /*! @name FETCHLAYER0_BASEADDRESS7 - Source buffer base address of layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS7_BaseAddress7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS7_BaseAddress7_SHIFT (0U) /*! BaseAddress7 - See BaseAddress0. */ #define IRIS_MVPL_FETCHLAYER0_BASEADDRESS7_BaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS7_BaseAddress7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS7_BaseAddress7_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES7 - Source buffer stride for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_Stride7_MASK (0xFFFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT (0U) /*! Stride7 - See Stride0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_Stride7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_Stride7_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK (0x3F0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT (16U) /*! BitsPerPixel7 - See BitsPerPixel0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK) /*! @} */ /*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION7 - Source buffer dimension of layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineWidth7_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT (0U) /*! LineWidth7 - See LineWidth0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineWidth7_MASK) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineCount7_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT (16U) /*! LineCount7 - See LineCount0. */ #define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineCount7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineCount7_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTBITS7 - Size of color components for RGB, YUV and index formats (layer 7). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK (0xFU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT (0U) /*! ComponentBitsAlpha7 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK (0xF00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT (8U) /*! ComponentBitsBlue7 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK (0xF0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT (16U) /*! ComponentBitsGreen7 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK (0xF000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT (24U) /*! ComponentBitsRed7 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFormat7_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFormat7_SHIFT (31U) /*! ITUFormat7 - See ITUFormat0. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFormat7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFormat7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFormat7_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORCOMPONENTSHIFT7 - Bit position of color components for RGB, YUV and index formats (layer 7). */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK (0x1FU) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT (0U) /*! ComponentShiftAlpha7 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK (0x1F00U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT (8U) /*! ComponentShiftBlue7 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK (0x1F0000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT (16U) /*! ComponentShiftGreen7 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK (0x1F000000U) #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT (24U) /*! ComponentShiftRed7 - Red, Y (luma) and palette index. */ #define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYEROFFSET7 - Position of layer 7 within the destination frame. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerXOffset7_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerXOffset7_SHIFT (0U) /*! LayerXOffset7 - Horizontal offset (X). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerXOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerXOffset7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerYOffset7_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerYOffset7_SHIFT (16U) /*! LayerYOffset7 - Vertical offset (Y). */ #define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerYOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerYOffset7_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWOFFSET7 - Clip window position for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK (0x7FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT (0U) /*! ClipWindowXOffset7 - Horizontal position (X). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK (0x7FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT (16U) /*! ClipWindowYOffset7 - Vertical position (Y). */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK) /*! @} */ /*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS7 - Clip window size for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT (0U) /*! ClipWindowWidth7 - Width. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT (16U) /*! ClipWindowHeight7 - Height. */ #define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK) /*! @} */ /*! @name FETCHLAYER0_CONSTANTCOLOR7 - Constant color for layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantAlpha7_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantAlpha7_SHIFT (0U) /*! ConstantAlpha7 - Alpha. */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantAlpha7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantAlpha7_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantBlue7_MASK (0xFF00U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantBlue7_SHIFT (8U) /*! ConstantBlue7 - Blue and V (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantBlue7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantBlue7_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantGreen7_MASK (0xFF0000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantGreen7_SHIFT (16U) /*! ConstantGreen7 - Green and U (chroma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantGreen7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantGreen7_MASK) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantRed7_MASK (0xFF000000U) #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantRed7_SHIFT (24U) /*! ConstantRed7 - Red and Y (luma). */ #define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantRed7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantRed7_MASK) /*! @} */ /*! @name FETCHLAYER0_LAYERPROPERTY7 - Common properties of layer 7. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PaletteEnable7_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PaletteEnable7_SHIFT (0U) /*! PaletteEnable7 - See PaletteEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PaletteEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PaletteEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PaletteEnable7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_TileMode7_MASK (0x30U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_TileMode7_SHIFT (4U) /*! TileMode7 - See TileMode0. * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_TileMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_TileMode7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_TileMode7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaSrcEnable7_MASK (0x100U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT (8U) /*! AlphaSrcEnable7 - See AlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaSrcEnable7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaConstEnable7_MASK (0x200U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaConstEnable7_SHIFT (9U) /*! AlphaConstEnable7 - See AlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaConstEnable7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaTransEnable7_MASK (0x800U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaTransEnable7_SHIFT (11U) /*! AlphaTransEnable7 - See AlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaTransEnable7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK (0x1000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT (12U) /*! RGBAlphaSrcEnable7 - See RGBAlphaSrcSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK (0x2000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT (13U) /*! RGBAlphaConstEnable7 - See RGBAlphaConstSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK (0x8000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT (15U) /*! RGBAlphaTransEnable7 - See RGBAlphaTransSelect0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PremulConstRGB7_MASK (0x10000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PremulConstRGB7_SHIFT (16U) /*! PremulConstRGB7 - See PremulConstRGB0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PremulConstRGB7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PremulConstRGB7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PremulConstRGB7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_YUVConversionMode7_MASK (0x60000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_YUVConversionMode7_SHIFT (17U) /*! YUVConversionMode7 - See YUVConversionMode0. * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_YUVConversionMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_YUVConversionMode7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_YUVConversionMode7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_GammaRemoveEnable7_MASK (0x100000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT (20U) /*! GammaRemoveEnable7 - See GammaRemoveEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_GammaRemoveEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_GammaRemoveEnable7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_ClipWindowEnable7_MASK (0x40000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_ClipWindowEnable7_SHIFT (30U) /*! ClipWindowEnable7 - See ClipWindowEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_ClipWindowEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_ClipWindowEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_ClipWindowEnable7_MASK) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_SourceBufferEnable7_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_SourceBufferEnable7_SHIFT (31U) /*! SourceBufferEnable7 - See SourceBufferEnable0. */ #define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_SourceBufferEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_SourceBufferEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_SourceBufferEnable7_MASK) /*! @} */ /*! @name FETCHLAYER0_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU) #define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U) /*! FrameWidth - Frame width minus one. */ #define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameWidth_MASK) #define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U) #define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U) /*! FrameHeight - Frame height minus one. */ #define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameHeight_MASK) #define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U) #define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U) /*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then. * Can be used to load shadows or to generate synchronization signals only (frame/sequence * complete). If enabled, InputSelect must be set to INACTIVE. */ #define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_EmptyFrame_MASK) /*! @} */ /*! @name FETCHLAYER0_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartX_MASK (0x3FU) #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartX_SHIFT (0U) /*! StartX - X coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartX_MASK) #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartY_MASK (0xFC0U) #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartY_SHIFT (6U) /*! StartY - Y coordinate of first sample point relative to origin. */ #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartY_MASK) #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaX_MASK (0x3F000U) #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaX_SHIFT (12U) /*! DeltaX - Increment of X coordinate for horizontal step in destination frame. */ #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaX_MASK) #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U) #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaY_SHIFT (18U) /*! DeltaY - Increment of Y coordinate for vertical step in destination frame. */ #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaY_MASK) #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U) #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_SwapDirection_SHIFT (24U) /*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied * for horizontal and DeltaX for vertical step on destination frame. */ #define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_SwapDirection_MASK) /*! @} */ /*! @name FETCHLAYER0_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CONTROL_RawPixel_MASK (0x80U) #define IRIS_MVPL_FETCHLAYER0_CONTROL_RawPixel_SHIFT (7U) /*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced * for all layers by fixed values that allow passing the pixel data read from memory unchanged * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color * are deactived. Skip and Tile pixels are not affected by this setting. */ #define IRIS_MVPL_FETCHLAYER0_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONTROL_RawPixel_MASK) #define IRIS_MVPL_FETCHLAYER0_CONTROL_PaletteIdxWidth_MASK (0x700U) #define IRIS_MVPL_FETCHLAYER0_CONTROL_PaletteIdxWidth_SHIFT (8U) /*! PaletteIdxWidth - Number minus one of least significant bits of pixel data read from the source * buffer that are used as index value for color palette look-up. */ #define IRIS_MVPL_FETCHLAYER0_CONTROL_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONTROL_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONTROL_PaletteIdxWidth_MASK) #define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipColor_MASK (0x10000U) #define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipColor_SHIFT (16U) /*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer. * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONTROL_ClipColor_MASK) #define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipLayer_MASK (0xE0000U) #define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipLayer_SHIFT (17U) /*! ClipLayer - Index of the layer which is used to fill the clipping area of the frame layout when * ClipColor is set to LAYER. The selected layer must be enabled (LayerEnable). */ #define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipLayer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONTROL_ClipLayer_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONTROL_ClipLayer_MASK) /*! @} */ /*! @name FETCHLAYER0_TRIGGERENABLE - Shadow load enable flags for all layers. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_TRIGGERENABLE_ShdLdReq_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_TRIGGERENABLE_ShdLdReq_SHIFT (0U) /*! ShdLdReq - Shadow load request flags for each layer (one time load). */ #define IRIS_MVPL_FETCHLAYER0_TRIGGERENABLE_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_TRIGGERENABLE_ShdLdReq_SHIFT)) & IRIS_MVPL_FETCHLAYER0_TRIGGERENABLE_ShdLdReq_MASK) /*! @} */ /*! @name FETCHLAYER0_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_CONTROLTRIGGER_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_CONTROLTRIGGER_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with * the next start of frame and send a shadow load token to subsequent units. */ #define IRIS_MVPL_FETCHLAYER0_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONTROLTRIGGER_ShdTokGen_MASK) /*! @} */ /*! @name FETCHLAYER0_START - Frame start trigger. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_START_Start_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_START_Start_SHIFT (0U) /*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only). */ #define IRIS_MVPL_FETCHLAYER0_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_START_Start_SHIFT)) & IRIS_MVPL_FETCHLAYER0_START_Start_MASK) /*! @} */ /*! @name FETCHLAYER0_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_FETCHTYPE_FetchType_MASK (0xFU) #define IRIS_MVPL_FETCHLAYER0_FETCHTYPE_FetchType_SHIFT (0U) /*! FetchType - This field can be used to determine what kind of fetch unit this is. * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. */ #define IRIS_MVPL_FETCHLAYER0_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FETCHTYPE_FetchType_MASK) /*! @} */ /*! @name FETCHLAYER0_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU) #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U) /*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface. */ #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK) #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U) #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U) /*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used. */ #define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name FETCHLAYER0_STATUS - Status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_STATUS_WriteTimeout_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_STATUS_WriteTimeout_SHIFT (0U) /*! WriteTimeout - Timeout detected when writing to the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHLAYER0_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHLAYER0_STATUS_WriteTimeout_MASK) #define IRIS_MVPL_FETCHLAYER0_STATUS_ReadTimeout_MASK (0x10U) #define IRIS_MVPL_FETCHLAYER0_STATUS_ReadTimeout_SHIFT (4U) /*! ReadTimeout - Timeout detected when reading from the palette entries or shadow token trigger * enables in fetchlayer derivate. Write 1 to clear. */ #define IRIS_MVPL_FETCHLAYER0_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHLAYER0_STATUS_ReadTimeout_MASK) /*! @} */ /*! @name FETCHLAYER0_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBusy_MASK (0x1U) #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBusy_SHIFT (0U) /*! StatusBusy - Fetch unit is busy. */ #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBusy_MASK) #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U) #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U) /*! StatusBuffersIdle - AXI interface buffers are idle. */ #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBuffersIdle_MASK) #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusRequest_MASK (0x20U) #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusRequest_SHIFT (5U) /*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge. */ #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusRequest_MASK) #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusComplete_MASK (0x40U) #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusComplete_SHIFT (6U) /*! StatusComplete - Fetch unit completed all requested AXI transfers. */ #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusComplete_MASK) #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U) #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_ShadowStatus_SHIFT (8U) /*! ShadowStatus - Shadow load status for all layers (layer index = bit index). */ #define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_ShadowStatus_MASK) /*! @} */ /*! @name FETCHLAYER0_COLORPALETTE - Color palette look up table. */ /*! @{ */ #define IRIS_MVPL_FETCHLAYER0_COLORPALETTE_ColorPalette_MASK (0xFFFFFFU) #define IRIS_MVPL_FETCHLAYER0_COLORPALETTE_ColorPalette_SHIFT (0U) /*! ColorPalette - Entry of the color palette look-up table */ #define IRIS_MVPL_FETCHLAYER0_COLORPALETTE_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORPALETTE_ColorPalette_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORPALETTE_ColorPalette_MASK) /*! @} */ /*! @name MATRIX4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX4_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_MATRIX4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX4_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name MATRIX4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_MATRIX4_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_MATRIX4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX4_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_MATRIX4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_MATRIX4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_MATRIX4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX4_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_MATRIX4_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_MATRIX4_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_MATRIX4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX4_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name MATRIX4_STATICCONTROL - Color Matrix static control register */ /*! @{ */ #define IRIS_MVPL_MATRIX4_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_MATRIX4_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_MATRIX4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX4_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name MATRIX4_CONTROL - Color Matrix control register */ /*! @{ */ #define IRIS_MVPL_MATRIX4_CONTROL_MODE_MASK (0x3U) #define IRIS_MVPL_MATRIX4_CONTROL_MODE_SHIFT (0U) /*! MODE - Operation mode for color matrix * 0b00..Module in neutral mode, input data is bypassed * 0b01..Module in matrix mode, input data is multiplied with matrix values * 0b10..Module in alpha pre-multiplication mode, input color is multiplied with input alpha * 0b11..Reserved, do not use */ #define IRIS_MVPL_MATRIX4_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX4_CONTROL_MODE_MASK) #define IRIS_MVPL_MATRIX4_CONTROL_AlphaMask_MASK (0x10U) #define IRIS_MVPL_MATRIX4_CONTROL_AlphaMask_SHIFT (4U) /*! AlphaMask - Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value * smaller than 0.5 are by-passed unchanged. */ #define IRIS_MVPL_MATRIX4_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX4_CONTROL_AlphaMask_MASK) #define IRIS_MVPL_MATRIX4_CONTROL_AlphaInvert_MASK (0x20U) #define IRIS_MVPL_MATRIX4_CONTROL_AlphaInvert_SHIFT (5U) /*! AlphaInvert - Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha * value greater or equal 0.5 are by-passed). */ #define IRIS_MVPL_MATRIX4_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX4_CONTROL_AlphaInvert_MASK) /*! @} */ /*! @name MATRIX4_RED0 - Matrix values for calculation of the red output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_RED0_A11_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX4_RED0_A11_SHIFT (0U) /*! A11 - Value for red input. */ #define IRIS_MVPL_MATRIX4_RED0_A11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX4_RED0_A11_MASK) #define IRIS_MVPL_MATRIX4_RED0_A12_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX4_RED0_A12_SHIFT (16U) /*! A12 - Value for green input. */ #define IRIS_MVPL_MATRIX4_RED0_A12(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX4_RED0_A12_MASK) /*! @} */ /*! @name MATRIX4_RED1 - Matrix values for calculation of the red output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_RED1_A13_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX4_RED1_A13_SHIFT (0U) /*! A13 - Value for blue input. */ #define IRIS_MVPL_MATRIX4_RED1_A13(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX4_RED1_A13_MASK) #define IRIS_MVPL_MATRIX4_RED1_A14_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX4_RED1_A14_SHIFT (16U) /*! A14 - Value for alpha input. */ #define IRIS_MVPL_MATRIX4_RED1_A14(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX4_RED1_A14_MASK) /*! @} */ /*! @name MATRIX4_GREEN0 - Matrix values for calculation of the green output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_GREEN0_A21_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX4_GREEN0_A21_SHIFT (0U) /*! A21 - Value for red input. */ #define IRIS_MVPL_MATRIX4_GREEN0_A21(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX4_GREEN0_A21_MASK) #define IRIS_MVPL_MATRIX4_GREEN0_A22_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX4_GREEN0_A22_SHIFT (16U) /*! A22 - Value for green input. */ #define IRIS_MVPL_MATRIX4_GREEN0_A22(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX4_GREEN0_A22_MASK) /*! @} */ /*! @name MATRIX4_GREEN1 - Matrix values for calculation of the green output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_GREEN1_A23_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX4_GREEN1_A23_SHIFT (0U) /*! A23 - Value for blue input. */ #define IRIS_MVPL_MATRIX4_GREEN1_A23(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX4_GREEN1_A23_MASK) #define IRIS_MVPL_MATRIX4_GREEN1_A24_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX4_GREEN1_A24_SHIFT (16U) /*! A24 - Value for alpha input. */ #define IRIS_MVPL_MATRIX4_GREEN1_A24(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX4_GREEN1_A24_MASK) /*! @} */ /*! @name MATRIX4_BLUE0 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_BLUE0_A31_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX4_BLUE0_A31_SHIFT (0U) /*! A31 - Value for red input. */ #define IRIS_MVPL_MATRIX4_BLUE0_A31(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX4_BLUE0_A31_MASK) #define IRIS_MVPL_MATRIX4_BLUE0_A32_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX4_BLUE0_A32_SHIFT (16U) /*! A32 - Value for green input. */ #define IRIS_MVPL_MATRIX4_BLUE0_A32(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX4_BLUE0_A32_MASK) /*! @} */ /*! @name MATRIX4_BLUE1 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_BLUE1_A33_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX4_BLUE1_A33_SHIFT (0U) /*! A33 - Value for blue input. */ #define IRIS_MVPL_MATRIX4_BLUE1_A33(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX4_BLUE1_A33_MASK) #define IRIS_MVPL_MATRIX4_BLUE1_A34_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX4_BLUE1_A34_SHIFT (16U) /*! A34 - Value for alpha input. */ #define IRIS_MVPL_MATRIX4_BLUE1_A34(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX4_BLUE1_A34_MASK) /*! @} */ /*! @name MATRIX4_ALPHA0 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_ALPHA0_A41_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX4_ALPHA0_A41_SHIFT (0U) /*! A41 - Value for red input. */ #define IRIS_MVPL_MATRIX4_ALPHA0_A41(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX4_ALPHA0_A41_MASK) #define IRIS_MVPL_MATRIX4_ALPHA0_A42_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX4_ALPHA0_A42_SHIFT (16U) /*! A42 - Value for green input. */ #define IRIS_MVPL_MATRIX4_ALPHA0_A42(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX4_ALPHA0_A42_MASK) /*! @} */ /*! @name MATRIX4_ALPHA1 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_ALPHA1_A43_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX4_ALPHA1_A43_SHIFT (0U) /*! A43 - Value for blue input. */ #define IRIS_MVPL_MATRIX4_ALPHA1_A43(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX4_ALPHA1_A43_MASK) #define IRIS_MVPL_MATRIX4_ALPHA1_A44_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX4_ALPHA1_A44_SHIFT (16U) /*! A44 - Value for alpha input. */ #define IRIS_MVPL_MATRIX4_ALPHA1_A44(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX4_ALPHA1_A44_MASK) /*! @} */ /*! @name MATRIX4_OFFSETVECTOR0 - Offset vectors for red and green output. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C1_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C1_SHIFT (0U) /*! C1 - Red output offset. */ #define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C1_MASK) #define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C2_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C2_SHIFT (16U) /*! C2 - Green output offset. */ #define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C2_MASK) /*! @} */ /*! @name MATRIX4_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C3_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C3_SHIFT (0U) /*! C3 - Blue output offset. */ #define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C3_MASK) #define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C4_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C4_SHIFT (16U) /*! C4 - Alpha output offset. Note that the 8-bit alpha input is up-scaled to 10-bit, before the * matrix and this offset is applied, and down-scaled to 8-bit for output afterwards. */ #define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C4_MASK) /*! @} */ /*! @name MATRIX4_LASTCONTROLWORD - Value of last received control word, for debugging. */ /*! @{ */ #define IRIS_MVPL_MATRIX4_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX4_LASTCONTROLWORD_L_VAL_SHIFT (0U) /*! L_VAL - Value of last received control word. For debug purposes only, read when stable only, * otherwise read data might be corrupted. */ #define IRIS_MVPL_MATRIX4_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX4_LASTCONTROLWORD_L_VAL_MASK) /*! @} */ /*! @name HSCALER4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_HSCALER4_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_HSCALER4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER4_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name HSCALER4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER4_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_HSCALER4_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_HSCALER4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER4_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_HSCALER4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_HSCALER4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_HSCALER4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER4_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_HSCALER4_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_HSCALER4_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_HSCALER4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER4_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name HSCALER4_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define IRIS_MVPL_HSCALER4_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_HSCALER4_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Shadow enable for RWS type configuration fields (0 = write-through, 1 = shadows enabled) */ #define IRIS_MVPL_HSCALER4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_HSCALER4_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name HSCALER4_SETUP1 - Phase interpolator setup. */ /*! @{ */ #define IRIS_MVPL_HSCALER4_SETUP1_scale_factor_MASK (0xFFFFFU) #define IRIS_MVPL_HSCALER4_SETUP1_scale_factor_SHIFT (0U) /*! scale_factor - Scale factor (unsigned fix-point 1.19). Must be greater 0.0 and less or equal * 1.0. If scale_mode is UPSCALE then the inverse scale factor must be programmed. */ #define IRIS_MVPL_HSCALER4_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_HSCALER4_SETUP1_scale_factor_MASK) /*! @} */ /*! @name HSCALER4_SETUP2 - Phase interpolator setup. */ /*! @{ */ #define IRIS_MVPL_HSCALER4_SETUP2_phase_offset_MASK (0x1FFFFFU) #define IRIS_MVPL_HSCALER4_SETUP2_phase_offset_SHIFT (0U) /*! phase_offset - Phase shift (signed fix-point 2.19). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the right, a positive one to the left. */ #define IRIS_MVPL_HSCALER4_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_HSCALER4_SETUP2_phase_offset_MASK) /*! @} */ /*! @name HSCALER4_CONTROL - Scaler operation control. */ /*! @{ */ #define IRIS_MVPL_HSCALER4_CONTROL_mode_MASK (0x1U) #define IRIS_MVPL_HSCALER4_CONTROL_mode_SHIFT (0U) /*! mode - Switches scaler on/off in datapath. * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored. * 0b1..Scaler is active. */ #define IRIS_MVPL_HSCALER4_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_CONTROL_mode_SHIFT)) & IRIS_MVPL_HSCALER4_CONTROL_mode_MASK) #define IRIS_MVPL_HSCALER4_CONTROL_scale_mode_MASK (0x10U) #define IRIS_MVPL_HSCALER4_CONTROL_scale_mode_SHIFT (4U) /*! scale_mode - Scale mode. * 0b0..Down-scaling (output size less or equal input size). * 0b1..Up-scaling (output size greater or equal input size) */ #define IRIS_MVPL_HSCALER4_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_HSCALER4_CONTROL_scale_mode_MASK) #define IRIS_MVPL_HSCALER4_CONTROL_filter_mode_MASK (0x100U) #define IRIS_MVPL_HSCALER4_CONTROL_filter_mode_SHIFT (8U) /*! filter_mode - Selects scaling filter algorithm. * 0b0..Nearest filter (point-sampling) * 0b1..Box filter (linear) */ #define IRIS_MVPL_HSCALER4_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_HSCALER4_CONTROL_filter_mode_MASK) #define IRIS_MVPL_HSCALER4_CONTROL_output_size_MASK (0x3FFF0000U) #define IRIS_MVPL_HSCALER4_CONTROL_output_size_SHIFT (16U) /*! output_size - Number of output pixel per input line. Value must be one less than actual number of pixels. */ #define IRIS_MVPL_HSCALER4_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_CONTROL_output_size_SHIFT)) & IRIS_MVPL_HSCALER4_CONTROL_output_size_MASK) /*! @} */ /*! @name VSCALER4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_VSCALER4_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_VSCALER4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER4_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name VSCALER4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER4_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_VSCALER4_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_VSCALER4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER4_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_VSCALER4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_VSCALER4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_VSCALER4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER4_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_VSCALER4_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_VSCALER4_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_VSCALER4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER4_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name VSCALER4_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define IRIS_MVPL_VSCALER4_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_VSCALER4_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Shadow enable for RWS type configuration fields (0 = write-through, 1 = shadows enabled) */ #define IRIS_MVPL_VSCALER4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_VSCALER4_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name VSCALER4_SETUP1 - Phase interpolator setup. */ /*! @{ */ #define IRIS_MVPL_VSCALER4_SETUP1_scale_factor_MASK (0xFFFFFU) #define IRIS_MVPL_VSCALER4_SETUP1_scale_factor_SHIFT (0U) /*! scale_factor - Scale factor (unsigned fix-point 1.19). Must be greater 0.0 and less or equal * 1.0. If scale_mode is UPSCALE then the inverse scale factor must be programmed. */ #define IRIS_MVPL_VSCALER4_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_VSCALER4_SETUP1_scale_factor_MASK) /*! @} */ /*! @name VSCALER4_SETUP2 - Phase interpolator setup, selected if input and output field polarity is 0. */ /*! @{ */ #define IRIS_MVPL_VSCALER4_SETUP2_phase_offset_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER4_SETUP2_phase_offset_SHIFT (0U) /*! phase_offset - Phase shift (signed fix-point 2.19). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the top. */ #define IRIS_MVPL_VSCALER4_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_VSCALER4_SETUP2_phase_offset_MASK) /*! @} */ /*! @name VSCALER4_SETUP3 - Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0. */ /*! @{ */ #define IRIS_MVPL_VSCALER4_SETUP3_phase_offset1_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER4_SETUP3_phase_offset1_SHIFT (0U) /*! phase_offset1 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the * top. */ #define IRIS_MVPL_VSCALER4_SETUP3_phase_offset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_SETUP3_phase_offset1_SHIFT)) & IRIS_MVPL_VSCALER4_SETUP3_phase_offset1_MASK) /*! @} */ /*! @name VSCALER4_SETUP4 - Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1. */ /*! @{ */ #define IRIS_MVPL_VSCALER4_SETUP4_phase_offset2_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER4_SETUP4_phase_offset2_SHIFT (0U) /*! phase_offset2 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the * top. */ #define IRIS_MVPL_VSCALER4_SETUP4_phase_offset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_SETUP4_phase_offset2_SHIFT)) & IRIS_MVPL_VSCALER4_SETUP4_phase_offset2_MASK) /*! @} */ /*! @name VSCALER4_SETUP5 - Phase interpolator setup, selected if input and output field polarity is 1. */ /*! @{ */ #define IRIS_MVPL_VSCALER4_SETUP5_phase_offset3_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER4_SETUP5_phase_offset3_SHIFT (0U) /*! phase_offset3 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the * top. */ #define IRIS_MVPL_VSCALER4_SETUP5_phase_offset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_SETUP5_phase_offset3_SHIFT)) & IRIS_MVPL_VSCALER4_SETUP5_phase_offset3_MASK) /*! @} */ /*! @name VSCALER4_CONTROL - Scaler operation control. */ /*! @{ */ #define IRIS_MVPL_VSCALER4_CONTROL_mode_MASK (0x1U) #define IRIS_MVPL_VSCALER4_CONTROL_mode_SHIFT (0U) /*! mode - Operation mode. * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored. * 0b1..Scaler is active. */ #define IRIS_MVPL_VSCALER4_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_CONTROL_mode_SHIFT)) & IRIS_MVPL_VSCALER4_CONTROL_mode_MASK) #define IRIS_MVPL_VSCALER4_CONTROL_scale_mode_MASK (0x10U) #define IRIS_MVPL_VSCALER4_CONTROL_scale_mode_SHIFT (4U) /*! scale_mode - Operation mode. * 0b0..Down-scaling (output size less or equal input size). * 0b1..Up-scaling (output size greater or equal input size). */ #define IRIS_MVPL_VSCALER4_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_VSCALER4_CONTROL_scale_mode_MASK) #define IRIS_MVPL_VSCALER4_CONTROL_filter_mode_MASK (0x100U) #define IRIS_MVPL_VSCALER4_CONTROL_filter_mode_SHIFT (8U) /*! filter_mode - Scaling filter. * 0b0..Nearest filter (point-sampling) * 0b1..Box filter (linear) */ #define IRIS_MVPL_VSCALER4_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_VSCALER4_CONTROL_filter_mode_MASK) #define IRIS_MVPL_VSCALER4_CONTROL_field_mode_MASK (0x3000U) #define IRIS_MVPL_VSCALER4_CONTROL_field_mode_SHIFT (12U) /*! field_mode - Controls generation of output field polarity. Has no effect in NEUTRAL mode. * 0b00..Constant 0 indicates frame or top field. * 0b01..Constant 1 indicates bottom field. * 0b10..Output field polarity is taken from input field polarity. * 0b11..Output field polarity toggles, starting with 0 after reset. */ #define IRIS_MVPL_VSCALER4_CONTROL_field_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_CONTROL_field_mode_SHIFT)) & IRIS_MVPL_VSCALER4_CONTROL_field_mode_MASK) #define IRIS_MVPL_VSCALER4_CONTROL_output_size_MASK (0x3FFF0000U) #define IRIS_MVPL_VSCALER4_CONTROL_output_size_SHIFT (16U) /*! output_size - Number of output lines per input frame. Value must be one less than actual number of pixels. */ #define IRIS_MVPL_VSCALER4_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_CONTROL_output_size_SHIFT)) & IRIS_MVPL_VSCALER4_CONTROL_output_size_MASK) /*! @} */ /*! @name MATRIX5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX5_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_MATRIX5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX5_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name MATRIX5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_MATRIX5_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_MATRIX5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX5_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_MATRIX5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_MATRIX5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_MATRIX5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX5_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_MATRIX5_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_MATRIX5_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_MATRIX5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX5_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name MATRIX5_STATICCONTROL - Color Matrix static control register */ /*! @{ */ #define IRIS_MVPL_MATRIX5_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_MATRIX5_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_MATRIX5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX5_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name MATRIX5_CONTROL - Color Matrix control register */ /*! @{ */ #define IRIS_MVPL_MATRIX5_CONTROL_MODE_MASK (0x3U) #define IRIS_MVPL_MATRIX5_CONTROL_MODE_SHIFT (0U) /*! MODE - Operation mode for color matrix * 0b00..Module in neutral mode, input data is bypassed * 0b01..Module in matrix mode, input data is multiplied with matrix values * 0b10..Module in alpha pre-multiplication mode, input color is multiplied with input alpha * 0b11..Reserved, do not use */ #define IRIS_MVPL_MATRIX5_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX5_CONTROL_MODE_MASK) #define IRIS_MVPL_MATRIX5_CONTROL_AlphaMask_MASK (0x10U) #define IRIS_MVPL_MATRIX5_CONTROL_AlphaMask_SHIFT (4U) /*! AlphaMask - Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value * smaller than 0.5 are by-passed unchanged. */ #define IRIS_MVPL_MATRIX5_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX5_CONTROL_AlphaMask_MASK) #define IRIS_MVPL_MATRIX5_CONTROL_AlphaInvert_MASK (0x20U) #define IRIS_MVPL_MATRIX5_CONTROL_AlphaInvert_SHIFT (5U) /*! AlphaInvert - Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha * value greater or equal 0.5 are by-passed). */ #define IRIS_MVPL_MATRIX5_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX5_CONTROL_AlphaInvert_MASK) /*! @} */ /*! @name MATRIX5_RED0 - Matrix values for calculation of the red output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_RED0_A11_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX5_RED0_A11_SHIFT (0U) /*! A11 - Value for red input. */ #define IRIS_MVPL_MATRIX5_RED0_A11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX5_RED0_A11_MASK) #define IRIS_MVPL_MATRIX5_RED0_A12_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX5_RED0_A12_SHIFT (16U) /*! A12 - Value for green input. */ #define IRIS_MVPL_MATRIX5_RED0_A12(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX5_RED0_A12_MASK) /*! @} */ /*! @name MATRIX5_RED1 - Matrix values for calculation of the red output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_RED1_A13_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX5_RED1_A13_SHIFT (0U) /*! A13 - Value for blue input. */ #define IRIS_MVPL_MATRIX5_RED1_A13(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX5_RED1_A13_MASK) #define IRIS_MVPL_MATRIX5_RED1_A14_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX5_RED1_A14_SHIFT (16U) /*! A14 - Value for alpha input. */ #define IRIS_MVPL_MATRIX5_RED1_A14(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX5_RED1_A14_MASK) /*! @} */ /*! @name MATRIX5_GREEN0 - Matrix values for calculation of the green output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_GREEN0_A21_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX5_GREEN0_A21_SHIFT (0U) /*! A21 - Value for red input. */ #define IRIS_MVPL_MATRIX5_GREEN0_A21(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX5_GREEN0_A21_MASK) #define IRIS_MVPL_MATRIX5_GREEN0_A22_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX5_GREEN0_A22_SHIFT (16U) /*! A22 - Value for green input. */ #define IRIS_MVPL_MATRIX5_GREEN0_A22(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX5_GREEN0_A22_MASK) /*! @} */ /*! @name MATRIX5_GREEN1 - Matrix values for calculation of the green output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_GREEN1_A23_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX5_GREEN1_A23_SHIFT (0U) /*! A23 - Value for blue input. */ #define IRIS_MVPL_MATRIX5_GREEN1_A23(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX5_GREEN1_A23_MASK) #define IRIS_MVPL_MATRIX5_GREEN1_A24_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX5_GREEN1_A24_SHIFT (16U) /*! A24 - Value for alpha input. */ #define IRIS_MVPL_MATRIX5_GREEN1_A24(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX5_GREEN1_A24_MASK) /*! @} */ /*! @name MATRIX5_BLUE0 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_BLUE0_A31_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX5_BLUE0_A31_SHIFT (0U) /*! A31 - Value for red input. */ #define IRIS_MVPL_MATRIX5_BLUE0_A31(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX5_BLUE0_A31_MASK) #define IRIS_MVPL_MATRIX5_BLUE0_A32_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX5_BLUE0_A32_SHIFT (16U) /*! A32 - Value for green input. */ #define IRIS_MVPL_MATRIX5_BLUE0_A32(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX5_BLUE0_A32_MASK) /*! @} */ /*! @name MATRIX5_BLUE1 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_BLUE1_A33_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX5_BLUE1_A33_SHIFT (0U) /*! A33 - Value for blue input. */ #define IRIS_MVPL_MATRIX5_BLUE1_A33(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX5_BLUE1_A33_MASK) #define IRIS_MVPL_MATRIX5_BLUE1_A34_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX5_BLUE1_A34_SHIFT (16U) /*! A34 - Value for alpha input. */ #define IRIS_MVPL_MATRIX5_BLUE1_A34(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX5_BLUE1_A34_MASK) /*! @} */ /*! @name MATRIX5_ALPHA0 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_ALPHA0_A41_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX5_ALPHA0_A41_SHIFT (0U) /*! A41 - Value for red input. */ #define IRIS_MVPL_MATRIX5_ALPHA0_A41(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX5_ALPHA0_A41_MASK) #define IRIS_MVPL_MATRIX5_ALPHA0_A42_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX5_ALPHA0_A42_SHIFT (16U) /*! A42 - Value for green input. */ #define IRIS_MVPL_MATRIX5_ALPHA0_A42(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX5_ALPHA0_A42_MASK) /*! @} */ /*! @name MATRIX5_ALPHA1 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_ALPHA1_A43_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX5_ALPHA1_A43_SHIFT (0U) /*! A43 - Value for blue input. */ #define IRIS_MVPL_MATRIX5_ALPHA1_A43(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX5_ALPHA1_A43_MASK) #define IRIS_MVPL_MATRIX5_ALPHA1_A44_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX5_ALPHA1_A44_SHIFT (16U) /*! A44 - Value for alpha input. */ #define IRIS_MVPL_MATRIX5_ALPHA1_A44(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX5_ALPHA1_A44_MASK) /*! @} */ /*! @name MATRIX5_OFFSETVECTOR0 - Offset vectors for red and green output. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C1_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C1_SHIFT (0U) /*! C1 - Red output offset. */ #define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C1_MASK) #define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C2_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C2_SHIFT (16U) /*! C2 - Green output offset. */ #define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C2_MASK) /*! @} */ /*! @name MATRIX5_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C3_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C3_SHIFT (0U) /*! C3 - Blue output offset. */ #define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C3_MASK) #define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C4_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C4_SHIFT (16U) /*! C4 - Alpha output offset. Note that the 8-bit alpha input is up-scaled to 10-bit, before the * matrix and this offset is applied, and down-scaled to 8-bit for output afterwards. */ #define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C4_MASK) /*! @} */ /*! @name MATRIX5_LASTCONTROLWORD - Value of last received control word, for debugging. */ /*! @{ */ #define IRIS_MVPL_MATRIX5_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX5_LASTCONTROLWORD_L_VAL_SHIFT (0U) /*! L_VAL - Value of last received control word. For debug purposes only, read when stable only, * otherwise read data might be corrupted. */ #define IRIS_MVPL_MATRIX5_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX5_LASTCONTROLWORD_L_VAL_MASK) /*! @} */ /*! @name HSCALER5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_HSCALER5_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_HSCALER5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER5_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name HSCALER5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_HSCALER5_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_HSCALER5_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_HSCALER5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER5_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_HSCALER5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_HSCALER5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_HSCALER5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER5_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_HSCALER5_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_HSCALER5_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_HSCALER5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER5_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name HSCALER5_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define IRIS_MVPL_HSCALER5_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_HSCALER5_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Shadow enable for RWS type configuration fields (0 = write-through, 1 = shadows enabled) */ #define IRIS_MVPL_HSCALER5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_HSCALER5_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name HSCALER5_SETUP1 - Phase interpolator setup. */ /*! @{ */ #define IRIS_MVPL_HSCALER5_SETUP1_scale_factor_MASK (0xFFFFFU) #define IRIS_MVPL_HSCALER5_SETUP1_scale_factor_SHIFT (0U) /*! scale_factor - Scale factor (unsigned fix-point 1.19). Must be greater 0.0 and less or equal * 1.0. If scale_mode is UPSCALE then the inverse scale factor must be programmed. */ #define IRIS_MVPL_HSCALER5_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_HSCALER5_SETUP1_scale_factor_MASK) /*! @} */ /*! @name HSCALER5_SETUP2 - Phase interpolator setup. */ /*! @{ */ #define IRIS_MVPL_HSCALER5_SETUP2_phase_offset_MASK (0x1FFFFFU) #define IRIS_MVPL_HSCALER5_SETUP2_phase_offset_SHIFT (0U) /*! phase_offset - Phase shift (signed fix-point 2.19). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the right, a positive one to the left. */ #define IRIS_MVPL_HSCALER5_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_HSCALER5_SETUP2_phase_offset_MASK) /*! @} */ /*! @name HSCALER5_CONTROL - Scaler operation control. */ /*! @{ */ #define IRIS_MVPL_HSCALER5_CONTROL_mode_MASK (0x1U) #define IRIS_MVPL_HSCALER5_CONTROL_mode_SHIFT (0U) /*! mode - Switches scaler on/off in datapath. * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored. * 0b1..Scaler is active. */ #define IRIS_MVPL_HSCALER5_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_CONTROL_mode_SHIFT)) & IRIS_MVPL_HSCALER5_CONTROL_mode_MASK) #define IRIS_MVPL_HSCALER5_CONTROL_scale_mode_MASK (0x10U) #define IRIS_MVPL_HSCALER5_CONTROL_scale_mode_SHIFT (4U) /*! scale_mode - Scale mode. * 0b0..Down-scaling (output size less or equal input size). * 0b1..Up-scaling (output size greater or equal input size) */ #define IRIS_MVPL_HSCALER5_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_HSCALER5_CONTROL_scale_mode_MASK) #define IRIS_MVPL_HSCALER5_CONTROL_filter_mode_MASK (0x100U) #define IRIS_MVPL_HSCALER5_CONTROL_filter_mode_SHIFT (8U) /*! filter_mode - Selects scaling filter algorithm. * 0b0..Nearest filter (point-sampling) * 0b1..Box filter (linear) */ #define IRIS_MVPL_HSCALER5_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_HSCALER5_CONTROL_filter_mode_MASK) #define IRIS_MVPL_HSCALER5_CONTROL_output_size_MASK (0x3FFF0000U) #define IRIS_MVPL_HSCALER5_CONTROL_output_size_SHIFT (16U) /*! output_size - Number of output pixel per input line. Value must be one less than actual number of pixels. */ #define IRIS_MVPL_HSCALER5_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_CONTROL_output_size_SHIFT)) & IRIS_MVPL_HSCALER5_CONTROL_output_size_MASK) /*! @} */ /*! @name VSCALER5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_VSCALER5_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_VSCALER5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER5_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name VSCALER5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_VSCALER5_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_VSCALER5_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_VSCALER5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER5_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_VSCALER5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_VSCALER5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_VSCALER5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER5_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_VSCALER5_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_VSCALER5_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_VSCALER5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER5_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name VSCALER5_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define IRIS_MVPL_VSCALER5_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_VSCALER5_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Shadow enable for RWS type configuration fields (0 = write-through, 1 = shadows enabled) */ #define IRIS_MVPL_VSCALER5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_VSCALER5_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name VSCALER5_SETUP1 - Phase interpolator setup. */ /*! @{ */ #define IRIS_MVPL_VSCALER5_SETUP1_scale_factor_MASK (0xFFFFFU) #define IRIS_MVPL_VSCALER5_SETUP1_scale_factor_SHIFT (0U) /*! scale_factor - Scale factor (unsigned fix-point 1.19). Must be greater 0.0 and less or equal * 1.0. If scale_mode is UPSCALE then the inverse scale factor must be programmed. */ #define IRIS_MVPL_VSCALER5_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_VSCALER5_SETUP1_scale_factor_MASK) /*! @} */ /*! @name VSCALER5_SETUP2 - Phase interpolator setup, selected if input and output field polarity is 0. */ /*! @{ */ #define IRIS_MVPL_VSCALER5_SETUP2_phase_offset_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER5_SETUP2_phase_offset_SHIFT (0U) /*! phase_offset - Phase shift (signed fix-point 2.19). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the top. */ #define IRIS_MVPL_VSCALER5_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_VSCALER5_SETUP2_phase_offset_MASK) /*! @} */ /*! @name VSCALER5_SETUP3 - Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0. */ /*! @{ */ #define IRIS_MVPL_VSCALER5_SETUP3_phase_offset1_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER5_SETUP3_phase_offset1_SHIFT (0U) /*! phase_offset1 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the * top. */ #define IRIS_MVPL_VSCALER5_SETUP3_phase_offset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_SETUP3_phase_offset1_SHIFT)) & IRIS_MVPL_VSCALER5_SETUP3_phase_offset1_MASK) /*! @} */ /*! @name VSCALER5_SETUP4 - Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1. */ /*! @{ */ #define IRIS_MVPL_VSCALER5_SETUP4_phase_offset2_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER5_SETUP4_phase_offset2_SHIFT (0U) /*! phase_offset2 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the * top. */ #define IRIS_MVPL_VSCALER5_SETUP4_phase_offset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_SETUP4_phase_offset2_SHIFT)) & IRIS_MVPL_VSCALER5_SETUP4_phase_offset2_MASK) /*! @} */ /*! @name VSCALER5_SETUP5 - Phase interpolator setup, selected if input and output field polarity is 1. */ /*! @{ */ #define IRIS_MVPL_VSCALER5_SETUP5_phase_offset3_MASK (0x1FFFFFU) #define IRIS_MVPL_VSCALER5_SETUP5_phase_offset3_SHIFT (0U) /*! phase_offset3 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the * top. */ #define IRIS_MVPL_VSCALER5_SETUP5_phase_offset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_SETUP5_phase_offset3_SHIFT)) & IRIS_MVPL_VSCALER5_SETUP5_phase_offset3_MASK) /*! @} */ /*! @name VSCALER5_CONTROL - Scaler operation control. */ /*! @{ */ #define IRIS_MVPL_VSCALER5_CONTROL_mode_MASK (0x1U) #define IRIS_MVPL_VSCALER5_CONTROL_mode_SHIFT (0U) /*! mode - Operation mode. * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored. * 0b1..Scaler is active. */ #define IRIS_MVPL_VSCALER5_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_CONTROL_mode_SHIFT)) & IRIS_MVPL_VSCALER5_CONTROL_mode_MASK) #define IRIS_MVPL_VSCALER5_CONTROL_scale_mode_MASK (0x10U) #define IRIS_MVPL_VSCALER5_CONTROL_scale_mode_SHIFT (4U) /*! scale_mode - Operation mode. * 0b0..Down-scaling (output size less or equal input size). * 0b1..Up-scaling (output size greater or equal input size). */ #define IRIS_MVPL_VSCALER5_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_VSCALER5_CONTROL_scale_mode_MASK) #define IRIS_MVPL_VSCALER5_CONTROL_filter_mode_MASK (0x100U) #define IRIS_MVPL_VSCALER5_CONTROL_filter_mode_SHIFT (8U) /*! filter_mode - Scaling filter. * 0b0..Nearest filter (point-sampling) * 0b1..Box filter (linear) */ #define IRIS_MVPL_VSCALER5_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_VSCALER5_CONTROL_filter_mode_MASK) #define IRIS_MVPL_VSCALER5_CONTROL_field_mode_MASK (0x3000U) #define IRIS_MVPL_VSCALER5_CONTROL_field_mode_SHIFT (12U) /*! field_mode - Controls generation of output field polarity. Has no effect in NEUTRAL mode. * 0b00..Constant 0 indicates frame or top field. * 0b01..Constant 1 indicates bottom field. * 0b10..Output field polarity is taken from input field polarity. * 0b11..Output field polarity toggles, starting with 0 after reset. */ #define IRIS_MVPL_VSCALER5_CONTROL_field_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_CONTROL_field_mode_SHIFT)) & IRIS_MVPL_VSCALER5_CONTROL_field_mode_MASK) #define IRIS_MVPL_VSCALER5_CONTROL_output_size_MASK (0x3FFF0000U) #define IRIS_MVPL_VSCALER5_CONTROL_output_size_SHIFT (16U) /*! output_size - Number of output lines per input frame. Value must be one less than actual number of pixels. */ #define IRIS_MVPL_VSCALER5_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_CONTROL_output_size_SHIFT)) & IRIS_MVPL_VSCALER5_CONTROL_output_size_MASK) /*! @} */ /*! @name LAYERBLEND0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_LAYERBLEND0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name LAYERBLEND0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name LAYERBLEND0_STATICCONTROL - Static control settings. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type fields of this unit (0 = write through, 1 = shadowed). */ #define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdLdSel_MASK (0x6U) #define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdLdSel_SHIFT (1U) /*! ShdLdSel - Controls when shadow fields of this unit are loaded into the active configuration in case that ShdEn is enabled. * 0b00..Load shadows with shadow load token on primary input (background plane). * 0b01..Load shadows with shadow load token on secondary input (foreground plane). * 0b10..Load shadows with shadow load token on any input. */ #define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdLdSel_MASK) #define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdTokSel_MASK (0x18U) #define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdTokSel_SHIFT (3U) /*! ShdTokSel - Controls when a shadow load token is generated on the output port, which controls * shadow load in subsequent processing units. * 0b00..When a token was received on the primary input (background plane). * 0b01..When a token was received on the secondary input (foreground plane). * 0b10..When a token was received on any input. */ #define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdTokSel_MASK) /*! @} */ /*! @name LAYERBLEND0_CONTROL - Common control settings. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND0_CONTROL_MODE_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND0_CONTROL_MODE_SHIFT (0U) /*! MODE - Operation mode. * 0b0..Module is in neutral mode. Output is same as primary input. * 0b1..Module is in blending mode. */ #define IRIS_MVPL_LAYERBLEND0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_MODE_MASK) #define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskEnable_MASK (0x4U) #define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskEnable_SHIFT (2U) /*! AlphaMaskEnable - Enables Alpha Mask feature. This will limit possible output alpha values to 0 * and 255. Generation of this alpha value will depend on the AlphaMaskMode field. * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskEnable_MASK) #define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskMode_MASK (0x70U) #define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskMode_SHIFT (4U) /*! AlphaMaskMode - AlphaMaskMode determines how the output alpha is generated when AlphaMaskEnable is set to ENABLE * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskMode_MASK) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecLowPassEn_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecLowPassEn_SHIFT (8U) /*! SecLowPassEn - Enables a horizontal low-pass filter for the secondary input port. Should be used * for dual view and dual display mode when the secondary input frame has twice the resolution * of one view (= full resolution of the panel interface). Every 2nd pixel only is sampled then. */ #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecLowPassEn_MASK) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecReplicateEn_MASK (0x200U) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecReplicateEn_SHIFT (9U) /*! SecReplicateEn - Enables horizontal replication of pixels by factor 2 on secondary input port. * Must be used for dual display mode when the secondary input frame has the resolution of one * display (= half the resolution of the panel interface). */ #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecReplicateEn_MASK) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowEvenColDis_SHIFT (10U) /*! SecEvenRowEvenColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * and column index is even. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowEvenColDis_MASK) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowOddColDis_SHIFT (14U) /*! SecEvenRowOddColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * index is even and column index is odd. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowOddColDis_MASK) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowEvenColDis_SHIFT (18U) /*! SecOddRowEvenColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * index is odd and column index is even. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowEvenColDis_MASK) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U) #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowOddColDis_SHIFT (22U) /*! SecOddRowOddColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * and column index is odd. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowOddColDis_MASK) /*! @} */ /*! @name LAYERBLEND0_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U) #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U) /*! PRIM_C_BLD_FUNC - Primary (background) input color blending function * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U) #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U) /*! SEC_C_BLD_FUNC - Secondary (overlay) input color blending function * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U) #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U) /*! PRIM_A_BLD_FUNC - Primary (background) input alpha blending function * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U) #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U) /*! SEC_A_BLD_FUNC - Secondary (overlay) input alpha blending function * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U) #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_BlendAlpha_SHIFT (16U) /*! BlendAlpha - Constant alpha value, used for constant alpha blending */ #define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_BlendAlpha_MASK) /*! @} */ /*! @name LAYERBLEND0_POSITION - Position of secondary (overlay) input frame */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND0_POSITION_XPOS_MASK (0xFFFFU) #define IRIS_MVPL_LAYERBLEND0_POSITION_XPOS_SHIFT (0U) /*! XPOS - horizontal position, first pixel is at 0, format s15 (twos complement) */ #define IRIS_MVPL_LAYERBLEND0_POSITION_XPOS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND0_POSITION_XPOS_MASK) #define IRIS_MVPL_LAYERBLEND0_POSITION_YPOS_MASK (0xFFFF0000U) #define IRIS_MVPL_LAYERBLEND0_POSITION_YPOS_SHIFT (16U) /*! YPOS - vertical position, first pixel is at 0, format s15 (twos complement) */ #define IRIS_MVPL_LAYERBLEND0_POSITION_YPOS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND0_POSITION_YPOS_MASK) /*! @} */ /*! @name LAYERBLEND0_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_SHIFT (0U) /*! P_VAL - Value of last received control word */ #define IRIS_MVPL_LAYERBLEND0_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_MASK) /*! @} */ /*! @name LAYERBLEND0_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND0_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND0_SECCONTROLWORD_S_VAL_SHIFT (0U) /*! S_VAL - Value of last received control word */ #define IRIS_MVPL_LAYERBLEND0_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND0_SECCONTROLWORD_S_VAL_MASK) /*! @} */ /*! @name LAYERBLEND1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND1_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_LAYERBLEND1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND1_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name LAYERBLEND1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name LAYERBLEND1_STATICCONTROL - Static control settings. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type fields of this unit (0 = write through, 1 = shadowed). */ #define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdLdSel_MASK (0x6U) #define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdLdSel_SHIFT (1U) /*! ShdLdSel - Controls when shadow fields of this unit are loaded into the active configuration in case that ShdEn is enabled. * 0b00..Load shadows with shadow load token on primary input (background plane). * 0b01..Load shadows with shadow load token on secondary input (foreground plane). * 0b10..Load shadows with shadow load token on any input. */ #define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdLdSel_MASK) #define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdTokSel_MASK (0x18U) #define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdTokSel_SHIFT (3U) /*! ShdTokSel - Controls when a shadow load token is generated on the output port, which controls * shadow load in subsequent processing units. * 0b00..When a token was received on the primary input (background plane). * 0b01..When a token was received on the secondary input (foreground plane). * 0b10..When a token was received on any input. */ #define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdTokSel_MASK) /*! @} */ /*! @name LAYERBLEND1_CONTROL - Common control settings. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1_CONTROL_MODE_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND1_CONTROL_MODE_SHIFT (0U) /*! MODE - Operation mode. * 0b0..Module is in neutral mode. Output is same as primary input. * 0b1..Module is in blending mode. */ #define IRIS_MVPL_LAYERBLEND1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_MODE_MASK) #define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskEnable_MASK (0x4U) #define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskEnable_SHIFT (2U) /*! AlphaMaskEnable - Enables Alpha Mask feature. This will limit possible output alpha values to 0 * and 255. Generation of this alpha value will depend on the AlphaMaskMode field. * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskEnable_MASK) #define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskMode_MASK (0x70U) #define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskMode_SHIFT (4U) /*! AlphaMaskMode - AlphaMaskMode determines how the output alpha is generated when AlphaMaskEnable is set to ENABLE * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskMode_MASK) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecLowPassEn_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecLowPassEn_SHIFT (8U) /*! SecLowPassEn - Enables a horizontal low-pass filter for the secondary input port. Should be used * for dual view and dual display mode when the secondary input frame has twice the resolution * of one view (= full resolution of the panel interface). Every 2nd pixel only is sampled then. */ #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecLowPassEn_MASK) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecReplicateEn_MASK (0x200U) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecReplicateEn_SHIFT (9U) /*! SecReplicateEn - Enables horizontal replication of pixels by factor 2 on secondary input port. * Must be used for dual display mode when the secondary input frame has the resolution of one * display (= half the resolution of the panel interface). */ #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecReplicateEn_MASK) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowEvenColDis_SHIFT (10U) /*! SecEvenRowEvenColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * and column index is even. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowEvenColDis_MASK) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowOddColDis_SHIFT (14U) /*! SecEvenRowOddColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * index is even and column index is odd. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowOddColDis_MASK) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowEvenColDis_SHIFT (18U) /*! SecOddRowEvenColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * index is odd and column index is even. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowEvenColDis_MASK) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U) #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowOddColDis_SHIFT (22U) /*! SecOddRowOddColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * and column index is odd. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowOddColDis_MASK) /*! @} */ /*! @name LAYERBLEND1_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U) #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U) /*! PRIM_C_BLD_FUNC - Primary (background) input color blending function * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U) #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U) /*! SEC_C_BLD_FUNC - Secondary (overlay) input color blending function * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U) #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U) /*! PRIM_A_BLD_FUNC - Primary (background) input alpha blending function * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U) #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U) /*! SEC_A_BLD_FUNC - Secondary (overlay) input alpha blending function * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U) #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_BlendAlpha_SHIFT (16U) /*! BlendAlpha - Constant alpha value, used for constant alpha blending */ #define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_BlendAlpha_MASK) /*! @} */ /*! @name LAYERBLEND1_POSITION - Position of secondary (overlay) input frame */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1_POSITION_XPOS_MASK (0xFFFFU) #define IRIS_MVPL_LAYERBLEND1_POSITION_XPOS_SHIFT (0U) /*! XPOS - horizontal position, first pixel is at 0, format s15 (twos complement) */ #define IRIS_MVPL_LAYERBLEND1_POSITION_XPOS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND1_POSITION_XPOS_MASK) #define IRIS_MVPL_LAYERBLEND1_POSITION_YPOS_MASK (0xFFFF0000U) #define IRIS_MVPL_LAYERBLEND1_POSITION_YPOS_SHIFT (16U) /*! YPOS - vertical position, first pixel is at 0, format s15 (twos complement) */ #define IRIS_MVPL_LAYERBLEND1_POSITION_YPOS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND1_POSITION_YPOS_MASK) /*! @} */ /*! @name LAYERBLEND1_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_SHIFT (0U) /*! P_VAL - Value of last received control word */ #define IRIS_MVPL_LAYERBLEND1_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_MASK) /*! @} */ /*! @name LAYERBLEND1_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND1_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND1_SECCONTROLWORD_S_VAL_SHIFT (0U) /*! S_VAL - Value of last received control word */ #define IRIS_MVPL_LAYERBLEND1_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND1_SECCONTROLWORD_S_VAL_MASK) /*! @} */ /*! @name LAYERBLEND2_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND2_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND2_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_LAYERBLEND2_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND2_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name LAYERBLEND2_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name LAYERBLEND2_STATICCONTROL - Static control settings. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type fields of this unit (0 = write through, 1 = shadowed). */ #define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdLdSel_MASK (0x6U) #define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdLdSel_SHIFT (1U) /*! ShdLdSel - Controls when shadow fields of this unit are loaded into the active configuration in case that ShdEn is enabled. * 0b00..Load shadows with shadow load token on primary input (background plane). * 0b01..Load shadows with shadow load token on secondary input (foreground plane). * 0b10..Load shadows with shadow load token on any input. */ #define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdLdSel_MASK) #define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdTokSel_MASK (0x18U) #define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdTokSel_SHIFT (3U) /*! ShdTokSel - Controls when a shadow load token is generated on the output port, which controls * shadow load in subsequent processing units. * 0b00..When a token was received on the primary input (background plane). * 0b01..When a token was received on the secondary input (foreground plane). * 0b10..When a token was received on any input. */ #define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdTokSel_MASK) /*! @} */ /*! @name LAYERBLEND2_CONTROL - Common control settings. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND2_CONTROL_MODE_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND2_CONTROL_MODE_SHIFT (0U) /*! MODE - Operation mode. * 0b0..Module is in neutral mode. Output is same as primary input. * 0b1..Module is in blending mode. */ #define IRIS_MVPL_LAYERBLEND2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_MODE_MASK) #define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskEnable_MASK (0x4U) #define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskEnable_SHIFT (2U) /*! AlphaMaskEnable - Enables Alpha Mask feature. This will limit possible output alpha values to 0 * and 255. Generation of this alpha value will depend on the AlphaMaskMode field. * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskEnable_MASK) #define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskMode_MASK (0x70U) #define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskMode_SHIFT (4U) /*! AlphaMaskMode - AlphaMaskMode determines how the output alpha is generated when AlphaMaskEnable is set to ENABLE * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskMode_MASK) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecLowPassEn_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecLowPassEn_SHIFT (8U) /*! SecLowPassEn - Enables a horizontal low-pass filter for the secondary input port. Should be used * for dual view and dual display mode when the secondary input frame has twice the resolution * of one view (= full resolution of the panel interface). Every 2nd pixel only is sampled then. */ #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecLowPassEn_MASK) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecReplicateEn_MASK (0x200U) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecReplicateEn_SHIFT (9U) /*! SecReplicateEn - Enables horizontal replication of pixels by factor 2 on secondary input port. * Must be used for dual display mode when the secondary input frame has the resolution of one * display (= half the resolution of the panel interface). */ #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecReplicateEn_MASK) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowEvenColDis_SHIFT (10U) /*! SecEvenRowEvenColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * and column index is even. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowEvenColDis_MASK) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowOddColDis_SHIFT (14U) /*! SecEvenRowOddColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * index is even and column index is odd. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowOddColDis_MASK) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowEvenColDis_SHIFT (18U) /*! SecOddRowEvenColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * index is odd and column index is even. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowEvenColDis_MASK) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U) #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowOddColDis_SHIFT (22U) /*! SecOddRowOddColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * and column index is odd. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowOddColDis_MASK) /*! @} */ /*! @name LAYERBLEND2_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U) #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U) /*! PRIM_C_BLD_FUNC - Primary (background) input color blending function * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U) #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U) /*! SEC_C_BLD_FUNC - Secondary (overlay) input color blending function * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U) #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U) /*! PRIM_A_BLD_FUNC - Primary (background) input alpha blending function * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U) #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U) /*! SEC_A_BLD_FUNC - Secondary (overlay) input alpha blending function * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U) #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_BlendAlpha_SHIFT (16U) /*! BlendAlpha - Constant alpha value, used for constant alpha blending */ #define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_BlendAlpha_MASK) /*! @} */ /*! @name LAYERBLEND2_POSITION - Position of secondary (overlay) input frame */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND2_POSITION_XPOS_MASK (0xFFFFU) #define IRIS_MVPL_LAYERBLEND2_POSITION_XPOS_SHIFT (0U) /*! XPOS - horizontal position, first pixel is at 0, format s15 (twos complement) */ #define IRIS_MVPL_LAYERBLEND2_POSITION_XPOS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND2_POSITION_XPOS_MASK) #define IRIS_MVPL_LAYERBLEND2_POSITION_YPOS_MASK (0xFFFF0000U) #define IRIS_MVPL_LAYERBLEND2_POSITION_YPOS_SHIFT (16U) /*! YPOS - vertical position, first pixel is at 0, format s15 (twos complement) */ #define IRIS_MVPL_LAYERBLEND2_POSITION_YPOS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND2_POSITION_YPOS_MASK) /*! @} */ /*! @name LAYERBLEND2_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_SHIFT (0U) /*! P_VAL - Value of last received control word */ #define IRIS_MVPL_LAYERBLEND2_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_MASK) /*! @} */ /*! @name LAYERBLEND2_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND2_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND2_SECCONTROLWORD_S_VAL_SHIFT (0U) /*! S_VAL - Value of last received control word */ #define IRIS_MVPL_LAYERBLEND2_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND2_SECCONTROLWORD_S_VAL_MASK) /*! @} */ /*! @name LAYERBLEND3_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND3_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND3_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_LAYERBLEND3_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND3_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name LAYERBLEND3_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name LAYERBLEND3_STATICCONTROL - Static control settings. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type fields of this unit (0 = write through, 1 = shadowed). */ #define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdLdSel_MASK (0x6U) #define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdLdSel_SHIFT (1U) /*! ShdLdSel - Controls when shadow fields of this unit are loaded into the active configuration in case that ShdEn is enabled. * 0b00..Load shadows with shadow load token on primary input (background plane). * 0b01..Load shadows with shadow load token on secondary input (foreground plane). * 0b10..Load shadows with shadow load token on any input. */ #define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdLdSel_MASK) #define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdTokSel_MASK (0x18U) #define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdTokSel_SHIFT (3U) /*! ShdTokSel - Controls when a shadow load token is generated on the output port, which controls * shadow load in subsequent processing units. * 0b00..When a token was received on the primary input (background plane). * 0b01..When a token was received on the secondary input (foreground plane). * 0b10..When a token was received on any input. */ #define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdTokSel_MASK) /*! @} */ /*! @name LAYERBLEND3_CONTROL - Common control settings. */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND3_CONTROL_MODE_MASK (0x1U) #define IRIS_MVPL_LAYERBLEND3_CONTROL_MODE_SHIFT (0U) /*! MODE - Operation mode. * 0b0..Module is in neutral mode. Output is same as primary input. * 0b1..Module is in blending mode. */ #define IRIS_MVPL_LAYERBLEND3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_MODE_MASK) #define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskEnable_MASK (0x4U) #define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskEnable_SHIFT (2U) /*! AlphaMaskEnable - Enables Alpha Mask feature. This will limit possible output alpha values to 0 * and 255. Generation of this alpha value will depend on the AlphaMaskMode field. * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskEnable_MASK) #define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskMode_MASK (0x70U) #define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskMode_SHIFT (4U) /*! AlphaMaskMode - AlphaMaskMode determines how the output alpha is generated when AlphaMaskEnable is set to ENABLE * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskMode_MASK) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecLowPassEn_MASK (0x100U) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecLowPassEn_SHIFT (8U) /*! SecLowPassEn - Enables a horizontal low-pass filter for the secondary input port. Should be used * for dual view and dual display mode when the secondary input frame has twice the resolution * of one view (= full resolution of the panel interface). Every 2nd pixel only is sampled then. */ #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecLowPassEn_MASK) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecReplicateEn_MASK (0x200U) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecReplicateEn_SHIFT (9U) /*! SecReplicateEn - Enables horizontal replication of pixels by factor 2 on secondary input port. * Must be used for dual display mode when the secondary input frame has the resolution of one * display (= half the resolution of the panel interface). */ #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecReplicateEn_MASK) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowEvenColDis_SHIFT (10U) /*! SecEvenRowEvenColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * and column index is even. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowEvenColDis_MASK) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowOddColDis_SHIFT (14U) /*! SecEvenRowOddColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * index is even and column index is odd. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowOddColDis_MASK) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowEvenColDis_SHIFT (18U) /*! SecOddRowEvenColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * index is odd and column index is even. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowEvenColDis_MASK) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U) #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowOddColDis_SHIFT (22U) /*! SecOddRowOddColDis - Disable bits for R/Y, G/U, B/V and A channels of secondary input when row * and column index is odd. R/Y is MSBit, A is LSBit. */ #define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowOddColDis_MASK) /*! @} */ /*! @name LAYERBLEND3_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U) #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U) /*! PRIM_C_BLD_FUNC - Primary (background) input color blending function * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U) #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U) /*! SEC_C_BLD_FUNC - Secondary (overlay) input color blending function * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U) #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U) /*! PRIM_A_BLD_FUNC - Primary (background) input alpha blending function * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U) #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U) /*! SEC_A_BLD_FUNC - Secondary (overlay) input alpha blending function * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_MASK) #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U) #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_BlendAlpha_SHIFT (16U) /*! BlendAlpha - Constant alpha value, used for constant alpha blending */ #define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_BlendAlpha_MASK) /*! @} */ /*! @name LAYERBLEND3_POSITION - Position of secondary (overlay) input frame */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND3_POSITION_XPOS_MASK (0xFFFFU) #define IRIS_MVPL_LAYERBLEND3_POSITION_XPOS_SHIFT (0U) /*! XPOS - horizontal position, first pixel is at 0, format s15 (twos complement) */ #define IRIS_MVPL_LAYERBLEND3_POSITION_XPOS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND3_POSITION_XPOS_MASK) #define IRIS_MVPL_LAYERBLEND3_POSITION_YPOS_MASK (0xFFFF0000U) #define IRIS_MVPL_LAYERBLEND3_POSITION_YPOS_SHIFT (16U) /*! YPOS - vertical position, first pixel is at 0, format s15 (twos complement) */ #define IRIS_MVPL_LAYERBLEND3_POSITION_YPOS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND3_POSITION_YPOS_MASK) /*! @} */ /*! @name LAYERBLEND3_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_SHIFT (0U) /*! P_VAL - Value of last received control word */ #define IRIS_MVPL_LAYERBLEND3_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_MASK) /*! @} */ /*! @name LAYERBLEND3_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */ /*! @{ */ #define IRIS_MVPL_LAYERBLEND3_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LAYERBLEND3_SECCONTROLWORD_S_VAL_SHIFT (0U) /*! S_VAL - Value of last received control word */ #define IRIS_MVPL_LAYERBLEND3_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND3_SECCONTROLWORD_S_VAL_MASK) /*! @} */ /*! @name LOCKUNLOCK0 - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LOCKUNLOCK0_LockUnlock0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LOCKUNLOCK0_LockUnlock0_SHIFT (0U) /*! LockUnlock0 - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_LOCKUNLOCK0_LockUnlock0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LOCKUNLOCK0_LockUnlock0_SHIFT)) & IRIS_MVPL_LOCKUNLOCK0_LockUnlock0_MASK) /*! @} */ /*! @name LOCKSTATUS0 - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LOCKSTATUS0_LockStatus0_MASK (0x1U) #define IRIS_MVPL_LOCKSTATUS0_LockStatus0_SHIFT (0U) /*! LockStatus0 - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_LOCKSTATUS0_LockStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LOCKSTATUS0_LockStatus0_SHIFT)) & IRIS_MVPL_LOCKSTATUS0_LockStatus0_MASK) #define IRIS_MVPL_LOCKSTATUS0_PrivilegeStatus0_MASK (0x10U) #define IRIS_MVPL_LOCKSTATUS0_PrivilegeStatus0_SHIFT (4U) /*! PrivilegeStatus0 - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_LOCKSTATUS0_PrivilegeStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LOCKSTATUS0_PrivilegeStatus0_SHIFT)) & IRIS_MVPL_LOCKSTATUS0_PrivilegeStatus0_MASK) #define IRIS_MVPL_LOCKSTATUS0_FreezeStatus0_MASK (0x100U) #define IRIS_MVPL_LOCKSTATUS0_FreezeStatus0_SHIFT (8U) /*! FreezeStatus0 - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_LOCKSTATUS0_FreezeStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LOCKSTATUS0_FreezeStatus0_SHIFT)) & IRIS_MVPL_LOCKSTATUS0_FreezeStatus0_MASK) /*! @} */ /*! @name CLOCKCTRL0 - No function in SEERIS-MVPL, internally hardwired to DIV1. */ /*! @{ */ #define IRIS_MVPL_CLOCKCTRL0_DspClkDivide0_MASK (0x1U) #define IRIS_MVPL_CLOCKCTRL0_DspClkDivide0_SHIFT (0U) /*! DspClkDivide0 - Controls generation of display clock signals for display stream 0. * 0b0..External display clock signal has pixel clock frequency. * 0b1..External display clock signal has twice the pixel clock frequency. */ #define IRIS_MVPL_CLOCKCTRL0_DspClkDivide0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLOCKCTRL0_DspClkDivide0_SHIFT)) & IRIS_MVPL_CLOCKCTRL0_DspClkDivide0_MASK) /*! @} */ /*! @name POLARITYCTRL0 - Polarity control for TCon#0 input and corresponding top-level output (TCon by-pass port). */ /*! @{ */ #define IRIS_MVPL_POLARITYCTRL0_PolHs0_MASK (0x1U) #define IRIS_MVPL_POLARITYCTRL0_PolHs0_SHIFT (0U) /*! PolHs0 - Polarity of hsync signal. * 0b0..Low active * 0b1..High active */ #define IRIS_MVPL_POLARITYCTRL0_PolHs0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_POLARITYCTRL0_PolHs0_SHIFT)) & IRIS_MVPL_POLARITYCTRL0_PolHs0_MASK) #define IRIS_MVPL_POLARITYCTRL0_PolVs0_MASK (0x2U) #define IRIS_MVPL_POLARITYCTRL0_PolVs0_SHIFT (1U) /*! PolVs0 - Polarity of vsync signal. * 0b0..Low active * 0b1..High active */ #define IRIS_MVPL_POLARITYCTRL0_PolVs0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_POLARITYCTRL0_PolVs0_SHIFT)) & IRIS_MVPL_POLARITYCTRL0_PolVs0_MASK) #define IRIS_MVPL_POLARITYCTRL0_PolEn0_MASK (0x4U) #define IRIS_MVPL_POLARITYCTRL0_PolEn0_SHIFT (2U) /*! PolEn0 - Polarity of Data_Enable signal. * 0b0..Low active * 0b1..High active */ #define IRIS_MVPL_POLARITYCTRL0_PolEn0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_POLARITYCTRL0_PolEn0_SHIFT)) & IRIS_MVPL_POLARITYCTRL0_PolEn0_MASK) #define IRIS_MVPL_POLARITYCTRL0_PixInv0_MASK (0x8U) #define IRIS_MVPL_POLARITYCTRL0_PixInv0_SHIFT (3U) /*! PixInv0 - Inversion of RGB data. * 0b0..No inversion of pixel data * 0b1..Pixel data inverted (1. complement) */ #define IRIS_MVPL_POLARITYCTRL0_PixInv0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_POLARITYCTRL0_PixInv0_SHIFT)) & IRIS_MVPL_POLARITYCTRL0_PixInv0_MASK) /*! @} */ /*! @name SRCSELECT0 - Tap selection for Signature (display stream 0). Disable framegen#0 for reprogramming. */ /*! @{ */ #define IRIS_MVPL_SRCSELECT0_sig_select0_MASK (0x3U) #define IRIS_MVPL_SRCSELECT0_sig_select0_SHIFT (0U) /*! sig_select0 - Selects a source for Sig#0 unit. * 0b00..Source is FrameGen#0 output. * 0b01..Source is GammaCor#0 output. * 0b10..Source is Matrix#0 output. * 0b11..Source is Dither#0 output. */ #define IRIS_MVPL_SRCSELECT0_sig_select0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SRCSELECT0_sig_select0_SHIFT)) & IRIS_MVPL_SRCSELECT0_sig_select0_MASK) #define IRIS_MVPL_SRCSELECT0_path_select0_MASK (0x10U) #define IRIS_MVPL_SRCSELECT0_path_select0_SHIFT (4U) /*! path_select0 - Selects display#0 path. * 0b0..Framegen - Gamma - Matrix - Dither. * 0b1..Framegen - Matrix - Gamma - Dither. */ #define IRIS_MVPL_SRCSELECT0_path_select0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SRCSELECT0_path_select0_SHIFT)) & IRIS_MVPL_SRCSELECT0_path_select0_MASK) /*! @} */ /*! @name LOCKUNLOCK1 - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LOCKUNLOCK1_LockUnlock1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_LOCKUNLOCK1_LockUnlock1_SHIFT (0U) /*! LockUnlock1 - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_LOCKUNLOCK1_LockUnlock1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LOCKUNLOCK1_LockUnlock1_SHIFT)) & IRIS_MVPL_LOCKUNLOCK1_LockUnlock1_MASK) /*! @} */ /*! @name LOCKSTATUS1 - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_LOCKSTATUS1_LockStatus1_MASK (0x1U) #define IRIS_MVPL_LOCKSTATUS1_LockStatus1_SHIFT (0U) /*! LockStatus1 - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_LOCKSTATUS1_LockStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LOCKSTATUS1_LockStatus1_SHIFT)) & IRIS_MVPL_LOCKSTATUS1_LockStatus1_MASK) #define IRIS_MVPL_LOCKSTATUS1_PrivilegeStatus1_MASK (0x10U) #define IRIS_MVPL_LOCKSTATUS1_PrivilegeStatus1_SHIFT (4U) /*! PrivilegeStatus1 - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_LOCKSTATUS1_PrivilegeStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LOCKSTATUS1_PrivilegeStatus1_SHIFT)) & IRIS_MVPL_LOCKSTATUS1_PrivilegeStatus1_MASK) #define IRIS_MVPL_LOCKSTATUS1_FreezeStatus1_MASK (0x100U) #define IRIS_MVPL_LOCKSTATUS1_FreezeStatus1_SHIFT (8U) /*! FreezeStatus1 - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_LOCKSTATUS1_FreezeStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LOCKSTATUS1_FreezeStatus1_SHIFT)) & IRIS_MVPL_LOCKSTATUS1_FreezeStatus1_MASK) /*! @} */ /*! @name CLOCKCTRL1 - No function in SEERIS-MVPL, internally hardwired to DIV1. */ /*! @{ */ #define IRIS_MVPL_CLOCKCTRL1_DspClkDivide1_MASK (0x1U) #define IRIS_MVPL_CLOCKCTRL1_DspClkDivide1_SHIFT (0U) /*! DspClkDivide1 - Controls generation of display clock signals for display stream 1. * 0b0..External display clock signal has pixel clock frequency. * 0b1..External display clock signal has twice the pixel clock frequency. */ #define IRIS_MVPL_CLOCKCTRL1_DspClkDivide1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLOCKCTRL1_DspClkDivide1_SHIFT)) & IRIS_MVPL_CLOCKCTRL1_DspClkDivide1_MASK) /*! @} */ /*! @name POLARITYCTRL1 - Polarity control for TCon#1 input and corresponding top-level output (TCon by-pass port). */ /*! @{ */ #define IRIS_MVPL_POLARITYCTRL1_PolHs1_MASK (0x1U) #define IRIS_MVPL_POLARITYCTRL1_PolHs1_SHIFT (0U) /*! PolHs1 - Polarity of hsync signal. * 0b0..Low active * 0b1..High active */ #define IRIS_MVPL_POLARITYCTRL1_PolHs1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_POLARITYCTRL1_PolHs1_SHIFT)) & IRIS_MVPL_POLARITYCTRL1_PolHs1_MASK) #define IRIS_MVPL_POLARITYCTRL1_PolVs1_MASK (0x2U) #define IRIS_MVPL_POLARITYCTRL1_PolVs1_SHIFT (1U) /*! PolVs1 - Polarity of vsync signal. * 0b0..Low active * 0b1..High active */ #define IRIS_MVPL_POLARITYCTRL1_PolVs1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_POLARITYCTRL1_PolVs1_SHIFT)) & IRIS_MVPL_POLARITYCTRL1_PolVs1_MASK) #define IRIS_MVPL_POLARITYCTRL1_PolEn1_MASK (0x4U) #define IRIS_MVPL_POLARITYCTRL1_PolEn1_SHIFT (2U) /*! PolEn1 - Polarity of Data_Enable signal. * 0b0..Low active * 0b1..High active */ #define IRIS_MVPL_POLARITYCTRL1_PolEn1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_POLARITYCTRL1_PolEn1_SHIFT)) & IRIS_MVPL_POLARITYCTRL1_PolEn1_MASK) #define IRIS_MVPL_POLARITYCTRL1_PixInv1_MASK (0x8U) #define IRIS_MVPL_POLARITYCTRL1_PixInv1_SHIFT (3U) /*! PixInv1 - Inversion of RGB data. * 0b0..No inversion of pixel data * 0b1..Pixel data inverted (1. complement) */ #define IRIS_MVPL_POLARITYCTRL1_PixInv1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_POLARITYCTRL1_PixInv1_SHIFT)) & IRIS_MVPL_POLARITYCTRL1_PixInv1_MASK) /*! @} */ /*! @name SRCSELECT1 - Tap selection for Signature (display stream 1). Disable framegen#1 for reprogramming. */ /*! @{ */ #define IRIS_MVPL_SRCSELECT1_sig_select1_MASK (0x3U) #define IRIS_MVPL_SRCSELECT1_sig_select1_SHIFT (0U) /*! sig_select1 - Selects a source for Sig#1 unit. * 0b00..Source is FrameGen#1 output. * 0b01..Source is GammaCor#1 output. * 0b10..Source is Matrix#1 output. * 0b11..Source is Dither#1 output. */ #define IRIS_MVPL_SRCSELECT1_sig_select1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SRCSELECT1_sig_select1_SHIFT)) & IRIS_MVPL_SRCSELECT1_sig_select1_MASK) #define IRIS_MVPL_SRCSELECT1_path_select1_MASK (0x10U) #define IRIS_MVPL_SRCSELECT1_path_select1_SHIFT (4U) /*! path_select1 - Selects display#1 path. * 0b0..Framegen - Gamma - Matrix - Dither. * 0b1..Framegen - Matrix - Gamma - Dither. */ #define IRIS_MVPL_SRCSELECT1_path_select1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SRCSELECT1_path_select1_SHIFT)) & IRIS_MVPL_SRCSELECT1_path_select1_MASK) /*! @} */ /*! @name FRAMEGEN0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FRAMEGEN0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FRAMEGEN0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FRAMEGEN0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name FRAMEGEN0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSTCTRL - FrameGen Static Control Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_ShdEn_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing for RWS type configuration fields. */ #define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSTCTRL_ShdEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSTCTRL_ShdEn_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_FgSyncMode_MASK (0x6U) #define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_FgSyncMode_SHIFT (1U) /*! FgSyncMode - Determines the operating mode of the framegen unit for side-by-side synchronization. * 0b00..No side-by-side synchronization. * 0b01..Framegen is master. * 0b10..Framegen is slave. Runs in cyclic synchronization mode. * 0b11..Framegen is slave. Runs in one time synchronization mode. */ #define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_FgSyncMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSTCTRL_FgSyncMode_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSTCTRL_FgSyncMode_MASK) /*! @} */ /*! @name FRAMEGEN0_HTCFG1 - FrameGen Horizontal Timing Config Register 1 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_HTCFG1_Hact_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_HTCFG1_Hact_SHIFT (0U) /*! Hact - Horizontal size of active display area in pixels. */ #define IRIS_MVPL_FRAMEGEN0_HTCFG1_Hact(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_HTCFG1_Hact_SHIFT)) & IRIS_MVPL_FRAMEGEN0_HTCFG1_Hact_MASK) #define IRIS_MVPL_FRAMEGEN0_HTCFG1_Htotal_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_HTCFG1_Htotal_SHIFT (16U) /*! Htotal - Total horizontal size of frame in pixels. */ #define IRIS_MVPL_FRAMEGEN0_HTCFG1_Htotal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_HTCFG1_Htotal_SHIFT)) & IRIS_MVPL_FRAMEGEN0_HTCFG1_Htotal_MASK) /*! @} */ /*! @name FRAMEGEN0_HTCFG2 - FrameGen Horizontal Timing Config Register 2 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsync_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsync_SHIFT (0U) /*! Hsync - Width of HSYNC pulse in pixels. */ #define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsync_SHIFT)) & IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsync_MASK) #define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsbp_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsbp_SHIFT (16U) /*! Hsbp - Width of HSYNC pulse plus width of horizontal back porch in pixels. */ #define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsbp(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsbp_SHIFT)) & IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsbp_MASK) #define IRIS_MVPL_FRAMEGEN0_HTCFG2_HsEn_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN0_HTCFG2_HsEn_SHIFT (31U) /*! HsEn - Enables generation of HSYNC pulse. */ #define IRIS_MVPL_FRAMEGEN0_HTCFG2_HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_HTCFG2_HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_HTCFG2_HsEn_MASK) /*! @} */ /*! @name FRAMEGEN0_VTCFG1 - FrameGen Vertical Timing Config Register 1 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vact_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vact_SHIFT (0U) /*! Vact - Vertical size of active display area in lines. */ #define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vact(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_VTCFG1_Vact_SHIFT)) & IRIS_MVPL_FRAMEGEN0_VTCFG1_Vact_MASK) #define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vtotal_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vtotal_SHIFT (16U) /*! Vtotal - Total vertical size of frame in lines. */ #define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vtotal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_VTCFG1_Vtotal_SHIFT)) & IRIS_MVPL_FRAMEGEN0_VTCFG1_Vtotal_MASK) /*! @} */ /*! @name FRAMEGEN0_VTCFG2 - FrameGen Vertical Timing Config Register 2 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsync_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsync_SHIFT (0U) /*! Vsync - Width of VSYNC pulse in lines. */ #define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsync_SHIFT)) & IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsync_MASK) #define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsbp_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsbp_SHIFT (16U) /*! Vsbp - Width of VSYNC pulse plus width of vertical back porch in lines. */ #define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsbp(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsbp_SHIFT)) & IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsbp_MASK) #define IRIS_MVPL_FRAMEGEN0_VTCFG2_VsEn_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN0_VTCFG2_VsEn_SHIFT (31U) /*! VsEn - Enables generation of VSYNC pulse. */ #define IRIS_MVPL_FRAMEGEN0_VTCFG2_VsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_VTCFG2_VsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_VTCFG2_VsEn_MASK) /*! @} */ /*! @name FRAMEGEN0_INT0CONFIG - Coordinates of the trigger point for generation of the Int0 interrupt signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Col_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Col_SHIFT (0U) /*! Int0Col - Specifies on which column of the display raster the Int0 signal is triggered (1 .. Int0Col .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Col_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Col_MASK) #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0HsEn_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0HsEn_SHIFT (15U) /*! Int0HsEn - When enabled, Int0Row setting is ignored so that the interrupt occurs every line at position given by Int0Col. */ #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0HsEn_MASK) #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Row_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Row_SHIFT (16U) /*! Int0Row - Specifies on which row of the display raster the Int0 signal is triggered (1 .. Int0Row .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Row_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Row_MASK) #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0En_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0En_SHIFT (31U) /*! Int0En - Enables Int0. */ #define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0En_MASK) /*! @} */ /*! @name FRAMEGEN0_INT1CONFIG - Coordinates of the trigger point for generation of the Int1 interrupt signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Col_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Col_SHIFT (0U) /*! Int1Col - Specifies on which column of the display raster the Int1 signal is triggered (1 .. Int1Col .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Col_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Col_MASK) #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1HsEn_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1HsEn_SHIFT (15U) /*! Int1HsEn - When enabled, Int1Row setting is ignored so that the interrupt occurs every line at position given by Int1Col. */ #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1HsEn_MASK) #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Row_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Row_SHIFT (16U) /*! Int1Row - Specifies on which row of the display raster the Int1 signal is triggered (1 .. Int1Row .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Row_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Row_MASK) #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1En_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1En_SHIFT (31U) /*! Int1En - Enables Int1 (irq[1]). */ #define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1En_MASK) /*! @} */ /*! @name FRAMEGEN0_INT2CONFIG - Coordinates of the trigger point for generation of the Int2 interrupt signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Col_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Col_SHIFT (0U) /*! Int2Col - Specifies on which column of the display raster the Int2 signal is triggered (1 .. Int2Col .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Col_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Col_MASK) #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2HsEn_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2HsEn_SHIFT (15U) /*! Int2HsEn - When enabled, Int2Row setting is ignored so that the interrupt occurs every line at position given by Int2Col. */ #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2HsEn_MASK) #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Row_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Row_SHIFT (16U) /*! Int2Row - Specifies on which row of the display raster the Int2 signal is triggered (1 .. Int2Row .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Row_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Row_MASK) #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2En_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2En_SHIFT (31U) /*! Int2En - Enables Int2. */ #define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2En_MASK) /*! @} */ /*! @name FRAMEGEN0_INT3CONFIG - Coordinates of the trigger point for generation of the Int3 interrupt signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Col_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Col_SHIFT (0U) /*! Int3Col - Specifies on which column of the display raster the Int3 signal is triggered (1 .. Int3Col .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Col_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Col_MASK) #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3HsEn_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3HsEn_SHIFT (15U) /*! Int3HsEn - When enabled, Int3Row setting is ignored so that the interrupt occurs every line at position given by Int3Col. */ #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3HsEn_MASK) #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Row_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Row_SHIFT (16U) /*! Int3Row - Specifies on which row of the display raster the Int3 signal is triggered (1 .. Int3Row .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Row_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Row_MASK) #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3En_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3En_SHIFT (31U) /*! Int3En - Enables Int3. */ #define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3En_MASK) /*! @} */ /*! @name FRAMEGEN0_PKICKCONFIG - Coordinates of the trigger point for generation of the primary kick signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickCol_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickCol_SHIFT (0U) /*! PKickCol - Specifies on which column of the display raster the pkick signal is triggered (1 .. PKickCol .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickCol(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickCol_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickCol_MASK) #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickInt0En_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickInt0En_SHIFT (15U) /*! PKickInt0En - If enabled, maps the primary kick signal (pkick) on the interrupt pin int0. Overrides int0en. */ #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickInt0En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickInt0En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickInt0En_MASK) #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickRow_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickRow_SHIFT (16U) /*! PKickRow - Specifies on which row of the display raster the pkick signal is triggered (1 .. PKickRow .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickRow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickRow_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickRow_MASK) #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickEn_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickEn_SHIFT (31U) /*! PKickEn - Enables pkick signal. */ #define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickEn_MASK) /*! @} */ /*! @name FRAMEGEN0_SKICKCONFIG - Coordinates of the trigger point for generation of the secondary kick signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickCol_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickCol_SHIFT (0U) /*! SKickCol - Specifies on which column of the display raster the skick signal is triggered (1 .. SKickCol .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickCol(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickCol_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickCol_MASK) #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickInt1En_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickInt1En_SHIFT (15U) /*! SKickInt1En - If enabled, maps the secondary kick signal (skick) on the interrupt pin int1. Overrides int1en. */ #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickInt1En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickInt1En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickInt1En_MASK) #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickRow_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickRow_SHIFT (16U) /*! SKickRow - Specifies on which row of the display raster the skick signal is triggered (1 .. SKickRow .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickRow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickRow_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickRow_MASK) #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickTrig_MASK (0x40000000U) #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickTrig_SHIFT (30U) /*! SKickTrig - Select source for skick generation. * 0b0..Use internal skick signal, trigger point defined by SKickRow and SKickCol. * 0b1..Use external skick input as trigger. */ #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickTrig(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickTrig_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickTrig_MASK) #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickEn_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickEn_SHIFT (31U) /*! SKickEn - Enables generation of internal skick signal. */ #define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickEn_MASK) /*! @} */ /*! @name FRAMEGEN0_SECSTATCONFIG - Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register. */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevGoodFrames_MASK (0xFU) #define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevGoodFrames_SHIFT (0U) /*! LevGoodFrames - Number of continous correct frames that must be processed before SecSyncStat field goes 1 (in sync). */ #define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevGoodFrames(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevGoodFrames_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevGoodFrames_MASK) #define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevBadFrames_MASK (0xF0U) #define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevBadFrames_SHIFT (4U) /*! LevBadFrames - Not used. */ #define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevBadFrames(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevBadFrames_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevBadFrames_MASK) #define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevSkewInRange_MASK (0xF00U) #define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevSkewInRange_SHIFT (8U) /*! LevSkewInRange - Number of continous frames the measured skew value shall be within the range defined by SyncRangeLow and SyncRangeHigh. */ #define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevSkewInRange(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevSkewInRange_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevSkewInRange_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSRCR1 - FrameGen Skew Regulation Control Register 1. */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREn_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREn_SHIFT (0U) /*! SREn - If enabled, skew control for secondary channel is active. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREn_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRMode_MASK (0x6U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRMode_SHIFT (1U) /*! SRMode - Skew Control Operating Mode. * 0b00..Skew Regulation is off. * 0b01..Horizontal regulation enabled. * 0b10..Vertical regulation enabled. * 0b11..Both regulation modes are enabled. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRMode_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRMode_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRAdj_MASK (0x8U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRAdj_SHIFT (3U) /*! SRAdj - Enables line length adjustment for HTOTAL. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRAdj(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRAdj_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRAdj_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREven_MASK (0x10U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREven_SHIFT (4U) /*! SREven - Total line length HTOTAL is even when SRAdj is enabled. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREven(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREven_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREven_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRFastSync_MASK (0x20U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRFastSync_SHIFT (5U) /*! SRFastSync - Fast Synchronization Mode. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRFastSync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRFastSync_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRFastSync_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQAlign_MASK (0x40U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQAlign_SHIFT (6U) /*! SRQAlign - Enables alignment of HTOTAL to be a multiple of 4. Overrides SREven field. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQAlign(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQAlign_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQAlign_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQVal_MASK (0x180U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQVal_SHIFT (7U) /*! SRQVal - If SRQAlign is enabled, this field determines the fixed value of the two LSB bits of HTOTAL. * 0b00..Fixed two LSB values of HTOTAL are 0b00. * 0b01..Fixed two LSB values of HTOTAL are 0b01. * 0b10..Fixed two LSB values of HTOTAL are 0b10. * 0b11..Fixed two LSB values of HTOTAL are 0b11. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQVal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQVal_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQVal_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRDbgDisp_MASK (0x10000U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRDbgDisp_SHIFT (16U) /*! SRDbgDisp - If enabled, the pixels are displayed that are read from FIFO when secondary channel is not in sync yet. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRDbgDisp(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRDbgDisp_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRDbgDisp_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREpOff_MASK (0x20000U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREpOff_SHIFT (17U) /*! SREpOff - Disables the skew Extrapolation in blanking. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREpOff_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREpOff_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSRCR2 - FrameGen Skew Regulation Control Register 2 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMin_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMin_SHIFT (0U) /*! HTotalMin - Minimum value of htotal when horizontal regulation is enabled. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMin_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMin_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMax_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMax_SHIFT (16U) /*! HTotalMax - Maximum value of htotal when horizontal regulation is enabled. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMax_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMax_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSRCR3 - FrameGen Skew Regulation Control Register 3 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMin_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMin_SHIFT (0U) /*! VTotalMin - Minimum value of vtotal when vertical regulation is enabled. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMin_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMin_MASK) #define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMax_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMax_SHIFT (16U) /*! VTotalMax - Maximum value of vtotal when vertical regulation is enabled. */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMax_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMax_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSRCR4 - FrameGen Skew Regulation Control Register 4 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR4_TargetSkew_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FRAMEGEN0_FGSRCR4_TargetSkew_SHIFT (0U) /*! TargetSkew - Horizontal target skew value for horizontal and vertical skew regulation (signed value). */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR4_TargetSkew(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR4_TargetSkew_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR4_TargetSkew_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSRCR5 - FrameGen Skew Regulation Control Register 5 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR5_SyncRangeLow_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FRAMEGEN0_FGSRCR5_SyncRangeLow_SHIFT (0U) /*! SyncRangeLow - Sync range of horizontal and vertical skew regulation. Lower value (signed value). */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR5_SyncRangeLow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR5_SyncRangeLow_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR5_SyncRangeLow_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSRCR6 - FrameGen Skew Regulation Control Register 6 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR6_SyncRangeHigh_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FRAMEGEN0_FGSRCR6_SyncRangeHigh_SHIFT (0U) /*! SyncRangeHigh - Sync range of horizontal and vertical skew regulation. Upper value (signed value). */ #define IRIS_MVPL_FRAMEGEN0_FGSRCR6_SyncRangeHigh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR6_SyncRangeHigh_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR6_SyncRangeHigh_MASK) /*! @} */ /*! @name FRAMEGEN0_FGKSDR - FrameGen Kick System Debug Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGKSDR_PCntCplMax_MASK (0x7U) #define IRIS_MVPL_FRAMEGEN0_FGKSDR_PCntCplMax_SHIFT (0U) /*! PCntCplMax - Maximum Value for ppendcnt_cpl_s complementary primary kick counter. Do not change! */ #define IRIS_MVPL_FRAMEGEN0_FGKSDR_PCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGKSDR_PCntCplMax_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGKSDR_PCntCplMax_MASK) #define IRIS_MVPL_FRAMEGEN0_FGKSDR_SCntCplMax_MASK (0x70000U) #define IRIS_MVPL_FRAMEGEN0_FGKSDR_SCntCplMax_SHIFT (16U) /*! SCntCplMax - Maximum Value for spendcnt_cpl_s complementary secondary kick counter. Do not change! */ #define IRIS_MVPL_FRAMEGEN0_FGKSDR_SCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGKSDR_SCntCplMax_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGKSDR_SCntCplMax_MASK) /*! @} */ /*! @name FRAMEGEN0_PACFG - FrameGen Primary Area Config Register 1 (shadowed) */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_PACFG_Pstartx_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_PACFG_Pstartx_SHIFT (0U) /*! Pstartx - Primary screen upper left corner, x component. Counts from 1. Pstartx = 0 is not allowed. */ #define IRIS_MVPL_FRAMEGEN0_PACFG_Pstartx(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PACFG_Pstartx_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PACFG_Pstartx_MASK) #define IRIS_MVPL_FRAMEGEN0_PACFG_Pstarty_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_PACFG_Pstarty_SHIFT (16U) /*! Pstarty - Primary screen upper left corner, y component. Counts from 1. Pstarty = 0 is not allowed. */ #define IRIS_MVPL_FRAMEGEN0_PACFG_Pstarty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PACFG_Pstarty_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PACFG_Pstarty_MASK) /*! @} */ /*! @name FRAMEGEN0_SACFG - FrameGen Secondary Area Config Register 1 (shadowed) */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_SACFG_Sstartx_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_SACFG_Sstartx_SHIFT (0U) /*! Sstartx - Secondary screen upper left corner, x component. Counts from 1 . Sstartx = 0 is not allowed. */ #define IRIS_MVPL_FRAMEGEN0_SACFG_Sstartx(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SACFG_Sstartx_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SACFG_Sstartx_MASK) #define IRIS_MVPL_FRAMEGEN0_SACFG_Sstarty_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN0_SACFG_Sstarty_SHIFT (16U) /*! Sstarty - Secondary screen upper left corner, y component. Counts from 1 . Sstarty = 0 is not allowed. */ #define IRIS_MVPL_FRAMEGEN0_SACFG_Sstarty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SACFG_Sstarty_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SACFG_Sstarty_MASK) /*! @} */ /*! @name FRAMEGEN0_FGINCTRL - FrameGen Input Control Register (shadowed) */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGINCTRL_FgDm_MASK (0x7U) #define IRIS_MVPL_FRAMEGEN0_FGINCTRL_FgDm_SHIFT (0U) /*! FgDm - Frame Generator Display Mode. * 0b000..Black Color Background is shown. * 0b001..Constant Color Background is shown. * 0b010..Primary input only is shown. * 0b011..Secondary input only is shown. * 0b100..Both inputs overlaid with primary on top. * 0b101..Both inputs overlaid with secondary on top. * 0b110..White color background with test pattern is shown. */ #define IRIS_MVPL_FRAMEGEN0_FGINCTRL_FgDm(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRL_FgDm_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRL_FgDm_MASK) #define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnPrimAlpha_MASK (0x8U) #define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnPrimAlpha_SHIFT (3U) /*! EnPrimAlpha - When enabled, alpha plane of primary channel is considered for screen composition. */ #define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnPrimAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnPrimAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnPrimAlpha_MASK) #define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnSecAlpha_MASK (0x10U) #define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnSecAlpha_SHIFT (4U) /*! EnSecAlpha - When enabled, alpha plane of secondary channel is considered for screen composition. */ #define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnSecAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnSecAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnSecAlpha_MASK) /*! @} */ /*! @name FRAMEGEN0_FGINCTRLPANIC - FrameGen Input Control Panic Register (shadowed) */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_FgDmPanic_MASK (0x7U) #define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_FgDmPanic_SHIFT (0U) /*! FgDmPanic - Frame Generator Display Mode when Panic Switch active. * 0b000..Black Color Background is shown. * 0b001..Constant Color Background is shown. * 0b010..Primary input only is shown. * 0b011..Secondary input only is shown. * 0b100..Both inputs overlaid with primary on top. * 0b101..Both inputs overlaid with secondary on top. * 0b110..White color background with test pattern is shown. */ #define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_FgDmPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_FgDmPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_FgDmPanic_MASK) #define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnPrimAlphaPanic_MASK (0x8U) #define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnPrimAlphaPanic_SHIFT (3U) /*! EnPrimAlphaPanic - When enabled, alpha plane of primary channel is considered for screen composition. */ #define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnPrimAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnPrimAlphaPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnPrimAlphaPanic_MASK) #define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnSecAlphaPanic_MASK (0x10U) #define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnSecAlphaPanic_SHIFT (4U) /*! EnSecAlphaPanic - When enabled, alpha plane of secondary channel is considered for screen composition. */ #define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnSecAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnSecAlphaPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnSecAlphaPanic_MASK) /*! @} */ /*! @name FRAMEGEN0_FGCCR - FrameGen Constant Color Register (shadowed) */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcBlue_MASK (0x3FFU) #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcBlue_SHIFT (0U) /*! CcBlue - Constant color - blue component. */ #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCCR_CcBlue_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCCR_CcBlue_MASK) #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcGreen_MASK (0xFFC00U) #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcGreen_SHIFT (10U) /*! CcGreen - Constant color - green component. */ #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCCR_CcGreen_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCCR_CcGreen_MASK) #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcRed_MASK (0x3FF00000U) #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcRed_SHIFT (20U) /*! CcRed - Constant color - red component. */ #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCCR_CcRed_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCCR_CcRed_MASK) #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcAlpha_MASK (0x40000000U) #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcAlpha_SHIFT (30U) /*! CcAlpha - Constant color - alpha value. */ #define IRIS_MVPL_FRAMEGEN0_FGCCR_CcAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCCR_CcAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCCR_CcAlpha_MASK) /*! @} */ /*! @name FRAMEGEN0_FGENABLE - FrameGen Enable Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGENABLE_FgEn_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN0_FGENABLE_FgEn_SHIFT (0U) /*! FgEn - Frame Generator Enable. */ #define IRIS_MVPL_FRAMEGEN0_FGENABLE_FgEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGENABLE_FgEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGENABLE_FgEn_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSLR - FrameGen Shadow Load Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSLR_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN0_FGSLR_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Generate shadow load token. */ #define IRIS_MVPL_FRAMEGEN0_FGSLR_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSLR_ShdTokGen_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSLR_ShdTokGen_MASK) /*! @} */ /*! @name FRAMEGEN0_FGENSTS - FrameGen Enable Status Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGENSTS_EnSts_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN0_FGENSTS_EnSts_SHIFT (0U) /*! EnSts - Indicates the current operating mode of the frame generator. */ #define IRIS_MVPL_FRAMEGEN0_FGENSTS_EnSts(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGENSTS_EnSts_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGENSTS_EnSts_MASK) #define IRIS_MVPL_FRAMEGEN0_FGENSTS_PanicStat_MASK (0x2U) #define IRIS_MVPL_FRAMEGEN0_FGENSTS_PanicStat_SHIFT (1U) /*! PanicStat - Current status of panic mode (0=normal operation mode, 1=panic mode; not locked). */ #define IRIS_MVPL_FRAMEGEN0_FGENSTS_PanicStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGENSTS_PanicStat_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGENSTS_PanicStat_MASK) /*! @} */ /*! @name FRAMEGEN0_FGTIMESTAMP - Time stamp status. */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_LineIndex_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_LineIndex_SHIFT (0U) /*! LineIndex - Index of the output line that is currently generated (starts with 0 for first active output line). */ #define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_LineIndex(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_LineIndex_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_LineIndex_MASK) #define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_FrameIndex_MASK (0xFFFFC000U) #define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_FrameIndex_SHIFT (14U) /*! FrameIndex - Index of the output frame that is currently generated (starts with 0 after reset for first output frame). */ #define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_FrameIndex(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_FrameIndex_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_FrameIndex_MASK) /*! @} */ /*! @name FRAMEGEN0_FGCHSTAT - FrameGen Channel Status Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PFifoEmpty_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PFifoEmpty_SHIFT (0U) /*! PFifoEmpty - Read request to empty primary pixel FIFO detected. (Bit locked when 1, clear by using ClrPrimStat). */ #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PFifoEmpty_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PFifoEmpty_MASK) #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PrimSyncStat_MASK (0x100U) #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PrimSyncStat_SHIFT (8U) /*! PrimSyncStat - Current status primary channel synchronization (0 = out of sync (frame tearing), * 1 = in sync (normal operation); not locked). */ #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PrimSyncStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PrimSyncStat_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PrimSyncStat_MASK) #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SFifoEmpty_MASK (0x10000U) #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SFifoEmpty_SHIFT (16U) /*! SFifoEmpty - Read request to empty secondary pixel FIFO detected. (bit locked when 1, clear by using ClrSecStat). */ #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SFifoEmpty_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SFifoEmpty_MASK) #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SkewRangeErr_MASK (0x20000U) #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SkewRangeErr_SHIFT (17U) /*! SkewRangeErr - The secondary channel skew value has run out of the limit defined by SyncRangeLow * and SyncRangeHigh. (bit locked when 1, clear by using ClrSecStat). */ #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SkewRangeErr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SkewRangeErr_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SkewRangeErr_MASK) #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SecSyncStat_MASK (0x1000000U) #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SecSyncStat_SHIFT (24U) /*! SecSyncStat - Current status secondary channel synchronization (0 = out of sync, 1 = in sync; not locked). */ #define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SecSyncStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SecSyncStat_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SecSyncStat_MASK) /*! @} */ /*! @name FRAMEGEN0_FGCHSTATCLR - FrameGen Channel Status Clear Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrPrimStat_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrPrimStat_SHIFT (0U) /*! ClrPrimStat - Clears PFifoEmpty in FgChStat register. */ #define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrPrimStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrPrimStat_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrPrimStat_MASK) #define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrSecStat_MASK (0x10000U) #define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrSecStat_SHIFT (16U) /*! ClrSecStat - Clears SFifoEmpty and SkewRangeErr in FgChStat register. */ #define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrSecStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrSecStat_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrSecStat_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSKEWMON - FrameGen Skew Monitor Register for Secondary Channel Skew Control */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSKEWMON_SkewMon_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FRAMEGEN0_FGSKEWMON_SkewMon_SHIFT (0U) /*! SkewMon - Current skew value monitor for secondary channel skew control. Updated with hlast. */ #define IRIS_MVPL_FRAMEGEN0_FGSKEWMON_SkewMon(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSKEWMON_SkewMon_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSKEWMON_SkewMon_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSFIFOMIN - FrameGen Secondary FIFO Min Fill Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSFIFOMIN_SFifoMin_MASK (0xFFFU) #define IRIS_MVPL_FRAMEGEN0_FGSFIFOMIN_SFifoMin_SHIFT (0U) /*! SFifoMin - Shows the minimal fill level of the secondary channel pixel FIFO. */ #define IRIS_MVPL_FRAMEGEN0_FGSFIFOMIN_SFifoMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSFIFOMIN_SFifoMin_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSFIFOMIN_SFifoMin_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSFIFOMAX - FrameGen Secondary FIFO Max Fill Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSFIFOMAX_SFifoMax_MASK (0xFFFU) #define IRIS_MVPL_FRAMEGEN0_FGSFIFOMAX_SFifoMax_SHIFT (0U) /*! SFifoMax - Shows the maximal fill level of the secondary channel pixel FIFO. */ #define IRIS_MVPL_FRAMEGEN0_FGSFIFOMAX_SFifoMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSFIFOMAX_SFifoMax_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSFIFOMAX_SFifoMax_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSFIFOFILLCLR - FrameGen Secondary FIFO Fill Clear Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSFIFOFILLCLR_SFifoFillClr_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN0_FGSFIFOFILLCLR_SFifoFillClr_SHIFT (0U) /*! SFifoFillClr - Write for clearing register FgSFifoMin and FgSFifoMax. */ #define IRIS_MVPL_FRAMEGEN0_FGSFIFOFILLCLR_SFifoFillClr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSFIFOFILLCLR_SFifoFillClr_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSFIFOFILLCLR_SFifoFillClr_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSREPD - FrameGen Skew Regulation ExtraPolation Debug Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSREPD_EpVal_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FRAMEGEN0_FGSREPD_EpVal_SHIFT (0U) /*! EpVal - Calculated value for line skew extrapolation in blanking. */ #define IRIS_MVPL_FRAMEGEN0_FGSREPD_EpVal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSREPD_EpVal_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSREPD_EpVal_MASK) /*! @} */ /*! @name FRAMEGEN0_FGSRFTD - FrameGen Skew Regulation Frame Total Debug Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN0_FGSRFTD_FrTot_MASK (0xFFFFFFFU) #define IRIS_MVPL_FRAMEGEN0_FGSRFTD_FrTot_SHIFT (0U) /*! FrTot - Measured value for frame total measured in display clock cycles. */ #define IRIS_MVPL_FRAMEGEN0_FGSRFTD_FrTot(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRFTD_FrTot_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRFTD_FrTot_MASK) /*! @} */ /*! @name MATRIX0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_MATRIX0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name MATRIX0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_MATRIX0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_MATRIX0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_MATRIX0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_MATRIX0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_MATRIX0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_MATRIX0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_MATRIX0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_MATRIX0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name MATRIX0_STATICCONTROL - Color Matrix static control register */ /*! @{ */ #define IRIS_MVPL_MATRIX0_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_MATRIX0_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_MATRIX0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX0_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name MATRIX0_CONTROL - Color Matrix control register */ /*! @{ */ #define IRIS_MVPL_MATRIX0_CONTROL_MODE_MASK (0x3U) #define IRIS_MVPL_MATRIX0_CONTROL_MODE_SHIFT (0U) /*! MODE - Operation mode for color matrix * 0b00..Module in neutral mode, input data is bypassed * 0b01..Module in matrix mode, input data is multiplied with matrix values * 0b10..Module in alpha pre-multiplication mode, input color is multiplied with input alpha * 0b11..Reserved, do not use */ #define IRIS_MVPL_MATRIX0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX0_CONTROL_MODE_MASK) #define IRIS_MVPL_MATRIX0_CONTROL_AlphaMask_MASK (0x10U) #define IRIS_MVPL_MATRIX0_CONTROL_AlphaMask_SHIFT (4U) /*! AlphaMask - Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value * smaller than 0.5 are by-passed unchanged. */ #define IRIS_MVPL_MATRIX0_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX0_CONTROL_AlphaMask_MASK) #define IRIS_MVPL_MATRIX0_CONTROL_AlphaInvert_MASK (0x20U) #define IRIS_MVPL_MATRIX0_CONTROL_AlphaInvert_SHIFT (5U) /*! AlphaInvert - Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha * value greater or equal 0.5 are by-passed). */ #define IRIS_MVPL_MATRIX0_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX0_CONTROL_AlphaInvert_MASK) /*! @} */ /*! @name MATRIX0_RED0 - Matrix values for calculation of the red output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_RED0_A11_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX0_RED0_A11_SHIFT (0U) /*! A11 - Value for red input. */ #define IRIS_MVPL_MATRIX0_RED0_A11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX0_RED0_A11_MASK) #define IRIS_MVPL_MATRIX0_RED0_A12_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX0_RED0_A12_SHIFT (16U) /*! A12 - Value for green input. */ #define IRIS_MVPL_MATRIX0_RED0_A12(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX0_RED0_A12_MASK) /*! @} */ /*! @name MATRIX0_RED1 - Matrix values for calculation of the red output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_RED1_A13_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX0_RED1_A13_SHIFT (0U) /*! A13 - Value for blue input. */ #define IRIS_MVPL_MATRIX0_RED1_A13(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX0_RED1_A13_MASK) #define IRIS_MVPL_MATRIX0_RED1_A14_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX0_RED1_A14_SHIFT (16U) /*! A14 - Value for alpha input. */ #define IRIS_MVPL_MATRIX0_RED1_A14(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX0_RED1_A14_MASK) /*! @} */ /*! @name MATRIX0_GREEN0 - Matrix values for calculation of the green output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_GREEN0_A21_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX0_GREEN0_A21_SHIFT (0U) /*! A21 - Value for red input. */ #define IRIS_MVPL_MATRIX0_GREEN0_A21(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX0_GREEN0_A21_MASK) #define IRIS_MVPL_MATRIX0_GREEN0_A22_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX0_GREEN0_A22_SHIFT (16U) /*! A22 - Value for green input. */ #define IRIS_MVPL_MATRIX0_GREEN0_A22(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX0_GREEN0_A22_MASK) /*! @} */ /*! @name MATRIX0_GREEN1 - Matrix values for calculation of the green output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_GREEN1_A23_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX0_GREEN1_A23_SHIFT (0U) /*! A23 - Value for blue input. */ #define IRIS_MVPL_MATRIX0_GREEN1_A23(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX0_GREEN1_A23_MASK) #define IRIS_MVPL_MATRIX0_GREEN1_A24_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX0_GREEN1_A24_SHIFT (16U) /*! A24 - Value for alpha input. */ #define IRIS_MVPL_MATRIX0_GREEN1_A24(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX0_GREEN1_A24_MASK) /*! @} */ /*! @name MATRIX0_BLUE0 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_BLUE0_A31_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX0_BLUE0_A31_SHIFT (0U) /*! A31 - Value for red input. */ #define IRIS_MVPL_MATRIX0_BLUE0_A31(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX0_BLUE0_A31_MASK) #define IRIS_MVPL_MATRIX0_BLUE0_A32_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX0_BLUE0_A32_SHIFT (16U) /*! A32 - Value for green input. */ #define IRIS_MVPL_MATRIX0_BLUE0_A32(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX0_BLUE0_A32_MASK) /*! @} */ /*! @name MATRIX0_BLUE1 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_BLUE1_A33_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX0_BLUE1_A33_SHIFT (0U) /*! A33 - Value for blue input. */ #define IRIS_MVPL_MATRIX0_BLUE1_A33(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX0_BLUE1_A33_MASK) #define IRIS_MVPL_MATRIX0_BLUE1_A34_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX0_BLUE1_A34_SHIFT (16U) /*! A34 - Value for alpha input. */ #define IRIS_MVPL_MATRIX0_BLUE1_A34(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX0_BLUE1_A34_MASK) /*! @} */ /*! @name MATRIX0_ALPHA0 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_ALPHA0_A41_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX0_ALPHA0_A41_SHIFT (0U) /*! A41 - Value for red input. */ #define IRIS_MVPL_MATRIX0_ALPHA0_A41(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX0_ALPHA0_A41_MASK) #define IRIS_MVPL_MATRIX0_ALPHA0_A42_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX0_ALPHA0_A42_SHIFT (16U) /*! A42 - Value for green input. */ #define IRIS_MVPL_MATRIX0_ALPHA0_A42(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX0_ALPHA0_A42_MASK) /*! @} */ /*! @name MATRIX0_ALPHA1 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_ALPHA1_A43_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX0_ALPHA1_A43_SHIFT (0U) /*! A43 - Value for blue input. */ #define IRIS_MVPL_MATRIX0_ALPHA1_A43(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX0_ALPHA1_A43_MASK) #define IRIS_MVPL_MATRIX0_ALPHA1_A44_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX0_ALPHA1_A44_SHIFT (16U) /*! A44 - Value for alpha input. */ #define IRIS_MVPL_MATRIX0_ALPHA1_A44(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX0_ALPHA1_A44_MASK) /*! @} */ /*! @name MATRIX0_OFFSETVECTOR0 - Offset vectors for red and green output. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C1_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C1_SHIFT (0U) /*! C1 - Red output offset. */ #define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C1_MASK) #define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C2_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C2_SHIFT (16U) /*! C2 - Green output offset. */ #define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C2_MASK) /*! @} */ /*! @name MATRIX0_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C3_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C3_SHIFT (0U) /*! C3 - Blue output offset. */ #define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C3_MASK) #define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C4_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C4_SHIFT (16U) /*! C4 - Alpha output offset. Note that the 8-bit alpha input is up-scaled to 10-bit, before the * matrix and this offset is applied, and down-scaled to 8-bit for output afterwards. */ #define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C4_MASK) /*! @} */ /*! @name MATRIX0_LASTCONTROLWORD - Value of last received control word, for debugging. */ /*! @{ */ #define IRIS_MVPL_MATRIX0_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX0_LASTCONTROLWORD_L_VAL_SHIFT (0U) /*! L_VAL - Value of last received control word. For debug purposes only, read when stable only, * otherwise read data might be corrupted. */ #define IRIS_MVPL_MATRIX0_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX0_LASTCONTROLWORD_L_VAL_MASK) /*! @} */ /*! @name GAMMACOR0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_GAMMACOR0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_GAMMACOR0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_GAMMACOR0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name GAMMACOR0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_GAMMACOR0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name GAMMACOR0_STATICCONTROL - Static control settings. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_GAMMACOR0_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_BlueWriteEnable_MASK (0x2U) #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_BlueWriteEnable_SHIFT (1U) /*! BlueWriteEnable - Write enable for the blue color sampling point entries. */ #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_BlueWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_STATICCONTROL_BlueWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR0_STATICCONTROL_BlueWriteEnable_MASK) #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_GreenWriteEnable_MASK (0x4U) #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_GreenWriteEnable_SHIFT (2U) /*! GreenWriteEnable - Write enable for the green color sampling point entries. */ #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_GreenWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_STATICCONTROL_GreenWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR0_STATICCONTROL_GreenWriteEnable_MASK) #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_RedWriteEnable_MASK (0x8U) #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_RedWriteEnable_SHIFT (3U) /*! RedWriteEnable - Write enable for the red color sampling point entries. */ #define IRIS_MVPL_GAMMACOR0_STATICCONTROL_RedWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_STATICCONTROL_RedWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR0_STATICCONTROL_RedWriteEnable_MASK) /*! @} */ /*! @name GAMMACOR0_LUTSTART - Start values for look-up table programming. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR0_LUTSTART_StartBlue_MASK (0x3FFU) #define IRIS_MVPL_GAMMACOR0_LUTSTART_StartBlue_SHIFT (0U) /*! StartBlue - Start value for blue or chroma (V) channel. */ #define IRIS_MVPL_GAMMACOR0_LUTSTART_StartBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTSTART_StartBlue_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTSTART_StartBlue_MASK) #define IRIS_MVPL_GAMMACOR0_LUTSTART_StartGreen_MASK (0xFFC00U) #define IRIS_MVPL_GAMMACOR0_LUTSTART_StartGreen_SHIFT (10U) /*! StartGreen - Start value for green or chroma (U) channel. */ #define IRIS_MVPL_GAMMACOR0_LUTSTART_StartGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTSTART_StartGreen_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTSTART_StartGreen_MASK) #define IRIS_MVPL_GAMMACOR0_LUTSTART_StartRed_MASK (0x3FF00000U) #define IRIS_MVPL_GAMMACOR0_LUTSTART_StartRed_SHIFT (20U) /*! StartRed - Start value for red or luma (Y) channel. */ #define IRIS_MVPL_GAMMACOR0_LUTSTART_StartRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTSTART_StartRed_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTSTART_StartRed_MASK) /*! @} */ /*! @name GAMMACOR0_LUTDELTAS - Delta values for look-up table programming. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaBlue_MASK (0x3FFU) #define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaBlue_SHIFT (0U) /*! DeltaBlue - Delta value for blue or chroma (V) channel. */ #define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaBlue_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaBlue_MASK) #define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaGreen_MASK (0xFFC00U) #define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaGreen_SHIFT (10U) /*! DeltaGreen - Delta value for green or chroma (U) channel. */ #define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaGreen_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaGreen_MASK) #define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaRed_MASK (0x3FF00000U) #define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaRed_SHIFT (20U) /*! DeltaRed - Delta value for red or luma (Y) channel. */ #define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaRed_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaRed_MASK) /*! @} */ /*! @name GAMMACOR0_CONTROL - Dynamic control settings. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR0_CONTROL_Mode_MASK (0x1U) #define IRIS_MVPL_GAMMACOR0_CONTROL_Mode_SHIFT (0U) /*! Mode - Operation mode for gamma correction unit * 0b0..Module in neutral mode, input data is bypassed to the output. * 0b1..Module in gamma correction mode. */ #define IRIS_MVPL_GAMMACOR0_CONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_CONTROL_Mode_SHIFT)) & IRIS_MVPL_GAMMACOR0_CONTROL_Mode_MASK) #define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaMask_MASK (0x10U) #define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaMask_SHIFT (4U) /*! AlphaMask - Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value * smaller than 0.5 are by-passed unchanged. */ #define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_GAMMACOR0_CONTROL_AlphaMask_MASK) #define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaInvert_MASK (0x20U) #define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaInvert_SHIFT (5U) /*! AlphaInvert - Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha * value greater or equal 0.5 are by-passed). */ #define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_GAMMACOR0_CONTROL_AlphaInvert_MASK) /*! @} */ /*! @name GAMMACOR0_STATUS - Internal status bits. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR0_STATUS_WriteTimeout_MASK (0x1U) #define IRIS_MVPL_GAMMACOR0_STATUS_WriteTimeout_SHIFT (0U) /*! WriteTimeout - Timeout detected when writing to the sampling point table. */ #define IRIS_MVPL_GAMMACOR0_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_GAMMACOR0_STATUS_WriteTimeout_MASK) /*! @} */ /*! @name GAMMACOR0_LASTCONTROLWORD - Value of last received control word. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR0_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_GAMMACOR0_LASTCONTROLWORD_L_VAL_SHIFT (0U) /*! L_VAL - Value of last received control word. For debug purposes only, read when stable only, * otherwise read data might be corrupted. */ #define IRIS_MVPL_GAMMACOR0_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_GAMMACOR0_LASTCONTROLWORD_L_VAL_MASK) /*! @} */ /*! @name DITHER0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_DITHER0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_DITHER0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_DITHER0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_DITHER0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name DITHER0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_DITHER0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_DITHER0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_DITHER0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_DITHER0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_DITHER0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_DITHER0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_DITHER0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_DITHER0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_DITHER0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_DITHER0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_DITHER0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_DITHER0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name DITHER0_CONTROL - Dither Unit common control. */ /*! @{ */ #define IRIS_MVPL_DITHER0_CONTROL_mode_MASK (0x1U) #define IRIS_MVPL_DITHER0_CONTROL_mode_SHIFT (0U) /*! mode - Mode which switches Dither Unit on/off. * 0b0..Neutral mode. Pixels by-pass the Dither Unit, all other settings are ignored. * 0b1..Dither Unit is active. */ #define IRIS_MVPL_DITHER0_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_CONTROL_mode_SHIFT)) & IRIS_MVPL_DITHER0_CONTROL_mode_MASK) /*! @} */ /*! @name DITHER0_DITHERCONTROL - Dither Unit processing control. */ /*! @{ */ #define IRIS_MVPL_DITHER0_DITHERCONTROL_blue_range_select_MASK (0x7U) #define IRIS_MVPL_DITHER0_DITHERCONTROL_blue_range_select_SHIFT (0U) /*! blue_range_select - Mode which sets the reduction of component widths. * 0b010..Reduces blue component width from 10 bit to 8bit. * 0b011..Reduces blue component width from 10 bit to 7bit. * 0b100..Reduces blue component width from 10 bit to 6bit. * 0b101..Reduces blue component width from 10 bit to 5bit. */ #define IRIS_MVPL_DITHER0_DITHERCONTROL_blue_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_blue_range_select_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_blue_range_select_MASK) #define IRIS_MVPL_DITHER0_DITHERCONTROL_green_range_select_MASK (0x70U) #define IRIS_MVPL_DITHER0_DITHERCONTROL_green_range_select_SHIFT (4U) /*! green_range_select - Mode which sets the reduction of component widths. * 0b010..Reduces green component width from 10 bit to 8bit. * 0b011..Reduces green component width from 10 bit to 7bit. * 0b100..Reduces green component width from 10 bit to 6bit. * 0b101..Reduces green component width from 10 bit to 5bit. */ #define IRIS_MVPL_DITHER0_DITHERCONTROL_green_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_green_range_select_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_green_range_select_MASK) #define IRIS_MVPL_DITHER0_DITHERCONTROL_red_range_select_MASK (0x700U) #define IRIS_MVPL_DITHER0_DITHERCONTROL_red_range_select_SHIFT (8U) /*! red_range_select - Mode which sets the reduction of component widths. * 0b010..Reduces red component width from 10 bit to 8bit. * 0b011..Reduces red component width from 10 bit to 7bit. * 0b100..Reduces red component width from 10 bit to 6bit. * 0b101..Reduces red component width from 10 bit to 5bit. */ #define IRIS_MVPL_DITHER0_DITHERCONTROL_red_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_red_range_select_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_red_range_select_MASK) #define IRIS_MVPL_DITHER0_DITHERCONTROL_offset_select_MASK (0x10000U) #define IRIS_MVPL_DITHER0_DITHERCONTROL_offset_select_SHIFT (16U) /*! offset_select - Selects the method how the dither offset is calculated. * 0b0..Offset is a bayer matrix value, which is selected according to pixel frame position. * 0b1..Offset is the sum from a bayer matrix value, which is selected according to pixel frame position, and a * value from a regular sequence, which changes each frame. */ #define IRIS_MVPL_DITHER0_DITHERCONTROL_offset_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_offset_select_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_offset_select_MASK) #define IRIS_MVPL_DITHER0_DITHERCONTROL_algo_select_MASK (0x300000U) #define IRIS_MVPL_DITHER0_DITHERCONTROL_algo_select_SHIFT (20U) /*! algo_select - The number of output colors that can virtually be displayed by dithering is * slightly lower than the number of physical input colors. This field selects how the mapping is done. * 0b01..Best possible resolution for most dark colors. Adds a diminutive offset to overall image brightness. * 0b10..Preserves overall image brightness. Cannot resolve most dark and most bright colors. All codes in-between are distributed perfectly smooth. * 0b11..Preserves overall image brightness. Best possible distribution of color codes over complete range. */ #define IRIS_MVPL_DITHER0_DITHERCONTROL_algo_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_algo_select_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_algo_select_MASK) #define IRIS_MVPL_DITHER0_DITHERCONTROL_alpha_mode_MASK (0x3000000U) #define IRIS_MVPL_DITHER0_DITHERCONTROL_alpha_mode_SHIFT (24U) /*! alpha_mode - Enables/disables that dithering can be switched by alpha bit. * 0b00..The alpha bit is not considered. * 0b01..Red, green and blue components are only dithered, if the alpha bit is 1. * 0b10..Red, green and blue components are only dithered, if the alpha bit is 0. */ #define IRIS_MVPL_DITHER0_DITHERCONTROL_alpha_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_alpha_mode_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_alpha_mode_MASK) /*! @} */ /*! @name DITHER0_RELEASE - Dither Unit release. */ /*! @{ */ #define IRIS_MVPL_DITHER0_RELEASE_subversion_MASK (0xFFU) #define IRIS_MVPL_DITHER0_RELEASE_subversion_SHIFT (0U) /*! subversion - Dither Unit subversion. */ #define IRIS_MVPL_DITHER0_RELEASE_subversion(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_RELEASE_subversion_SHIFT)) & IRIS_MVPL_DITHER0_RELEASE_subversion_MASK) #define IRIS_MVPL_DITHER0_RELEASE_version_MASK (0xFF00U) #define IRIS_MVPL_DITHER0_RELEASE_version_SHIFT (8U) /*! version - Dither Unit version. */ #define IRIS_MVPL_DITHER0_RELEASE_version(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_RELEASE_version_SHIFT)) & IRIS_MVPL_DITHER0_RELEASE_version_MASK) /*! @} */ /*! @name TCON0_SSQCNTS - The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field */ /*! @{ */ #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQY_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQY_SHIFT (0U) /*! SSQCNTS_SEQY - Y scan position */ #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQY_SHIFT)) & IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQY_MASK) #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_FIELD_MASK (0x8000U) #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_FIELD_SHIFT (15U) /*! SSQCNTS_FIELD - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_FIELD_SHIFT)) & IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_FIELD_MASK) #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQX_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQX_SHIFT (16U) /*! SSQCNTS_SEQX - X scan position */ #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQX_SHIFT)) & IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQX_MASK) #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_OUT_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_OUT_SHIFT (31U) /*! SSQCNTS_OUT - This bit holds the value (0,1) to be output when the X/Y scan position is reached. */ #define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_OUT(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_OUT_SHIFT)) & IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_OUT_MASK) /*! @} */ /*! @name TCON0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_TCON0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_TCON0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_TCON0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name TCON0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_TCON0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_TCON0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_TCON0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_TCON0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_TCON0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_TCON0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_TCON0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_TCON0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_TCON0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_TCON0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_TCON0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_TCON0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name TCON0_SSQCYCLE - This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles */ /*! @{ */ #define IRIS_MVPL_TCON0_SSQCYCLE_SSQCYCLE_MASK (0x3FU) #define IRIS_MVPL_TCON0_SSQCYCLE_SSQCYCLE_SHIFT (0U) /*! SSQCYCLE - Sequencer cycle length (number -1) of sequencer cycles */ #define IRIS_MVPL_TCON0_SSQCYCLE_SSQCYCLE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SSQCYCLE_SSQCYCLE_SHIFT)) & IRIS_MVPL_TCON0_SSQCYCLE_SSQCYCLE_MASK) /*! @} */ /*! @name TCON0_SWRESET - TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document Note: 1/ if tsig[11] pulse=n*pixel_period, (n-1)*0xFF will be blent between ResetWordStart and ResetWordEnd into miniLVDS stream Note: 2/ if( EnResetWord=0) Reset-Pulse (ResetWordStart,ResetWordEnd) won't be blent into miniLVDS stream. Pixels will be transfered unchanged */ /*! @{ */ #define IRIS_MVPL_TCON0_SWRESET_SWReset_MASK (0x1U) #define IRIS_MVPL_TCON0_SWRESET_SWReset_SHIFT (0U) /*! SWReset - Software reset * 0b0..operation mode * 0b1..So long SWReset = 0x1 tcon is in 'SW reset state' and it is released by internal logic (SWReset is * released and end of frame arrived), read: 0b: reset not active 1b: reset active (that means NO pixel of video * frame is excepted until 'SW reset state' is released) */ #define IRIS_MVPL_TCON0_SWRESET_SWReset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SWRESET_SWReset_SHIFT)) & IRIS_MVPL_TCON0_SWRESET_SWReset_MASK) #define IRIS_MVPL_TCON0_SWRESET_EnResetWord_MASK (0xFFF0U) #define IRIS_MVPL_TCON0_SWRESET_EnResetWord_SHIFT (4U) /*! EnResetWord - Enable to blend ResetWord into miniLVDS stream EnResetWord[5:0] mapped to enable * Blending Reset Pulse to [RLV5.RLV0]. EnResetWord[11:6] mapped to enable Blending Reset Pulse to * [LLV5.LLV0]. */ #define IRIS_MVPL_TCON0_SWRESET_EnResetWord(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SWRESET_EnResetWord_SHIFT)) & IRIS_MVPL_TCON0_SWRESET_EnResetWord_MASK) #define IRIS_MVPL_TCON0_SWRESET_ResetWordEnd_MASK (0xFF0000U) #define IRIS_MVPL_TCON0_SWRESET_ResetWordEnd_SHIFT (16U) /*! ResetWordEnd - 8-Bits Value, that will be blent on falling edge of tsig[11] into miniLVDS stream */ #define IRIS_MVPL_TCON0_SWRESET_ResetWordEnd(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SWRESET_ResetWordEnd_SHIFT)) & IRIS_MVPL_TCON0_SWRESET_ResetWordEnd_MASK) #define IRIS_MVPL_TCON0_SWRESET_ResetWordStart_MASK (0xFF000000U) #define IRIS_MVPL_TCON0_SWRESET_ResetWordStart_SHIFT (24U) /*! ResetWordStart - 8-Bits Value, that will be blent on rising edge of tsig[11] into miniLVDS stream */ #define IRIS_MVPL_TCON0_SWRESET_ResetWordStart(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SWRESET_ResetWordStart_SHIFT)) & IRIS_MVPL_TCON0_SWRESET_ResetWordStart_MASK) /*! @} */ /*! @name TCON0_CTRL - TCON Control register */ /*! @{ */ #define IRIS_MVPL_TCON0_CTRL_ChannelMode_MASK (0x3U) #define IRIS_MVPL_TCON0_CTRL_ChannelMode_SHIFT (0U) /*! ChannelMode - Selects one of tcon operation modes, SINGLE, DUAL_INTERLEAVED or DUAL_SPLIT. If * MiniLVDS operation is selected (EnLVDS = ENABLE_LVDS and LVDSMode = Mini_LVDS), tcon operates in * MiniLVDS mode, indepent on the Value of channelMode. SplitPosition must be specified in * MiniLVDS operation in DUAL_INTERLEAVED or DUAL_SPLIT mode, the horizontal parameter of signal * generator have to set twice as they are specified in the panel-specification (panel: 320, * tsig_start 0, tsig_stop 320 on DUAL-Mode : tsig_start 0, tsig_stop 640 ... (SplitPosition is * automatically adjusted) ) * 0b00..Single pixel mode. Both channels channel are active at full pixel clock. If bitmap of both panels are the same, both panels are identical * 0b01..Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives display columns with even and 2nd one with odd index. * 0b10..Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives the left and 2nd * one the righ half of the display. Note : data_en is needed in this mode */ #define IRIS_MVPL_TCON0_CTRL_ChannelMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_ChannelMode_SHIFT)) & IRIS_MVPL_TCON0_CTRL_ChannelMode_MASK) #define IRIS_MVPL_TCON0_CTRL_tcon0_sync_MASK (0x4U) #define IRIS_MVPL_TCON0_CTRL_tcon0_sync_SHIFT (2U) /*! tcon0_sync - Select synchronization between hsync/vsync and hlast/vlast * 0b0..tcon timing generator synchronized to hlast, vlast * 0b1..tcon timing generator synchronized to hsync, vsync where horizontal synchronization is synchronized at the falling edge of hsync */ #define IRIS_MVPL_TCON0_CTRL_tcon0_sync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_tcon0_sync_SHIFT)) & IRIS_MVPL_TCON0_CTRL_tcon0_sync_MASK) #define IRIS_MVPL_TCON0_CTRL_Bypass_MASK (0x8U) #define IRIS_MVPL_TCON0_CTRL_Bypass_SHIFT (3U) /*! Bypass - Bypassing synchronization * 0b0..tcon operation mode * 0b1..tcon in Bypass mode. input pixel and its sync-signals are bypassed to tcon-output */ #define IRIS_MVPL_TCON0_CTRL_Bypass(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_Bypass_SHIFT)) & IRIS_MVPL_TCON0_CTRL_Bypass_MASK) #define IRIS_MVPL_TCON0_CTRL_Inv_Ctrl_MASK (0xF0U) #define IRIS_MVPL_TCON0_CTRL_Inv_Ctrl_SHIFT (4U) /*! Inv_Ctrl - Minimize the toggle rate of tcon output for display panel, that supports data * inversion control. Otherwise set Inv_Ctrl = 0. Valid for all channels . Inv_Ctrl does not effect any * function on LVDS-Output. * 0b0000..Disable inversion control * 0b0001..Enable inversion control for number of RGB-Bits = 2 * 0b1010..Enable inversion control for number of RGB-Bits = 20 * 0b1011..Enable inversion control for number of RGB-Bits = 22 * 0b1100..Enable inversion control for number of RGB-Bits = 24 * 0b1101..Enable inversion control for number of RGB-Bits = 26 * 0b1110..Enable inversion control for number of RGB-Bits = 28 * 0b1111..Enable inversion control for number of RGB-Bits = 30 * 0b0010..Enable inversion control for number of RGB-Bits = 4 * 0b0011..Enable inversion control for number of RGB-Bits = 6 * 0b0100..Enable inversion control for number of RGB-Bits = 8 * 0b0101..Enable inversion control for number of RGB-Bits = 10 * 0b0110..Enable inversion control for number of RGB-Bits = 12 * 0b0111..Enable inversion control for number of RGB-Bits = 14 * 0b1000..Enable inversion control for number of RGB-Bits = 16 * 0b1001..Enable inversion control for number of RGB-Bits = 18 */ #define IRIS_MVPL_TCON0_CTRL_Inv_Ctrl(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_Inv_Ctrl_SHIFT)) & IRIS_MVPL_TCON0_CTRL_Inv_Ctrl_MASK) #define IRIS_MVPL_TCON0_CTRL_EnLVDS_MASK (0x100U) #define IRIS_MVPL_TCON0_CTRL_EnLVDS_SHIFT (8U) /*! EnLVDS - Enable LVDS Mode * 0b0..Disable LVDS, Enable TTL and RSDS * 0b1..Enable LVDS , TTL and RSDS are disable */ #define IRIS_MVPL_TCON0_CTRL_EnLVDS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_EnLVDS_SHIFT)) & IRIS_MVPL_TCON0_CTRL_EnLVDS_MASK) #define IRIS_MVPL_TCON0_CTRL_LVDSMode_MASK (0x200U) #define IRIS_MVPL_TCON0_CTRL_LVDSMode_SHIFT (9U) /*! LVDSMode - Selection the LVDS Mode if EnLVDS = ENABLE_LVDS * 0b0..LVDS Mode, refered to OpenLDI * 0b1..MiniLVDS */ #define IRIS_MVPL_TCON0_CTRL_LVDSMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_LVDSMode_SHIFT)) & IRIS_MVPL_TCON0_CTRL_LVDSMode_MASK) #define IRIS_MVPL_TCON0_CTRL_LVDS_Balance_MASK (0x400U) #define IRIS_MVPL_TCON0_CTRL_LVDS_Balance_SHIFT (10U) /*! LVDS_Balance - Operation mode of LVDS-OpenLDI * 0b0..LVDS operates in 24 bits Unbalanced Mode * 0b1..LVDS operates in 24 bits Balanced Mode */ #define IRIS_MVPL_TCON0_CTRL_LVDS_Balance(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_LVDS_Balance_SHIFT)) & IRIS_MVPL_TCON0_CTRL_LVDS_Balance_MASK) #define IRIS_MVPL_TCON0_CTRL_LVDS_CLOCK_INV_MASK (0x800U) #define IRIS_MVPL_TCON0_CTRL_LVDS_CLOCK_INV_SHIFT (11U) /*! LVDS_CLOCK_INV - Inversion the polatity of lvds clock in OpenLDI Mode * 0b0..NON-Invert LVDS Clock * 0b1..Invert LVDS Clock */ #define IRIS_MVPL_TCON0_CTRL_LVDS_CLOCK_INV(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_LVDS_CLOCK_INV_SHIFT)) & IRIS_MVPL_TCON0_CTRL_LVDS_CLOCK_INV_MASK) #define IRIS_MVPL_TCON0_CTRL_MiniLVDS_OpCode_MASK (0x7000U) #define IRIS_MVPL_TCON0_CTRL_MiniLVDS_OpCode_SHIFT (12U) /*! MiniLVDS_OpCode - Operation mode of MiniLVDS * 0b000..MiniLVDS operates in 6 and 8 bit data, three pairs * 0b001..Not Implemented * 0b010..Not Implemented * 0b011..MiniLVDS operates in 6 and 8 bit data, six pairs * 0b100..RESERVED1 * 0b101..RESERVED2 * 0b110..RESERVED3 * 0b111..RESERVED4 */ #define IRIS_MVPL_TCON0_CTRL_MiniLVDS_OpCode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_MiniLVDS_OpCode_SHIFT)) & IRIS_MVPL_TCON0_CTRL_MiniLVDS_OpCode_MASK) #define IRIS_MVPL_TCON0_CTRL_DUAL_SWAP_MASK (0x8000U) #define IRIS_MVPL_TCON0_CTRL_DUAL_SWAP_SHIFT (15U) /*! DUAL_SWAP - pixels of lower/upper channel can be swapped if tcon operates in DUAL-mode (include * LVDS/miniLVDS) no effect in SINGLE-mode * 0b0..NON-swapping pixels between lower-channel and upper-channel * 0b1..swapping pixels between lower-channel and upper-channel */ #define IRIS_MVPL_TCON0_CTRL_DUAL_SWAP(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_DUAL_SWAP_SHIFT)) & IRIS_MVPL_TCON0_CTRL_DUAL_SWAP_MASK) #define IRIS_MVPL_TCON0_CTRL_SplitPosition_MASK (0x3FFF0000U) #define IRIS_MVPL_TCON0_CTRL_SplitPosition_SHIFT (16U) /*! SplitPosition - Index of first column of right display half when ChannelMode is DUAL_SPLIT. - * SplitPosition must be less or equal 1280 - (Hact - SplitPosition) must be less or equal 1280 - * If (SplitPosition greater than (Hact - SplitPosition)) Htotal greather 2*SplitPosition else * Htotal greather (Hact - SplitPosition) - NOTE: once setting SplitPosition data_en is needed */ #define IRIS_MVPL_TCON0_CTRL_SplitPosition(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_CTRL_SplitPosition_SHIFT)) & IRIS_MVPL_TCON0_CTRL_SplitPosition_MASK) /*! @} */ /*! @name RSDSINVCTRL - Controls inversion of output polarity when connected IO cells operate in RSDS mode */ /*! @{ */ #define IRIS_MVPL_RSDSINVCTRL_RSDS_Inv_MASK (0x7FFFU) #define IRIS_MVPL_RSDSINVCTRL_RSDS_Inv_SHIFT (0U) /*! RSDS_Inv - Inversion vector for 1st channel. For i in [ 0 .. 11 ]; if RSDS_Inv [ i ] == 0 => * NON-Inversion of RSDS [ i ] else Inversion of RSDS [ i ] */ #define IRIS_MVPL_RSDSINVCTRL_RSDS_Inv(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_RSDSINVCTRL_RSDS_Inv_SHIFT)) & IRIS_MVPL_RSDSINVCTRL_RSDS_Inv_MASK) #define IRIS_MVPL_RSDSINVCTRL_RSDS_Inv_Dual_MASK (0x7FFF0000U) #define IRIS_MVPL_RSDSINVCTRL_RSDS_Inv_Dual_SHIFT (16U) /*! RSDS_Inv_Dual - Same as RSDS_inv for 2nd channel */ #define IRIS_MVPL_RSDSINVCTRL_RSDS_Inv_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_RSDSINVCTRL_RSDS_Inv_Dual_SHIFT)) & IRIS_MVPL_RSDSINVCTRL_RSDS_Inv_Dual_MASK) /*! @} */ /*! @name TCON0_MAPBIT3_0 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit0_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit0_SHIFT (0U) /*! MapBit0 - map bit[0] from [Blue, Green, Red] or from TSig[11:0]. If MapBit0 in [29..0] => bit[0] * = [Blue, Green, Red]; if MapBit0 in [41..30] => bit[0] in {TSig[11]..TSig[0]}; If MapBit0=43 * => bit[0]=0; if MapBit0=42 => bit[0]=1 */ #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_MapBit0_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_MapBit0_MASK) #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit1_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit1_SHIFT (8U) /*! MapBit1 - map bit[1] from [Blue, Green, Red] or from TSig[11:0]. If MapBit1 in [29..0] => bit[1] * = [Blue, Green, Red]; if MapBit1 in [41..30] => bit[1] in {TSig[11]..TSig[0]}; If MapBit1=43 * => bit[1]=0; if MapBit1=42 => bit[1]=1 */ #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_MapBit1_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_MapBit1_MASK) #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit2_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit2_SHIFT (16U) /*! MapBit2 - map bit[2] from [Blue, Green, Red] or from TSig[11:0]. If MapBit2 in [29..0] => bit[2] * = [Blue, Green, Red]; if MapBit2 in [41..30] => bit[2] in {TSig[11]..TSig[0]}; If MapBit2=43 * => bit[2]=0; if MapBit2=42 => bit[2]=1 */ #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_MapBit2_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_MapBit2_MASK) #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit3_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit3_SHIFT (24U) /*! MapBit3 - map bit[3] from [Blue, Green, Red] or from TSig[11:0]. If MapBit3 in [29..0] => bit[3] * = [Blue, Green, Red]; if MapBit3 in [41..30] => bit[3] in {TSig[11]..TSig[0]}; If MapBit3=43 * => bit[3]=0; if MapBit3=42 => bit[3]=1 */ #define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_MapBit3_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_MapBit3_MASK) /*! @} */ /*! @name TCON0_MAPBIT7_4 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit4_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit4_SHIFT (0U) /*! MapBit4 - map bit[4] from [Blue, Green, Red] or from TSig[11:0]. If MapBit4 in [29..0] => bit[4] * = [Blue, Green, Red]; if MapBit4 in [41..30] => bit[4] in {TSig[11]..TSig[0]}; If MapBit4=43 * => bit[4]=0; if MapBit4=42 => bit[4]=1 */ #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_MapBit4_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_MapBit4_MASK) #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit5_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit5_SHIFT (8U) /*! MapBit5 - map bit[5] from [Blue, Green, Red] or from TSig[11:0]. If MapBit5 in [29..0] => bit[5] * = [Blue, Green, Red]; if MapBit5 in [41..30] => bit[5] in {TSig[11]..TSig[0]}; If MapBit5=43 * => bit[5]=0; if MapBit5=42 => bit[5]=1 */ #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_MapBit5_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_MapBit5_MASK) #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit6_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit6_SHIFT (16U) /*! MapBit6 - map bit[6] from [Blue, Green, Red] or from TSig[11:0]. If MapBit6 in [29..0] => bit[6] * = [Blue, Green, Red]; if MapBit6 in [41..30] => bit[6] in {TSig[11]..TSig[0]}; If MapBit6=43 * => bit[6]=0; if MapBit6=42 => bit[6]=1 */ #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_MapBit6_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_MapBit6_MASK) #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit7_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit7_SHIFT (24U) /*! MapBit7 - map bit[7] from [Blue, Green, Red] or from TSig[11:0]. If MapBit7 in [29..0] => bit[7] * = [Blue, Green, Red]; if MapBit7 in [41..30] => bit[7] in {TSig[11]..TSig[0]}; If MapBit7=43 * => bit[7]=0; if MapBit7=42 => bit[7]=1 */ #define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_MapBit7_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_MapBit7_MASK) /*! @} */ /*! @name TCON0_MAPBIT11_8 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit8_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit8_SHIFT (0U) /*! MapBit8 - map bit[8] from [Blue, Green, Red] or from TSig[11:0]. If MapBit8 in [29..0] => bit[8] * = [Blue, Green, Red]; if MapBit8 in [41..30] => bit[8] in {TSig[11]..TSig[0]}; If MapBit8=43 * => bit[8]=0; if MapBit8=42 => bit[8]=1 */ #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_MapBit8_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_MapBit8_MASK) #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit9_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit9_SHIFT (8U) /*! MapBit9 - map bit[9] from [Blue, Green, Red] or from TSig[11:0]. If MapBit9 in [29..0] => bit[9] * = [Blue, Green, Red]; if MapBit9 in [41..30] => bit[9] in {TSig[11]..TSig[0]}; If MapBit9=43 * => bit[9]=0; if MapBit9=42 => bit[9]=1 */ #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_MapBit9_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_MapBit9_MASK) #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit10_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit10_SHIFT (16U) /*! MapBit10 - map bit[10] from [Blue, Green, Red] or from TSig[11:0]. If MapBit10 in [29..0] => * bit[10] = [Blue, Green, Red]; if MapBit10 in [41..30] => bit[10] in {TSig[11]..TSig[0]}; If * MapBit10=43 => bit[10]=0; if MapBit10=42 => bit[10]=1 */ #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_MapBit10_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_MapBit10_MASK) #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit11_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit11_SHIFT (24U) /*! MapBit11 - map bit[11] from [Blue, Green, Red] or from TSig[11:0]. If MapBit11 in [29..0] => * bit[11] = [Blue, Green, Red]; if MapBit11 in [41..30] => bit[11] in {TSig[11]..TSig[0]}; If * MapBit11=43 => bit[11]=0; if MapBit11=42 => bit[11]=1 */ #define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_MapBit11_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_MapBit11_MASK) /*! @} */ /*! @name TCON0_MAPBIT15_12 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit12_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit12_SHIFT (0U) /*! MapBit12 - map bit[12] from [Blue, Green, Red] or from TSig[11:0]. If MapBit12 in [29..0] => * bit[12] = [Blue, Green, Red]; if MapBit12 in [41..30] => bit[12] in {TSig[11]..TSig[0]}; If * MapBit12=43 => bit[12]=0; if MapBit12=42 => bit[12]=1 */ #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit12(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_MapBit12_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_MapBit12_MASK) #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit13_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit13_SHIFT (8U) /*! MapBit13 - map bit[13] from [Blue, Green, Red] or from TSig[11:0]. If MapBit13 in [29..0] => * bit[13] = [Blue, Green, Red]; if MapBit13 in [41..30] => bit[13] in {TSig[11]..TSig[0]}; If * MapBit13=43 => bit[13]=0; if MapBit13=42 => bit[13]=1 */ #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit13(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_MapBit13_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_MapBit13_MASK) #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit14_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit14_SHIFT (16U) /*! MapBit14 - map bit[14] from [Blue, Green, Red] or from TSig[11:0]. If MapBit14 in [29..0] => * bit[14] = [Blue, Green, Red]; if MapBit14 in [41..30] => bit[14] in {TSig[11]..TSig[0]}; If * MapBit14=43 => bit[14]=0; if MapBit14=42 => bit[14]=1 */ #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit14(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_MapBit14_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_MapBit14_MASK) #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit15_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit15_SHIFT (24U) /*! MapBit15 - map bit[15] from [Blue, Green, Red] or from TSig[11:0]. If MapBit15 in [29..0] => * bit[15] = [Blue, Green, Red]; if MapBit15 in [41..30] => bit[15] in {TSig[11]..TSig[0]}; If * MapBit15=43 => bit[15]=0; if MapBit15=42 => bit[15]=1 */ #define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit15(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_MapBit15_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_MapBit15_MASK) /*! @} */ /*! @name TCON0_MAPBIT19_16 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit16_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit16_SHIFT (0U) /*! MapBit16 - map bit[16] from [Blue, Green, Red] or from TSig[11:0]. If MapBit16 in [29..0] => * bit[16] = [Blue, Green, Red]; if MapBit16 in [41..30] => bit[16] in {TSig[11]..TSig[0]}; If * MapBit16=43 => bit[16]=0; if MapBit16=42 => bit[16]=1 */ #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit16(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_MapBit16_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_MapBit16_MASK) #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit17_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit17_SHIFT (8U) /*! MapBit17 - map bit[17] from [Blue, Green, Red] or from TSig[11:0]. If MapBit17 in [29..0] => * bit[17] = [Blue, Green, Red]; if MapBit17 in [41..30] => bit[17] in {TSig[11]..TSig[0]}; If * MapBit17=43 => bit[17]=0; if MapBit17=42 => bit[17]=1 */ #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit17(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_MapBit17_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_MapBit17_MASK) #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit18_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit18_SHIFT (16U) /*! MapBit18 - map bit[18] from [Blue, Green, Red] or from TSig[11:0]. If MapBit18 in [29..0] => * bit[18] = [Blue, Green, Red]; if MapBit18 in [41..30] => bit[18] in {TSig[11]..TSig[0]}; If * MapBit18=43 => bit[18]=0; if MapBit18=42 => bit[18]=1 */ #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit18(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_MapBit18_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_MapBit18_MASK) #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit19_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit19_SHIFT (24U) /*! MapBit19 - map bit[19] from [Blue, Green, Red] or from TSig[11:0]. If MapBit19 in [29..0] => * bit[19] = [Blue, Green, Red]; if MapBit19 in [41..30] => bit[19] in {TSig[11]..TSig[0]}; If * MapBit19=43 => bit[19]=0; if MapBit19=42 => bit[19]=1 */ #define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit19(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_MapBit19_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_MapBit19_MASK) /*! @} */ /*! @name TCON0_MAPBIT23_20 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit20_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit20_SHIFT (0U) /*! MapBit20 - map bit[20] from [Blue, Green, Red] or from TSig[11:0]. If MapBit20 in [29..0] => * bit[20] = [Blue, Green, Red]; if MapBit20 in [41..30] => bit[20] in {TSig[11]..TSig[0]}; If * MapBit20=43 => bit[20]=0; if MapBit20=42 => bit[20]=1 */ #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit20(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_MapBit20_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_MapBit20_MASK) #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit21_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit21_SHIFT (8U) /*! MapBit21 - map bit[21] from [Blue, Green, Red] or from TSig[11:0]. If MapBit21 in [29..0] => * bit[21] = [Blue, Green, Red]; if MapBit21 in [41..30] => bit[21] in {TSig[11]..TSig[0]}; If * MapBit21=43 => bit[21]=0; if MapBit21=42 => bit[21]=1 */ #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit21(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_MapBit21_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_MapBit21_MASK) #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit22_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit22_SHIFT (16U) /*! MapBit22 - map bit[22] from [Blue, Green, Red] or from TSig[11:0]. If MapBit22 in [29..0] => * bit[22] = [Blue, Green, Red]; if MapBit22 in [41..30] => bit[22] in {TSig[11]..TSig[0]}; If * MapBit22=43 => bit[22]=0; if MapBit22=42 => bit[22]=1 */ #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit22(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_MapBit22_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_MapBit22_MASK) #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit23_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit23_SHIFT (24U) /*! MapBit23 - map bit[23] from [Blue, Green, Red] or from TSig[11:0]. If MapBit23 in [29..0] => * bit[23] = [Blue, Green, Red]; if MapBit23 in [41..30] => bit[23] in {TSig[11]..TSig[0]}; If * MapBit23=43 => bit[23]=0; if MapBit23=42 => bit[23]=1 */ #define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit23(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_MapBit23_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_MapBit23_MASK) /*! @} */ /*! @name TCON0_MAPBIT27_24 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit24_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit24_SHIFT (0U) /*! MapBit24 - map bit[24] from [Blue, Green, Red] or from TSig[11:0]. If MapBit24 in [29..0] => * bit[24] = [Blue, Green, Red]; if MapBit24 in [41..30] => bit[24] in {TSig[11]..TSig[0]}; If * MapBit24=43 => bit[24]=0; if MapBit24=42 => bit[24]=1 */ #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit24(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_MapBit24_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_MapBit24_MASK) #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit25_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit25_SHIFT (8U) /*! MapBit25 - map bit[25] from [Blue, Green, Red] or from TSig[11:0]. If MapBit25 in [29..0] => * bit[25] = [Blue, Green, Red]; if MapBit25 in [41..30] => bit[25] in {TSig[11]..TSig[0]}; If * MapBit25=43 => bit[25]=0; if MapBit25=42 => bit[25]=1 */ #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit25(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_MapBit25_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_MapBit25_MASK) #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit26_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit26_SHIFT (16U) /*! MapBit26 - map bit[26] from [Blue, Green, Red] or from TSig[11:0]. If MapBit26 in [29..0] => * bit[26] = [Blue, Green, Red]; if MapBit26 in [41..30] => bit[26] in {TSig[11]..TSig[0]}; If * MapBit26=43 => bit[26]=0; if MapBit26=42 => bit[26]=1 */ #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit26(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_MapBit26_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_MapBit26_MASK) #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit27_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit27_SHIFT (24U) /*! MapBit27 - map bit[27] from [Blue, Green, Red] or from TSig[11:0]. If MapBit27 in [29..0] => * bit[27] = [Blue, Green, Red]; if MapBit27 in [41..30] => bit[27] in {TSig[11]..TSig[0]}; If * MapBit27=43 => bit[27]=0; if MapBit27=42 => bit[27]=1 */ #define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit27(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_MapBit27_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_MapBit27_MASK) /*! @} */ /*! @name TCON0_MAPBIT31_28 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit28_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit28_SHIFT (0U) /*! MapBit28 - map bit[28] from [Blue, Green, Red] or from TSig[11:0]. If MapBit28 in [29..0] => * bit[28] = [Blue, Green, Red]; if MapBit28 in [41..30] => bit[28] in {TSig[11]..TSig[0]}; If * MapBit28=43 => bit[28]=0; if MapBit28=42 => bit[28]=1 */ #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit28(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_MapBit28_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_MapBit28_MASK) #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit29_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit29_SHIFT (8U) /*! MapBit29 - map bit[29] from [Blue, Green, Red] or from TSig[11:0]. If MapBit29 in [29..0] => * bit[29] = [Blue, Green, Red]; if MapBit29 in [41..30] => bit[29] in {TSig[11]..TSig[0]}; If * MapBit29=43 => bit[29]=0; if MapBit29=42 => bit[29]=1 */ #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit29(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_MapBit29_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_MapBit29_MASK) #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit30_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit30_SHIFT (16U) /*! MapBit30 - map bit[30] from [Blue, Green, Red] or from TSig[11:0]. If MapBit30 in [29..0] => * bit[30] = [Blue, Green, Red]; if MapBit30 in [41..30] => bit[30] in {TSig[11]..TSig[0]}; If * MapBit30=43 => bit[30]=0; if MapBit30=42 => bit[30]=1 */ #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit30(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_MapBit30_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_MapBit30_MASK) #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit31_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit31_SHIFT (24U) /*! MapBit31 - map bit[31] from [Blue, Green, Red] or from TSig[11:0]. If MapBit31 in [29..0] => * bit[31] = [Blue, Green, Red]; if MapBit31 in [41..30] => bit[31] in {TSig[11]..TSig[0]}; If * MapBit31=43 => bit[31]=0; if MapBit31=42 => bit[31]=1 */ #define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit31(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_MapBit31_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_MapBit31_MASK) /*! @} */ /*! @name TCON0_MAPBIT34_32 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit32_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit32_SHIFT (0U) /*! MapBit32 - map bit[32] from [Blue, Green, Red] or from TSig[11:0]. If MapBit32 in [29..0] => * bit[32] = [Blue, Green, Red]; if MapBit32 in [41..30] => bit[32] in {TSig[11]..TSig[0]}; If * MapBit32=43 => bit[32]=0; if MapBit32=42 => bit[32]=1 */ #define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit32(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_MapBit32_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_MapBit32_MASK) #define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit33_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit33_SHIFT (8U) /*! MapBit33 - map bit[33] from [Blue, Green, Red] or from TSig[11:0]. If MapBit33 in [29..0] => * bit[33] = [Blue, Green, Red]; if MapBit33 in [41..30] => bit[33] in {TSig[11]..TSig[0]}; If * MapBit33=43 => bit[33]=0; if MapBit33=42 => bit[33]=1 */ #define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit33(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_MapBit33_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_MapBit33_MASK) #define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit34_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit34_SHIFT (16U) /*! MapBit34 - map bit[34] from [Blue, Green, Red] or from TSig[11:0]. If MapBit34 in [29..0] => * bit[34] = [Blue, Green, Red]; if MapBit34 in [41..30] => bit[34] in {TSig[11]..TSig[0]}; If * MapBit34=43 => bit[34]=0; if MapBit34=42 => bit[34]=1 */ #define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit34(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_MapBit34_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_MapBit34_MASK) /*! @} */ /*! @name TCON0_MAPBIT3_0_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit0_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit0_Dual_SHIFT (0U) /*! MapBit0_Dual - map bit[0] from [Blue, Green, Red] or from TSig[11:0]. If MapBit0_Dual in [29..0] * => bit[0] = [Blue, Green, Red]; if MapBit0_Dual in [41..30] => bit[0] in {TSig[11]..TSig[0]}; * If MapBit0_Dual=43 => bit[0]=0; if MapBit0_Dual=42 => bit[0]=1 */ #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit0_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit0_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit0_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit1_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit1_Dual_SHIFT (8U) /*! MapBit1_Dual - map bit[1] from [Blue, Green, Red] or from TSig[11:0]. If MapBit1_Dual in [29..0] * => bit[1] = [Blue, Green, Red]; if MapBit1_Dual in [41..30] => bit[1] in {TSig[11]..TSig[0]}; * If MapBit1_Dual=43 => bit[1]=0; if MapBit1_Dual=42 => bit[1]=1 */ #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit1_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit1_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit1_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit2_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit2_Dual_SHIFT (16U) /*! MapBit2_Dual - map bit[2] from [Blue, Green, Red] or from TSig[11:0]. If MapBit2_Dual in [29..0] * => bit[2] = [Blue, Green, Red]; if MapBit2_Dual in [41..30] => bit[2] in {TSig[11]..TSig[0]}; * If MapBit2_Dual=43 => bit[2]=0; if MapBit2_Dual=42 => bit[2]=1 */ #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit2_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit2_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit2_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit3_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit3_Dual_SHIFT (24U) /*! MapBit3_Dual - map bit[3] from [Blue, Green, Red] or from TSig[11:0]. If MapBit3_Dual in [29..0] * => bit[3] = [Blue, Green, Red]; if MapBit3_Dual in [41..30] => bit[3] in {TSig[11]..TSig[0]}; * If MapBit3_Dual=43 => bit[3]=0; if MapBit3_Dual=42 => bit[3]=1 */ #define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit3_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit3_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit3_Dual_MASK) /*! @} */ /*! @name TCON0_MAPBIT7_4_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit4_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit4_Dual_SHIFT (0U) /*! MapBit4_Dual - map bit[4] from [Blue, Green, Red] or from TSig[11:0]. If MapBit4_Dual in [29..0] * => bit[4] = [Blue, Green, Red]; if MapBit4_Dual in [41..30] => bit[4] in {TSig[11]..TSig[0]}; * If MapBit4_Dual=43 => bit[4]=0; if MapBit4_Dual=42 => bit[4]=1 */ #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit4_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit4_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit4_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit5_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit5_Dual_SHIFT (8U) /*! MapBit5_Dual - map bit[5] from [Blue, Green, Red] or from TSig[11:0]. If MapBit5_Dual in [29..0] * => bit[5] = [Blue, Green, Red]; if MapBit5_Dual in [41..30] => bit[5] in {TSig[11]..TSig[0]}; * If MapBit5_Dual=43 => bit[5]=0; if MapBit5_Dual=42 => bit[5]=1 */ #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit5_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit5_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit5_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit6_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit6_Dual_SHIFT (16U) /*! MapBit6_Dual - map bit[6] from [Blue, Green, Red] or from TSig[11:0]. If MapBit6_Dual in [29..0] * => bit[6] = [Blue, Green, Red]; if MapBit6_Dual in [41..30] => bit[6] in {TSig[11]..TSig[0]}; * If MapBit6_Dual=43 => bit[6]=0; if MapBit6_Dual=42 => bit[6]=1 */ #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit6_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit6_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit6_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit7_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit7_Dual_SHIFT (24U) /*! MapBit7_Dual - map bit[7] from [Blue, Green, Red] or from TSig[11:0]. If MapBit7_Dual in [29..0] * => bit[7] = [Blue, Green, Red]; if MapBit7_Dual in [41..30] => bit[7] in {TSig[11]..TSig[0]}; * If MapBit7_Dual=43 => bit[7]=0; if MapBit7_Dual=42 => bit[7]=1 */ #define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit7_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit7_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit7_Dual_MASK) /*! @} */ /*! @name TCON0_MAPBIT11_8_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit8_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit8_Dual_SHIFT (0U) /*! MapBit8_Dual - map bit[8] from [Blue, Green, Red] or from TSig[11:0]. If MapBit8_Dual in [29..0] * => bit[8] = [Blue, Green, Red]; if MapBit8_Dual in [41..30] => bit[8] in {TSig[11]..TSig[0]}; * If MapBit8_Dual=43 => bit[8]=0; if MapBit8_Dual=42 => bit[8]=1 */ #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit8_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit8_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit8_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit9_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit9_Dual_SHIFT (8U) /*! MapBit9_Dual - map bit[9] from [Blue, Green, Red] or from TSig[11:0]. If MapBit9_Dual in [29..0] * => bit[9] = [Blue, Green, Red]; if MapBit9_Dual in [41..30] => bit[9] in {TSig[11]..TSig[0]}; * If MapBit9_Dual=43 => bit[9]=0; if MapBit9_Dual=42 => bit[9]=1 */ #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit9_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit9_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit9_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit10_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit10_Dual_SHIFT (16U) /*! MapBit10_Dual - map bit[10] from [Blue, Green, Red] or from TSig[11:0]. If MapBit10_Dual in * [29..0] => bit[10] = [Blue, Green, Red]; if MapBit10_Dual in [41..30] => bit[10] in * {TSig[11]..TSig[0]}; If MapBit10_Dual=43 => bit[10]=0; if MapBit10_Dual=42 => bit[10]=1 */ #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit10_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit10_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit10_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit11_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit11_Dual_SHIFT (24U) /*! MapBit11_Dual - map bit[11] from [Blue, Green, Red] or from TSig[11:0]. If MapBit11_Dual in * [29..0] => bit[11] = [Blue, Green, Red]; if MapBit11_Dual in [41..30] => bit[11] in * {TSig[11]..TSig[0]}; If MapBit11_Dual=43 => bit[11]=0; if MapBit11_Dual=42 => bit[11]=1 */ #define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit11_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit11_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit11_Dual_MASK) /*! @} */ /*! @name TCON0_MAPBIT15_12_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit12_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit12_Dual_SHIFT (0U) /*! MapBit12_Dual - map bit[12] from [Blue, Green, Red] or from TSig[11:0]. If MapBit12_Dual in * [29..0] => bit[12] = [Blue, Green, Red]; if MapBit12_Dual in [41..30] => bit[12] in * {TSig[11]..TSig[0]}; If MapBit12_Dual=43 => bit[12]=0; if MapBit12_Dual=42 => bit[12]=1 */ #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit12_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit12_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit12_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit13_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit13_Dual_SHIFT (8U) /*! MapBit13_Dual - map bit[13] from [Blue, Green, Red] or from TSig[11:0]. If MapBit13_Dual in * [29..0] => bit[13] = [Blue, Green, Red]; if MapBit13_Dual in [41..30] => bit[13] in * {TSig[11]..TSig[0]}; If MapBit13_Dual=43 => bit[13]=0; if MapBit13_Dual=42 => bit[13]=1 */ #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit13_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit13_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit13_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit14_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit14_Dual_SHIFT (16U) /*! MapBit14_Dual - map bit[14] from [Blue, Green, Red] or from TSig[11:0]. If MapBit14_Dual in * [29..0] => bit[14] = [Blue, Green, Red]; if MapBit14_Dual in [41..30] => bit[14] in * {TSig[11]..TSig[0]}; If MapBit14_Dual=43 => bit[14]=0; if MapBit14_Dual=42 => bit[14]=1 */ #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit14_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit14_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit14_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit15_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit15_Dual_SHIFT (24U) /*! MapBit15_Dual - map bit[15] from [Blue, Green, Red] or from TSig[11:0]. If MapBit15_Dual in * [29..0] => bit[15] = [Blue, Green, Red]; if MapBit15_Dual in [41..30] => bit[15] in * {TSig[11]..TSig[0]}; If MapBit15_Dual=43 => bit[15]=0; if MapBit15_Dual=42 => bit[15]=1 */ #define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit15_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit15_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit15_Dual_MASK) /*! @} */ /*! @name TCON0_MAPBIT19_16_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit16_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit16_Dual_SHIFT (0U) /*! MapBit16_Dual - map bit[16] from [Blue, Green, Red] or from TSig[11:0]. If MapBit16_Dual in * [29..0] => bit[16] = [Blue, Green, Red]; if MapBit16_Dual in [41..30] => bit[16] in * {TSig[11]..TSig[0]}; If MapBit16_Dual=43 => bit[16]=0; if MapBit16_Dual=42 => bit[16]=1 */ #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit16_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit16_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit16_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit17_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit17_Dual_SHIFT (8U) /*! MapBit17_Dual - map bit[17] from [Blue, Green, Red] or from TSig[11:0]. If MapBit17_Dual in * [29..0] => bit[17] = [Blue, Green, Red]; if MapBit17_Dual in [41..30] => bit[17] in * {TSig[11]..TSig[0]}; If MapBit17_Dual=43 => bit[17]=0; if MapBit17_Dual=42 => bit[17]=1 */ #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit17_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit17_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit17_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit18_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit18_Dual_SHIFT (16U) /*! MapBit18_Dual - map bit[18] from [Blue, Green, Red] or from TSig[11:0]. If MapBit18_Dual in * [29..0] => bit[18] = [Blue, Green, Red]; if MapBit18_Dual in [41..30] => bit[18] in * {TSig[11]..TSig[0]}; If MapBit18_Dual=43 => bit[18]=0; if MapBit18_Dual=42 => bit[18]=1 */ #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit18_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit18_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit18_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit19_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit19_Dual_SHIFT (24U) /*! MapBit19_Dual - map bit[19] from [Blue, Green, Red] or from TSig[11:0]. If MapBit19_Dual in * [29..0] => bit[19] = [Blue, Green, Red]; if MapBit19_Dual in [41..30] => bit[19] in * {TSig[11]..TSig[0]}; If MapBit19_Dual=43 => bit[19]=0; if MapBit19_Dual=42 => bit[19]=1 */ #define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit19_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit19_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit19_Dual_MASK) /*! @} */ /*! @name TCON0_MAPBIT23_20_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit20_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit20_Dual_SHIFT (0U) /*! MapBit20_Dual - map bit[20] from [Blue, Green, Red] or from TSig[11:0]. If MapBit20_Dual in * [29..0] => bit[20] = [Blue, Green, Red]; if MapBit20_Dual in [41..30] => bit[20] in * {TSig[11]..TSig[0]}; If MapBit20_Dual=43 => bit[20]=0; if MapBit20_Dual=42 => bit[20]=1 */ #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit20_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit20_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit20_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit21_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit21_Dual_SHIFT (8U) /*! MapBit21_Dual - map bit[21] from [Blue, Green, Red] or from TSig[11:0]. If MapBit21_Dual in * [29..0] => bit[21] = [Blue, Green, Red]; if MapBit21_Dual in [41..30] => bit[21] in * {TSig[11]..TSig[0]}; If MapBit21_Dual=43 => bit[21]=0; if MapBit21_Dual=42 => bit[21]=1 */ #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit21_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit21_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit21_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit22_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit22_Dual_SHIFT (16U) /*! MapBit22_Dual - map bit[22] from [Blue, Green, Red] or from TSig[11:0]. If MapBit22_Dual in * [29..0] => bit[22] = [Blue, Green, Red]; if MapBit22_Dual in [41..30] => bit[22] in * {TSig[11]..TSig[0]}; If MapBit22_Dual=43 => bit[22]=0; if MapBit22_Dual=42 => bit[22]=1 */ #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit22_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit22_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit22_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit23_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit23_Dual_SHIFT (24U) /*! MapBit23_Dual - map bit[23] from [Blue, Green, Red] or from TSig[11:0]. If MapBit23_Dual in * [29..0] => bit[23] = [Blue, Green, Red]; if MapBit23_Dual in [41..30] => bit[23] in * {TSig[11]..TSig[0]}; If MapBit23_Dual=43 => bit[23]=0; if MapBit23_Dual=42 => bit[23]=1 */ #define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit23_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit23_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit23_Dual_MASK) /*! @} */ /*! @name TCON0_MAPBIT27_24_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit24_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit24_Dual_SHIFT (0U) /*! MapBit24_Dual - map bit[24] from [Blue, Green, Red] or from TSig[11:0]. If MapBit24_Dual in * [29..0] => bit[24] = [Blue, Green, Red]; if MapBit24_Dual in [41..30] => bit[24] in * {TSig[11]..TSig[0]}; If MapBit24_Dual=43 => bit[24]=0; if MapBit24_Dual=42 => bit[24]=1 */ #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit24_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit24_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit24_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit25_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit25_Dual_SHIFT (8U) /*! MapBit25_Dual - map bit[25] from [Blue, Green, Red] or from TSig[11:0]. If MapBit25_Dual in * [29..0] => bit[25] = [Blue, Green, Red]; if MapBit25_Dual in [41..30] => bit[25] in * {TSig[11]..TSig[0]}; If MapBit25_Dual=43 => bit[25]=0; if MapBit25_Dual=42 => bit[25]=1 */ #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit25_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit25_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit25_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit26_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit26_Dual_SHIFT (16U) /*! MapBit26_Dual - map bit[26] from [Blue, Green, Red] or from TSig[11:0]. If MapBit26_Dual in * [29..0] => bit[26] = [Blue, Green, Red]; if MapBit26_Dual in [41..30] => bit[26] in * {TSig[11]..TSig[0]}; If MapBit26_Dual=43 => bit[26]=0; if MapBit26_Dual=42 => bit[26]=1 */ #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit26_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit26_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit26_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit27_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit27_Dual_SHIFT (24U) /*! MapBit27_Dual - map bit[27] from [Blue, Green, Red] or from TSig[11:0]. If MapBit27_Dual in * [29..0] => bit[27] = [Blue, Green, Red]; if MapBit27_Dual in [41..30] => bit[27] in * {TSig[11]..TSig[0]}; If MapBit27_Dual=43 => bit[27]=0; if MapBit27_Dual=42 => bit[27]=1 */ #define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit27_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit27_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit27_Dual_MASK) /*! @} */ /*! @name TCON0_MAPBIT31_28_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit28_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit28_Dual_SHIFT (0U) /*! MapBit28_Dual - map bit[28] from [Blue, Green, Red] or from TSig[11:0]. If MapBit28_Dual in * [29..0] => bit[28] = [Blue, Green, Red]; if MapBit28_Dual in [41..30] => bit[28] in * {TSig[11]..TSig[0]}; If MapBit28_Dual=43 => bit[28]=0; if MapBit28_Dual=42 => bit[28]=1 */ #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit28_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit28_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit28_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit29_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit29_Dual_SHIFT (8U) /*! MapBit29_Dual - map bit[29] from [Blue, Green, Red] or from TSig[11:0]. If MapBit29_Dual in * [29..0] => bit[29] = [Blue, Green, Red]; if MapBit29_Dual in [41..30] => bit[29] in * {TSig[11]..TSig[0]}; If MapBit29_Dual=43 => bit[29]=0; if MapBit29_Dual=42 => bit[29]=1 */ #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit29_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit29_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit29_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit30_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit30_Dual_SHIFT (16U) /*! MapBit30_Dual - map bit[30] from [Blue, Green, Red] or from TSig[11:0]. If MapBit30_Dual in * [29..0] => bit[30] = [Blue, Green, Red]; if MapBit30_Dual in [41..30] => bit[30] in * {TSig[11]..TSig[0]}; If MapBit30_Dual=43 => bit[30]=0; if MapBit30_Dual=42 => bit[30]=1 */ #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit30_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit30_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit30_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit31_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit31_Dual_SHIFT (24U) /*! MapBit31_Dual - map bit[31] from [Blue, Green, Red] or from TSig[11:0]. If MapBit31_Dual in * [29..0] => bit[31] = [Blue, Green, Red]; if MapBit31_Dual in [41..30] => bit[31] in * {TSig[11]..TSig[0]}; If MapBit31_Dual=43 => bit[31]=0; if MapBit31_Dual=42 => bit[31]=1 */ #define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit31_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit31_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit31_Dual_MASK) /*! @} */ /*! @name TCON0_MAPBIT34_32_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit32_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit32_Dual_SHIFT (0U) /*! MapBit32_Dual - map bit[32] from [Blue, Green, Red] or from TSig[11:0]. If MapBit32_Dual in * [29..0] => bit[32] = [Blue, Green, Red]; if MapBit32_Dual in [41..30] => bit[32] in * {TSig[11]..TSig[0]}; If MapBit32_Dual=43 => bit[32]=0; if MapBit32_Dual=42 => bit[32]=1 */ #define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit32_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit32_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit32_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit33_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit33_Dual_SHIFT (8U) /*! MapBit33_Dual - map bit[33] from [Blue, Green, Red] or from TSig[11:0]. If MapBit33_Dual in * [29..0] => bit[33] = [Blue, Green, Red]; if MapBit33_Dual in [41..30] => bit[33] in * {TSig[11]..TSig[0]}; If MapBit33_Dual=43 => bit[33]=0; if MapBit33_Dual=42 => bit[33]=1 */ #define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit33_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit33_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit33_Dual_MASK) #define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit34_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit34_Dual_SHIFT (16U) /*! MapBit34_Dual - map bit[34] from [Blue, Green, Red] or from TSig[11:0]. If MapBit34_Dual in * [29..0] => bit[34] = [Blue, Green, Red]; if MapBit34_Dual in [41..30] => bit[34] in * {TSig[11]..TSig[0]}; If MapBit34_Dual=43 => bit[34]=0; if MapBit34_Dual=42 => bit[34]=1 */ #define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit34_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit34_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit34_Dual_MASK) /*! @} */ /*! @name TCON0_SPG0POSON - Sync pulse generator 0, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_Y0_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_Y0_SHIFT (0U) /*! SPGPSON_Y0 - Y scan position */ #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_Y0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_Y0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_Y0_MASK) #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_FIELD0_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_FIELD0_SHIFT (15U) /*! SPGPSON_FIELD0 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_FIELD0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_FIELD0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_FIELD0_MASK) #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_X0_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_X0_SHIFT (16U) /*! SPGPSON_X0 - X scan position */ #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_X0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_X0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_X0_MASK) #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_TOGGLE0_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_TOGGLE0_SHIFT (31U) /*! SPGPSON_TOGGLE0 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_TOGGLE0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_TOGGLE0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_TOGGLE0_MASK) /*! @} */ /*! @name TCON0_SPG0MASKON - The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG0MASKON_SPGMKON0_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG0MASKON_SPGMKON0_SHIFT (0U) /*! SPGMKON0 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG0MASKON_SPGMKON0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0MASKON_SPGMKON0_SHIFT)) & IRIS_MVPL_TCON0_SPG0MASKON_SPGMKON0_MASK) /*! @} */ /*! @name TCON0_SPG0POSOFF - Sync pulse generator 0, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_Y0_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_Y0_SHIFT (0U) /*! SPGPSOFF_Y0 - Y scan position */ #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_Y0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_Y0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_Y0_MASK) #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT (15U) /*! SPGPSOFF_FIELD0 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_MASK) #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_X0_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_X0_SHIFT (16U) /*! SPGPSOFF_X0 - X scan position */ #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_X0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_X0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_X0_MASK) #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT (31U) /*! SPGPSOFF_TOGGLE0 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK) /*! @} */ /*! @name TCON0_SPG0MASKOFF - The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG0MASKOFF_SPGMKOFF0_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG0MASKOFF_SPGMKOFF0_SHIFT (0U) /*! SPGMKOFF0 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG0MASKOFF_SPGMKOFF0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0MASKOFF_SPGMKOFF0_SHIFT)) & IRIS_MVPL_TCON0_SPG0MASKOFF_SPGMKOFF0_MASK) /*! @} */ /*! @name TCON0_SPG1POSON - Sync pulse generator 1, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_Y1_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_Y1_SHIFT (0U) /*! SPGPSON_Y1 - Y scan position */ #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_Y1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_Y1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_Y1_MASK) #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_FIELD1_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_FIELD1_SHIFT (15U) /*! SPGPSON_FIELD1 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_FIELD1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_FIELD1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_FIELD1_MASK) #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_X1_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_X1_SHIFT (16U) /*! SPGPSON_X1 - X scan position */ #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_X1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_X1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_X1_MASK) #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_TOGGLE1_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_TOGGLE1_SHIFT (31U) /*! SPGPSON_TOGGLE1 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_TOGGLE1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_TOGGLE1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_TOGGLE1_MASK) /*! @} */ /*! @name TCON0_SPG1MASKON - The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG1MASKON_SPGMKON1_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG1MASKON_SPGMKON1_SHIFT (0U) /*! SPGMKON1 - mask bits (1= do not include this bit into position matching) */ #define IRIS_MVPL_TCON0_SPG1MASKON_SPGMKON1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1MASKON_SPGMKON1_SHIFT)) & IRIS_MVPL_TCON0_SPG1MASKON_SPGMKON1_MASK) /*! @} */ /*! @name TCON0_SPG1POSOFF - Sync pulse generator 1, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_Y1_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_Y1_SHIFT (0U) /*! SPGPSOFF_Y1 - Y scan position */ #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_Y1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_Y1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_Y1_MASK) #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT (15U) /*! SPGPSOFF_FIELD1 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_MASK) #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_X1_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_X1_SHIFT (16U) /*! SPGPSOFF_X1 - X scan position */ #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_X1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_X1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_X1_MASK) #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT (31U) /*! SPGPSOFF_TOGGLE1 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK) /*! @} */ /*! @name TCON0_SPG1MASKOFF - The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG1MASKOFF_SPGMKOFF1_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG1MASKOFF_SPGMKOFF1_SHIFT (0U) /*! SPGMKOFF1 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG1MASKOFF_SPGMKOFF1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1MASKOFF_SPGMKOFF1_SHIFT)) & IRIS_MVPL_TCON0_SPG1MASKOFF_SPGMKOFF1_MASK) /*! @} */ /*! @name TCON0_SPG2POSON - Sync pulse generator 2, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_Y2_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_Y2_SHIFT (0U) /*! SPGPSON_Y2 - Y scan position */ #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_Y2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_Y2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_Y2_MASK) #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_FIELD2_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_FIELD2_SHIFT (15U) /*! SPGPSON_FIELD2 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_FIELD2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_FIELD2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_FIELD2_MASK) #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_X2_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_X2_SHIFT (16U) /*! SPGPSON_X2 - X scan position */ #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_X2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_X2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_X2_MASK) #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_TOGGLE2_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_TOGGLE2_SHIFT (31U) /*! SPGPSON_TOGGLE2 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_TOGGLE2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_TOGGLE2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_TOGGLE2_MASK) /*! @} */ /*! @name TCON0_SPG2MASKON - The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG2MASKON_SPGMKON2_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG2MASKON_SPGMKON2_SHIFT (0U) /*! SPGMKON2 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG2MASKON_SPGMKON2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2MASKON_SPGMKON2_SHIFT)) & IRIS_MVPL_TCON0_SPG2MASKON_SPGMKON2_MASK) /*! @} */ /*! @name TCON0_SPG2POSOFF - Sync pulse generator 2, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_Y2_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_Y2_SHIFT (0U) /*! SPGPSOFF_Y2 - Y scan position */ #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_Y2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_Y2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_Y2_MASK) #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT (15U) /*! SPGPSOFF_FIELD2 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_MASK) #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_X2_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_X2_SHIFT (16U) /*! SPGPSOFF_X2 - X scan position */ #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_X2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_X2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_X2_MASK) #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT (31U) /*! SPGPSOFF_TOGGLE2 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK) /*! @} */ /*! @name TCON0_SPG2MASKOFF - The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG2MASKOFF_SPGMKOFF2_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG2MASKOFF_SPGMKOFF2_SHIFT (0U) /*! SPGMKOFF2 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG2MASKOFF_SPGMKOFF2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2MASKOFF_SPGMKOFF2_SHIFT)) & IRIS_MVPL_TCON0_SPG2MASKOFF_SPGMKOFF2_MASK) /*! @} */ /*! @name TCON0_SPG3POSON - Sync pulse generator 3, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_Y3_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_Y3_SHIFT (0U) /*! SPGPSON_Y3 - Y scan position */ #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_Y3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_Y3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_Y3_MASK) #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_FIELD3_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_FIELD3_SHIFT (15U) /*! SPGPSON_FIELD3 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_FIELD3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_FIELD3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_FIELD3_MASK) #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_X3_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_X3_SHIFT (16U) /*! SPGPSON_X3 - X scan position */ #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_X3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_X3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_X3_MASK) #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_TOGGLE3_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_TOGGLE3_SHIFT (31U) /*! SPGPSON_TOGGLE3 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_TOGGLE3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_TOGGLE3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_TOGGLE3_MASK) /*! @} */ /*! @name TCON0_SPG3MASKON - The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG3MASKON_SPGMKON3_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG3MASKON_SPGMKON3_SHIFT (0U) /*! SPGMKON3 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG3MASKON_SPGMKON3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3MASKON_SPGMKON3_SHIFT)) & IRIS_MVPL_TCON0_SPG3MASKON_SPGMKON3_MASK) /*! @} */ /*! @name TCON0_SPG3POSOFF - Sync pulse generator 3, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_Y3_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_Y3_SHIFT (0U) /*! SPGPSOFF_Y3 - Y scan position */ #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_Y3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_Y3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_Y3_MASK) #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT (15U) /*! SPGPSOFF_FIELD3 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_MASK) #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_X3_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_X3_SHIFT (16U) /*! SPGPSOFF_X3 - X scan position */ #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_X3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_X3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_X3_MASK) #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT (31U) /*! SPGPSOFF_TOGGLE3 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK) /*! @} */ /*! @name TCON0_SPG3MASKOFF - The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG3MASKOFF_SPGMKOFF3_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG3MASKOFF_SPGMKOFF3_SHIFT (0U) /*! SPGMKOFF3 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG3MASKOFF_SPGMKOFF3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3MASKOFF_SPGMKOFF3_SHIFT)) & IRIS_MVPL_TCON0_SPG3MASKOFF_SPGMKOFF3_MASK) /*! @} */ /*! @name TCON0_SPG4POSON - Sync pulse generator 4, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_Y4_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_Y4_SHIFT (0U) /*! SPGPSON_Y4 - Y scan position */ #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_Y4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_Y4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_Y4_MASK) #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_FIELD4_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_FIELD4_SHIFT (15U) /*! SPGPSON_FIELD4 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_FIELD4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_FIELD4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_FIELD4_MASK) #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_X4_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_X4_SHIFT (16U) /*! SPGPSON_X4 - X scan position */ #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_X4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_X4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_X4_MASK) #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_TOGGLE4_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_TOGGLE4_SHIFT (31U) /*! SPGPSON_TOGGLE4 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_TOGGLE4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_TOGGLE4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_TOGGLE4_MASK) /*! @} */ /*! @name TCON0_SPG4MASKON - The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG4MASKON_SPGMKON4_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG4MASKON_SPGMKON4_SHIFT (0U) /*! SPGMKON4 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG4MASKON_SPGMKON4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4MASKON_SPGMKON4_SHIFT)) & IRIS_MVPL_TCON0_SPG4MASKON_SPGMKON4_MASK) /*! @} */ /*! @name TCON0_SPG4POSOFF - Sync pulse generator 4, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_Y4_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_Y4_SHIFT (0U) /*! SPGPSOFF_Y4 - Y scan position */ #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_Y4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_Y4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_Y4_MASK) #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT (15U) /*! SPGPSOFF_FIELD4 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_MASK) #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_X4_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_X4_SHIFT (16U) /*! SPGPSOFF_X4 - X scan position */ #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_X4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_X4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_X4_MASK) #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT (31U) /*! SPGPSOFF_TOGGLE4 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK) /*! @} */ /*! @name TCON0_SPG4MASKOFF - The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG4MASKOFF_SPGMKOFF4_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG4MASKOFF_SPGMKOFF4_SHIFT (0U) /*! SPGMKOFF4 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG4MASKOFF_SPGMKOFF4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4MASKOFF_SPGMKOFF4_SHIFT)) & IRIS_MVPL_TCON0_SPG4MASKOFF_SPGMKOFF4_MASK) /*! @} */ /*! @name TCON0_SPG5POSON - Sync pulse generator 5, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_Y5_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_Y5_SHIFT (0U) /*! SPGPSON_Y5 - Y scan position */ #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_Y5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_Y5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_Y5_MASK) #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_FIELD5_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_FIELD5_SHIFT (15U) /*! SPGPSON_FIELD5 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_FIELD5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_FIELD5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_FIELD5_MASK) #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_X5_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_X5_SHIFT (16U) /*! SPGPSON_X5 - X scan position */ #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_X5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_X5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_X5_MASK) #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_TOGGLE5_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_TOGGLE5_SHIFT (31U) /*! SPGPSON_TOGGLE5 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_TOGGLE5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_TOGGLE5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_TOGGLE5_MASK) /*! @} */ /*! @name TCON0_SPG5MASKON - The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG5MASKON_SPGMKON5_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG5MASKON_SPGMKON5_SHIFT (0U) /*! SPGMKON5 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG5MASKON_SPGMKON5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5MASKON_SPGMKON5_SHIFT)) & IRIS_MVPL_TCON0_SPG5MASKON_SPGMKON5_MASK) /*! @} */ /*! @name TCON0_SPG5POSOFF - Sync pulse generator 5, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_Y5_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_Y5_SHIFT (0U) /*! SPGPSOFF_Y5 - Y scan position */ #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_Y5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_Y5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_Y5_MASK) #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT (15U) /*! SPGPSOFF_FIELD5 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_MASK) #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_X5_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_X5_SHIFT (16U) /*! SPGPSOFF_X5 - X scan position */ #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_X5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_X5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_X5_MASK) #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT (31U) /*! SPGPSOFF_TOGGLE5 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK) /*! @} */ /*! @name TCON0_SPG5MASKOFF - The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG5MASKOFF_SPGMKOFF5_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG5MASKOFF_SPGMKOFF5_SHIFT (0U) /*! SPGMKOFF5 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG5MASKOFF_SPGMKOFF5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5MASKOFF_SPGMKOFF5_SHIFT)) & IRIS_MVPL_TCON0_SPG5MASKOFF_SPGMKOFF5_MASK) /*! @} */ /*! @name TCON0_SPG6POSON - Sync pulse generator 6, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_Y6_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_Y6_SHIFT (0U) /*! SPGPSON_Y6 - Y scan position */ #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_Y6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_Y6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_Y6_MASK) #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_FIELD6_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_FIELD6_SHIFT (15U) /*! SPGPSON_FIELD6 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_FIELD6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_FIELD6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_FIELD6_MASK) #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_X6_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_X6_SHIFT (16U) /*! SPGPSON_X6 - X scan position */ #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_X6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_X6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_X6_MASK) #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_TOGGLE6_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_TOGGLE6_SHIFT (31U) /*! SPGPSON_TOGGLE6 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_TOGGLE6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_TOGGLE6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_TOGGLE6_MASK) /*! @} */ /*! @name TCON0_SPG6MASKON - The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG6MASKON_SPGMKON6_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG6MASKON_SPGMKON6_SHIFT (0U) /*! SPGMKON6 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG6MASKON_SPGMKON6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6MASKON_SPGMKON6_SHIFT)) & IRIS_MVPL_TCON0_SPG6MASKON_SPGMKON6_MASK) /*! @} */ /*! @name TCON0_SPG6POSOFF - Sync pulse generator 6, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_Y6_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_Y6_SHIFT (0U) /*! SPGPSOFF_Y6 - Y scan position */ #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_Y6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_Y6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_Y6_MASK) #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT (15U) /*! SPGPSOFF_FIELD6 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_MASK) #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_X6_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_X6_SHIFT (16U) /*! SPGPSOFF_X6 - X scan position */ #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_X6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_X6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_X6_MASK) #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT (31U) /*! SPGPSOFF_TOGGLE6 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK) /*! @} */ /*! @name TCON0_SPG6MASKOFF - The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG6MASKOFF_SPGMKOFF6_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG6MASKOFF_SPGMKOFF6_SHIFT (0U) /*! SPGMKOFF6 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG6MASKOFF_SPGMKOFF6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6MASKOFF_SPGMKOFF6_SHIFT)) & IRIS_MVPL_TCON0_SPG6MASKOFF_SPGMKOFF6_MASK) /*! @} */ /*! @name TCON0_SPG7POSON - Sync pulse generator 7, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_Y7_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_Y7_SHIFT (0U) /*! SPGPSON_Y7 - Y scan position */ #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_Y7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_Y7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_Y7_MASK) #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_FIELD7_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_FIELD7_SHIFT (15U) /*! SPGPSON_FIELD7 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_FIELD7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_FIELD7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_FIELD7_MASK) #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_X7_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_X7_SHIFT (16U) /*! SPGPSON_X7 - X scan position */ #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_X7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_X7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_X7_MASK) #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_TOGGLE7_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_TOGGLE7_SHIFT (31U) /*! SPGPSON_TOGGLE7 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_TOGGLE7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_TOGGLE7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_TOGGLE7_MASK) /*! @} */ /*! @name TCON0_SPG7MASKON - The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG7MASKON_SPGMKON7_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG7MASKON_SPGMKON7_SHIFT (0U) /*! SPGMKON7 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG7MASKON_SPGMKON7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7MASKON_SPGMKON7_SHIFT)) & IRIS_MVPL_TCON0_SPG7MASKON_SPGMKON7_MASK) /*! @} */ /*! @name TCON0_SPG7POSOFF - Sync pulse generator 7, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_Y7_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_Y7_SHIFT (0U) /*! SPGPSOFF_Y7 - Y scan position */ #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_Y7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_Y7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_Y7_MASK) #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT (15U) /*! SPGPSOFF_FIELD7 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_MASK) #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_X7_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_X7_SHIFT (16U) /*! SPGPSOFF_X7 - X scan position */ #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_X7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_X7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_X7_MASK) #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT (31U) /*! SPGPSOFF_TOGGLE7 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK) /*! @} */ /*! @name TCON0_SPG7MASKOFF - The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG7MASKOFF_SPGMKOFF7_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG7MASKOFF_SPGMKOFF7_SHIFT (0U) /*! SPGMKOFF7 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG7MASKOFF_SPGMKOFF7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7MASKOFF_SPGMKOFF7_SHIFT)) & IRIS_MVPL_TCON0_SPG7MASKOFF_SPGMKOFF7_MASK) /*! @} */ /*! @name TCON0_SPG8POSON - Sync pulse generator 8, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_Y8_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_Y8_SHIFT (0U) /*! SPGPSON_Y8 - Y scan position */ #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_Y8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_Y8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_Y8_MASK) #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_FIELD8_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_FIELD8_SHIFT (15U) /*! SPGPSON_FIELD8 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_FIELD8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_FIELD8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_FIELD8_MASK) #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_X8_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_X8_SHIFT (16U) /*! SPGPSON_X8 - X scan position */ #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_X8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_X8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_X8_MASK) #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_TOGGLE8_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_TOGGLE8_SHIFT (31U) /*! SPGPSON_TOGGLE8 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_TOGGLE8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_TOGGLE8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_TOGGLE8_MASK) /*! @} */ /*! @name TCON0_SPG8MASKON - The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG8MASKON_SPGMKON8_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG8MASKON_SPGMKON8_SHIFT (0U) /*! SPGMKON8 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG8MASKON_SPGMKON8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8MASKON_SPGMKON8_SHIFT)) & IRIS_MVPL_TCON0_SPG8MASKON_SPGMKON8_MASK) /*! @} */ /*! @name TCON0_SPG8POSOFF - Sync pulse generator 8, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_Y8_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_Y8_SHIFT (0U) /*! SPGPSOFF_Y8 - Y scan position */ #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_Y8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_Y8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_Y8_MASK) #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT (15U) /*! SPGPSOFF_FIELD8 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_MASK) #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_X8_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_X8_SHIFT (16U) /*! SPGPSOFF_X8 - X scan position */ #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_X8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_X8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_X8_MASK) #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT (31U) /*! SPGPSOFF_TOGGLE8 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK) /*! @} */ /*! @name TCON0_SPG8MASKOFF - The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG8MASKOFF_SPGMKOFF8_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG8MASKOFF_SPGMKOFF8_SHIFT (0U) /*! SPGMKOFF8 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG8MASKOFF_SPGMKOFF8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8MASKOFF_SPGMKOFF8_SHIFT)) & IRIS_MVPL_TCON0_SPG8MASKOFF_SPGMKOFF8_MASK) /*! @} */ /*! @name TCON0_SPG9POSON - Sync pulse generator 9, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_Y9_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_Y9_SHIFT (0U) /*! SPGPSON_Y9 - Y scan position */ #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_Y9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_Y9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_Y9_MASK) #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_FIELD9_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_FIELD9_SHIFT (15U) /*! SPGPSON_FIELD9 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_FIELD9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_FIELD9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_FIELD9_MASK) #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_X9_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_X9_SHIFT (16U) /*! SPGPSON_X9 - X scan position */ #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_X9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_X9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_X9_MASK) #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_TOGGLE9_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_TOGGLE9_SHIFT (31U) /*! SPGPSON_TOGGLE9 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_TOGGLE9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_TOGGLE9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_TOGGLE9_MASK) /*! @} */ /*! @name TCON0_SPG9MASKON - The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG9MASKON_SPGMKON9_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG9MASKON_SPGMKON9_SHIFT (0U) /*! SPGMKON9 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG9MASKON_SPGMKON9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9MASKON_SPGMKON9_SHIFT)) & IRIS_MVPL_TCON0_SPG9MASKON_SPGMKON9_MASK) /*! @} */ /*! @name TCON0_SPG9POSOFF - Sync pulse generator 9, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_Y9_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_Y9_SHIFT (0U) /*! SPGPSOFF_Y9 - Y scan position */ #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_Y9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_Y9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_Y9_MASK) #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT (15U) /*! SPGPSOFF_FIELD9 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_MASK) #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_X9_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_X9_SHIFT (16U) /*! SPGPSOFF_X9 - X scan position */ #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_X9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_X9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_X9_MASK) #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT (31U) /*! SPGPSOFF_TOGGLE9 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK) /*! @} */ /*! @name TCON0_SPG9MASKOFF - The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG9MASKOFF_SPGMKOFF9_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG9MASKOFF_SPGMKOFF9_SHIFT (0U) /*! SPGMKOFF9 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG9MASKOFF_SPGMKOFF9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9MASKOFF_SPGMKOFF9_SHIFT)) & IRIS_MVPL_TCON0_SPG9MASKOFF_SPGMKOFF9_MASK) /*! @} */ /*! @name TCON0_SPG10POSON - Sync pulse generator 10, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_Y10_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_Y10_SHIFT (0U) /*! SPGPSON_Y10 - Y scan position */ #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_Y10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_Y10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_Y10_MASK) #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_FIELD10_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_FIELD10_SHIFT (15U) /*! SPGPSON_FIELD10 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_FIELD10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_FIELD10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_FIELD10_MASK) #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_X10_SHIFT (16U) /*! SPGPSON_X10 - X scan position */ #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_X10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_X10_MASK) #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_TOGGLE10_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_TOGGLE10_SHIFT (31U) /*! SPGPSON_TOGGLE10 - toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_TOGGLE10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_TOGGLE10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_TOGGLE10_MASK) /*! @} */ /*! @name TCON0_SPG10MASKON - The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG10MASKON_SPGMKON10_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG10MASKON_SPGMKON10_SHIFT (0U) /*! SPGMKON10 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG10MASKON_SPGMKON10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10MASKON_SPGMKON10_SHIFT)) & IRIS_MVPL_TCON0_SPG10MASKON_SPGMKON10_MASK) /*! @} */ /*! @name TCON0_SPG10POSOFF - Sync pulse generator 10, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_Y10_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_Y10_SHIFT (0U) /*! SPGPSOFF_Y10 - Y scan position */ #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_Y10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_Y10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_Y10_MASK) #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT (15U) /*! SPGPSOFF_FIELD10 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_MASK) #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_X10_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_X10_SHIFT (16U) /*! SPGPSOFF_X10 - X scan position */ #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_X10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_X10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_X10_MASK) #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT (31U) /*! SPGPSOFF_TOGGLE10 - toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK) /*! @} */ /*! @name TCON0_SPG10MASKOFF - The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG10MASKOFF_SPGMKOFF10_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG10MASKOFF_SPGMKOFF10_SHIFT (0U) /*! SPGMKOFF10 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG10MASKOFF_SPGMKOFF10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10MASKOFF_SPGMKOFF10_SHIFT)) & IRIS_MVPL_TCON0_SPG10MASKOFF_SPGMKOFF10_MASK) /*! @} */ /*! @name TCON0_SPG11POSON - Sync pulse generator 11, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_Y11_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_Y11_SHIFT (0U) /*! SPGPSON_Y11 - Y scan position */ #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_Y11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_Y11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_Y11_MASK) #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_FIELD11_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_FIELD11_SHIFT (15U) /*! SPGPSON_FIELD11 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_FIELD11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_FIELD11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_FIELD11_MASK) #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_X11_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_X11_SHIFT (16U) /*! SPGPSON_X11 - X scan position */ #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_X11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_X11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_X11_MASK) #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_TOGGLE11_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_TOGGLE11_SHIFT (31U) /*! SPGPSON_TOGGLE11 - toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_TOGGLE11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_TOGGLE11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_TOGGLE11_MASK) /*! @} */ /*! @name TCON0_SPG11MASKON - The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG11MASKON_SPGMKON11_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG11MASKON_SPGMKON11_SHIFT (0U) /*! SPGMKON11 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG11MASKON_SPGMKON11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11MASKON_SPGMKON11_SHIFT)) & IRIS_MVPL_TCON0_SPG11MASKON_SPGMKON11_MASK) /*! @} */ /*! @name TCON0_SPG11POSOFF - Sync pulse generator 11, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_Y11_MASK (0x7FFFU) #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_Y11_SHIFT (0U) /*! SPGPSOFF_Y11 - Y scan position */ #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_Y11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_Y11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_Y11_MASK) #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_MASK (0x8000U) #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT (15U) /*! SPGPSOFF_FIELD11 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_MASK) #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_X11_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_X11_SHIFT (16U) /*! SPGPSOFF_X11 - X scan position */ #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_X11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_X11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_X11_MASK) #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK (0x80000000U) #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT (31U) /*! SPGPSOFF_TOGGLE11 - toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK) /*! @} */ /*! @name TCON0_SPG11MASKOFF - The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11 */ /*! @{ */ #define IRIS_MVPL_TCON0_SPG11MASKOFF_SPGMKOFF11_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON0_SPG11MASKOFF_SPGMKOFF11_SHIFT (0U) /*! SPGMKOFF11 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON0_SPG11MASKOFF_SPGMKOFF11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11MASKOFF_SPGMKOFF11_SHIFT)) & IRIS_MVPL_TCON0_SPG11MASKOFF_SPGMKOFF11_MASK) /*! @} */ /*! @name TCON0_SMX0SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S0_SHIFT (0U) /*! SMX0SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S1_SHIFT (3U) /*! SMX0SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S2_SHIFT (6U) /*! SMX0SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S3_SHIFT (9U) /*! SMX0SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S4_SHIFT (12U) /*! SMX0SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX0FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX0FCTTABLE_SMXFCT0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX0FCTTABLE_SMXFCT0_SHIFT (0U) /*! SMXFCT0 - Sync mixer 0 function table */ #define IRIS_MVPL_TCON0_SMX0FCTTABLE_SMXFCT0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0FCTTABLE_SMXFCT0_SHIFT)) & IRIS_MVPL_TCON0_SMX0FCTTABLE_SMXFCT0_MASK) /*! @} */ /*! @name TCON0_SMX1SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S0_SHIFT (0U) /*! SMX1SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S1_SHIFT (3U) /*! SMX1SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S2_SHIFT (6U) /*! SMX1SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S3_SHIFT (9U) /*! SMX1SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S4_SHIFT (12U) /*! SMX1SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX1FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX1FCTTABLE_SMXFCT1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX1FCTTABLE_SMXFCT1_SHIFT (0U) /*! SMXFCT1 - Sync mixer 1 function table */ #define IRIS_MVPL_TCON0_SMX1FCTTABLE_SMXFCT1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1FCTTABLE_SMXFCT1_SHIFT)) & IRIS_MVPL_TCON0_SMX1FCTTABLE_SMXFCT1_MASK) /*! @} */ /*! @name TCON0_SMX2SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S0_SHIFT (0U) /*! SMX2SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S1_SHIFT (3U) /*! SMX2SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S2_SHIFT (6U) /*! SMX2SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S3_SHIFT (9U) /*! SMX2SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S4_SHIFT (12U) /*! SMX2SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX2FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX2FCTTABLE_SMXFCT2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX2FCTTABLE_SMXFCT2_SHIFT (0U) /*! SMXFCT2 - Sync mixer 2 function table */ #define IRIS_MVPL_TCON0_SMX2FCTTABLE_SMXFCT2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2FCTTABLE_SMXFCT2_SHIFT)) & IRIS_MVPL_TCON0_SMX2FCTTABLE_SMXFCT2_MASK) /*! @} */ /*! @name TCON0_SMX3SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S0_SHIFT (0U) /*! SMX3SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S1_SHIFT (3U) /*! SMX3SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S2_SHIFT (6U) /*! SMX3SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S3_SHIFT (9U) /*! SMX3SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S4_SHIFT (12U) /*! SMX3SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX3FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX3FCTTABLE_SMXFCT3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX3FCTTABLE_SMXFCT3_SHIFT (0U) /*! SMXFCT3 - Sync mixer 3 function table */ #define IRIS_MVPL_TCON0_SMX3FCTTABLE_SMXFCT3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3FCTTABLE_SMXFCT3_SHIFT)) & IRIS_MVPL_TCON0_SMX3FCTTABLE_SMXFCT3_MASK) /*! @} */ /*! @name TCON0_SMX4SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S0_SHIFT (0U) /*! SMX4SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S1_SHIFT (3U) /*! SMX4SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S2_SHIFT (6U) /*! SMX4SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S3_SHIFT (9U) /*! SMX4SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S4_SHIFT (12U) /*! SMX4SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX4FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX4FCTTABLE_SMXFCT4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX4FCTTABLE_SMXFCT4_SHIFT (0U) /*! SMXFCT4 - Sync mixer 4 function table */ #define IRIS_MVPL_TCON0_SMX4FCTTABLE_SMXFCT4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4FCTTABLE_SMXFCT4_SHIFT)) & IRIS_MVPL_TCON0_SMX4FCTTABLE_SMXFCT4_MASK) /*! @} */ /*! @name TCON0_SMX5SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S0_SHIFT (0U) /*! SMX5SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S1_SHIFT (3U) /*! SMX5SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S2_SHIFT (6U) /*! SMX5SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S3_SHIFT (9U) /*! SMX5SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S4_SHIFT (12U) /*! SMX5SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX5FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX5FCTTABLE_SMXFCT5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX5FCTTABLE_SMXFCT5_SHIFT (0U) /*! SMXFCT5 - Sync mixer 5 function table */ #define IRIS_MVPL_TCON0_SMX5FCTTABLE_SMXFCT5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5FCTTABLE_SMXFCT5_SHIFT)) & IRIS_MVPL_TCON0_SMX5FCTTABLE_SMXFCT5_MASK) /*! @} */ /*! @name TCON0_SMX6SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S0_SHIFT (0U) /*! SMX6SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S1_SHIFT (3U) /*! SMX6SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S2_SHIFT (6U) /*! SMX6SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S3_SHIFT (9U) /*! SMX6SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S4_SHIFT (12U) /*! SMX6SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX6FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX6FCTTABLE_SMXFCT6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX6FCTTABLE_SMXFCT6_SHIFT (0U) /*! SMXFCT6 - Sync mixer 6 function table */ #define IRIS_MVPL_TCON0_SMX6FCTTABLE_SMXFCT6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6FCTTABLE_SMXFCT6_SHIFT)) & IRIS_MVPL_TCON0_SMX6FCTTABLE_SMXFCT6_MASK) /*! @} */ /*! @name TCON0_SMX7SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S0_SHIFT (0U) /*! SMX7SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S1_SHIFT (3U) /*! SMX7SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S2_SHIFT (6U) /*! SMX7SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S3_SHIFT (9U) /*! SMX7SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S4_SHIFT (12U) /*! SMX7SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX7FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX7FCTTABLE_SMXFCT7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX7FCTTABLE_SMXFCT7_SHIFT (0U) /*! SMXFCT7 - Sync mixer 7 function table */ #define IRIS_MVPL_TCON0_SMX7FCTTABLE_SMXFCT7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7FCTTABLE_SMXFCT7_SHIFT)) & IRIS_MVPL_TCON0_SMX7FCTTABLE_SMXFCT7_MASK) /*! @} */ /*! @name TCON0_SMX8SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S0_SHIFT (0U) /*! SMX8SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S1_SHIFT (3U) /*! SMX8SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S2_SHIFT (6U) /*! SMX8SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S3_SHIFT (9U) /*! SMX8SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S4_SHIFT (12U) /*! SMX8SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX8FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX8FCTTABLE_SMXFCT8_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX8FCTTABLE_SMXFCT8_SHIFT (0U) /*! SMXFCT8 - Sync mixer 8 function table */ #define IRIS_MVPL_TCON0_SMX8FCTTABLE_SMXFCT8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8FCTTABLE_SMXFCT8_SHIFT)) & IRIS_MVPL_TCON0_SMX8FCTTABLE_SMXFCT8_MASK) /*! @} */ /*! @name TCON0_SMX9SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S0_SHIFT (0U) /*! SMX9SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S1_SHIFT (3U) /*! SMX9SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S2_SHIFT (6U) /*! SMX9SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S3_SHIFT (9U) /*! SMX9SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S4_SHIFT (12U) /*! SMX9SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX9FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX9FCTTABLE_SMXFCT9_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX9FCTTABLE_SMXFCT9_SHIFT (0U) /*! SMXFCT9 - Sync mixer 9 function table */ #define IRIS_MVPL_TCON0_SMX9FCTTABLE_SMXFCT9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9FCTTABLE_SMXFCT9_SHIFT)) & IRIS_MVPL_TCON0_SMX9FCTTABLE_SMXFCT9_MASK) /*! @} */ /*! @name TCON0_SMX10SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S0_SHIFT (0U) /*! SMX10SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S1_SHIFT (3U) /*! SMX10SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S2_SHIFT (6U) /*! SMX10SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S3_SHIFT (9U) /*! SMX10SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S4_SHIFT (12U) /*! SMX10SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX10FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX10FCTTABLE_SMXFCT10_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX10FCTTABLE_SMXFCT10_SHIFT (0U) /*! SMXFCT10 - Sync mixer 10 function table */ #define IRIS_MVPL_TCON0_SMX10FCTTABLE_SMXFCT10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10FCTTABLE_SMXFCT10_SHIFT)) & IRIS_MVPL_TCON0_SMX10FCTTABLE_SMXFCT10_MASK) /*! @} */ /*! @name TCON0_SMX11SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S0_SHIFT (0U) /*! SMX11SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S0_MASK) #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S1_SHIFT (3U) /*! SMX11SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S1_MASK) #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S2_SHIFT (6U) /*! SMX11SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S2_MASK) #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S3_SHIFT (9U) /*! SMX11SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S3_MASK) #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S4_SHIFT (12U) /*! SMX11SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S4_MASK) /*! @} */ /*! @name TCON0_SMX11FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON0_SMX11FCTTABLE_SMXFCT11_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON0_SMX11FCTTABLE_SMXFCT11_SHIFT (0U) /*! SMXFCT11 - Sync mixer 11 function table */ #define IRIS_MVPL_TCON0_SMX11FCTTABLE_SMXFCT11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11FCTTABLE_SMXFCT11_SHIFT)) & IRIS_MVPL_TCON0_SMX11FCTTABLE_SMXFCT11_MASK) /*! @} */ /*! @name TCON0_RESET_OVER_UNFERFLOW - reset status overflow and underflow of both dual channel fifos */ /*! @{ */ #define IRIS_MVPL_TCON0_RESET_OVER_UNFERFLOW_reset_status_MASK (0x1U) #define IRIS_MVPL_TCON0_RESET_OVER_UNFERFLOW_reset_status_SHIFT (0U) /*! reset_status - write a '1' to clear all overflow-Bits and underflow-Bits in Dual_Debug register */ #define IRIS_MVPL_TCON0_RESET_OVER_UNFERFLOW_reset_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_RESET_OVER_UNFERFLOW_reset_status_SHIFT)) & IRIS_MVPL_TCON0_RESET_OVER_UNFERFLOW_reset_status_MASK) /*! @} */ /*! @name TCON0_DUAL_DEBUG - Status of fifo during dual channel operation. They are only available in Split Mode For Debug only */ /*! @{ */ #define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_overflow_MASK (0x1U) #define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_overflow_SHIFT (0U) /*! lower_fifo_overflow - There are more input pixels than output pixels in a line of lower fifo * (too less horizontal blanking or others ...). Once it is set, it remains active until it's reset * on software reset or on Reset_Over_Unferflow/reset_status */ #define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_overflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_overflow_SHIFT)) & IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_overflow_MASK) #define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_underflow_MASK (0x2U) #define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_underflow_SHIFT (1U) /*! lower_fifo_underflow - There are less input pixels than output pixels in a line of lower fifo * (check data_en and split-position or others ...). Once it is set, it remains active until it's * reset on software reset or on Reset_Over_Unferflow/reset_status */ #define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_underflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_underflow_SHIFT)) & IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_underflow_MASK) #define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_overflow_MASK (0x10U) #define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_overflow_SHIFT (4U) /*! upper_fifo_overflow - There are more input pixels than output pixels in a line of upper fifo * (too less horizontal blanking or others ...). Once it is set, it remains active until it's reset * on software reset or on Reset_Over_Unferflow/reset_status */ #define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_overflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_overflow_SHIFT)) & IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_overflow_MASK) #define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_underflow_MASK (0x20U) #define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_underflow_SHIFT (5U) /*! upper_fifo_underflow - There are less input pixels than output pixels in a line of upper fifo * (check data_en and split-position or others ...). Once it is set, it remains active until it's * reset on software reset or on Reset_Over_Unferflow/reset_status */ #define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_underflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_underflow_SHIFT)) & IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_underflow_MASK) /*! @} */ /*! @name SIG0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_SIG0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_SIG0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_SIG0_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name SIG0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_SIG0_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_SIG0_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_SIG0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_SIG0_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_SIG0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_SIG0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_SIG0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_SIG0_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_SIG0_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_SIG0_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_SIG0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_SIG0_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name SIG0_STATICCONTROL - Global configuration shared by all evaluation windows. */ /*! @{ */ #define IRIS_MVPL_SIG0_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_SIG0_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadow registers for RWS type fields (0 = write through, 1 = shadowed). */ #define IRIS_MVPL_SIG0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_SIG0_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_SIG0_STATICCONTROL_ShdLdSel_MASK (0x10U) #define IRIS_MVPL_SIG0_STATICCONTROL_ShdLdSel_SHIFT (4U) /*! ShdLdSel - Source select for events that will load shadow registers into the active configuration. * 0b0..Shadows are loaded at start of frame for each evaluation window for which ShdLdReq has been set. * 0b1..Shadows of all evaluation windows are loaded synchronous to the display stream (shadow load token received on frame input port). */ #define IRIS_MVPL_SIG0_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_SIG0_STATICCONTROL_ShdLdSel_MASK) #define IRIS_MVPL_SIG0_STATICCONTROL_ErrThres_MASK (0xFF0000U) #define IRIS_MVPL_SIG0_STATICCONTROL_ErrThres_SHIFT (16U) /*! ErrThres - Number of frames with signature violation before StsSigError is set for an evaluation window. */ #define IRIS_MVPL_SIG0_STATICCONTROL_ErrThres(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATICCONTROL_ErrThres_SHIFT)) & IRIS_MVPL_SIG0_STATICCONTROL_ErrThres_MASK) #define IRIS_MVPL_SIG0_STATICCONTROL_ErrThresReset_MASK (0xFF000000U) #define IRIS_MVPL_SIG0_STATICCONTROL_ErrThresReset_SHIFT (24U) /*! ErrThresReset - Number of consecutive frames without signature violation before StsSigError is reset for an evaluation window. */ #define IRIS_MVPL_SIG0_STATICCONTROL_ErrThresReset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATICCONTROL_ErrThresReset_SHIFT)) & IRIS_MVPL_SIG0_STATICCONTROL_ErrThresReset_MASK) /*! @} */ /*! @name SIG0_PANICCOLOR - Overlay color for evaluation windows in panic mode. */ /*! @{ */ #define IRIS_MVPL_SIG0_PANICCOLOR_PanicAlpha_MASK (0x80U) #define IRIS_MVPL_SIG0_PANICCOLOR_PanicAlpha_SHIFT (7U) /*! PanicAlpha - Alpha mask bit. */ #define IRIS_MVPL_SIG0_PANICCOLOR_PanicAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_PANICCOLOR_PanicAlpha_SHIFT)) & IRIS_MVPL_SIG0_PANICCOLOR_PanicAlpha_MASK) #define IRIS_MVPL_SIG0_PANICCOLOR_PanicBlue_MASK (0xFF00U) #define IRIS_MVPL_SIG0_PANICCOLOR_PanicBlue_SHIFT (8U) /*! PanicBlue - Blue color component. */ #define IRIS_MVPL_SIG0_PANICCOLOR_PanicBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_PANICCOLOR_PanicBlue_SHIFT)) & IRIS_MVPL_SIG0_PANICCOLOR_PanicBlue_MASK) #define IRIS_MVPL_SIG0_PANICCOLOR_PanicGreen_MASK (0xFF0000U) #define IRIS_MVPL_SIG0_PANICCOLOR_PanicGreen_SHIFT (16U) /*! PanicGreen - Green color component. */ #define IRIS_MVPL_SIG0_PANICCOLOR_PanicGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_PANICCOLOR_PanicGreen_SHIFT)) & IRIS_MVPL_SIG0_PANICCOLOR_PanicGreen_MASK) #define IRIS_MVPL_SIG0_PANICCOLOR_PanicRed_MASK (0xFF000000U) #define IRIS_MVPL_SIG0_PANICCOLOR_PanicRed_SHIFT (24U) /*! PanicRed - Red color component. */ #define IRIS_MVPL_SIG0_PANICCOLOR_PanicRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_PANICCOLOR_PanicRed_SHIFT)) & IRIS_MVPL_SIG0_PANICCOLOR_PanicRed_MASK) /*! @} */ /*! @name SIG0_EVALCONTROL0 - Control settings for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALCONTROL0_EnEvalWin0_MASK (0x1U) #define IRIS_MVPL_SIG0_EVALCONTROL0_EnEvalWin0_SHIFT (0U) /*! EnEvalWin0 - When enabled (value 1) a CRC signature is computed for all pixels inside this evaluation window (SigCRC). */ #define IRIS_MVPL_SIG0_EVALCONTROL0_EnEvalWin0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_EnEvalWin0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_EnEvalWin0_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL0_EnCRC0_MASK (0x2U) #define IRIS_MVPL_SIG0_EVALCONTROL0_EnCRC0_SHIFT (1U) /*! EnCRC0 - When enabled (value 1) the measured signature is checked against a reference value (SigCRCRef). */ #define IRIS_MVPL_SIG0_EVALCONTROL0_EnCRC0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_EnCRC0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_EnCRC0_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaMask0_MASK (0x100U) #define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaMask0_SHIFT (8U) /*! AlphaMask0 - When enabled (value 1) pixels with alpha bit = 0 are ignored for signature computation. */ #define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaMask0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_AlphaMask0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_AlphaMask0_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaInv0_MASK (0x200U) #define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaInv0_SHIFT (9U) /*! AlphaInv0 - When enabled (value 1) the effect of AlphaMask is inverted (pixels with alpha bit = 1 are ignored then). */ #define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaInv0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_AlphaInv0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_AlphaInv0_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL0_EnLocalPanic0_MASK (0x10000U) #define IRIS_MVPL_SIG0_EVALCONTROL0_EnLocalPanic0_SHIFT (16U) /*! EnLocalPanic0 - When enabled (value 1) the error status this window (StsSigError) will replace * all pixels inside the window by a constant color on the display. Skip regions due to other * evaluation windows on top are not modified. AlphaMask, when enabled, is not considered for this * replacement. */ #define IRIS_MVPL_SIG0_EVALCONTROL0_EnLocalPanic0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_EnLocalPanic0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_EnLocalPanic0_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL0_EnGlobalPanic0_MASK (0x20000U) #define IRIS_MVPL_SIG0_EVALCONTROL0_EnGlobalPanic0_SHIFT (17U) /*! EnGlobalPanic0 - When enabled (value 1) the error status of this window (StsSigError) will * activate the panic mode of the display stream's Frame Generator, which can switch to another * display mode in response. */ #define IRIS_MVPL_SIG0_EVALCONTROL0_EnGlobalPanic0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_EnGlobalPanic0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_EnGlobalPanic0_MASK) /*! @} */ /*! @name SIG0_EVALUPPERLEFT0 - Upper left corner of evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT0_XEvalUpperLeft0_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALUPPERLEFT0_XEvalUpperLeft0_SHIFT (0U) /*! XEvalUpperLeft0 - X coordinate. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT0_XEvalUpperLeft0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT0_XEvalUpperLeft0_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT0_XEvalUpperLeft0_MASK) #define IRIS_MVPL_SIG0_EVALUPPERLEFT0_YEvalUpperLeft0_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALUPPERLEFT0_YEvalUpperLeft0_SHIFT (16U) /*! YEvalUpperLeft0 - Y coordinate. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT0_YEvalUpperLeft0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT0_YEvalUpperLeft0_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT0_YEvalUpperLeft0_MASK) /*! @} */ /*! @name SIG0_EVALLOWERRIGHT0 - Lower right corner of evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_XEvalLowerRight0_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_XEvalLowerRight0_SHIFT (0U) /*! XEvalLowerRight0 - X coordinate. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_XEvalLowerRight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT0_XEvalLowerRight0_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT0_XEvalLowerRight0_MASK) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_YEvalLowerRight0_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_YEvalLowerRight0_SHIFT (16U) /*! YEvalLowerRight0 - Y coordinate. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_YEvalLowerRight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT0_YEvalLowerRight0_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT0_YEvalLowerRight0_MASK) /*! @} */ /*! @name SIG0_SIGCRCREDREF0 - Reference signature of red channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCREDREF0_SigCRCRedRef0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCREDREF0_SigCRCRedRef0_SHIFT (0U) /*! SigCRCRedRef0 - Reference value that is compared against measured SigCRCRed value. */ #define IRIS_MVPL_SIG0_SIGCRCREDREF0_SigCRCRedRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF0_SigCRCRedRef0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF0_SigCRCRedRef0_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREENREF0 - Reference signature of green channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF0_SigCRCGreenRef0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREENREF0_SigCRCGreenRef0_SHIFT (0U) /*! SigCRCGreenRef0 - Reference value that is compared against measured SigCRCGreen value. */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF0_SigCRCGreenRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF0_SigCRCGreenRef0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF0_SigCRCGreenRef0_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUEREF0 - Reference signature of blue channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF0_SigCRCBlueRef0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUEREF0_SigCRCBlueRef0_SHIFT (0U) /*! SigCRCBlueRef0 - Reference value that is compared against measured SigCRCBlue value. */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF0_SigCRCBlueRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF0_SigCRCBlueRef0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF0_SigCRCBlueRef0_MASK) /*! @} */ /*! @name SIG0_SIGCRCRED0 - Measured signature of red channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCRED0_SigCRCRed0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCRED0_SigCRCRed0_SHIFT (0U) /*! SigCRCRed0 - CRC values from red channel. */ #define IRIS_MVPL_SIG0_SIGCRCRED0_SigCRCRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED0_SigCRCRed0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED0_SigCRCRed0_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREEN0 - Measured signature of green channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREEN0_SigCRCGreen0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREEN0_SigCRCGreen0_SHIFT (0U) /*! SigCRCGreen0 - CRC values from green channel. */ #define IRIS_MVPL_SIG0_SIGCRCGREEN0_SigCRCGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN0_SigCRCGreen0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN0_SigCRCGreen0_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUE0 - Measured signature of blue channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUE0_SigCRCBlue0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUE0_SigCRCBlue0_SHIFT (0U) /*! SigCRCBlue0 - CRC values from blue channel. */ #define IRIS_MVPL_SIG0_SIGCRCBLUE0_SigCRCBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE0_SigCRCBlue0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE0_SigCRCBlue0_MASK) /*! @} */ /*! @name SIG0_EVALCONTROL1 - Control settings for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALCONTROL1_EnEvalWin1_MASK (0x1U) #define IRIS_MVPL_SIG0_EVALCONTROL1_EnEvalWin1_SHIFT (0U) /*! EnEvalWin1 - See EnEvalWin0. */ #define IRIS_MVPL_SIG0_EVALCONTROL1_EnEvalWin1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_EnEvalWin1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_EnEvalWin1_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL1_EnCRC1_MASK (0x2U) #define IRIS_MVPL_SIG0_EVALCONTROL1_EnCRC1_SHIFT (1U) /*! EnCRC1 - See EnCRC0. */ #define IRIS_MVPL_SIG0_EVALCONTROL1_EnCRC1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_EnCRC1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_EnCRC1_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaMask1_MASK (0x100U) #define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaMask1_SHIFT (8U) /*! AlphaMask1 - See AlphaMask0. */ #define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaMask1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_AlphaMask1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_AlphaMask1_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaInv1_MASK (0x200U) #define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaInv1_SHIFT (9U) /*! AlphaInv1 - See AlphaInv0. */ #define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaInv1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_AlphaInv1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_AlphaInv1_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL1_EnLocalPanic1_MASK (0x10000U) #define IRIS_MVPL_SIG0_EVALCONTROL1_EnLocalPanic1_SHIFT (16U) /*! EnLocalPanic1 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL1_EnLocalPanic1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_EnLocalPanic1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_EnLocalPanic1_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL1_EnGlobalPanic1_MASK (0x20000U) #define IRIS_MVPL_SIG0_EVALCONTROL1_EnGlobalPanic1_SHIFT (17U) /*! EnGlobalPanic1 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL1_EnGlobalPanic1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_EnGlobalPanic1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_EnGlobalPanic1_MASK) /*! @} */ /*! @name SIG0_EVALUPPERLEFT1 - Upper left corner of evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT1_XEvalUpperLeft1_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALUPPERLEFT1_XEvalUpperLeft1_SHIFT (0U) /*! XEvalUpperLeft1 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT1_XEvalUpperLeft1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT1_XEvalUpperLeft1_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT1_XEvalUpperLeft1_MASK) #define IRIS_MVPL_SIG0_EVALUPPERLEFT1_YEvalUpperLeft1_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALUPPERLEFT1_YEvalUpperLeft1_SHIFT (16U) /*! YEvalUpperLeft1 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT1_YEvalUpperLeft1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT1_YEvalUpperLeft1_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT1_YEvalUpperLeft1_MASK) /*! @} */ /*! @name SIG0_EVALLOWERRIGHT1 - Lower right corner of evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_XEvalLowerRight1_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_XEvalLowerRight1_SHIFT (0U) /*! XEvalLowerRight1 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_XEvalLowerRight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT1_XEvalLowerRight1_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT1_XEvalLowerRight1_MASK) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_YEvalLowerRight1_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_YEvalLowerRight1_SHIFT (16U) /*! YEvalLowerRight1 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_YEvalLowerRight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT1_YEvalLowerRight1_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT1_YEvalLowerRight1_MASK) /*! @} */ /*! @name SIG0_SIGCRCREDREF1 - Reference signature of red channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCREDREF1_SigCRCRedRef1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCREDREF1_SigCRCRedRef1_SHIFT (0U) /*! SigCRCRedRef1 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG0_SIGCRCREDREF1_SigCRCRedRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF1_SigCRCRedRef1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF1_SigCRCRedRef1_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREENREF1 - Reference signature of green channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF1_SigCRCGreenRef1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREENREF1_SigCRCGreenRef1_SHIFT (0U) /*! SigCRCGreenRef1 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF1_SigCRCGreenRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF1_SigCRCGreenRef1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF1_SigCRCGreenRef1_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUEREF1 - Reference signature of blue channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF1_SigCRCBlueRef1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUEREF1_SigCRCBlueRef1_SHIFT (0U) /*! SigCRCBlueRef1 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF1_SigCRCBlueRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF1_SigCRCBlueRef1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF1_SigCRCBlueRef1_MASK) /*! @} */ /*! @name SIG0_SIGCRCRED1 - Measured signature of red channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCRED1_SigCRCRed1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCRED1_SigCRCRed1_SHIFT (0U) /*! SigCRCRed1 - See SigCRCRed0. */ #define IRIS_MVPL_SIG0_SIGCRCRED1_SigCRCRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED1_SigCRCRed1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED1_SigCRCRed1_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREEN1 - Measured signature of green channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREEN1_SigCRCGreen1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREEN1_SigCRCGreen1_SHIFT (0U) /*! SigCRCGreen1 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG0_SIGCRCGREEN1_SigCRCGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN1_SigCRCGreen1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN1_SigCRCGreen1_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUE1 - Measured signature of blue channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUE1_SigCRCBlue1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUE1_SigCRCBlue1_SHIFT (0U) /*! SigCRCBlue1 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUE1_SigCRCBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE1_SigCRCBlue1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE1_SigCRCBlue1_MASK) /*! @} */ /*! @name SIG0_EVALCONTROL2 - Control settings for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALCONTROL2_EnEvalWin2_MASK (0x1U) #define IRIS_MVPL_SIG0_EVALCONTROL2_EnEvalWin2_SHIFT (0U) /*! EnEvalWin2 - See EnEvalWin0. */ #define IRIS_MVPL_SIG0_EVALCONTROL2_EnEvalWin2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_EnEvalWin2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_EnEvalWin2_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL2_EnCRC2_MASK (0x2U) #define IRIS_MVPL_SIG0_EVALCONTROL2_EnCRC2_SHIFT (1U) /*! EnCRC2 - See EnCRC0. */ #define IRIS_MVPL_SIG0_EVALCONTROL2_EnCRC2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_EnCRC2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_EnCRC2_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaMask2_MASK (0x100U) #define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaMask2_SHIFT (8U) /*! AlphaMask2 - See AlphaMask0. */ #define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaMask2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_AlphaMask2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_AlphaMask2_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaInv2_MASK (0x200U) #define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaInv2_SHIFT (9U) /*! AlphaInv2 - See AlphaInv0. */ #define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaInv2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_AlphaInv2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_AlphaInv2_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL2_EnLocalPanic2_MASK (0x10000U) #define IRIS_MVPL_SIG0_EVALCONTROL2_EnLocalPanic2_SHIFT (16U) /*! EnLocalPanic2 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL2_EnLocalPanic2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_EnLocalPanic2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_EnLocalPanic2_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL2_EnGlobalPanic2_MASK (0x20000U) #define IRIS_MVPL_SIG0_EVALCONTROL2_EnGlobalPanic2_SHIFT (17U) /*! EnGlobalPanic2 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL2_EnGlobalPanic2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_EnGlobalPanic2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_EnGlobalPanic2_MASK) /*! @} */ /*! @name SIG0_EVALUPPERLEFT2 - Upper left corner of evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT2_XEvalUpperLeft2_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALUPPERLEFT2_XEvalUpperLeft2_SHIFT (0U) /*! XEvalUpperLeft2 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT2_XEvalUpperLeft2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT2_XEvalUpperLeft2_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT2_XEvalUpperLeft2_MASK) #define IRIS_MVPL_SIG0_EVALUPPERLEFT2_YEvalUpperLeft2_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALUPPERLEFT2_YEvalUpperLeft2_SHIFT (16U) /*! YEvalUpperLeft2 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT2_YEvalUpperLeft2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT2_YEvalUpperLeft2_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT2_YEvalUpperLeft2_MASK) /*! @} */ /*! @name SIG0_EVALLOWERRIGHT2 - Lower right corner of evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_XEvalLowerRight2_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_XEvalLowerRight2_SHIFT (0U) /*! XEvalLowerRight2 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_XEvalLowerRight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT2_XEvalLowerRight2_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT2_XEvalLowerRight2_MASK) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_YEvalLowerRight2_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_YEvalLowerRight2_SHIFT (16U) /*! YEvalLowerRight2 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_YEvalLowerRight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT2_YEvalLowerRight2_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT2_YEvalLowerRight2_MASK) /*! @} */ /*! @name SIG0_SIGCRCREDREF2 - Reference signature of red channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCREDREF2_SigCRCRedRef2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCREDREF2_SigCRCRedRef2_SHIFT (0U) /*! SigCRCRedRef2 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG0_SIGCRCREDREF2_SigCRCRedRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF2_SigCRCRedRef2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF2_SigCRCRedRef2_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREENREF2 - Reference signature of green channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF2_SigCRCGreenRef2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREENREF2_SigCRCGreenRef2_SHIFT (0U) /*! SigCRCGreenRef2 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF2_SigCRCGreenRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF2_SigCRCGreenRef2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF2_SigCRCGreenRef2_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUEREF2 - Reference signature of blue channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF2_SigCRCBlueRef2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUEREF2_SigCRCBlueRef2_SHIFT (0U) /*! SigCRCBlueRef2 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF2_SigCRCBlueRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF2_SigCRCBlueRef2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF2_SigCRCBlueRef2_MASK) /*! @} */ /*! @name SIG0_SIGCRCRED2 - Measured signature of red channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCRED2_SigCRCRed2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCRED2_SigCRCRed2_SHIFT (0U) /*! SigCRCRed2 - See SigCRCRed0. */ #define IRIS_MVPL_SIG0_SIGCRCRED2_SigCRCRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED2_SigCRCRed2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED2_SigCRCRed2_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREEN2 - Measured signature of green channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREEN2_SigCRCGreen2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREEN2_SigCRCGreen2_SHIFT (0U) /*! SigCRCGreen2 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG0_SIGCRCGREEN2_SigCRCGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN2_SigCRCGreen2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN2_SigCRCGreen2_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUE2 - Measured signature of blue channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUE2_SigCRCBlue2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUE2_SigCRCBlue2_SHIFT (0U) /*! SigCRCBlue2 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUE2_SigCRCBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE2_SigCRCBlue2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE2_SigCRCBlue2_MASK) /*! @} */ /*! @name SIG0_EVALCONTROL3 - Control settings for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALCONTROL3_EnEvalWin3_MASK (0x1U) #define IRIS_MVPL_SIG0_EVALCONTROL3_EnEvalWin3_SHIFT (0U) /*! EnEvalWin3 - See EnEvalWin0. */ #define IRIS_MVPL_SIG0_EVALCONTROL3_EnEvalWin3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_EnEvalWin3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_EnEvalWin3_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL3_EnCRC3_MASK (0x2U) #define IRIS_MVPL_SIG0_EVALCONTROL3_EnCRC3_SHIFT (1U) /*! EnCRC3 - See EnCRC0. */ #define IRIS_MVPL_SIG0_EVALCONTROL3_EnCRC3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_EnCRC3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_EnCRC3_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaMask3_MASK (0x100U) #define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaMask3_SHIFT (8U) /*! AlphaMask3 - See AlphaMask0. */ #define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaMask3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_AlphaMask3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_AlphaMask3_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaInv3_MASK (0x200U) #define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaInv3_SHIFT (9U) /*! AlphaInv3 - See AlphaInv0. */ #define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaInv3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_AlphaInv3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_AlphaInv3_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL3_EnLocalPanic3_MASK (0x10000U) #define IRIS_MVPL_SIG0_EVALCONTROL3_EnLocalPanic3_SHIFT (16U) /*! EnLocalPanic3 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL3_EnLocalPanic3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_EnLocalPanic3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_EnLocalPanic3_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL3_EnGlobalPanic3_MASK (0x20000U) #define IRIS_MVPL_SIG0_EVALCONTROL3_EnGlobalPanic3_SHIFT (17U) /*! EnGlobalPanic3 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL3_EnGlobalPanic3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_EnGlobalPanic3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_EnGlobalPanic3_MASK) /*! @} */ /*! @name SIG0_EVALUPPERLEFT3 - Upper left corner of evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT3_XEvalUpperLeft3_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALUPPERLEFT3_XEvalUpperLeft3_SHIFT (0U) /*! XEvalUpperLeft3 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT3_XEvalUpperLeft3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT3_XEvalUpperLeft3_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT3_XEvalUpperLeft3_MASK) #define IRIS_MVPL_SIG0_EVALUPPERLEFT3_YEvalUpperLeft3_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALUPPERLEFT3_YEvalUpperLeft3_SHIFT (16U) /*! YEvalUpperLeft3 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT3_YEvalUpperLeft3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT3_YEvalUpperLeft3_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT3_YEvalUpperLeft3_MASK) /*! @} */ /*! @name SIG0_EVALLOWERRIGHT3 - Lower right corner of evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_XEvalLowerRight3_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_XEvalLowerRight3_SHIFT (0U) /*! XEvalLowerRight3 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_XEvalLowerRight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT3_XEvalLowerRight3_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT3_XEvalLowerRight3_MASK) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_YEvalLowerRight3_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_YEvalLowerRight3_SHIFT (16U) /*! YEvalLowerRight3 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_YEvalLowerRight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT3_YEvalLowerRight3_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT3_YEvalLowerRight3_MASK) /*! @} */ /*! @name SIG0_SIGCRCREDREF3 - Reference signature of red channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCREDREF3_SigCRCRedRef3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCREDREF3_SigCRCRedRef3_SHIFT (0U) /*! SigCRCRedRef3 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG0_SIGCRCREDREF3_SigCRCRedRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF3_SigCRCRedRef3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF3_SigCRCRedRef3_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREENREF3 - Reference signature of green channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF3_SigCRCGreenRef3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREENREF3_SigCRCGreenRef3_SHIFT (0U) /*! SigCRCGreenRef3 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF3_SigCRCGreenRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF3_SigCRCGreenRef3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF3_SigCRCGreenRef3_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUEREF3 - Reference signature of blue channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF3_SigCRCBlueRef3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUEREF3_SigCRCBlueRef3_SHIFT (0U) /*! SigCRCBlueRef3 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF3_SigCRCBlueRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF3_SigCRCBlueRef3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF3_SigCRCBlueRef3_MASK) /*! @} */ /*! @name SIG0_SIGCRCRED3 - Measured signature of red channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCRED3_SigCRCRed3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCRED3_SigCRCRed3_SHIFT (0U) /*! SigCRCRed3 - See SigCRCRed0. */ #define IRIS_MVPL_SIG0_SIGCRCRED3_SigCRCRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED3_SigCRCRed3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED3_SigCRCRed3_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREEN3 - Measured signature of green channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREEN3_SigCRCGreen3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREEN3_SigCRCGreen3_SHIFT (0U) /*! SigCRCGreen3 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG0_SIGCRCGREEN3_SigCRCGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN3_SigCRCGreen3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN3_SigCRCGreen3_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUE3 - Measured signature of blue channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUE3_SigCRCBlue3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUE3_SigCRCBlue3_SHIFT (0U) /*! SigCRCBlue3 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUE3_SigCRCBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE3_SigCRCBlue3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE3_SigCRCBlue3_MASK) /*! @} */ /*! @name SIG0_EVALCONTROL4 - Control settings for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALCONTROL4_EnEvalWin4_MASK (0x1U) #define IRIS_MVPL_SIG0_EVALCONTROL4_EnEvalWin4_SHIFT (0U) /*! EnEvalWin4 - See EnEvalWin0. */ #define IRIS_MVPL_SIG0_EVALCONTROL4_EnEvalWin4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_EnEvalWin4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_EnEvalWin4_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL4_EnCRC4_MASK (0x2U) #define IRIS_MVPL_SIG0_EVALCONTROL4_EnCRC4_SHIFT (1U) /*! EnCRC4 - See EnCRC0. */ #define IRIS_MVPL_SIG0_EVALCONTROL4_EnCRC4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_EnCRC4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_EnCRC4_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaMask4_MASK (0x100U) #define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaMask4_SHIFT (8U) /*! AlphaMask4 - See AlphaMask0. */ #define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaMask4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_AlphaMask4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_AlphaMask4_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaInv4_MASK (0x200U) #define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaInv4_SHIFT (9U) /*! AlphaInv4 - See AlphaInv0. */ #define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaInv4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_AlphaInv4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_AlphaInv4_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL4_EnLocalPanic4_MASK (0x10000U) #define IRIS_MVPL_SIG0_EVALCONTROL4_EnLocalPanic4_SHIFT (16U) /*! EnLocalPanic4 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL4_EnLocalPanic4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_EnLocalPanic4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_EnLocalPanic4_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL4_EnGlobalPanic4_MASK (0x20000U) #define IRIS_MVPL_SIG0_EVALCONTROL4_EnGlobalPanic4_SHIFT (17U) /*! EnGlobalPanic4 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL4_EnGlobalPanic4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_EnGlobalPanic4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_EnGlobalPanic4_MASK) /*! @} */ /*! @name SIG0_EVALUPPERLEFT4 - Upper left corner of evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT4_XEvalUpperLeft4_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALUPPERLEFT4_XEvalUpperLeft4_SHIFT (0U) /*! XEvalUpperLeft4 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT4_XEvalUpperLeft4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT4_XEvalUpperLeft4_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT4_XEvalUpperLeft4_MASK) #define IRIS_MVPL_SIG0_EVALUPPERLEFT4_YEvalUpperLeft4_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALUPPERLEFT4_YEvalUpperLeft4_SHIFT (16U) /*! YEvalUpperLeft4 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT4_YEvalUpperLeft4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT4_YEvalUpperLeft4_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT4_YEvalUpperLeft4_MASK) /*! @} */ /*! @name SIG0_EVALLOWERRIGHT4 - Lower right corner of evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_XEvalLowerRight4_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_XEvalLowerRight4_SHIFT (0U) /*! XEvalLowerRight4 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_XEvalLowerRight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT4_XEvalLowerRight4_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT4_XEvalLowerRight4_MASK) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_YEvalLowerRight4_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_YEvalLowerRight4_SHIFT (16U) /*! YEvalLowerRight4 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_YEvalLowerRight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT4_YEvalLowerRight4_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT4_YEvalLowerRight4_MASK) /*! @} */ /*! @name SIG0_SIGCRCREDREF4 - Reference signature of red channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCREDREF4_SigCRCRedRef4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCREDREF4_SigCRCRedRef4_SHIFT (0U) /*! SigCRCRedRef4 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG0_SIGCRCREDREF4_SigCRCRedRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF4_SigCRCRedRef4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF4_SigCRCRedRef4_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREENREF4 - Reference signature of green channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF4_SigCRCGreenRef4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREENREF4_SigCRCGreenRef4_SHIFT (0U) /*! SigCRCGreenRef4 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF4_SigCRCGreenRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF4_SigCRCGreenRef4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF4_SigCRCGreenRef4_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUEREF4 - Reference signature of blue channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF4_SigCRCBlueRef4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUEREF4_SigCRCBlueRef4_SHIFT (0U) /*! SigCRCBlueRef4 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF4_SigCRCBlueRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF4_SigCRCBlueRef4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF4_SigCRCBlueRef4_MASK) /*! @} */ /*! @name SIG0_SIGCRCRED4 - Measured signature of red channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCRED4_SigCRCRed4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCRED4_SigCRCRed4_SHIFT (0U) /*! SigCRCRed4 - See SigCRCRed0. */ #define IRIS_MVPL_SIG0_SIGCRCRED4_SigCRCRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED4_SigCRCRed4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED4_SigCRCRed4_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREEN4 - Measured signature of green channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREEN4_SigCRCGreen4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREEN4_SigCRCGreen4_SHIFT (0U) /*! SigCRCGreen4 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG0_SIGCRCGREEN4_SigCRCGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN4_SigCRCGreen4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN4_SigCRCGreen4_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUE4 - Measured signature of blue channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUE4_SigCRCBlue4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUE4_SigCRCBlue4_SHIFT (0U) /*! SigCRCBlue4 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUE4_SigCRCBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE4_SigCRCBlue4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE4_SigCRCBlue4_MASK) /*! @} */ /*! @name SIG0_EVALCONTROL5 - Control settings for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALCONTROL5_EnEvalWin5_MASK (0x1U) #define IRIS_MVPL_SIG0_EVALCONTROL5_EnEvalWin5_SHIFT (0U) /*! EnEvalWin5 - See EnEvalWin0. */ #define IRIS_MVPL_SIG0_EVALCONTROL5_EnEvalWin5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_EnEvalWin5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_EnEvalWin5_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL5_EnCRC5_MASK (0x2U) #define IRIS_MVPL_SIG0_EVALCONTROL5_EnCRC5_SHIFT (1U) /*! EnCRC5 - See EnCRC0. */ #define IRIS_MVPL_SIG0_EVALCONTROL5_EnCRC5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_EnCRC5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_EnCRC5_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaMask5_MASK (0x100U) #define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaMask5_SHIFT (8U) /*! AlphaMask5 - See AlphaMask0. */ #define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaMask5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_AlphaMask5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_AlphaMask5_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaInv5_MASK (0x200U) #define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaInv5_SHIFT (9U) /*! AlphaInv5 - See AlphaInv0. */ #define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaInv5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_AlphaInv5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_AlphaInv5_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL5_EnLocalPanic5_MASK (0x10000U) #define IRIS_MVPL_SIG0_EVALCONTROL5_EnLocalPanic5_SHIFT (16U) /*! EnLocalPanic5 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL5_EnLocalPanic5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_EnLocalPanic5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_EnLocalPanic5_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL5_EnGlobalPanic5_MASK (0x20000U) #define IRIS_MVPL_SIG0_EVALCONTROL5_EnGlobalPanic5_SHIFT (17U) /*! EnGlobalPanic5 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL5_EnGlobalPanic5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_EnGlobalPanic5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_EnGlobalPanic5_MASK) /*! @} */ /*! @name SIG0_EVALUPPERLEFT5 - Upper left corner of evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT5_XEvalUpperLeft5_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALUPPERLEFT5_XEvalUpperLeft5_SHIFT (0U) /*! XEvalUpperLeft5 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT5_XEvalUpperLeft5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT5_XEvalUpperLeft5_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT5_XEvalUpperLeft5_MASK) #define IRIS_MVPL_SIG0_EVALUPPERLEFT5_YEvalUpperLeft5_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALUPPERLEFT5_YEvalUpperLeft5_SHIFT (16U) /*! YEvalUpperLeft5 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT5_YEvalUpperLeft5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT5_YEvalUpperLeft5_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT5_YEvalUpperLeft5_MASK) /*! @} */ /*! @name SIG0_EVALLOWERRIGHT5 - Lower right corner of evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_XEvalLowerRight5_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_XEvalLowerRight5_SHIFT (0U) /*! XEvalLowerRight5 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_XEvalLowerRight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT5_XEvalLowerRight5_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT5_XEvalLowerRight5_MASK) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_YEvalLowerRight5_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_YEvalLowerRight5_SHIFT (16U) /*! YEvalLowerRight5 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_YEvalLowerRight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT5_YEvalLowerRight5_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT5_YEvalLowerRight5_MASK) /*! @} */ /*! @name SIG0_SIGCRCREDREF5 - Reference signature of red channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCREDREF5_SigCRCRedRef5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCREDREF5_SigCRCRedRef5_SHIFT (0U) /*! SigCRCRedRef5 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG0_SIGCRCREDREF5_SigCRCRedRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF5_SigCRCRedRef5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF5_SigCRCRedRef5_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREENREF5 - Reference signature of green channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF5_SigCRCGreenRef5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREENREF5_SigCRCGreenRef5_SHIFT (0U) /*! SigCRCGreenRef5 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF5_SigCRCGreenRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF5_SigCRCGreenRef5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF5_SigCRCGreenRef5_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUEREF5 - Reference signature of blue channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF5_SigCRCBlueRef5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUEREF5_SigCRCBlueRef5_SHIFT (0U) /*! SigCRCBlueRef5 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF5_SigCRCBlueRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF5_SigCRCBlueRef5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF5_SigCRCBlueRef5_MASK) /*! @} */ /*! @name SIG0_SIGCRCRED5 - Measured signature of red channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCRED5_SigCRCRed5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCRED5_SigCRCRed5_SHIFT (0U) /*! SigCRCRed5 - See SigCRCRed0. */ #define IRIS_MVPL_SIG0_SIGCRCRED5_SigCRCRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED5_SigCRCRed5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED5_SigCRCRed5_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREEN5 - Measured signature of green channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREEN5_SigCRCGreen5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREEN5_SigCRCGreen5_SHIFT (0U) /*! SigCRCGreen5 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG0_SIGCRCGREEN5_SigCRCGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN5_SigCRCGreen5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN5_SigCRCGreen5_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUE5 - Measured signature of blue channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUE5_SigCRCBlue5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUE5_SigCRCBlue5_SHIFT (0U) /*! SigCRCBlue5 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUE5_SigCRCBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE5_SigCRCBlue5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE5_SigCRCBlue5_MASK) /*! @} */ /*! @name SIG0_EVALCONTROL6 - Control settings for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALCONTROL6_EnEvalWin6_MASK (0x1U) #define IRIS_MVPL_SIG0_EVALCONTROL6_EnEvalWin6_SHIFT (0U) /*! EnEvalWin6 - See EnEvalWin0. */ #define IRIS_MVPL_SIG0_EVALCONTROL6_EnEvalWin6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_EnEvalWin6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_EnEvalWin6_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL6_EnCRC6_MASK (0x2U) #define IRIS_MVPL_SIG0_EVALCONTROL6_EnCRC6_SHIFT (1U) /*! EnCRC6 - See EnCRC0. */ #define IRIS_MVPL_SIG0_EVALCONTROL6_EnCRC6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_EnCRC6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_EnCRC6_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaMask6_MASK (0x100U) #define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaMask6_SHIFT (8U) /*! AlphaMask6 - See AlphaMask0. */ #define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaMask6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_AlphaMask6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_AlphaMask6_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaInv6_MASK (0x200U) #define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaInv6_SHIFT (9U) /*! AlphaInv6 - See AlphaInv0. */ #define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaInv6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_AlphaInv6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_AlphaInv6_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL6_EnLocalPanic6_MASK (0x10000U) #define IRIS_MVPL_SIG0_EVALCONTROL6_EnLocalPanic6_SHIFT (16U) /*! EnLocalPanic6 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL6_EnLocalPanic6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_EnLocalPanic6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_EnLocalPanic6_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL6_EnGlobalPanic6_MASK (0x20000U) #define IRIS_MVPL_SIG0_EVALCONTROL6_EnGlobalPanic6_SHIFT (17U) /*! EnGlobalPanic6 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL6_EnGlobalPanic6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_EnGlobalPanic6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_EnGlobalPanic6_MASK) /*! @} */ /*! @name SIG0_EVALUPPERLEFT6 - Upper left corner of evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT6_XEvalUpperLeft6_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALUPPERLEFT6_XEvalUpperLeft6_SHIFT (0U) /*! XEvalUpperLeft6 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT6_XEvalUpperLeft6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT6_XEvalUpperLeft6_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT6_XEvalUpperLeft6_MASK) #define IRIS_MVPL_SIG0_EVALUPPERLEFT6_YEvalUpperLeft6_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALUPPERLEFT6_YEvalUpperLeft6_SHIFT (16U) /*! YEvalUpperLeft6 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT6_YEvalUpperLeft6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT6_YEvalUpperLeft6_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT6_YEvalUpperLeft6_MASK) /*! @} */ /*! @name SIG0_EVALLOWERRIGHT6 - Lower right corner of evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_XEvalLowerRight6_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_XEvalLowerRight6_SHIFT (0U) /*! XEvalLowerRight6 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_XEvalLowerRight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT6_XEvalLowerRight6_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT6_XEvalLowerRight6_MASK) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_YEvalLowerRight6_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_YEvalLowerRight6_SHIFT (16U) /*! YEvalLowerRight6 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_YEvalLowerRight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT6_YEvalLowerRight6_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT6_YEvalLowerRight6_MASK) /*! @} */ /*! @name SIG0_SIGCRCREDREF6 - Reference signature of red channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCREDREF6_SigCRCRedRef6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCREDREF6_SigCRCRedRef6_SHIFT (0U) /*! SigCRCRedRef6 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG0_SIGCRCREDREF6_SigCRCRedRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF6_SigCRCRedRef6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF6_SigCRCRedRef6_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREENREF6 - Reference signature of green channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF6_SigCRCGreenRef6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREENREF6_SigCRCGreenRef6_SHIFT (0U) /*! SigCRCGreenRef6 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF6_SigCRCGreenRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF6_SigCRCGreenRef6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF6_SigCRCGreenRef6_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUEREF6 - Reference signature of blue channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF6_SigCRCBlueRef6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUEREF6_SigCRCBlueRef6_SHIFT (0U) /*! SigCRCBlueRef6 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF6_SigCRCBlueRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF6_SigCRCBlueRef6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF6_SigCRCBlueRef6_MASK) /*! @} */ /*! @name SIG0_SIGCRCRED6 - Measured signature of red channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCRED6_SigCRCRed6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCRED6_SigCRCRed6_SHIFT (0U) /*! SigCRCRed6 - See SigCRCRed0. */ #define IRIS_MVPL_SIG0_SIGCRCRED6_SigCRCRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED6_SigCRCRed6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED6_SigCRCRed6_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREEN6 - Measured signature of green channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREEN6_SigCRCGreen6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREEN6_SigCRCGreen6_SHIFT (0U) /*! SigCRCGreen6 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG0_SIGCRCGREEN6_SigCRCGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN6_SigCRCGreen6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN6_SigCRCGreen6_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUE6 - Measured signature of blue channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUE6_SigCRCBlue6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUE6_SigCRCBlue6_SHIFT (0U) /*! SigCRCBlue6 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUE6_SigCRCBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE6_SigCRCBlue6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE6_SigCRCBlue6_MASK) /*! @} */ /*! @name SIG0_EVALCONTROL7 - Control settings for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALCONTROL7_EnEvalWin7_MASK (0x1U) #define IRIS_MVPL_SIG0_EVALCONTROL7_EnEvalWin7_SHIFT (0U) /*! EnEvalWin7 - See EnEvalWin0. */ #define IRIS_MVPL_SIG0_EVALCONTROL7_EnEvalWin7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_EnEvalWin7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_EnEvalWin7_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL7_EnCRC7_MASK (0x2U) #define IRIS_MVPL_SIG0_EVALCONTROL7_EnCRC7_SHIFT (1U) /*! EnCRC7 - See EnCRC0. */ #define IRIS_MVPL_SIG0_EVALCONTROL7_EnCRC7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_EnCRC7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_EnCRC7_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaMask7_MASK (0x100U) #define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaMask7_SHIFT (8U) /*! AlphaMask7 - See AlphaMask0. */ #define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaMask7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_AlphaMask7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_AlphaMask7_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaInv7_MASK (0x200U) #define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaInv7_SHIFT (9U) /*! AlphaInv7 - See AlphaInv0. */ #define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaInv7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_AlphaInv7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_AlphaInv7_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL7_EnLocalPanic7_MASK (0x10000U) #define IRIS_MVPL_SIG0_EVALCONTROL7_EnLocalPanic7_SHIFT (16U) /*! EnLocalPanic7 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL7_EnLocalPanic7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_EnLocalPanic7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_EnLocalPanic7_MASK) #define IRIS_MVPL_SIG0_EVALCONTROL7_EnGlobalPanic7_MASK (0x20000U) #define IRIS_MVPL_SIG0_EVALCONTROL7_EnGlobalPanic7_SHIFT (17U) /*! EnGlobalPanic7 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG0_EVALCONTROL7_EnGlobalPanic7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_EnGlobalPanic7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_EnGlobalPanic7_MASK) /*! @} */ /*! @name SIG0_EVALUPPERLEFT7 - Upper left corner of evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT7_XEvalUpperLeft7_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALUPPERLEFT7_XEvalUpperLeft7_SHIFT (0U) /*! XEvalUpperLeft7 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT7_XEvalUpperLeft7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT7_XEvalUpperLeft7_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT7_XEvalUpperLeft7_MASK) #define IRIS_MVPL_SIG0_EVALUPPERLEFT7_YEvalUpperLeft7_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALUPPERLEFT7_YEvalUpperLeft7_SHIFT (16U) /*! YEvalUpperLeft7 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG0_EVALUPPERLEFT7_YEvalUpperLeft7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT7_YEvalUpperLeft7_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT7_YEvalUpperLeft7_MASK) /*! @} */ /*! @name SIG0_EVALLOWERRIGHT7 - Lower right corner of evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_XEvalLowerRight7_MASK (0x3FFFU) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_XEvalLowerRight7_SHIFT (0U) /*! XEvalLowerRight7 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_XEvalLowerRight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT7_XEvalLowerRight7_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT7_XEvalLowerRight7_MASK) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_YEvalLowerRight7_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_YEvalLowerRight7_SHIFT (16U) /*! YEvalLowerRight7 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_YEvalLowerRight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT7_YEvalLowerRight7_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT7_YEvalLowerRight7_MASK) /*! @} */ /*! @name SIG0_SIGCRCREDREF7 - Reference signature of red channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCREDREF7_SigCRCRedRef7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCREDREF7_SigCRCRedRef7_SHIFT (0U) /*! SigCRCRedRef7 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG0_SIGCRCREDREF7_SigCRCRedRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF7_SigCRCRedRef7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF7_SigCRCRedRef7_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREENREF7 - Reference signature of green channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF7_SigCRCGreenRef7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREENREF7_SigCRCGreenRef7_SHIFT (0U) /*! SigCRCGreenRef7 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG0_SIGCRCGREENREF7_SigCRCGreenRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF7_SigCRCGreenRef7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF7_SigCRCGreenRef7_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUEREF7 - Reference signature of blue channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF7_SigCRCBlueRef7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUEREF7_SigCRCBlueRef7_SHIFT (0U) /*! SigCRCBlueRef7 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUEREF7_SigCRCBlueRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF7_SigCRCBlueRef7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF7_SigCRCBlueRef7_MASK) /*! @} */ /*! @name SIG0_SIGCRCRED7 - Measured signature of red channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCRED7_SigCRCRed7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCRED7_SigCRCRed7_SHIFT (0U) /*! SigCRCRed7 - See SigCRCRed0. */ #define IRIS_MVPL_SIG0_SIGCRCRED7_SigCRCRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED7_SigCRCRed7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED7_SigCRCRed7_MASK) /*! @} */ /*! @name SIG0_SIGCRCGREEN7 - Measured signature of green channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCGREEN7_SigCRCGreen7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCGREEN7_SigCRCGreen7_SHIFT (0U) /*! SigCRCGreen7 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG0_SIGCRCGREEN7_SigCRCGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN7_SigCRCGreen7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN7_SigCRCGreen7_MASK) /*! @} */ /*! @name SIG0_SIGCRCBLUE7 - Measured signature of blue channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG0_SIGCRCBLUE7_SigCRCBlue7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG0_SIGCRCBLUE7_SigCRCBlue7_SHIFT (0U) /*! SigCRCBlue7 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG0_SIGCRCBLUE7_SigCRCBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE7_SigCRCBlue7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE7_SigCRCBlue7_MASK) /*! @} */ /*! @name SIG0_SHADOWLOAD - Shadow load control register. */ /*! @{ */ #define IRIS_MVPL_SIG0_SHADOWLOAD_ShdLdReq_MASK (0xFFU) #define IRIS_MVPL_SIG0_SHADOWLOAD_ShdLdReq_SHIFT (0U) /*! ShdLdReq - Shadow load request for each evaluation window (bit index = window index). */ #define IRIS_MVPL_SIG0_SHADOWLOAD_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SHADOWLOAD_ShdLdReq_SHIFT)) & IRIS_MVPL_SIG0_SHADOWLOAD_ShdLdReq_MASK) /*! @} */ /*! @name SIG0_CONTINUOUSMODE - Signature operation mode control. */ /*! @{ */ #define IRIS_MVPL_SIG0_CONTINUOUSMODE_EnCont_MASK (0x1U) #define IRIS_MVPL_SIG0_CONTINUOUSMODE_EnCont_SHIFT (0U) /*! EnCont - EnCont = 0: disables continuous mode. */ #define IRIS_MVPL_SIG0_CONTINUOUSMODE_EnCont(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_CONTINUOUSMODE_EnCont_SHIFT)) & IRIS_MVPL_SIG0_CONTINUOUSMODE_EnCont_MASK) /*! @} */ /*! @name SIG0_SOFTWAREKICK - Signature measurement trigger. */ /*! @{ */ #define IRIS_MVPL_SIG0_SOFTWAREKICK_Kick_MASK (0x1U) #define IRIS_MVPL_SIG0_SOFTWAREKICK_Kick_SHIFT (0U) /*! Kick - ContinueMode.EnCont=0: Write '1' to this field in order to start signature computation with next frame. */ #define IRIS_MVPL_SIG0_SOFTWAREKICK_Kick(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SOFTWAREKICK_Kick_SHIFT)) & IRIS_MVPL_SIG0_SOFTWAREKICK_Kick_MASK) /*! @} */ /*! @name SIG0_STATUS - Module status. */ /*! @{ */ #define IRIS_MVPL_SIG0_STATUS_StsSigError_MASK (0xFFU) #define IRIS_MVPL_SIG0_STATUS_StsSigError_SHIFT (0U) /*! StsSigError - Error status bits for all evaluation windows (bit index = window index). */ #define IRIS_MVPL_SIG0_STATUS_StsSigError(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATUS_StsSigError_SHIFT)) & IRIS_MVPL_SIG0_STATUS_StsSigError_MASK) #define IRIS_MVPL_SIG0_STATUS_StsSigValid_MASK (0x10000U) #define IRIS_MVPL_SIG0_STATUS_StsSigValid_SHIFT (16U) /*! StsSigValid - Measured signature values are valid. */ #define IRIS_MVPL_SIG0_STATUS_StsSigValid(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATUS_StsSigValid_SHIFT)) & IRIS_MVPL_SIG0_STATUS_StsSigValid_MASK) #define IRIS_MVPL_SIG0_STATUS_StsSigIdle_MASK (0x100000U) #define IRIS_MVPL_SIG0_STATUS_StsSigIdle_SHIFT (20U) /*! StsSigIdle - StsSigIdle = 1: Signature is in Idle state. */ #define IRIS_MVPL_SIG0_STATUS_StsSigIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATUS_StsSigIdle_SHIFT)) & IRIS_MVPL_SIG0_STATUS_StsSigIdle_MASK) /*! @} */ /*! @name FRAMEGEN1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_FRAMEGEN1_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_FRAMEGEN1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FRAMEGEN1_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name FRAMEGEN1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSTCTRL - FrameGen Static Control Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_ShdEn_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing for RWS type configuration fields. */ #define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSTCTRL_ShdEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSTCTRL_ShdEn_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_FgSyncMode_MASK (0x6U) #define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_FgSyncMode_SHIFT (1U) /*! FgSyncMode - Determines the operating mode of the framegen unit for side-by-side synchronization. * 0b00..No side-by-side synchronization. * 0b01..Framegen is master. * 0b10..Framegen is slave. Runs in cyclic synchronization mode. * 0b11..Framegen is slave. Runs in one time synchronization mode. */ #define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_FgSyncMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSTCTRL_FgSyncMode_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSTCTRL_FgSyncMode_MASK) /*! @} */ /*! @name FRAMEGEN1_HTCFG1 - FrameGen Horizontal Timing Config Register 1 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_HTCFG1_Hact_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_HTCFG1_Hact_SHIFT (0U) /*! Hact - Horizontal size of active display area in pixels. */ #define IRIS_MVPL_FRAMEGEN1_HTCFG1_Hact(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_HTCFG1_Hact_SHIFT)) & IRIS_MVPL_FRAMEGEN1_HTCFG1_Hact_MASK) #define IRIS_MVPL_FRAMEGEN1_HTCFG1_Htotal_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_HTCFG1_Htotal_SHIFT (16U) /*! Htotal - Total horizontal size of frame in pixels. */ #define IRIS_MVPL_FRAMEGEN1_HTCFG1_Htotal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_HTCFG1_Htotal_SHIFT)) & IRIS_MVPL_FRAMEGEN1_HTCFG1_Htotal_MASK) /*! @} */ /*! @name FRAMEGEN1_HTCFG2 - FrameGen Horizontal Timing Config Register 2 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsync_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsync_SHIFT (0U) /*! Hsync - Width of HSYNC pulse in pixels. */ #define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsync_SHIFT)) & IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsync_MASK) #define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsbp_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsbp_SHIFT (16U) /*! Hsbp - Width of HSYNC pulse plus width of horizontal back porch in pixels. */ #define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsbp(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsbp_SHIFT)) & IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsbp_MASK) #define IRIS_MVPL_FRAMEGEN1_HTCFG2_HsEn_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN1_HTCFG2_HsEn_SHIFT (31U) /*! HsEn - Enables generation of HSYNC pulse. */ #define IRIS_MVPL_FRAMEGEN1_HTCFG2_HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_HTCFG2_HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_HTCFG2_HsEn_MASK) /*! @} */ /*! @name FRAMEGEN1_VTCFG1 - FrameGen Vertical Timing Config Register 1 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vact_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vact_SHIFT (0U) /*! Vact - Vertical size of active display area in lines. */ #define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vact(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_VTCFG1_Vact_SHIFT)) & IRIS_MVPL_FRAMEGEN1_VTCFG1_Vact_MASK) #define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vtotal_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vtotal_SHIFT (16U) /*! Vtotal - Total vertical size of frame in lines. */ #define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vtotal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_VTCFG1_Vtotal_SHIFT)) & IRIS_MVPL_FRAMEGEN1_VTCFG1_Vtotal_MASK) /*! @} */ /*! @name FRAMEGEN1_VTCFG2 - FrameGen Vertical Timing Config Register 2 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsync_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsync_SHIFT (0U) /*! Vsync - Width of VSYNC pulse in lines. */ #define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsync_SHIFT)) & IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsync_MASK) #define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsbp_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsbp_SHIFT (16U) /*! Vsbp - Width of VSYNC pulse plus width of vertical back porch in lines. */ #define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsbp(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsbp_SHIFT)) & IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsbp_MASK) #define IRIS_MVPL_FRAMEGEN1_VTCFG2_VsEn_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN1_VTCFG2_VsEn_SHIFT (31U) /*! VsEn - Enables generation of VSYNC pulse. */ #define IRIS_MVPL_FRAMEGEN1_VTCFG2_VsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_VTCFG2_VsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_VTCFG2_VsEn_MASK) /*! @} */ /*! @name FRAMEGEN1_INT0CONFIG - Coordinates of the trigger point for generation of the Int0 interrupt signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Col_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Col_SHIFT (0U) /*! Int0Col - Specifies on which column of the display raster the Int0 signal is triggered (1 .. Int0Col .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Col_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Col_MASK) #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0HsEn_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0HsEn_SHIFT (15U) /*! Int0HsEn - When enabled, Int0Row setting is ignored so that the interrupt occurs every line at position given by Int0Col. */ #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0HsEn_MASK) #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Row_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Row_SHIFT (16U) /*! Int0Row - Specifies on which row of the display raster the Int0 signal is triggered (1 .. Int0Row .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Row_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Row_MASK) #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0En_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0En_SHIFT (31U) /*! Int0En - Enables Int0. */ #define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0En_MASK) /*! @} */ /*! @name FRAMEGEN1_INT1CONFIG - Coordinates of the trigger point for generation of the Int1 interrupt signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Col_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Col_SHIFT (0U) /*! Int1Col - Specifies on which column of the display raster the Int1 signal is triggered (1 .. Int1Col .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Col_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Col_MASK) #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1HsEn_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1HsEn_SHIFT (15U) /*! Int1HsEn - When enabled, Int1Row setting is ignored so that the interrupt occurs every line at position given by Int1Col. */ #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1HsEn_MASK) #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Row_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Row_SHIFT (16U) /*! Int1Row - Specifies on which row of the display raster the Int1 signal is triggered (1 .. Int1Row .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Row_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Row_MASK) #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1En_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1En_SHIFT (31U) /*! Int1En - Enables Int1 (irq[1]). */ #define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1En_MASK) /*! @} */ /*! @name FRAMEGEN1_INT2CONFIG - Coordinates of the trigger point for generation of the Int2 interrupt signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Col_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Col_SHIFT (0U) /*! Int2Col - Specifies on which column of the display raster the Int2 signal is triggered (1 .. Int2Col .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Col_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Col_MASK) #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2HsEn_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2HsEn_SHIFT (15U) /*! Int2HsEn - When enabled, Int2Row setting is ignored so that the interrupt occurs every line at position given by Int2Col. */ #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2HsEn_MASK) #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Row_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Row_SHIFT (16U) /*! Int2Row - Specifies on which row of the display raster the Int2 signal is triggered (1 .. Int2Row .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Row_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Row_MASK) #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2En_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2En_SHIFT (31U) /*! Int2En - Enables Int2. */ #define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2En_MASK) /*! @} */ /*! @name FRAMEGEN1_INT3CONFIG - Coordinates of the trigger point for generation of the Int3 interrupt signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Col_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Col_SHIFT (0U) /*! Int3Col - Specifies on which column of the display raster the Int3 signal is triggered (1 .. Int3Col .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Col_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Col_MASK) #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3HsEn_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3HsEn_SHIFT (15U) /*! Int3HsEn - When enabled, Int3Row setting is ignored so that the interrupt occurs every line at position given by Int3Col. */ #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3HsEn_MASK) #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Row_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Row_SHIFT (16U) /*! Int3Row - Specifies on which row of the display raster the Int3 signal is triggered (1 .. Int3Row .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Row_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Row_MASK) #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3En_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3En_SHIFT (31U) /*! Int3En - Enables Int3. */ #define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3En_MASK) /*! @} */ /*! @name FRAMEGEN1_PKICKCONFIG - Coordinates of the trigger point for generation of the primary kick signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickCol_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickCol_SHIFT (0U) /*! PKickCol - Specifies on which column of the display raster the pkick signal is triggered (1 .. PKickCol .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickCol(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickCol_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickCol_MASK) #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickInt0En_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickInt0En_SHIFT (15U) /*! PKickInt0En - If enabled, maps the primary kick signal (pkick) on the interrupt pin int0. Overrides int0en. */ #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickInt0En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickInt0En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickInt0En_MASK) #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickRow_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickRow_SHIFT (16U) /*! PKickRow - Specifies on which row of the display raster the pkick signal is triggered (1 .. PKickRow .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickRow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickRow_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickRow_MASK) #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickEn_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickEn_SHIFT (31U) /*! PKickEn - Enables pkick signal. */ #define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickEn_MASK) /*! @} */ /*! @name FRAMEGEN1_SKICKCONFIG - Coordinates of the trigger point for generation of the secondary kick signal */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickCol_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickCol_SHIFT (0U) /*! SKickCol - Specifies on which column of the display raster the skick signal is triggered (1 .. SKickCol .. HTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickCol(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickCol_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickCol_MASK) #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickInt1En_MASK (0x8000U) #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickInt1En_SHIFT (15U) /*! SKickInt1En - If enabled, maps the secondary kick signal (skick) on the interrupt pin int1. Overrides int1en. */ #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickInt1En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickInt1En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickInt1En_MASK) #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickRow_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickRow_SHIFT (16U) /*! SKickRow - Specifies on which row of the display raster the skick signal is triggered (1 .. SKickRow .. VTOTAL). */ #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickRow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickRow_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickRow_MASK) #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickTrig_MASK (0x40000000U) #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickTrig_SHIFT (30U) /*! SKickTrig - Select source for skick generation. * 0b0..Use internal skick signal, trigger point defined by SKickRow and SKickCol. * 0b1..Use external skick input as trigger. */ #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickTrig(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickTrig_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickTrig_MASK) #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickEn_MASK (0x80000000U) #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickEn_SHIFT (31U) /*! SKickEn - Enables generation of internal skick signal. */ #define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickEn_MASK) /*! @} */ /*! @name FRAMEGEN1_SECSTATCONFIG - Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register. */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevGoodFrames_MASK (0xFU) #define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevGoodFrames_SHIFT (0U) /*! LevGoodFrames - Number of continous correct frames that must be processed before SecSyncStat field goes 1 (in sync). */ #define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevGoodFrames(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevGoodFrames_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevGoodFrames_MASK) #define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevBadFrames_MASK (0xF0U) #define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevBadFrames_SHIFT (4U) /*! LevBadFrames - Not used. */ #define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevBadFrames(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevBadFrames_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevBadFrames_MASK) #define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevSkewInRange_MASK (0xF00U) #define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevSkewInRange_SHIFT (8U) /*! LevSkewInRange - Number of continous frames the measured skew value shall be within the range defined by SyncRangeLow and SyncRangeHigh. */ #define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevSkewInRange(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevSkewInRange_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevSkewInRange_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSRCR1 - FrameGen Skew Regulation Control Register 1. */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREn_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREn_SHIFT (0U) /*! SREn - If enabled, skew control for secondary channel is active. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREn_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRMode_MASK (0x6U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRMode_SHIFT (1U) /*! SRMode - Skew Control Operating Mode. * 0b00..Skew Regulation is off. * 0b01..Horizontal regulation enabled. * 0b10..Vertical regulation enabled. * 0b11..Both regulation modes are enabled. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRMode_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRMode_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRAdj_MASK (0x8U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRAdj_SHIFT (3U) /*! SRAdj - Enables line length adjustment for HTOTAL. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRAdj(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRAdj_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRAdj_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREven_MASK (0x10U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREven_SHIFT (4U) /*! SREven - Total line length HTOTAL is even when SRAdj is enabled. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREven(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREven_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREven_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRFastSync_MASK (0x20U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRFastSync_SHIFT (5U) /*! SRFastSync - Fast Synchronization Mode. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRFastSync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRFastSync_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRFastSync_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQAlign_MASK (0x40U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQAlign_SHIFT (6U) /*! SRQAlign - Enables alignment of HTOTAL to be a multiple of 4. Overrides SREven field. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQAlign(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQAlign_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQAlign_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQVal_MASK (0x180U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQVal_SHIFT (7U) /*! SRQVal - If SRQAlign is enabled, this field determines the fixed value of the two LSB bits of HTOTAL. * 0b00..Fixed two LSB values of HTOTAL are 0b00. * 0b01..Fixed two LSB values of HTOTAL are 0b01. * 0b10..Fixed two LSB values of HTOTAL are 0b10. * 0b11..Fixed two LSB values of HTOTAL are 0b11. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQVal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQVal_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQVal_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRDbgDisp_MASK (0x10000U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRDbgDisp_SHIFT (16U) /*! SRDbgDisp - If enabled, the pixels are displayed that are read from FIFO when secondary channel is not in sync yet. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRDbgDisp(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRDbgDisp_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRDbgDisp_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_MASK (0x20000U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) /*! SREpOff - Disables the skew Extrapolation in blanking. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSRCR2 - FrameGen Skew Regulation Control Register 2 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMin_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMin_SHIFT (0U) /*! HTotalMin - Minimum value of htotal when horizontal regulation is enabled. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMin_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMin_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMax_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMax_SHIFT (16U) /*! HTotalMax - Maximum value of htotal when horizontal regulation is enabled. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMax_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMax_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSRCR3 - FrameGen Skew Regulation Control Register 3 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMin_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMin_SHIFT (0U) /*! VTotalMin - Minimum value of vtotal when vertical regulation is enabled. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMin_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMin_MASK) #define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMax_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMax_SHIFT (16U) /*! VTotalMax - Maximum value of vtotal when vertical regulation is enabled. */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMax_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMax_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSRCR4 - FrameGen Skew Regulation Control Register 4 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR4_TargetSkew_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FRAMEGEN1_FGSRCR4_TargetSkew_SHIFT (0U) /*! TargetSkew - Horizontal target skew value for horizontal and vertical skew regulation (signed value). */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR4_TargetSkew(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR4_TargetSkew_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR4_TargetSkew_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSRCR5 - FrameGen Skew Regulation Control Register 5 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR5_SyncRangeLow_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FRAMEGEN1_FGSRCR5_SyncRangeLow_SHIFT (0U) /*! SyncRangeLow - Sync range of horizontal and vertical skew regulation. Lower value (signed value). */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR5_SyncRangeLow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR5_SyncRangeLow_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR5_SyncRangeLow_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSRCR6 - FrameGen Skew Regulation Control Register 6 */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR6_SyncRangeHigh_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FRAMEGEN1_FGSRCR6_SyncRangeHigh_SHIFT (0U) /*! SyncRangeHigh - Sync range of horizontal and vertical skew regulation. Upper value (signed value). */ #define IRIS_MVPL_FRAMEGEN1_FGSRCR6_SyncRangeHigh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR6_SyncRangeHigh_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR6_SyncRangeHigh_MASK) /*! @} */ /*! @name FRAMEGEN1_FGKSDR - FrameGen Kick System Debug Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGKSDR_PCntCplMax_MASK (0x7U) #define IRIS_MVPL_FRAMEGEN1_FGKSDR_PCntCplMax_SHIFT (0U) /*! PCntCplMax - Maximum Value for ppendcnt_cpl_s complementary primary kick counter. Do not change! */ #define IRIS_MVPL_FRAMEGEN1_FGKSDR_PCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGKSDR_PCntCplMax_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGKSDR_PCntCplMax_MASK) #define IRIS_MVPL_FRAMEGEN1_FGKSDR_SCntCplMax_MASK (0x70000U) #define IRIS_MVPL_FRAMEGEN1_FGKSDR_SCntCplMax_SHIFT (16U) /*! SCntCplMax - Maximum Value for spendcnt_cpl_s complementary secondary kick counter. Do not change! */ #define IRIS_MVPL_FRAMEGEN1_FGKSDR_SCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGKSDR_SCntCplMax_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGKSDR_SCntCplMax_MASK) /*! @} */ /*! @name FRAMEGEN1_PACFG - FrameGen Primary Area Config Register 1 (shadowed) */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_PACFG_Pstartx_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_PACFG_Pstartx_SHIFT (0U) /*! Pstartx - Primary screen upper left corner, x component. Counts from 1. Pstartx = 0 is not allowed. */ #define IRIS_MVPL_FRAMEGEN1_PACFG_Pstartx(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PACFG_Pstartx_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PACFG_Pstartx_MASK) #define IRIS_MVPL_FRAMEGEN1_PACFG_Pstarty_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_PACFG_Pstarty_SHIFT (16U) /*! Pstarty - Primary screen upper left corner, y component. Counts from 1. Pstarty = 0 is not allowed. */ #define IRIS_MVPL_FRAMEGEN1_PACFG_Pstarty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PACFG_Pstarty_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PACFG_Pstarty_MASK) /*! @} */ /*! @name FRAMEGEN1_SACFG - FrameGen Secondary Area Config Register 1 (shadowed) */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_SACFG_Sstartx_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_SACFG_Sstartx_SHIFT (0U) /*! Sstartx - Secondary screen upper left corner, x component. Counts from 1 . Sstartx = 0 is not allowed. */ #define IRIS_MVPL_FRAMEGEN1_SACFG_Sstartx(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SACFG_Sstartx_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SACFG_Sstartx_MASK) #define IRIS_MVPL_FRAMEGEN1_SACFG_Sstarty_MASK (0x3FFF0000U) #define IRIS_MVPL_FRAMEGEN1_SACFG_Sstarty_SHIFT (16U) /*! Sstarty - Secondary screen upper left corner, y component. Counts from 1 . Sstarty = 0 is not allowed. */ #define IRIS_MVPL_FRAMEGEN1_SACFG_Sstarty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SACFG_Sstarty_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SACFG_Sstarty_MASK) /*! @} */ /*! @name FRAMEGEN1_FGINCTRL - FrameGen Input Control Register (shadowed) */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGINCTRL_FgDm_MASK (0x7U) #define IRIS_MVPL_FRAMEGEN1_FGINCTRL_FgDm_SHIFT (0U) /*! FgDm - Frame Generator Display Mode. * 0b000..Black Color Background is shown. * 0b001..Constant Color Background is shown. * 0b010..Primary input only is shown. * 0b011..Secondary input only is shown. * 0b100..Both inputs overlaid with primary on top. * 0b101..Both inputs overlaid with secondary on top. * 0b110..White color background with test pattern is shown. */ #define IRIS_MVPL_FRAMEGEN1_FGINCTRL_FgDm(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRL_FgDm_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRL_FgDm_MASK) #define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnPrimAlpha_MASK (0x8U) #define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnPrimAlpha_SHIFT (3U) /*! EnPrimAlpha - When enabled, alpha plane of primary channel is considered for screen composition. */ #define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnPrimAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnPrimAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnPrimAlpha_MASK) #define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnSecAlpha_MASK (0x10U) #define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnSecAlpha_SHIFT (4U) /*! EnSecAlpha - When enabled, alpha plane of secondary channel is considered for screen composition. */ #define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnSecAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnSecAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnSecAlpha_MASK) /*! @} */ /*! @name FRAMEGEN1_FGINCTRLPANIC - FrameGen Input Control Panic Register (shadowed) */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_FgDmPanic_MASK (0x7U) #define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_FgDmPanic_SHIFT (0U) /*! FgDmPanic - Frame Generator Display Mode when Panic Switch active. * 0b000..Black Color Background is shown. * 0b001..Constant Color Background is shown. * 0b010..Primary input only is shown. * 0b011..Secondary input only is shown. * 0b100..Both inputs overlaid with primary on top. * 0b101..Both inputs overlaid with secondary on top. * 0b110..White color background with test pattern is shown. */ #define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_FgDmPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_FgDmPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_FgDmPanic_MASK) #define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnPrimAlphaPanic_MASK (0x8U) #define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnPrimAlphaPanic_SHIFT (3U) /*! EnPrimAlphaPanic - When enabled, alpha plane of primary channel is considered for screen composition. */ #define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnPrimAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnPrimAlphaPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnPrimAlphaPanic_MASK) #define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnSecAlphaPanic_MASK (0x10U) #define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnSecAlphaPanic_SHIFT (4U) /*! EnSecAlphaPanic - When enabled, alpha plane of secondary channel is considered for screen composition. */ #define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnSecAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnSecAlphaPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnSecAlphaPanic_MASK) /*! @} */ /*! @name FRAMEGEN1_FGCCR - FrameGen Constant Color Register (shadowed) */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcBlue_MASK (0x3FFU) #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcBlue_SHIFT (0U) /*! CcBlue - Constant color - blue component. */ #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCCR_CcBlue_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCCR_CcBlue_MASK) #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcGreen_MASK (0xFFC00U) #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcGreen_SHIFT (10U) /*! CcGreen - Constant color - green component. */ #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCCR_CcGreen_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCCR_CcGreen_MASK) #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcRed_MASK (0x3FF00000U) #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcRed_SHIFT (20U) /*! CcRed - Constant color - red component. */ #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCCR_CcRed_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCCR_CcRed_MASK) #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcAlpha_MASK (0x40000000U) #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcAlpha_SHIFT (30U) /*! CcAlpha - Constant color - alpha value. */ #define IRIS_MVPL_FRAMEGEN1_FGCCR_CcAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCCR_CcAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCCR_CcAlpha_MASK) /*! @} */ /*! @name FRAMEGEN1_FGENABLE - FrameGen Enable Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGENABLE_FgEn_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN1_FGENABLE_FgEn_SHIFT (0U) /*! FgEn - Frame Generator Enable. */ #define IRIS_MVPL_FRAMEGEN1_FGENABLE_FgEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGENABLE_FgEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGENABLE_FgEn_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSLR - FrameGen Shadow Load Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSLR_ShdTokGen_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN1_FGSLR_ShdTokGen_SHIFT (0U) /*! ShdTokGen - Generate shadow load token. */ #define IRIS_MVPL_FRAMEGEN1_FGSLR_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSLR_ShdTokGen_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSLR_ShdTokGen_MASK) /*! @} */ /*! @name FRAMEGEN1_FGENSTS - FrameGen Enable Status Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGENSTS_EnSts_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN1_FGENSTS_EnSts_SHIFT (0U) /*! EnSts - Indicates the current operating mode of the frame generator. */ #define IRIS_MVPL_FRAMEGEN1_FGENSTS_EnSts(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGENSTS_EnSts_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGENSTS_EnSts_MASK) #define IRIS_MVPL_FRAMEGEN1_FGENSTS_PanicStat_MASK (0x2U) #define IRIS_MVPL_FRAMEGEN1_FGENSTS_PanicStat_SHIFT (1U) /*! PanicStat - Current status of panic mode (0=normal operation mode, 1=panic mode; not locked). */ #define IRIS_MVPL_FRAMEGEN1_FGENSTS_PanicStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGENSTS_PanicStat_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGENSTS_PanicStat_MASK) /*! @} */ /*! @name FRAMEGEN1_FGTIMESTAMP - Time stamp status. */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_LineIndex_MASK (0x3FFFU) #define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_LineIndex_SHIFT (0U) /*! LineIndex - Index of the output line that is currently generated (starts with 0 for first active output line). */ #define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_LineIndex(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_LineIndex_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_LineIndex_MASK) #define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_FrameIndex_MASK (0xFFFFC000U) #define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_FrameIndex_SHIFT (14U) /*! FrameIndex - Index of the output frame that is currently generated (starts with 0 after reset for first output frame). */ #define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_FrameIndex(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_FrameIndex_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_FrameIndex_MASK) /*! @} */ /*! @name FRAMEGEN1_FGCHSTAT - FrameGen Channel Status Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PFifoEmpty_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PFifoEmpty_SHIFT (0U) /*! PFifoEmpty - Read request to empty primary pixel FIFO detected. (Bit locked when 1, clear by using ClrPrimStat). */ #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PFifoEmpty_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PFifoEmpty_MASK) #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PrimSyncStat_MASK (0x100U) #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PrimSyncStat_SHIFT (8U) /*! PrimSyncStat - Current status primary channel synchronization (0 = out of sync (frame tearing), * 1 = in sync (normal operation); not locked). */ #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PrimSyncStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PrimSyncStat_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PrimSyncStat_MASK) #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SFifoEmpty_MASK (0x10000U) #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SFifoEmpty_SHIFT (16U) /*! SFifoEmpty - Read request to empty secondary pixel FIFO detected. (bit locked when 1, clear by using ClrSecStat). */ #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SFifoEmpty_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SFifoEmpty_MASK) #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SkewRangeErr_MASK (0x20000U) #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SkewRangeErr_SHIFT (17U) /*! SkewRangeErr - The secondary channel skew value has run out of the limit defined by SyncRangeLow * and SyncRangeHigh. (bit locked when 1, clear by using ClrSecStat). */ #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SkewRangeErr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SkewRangeErr_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SkewRangeErr_MASK) #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SecSyncStat_MASK (0x1000000U) #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SecSyncStat_SHIFT (24U) /*! SecSyncStat - Current status secondary channel synchronization (0 = out of sync, 1 = in sync; not locked). */ #define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SecSyncStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SecSyncStat_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SecSyncStat_MASK) /*! @} */ /*! @name FRAMEGEN1_FGCHSTATCLR - FrameGen Channel Status Clear Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrPrimStat_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrPrimStat_SHIFT (0U) /*! ClrPrimStat - Clears PFifoEmpty in FgChStat register. */ #define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrPrimStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrPrimStat_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrPrimStat_MASK) #define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrSecStat_MASK (0x10000U) #define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrSecStat_SHIFT (16U) /*! ClrSecStat - Clears SFifoEmpty and SkewRangeErr in FgChStat register. */ #define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrSecStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrSecStat_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrSecStat_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSKEWMON - FrameGen Skew Monitor Register for Secondary Channel Skew Control */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSKEWMON_SkewMon_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FRAMEGEN1_FGSKEWMON_SkewMon_SHIFT (0U) /*! SkewMon - Current skew value monitor for secondary channel skew control. Updated with hlast. */ #define IRIS_MVPL_FRAMEGEN1_FGSKEWMON_SkewMon(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSKEWMON_SkewMon_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSKEWMON_SkewMon_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSFIFOMIN - FrameGen Secondary FIFO Min Fill Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSFIFOMIN_SFifoMin_MASK (0xFFFU) #define IRIS_MVPL_FRAMEGEN1_FGSFIFOMIN_SFifoMin_SHIFT (0U) /*! SFifoMin - Shows the minimal fill level of the secondary channel pixel FIFO. */ #define IRIS_MVPL_FRAMEGEN1_FGSFIFOMIN_SFifoMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSFIFOMIN_SFifoMin_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSFIFOMIN_SFifoMin_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSFIFOMAX - FrameGen Secondary FIFO Max Fill Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSFIFOMAX_SFifoMax_MASK (0xFFFU) #define IRIS_MVPL_FRAMEGEN1_FGSFIFOMAX_SFifoMax_SHIFT (0U) /*! SFifoMax - Shows the maximal fill level of the secondary channel pixel FIFO. */ #define IRIS_MVPL_FRAMEGEN1_FGSFIFOMAX_SFifoMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSFIFOMAX_SFifoMax_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSFIFOMAX_SFifoMax_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSFIFOFILLCLR - FrameGen Secondary FIFO Fill Clear Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSFIFOFILLCLR_SFifoFillClr_MASK (0x1U) #define IRIS_MVPL_FRAMEGEN1_FGSFIFOFILLCLR_SFifoFillClr_SHIFT (0U) /*! SFifoFillClr - Write for clearing register FgSFifoMin and FgSFifoMax. */ #define IRIS_MVPL_FRAMEGEN1_FGSFIFOFILLCLR_SFifoFillClr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSFIFOFILLCLR_SFifoFillClr_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSFIFOFILLCLR_SFifoFillClr_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSREPD - FrameGen Skew Regulation ExtraPolation Debug Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSREPD_EpVal_MASK (0x1FFFFFFFU) #define IRIS_MVPL_FRAMEGEN1_FGSREPD_EpVal_SHIFT (0U) /*! EpVal - Calculated value for line skew extrapolation in blanking. */ #define IRIS_MVPL_FRAMEGEN1_FGSREPD_EpVal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSREPD_EpVal_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSREPD_EpVal_MASK) /*! @} */ /*! @name FRAMEGEN1_FGSRFTD - FrameGen Skew Regulation Frame Total Debug Register */ /*! @{ */ #define IRIS_MVPL_FRAMEGEN1_FGSRFTD_FrTot_MASK (0xFFFFFFFU) #define IRIS_MVPL_FRAMEGEN1_FGSRFTD_FrTot_SHIFT (0U) /*! FrTot - Measured value for frame total measured in display clock cycles. */ #define IRIS_MVPL_FRAMEGEN1_FGSRFTD_FrTot(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRFTD_FrTot_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRFTD_FrTot_MASK) /*! @} */ /*! @name MATRIX1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX1_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_MATRIX1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX1_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name MATRIX1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_MATRIX1_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_MATRIX1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX1_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_MATRIX1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_MATRIX1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_MATRIX1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX1_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_MATRIX1_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_MATRIX1_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_MATRIX1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX1_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name MATRIX1_STATICCONTROL - Color Matrix static control register */ /*! @{ */ #define IRIS_MVPL_MATRIX1_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_MATRIX1_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_MATRIX1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX1_STATICCONTROL_ShdEn_MASK) /*! @} */ /*! @name MATRIX1_CONTROL - Color Matrix control register */ /*! @{ */ #define IRIS_MVPL_MATRIX1_CONTROL_MODE_MASK (0x3U) #define IRIS_MVPL_MATRIX1_CONTROL_MODE_SHIFT (0U) /*! MODE - Operation mode for color matrix * 0b00..Module in neutral mode, input data is bypassed * 0b01..Module in matrix mode, input data is multiplied with matrix values * 0b10..Module in alpha pre-multiplication mode, input color is multiplied with input alpha * 0b11..Reserved, do not use */ #define IRIS_MVPL_MATRIX1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX1_CONTROL_MODE_MASK) #define IRIS_MVPL_MATRIX1_CONTROL_AlphaMask_MASK (0x10U) #define IRIS_MVPL_MATRIX1_CONTROL_AlphaMask_SHIFT (4U) /*! AlphaMask - Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value * smaller than 0.5 are by-passed unchanged. */ #define IRIS_MVPL_MATRIX1_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX1_CONTROL_AlphaMask_MASK) #define IRIS_MVPL_MATRIX1_CONTROL_AlphaInvert_MASK (0x20U) #define IRIS_MVPL_MATRIX1_CONTROL_AlphaInvert_SHIFT (5U) /*! AlphaInvert - Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha * value greater or equal 0.5 are by-passed). */ #define IRIS_MVPL_MATRIX1_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX1_CONTROL_AlphaInvert_MASK) /*! @} */ /*! @name MATRIX1_RED0 - Matrix values for calculation of the red output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_RED0_A11_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX1_RED0_A11_SHIFT (0U) /*! A11 - Value for red input. */ #define IRIS_MVPL_MATRIX1_RED0_A11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX1_RED0_A11_MASK) #define IRIS_MVPL_MATRIX1_RED0_A12_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX1_RED0_A12_SHIFT (16U) /*! A12 - Value for green input. */ #define IRIS_MVPL_MATRIX1_RED0_A12(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX1_RED0_A12_MASK) /*! @} */ /*! @name MATRIX1_RED1 - Matrix values for calculation of the red output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_RED1_A13_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX1_RED1_A13_SHIFT (0U) /*! A13 - Value for blue input. */ #define IRIS_MVPL_MATRIX1_RED1_A13(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX1_RED1_A13_MASK) #define IRIS_MVPL_MATRIX1_RED1_A14_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX1_RED1_A14_SHIFT (16U) /*! A14 - Value for alpha input. */ #define IRIS_MVPL_MATRIX1_RED1_A14(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX1_RED1_A14_MASK) /*! @} */ /*! @name MATRIX1_GREEN0 - Matrix values for calculation of the green output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_GREEN0_A21_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX1_GREEN0_A21_SHIFT (0U) /*! A21 - Value for red input. */ #define IRIS_MVPL_MATRIX1_GREEN0_A21(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX1_GREEN0_A21_MASK) #define IRIS_MVPL_MATRIX1_GREEN0_A22_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX1_GREEN0_A22_SHIFT (16U) /*! A22 - Value for green input. */ #define IRIS_MVPL_MATRIX1_GREEN0_A22(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX1_GREEN0_A22_MASK) /*! @} */ /*! @name MATRIX1_GREEN1 - Matrix values for calculation of the green output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_GREEN1_A23_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX1_GREEN1_A23_SHIFT (0U) /*! A23 - Value for blue input. */ #define IRIS_MVPL_MATRIX1_GREEN1_A23(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX1_GREEN1_A23_MASK) #define IRIS_MVPL_MATRIX1_GREEN1_A24_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX1_GREEN1_A24_SHIFT (16U) /*! A24 - Value for alpha input. */ #define IRIS_MVPL_MATRIX1_GREEN1_A24(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX1_GREEN1_A24_MASK) /*! @} */ /*! @name MATRIX1_BLUE0 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_BLUE0_A31_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX1_BLUE0_A31_SHIFT (0U) /*! A31 - Value for red input. */ #define IRIS_MVPL_MATRIX1_BLUE0_A31(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX1_BLUE0_A31_MASK) #define IRIS_MVPL_MATRIX1_BLUE0_A32_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX1_BLUE0_A32_SHIFT (16U) /*! A32 - Value for green input. */ #define IRIS_MVPL_MATRIX1_BLUE0_A32(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX1_BLUE0_A32_MASK) /*! @} */ /*! @name MATRIX1_BLUE1 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_BLUE1_A33_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX1_BLUE1_A33_SHIFT (0U) /*! A33 - Value for blue input. */ #define IRIS_MVPL_MATRIX1_BLUE1_A33(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX1_BLUE1_A33_MASK) #define IRIS_MVPL_MATRIX1_BLUE1_A34_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX1_BLUE1_A34_SHIFT (16U) /*! A34 - Value for alpha input. */ #define IRIS_MVPL_MATRIX1_BLUE1_A34(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX1_BLUE1_A34_MASK) /*! @} */ /*! @name MATRIX1_ALPHA0 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_ALPHA0_A41_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX1_ALPHA0_A41_SHIFT (0U) /*! A41 - Value for red input. */ #define IRIS_MVPL_MATRIX1_ALPHA0_A41(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX1_ALPHA0_A41_MASK) #define IRIS_MVPL_MATRIX1_ALPHA0_A42_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX1_ALPHA0_A42_SHIFT (16U) /*! A42 - Value for green input. */ #define IRIS_MVPL_MATRIX1_ALPHA0_A42(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX1_ALPHA0_A42_MASK) /*! @} */ /*! @name MATRIX1_ALPHA1 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_ALPHA1_A43_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX1_ALPHA1_A43_SHIFT (0U) /*! A43 - Value for blue input. */ #define IRIS_MVPL_MATRIX1_ALPHA1_A43(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX1_ALPHA1_A43_MASK) #define IRIS_MVPL_MATRIX1_ALPHA1_A44_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX1_ALPHA1_A44_SHIFT (16U) /*! A44 - Value for alpha input. */ #define IRIS_MVPL_MATRIX1_ALPHA1_A44(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX1_ALPHA1_A44_MASK) /*! @} */ /*! @name MATRIX1_OFFSETVECTOR0 - Offset vectors for red and green output. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C1_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C1_SHIFT (0U) /*! C1 - Red output offset. */ #define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C1_MASK) #define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C2_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C2_SHIFT (16U) /*! C2 - Green output offset. */ #define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C2_MASK) /*! @} */ /*! @name MATRIX1_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C3_MASK (0x1FFFU) #define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C3_SHIFT (0U) /*! C3 - Blue output offset. */ #define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C3_MASK) #define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C4_MASK (0x1FFF0000U) #define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C4_SHIFT (16U) /*! C4 - Alpha output offset. Note that the 8-bit alpha input is up-scaled to 10-bit, before the * matrix and this offset is applied, and down-scaled to 8-bit for output afterwards. */ #define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C4_MASK) /*! @} */ /*! @name MATRIX1_LASTCONTROLWORD - Value of last received control word, for debugging. */ /*! @{ */ #define IRIS_MVPL_MATRIX1_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MATRIX1_LASTCONTROLWORD_L_VAL_SHIFT (0U) /*! L_VAL - Value of last received control word. For debug purposes only, read when stable only, * otherwise read data might be corrupted. */ #define IRIS_MVPL_MATRIX1_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX1_LASTCONTROLWORD_L_VAL_MASK) /*! @} */ /*! @name GAMMACOR1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_GAMMACOR1_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_GAMMACOR1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_GAMMACOR1_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name GAMMACOR1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_GAMMACOR1_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR1_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR1_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name GAMMACOR1_STATICCONTROL - Static control settings. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed). */ #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_GAMMACOR1_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_BlueWriteEnable_MASK (0x2U) #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_BlueWriteEnable_SHIFT (1U) /*! BlueWriteEnable - Write enable for the blue color sampling point entries. */ #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_BlueWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_STATICCONTROL_BlueWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR1_STATICCONTROL_BlueWriteEnable_MASK) #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_GreenWriteEnable_MASK (0x4U) #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_GreenWriteEnable_SHIFT (2U) /*! GreenWriteEnable - Write enable for the green color sampling point entries. */ #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_GreenWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_STATICCONTROL_GreenWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR1_STATICCONTROL_GreenWriteEnable_MASK) #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_RedWriteEnable_MASK (0x8U) #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_RedWriteEnable_SHIFT (3U) /*! RedWriteEnable - Write enable for the red color sampling point entries. */ #define IRIS_MVPL_GAMMACOR1_STATICCONTROL_RedWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_STATICCONTROL_RedWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR1_STATICCONTROL_RedWriteEnable_MASK) /*! @} */ /*! @name GAMMACOR1_LUTSTART - Start values for look-up table programming. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR1_LUTSTART_StartBlue_MASK (0x3FFU) #define IRIS_MVPL_GAMMACOR1_LUTSTART_StartBlue_SHIFT (0U) /*! StartBlue - Start value for blue or chroma (V) channel. */ #define IRIS_MVPL_GAMMACOR1_LUTSTART_StartBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTSTART_StartBlue_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTSTART_StartBlue_MASK) #define IRIS_MVPL_GAMMACOR1_LUTSTART_StartGreen_MASK (0xFFC00U) #define IRIS_MVPL_GAMMACOR1_LUTSTART_StartGreen_SHIFT (10U) /*! StartGreen - Start value for green or chroma (U) channel. */ #define IRIS_MVPL_GAMMACOR1_LUTSTART_StartGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTSTART_StartGreen_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTSTART_StartGreen_MASK) #define IRIS_MVPL_GAMMACOR1_LUTSTART_StartRed_MASK (0x3FF00000U) #define IRIS_MVPL_GAMMACOR1_LUTSTART_StartRed_SHIFT (20U) /*! StartRed - Start value for red or luma (Y) channel. */ #define IRIS_MVPL_GAMMACOR1_LUTSTART_StartRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTSTART_StartRed_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTSTART_StartRed_MASK) /*! @} */ /*! @name GAMMACOR1_LUTDELTAS - Delta values for look-up table programming. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaBlue_MASK (0x3FFU) #define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaBlue_SHIFT (0U) /*! DeltaBlue - Delta value for blue or chroma (V) channel. */ #define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaBlue_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaBlue_MASK) #define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaGreen_MASK (0xFFC00U) #define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaGreen_SHIFT (10U) /*! DeltaGreen - Delta value for green or chroma (U) channel. */ #define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaGreen_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaGreen_MASK) #define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaRed_MASK (0x3FF00000U) #define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaRed_SHIFT (20U) /*! DeltaRed - Delta value for red or luma (Y) channel. */ #define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaRed_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaRed_MASK) /*! @} */ /*! @name GAMMACOR1_CONTROL - Dynamic control settings. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR1_CONTROL_Mode_MASK (0x1U) #define IRIS_MVPL_GAMMACOR1_CONTROL_Mode_SHIFT (0U) /*! Mode - Operation mode for gamma correction unit * 0b0..Module in neutral mode, input data is bypassed to the output. * 0b1..Module in gamma correction mode. */ #define IRIS_MVPL_GAMMACOR1_CONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_CONTROL_Mode_SHIFT)) & IRIS_MVPL_GAMMACOR1_CONTROL_Mode_MASK) #define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaMask_MASK (0x10U) #define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaMask_SHIFT (4U) /*! AlphaMask - Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value * smaller than 0.5 are by-passed unchanged. */ #define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_GAMMACOR1_CONTROL_AlphaMask_MASK) #define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaInvert_MASK (0x20U) #define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaInvert_SHIFT (5U) /*! AlphaInvert - Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha * value greater or equal 0.5 are by-passed). */ #define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_GAMMACOR1_CONTROL_AlphaInvert_MASK) /*! @} */ /*! @name GAMMACOR1_STATUS - Internal status bits. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR1_STATUS_WriteTimeout_MASK (0x1U) #define IRIS_MVPL_GAMMACOR1_STATUS_WriteTimeout_SHIFT (0U) /*! WriteTimeout - Timeout detected when writing to the sampling point table. */ #define IRIS_MVPL_GAMMACOR1_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_GAMMACOR1_STATUS_WriteTimeout_MASK) /*! @} */ /*! @name GAMMACOR1_LASTCONTROLWORD - Value of last received control word. */ /*! @{ */ #define IRIS_MVPL_GAMMACOR1_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU) #define IRIS_MVPL_GAMMACOR1_LASTCONTROLWORD_L_VAL_SHIFT (0U) /*! L_VAL - Value of last received control word. For debug purposes only, read when stable only, * otherwise read data might be corrupted. */ #define IRIS_MVPL_GAMMACOR1_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_GAMMACOR1_LASTCONTROLWORD_L_VAL_MASK) /*! @} */ /*! @name DITHER1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_DITHER1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_DITHER1_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_DITHER1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_DITHER1_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name DITHER1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_DITHER1_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_DITHER1_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_DITHER1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_DITHER1_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_DITHER1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_DITHER1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_DITHER1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_DITHER1_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_DITHER1_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_DITHER1_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_DITHER1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_DITHER1_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name DITHER1_CONTROL - Dither Unit common control. */ /*! @{ */ #define IRIS_MVPL_DITHER1_CONTROL_mode_MASK (0x1U) #define IRIS_MVPL_DITHER1_CONTROL_mode_SHIFT (0U) /*! mode - Mode which switches Dither Unit on/off. * 0b0..Neutral mode. Pixels by-pass the Dither Unit, all other settings are ignored. * 0b1..Dither Unit is active. */ #define IRIS_MVPL_DITHER1_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_CONTROL_mode_SHIFT)) & IRIS_MVPL_DITHER1_CONTROL_mode_MASK) /*! @} */ /*! @name DITHER1_DITHERCONTROL - Dither Unit processing control. */ /*! @{ */ #define IRIS_MVPL_DITHER1_DITHERCONTROL_blue_range_select_MASK (0x7U) #define IRIS_MVPL_DITHER1_DITHERCONTROL_blue_range_select_SHIFT (0U) /*! blue_range_select - Mode which sets the reduction of component widths. * 0b010..Reduces blue component width from 10 bit to 8bit. * 0b011..Reduces blue component width from 10 bit to 7bit. * 0b100..Reduces blue component width from 10 bit to 6bit. * 0b101..Reduces blue component width from 10 bit to 5bit. */ #define IRIS_MVPL_DITHER1_DITHERCONTROL_blue_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_blue_range_select_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_blue_range_select_MASK) #define IRIS_MVPL_DITHER1_DITHERCONTROL_green_range_select_MASK (0x70U) #define IRIS_MVPL_DITHER1_DITHERCONTROL_green_range_select_SHIFT (4U) /*! green_range_select - Mode which sets the reduction of component widths. * 0b010..Reduces green component width from 10 bit to 8bit. * 0b011..Reduces green component width from 10 bit to 7bit. * 0b100..Reduces green component width from 10 bit to 6bit. * 0b101..Reduces green component width from 10 bit to 5bit. */ #define IRIS_MVPL_DITHER1_DITHERCONTROL_green_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_green_range_select_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_green_range_select_MASK) #define IRIS_MVPL_DITHER1_DITHERCONTROL_red_range_select_MASK (0x700U) #define IRIS_MVPL_DITHER1_DITHERCONTROL_red_range_select_SHIFT (8U) /*! red_range_select - Mode which sets the reduction of component widths. * 0b010..Reduces red component width from 10 bit to 8bit. * 0b011..Reduces red component width from 10 bit to 7bit. * 0b100..Reduces red component width from 10 bit to 6bit. * 0b101..Reduces red component width from 10 bit to 5bit. */ #define IRIS_MVPL_DITHER1_DITHERCONTROL_red_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_red_range_select_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_red_range_select_MASK) #define IRIS_MVPL_DITHER1_DITHERCONTROL_offset_select_MASK (0x10000U) #define IRIS_MVPL_DITHER1_DITHERCONTROL_offset_select_SHIFT (16U) /*! offset_select - Selects the method how the dither offset is calculated. * 0b0..Offset is a bayer matrix value, which is selected according to pixel frame position. * 0b1..Offset is the sum from a bayer matrix value, which is selected according to pixel frame position, and a * value from a regular sequence, which changes each frame. */ #define IRIS_MVPL_DITHER1_DITHERCONTROL_offset_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_offset_select_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_offset_select_MASK) #define IRIS_MVPL_DITHER1_DITHERCONTROL_algo_select_MASK (0x300000U) #define IRIS_MVPL_DITHER1_DITHERCONTROL_algo_select_SHIFT (20U) /*! algo_select - The number of output colors that can virtually be displayed by dithering is * slightly lower than the number of physical input colors. This field selects how the mapping is done. * 0b01..Best possible resolution for most dark colors. Adds a diminutive offset to overall image brightness. * 0b10..Preserves overall image brightness. Cannot resolve most dark and most bright colors. All codes in-between are distributed perfectly smooth. * 0b11..Preserves overall image brightness. Best possible distribution of color codes over complete range. */ #define IRIS_MVPL_DITHER1_DITHERCONTROL_algo_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_algo_select_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_algo_select_MASK) #define IRIS_MVPL_DITHER1_DITHERCONTROL_alpha_mode_MASK (0x3000000U) #define IRIS_MVPL_DITHER1_DITHERCONTROL_alpha_mode_SHIFT (24U) /*! alpha_mode - Enables/disables that dithering can be switched by alpha bit. * 0b00..The alpha bit is not considered. * 0b01..Red, green and blue components are only dithered, if the alpha bit is 1. * 0b10..Red, green and blue components are only dithered, if the alpha bit is 0. */ #define IRIS_MVPL_DITHER1_DITHERCONTROL_alpha_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_alpha_mode_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_alpha_mode_MASK) /*! @} */ /*! @name DITHER1_RELEASE - Dither Unit release. */ /*! @{ */ #define IRIS_MVPL_DITHER1_RELEASE_subversion_MASK (0xFFU) #define IRIS_MVPL_DITHER1_RELEASE_subversion_SHIFT (0U) /*! subversion - Dither Unit subversion. */ #define IRIS_MVPL_DITHER1_RELEASE_subversion(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_RELEASE_subversion_SHIFT)) & IRIS_MVPL_DITHER1_RELEASE_subversion_MASK) #define IRIS_MVPL_DITHER1_RELEASE_version_MASK (0xFF00U) #define IRIS_MVPL_DITHER1_RELEASE_version_SHIFT (8U) /*! version - Dither Unit version. */ #define IRIS_MVPL_DITHER1_RELEASE_version(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_RELEASE_version_SHIFT)) & IRIS_MVPL_DITHER1_RELEASE_version_MASK) /*! @} */ /*! @name TCON1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_TCON1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_TCON1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_TCON1_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name TCON1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_TCON1_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_TCON1_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_TCON1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_TCON1_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_TCON1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_TCON1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_TCON1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_TCON1_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_TCON1_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_TCON1_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_TCON1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_TCON1_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name TCON1_SSQCYCLE - This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles */ /*! @{ */ #define IRIS_MVPL_TCON1_SSQCYCLE_SSQCYCLE_MASK (0x3FU) #define IRIS_MVPL_TCON1_SSQCYCLE_SSQCYCLE_SHIFT (0U) /*! SSQCYCLE - Sequencer cycle length (number -1) of sequencer cycles */ #define IRIS_MVPL_TCON1_SSQCYCLE_SSQCYCLE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SSQCYCLE_SSQCYCLE_SHIFT)) & IRIS_MVPL_TCON1_SSQCYCLE_SSQCYCLE_MASK) /*! @} */ /*! @name TCON1_SWRESET - TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document Note: 1/ if tsig[11] pulse=n*pixel_period, (n-1)*0xFF will be blent between ResetWordStart and ResetWordEnd into miniLVDS stream Note: 2/ if( EnResetWord=0) Reset-Pulse (ResetWordStart,ResetWordEnd) won't be blent into miniLVDS stream. Pixels will be transfered unchanged */ /*! @{ */ #define IRIS_MVPL_TCON1_SWRESET_SWReset_MASK (0x1U) #define IRIS_MVPL_TCON1_SWRESET_SWReset_SHIFT (0U) /*! SWReset - Software reset * 0b0..operation mode * 0b1..So long SWReset = 0x1 tcon is in 'SW reset state' and it is released by internal logic (SWReset is * released and end of frame arrived), read: 0b: reset not active 1b: reset active (that means NO pixel of video * frame is excepted until 'SW reset state' is released) */ #define IRIS_MVPL_TCON1_SWRESET_SWReset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SWRESET_SWReset_SHIFT)) & IRIS_MVPL_TCON1_SWRESET_SWReset_MASK) #define IRIS_MVPL_TCON1_SWRESET_EnResetWord_MASK (0xFFF0U) #define IRIS_MVPL_TCON1_SWRESET_EnResetWord_SHIFT (4U) /*! EnResetWord - Enable to blend ResetWord into miniLVDS stream EnResetWord[5:0] mapped to enable * Blending Reset Pulse to [RLV5.RLV0]. EnResetWord[11:6] mapped to enable Blending Reset Pulse to * [LLV5.LLV0]. */ #define IRIS_MVPL_TCON1_SWRESET_EnResetWord(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SWRESET_EnResetWord_SHIFT)) & IRIS_MVPL_TCON1_SWRESET_EnResetWord_MASK) #define IRIS_MVPL_TCON1_SWRESET_ResetWordEnd_MASK (0xFF0000U) #define IRIS_MVPL_TCON1_SWRESET_ResetWordEnd_SHIFT (16U) /*! ResetWordEnd - 8-Bits Value, that will be blent on falling edge of tsig[11] into miniLVDS stream */ #define IRIS_MVPL_TCON1_SWRESET_ResetWordEnd(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SWRESET_ResetWordEnd_SHIFT)) & IRIS_MVPL_TCON1_SWRESET_ResetWordEnd_MASK) #define IRIS_MVPL_TCON1_SWRESET_ResetWordStart_MASK (0xFF000000U) #define IRIS_MVPL_TCON1_SWRESET_ResetWordStart_SHIFT (24U) /*! ResetWordStart - 8-Bits Value, that will be blent on rising edge of tsig[11] into miniLVDS stream */ #define IRIS_MVPL_TCON1_SWRESET_ResetWordStart(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SWRESET_ResetWordStart_SHIFT)) & IRIS_MVPL_TCON1_SWRESET_ResetWordStart_MASK) /*! @} */ /*! @name TCON1_CTRL - TCON Control register */ /*! @{ */ #define IRIS_MVPL_TCON1_CTRL_ChannelMode_MASK (0x3U) #define IRIS_MVPL_TCON1_CTRL_ChannelMode_SHIFT (0U) /*! ChannelMode - Selects one of tcon operation modes, SINGLE, DUAL_INTERLEAVED or DUAL_SPLIT. If * MiniLVDS operation is selected (EnLVDS = ENABLE_LVDS and LVDSMode = Mini_LVDS), tcon operates in * MiniLVDS mode, indepent on the Value of channelMode. SplitPosition must be specified in * MiniLVDS operation in DUAL_INTERLEAVED or DUAL_SPLIT mode, the horizontal parameter of signal * generator have to set twice as they are specified in the panel-specification (panel: 320, * tsig_start 0, tsig_stop 320 on DUAL-Mode : tsig_start 0, tsig_stop 640 ... (SplitPosition is * automatically adjusted) ) * 0b00..Single pixel mode. Both channels channel are active at full pixel clock. If bitmap of both panels are the same, both panels are identical * 0b01..Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives display columns with even and 2nd one with odd index. * 0b10..Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives the left and 2nd * one the righ half of the display. Note : data_en is needed in this mode */ #define IRIS_MVPL_TCON1_CTRL_ChannelMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_ChannelMode_SHIFT)) & IRIS_MVPL_TCON1_CTRL_ChannelMode_MASK) #define IRIS_MVPL_TCON1_CTRL_tcon1_sync_MASK (0x4U) #define IRIS_MVPL_TCON1_CTRL_tcon1_sync_SHIFT (2U) /*! tcon1_sync - Select synchronization between hsync/vsync and hlast/vlast * 0b0..tcon timing generator synchronized to hlast, vlast * 0b1..tcon timing generator synchronized to hsync, vsync where horizontal synchronization is synchronized at the falling edge of hsync */ #define IRIS_MVPL_TCON1_CTRL_tcon1_sync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_tcon1_sync_SHIFT)) & IRIS_MVPL_TCON1_CTRL_tcon1_sync_MASK) #define IRIS_MVPL_TCON1_CTRL_Bypass_MASK (0x8U) #define IRIS_MVPL_TCON1_CTRL_Bypass_SHIFT (3U) /*! Bypass - Bypassing synchronization * 0b0..tcon operation mode * 0b1..tcon in Bypass mode. input pixel and its sync-signals are bypassed to tcon-output */ #define IRIS_MVPL_TCON1_CTRL_Bypass(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_Bypass_SHIFT)) & IRIS_MVPL_TCON1_CTRL_Bypass_MASK) #define IRIS_MVPL_TCON1_CTRL_Inv_Ctrl_MASK (0xF0U) #define IRIS_MVPL_TCON1_CTRL_Inv_Ctrl_SHIFT (4U) /*! Inv_Ctrl - Minimize the toggle rate of tcon output for display panel, that supports data * inversion control. Otherwise set Inv_Ctrl = 0. Valid for all channels . Inv_Ctrl does not effect any * function on LVDS-Output. * 0b0000..Disable inversion control * 0b0001..Enable inversion control for number of RGB-Bits = 2 * 0b1010..Enable inversion control for number of RGB-Bits = 20 * 0b1011..Enable inversion control for number of RGB-Bits = 22 * 0b1100..Enable inversion control for number of RGB-Bits = 24 * 0b1101..Enable inversion control for number of RGB-Bits = 26 * 0b1110..Enable inversion control for number of RGB-Bits = 28 * 0b1111..Enable inversion control for number of RGB-Bits = 30 * 0b0010..Enable inversion control for number of RGB-Bits = 4 * 0b0011..Enable inversion control for number of RGB-Bits = 6 * 0b0100..Enable inversion control for number of RGB-Bits = 8 * 0b0101..Enable inversion control for number of RGB-Bits = 10 * 0b0110..Enable inversion control for number of RGB-Bits = 12 * 0b0111..Enable inversion control for number of RGB-Bits = 14 * 0b1000..Enable inversion control for number of RGB-Bits = 16 * 0b1001..Enable inversion control for number of RGB-Bits = 18 */ #define IRIS_MVPL_TCON1_CTRL_Inv_Ctrl(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_Inv_Ctrl_SHIFT)) & IRIS_MVPL_TCON1_CTRL_Inv_Ctrl_MASK) #define IRIS_MVPL_TCON1_CTRL_EnLVDS_MASK (0x100U) #define IRIS_MVPL_TCON1_CTRL_EnLVDS_SHIFT (8U) /*! EnLVDS - Enable LVDS Mode * 0b0..Disable LVDS, Enable TTL and RSDS * 0b1..Enable LVDS , TTL and RSDS are disable */ #define IRIS_MVPL_TCON1_CTRL_EnLVDS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_EnLVDS_SHIFT)) & IRIS_MVPL_TCON1_CTRL_EnLVDS_MASK) #define IRIS_MVPL_TCON1_CTRL_LVDSMode_MASK (0x200U) #define IRIS_MVPL_TCON1_CTRL_LVDSMode_SHIFT (9U) /*! LVDSMode - Selection the LVDS Mode if EnLVDS = ENABLE_LVDS * 0b0..LVDS Mode, refered to OpenLDI * 0b1..MiniLVDS */ #define IRIS_MVPL_TCON1_CTRL_LVDSMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_LVDSMode_SHIFT)) & IRIS_MVPL_TCON1_CTRL_LVDSMode_MASK) #define IRIS_MVPL_TCON1_CTRL_LVDS_Balance_MASK (0x400U) #define IRIS_MVPL_TCON1_CTRL_LVDS_Balance_SHIFT (10U) /*! LVDS_Balance - Operation mode of LVDS-OpenLDI * 0b0..LVDS operates in 24 bits Unbalanced Mode * 0b1..LVDS operates in 24 bits Balanced Mode */ #define IRIS_MVPL_TCON1_CTRL_LVDS_Balance(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_LVDS_Balance_SHIFT)) & IRIS_MVPL_TCON1_CTRL_LVDS_Balance_MASK) #define IRIS_MVPL_TCON1_CTRL_LVDS_CLOCK_INV_MASK (0x800U) #define IRIS_MVPL_TCON1_CTRL_LVDS_CLOCK_INV_SHIFT (11U) /*! LVDS_CLOCK_INV - Inversion the polatity of lvds clock in OpenLDI Mode * 0b0..NON-Invert LVDS Clock * 0b1..Invert LVDS Clock */ #define IRIS_MVPL_TCON1_CTRL_LVDS_CLOCK_INV(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_LVDS_CLOCK_INV_SHIFT)) & IRIS_MVPL_TCON1_CTRL_LVDS_CLOCK_INV_MASK) #define IRIS_MVPL_TCON1_CTRL_MiniLVDS_OpCode_MASK (0x7000U) #define IRIS_MVPL_TCON1_CTRL_MiniLVDS_OpCode_SHIFT (12U) /*! MiniLVDS_OpCode - Operation mode of MiniLVDS * 0b000..MiniLVDS operates in 6 and 8 bit data, three pairs * 0b001..Not Implemented * 0b010..Not Implemented * 0b011..MiniLVDS operates in 6 and 8 bit data, six pairs * 0b100..RESERVED1 * 0b101..RESERVED2 * 0b110..RESERVED3 * 0b111..RESERVED4 */ #define IRIS_MVPL_TCON1_CTRL_MiniLVDS_OpCode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_MiniLVDS_OpCode_SHIFT)) & IRIS_MVPL_TCON1_CTRL_MiniLVDS_OpCode_MASK) #define IRIS_MVPL_TCON1_CTRL_DUAL_SWAP_MASK (0x8000U) #define IRIS_MVPL_TCON1_CTRL_DUAL_SWAP_SHIFT (15U) /*! DUAL_SWAP - pixels of lower/upper channel can be swapped if tcon operates in DUAL-mode (include * LVDS/miniLVDS) no effect in SINGLE-mode * 0b0..NON-swapping pixels between lower-channel and upper-channel * 0b1..swapping pixels between lower-channel and upper-channel */ #define IRIS_MVPL_TCON1_CTRL_DUAL_SWAP(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_DUAL_SWAP_SHIFT)) & IRIS_MVPL_TCON1_CTRL_DUAL_SWAP_MASK) #define IRIS_MVPL_TCON1_CTRL_SplitPosition_MASK (0x3FFF0000U) #define IRIS_MVPL_TCON1_CTRL_SplitPosition_SHIFT (16U) /*! SplitPosition - Index of first column of right display half when ChannelMode is DUAL_SPLIT. - * SplitPosition must be less or equal 1280 - (Hact - SplitPosition) must be less or equal 1280 - * If (SplitPosition greater than (Hact - SplitPosition)) Htotal greather 2*SplitPosition else * Htotal greather (Hact - SplitPosition) - NOTE: once setting SplitPosition data_en is needed */ #define IRIS_MVPL_TCON1_CTRL_SplitPosition(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_CTRL_SplitPosition_SHIFT)) & IRIS_MVPL_TCON1_CTRL_SplitPosition_MASK) /*! @} */ /*! @name TCON1_RSDSINVCTRL - Controls inversion of output polarity when connected IO cells operate in RSDS mode */ /*! @{ */ #define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_SHIFT (0U) /*! RSDS_Inv - Inversion vector for 1st channel. For i in [ 0 .. 11 ]; if RSDS_Inv [ i ] == 0 => * NON-Inversion of RSDS [ i ] else Inversion of RSDS [ i ] */ #define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_SHIFT)) & IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_MASK) #define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_Dual_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_Dual_SHIFT (16U) /*! RSDS_Inv_Dual - Same as RSDS_inv for 2nd channel */ #define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_Dual_SHIFT)) & IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_Dual_MASK) /*! @} */ /*! @name TCON1_MAPBIT3_0 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit0_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit0_SHIFT (0U) /*! MapBit0 - map bit[0] from [Blue, Green, Red] or from TSig[11:0]. If MapBit0 in [29..0] => bit[0] * = [Blue, Green, Red]; if MapBit0 in [41..30] => bit[0] in {TSig[11]..TSig[0]}; If MapBit0=43 * => bit[0]=0; if MapBit0=42 => bit[0]=1 */ #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_MapBit0_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_MapBit0_MASK) #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit1_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit1_SHIFT (8U) /*! MapBit1 - map bit[1] from [Blue, Green, Red] or from TSig[11:0]. If MapBit1 in [29..0] => bit[1] * = [Blue, Green, Red]; if MapBit1 in [41..30] => bit[1] in {TSig[11]..TSig[0]}; If MapBit1=43 * => bit[1]=0; if MapBit1=42 => bit[1]=1 */ #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_MapBit1_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_MapBit1_MASK) #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit2_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit2_SHIFT (16U) /*! MapBit2 - map bit[2] from [Blue, Green, Red] or from TSig[11:0]. If MapBit2 in [29..0] => bit[2] * = [Blue, Green, Red]; if MapBit2 in [41..30] => bit[2] in {TSig[11]..TSig[0]}; If MapBit2=43 * => bit[2]=0; if MapBit2=42 => bit[2]=1 */ #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_MapBit2_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_MapBit2_MASK) #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit3_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit3_SHIFT (24U) /*! MapBit3 - map bit[3] from [Blue, Green, Red] or from TSig[11:0]. If MapBit3 in [29..0] => bit[3] * = [Blue, Green, Red]; if MapBit3 in [41..30] => bit[3] in {TSig[11]..TSig[0]}; If MapBit3=43 * => bit[3]=0; if MapBit3=42 => bit[3]=1 */ #define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_MapBit3_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_MapBit3_MASK) /*! @} */ /*! @name TCON1_MAPBIT7_4 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit4_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit4_SHIFT (0U) /*! MapBit4 - map bit[4] from [Blue, Green, Red] or from TSig[11:0]. If MapBit4 in [29..0] => bit[4] * = [Blue, Green, Red]; if MapBit4 in [41..30] => bit[4] in {TSig[11]..TSig[0]}; If MapBit4=43 * => bit[4]=0; if MapBit4=42 => bit[4]=1 */ #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_MapBit4_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_MapBit4_MASK) #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit5_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit5_SHIFT (8U) /*! MapBit5 - map bit[5] from [Blue, Green, Red] or from TSig[11:0]. If MapBit5 in [29..0] => bit[5] * = [Blue, Green, Red]; if MapBit5 in [41..30] => bit[5] in {TSig[11]..TSig[0]}; If MapBit5=43 * => bit[5]=0; if MapBit5=42 => bit[5]=1 */ #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_MapBit5_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_MapBit5_MASK) #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit6_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit6_SHIFT (16U) /*! MapBit6 - map bit[6] from [Blue, Green, Red] or from TSig[11:0]. If MapBit6 in [29..0] => bit[6] * = [Blue, Green, Red]; if MapBit6 in [41..30] => bit[6] in {TSig[11]..TSig[0]}; If MapBit6=43 * => bit[6]=0; if MapBit6=42 => bit[6]=1 */ #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_MapBit6_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_MapBit6_MASK) #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit7_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit7_SHIFT (24U) /*! MapBit7 - map bit[7] from [Blue, Green, Red] or from TSig[11:0]. If MapBit7 in [29..0] => bit[7] * = [Blue, Green, Red]; if MapBit7 in [41..30] => bit[7] in {TSig[11]..TSig[0]}; If MapBit7=43 * => bit[7]=0; if MapBit7=42 => bit[7]=1 */ #define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_MapBit7_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_MapBit7_MASK) /*! @} */ /*! @name TCON1_MAPBIT11_8 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit8_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit8_SHIFT (0U) /*! MapBit8 - map bit[8] from [Blue, Green, Red] or from TSig[11:0]. If MapBit8 in [29..0] => bit[8] * = [Blue, Green, Red]; if MapBit8 in [41..30] => bit[8] in {TSig[11]..TSig[0]}; If MapBit8=43 * => bit[8]=0; if MapBit8=42 => bit[8]=1 */ #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_MapBit8_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_MapBit8_MASK) #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit9_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit9_SHIFT (8U) /*! MapBit9 - map bit[9] from [Blue, Green, Red] or from TSig[11:0]. If MapBit9 in [29..0] => bit[9] * = [Blue, Green, Red]; if MapBit9 in [41..30] => bit[9] in {TSig[11]..TSig[0]}; If MapBit9=43 * => bit[9]=0; if MapBit9=42 => bit[9]=1 */ #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_MapBit9_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_MapBit9_MASK) #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit10_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit10_SHIFT (16U) /*! MapBit10 - map bit[10] from [Blue, Green, Red] or from TSig[11:0]. If MapBit10 in [29..0] => * bit[10] = [Blue, Green, Red]; if MapBit10 in [41..30] => bit[10] in {TSig[11]..TSig[0]}; If * MapBit10=43 => bit[10]=0; if MapBit10=42 => bit[10]=1 */ #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_MapBit10_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_MapBit10_MASK) #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit11_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit11_SHIFT (24U) /*! MapBit11 - map bit[11] from [Blue, Green, Red] or from TSig[11:0]. If MapBit11 in [29..0] => * bit[11] = [Blue, Green, Red]; if MapBit11 in [41..30] => bit[11] in {TSig[11]..TSig[0]}; If * MapBit11=43 => bit[11]=0; if MapBit11=42 => bit[11]=1 */ #define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_MapBit11_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_MapBit11_MASK) /*! @} */ /*! @name TCON1_MAPBIT15_12 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit12_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit12_SHIFT (0U) /*! MapBit12 - map bit[12] from [Blue, Green, Red] or from TSig[11:0]. If MapBit12 in [29..0] => * bit[12] = [Blue, Green, Red]; if MapBit12 in [41..30] => bit[12] in {TSig[11]..TSig[0]}; If * MapBit12=43 => bit[12]=0; if MapBit12=42 => bit[12]=1 */ #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit12(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_MapBit12_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_MapBit12_MASK) #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit13_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit13_SHIFT (8U) /*! MapBit13 - map bit[13] from [Blue, Green, Red] or from TSig[11:0]. If MapBit13 in [29..0] => * bit[13] = [Blue, Green, Red]; if MapBit13 in [41..30] => bit[13] in {TSig[11]..TSig[0]}; If * MapBit13=43 => bit[13]=0; if MapBit13=42 => bit[13]=1 */ #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit13(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_MapBit13_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_MapBit13_MASK) #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit14_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit14_SHIFT (16U) /*! MapBit14 - map bit[14] from [Blue, Green, Red] or from TSig[11:0]. If MapBit14 in [29..0] => * bit[14] = [Blue, Green, Red]; if MapBit14 in [41..30] => bit[14] in {TSig[11]..TSig[0]}; If * MapBit14=43 => bit[14]=0; if MapBit14=42 => bit[14]=1 */ #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit14(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_MapBit14_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_MapBit14_MASK) #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit15_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit15_SHIFT (24U) /*! MapBit15 - map bit[15] from [Blue, Green, Red] or from TSig[11:0]. If MapBit15 in [29..0] => * bit[15] = [Blue, Green, Red]; if MapBit15 in [41..30] => bit[15] in {TSig[11]..TSig[0]}; If * MapBit15=43 => bit[15]=0; if MapBit15=42 => bit[15]=1 */ #define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit15(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_MapBit15_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_MapBit15_MASK) /*! @} */ /*! @name TCON1_MAPBIT19_16 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit16_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit16_SHIFT (0U) /*! MapBit16 - map bit[16] from [Blue, Green, Red] or from TSig[11:0]. If MapBit16 in [29..0] => * bit[16] = [Blue, Green, Red]; if MapBit16 in [41..30] => bit[16] in {TSig[11]..TSig[0]}; If * MapBit16=43 => bit[16]=0; if MapBit16=42 => bit[16]=1 */ #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit16(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_MapBit16_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_MapBit16_MASK) #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit17_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit17_SHIFT (8U) /*! MapBit17 - map bit[17] from [Blue, Green, Red] or from TSig[11:0]. If MapBit17 in [29..0] => * bit[17] = [Blue, Green, Red]; if MapBit17 in [41..30] => bit[17] in {TSig[11]..TSig[0]}; If * MapBit17=43 => bit[17]=0; if MapBit17=42 => bit[17]=1 */ #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit17(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_MapBit17_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_MapBit17_MASK) #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit18_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit18_SHIFT (16U) /*! MapBit18 - map bit[18] from [Blue, Green, Red] or from TSig[11:0]. If MapBit18 in [29..0] => * bit[18] = [Blue, Green, Red]; if MapBit18 in [41..30] => bit[18] in {TSig[11]..TSig[0]}; If * MapBit18=43 => bit[18]=0; if MapBit18=42 => bit[18]=1 */ #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit18(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_MapBit18_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_MapBit18_MASK) #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit19_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit19_SHIFT (24U) /*! MapBit19 - map bit[19] from [Blue, Green, Red] or from TSig[11:0]. If MapBit19 in [29..0] => * bit[19] = [Blue, Green, Red]; if MapBit19 in [41..30] => bit[19] in {TSig[11]..TSig[0]}; If * MapBit19=43 => bit[19]=0; if MapBit19=42 => bit[19]=1 */ #define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit19(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_MapBit19_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_MapBit19_MASK) /*! @} */ /*! @name TCON1_MAPBIT23_20 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit20_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit20_SHIFT (0U) /*! MapBit20 - map bit[20] from [Blue, Green, Red] or from TSig[11:0]. If MapBit20 in [29..0] => * bit[20] = [Blue, Green, Red]; if MapBit20 in [41..30] => bit[20] in {TSig[11]..TSig[0]}; If * MapBit20=43 => bit[20]=0; if MapBit20=42 => bit[20]=1 */ #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit20(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_MapBit20_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_MapBit20_MASK) #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit21_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit21_SHIFT (8U) /*! MapBit21 - map bit[21] from [Blue, Green, Red] or from TSig[11:0]. If MapBit21 in [29..0] => * bit[21] = [Blue, Green, Red]; if MapBit21 in [41..30] => bit[21] in {TSig[11]..TSig[0]}; If * MapBit21=43 => bit[21]=0; if MapBit21=42 => bit[21]=1 */ #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit21(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_MapBit21_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_MapBit21_MASK) #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit22_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit22_SHIFT (16U) /*! MapBit22 - map bit[22] from [Blue, Green, Red] or from TSig[11:0]. If MapBit22 in [29..0] => * bit[22] = [Blue, Green, Red]; if MapBit22 in [41..30] => bit[22] in {TSig[11]..TSig[0]}; If * MapBit22=43 => bit[22]=0; if MapBit22=42 => bit[22]=1 */ #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit22(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_MapBit22_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_MapBit22_MASK) #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit23_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit23_SHIFT (24U) /*! MapBit23 - map bit[23] from [Blue, Green, Red] or from TSig[11:0]. If MapBit23 in [29..0] => * bit[23] = [Blue, Green, Red]; if MapBit23 in [41..30] => bit[23] in {TSig[11]..TSig[0]}; If * MapBit23=43 => bit[23]=0; if MapBit23=42 => bit[23]=1 */ #define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit23(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_MapBit23_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_MapBit23_MASK) /*! @} */ /*! @name TCON1_MAPBIT27_24 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit24_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit24_SHIFT (0U) /*! MapBit24 - map bit[24] from [Blue, Green, Red] or from TSig[11:0]. If MapBit24 in [29..0] => * bit[24] = [Blue, Green, Red]; if MapBit24 in [41..30] => bit[24] in {TSig[11]..TSig[0]}; If * MapBit24=43 => bit[24]=0; if MapBit24=42 => bit[24]=1 */ #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit24(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_MapBit24_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_MapBit24_MASK) #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit25_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit25_SHIFT (8U) /*! MapBit25 - map bit[25] from [Blue, Green, Red] or from TSig[11:0]. If MapBit25 in [29..0] => * bit[25] = [Blue, Green, Red]; if MapBit25 in [41..30] => bit[25] in {TSig[11]..TSig[0]}; If * MapBit25=43 => bit[25]=0; if MapBit25=42 => bit[25]=1 */ #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit25(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_MapBit25_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_MapBit25_MASK) #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit26_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit26_SHIFT (16U) /*! MapBit26 - map bit[26] from [Blue, Green, Red] or from TSig[11:0]. If MapBit26 in [29..0] => * bit[26] = [Blue, Green, Red]; if MapBit26 in [41..30] => bit[26] in {TSig[11]..TSig[0]}; If * MapBit26=43 => bit[26]=0; if MapBit26=42 => bit[26]=1 */ #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit26(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_MapBit26_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_MapBit26_MASK) #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit27_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit27_SHIFT (24U) /*! MapBit27 - map bit[27] from [Blue, Green, Red] or from TSig[11:0]. If MapBit27 in [29..0] => * bit[27] = [Blue, Green, Red]; if MapBit27 in [41..30] => bit[27] in {TSig[11]..TSig[0]}; If * MapBit27=43 => bit[27]=0; if MapBit27=42 => bit[27]=1 */ #define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit27(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_MapBit27_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_MapBit27_MASK) /*! @} */ /*! @name TCON1_MAPBIT31_28 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit28_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit28_SHIFT (0U) /*! MapBit28 - map bit[28] from [Blue, Green, Red] or from TSig[11:0]. If MapBit28 in [29..0] => * bit[28] = [Blue, Green, Red]; if MapBit28 in [41..30] => bit[28] in {TSig[11]..TSig[0]}; If * MapBit28=43 => bit[28]=0; if MapBit28=42 => bit[28]=1 */ #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit28(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_MapBit28_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_MapBit28_MASK) #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit29_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit29_SHIFT (8U) /*! MapBit29 - map bit[29] from [Blue, Green, Red] or from TSig[11:0]. If MapBit29 in [29..0] => * bit[29] = [Blue, Green, Red]; if MapBit29 in [41..30] => bit[29] in {TSig[11]..TSig[0]}; If * MapBit29=43 => bit[29]=0; if MapBit29=42 => bit[29]=1 */ #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit29(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_MapBit29_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_MapBit29_MASK) #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit30_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit30_SHIFT (16U) /*! MapBit30 - map bit[30] from [Blue, Green, Red] or from TSig[11:0]. If MapBit30 in [29..0] => * bit[30] = [Blue, Green, Red]; if MapBit30 in [41..30] => bit[30] in {TSig[11]..TSig[0]}; If * MapBit30=43 => bit[30]=0; if MapBit30=42 => bit[30]=1 */ #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit30(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_MapBit30_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_MapBit30_MASK) #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit31_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit31_SHIFT (24U) /*! MapBit31 - map bit[31] from [Blue, Green, Red] or from TSig[11:0]. If MapBit31 in [29..0] => * bit[31] = [Blue, Green, Red]; if MapBit31 in [41..30] => bit[31] in {TSig[11]..TSig[0]}; If * MapBit31=43 => bit[31]=0; if MapBit31=42 => bit[31]=1 */ #define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit31(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_MapBit31_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_MapBit31_MASK) /*! @} */ /*! @name TCON1_MAPBIT34_32 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit32_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit32_SHIFT (0U) /*! MapBit32 - map bit[32] from [Blue, Green, Red] or from TSig[11:0]. If MapBit32 in [29..0] => * bit[32] = [Blue, Green, Red]; if MapBit32 in [41..30] => bit[32] in {TSig[11]..TSig[0]}; If * MapBit32=43 => bit[32]=0; if MapBit32=42 => bit[32]=1 */ #define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit32(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_MapBit32_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_MapBit32_MASK) #define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit33_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit33_SHIFT (8U) /*! MapBit33 - map bit[33] from [Blue, Green, Red] or from TSig[11:0]. If MapBit33 in [29..0] => * bit[33] = [Blue, Green, Red]; if MapBit33 in [41..30] => bit[33] in {TSig[11]..TSig[0]}; If * MapBit33=43 => bit[33]=0; if MapBit33=42 => bit[33]=1 */ #define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit33(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_MapBit33_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_MapBit33_MASK) #define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit34_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit34_SHIFT (16U) /*! MapBit34 - map bit[34] from [Blue, Green, Red] or from TSig[11:0]. If MapBit34 in [29..0] => * bit[34] = [Blue, Green, Red]; if MapBit34 in [41..30] => bit[34] in {TSig[11]..TSig[0]}; If * MapBit34=43 => bit[34]=0; if MapBit34=42 => bit[34]=1 */ #define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit34(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_MapBit34_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_MapBit34_MASK) /*! @} */ /*! @name TCON1_MAPBIT3_0_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit0_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit0_Dual_SHIFT (0U) /*! MapBit0_Dual - map bit[0] from [Blue, Green, Red] or from TSig[11:0]. If MapBit0_Dual in [29..0] * => bit[0] = [Blue, Green, Red]; if MapBit0_Dual in [41..30] => bit[0] in {TSig[11]..TSig[0]}; * If MapBit0_Dual=43 => bit[0]=0; if MapBit0_Dual=42 => bit[0]=1 */ #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit0_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit0_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit0_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit1_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit1_Dual_SHIFT (8U) /*! MapBit1_Dual - map bit[1] from [Blue, Green, Red] or from TSig[11:0]. If MapBit1_Dual in [29..0] * => bit[1] = [Blue, Green, Red]; if MapBit1_Dual in [41..30] => bit[1] in {TSig[11]..TSig[0]}; * If MapBit1_Dual=43 => bit[1]=0; if MapBit1_Dual=42 => bit[1]=1 */ #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit1_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit1_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit1_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit2_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit2_Dual_SHIFT (16U) /*! MapBit2_Dual - map bit[2] from [Blue, Green, Red] or from TSig[11:0]. If MapBit2_Dual in [29..0] * => bit[2] = [Blue, Green, Red]; if MapBit2_Dual in [41..30] => bit[2] in {TSig[11]..TSig[0]}; * If MapBit2_Dual=43 => bit[2]=0; if MapBit2_Dual=42 => bit[2]=1 */ #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit2_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit2_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit2_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit3_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit3_Dual_SHIFT (24U) /*! MapBit3_Dual - map bit[3] from [Blue, Green, Red] or from TSig[11:0]. If MapBit3_Dual in [29..0] * => bit[3] = [Blue, Green, Red]; if MapBit3_Dual in [41..30] => bit[3] in {TSig[11]..TSig[0]}; * If MapBit3_Dual=43 => bit[3]=0; if MapBit3_Dual=42 => bit[3]=1 */ #define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit3_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit3_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit3_Dual_MASK) /*! @} */ /*! @name TCON1_MAPBIT7_4_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit4_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit4_Dual_SHIFT (0U) /*! MapBit4_Dual - map bit[4] from [Blue, Green, Red] or from TSig[11:0]. If MapBit4_Dual in [29..0] * => bit[4] = [Blue, Green, Red]; if MapBit4_Dual in [41..30] => bit[4] in {TSig[11]..TSig[0]}; * If MapBit4_Dual=43 => bit[4]=0; if MapBit4_Dual=42 => bit[4]=1 */ #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit4_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit4_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit4_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit5_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit5_Dual_SHIFT (8U) /*! MapBit5_Dual - map bit[5] from [Blue, Green, Red] or from TSig[11:0]. If MapBit5_Dual in [29..0] * => bit[5] = [Blue, Green, Red]; if MapBit5_Dual in [41..30] => bit[5] in {TSig[11]..TSig[0]}; * If MapBit5_Dual=43 => bit[5]=0; if MapBit5_Dual=42 => bit[5]=1 */ #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit5_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit5_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit5_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit6_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit6_Dual_SHIFT (16U) /*! MapBit6_Dual - map bit[6] from [Blue, Green, Red] or from TSig[11:0]. If MapBit6_Dual in [29..0] * => bit[6] = [Blue, Green, Red]; if MapBit6_Dual in [41..30] => bit[6] in {TSig[11]..TSig[0]}; * If MapBit6_Dual=43 => bit[6]=0; if MapBit6_Dual=42 => bit[6]=1 */ #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit6_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit6_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit6_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit7_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit7_Dual_SHIFT (24U) /*! MapBit7_Dual - map bit[7] from [Blue, Green, Red] or from TSig[11:0]. If MapBit7_Dual in [29..0] * => bit[7] = [Blue, Green, Red]; if MapBit7_Dual in [41..30] => bit[7] in {TSig[11]..TSig[0]}; * If MapBit7_Dual=43 => bit[7]=0; if MapBit7_Dual=42 => bit[7]=1 */ #define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit7_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit7_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit7_Dual_MASK) /*! @} */ /*! @name TCON1_MAPBIT11_8_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit8_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit8_Dual_SHIFT (0U) /*! MapBit8_Dual - map bit[8] from [Blue, Green, Red] or from TSig[11:0]. If MapBit8_Dual in [29..0] * => bit[8] = [Blue, Green, Red]; if MapBit8_Dual in [41..30] => bit[8] in {TSig[11]..TSig[0]}; * If MapBit8_Dual=43 => bit[8]=0; if MapBit8_Dual=42 => bit[8]=1 */ #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit8_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit8_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit8_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit9_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit9_Dual_SHIFT (8U) /*! MapBit9_Dual - map bit[9] from [Blue, Green, Red] or from TSig[11:0]. If MapBit9_Dual in [29..0] * => bit[9] = [Blue, Green, Red]; if MapBit9_Dual in [41..30] => bit[9] in {TSig[11]..TSig[0]}; * If MapBit9_Dual=43 => bit[9]=0; if MapBit9_Dual=42 => bit[9]=1 */ #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit9_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit9_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit9_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit10_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit10_Dual_SHIFT (16U) /*! MapBit10_Dual - map bit[10] from [Blue, Green, Red] or from TSig[11:0]. If MapBit10_Dual in * [29..0] => bit[10] = [Blue, Green, Red]; if MapBit10_Dual in [41..30] => bit[10] in * {TSig[11]..TSig[0]}; If MapBit10_Dual=43 => bit[10]=0; if MapBit10_Dual=42 => bit[10]=1 */ #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit10_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit10_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit10_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit11_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit11_Dual_SHIFT (24U) /*! MapBit11_Dual - map bit[11] from [Blue, Green, Red] or from TSig[11:0]. If MapBit11_Dual in * [29..0] => bit[11] = [Blue, Green, Red]; if MapBit11_Dual in [41..30] => bit[11] in * {TSig[11]..TSig[0]}; If MapBit11_Dual=43 => bit[11]=0; if MapBit11_Dual=42 => bit[11]=1 */ #define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit11_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit11_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit11_Dual_MASK) /*! @} */ /*! @name TCON1_MAPBIT15_12_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit12_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit12_Dual_SHIFT (0U) /*! MapBit12_Dual - map bit[12] from [Blue, Green, Red] or from TSig[11:0]. If MapBit12_Dual in * [29..0] => bit[12] = [Blue, Green, Red]; if MapBit12_Dual in [41..30] => bit[12] in * {TSig[11]..TSig[0]}; If MapBit12_Dual=43 => bit[12]=0; if MapBit12_Dual=42 => bit[12]=1 */ #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit12_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit12_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit12_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit13_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit13_Dual_SHIFT (8U) /*! MapBit13_Dual - map bit[13] from [Blue, Green, Red] or from TSig[11:0]. If MapBit13_Dual in * [29..0] => bit[13] = [Blue, Green, Red]; if MapBit13_Dual in [41..30] => bit[13] in * {TSig[11]..TSig[0]}; If MapBit13_Dual=43 => bit[13]=0; if MapBit13_Dual=42 => bit[13]=1 */ #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit13_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit13_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit13_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit14_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit14_Dual_SHIFT (16U) /*! MapBit14_Dual - map bit[14] from [Blue, Green, Red] or from TSig[11:0]. If MapBit14_Dual in * [29..0] => bit[14] = [Blue, Green, Red]; if MapBit14_Dual in [41..30] => bit[14] in * {TSig[11]..TSig[0]}; If MapBit14_Dual=43 => bit[14]=0; if MapBit14_Dual=42 => bit[14]=1 */ #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit14_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit14_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit14_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit15_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit15_Dual_SHIFT (24U) /*! MapBit15_Dual - map bit[15] from [Blue, Green, Red] or from TSig[11:0]. If MapBit15_Dual in * [29..0] => bit[15] = [Blue, Green, Red]; if MapBit15_Dual in [41..30] => bit[15] in * {TSig[11]..TSig[0]}; If MapBit15_Dual=43 => bit[15]=0; if MapBit15_Dual=42 => bit[15]=1 */ #define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit15_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit15_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit15_Dual_MASK) /*! @} */ /*! @name TCON1_MAPBIT19_16_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit16_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit16_Dual_SHIFT (0U) /*! MapBit16_Dual - map bit[16] from [Blue, Green, Red] or from TSig[11:0]. If MapBit16_Dual in * [29..0] => bit[16] = [Blue, Green, Red]; if MapBit16_Dual in [41..30] => bit[16] in * {TSig[11]..TSig[0]}; If MapBit16_Dual=43 => bit[16]=0; if MapBit16_Dual=42 => bit[16]=1 */ #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit16_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit16_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit16_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit17_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit17_Dual_SHIFT (8U) /*! MapBit17_Dual - map bit[17] from [Blue, Green, Red] or from TSig[11:0]. If MapBit17_Dual in * [29..0] => bit[17] = [Blue, Green, Red]; if MapBit17_Dual in [41..30] => bit[17] in * {TSig[11]..TSig[0]}; If MapBit17_Dual=43 => bit[17]=0; if MapBit17_Dual=42 => bit[17]=1 */ #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit17_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit17_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit17_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit18_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit18_Dual_SHIFT (16U) /*! MapBit18_Dual - map bit[18] from [Blue, Green, Red] or from TSig[11:0]. If MapBit18_Dual in * [29..0] => bit[18] = [Blue, Green, Red]; if MapBit18_Dual in [41..30] => bit[18] in * {TSig[11]..TSig[0]}; If MapBit18_Dual=43 => bit[18]=0; if MapBit18_Dual=42 => bit[18]=1 */ #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit18_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit18_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit18_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit19_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit19_Dual_SHIFT (24U) /*! MapBit19_Dual - map bit[19] from [Blue, Green, Red] or from TSig[11:0]. If MapBit19_Dual in * [29..0] => bit[19] = [Blue, Green, Red]; if MapBit19_Dual in [41..30] => bit[19] in * {TSig[11]..TSig[0]}; If MapBit19_Dual=43 => bit[19]=0; if MapBit19_Dual=42 => bit[19]=1 */ #define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit19_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit19_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit19_Dual_MASK) /*! @} */ /*! @name TCON1_MAPBIT23_20_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit20_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit20_Dual_SHIFT (0U) /*! MapBit20_Dual - map bit[20] from [Blue, Green, Red] or from TSig[11:0]. If MapBit20_Dual in * [29..0] => bit[20] = [Blue, Green, Red]; if MapBit20_Dual in [41..30] => bit[20] in * {TSig[11]..TSig[0]}; If MapBit20_Dual=43 => bit[20]=0; if MapBit20_Dual=42 => bit[20]=1 */ #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit20_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit20_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit20_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit21_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit21_Dual_SHIFT (8U) /*! MapBit21_Dual - map bit[21] from [Blue, Green, Red] or from TSig[11:0]. If MapBit21_Dual in * [29..0] => bit[21] = [Blue, Green, Red]; if MapBit21_Dual in [41..30] => bit[21] in * {TSig[11]..TSig[0]}; If MapBit21_Dual=43 => bit[21]=0; if MapBit21_Dual=42 => bit[21]=1 */ #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit21_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit21_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit21_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit22_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit22_Dual_SHIFT (16U) /*! MapBit22_Dual - map bit[22] from [Blue, Green, Red] or from TSig[11:0]. If MapBit22_Dual in * [29..0] => bit[22] = [Blue, Green, Red]; if MapBit22_Dual in [41..30] => bit[22] in * {TSig[11]..TSig[0]}; If MapBit22_Dual=43 => bit[22]=0; if MapBit22_Dual=42 => bit[22]=1 */ #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit22_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit22_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit22_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit23_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit23_Dual_SHIFT (24U) /*! MapBit23_Dual - map bit[23] from [Blue, Green, Red] or from TSig[11:0]. If MapBit23_Dual in * [29..0] => bit[23] = [Blue, Green, Red]; if MapBit23_Dual in [41..30] => bit[23] in * {TSig[11]..TSig[0]}; If MapBit23_Dual=43 => bit[23]=0; if MapBit23_Dual=42 => bit[23]=1 */ #define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit23_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit23_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit23_Dual_MASK) /*! @} */ /*! @name TCON1_MAPBIT27_24_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit24_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit24_Dual_SHIFT (0U) /*! MapBit24_Dual - map bit[24] from [Blue, Green, Red] or from TSig[11:0]. If MapBit24_Dual in * [29..0] => bit[24] = [Blue, Green, Red]; if MapBit24_Dual in [41..30] => bit[24] in * {TSig[11]..TSig[0]}; If MapBit24_Dual=43 => bit[24]=0; if MapBit24_Dual=42 => bit[24]=1 */ #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit24_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit24_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit24_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit25_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit25_Dual_SHIFT (8U) /*! MapBit25_Dual - map bit[25] from [Blue, Green, Red] or from TSig[11:0]. If MapBit25_Dual in * [29..0] => bit[25] = [Blue, Green, Red]; if MapBit25_Dual in [41..30] => bit[25] in * {TSig[11]..TSig[0]}; If MapBit25_Dual=43 => bit[25]=0; if MapBit25_Dual=42 => bit[25]=1 */ #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit25_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit25_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit25_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit26_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit26_Dual_SHIFT (16U) /*! MapBit26_Dual - map bit[26] from [Blue, Green, Red] or from TSig[11:0]. If MapBit26_Dual in * [29..0] => bit[26] = [Blue, Green, Red]; if MapBit26_Dual in [41..30] => bit[26] in * {TSig[11]..TSig[0]}; If MapBit26_Dual=43 => bit[26]=0; if MapBit26_Dual=42 => bit[26]=1 */ #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit26_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit26_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit26_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit27_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit27_Dual_SHIFT (24U) /*! MapBit27_Dual - map bit[27] from [Blue, Green, Red] or from TSig[11:0]. If MapBit27_Dual in * [29..0] => bit[27] = [Blue, Green, Red]; if MapBit27_Dual in [41..30] => bit[27] in * {TSig[11]..TSig[0]}; If MapBit27_Dual=43 => bit[27]=0; if MapBit27_Dual=42 => bit[27]=1 */ #define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit27_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit27_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit27_Dual_MASK) /*! @} */ /*! @name TCON1_MAPBIT31_28_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit28_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit28_Dual_SHIFT (0U) /*! MapBit28_Dual - map bit[28] from [Blue, Green, Red] or from TSig[11:0]. If MapBit28_Dual in * [29..0] => bit[28] = [Blue, Green, Red]; if MapBit28_Dual in [41..30] => bit[28] in * {TSig[11]..TSig[0]}; If MapBit28_Dual=43 => bit[28]=0; if MapBit28_Dual=42 => bit[28]=1 */ #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit28_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit28_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit28_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit29_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit29_Dual_SHIFT (8U) /*! MapBit29_Dual - map bit[29] from [Blue, Green, Red] or from TSig[11:0]. If MapBit29_Dual in * [29..0] => bit[29] = [Blue, Green, Red]; if MapBit29_Dual in [41..30] => bit[29] in * {TSig[11]..TSig[0]}; If MapBit29_Dual=43 => bit[29]=0; if MapBit29_Dual=42 => bit[29]=1 */ #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit29_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit29_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit29_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit30_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit30_Dual_SHIFT (16U) /*! MapBit30_Dual - map bit[30] from [Blue, Green, Red] or from TSig[11:0]. If MapBit30_Dual in * [29..0] => bit[30] = [Blue, Green, Red]; if MapBit30_Dual in [41..30] => bit[30] in * {TSig[11]..TSig[0]}; If MapBit30_Dual=43 => bit[30]=0; if MapBit30_Dual=42 => bit[30]=1 */ #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit30_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit30_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit30_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit31_Dual_MASK (0x3F000000U) #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit31_Dual_SHIFT (24U) /*! MapBit31_Dual - map bit[31] from [Blue, Green, Red] or from TSig[11:0]. If MapBit31_Dual in * [29..0] => bit[31] = [Blue, Green, Red]; if MapBit31_Dual in [41..30] => bit[31] in * {TSig[11]..TSig[0]}; If MapBit31_Dual=43 => bit[31]=0; if MapBit31_Dual=42 => bit[31]=1 */ #define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit31_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit31_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit31_Dual_MASK) /*! @} */ /*! @name TCON1_MAPBIT34_32_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 2nd channel */ /*! @{ */ #define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit32_Dual_MASK (0x3FU) #define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit32_Dual_SHIFT (0U) /*! MapBit32_Dual - map bit[32] from [Blue, Green, Red] or from TSig[11:0]. If MapBit32_Dual in * [29..0] => bit[32] = [Blue, Green, Red]; if MapBit32_Dual in [41..30] => bit[32] in * {TSig[11]..TSig[0]}; If MapBit32_Dual=43 => bit[32]=0; if MapBit32_Dual=42 => bit[32]=1 */ #define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit32_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit32_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit32_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit33_Dual_MASK (0x3F00U) #define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit33_Dual_SHIFT (8U) /*! MapBit33_Dual - map bit[33] from [Blue, Green, Red] or from TSig[11:0]. If MapBit33_Dual in * [29..0] => bit[33] = [Blue, Green, Red]; if MapBit33_Dual in [41..30] => bit[33] in * {TSig[11]..TSig[0]}; If MapBit33_Dual=43 => bit[33]=0; if MapBit33_Dual=42 => bit[33]=1 */ #define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit33_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit33_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit33_Dual_MASK) #define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit34_Dual_MASK (0x3F0000U) #define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit34_Dual_SHIFT (16U) /*! MapBit34_Dual - map bit[34] from [Blue, Green, Red] or from TSig[11:0]. If MapBit34_Dual in * [29..0] => bit[34] = [Blue, Green, Red]; if MapBit34_Dual in [41..30] => bit[34] in * {TSig[11]..TSig[0]}; If MapBit34_Dual=43 => bit[34]=0; if MapBit34_Dual=42 => bit[34]=1 */ #define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit34_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit34_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit34_Dual_MASK) /*! @} */ /*! @name TCON1_SPG0POSON - Sync pulse generator 0, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_Y0_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_Y0_SHIFT (0U) /*! SPGPSON_Y0 - Y scan position */ #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_Y0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_Y0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_Y0_MASK) #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_FIELD0_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_FIELD0_SHIFT (15U) /*! SPGPSON_FIELD0 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_FIELD0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_FIELD0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_FIELD0_MASK) #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_X0_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_X0_SHIFT (16U) /*! SPGPSON_X0 - X scan position */ #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_X0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_X0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_X0_MASK) #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_TOGGLE0_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_TOGGLE0_SHIFT (31U) /*! SPGPSON_TOGGLE0 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_TOGGLE0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_TOGGLE0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_TOGGLE0_MASK) /*! @} */ /*! @name TCON1_SPG0MASKON - The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG0MASKON_SPGMKON0_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG0MASKON_SPGMKON0_SHIFT (0U) /*! SPGMKON0 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG0MASKON_SPGMKON0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0MASKON_SPGMKON0_SHIFT)) & IRIS_MVPL_TCON1_SPG0MASKON_SPGMKON0_MASK) /*! @} */ /*! @name TCON1_SPG0POSOFF - Sync pulse generator 0, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_Y0_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_Y0_SHIFT (0U) /*! SPGPSOFF_Y0 - Y scan position */ #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_Y0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_Y0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_Y0_MASK) #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT (15U) /*! SPGPSOFF_FIELD0 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_MASK) #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_X0_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_X0_SHIFT (16U) /*! SPGPSOFF_X0 - X scan position */ #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_X0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_X0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_X0_MASK) #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT (31U) /*! SPGPSOFF_TOGGLE0 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK) /*! @} */ /*! @name TCON1_SPG0MASKOFF - The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG0MASKOFF_SPGMKOFF0_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG0MASKOFF_SPGMKOFF0_SHIFT (0U) /*! SPGMKOFF0 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG0MASKOFF_SPGMKOFF0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0MASKOFF_SPGMKOFF0_SHIFT)) & IRIS_MVPL_TCON1_SPG0MASKOFF_SPGMKOFF0_MASK) /*! @} */ /*! @name TCON1_SPG1POSON - Sync pulse generator 1, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_Y1_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_Y1_SHIFT (0U) /*! SPGPSON_Y1 - Y scan position */ #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_Y1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_Y1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_Y1_MASK) #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_FIELD1_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_FIELD1_SHIFT (15U) /*! SPGPSON_FIELD1 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_FIELD1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_FIELD1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_FIELD1_MASK) #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_X1_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_X1_SHIFT (16U) /*! SPGPSON_X1 - X scan position */ #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_X1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_X1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_X1_MASK) #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_TOGGLE1_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_TOGGLE1_SHIFT (31U) /*! SPGPSON_TOGGLE1 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_TOGGLE1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_TOGGLE1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_TOGGLE1_MASK) /*! @} */ /*! @name TCON1_SPG1MASKON - The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG1MASKON_SPGMKON1_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG1MASKON_SPGMKON1_SHIFT (0U) /*! SPGMKON1 - mask bits (1= do not include this bit into position matching) */ #define IRIS_MVPL_TCON1_SPG1MASKON_SPGMKON1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1MASKON_SPGMKON1_SHIFT)) & IRIS_MVPL_TCON1_SPG1MASKON_SPGMKON1_MASK) /*! @} */ /*! @name TCON1_SPG1POSOFF - Sync pulse generator 1, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_Y1_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_Y1_SHIFT (0U) /*! SPGPSOFF_Y1 - Y scan position */ #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_Y1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_Y1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_Y1_MASK) #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT (15U) /*! SPGPSOFF_FIELD1 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_MASK) #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_X1_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_X1_SHIFT (16U) /*! SPGPSOFF_X1 - X scan position */ #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_X1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_X1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_X1_MASK) #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT (31U) /*! SPGPSOFF_TOGGLE1 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK) /*! @} */ /*! @name TCON1_SPG1MASKOFF - The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG1MASKOFF_SPGMKOFF1_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG1MASKOFF_SPGMKOFF1_SHIFT (0U) /*! SPGMKOFF1 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG1MASKOFF_SPGMKOFF1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1MASKOFF_SPGMKOFF1_SHIFT)) & IRIS_MVPL_TCON1_SPG1MASKOFF_SPGMKOFF1_MASK) /*! @} */ /*! @name TCON1_SPG2POSON - Sync pulse generator 2, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_Y2_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_Y2_SHIFT (0U) /*! SPGPSON_Y2 - Y scan position */ #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_Y2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_Y2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_Y2_MASK) #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_FIELD2_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_FIELD2_SHIFT (15U) /*! SPGPSON_FIELD2 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_FIELD2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_FIELD2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_FIELD2_MASK) #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_X2_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_X2_SHIFT (16U) /*! SPGPSON_X2 - X scan position */ #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_X2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_X2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_X2_MASK) #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_TOGGLE2_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_TOGGLE2_SHIFT (31U) /*! SPGPSON_TOGGLE2 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_TOGGLE2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_TOGGLE2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_TOGGLE2_MASK) /*! @} */ /*! @name TCON1_SPG2MASKON - The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG2MASKON_SPGMKON2_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG2MASKON_SPGMKON2_SHIFT (0U) /*! SPGMKON2 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG2MASKON_SPGMKON2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2MASKON_SPGMKON2_SHIFT)) & IRIS_MVPL_TCON1_SPG2MASKON_SPGMKON2_MASK) /*! @} */ /*! @name TCON1_SPG2POSOFF - Sync pulse generator 2, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_Y2_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_Y2_SHIFT (0U) /*! SPGPSOFF_Y2 - Y scan position */ #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_Y2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_Y2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_Y2_MASK) #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT (15U) /*! SPGPSOFF_FIELD2 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_MASK) #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_X2_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_X2_SHIFT (16U) /*! SPGPSOFF_X2 - X scan position */ #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_X2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_X2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_X2_MASK) #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT (31U) /*! SPGPSOFF_TOGGLE2 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK) /*! @} */ /*! @name TCON1_SPG2MASKOFF - The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG2MASKOFF_SPGMKOFF2_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG2MASKOFF_SPGMKOFF2_SHIFT (0U) /*! SPGMKOFF2 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG2MASKOFF_SPGMKOFF2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2MASKOFF_SPGMKOFF2_SHIFT)) & IRIS_MVPL_TCON1_SPG2MASKOFF_SPGMKOFF2_MASK) /*! @} */ /*! @name TCON1_SPG3POSON - Sync pulse generator 3, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_Y3_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_Y3_SHIFT (0U) /*! SPGPSON_Y3 - Y scan position */ #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_Y3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_Y3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_Y3_MASK) #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_FIELD3_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_FIELD3_SHIFT (15U) /*! SPGPSON_FIELD3 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_FIELD3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_FIELD3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_FIELD3_MASK) #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_X3_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_X3_SHIFT (16U) /*! SPGPSON_X3 - X scan position */ #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_X3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_X3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_X3_MASK) #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_TOGGLE3_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_TOGGLE3_SHIFT (31U) /*! SPGPSON_TOGGLE3 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_TOGGLE3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_TOGGLE3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_TOGGLE3_MASK) /*! @} */ /*! @name TCON1_SPG3MASKON - The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG3MASKON_SPGMKON3_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG3MASKON_SPGMKON3_SHIFT (0U) /*! SPGMKON3 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG3MASKON_SPGMKON3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3MASKON_SPGMKON3_SHIFT)) & IRIS_MVPL_TCON1_SPG3MASKON_SPGMKON3_MASK) /*! @} */ /*! @name TCON1_SPG3POSOFF - Sync pulse generator 3, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_Y3_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_Y3_SHIFT (0U) /*! SPGPSOFF_Y3 - Y scan position */ #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_Y3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_Y3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_Y3_MASK) #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT (15U) /*! SPGPSOFF_FIELD3 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_MASK) #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_X3_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_X3_SHIFT (16U) /*! SPGPSOFF_X3 - X scan position */ #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_X3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_X3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_X3_MASK) #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT (31U) /*! SPGPSOFF_TOGGLE3 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK) /*! @} */ /*! @name TCON1_SPG3MASKOFF - The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG3MASKOFF_SPGMKOFF3_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG3MASKOFF_SPGMKOFF3_SHIFT (0U) /*! SPGMKOFF3 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG3MASKOFF_SPGMKOFF3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3MASKOFF_SPGMKOFF3_SHIFT)) & IRIS_MVPL_TCON1_SPG3MASKOFF_SPGMKOFF3_MASK) /*! @} */ /*! @name TCON1_SPG4POSON - Sync pulse generator 4, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_Y4_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_Y4_SHIFT (0U) /*! SPGPSON_Y4 - Y scan position */ #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_Y4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_Y4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_Y4_MASK) #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_FIELD4_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_FIELD4_SHIFT (15U) /*! SPGPSON_FIELD4 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_FIELD4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_FIELD4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_FIELD4_MASK) #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_X4_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_X4_SHIFT (16U) /*! SPGPSON_X4 - X scan position */ #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_X4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_X4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_X4_MASK) #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_TOGGLE4_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_TOGGLE4_SHIFT (31U) /*! SPGPSON_TOGGLE4 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_TOGGLE4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_TOGGLE4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_TOGGLE4_MASK) /*! @} */ /*! @name TCON1_SPG4MASKON - The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG4MASKON_SPGMKON4_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG4MASKON_SPGMKON4_SHIFT (0U) /*! SPGMKON4 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG4MASKON_SPGMKON4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4MASKON_SPGMKON4_SHIFT)) & IRIS_MVPL_TCON1_SPG4MASKON_SPGMKON4_MASK) /*! @} */ /*! @name TCON1_SPG4POSOFF - Sync pulse generator 4, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_Y4_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_Y4_SHIFT (0U) /*! SPGPSOFF_Y4 - Y scan position */ #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_Y4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_Y4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_Y4_MASK) #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT (15U) /*! SPGPSOFF_FIELD4 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_MASK) #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_X4_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_X4_SHIFT (16U) /*! SPGPSOFF_X4 - X scan position */ #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_X4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_X4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_X4_MASK) #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT (31U) /*! SPGPSOFF_TOGGLE4 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK) /*! @} */ /*! @name TCON1_SPG4MASKOFF - The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG4MASKOFF_SPGMKOFF4_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG4MASKOFF_SPGMKOFF4_SHIFT (0U) /*! SPGMKOFF4 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG4MASKOFF_SPGMKOFF4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4MASKOFF_SPGMKOFF4_SHIFT)) & IRIS_MVPL_TCON1_SPG4MASKOFF_SPGMKOFF4_MASK) /*! @} */ /*! @name TCON1_SPG5POSON - Sync pulse generator 5, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_Y5_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_Y5_SHIFT (0U) /*! SPGPSON_Y5 - Y scan position */ #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_Y5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_Y5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_Y5_MASK) #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_FIELD5_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_FIELD5_SHIFT (15U) /*! SPGPSON_FIELD5 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_FIELD5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_FIELD5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_FIELD5_MASK) #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_X5_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_X5_SHIFT (16U) /*! SPGPSON_X5 - X scan position */ #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_X5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_X5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_X5_MASK) #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_TOGGLE5_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_TOGGLE5_SHIFT (31U) /*! SPGPSON_TOGGLE5 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_TOGGLE5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_TOGGLE5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_TOGGLE5_MASK) /*! @} */ /*! @name TCON1_SPG5MASKON - The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG5MASKON_SPGMKON5_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG5MASKON_SPGMKON5_SHIFT (0U) /*! SPGMKON5 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG5MASKON_SPGMKON5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5MASKON_SPGMKON5_SHIFT)) & IRIS_MVPL_TCON1_SPG5MASKON_SPGMKON5_MASK) /*! @} */ /*! @name TCON1_SPG5POSOFF - Sync pulse generator 5, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_Y5_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_Y5_SHIFT (0U) /*! SPGPSOFF_Y5 - Y scan position */ #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_Y5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_Y5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_Y5_MASK) #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT (15U) /*! SPGPSOFF_FIELD5 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_MASK) #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_X5_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_X5_SHIFT (16U) /*! SPGPSOFF_X5 - X scan position */ #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_X5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_X5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_X5_MASK) #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT (31U) /*! SPGPSOFF_TOGGLE5 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK) /*! @} */ /*! @name TCON1_SPG5MASKOFF - The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG5MASKOFF_SPGMKOFF5_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG5MASKOFF_SPGMKOFF5_SHIFT (0U) /*! SPGMKOFF5 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG5MASKOFF_SPGMKOFF5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5MASKOFF_SPGMKOFF5_SHIFT)) & IRIS_MVPL_TCON1_SPG5MASKOFF_SPGMKOFF5_MASK) /*! @} */ /*! @name TCON1_SPG6POSON - Sync pulse generator 6, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_Y6_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_Y6_SHIFT (0U) /*! SPGPSON_Y6 - Y scan position */ #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_Y6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_Y6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_Y6_MASK) #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_FIELD6_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_FIELD6_SHIFT (15U) /*! SPGPSON_FIELD6 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_FIELD6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_FIELD6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_FIELD6_MASK) #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_X6_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_X6_SHIFT (16U) /*! SPGPSON_X6 - X scan position */ #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_X6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_X6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_X6_MASK) #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_TOGGLE6_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_TOGGLE6_SHIFT (31U) /*! SPGPSON_TOGGLE6 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_TOGGLE6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_TOGGLE6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_TOGGLE6_MASK) /*! @} */ /*! @name TCON1_SPG6MASKON - The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG6MASKON_SPGMKON6_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG6MASKON_SPGMKON6_SHIFT (0U) /*! SPGMKON6 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG6MASKON_SPGMKON6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6MASKON_SPGMKON6_SHIFT)) & IRIS_MVPL_TCON1_SPG6MASKON_SPGMKON6_MASK) /*! @} */ /*! @name TCON1_SPG6POSOFF - Sync pulse generator 6, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_Y6_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_Y6_SHIFT (0U) /*! SPGPSOFF_Y6 - Y scan position */ #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_Y6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_Y6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_Y6_MASK) #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT (15U) /*! SPGPSOFF_FIELD6 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_MASK) #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_X6_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_X6_SHIFT (16U) /*! SPGPSOFF_X6 - X scan position */ #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_X6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_X6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_X6_MASK) #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT (31U) /*! SPGPSOFF_TOGGLE6 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK) /*! @} */ /*! @name TCON1_SPG6MASKOFF - The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG6MASKOFF_SPGMKOFF6_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG6MASKOFF_SPGMKOFF6_SHIFT (0U) /*! SPGMKOFF6 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG6MASKOFF_SPGMKOFF6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6MASKOFF_SPGMKOFF6_SHIFT)) & IRIS_MVPL_TCON1_SPG6MASKOFF_SPGMKOFF6_MASK) /*! @} */ /*! @name TCON1_SPG7POSON - Sync pulse generator 7, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_Y7_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_Y7_SHIFT (0U) /*! SPGPSON_Y7 - Y scan position */ #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_Y7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_Y7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_Y7_MASK) #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_FIELD7_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_FIELD7_SHIFT (15U) /*! SPGPSON_FIELD7 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_FIELD7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_FIELD7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_FIELD7_MASK) #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_X7_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_X7_SHIFT (16U) /*! SPGPSON_X7 - X scan position */ #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_X7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_X7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_X7_MASK) #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_TOGGLE7_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_TOGGLE7_SHIFT (31U) /*! SPGPSON_TOGGLE7 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_TOGGLE7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_TOGGLE7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_TOGGLE7_MASK) /*! @} */ /*! @name TCON1_SPG7MASKON - The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG7MASKON_SPGMKON7_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG7MASKON_SPGMKON7_SHIFT (0U) /*! SPGMKON7 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG7MASKON_SPGMKON7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7MASKON_SPGMKON7_SHIFT)) & IRIS_MVPL_TCON1_SPG7MASKON_SPGMKON7_MASK) /*! @} */ /*! @name TCON1_SPG7POSOFF - Sync pulse generator 7, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_Y7_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_Y7_SHIFT (0U) /*! SPGPSOFF_Y7 - Y scan position */ #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_Y7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_Y7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_Y7_MASK) #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT (15U) /*! SPGPSOFF_FIELD7 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_MASK) #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_X7_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_X7_SHIFT (16U) /*! SPGPSOFF_X7 - X scan position */ #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_X7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_X7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_X7_MASK) #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT (31U) /*! SPGPSOFF_TOGGLE7 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK) /*! @} */ /*! @name TCON1_SPG7MASKOFF - The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG7MASKOFF_SPGMKOFF7_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG7MASKOFF_SPGMKOFF7_SHIFT (0U) /*! SPGMKOFF7 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG7MASKOFF_SPGMKOFF7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7MASKOFF_SPGMKOFF7_SHIFT)) & IRIS_MVPL_TCON1_SPG7MASKOFF_SPGMKOFF7_MASK) /*! @} */ /*! @name TCON1_SPG8POSON - Sync pulse generator 8, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_Y8_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_Y8_SHIFT (0U) /*! SPGPSON_Y8 - Y scan position */ #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_Y8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_Y8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_Y8_MASK) #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_FIELD8_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_FIELD8_SHIFT (15U) /*! SPGPSON_FIELD8 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_FIELD8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_FIELD8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_FIELD8_MASK) #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_X8_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_X8_SHIFT (16U) /*! SPGPSON_X8 - X scan position */ #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_X8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_X8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_X8_MASK) #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_TOGGLE8_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_TOGGLE8_SHIFT (31U) /*! SPGPSON_TOGGLE8 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_TOGGLE8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_TOGGLE8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_TOGGLE8_MASK) /*! @} */ /*! @name TCON1_SPG8MASKON - The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG8MASKON_SPGMKON8_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG8MASKON_SPGMKON8_SHIFT (0U) /*! SPGMKON8 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG8MASKON_SPGMKON8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8MASKON_SPGMKON8_SHIFT)) & IRIS_MVPL_TCON1_SPG8MASKON_SPGMKON8_MASK) /*! @} */ /*! @name TCON1_SPG8POSOFF - Sync pulse generator 8, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_Y8_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_Y8_SHIFT (0U) /*! SPGPSOFF_Y8 - Y scan position */ #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_Y8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_Y8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_Y8_MASK) #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT (15U) /*! SPGPSOFF_FIELD8 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_MASK) #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_X8_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_X8_SHIFT (16U) /*! SPGPSOFF_X8 - X scan position */ #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_X8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_X8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_X8_MASK) #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT (31U) /*! SPGPSOFF_TOGGLE8 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK) /*! @} */ /*! @name TCON1_SPG8MASKOFF - The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG8MASKOFF_SPGMKOFF8_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG8MASKOFF_SPGMKOFF8_SHIFT (0U) /*! SPGMKOFF8 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG8MASKOFF_SPGMKOFF8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8MASKOFF_SPGMKOFF8_SHIFT)) & IRIS_MVPL_TCON1_SPG8MASKOFF_SPGMKOFF8_MASK) /*! @} */ /*! @name TCON1_SPG9POSON - Sync pulse generator 9, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_Y9_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_Y9_SHIFT (0U) /*! SPGPSON_Y9 - Y scan position */ #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_Y9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_Y9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_Y9_MASK) #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_FIELD9_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_FIELD9_SHIFT (15U) /*! SPGPSON_FIELD9 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_FIELD9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_FIELD9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_FIELD9_MASK) #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_X9_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_X9_SHIFT (16U) /*! SPGPSON_X9 - X scan position */ #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_X9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_X9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_X9_MASK) #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_TOGGLE9_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_TOGGLE9_SHIFT (31U) /*! SPGPSON_TOGGLE9 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_TOGGLE9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_TOGGLE9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_TOGGLE9_MASK) /*! @} */ /*! @name TCON1_SPG9MASKON - The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG9MASKON_SPGMKON9_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG9MASKON_SPGMKON9_SHIFT (0U) /*! SPGMKON9 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG9MASKON_SPGMKON9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9MASKON_SPGMKON9_SHIFT)) & IRIS_MVPL_TCON1_SPG9MASKON_SPGMKON9_MASK) /*! @} */ /*! @name TCON1_SPG9POSOFF - Sync pulse generator 9, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_Y9_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_Y9_SHIFT (0U) /*! SPGPSOFF_Y9 - Y scan position */ #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_Y9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_Y9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_Y9_MASK) #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT (15U) /*! SPGPSOFF_FIELD9 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_MASK) #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_X9_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_X9_SHIFT (16U) /*! SPGPSOFF_X9 - X scan position */ #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_X9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_X9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_X9_MASK) #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT (31U) /*! SPGPSOFF_TOGGLE9 - Toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK) /*! @} */ /*! @name TCON1_SPG9MASKOFF - The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG9MASKOFF_SPGMKOFF9_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG9MASKOFF_SPGMKOFF9_SHIFT (0U) /*! SPGMKOFF9 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG9MASKOFF_SPGMKOFF9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9MASKOFF_SPGMKOFF9_SHIFT)) & IRIS_MVPL_TCON1_SPG9MASKOFF_SPGMKOFF9_MASK) /*! @} */ /*! @name TCON1_SPG10POSON - Sync pulse generator 10, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_Y10_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_Y10_SHIFT (0U) /*! SPGPSON_Y10 - Y scan position */ #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_Y10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_Y10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_Y10_MASK) #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_FIELD10_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_FIELD10_SHIFT (15U) /*! SPGPSON_FIELD10 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_FIELD10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_FIELD10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_FIELD10_MASK) #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT (16U) /*! SPGPSON_X10 - X scan position */ #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK) #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_TOGGLE10_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_TOGGLE10_SHIFT (31U) /*! SPGPSON_TOGGLE10 - toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_TOGGLE10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_TOGGLE10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_TOGGLE10_MASK) /*! @} */ /*! @name TCON1_SPG10MASKON - The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG10MASKON_SPGMKON10_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG10MASKON_SPGMKON10_SHIFT (0U) /*! SPGMKON10 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG10MASKON_SPGMKON10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10MASKON_SPGMKON10_SHIFT)) & IRIS_MVPL_TCON1_SPG10MASKON_SPGMKON10_MASK) /*! @} */ /*! @name TCON1_SPG10POSOFF - Sync pulse generator 10, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_Y10_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_Y10_SHIFT (0U) /*! SPGPSOFF_Y10 - Y scan position */ #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_Y10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_Y10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_Y10_MASK) #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT (15U) /*! SPGPSOFF_FIELD10 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_MASK) #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_X10_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_X10_SHIFT (16U) /*! SPGPSOFF_X10 - X scan position */ #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_X10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_X10_MASK) #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT (31U) /*! SPGPSOFF_TOGGLE10 - toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK) /*! @} */ /*! @name TCON1_SPG10MASKOFF - The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG10MASKOFF_SPGMKOFF10_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG10MASKOFF_SPGMKOFF10_SHIFT (0U) /*! SPGMKOFF10 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG10MASKOFF_SPGMKOFF10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10MASKOFF_SPGMKOFF10_SHIFT)) & IRIS_MVPL_TCON1_SPG10MASKOFF_SPGMKOFF10_MASK) /*! @} */ /*! @name TCON1_SPG11POSON - Sync pulse generator 11, 'Switch on' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_Y11_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_Y11_SHIFT (0U) /*! SPGPSON_Y11 - Y scan position */ #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_Y11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_Y11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_Y11_MASK) #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_FIELD11_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_FIELD11_SHIFT (15U) /*! SPGPSON_FIELD11 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_FIELD11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_FIELD11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_FIELD11_MASK) #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_X11_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_X11_SHIFT (16U) /*! SPGPSON_X11 - X scan position */ #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_X11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_X11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_X11_MASK) #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_TOGGLE11_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_TOGGLE11_SHIFT (31U) /*! SPGPSON_TOGGLE11 - toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_TOGGLE11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_TOGGLE11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_TOGGLE11_MASK) /*! @} */ /*! @name TCON1_SPG11MASKON - The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG11MASKON_SPGMKON11_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG11MASKON_SPGMKON11_SHIFT (0U) /*! SPGMKON11 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG11MASKON_SPGMKON11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11MASKON_SPGMKON11_SHIFT)) & IRIS_MVPL_TCON1_SPG11MASKON_SPGMKON11_MASK) /*! @} */ /*! @name TCON1_SPG11POSOFF - Sync pulse generator 11, 'Switch off' position */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_Y11_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_Y11_SHIFT (0U) /*! SPGPSOFF_Y11 - Y scan position */ #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_Y11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_Y11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_Y11_MASK) #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_MASK (0x8000U) #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT (15U) /*! SPGPSOFF_FIELD11 - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_MASK) #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_X11_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_X11_SHIFT (16U) /*! SPGPSOFF_X11 - X scan position */ #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_X11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_X11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_X11_MASK) #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT (31U) /*! SPGPSOFF_TOGGLE11 - toggle enable: 0b=disable, 1b=enable */ #define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK) /*! @} */ /*! @name TCON1_SPG11MASKOFF - The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11 */ /*! @{ */ #define IRIS_MVPL_TCON1_SPG11MASKOFF_SPGMKOFF11_MASK (0x7FFFFFFFU) #define IRIS_MVPL_TCON1_SPG11MASKOFF_SPGMKOFF11_SHIFT (0U) /*! SPGMKOFF11 - Mask bits: 0b=Include this bit in position matching, 1b= Do not include this bit in position matching */ #define IRIS_MVPL_TCON1_SPG11MASKOFF_SPGMKOFF11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11MASKOFF_SPGMKOFF11_SHIFT)) & IRIS_MVPL_TCON1_SPG11MASKOFF_SPGMKOFF11_MASK) /*! @} */ /*! @name TCON1_SMX0SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S0_SHIFT (0U) /*! SMX0SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S1_SHIFT (3U) /*! SMX0SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S2_SHIFT (6U) /*! SMX0SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S3_SHIFT (9U) /*! SMX0SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S4_SHIFT (12U) /*! SMX0SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX0FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX0FCTTABLE_SMXFCT0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX0FCTTABLE_SMXFCT0_SHIFT (0U) /*! SMXFCT0 - Sync mixer 0 function table */ #define IRIS_MVPL_TCON1_SMX0FCTTABLE_SMXFCT0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0FCTTABLE_SMXFCT0_SHIFT)) & IRIS_MVPL_TCON1_SMX0FCTTABLE_SMXFCT0_MASK) /*! @} */ /*! @name TCON1_SMX1SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S0_SHIFT (0U) /*! SMX1SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S1_SHIFT (3U) /*! SMX1SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S2_SHIFT (6U) /*! SMX1SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S3_SHIFT (9U) /*! SMX1SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S4_SHIFT (12U) /*! SMX1SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX1FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX1FCTTABLE_SMXFCT1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX1FCTTABLE_SMXFCT1_SHIFT (0U) /*! SMXFCT1 - Sync mixer 1 function table */ #define IRIS_MVPL_TCON1_SMX1FCTTABLE_SMXFCT1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1FCTTABLE_SMXFCT1_SHIFT)) & IRIS_MVPL_TCON1_SMX1FCTTABLE_SMXFCT1_MASK) /*! @} */ /*! @name TCON1_SMX2SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S0_SHIFT (0U) /*! SMX2SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S1_SHIFT (3U) /*! SMX2SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S2_SHIFT (6U) /*! SMX2SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S3_SHIFT (9U) /*! SMX2SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S4_SHIFT (12U) /*! SMX2SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX2FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX2FCTTABLE_SMXFCT2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX2FCTTABLE_SMXFCT2_SHIFT (0U) /*! SMXFCT2 - Sync mixer 2 function table */ #define IRIS_MVPL_TCON1_SMX2FCTTABLE_SMXFCT2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2FCTTABLE_SMXFCT2_SHIFT)) & IRIS_MVPL_TCON1_SMX2FCTTABLE_SMXFCT2_MASK) /*! @} */ /*! @name TCON1_SMX3SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S0_SHIFT (0U) /*! SMX3SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S1_SHIFT (3U) /*! SMX3SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S2_SHIFT (6U) /*! SMX3SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S3_SHIFT (9U) /*! SMX3SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S4_SHIFT (12U) /*! SMX3SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX3FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX3FCTTABLE_SMXFCT3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX3FCTTABLE_SMXFCT3_SHIFT (0U) /*! SMXFCT3 - Sync mixer 3 function table */ #define IRIS_MVPL_TCON1_SMX3FCTTABLE_SMXFCT3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3FCTTABLE_SMXFCT3_SHIFT)) & IRIS_MVPL_TCON1_SMX3FCTTABLE_SMXFCT3_MASK) /*! @} */ /*! @name TCON1_SMX4SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S0_SHIFT (0U) /*! SMX4SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S1_SHIFT (3U) /*! SMX4SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S2_SHIFT (6U) /*! SMX4SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S3_SHIFT (9U) /*! SMX4SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S4_SHIFT (12U) /*! SMX4SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX4FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX4FCTTABLE_SMXFCT4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX4FCTTABLE_SMXFCT4_SHIFT (0U) /*! SMXFCT4 - Sync mixer 4 function table */ #define IRIS_MVPL_TCON1_SMX4FCTTABLE_SMXFCT4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4FCTTABLE_SMXFCT4_SHIFT)) & IRIS_MVPL_TCON1_SMX4FCTTABLE_SMXFCT4_MASK) /*! @} */ /*! @name TCON1_SMX5SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S0_SHIFT (0U) /*! SMX5SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S1_SHIFT (3U) /*! SMX5SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S2_SHIFT (6U) /*! SMX5SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S3_SHIFT (9U) /*! SMX5SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S4_SHIFT (12U) /*! SMX5SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG0 .. SPG5 */ #define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX5FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX5FCTTABLE_SMXFCT5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX5FCTTABLE_SMXFCT5_SHIFT (0U) /*! SMXFCT5 - Sync mixer 5 function table */ #define IRIS_MVPL_TCON1_SMX5FCTTABLE_SMXFCT5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5FCTTABLE_SMXFCT5_SHIFT)) & IRIS_MVPL_TCON1_SMX5FCTTABLE_SMXFCT5_MASK) /*! @} */ /*! @name TCON1_SMX6SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S0_SHIFT (0U) /*! SMX6SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S1_SHIFT (3U) /*! SMX6SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S2_SHIFT (6U) /*! SMX6SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S3_SHIFT (9U) /*! SMX6SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S4_SHIFT (12U) /*! SMX6SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX6FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX6FCTTABLE_SMXFCT6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX6FCTTABLE_SMXFCT6_SHIFT (0U) /*! SMXFCT6 - Sync mixer 6 function table */ #define IRIS_MVPL_TCON1_SMX6FCTTABLE_SMXFCT6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6FCTTABLE_SMXFCT6_SHIFT)) & IRIS_MVPL_TCON1_SMX6FCTTABLE_SMXFCT6_MASK) /*! @} */ /*! @name TCON1_SMX7SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S0_SHIFT (0U) /*! SMX7SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S1_SHIFT (3U) /*! SMX7SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S2_SHIFT (6U) /*! SMX7SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S3_SHIFT (9U) /*! SMX7SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S4_SHIFT (12U) /*! SMX7SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX7FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX7FCTTABLE_SMXFCT7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX7FCTTABLE_SMXFCT7_SHIFT (0U) /*! SMXFCT7 - Sync mixer 7 function table */ #define IRIS_MVPL_TCON1_SMX7FCTTABLE_SMXFCT7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7FCTTABLE_SMXFCT7_SHIFT)) & IRIS_MVPL_TCON1_SMX7FCTTABLE_SMXFCT7_MASK) /*! @} */ /*! @name TCON1_SMX8SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S0_SHIFT (0U) /*! SMX8SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S1_SHIFT (3U) /*! SMX8SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S2_SHIFT (6U) /*! SMX8SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S3_SHIFT (9U) /*! SMX8SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S4_SHIFT (12U) /*! SMX8SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX8FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX8FCTTABLE_SMXFCT8_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX8FCTTABLE_SMXFCT8_SHIFT (0U) /*! SMXFCT8 - Sync mixer 8 function table */ #define IRIS_MVPL_TCON1_SMX8FCTTABLE_SMXFCT8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8FCTTABLE_SMXFCT8_SHIFT)) & IRIS_MVPL_TCON1_SMX8FCTTABLE_SMXFCT8_MASK) /*! @} */ /*! @name TCON1_SMX9SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S0_SHIFT (0U) /*! SMX9SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S1_SHIFT (3U) /*! SMX9SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S2_SHIFT (6U) /*! SMX9SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S3_SHIFT (9U) /*! SMX9SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S4_SHIFT (12U) /*! SMX9SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX9FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX9FCTTABLE_SMXFCT9_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX9FCTTABLE_SMXFCT9_SHIFT (0U) /*! SMXFCT9 - Sync mixer 9 function table */ #define IRIS_MVPL_TCON1_SMX9FCTTABLE_SMXFCT9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9FCTTABLE_SMXFCT9_SHIFT)) & IRIS_MVPL_TCON1_SMX9FCTTABLE_SMXFCT9_MASK) /*! @} */ /*! @name TCON1_SMX10SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S0_SHIFT (0U) /*! SMX10SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S1_SHIFT (3U) /*! SMX10SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S2_SHIFT (6U) /*! SMX10SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S3_SHIFT (9U) /*! SMX10SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S4_SHIFT (12U) /*! SMX10SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX10FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX10FCTTABLE_SMXFCT10_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX10FCTTABLE_SMXFCT10_SHIFT (0U) /*! SMXFCT10 - Sync mixer 10 function table */ #define IRIS_MVPL_TCON1_SMX10FCTTABLE_SMXFCT10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10FCTTABLE_SMXFCT10_SHIFT)) & IRIS_MVPL_TCON1_SMX10FCTTABLE_SMXFCT10_MASK) /*! @} */ /*! @name TCON1_SMX11SIGS - Selection of input signals of sync mixer */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S0_MASK (0x7U) #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S0_SHIFT (0U) /*! SMX11SIGS_S0 - select 0 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S0_MASK) #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S1_MASK (0x38U) #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S1_SHIFT (3U) /*! SMX11SIGS_S1 - select 1 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S1_MASK) #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S2_MASK (0x1C0U) #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S2_SHIFT (6U) /*! SMX11SIGS_S2 - select 2 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S2_MASK) #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S3_MASK (0xE00U) #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S3_SHIFT (9U) /*! SMX11SIGS_S3 - select 3 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S3_MASK) #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S4_MASK (0x7000U) #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S4_SHIFT (12U) /*! SMX11SIGS_S4 - select 4 000b=constant 0, 001b=sync sequencer output, 010b...111b sync pulse generator SPG6 .. SPG11 */ #define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S4_MASK) /*! @} */ /*! @name TCON1_SMX11FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */ /*! @{ */ #define IRIS_MVPL_TCON1_SMX11FCTTABLE_SMXFCT11_MASK (0xFFFFFFFFU) #define IRIS_MVPL_TCON1_SMX11FCTTABLE_SMXFCT11_SHIFT (0U) /*! SMXFCT11 - Sync mixer 11 function table */ #define IRIS_MVPL_TCON1_SMX11FCTTABLE_SMXFCT11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11FCTTABLE_SMXFCT11_SHIFT)) & IRIS_MVPL_TCON1_SMX11FCTTABLE_SMXFCT11_MASK) /*! @} */ /*! @name TCON1_RESET_OVER_UNFERFLOW - reset status overflow and underflow of both dual channel fifos */ /*! @{ */ #define IRIS_MVPL_TCON1_RESET_OVER_UNFERFLOW_reset_status_MASK (0x1U) #define IRIS_MVPL_TCON1_RESET_OVER_UNFERFLOW_reset_status_SHIFT (0U) /*! reset_status - write a '1' to clear all overflow-Bits and underflow-Bits in Dual_Debug register */ #define IRIS_MVPL_TCON1_RESET_OVER_UNFERFLOW_reset_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_RESET_OVER_UNFERFLOW_reset_status_SHIFT)) & IRIS_MVPL_TCON1_RESET_OVER_UNFERFLOW_reset_status_MASK) /*! @} */ /*! @name TCON1_DUAL_DEBUG - Status of fifo during dual channel operation. They are only available in Split Mode For Debug only */ /*! @{ */ #define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_overflow_MASK (0x1U) #define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_overflow_SHIFT (0U) /*! lower_fifo_overflow - There are more input pixels than output pixels in a line of lower fifo * (too less horizontal blanking or others ...). Once it is set, it remains active until it's reset * on software reset or on Reset_Over_Unferflow/reset_status */ #define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_overflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_overflow_SHIFT)) & IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_overflow_MASK) #define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_underflow_MASK (0x2U) #define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_underflow_SHIFT (1U) /*! lower_fifo_underflow - There are less input pixels than output pixels in a line of lower fifo * (check data_en and split-position or others ...). Once it is set, it remains active until it's * reset on software reset or on Reset_Over_Unferflow/reset_status */ #define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_underflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_underflow_SHIFT)) & IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_underflow_MASK) #define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_overflow_MASK (0x10U) #define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_overflow_SHIFT (4U) /*! upper_fifo_overflow - There are more input pixels than output pixels in a line of upper fifo * (too less horizontal blanking or others ...). Once it is set, it remains active until it's reset * on software reset or on Reset_Over_Unferflow/reset_status */ #define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_overflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_overflow_SHIFT)) & IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_overflow_MASK) #define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_underflow_MASK (0x20U) #define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_underflow_SHIFT (5U) /*! upper_fifo_underflow - There are less input pixels than output pixels in a line of upper fifo * (check data_en and split-position or others ...). Once it is set, it remains active until it's * reset on software reset or on Reset_Over_Unferflow/reset_status */ #define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_underflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_underflow_SHIFT)) & IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_underflow_MASK) /*! @} */ /*! @name SIG1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_SIG1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_LOCKUNLOCK_LockUnlock_SHIFT (0U) /*! LockUnlock - The protection status is changed by writing one of the following key values to this field: * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define IRIS_MVPL_SIG1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_SIG1_LOCKUNLOCK_LockUnlock_MASK) /*! @} */ /*! @name SIG1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define IRIS_MVPL_SIG1_LOCKSTATUS_LockStatus_MASK (0x1U) #define IRIS_MVPL_SIG1_LOCKSTATUS_LockStatus_SHIFT (0U) /*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0). */ #define IRIS_MVPL_SIG1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_SIG1_LOCKSTATUS_LockStatus_MASK) #define IRIS_MVPL_SIG1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U) #define IRIS_MVPL_SIG1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U) /*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active. */ #define IRIS_MVPL_SIG1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_SIG1_LOCKSTATUS_PrivilegeStatus_MASK) #define IRIS_MVPL_SIG1_LOCKSTATUS_FreezeStatus_MASK (0x100U) #define IRIS_MVPL_SIG1_LOCKSTATUS_FreezeStatus_SHIFT (8U) /*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed. */ #define IRIS_MVPL_SIG1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_SIG1_LOCKSTATUS_FreezeStatus_MASK) /*! @} */ /*! @name SIG1_STATICCONTROL - Global configuration shared by all evaluation windows. */ /*! @{ */ #define IRIS_MVPL_SIG1_STATICCONTROL_ShdEn_MASK (0x1U) #define IRIS_MVPL_SIG1_STATICCONTROL_ShdEn_SHIFT (0U) /*! ShdEn - Enables shadow registers for RWS type fields (0 = write through, 1 = shadowed). */ #define IRIS_MVPL_SIG1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_SIG1_STATICCONTROL_ShdEn_MASK) #define IRIS_MVPL_SIG1_STATICCONTROL_ShdLdSel_MASK (0x10U) #define IRIS_MVPL_SIG1_STATICCONTROL_ShdLdSel_SHIFT (4U) /*! ShdLdSel - Source select for events that will load shadow registers into the active configuration. * 0b0..Shadows are loaded at start of frame for each evaluation window for which ShdLdReq has been set. * 0b1..Shadows of all evaluation windows are loaded synchronous to the display stream (shadow load token received on frame input port). */ #define IRIS_MVPL_SIG1_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_SIG1_STATICCONTROL_ShdLdSel_MASK) #define IRIS_MVPL_SIG1_STATICCONTROL_ErrThres_MASK (0xFF0000U) #define IRIS_MVPL_SIG1_STATICCONTROL_ErrThres_SHIFT (16U) /*! ErrThres - Number of frames with signature violation before StsSigError is set for an evaluation window. */ #define IRIS_MVPL_SIG1_STATICCONTROL_ErrThres(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATICCONTROL_ErrThres_SHIFT)) & IRIS_MVPL_SIG1_STATICCONTROL_ErrThres_MASK) #define IRIS_MVPL_SIG1_STATICCONTROL_ErrThresReset_MASK (0xFF000000U) #define IRIS_MVPL_SIG1_STATICCONTROL_ErrThresReset_SHIFT (24U) /*! ErrThresReset - Number of consecutive frames without signature violation before StsSigError is reset for an evaluation window. */ #define IRIS_MVPL_SIG1_STATICCONTROL_ErrThresReset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATICCONTROL_ErrThresReset_SHIFT)) & IRIS_MVPL_SIG1_STATICCONTROL_ErrThresReset_MASK) /*! @} */ /*! @name SIG1_PANICCOLOR - Overlay color for evaluation windows in panic mode. */ /*! @{ */ #define IRIS_MVPL_SIG1_PANICCOLOR_PanicAlpha_MASK (0x80U) #define IRIS_MVPL_SIG1_PANICCOLOR_PanicAlpha_SHIFT (7U) /*! PanicAlpha - Alpha mask bit. */ #define IRIS_MVPL_SIG1_PANICCOLOR_PanicAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_PANICCOLOR_PanicAlpha_SHIFT)) & IRIS_MVPL_SIG1_PANICCOLOR_PanicAlpha_MASK) #define IRIS_MVPL_SIG1_PANICCOLOR_PanicBlue_MASK (0xFF00U) #define IRIS_MVPL_SIG1_PANICCOLOR_PanicBlue_SHIFT (8U) /*! PanicBlue - Blue color component. */ #define IRIS_MVPL_SIG1_PANICCOLOR_PanicBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_PANICCOLOR_PanicBlue_SHIFT)) & IRIS_MVPL_SIG1_PANICCOLOR_PanicBlue_MASK) #define IRIS_MVPL_SIG1_PANICCOLOR_PanicGreen_MASK (0xFF0000U) #define IRIS_MVPL_SIG1_PANICCOLOR_PanicGreen_SHIFT (16U) /*! PanicGreen - Green color component. */ #define IRIS_MVPL_SIG1_PANICCOLOR_PanicGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_PANICCOLOR_PanicGreen_SHIFT)) & IRIS_MVPL_SIG1_PANICCOLOR_PanicGreen_MASK) #define IRIS_MVPL_SIG1_PANICCOLOR_PanicRed_MASK (0xFF000000U) #define IRIS_MVPL_SIG1_PANICCOLOR_PanicRed_SHIFT (24U) /*! PanicRed - Red color component. */ #define IRIS_MVPL_SIG1_PANICCOLOR_PanicRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_PANICCOLOR_PanicRed_SHIFT)) & IRIS_MVPL_SIG1_PANICCOLOR_PanicRed_MASK) /*! @} */ /*! @name SIG1_EVALCONTROL0 - Control settings for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALCONTROL0_EnEvalWin0_MASK (0x1U) #define IRIS_MVPL_SIG1_EVALCONTROL0_EnEvalWin0_SHIFT (0U) /*! EnEvalWin0 - When enabled (value 1) a CRC signature is computed for all pixels inside this evaluation window (SigCRC). */ #define IRIS_MVPL_SIG1_EVALCONTROL0_EnEvalWin0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_EnEvalWin0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_EnEvalWin0_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL0_EnCRC0_MASK (0x2U) #define IRIS_MVPL_SIG1_EVALCONTROL0_EnCRC0_SHIFT (1U) /*! EnCRC0 - When enabled (value 1) the measured signature is checked against a reference value (SigCRCRef). */ #define IRIS_MVPL_SIG1_EVALCONTROL0_EnCRC0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_EnCRC0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_EnCRC0_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaMask0_MASK (0x100U) #define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaMask0_SHIFT (8U) /*! AlphaMask0 - When enabled (value 1) pixels with alpha bit = 0 are ignored for signature computation. */ #define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaMask0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_AlphaMask0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_AlphaMask0_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaInv0_MASK (0x200U) #define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaInv0_SHIFT (9U) /*! AlphaInv0 - When enabled (value 1) the effect of AlphaMask is inverted (pixels with alpha bit = 1 are ignored then). */ #define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaInv0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_AlphaInv0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_AlphaInv0_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL0_EnLocalPanic0_MASK (0x10000U) #define IRIS_MVPL_SIG1_EVALCONTROL0_EnLocalPanic0_SHIFT (16U) /*! EnLocalPanic0 - When enabled (value 1) the error status this window (StsSigError) will replace * all pixels inside the window by a constant color on the display. Skip regions due to other * evaluation windows on top are not modified. AlphaMask, when enabled, is not considered for this * replacement. */ #define IRIS_MVPL_SIG1_EVALCONTROL0_EnLocalPanic0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_EnLocalPanic0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_EnLocalPanic0_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL0_EnGlobalPanic0_MASK (0x20000U) #define IRIS_MVPL_SIG1_EVALCONTROL0_EnGlobalPanic0_SHIFT (17U) /*! EnGlobalPanic0 - When enabled (value 1) the error status of this window (StsSigError) will * activate the panic mode of the display stream's Frame Generator, which can switch to another * display mode in response. */ #define IRIS_MVPL_SIG1_EVALCONTROL0_EnGlobalPanic0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_EnGlobalPanic0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_EnGlobalPanic0_MASK) /*! @} */ /*! @name SIG1_EVALUPPERLEFT0 - Upper left corner of evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT0_XEvalUpperLeft0_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALUPPERLEFT0_XEvalUpperLeft0_SHIFT (0U) /*! XEvalUpperLeft0 - X coordinate. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT0_XEvalUpperLeft0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT0_XEvalUpperLeft0_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT0_XEvalUpperLeft0_MASK) #define IRIS_MVPL_SIG1_EVALUPPERLEFT0_YEvalUpperLeft0_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALUPPERLEFT0_YEvalUpperLeft0_SHIFT (16U) /*! YEvalUpperLeft0 - Y coordinate. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT0_YEvalUpperLeft0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT0_YEvalUpperLeft0_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT0_YEvalUpperLeft0_MASK) /*! @} */ /*! @name SIG1_EVALLOWERRIGHT0 - Lower right corner of evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_XEvalLowerRight0_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_XEvalLowerRight0_SHIFT (0U) /*! XEvalLowerRight0 - X coordinate. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_XEvalLowerRight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT0_XEvalLowerRight0_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT0_XEvalLowerRight0_MASK) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_YEvalLowerRight0_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_YEvalLowerRight0_SHIFT (16U) /*! YEvalLowerRight0 - Y coordinate. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_YEvalLowerRight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT0_YEvalLowerRight0_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT0_YEvalLowerRight0_MASK) /*! @} */ /*! @name SIG1_SIGCRCREDREF0 - Reference signature of red channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCREDREF0_SigCRCRedRef0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCREDREF0_SigCRCRedRef0_SHIFT (0U) /*! SigCRCRedRef0 - Reference value that is compared against measured SigCRCRed value. */ #define IRIS_MVPL_SIG1_SIGCRCREDREF0_SigCRCRedRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF0_SigCRCRedRef0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF0_SigCRCRedRef0_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREENREF0 - Reference signature of green channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF0_SigCRCGreenRef0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREENREF0_SigCRCGreenRef0_SHIFT (0U) /*! SigCRCGreenRef0 - Reference value that is compared against measured SigCRCGreen value. */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF0_SigCRCGreenRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF0_SigCRCGreenRef0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF0_SigCRCGreenRef0_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUEREF0 - Reference signature of blue channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF0_SigCRCBlueRef0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUEREF0_SigCRCBlueRef0_SHIFT (0U) /*! SigCRCBlueRef0 - Reference value that is compared against measured SigCRCBlue value. */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF0_SigCRCBlueRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF0_SigCRCBlueRef0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF0_SigCRCBlueRef0_MASK) /*! @} */ /*! @name SIG1_SIGCRCRED0 - Measured signature of red channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCRED0_SigCRCRed0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCRED0_SigCRCRed0_SHIFT (0U) /*! SigCRCRed0 - CRC values from red channel. */ #define IRIS_MVPL_SIG1_SIGCRCRED0_SigCRCRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED0_SigCRCRed0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED0_SigCRCRed0_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREEN0 - Measured signature of green channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREEN0_SigCRCGreen0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREEN0_SigCRCGreen0_SHIFT (0U) /*! SigCRCGreen0 - CRC values from green channel. */ #define IRIS_MVPL_SIG1_SIGCRCGREEN0_SigCRCGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN0_SigCRCGreen0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN0_SigCRCGreen0_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUE0 - Measured signature of blue channel for evaluation window 0. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUE0_SigCRCBlue0_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUE0_SigCRCBlue0_SHIFT (0U) /*! SigCRCBlue0 - CRC values from blue channel. */ #define IRIS_MVPL_SIG1_SIGCRCBLUE0_SigCRCBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE0_SigCRCBlue0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE0_SigCRCBlue0_MASK) /*! @} */ /*! @name SIG1_EVALCONTROL1 - Control settings for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALCONTROL1_EnEvalWin1_MASK (0x1U) #define IRIS_MVPL_SIG1_EVALCONTROL1_EnEvalWin1_SHIFT (0U) /*! EnEvalWin1 - See EnEvalWin0. */ #define IRIS_MVPL_SIG1_EVALCONTROL1_EnEvalWin1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_EnEvalWin1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_EnEvalWin1_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL1_EnCRC1_MASK (0x2U) #define IRIS_MVPL_SIG1_EVALCONTROL1_EnCRC1_SHIFT (1U) /*! EnCRC1 - See EnCRC0. */ #define IRIS_MVPL_SIG1_EVALCONTROL1_EnCRC1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_EnCRC1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_EnCRC1_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaMask1_MASK (0x100U) #define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaMask1_SHIFT (8U) /*! AlphaMask1 - See AlphaMask0. */ #define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaMask1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_AlphaMask1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_AlphaMask1_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaInv1_MASK (0x200U) #define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaInv1_SHIFT (9U) /*! AlphaInv1 - See AlphaInv0. */ #define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaInv1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_AlphaInv1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_AlphaInv1_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL1_EnLocalPanic1_MASK (0x10000U) #define IRIS_MVPL_SIG1_EVALCONTROL1_EnLocalPanic1_SHIFT (16U) /*! EnLocalPanic1 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL1_EnLocalPanic1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_EnLocalPanic1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_EnLocalPanic1_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL1_EnGlobalPanic1_MASK (0x20000U) #define IRIS_MVPL_SIG1_EVALCONTROL1_EnGlobalPanic1_SHIFT (17U) /*! EnGlobalPanic1 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL1_EnGlobalPanic1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_EnGlobalPanic1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_EnGlobalPanic1_MASK) /*! @} */ /*! @name SIG1_EVALUPPERLEFT1 - Upper left corner of evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT1_XEvalUpperLeft1_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALUPPERLEFT1_XEvalUpperLeft1_SHIFT (0U) /*! XEvalUpperLeft1 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT1_XEvalUpperLeft1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT1_XEvalUpperLeft1_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT1_XEvalUpperLeft1_MASK) #define IRIS_MVPL_SIG1_EVALUPPERLEFT1_YEvalUpperLeft1_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALUPPERLEFT1_YEvalUpperLeft1_SHIFT (16U) /*! YEvalUpperLeft1 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT1_YEvalUpperLeft1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT1_YEvalUpperLeft1_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT1_YEvalUpperLeft1_MASK) /*! @} */ /*! @name SIG1_EVALLOWERRIGHT1 - Lower right corner of evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_XEvalLowerRight1_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_XEvalLowerRight1_SHIFT (0U) /*! XEvalLowerRight1 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_XEvalLowerRight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT1_XEvalLowerRight1_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT1_XEvalLowerRight1_MASK) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_YEvalLowerRight1_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_YEvalLowerRight1_SHIFT (16U) /*! YEvalLowerRight1 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_YEvalLowerRight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT1_YEvalLowerRight1_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT1_YEvalLowerRight1_MASK) /*! @} */ /*! @name SIG1_SIGCRCREDREF1 - Reference signature of red channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCREDREF1_SigCRCRedRef1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCREDREF1_SigCRCRedRef1_SHIFT (0U) /*! SigCRCRedRef1 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG1_SIGCRCREDREF1_SigCRCRedRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF1_SigCRCRedRef1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF1_SigCRCRedRef1_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREENREF1 - Reference signature of green channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF1_SigCRCGreenRef1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREENREF1_SigCRCGreenRef1_SHIFT (0U) /*! SigCRCGreenRef1 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF1_SigCRCGreenRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF1_SigCRCGreenRef1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF1_SigCRCGreenRef1_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUEREF1 - Reference signature of blue channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF1_SigCRCBlueRef1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUEREF1_SigCRCBlueRef1_SHIFT (0U) /*! SigCRCBlueRef1 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF1_SigCRCBlueRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF1_SigCRCBlueRef1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF1_SigCRCBlueRef1_MASK) /*! @} */ /*! @name SIG1_SIGCRCRED1 - Measured signature of red channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCRED1_SigCRCRed1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCRED1_SigCRCRed1_SHIFT (0U) /*! SigCRCRed1 - See SigCRCRed0. */ #define IRIS_MVPL_SIG1_SIGCRCRED1_SigCRCRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED1_SigCRCRed1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED1_SigCRCRed1_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREEN1 - Measured signature of green channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREEN1_SigCRCGreen1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREEN1_SigCRCGreen1_SHIFT (0U) /*! SigCRCGreen1 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG1_SIGCRCGREEN1_SigCRCGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN1_SigCRCGreen1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN1_SigCRCGreen1_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUE1 - Measured signature of blue channel for evaluation window 1. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUE1_SigCRCBlue1_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUE1_SigCRCBlue1_SHIFT (0U) /*! SigCRCBlue1 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUE1_SigCRCBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE1_SigCRCBlue1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE1_SigCRCBlue1_MASK) /*! @} */ /*! @name SIG1_EVALCONTROL2 - Control settings for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALCONTROL2_EnEvalWin2_MASK (0x1U) #define IRIS_MVPL_SIG1_EVALCONTROL2_EnEvalWin2_SHIFT (0U) /*! EnEvalWin2 - See EnEvalWin0. */ #define IRIS_MVPL_SIG1_EVALCONTROL2_EnEvalWin2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_EnEvalWin2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_EnEvalWin2_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL2_EnCRC2_MASK (0x2U) #define IRIS_MVPL_SIG1_EVALCONTROL2_EnCRC2_SHIFT (1U) /*! EnCRC2 - See EnCRC0. */ #define IRIS_MVPL_SIG1_EVALCONTROL2_EnCRC2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_EnCRC2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_EnCRC2_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaMask2_MASK (0x100U) #define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaMask2_SHIFT (8U) /*! AlphaMask2 - See AlphaMask0. */ #define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaMask2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_AlphaMask2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_AlphaMask2_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaInv2_MASK (0x200U) #define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaInv2_SHIFT (9U) /*! AlphaInv2 - See AlphaInv0. */ #define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaInv2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_AlphaInv2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_AlphaInv2_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL2_EnLocalPanic2_MASK (0x10000U) #define IRIS_MVPL_SIG1_EVALCONTROL2_EnLocalPanic2_SHIFT (16U) /*! EnLocalPanic2 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL2_EnLocalPanic2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_EnLocalPanic2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_EnLocalPanic2_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL2_EnGlobalPanic2_MASK (0x20000U) #define IRIS_MVPL_SIG1_EVALCONTROL2_EnGlobalPanic2_SHIFT (17U) /*! EnGlobalPanic2 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL2_EnGlobalPanic2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_EnGlobalPanic2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_EnGlobalPanic2_MASK) /*! @} */ /*! @name SIG1_EVALUPPERLEFT2 - Upper left corner of evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT2_XEvalUpperLeft2_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALUPPERLEFT2_XEvalUpperLeft2_SHIFT (0U) /*! XEvalUpperLeft2 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT2_XEvalUpperLeft2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT2_XEvalUpperLeft2_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT2_XEvalUpperLeft2_MASK) #define IRIS_MVPL_SIG1_EVALUPPERLEFT2_YEvalUpperLeft2_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALUPPERLEFT2_YEvalUpperLeft2_SHIFT (16U) /*! YEvalUpperLeft2 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT2_YEvalUpperLeft2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT2_YEvalUpperLeft2_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT2_YEvalUpperLeft2_MASK) /*! @} */ /*! @name SIG1_EVALLOWERRIGHT2 - Lower right corner of evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_XEvalLowerRight2_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_XEvalLowerRight2_SHIFT (0U) /*! XEvalLowerRight2 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_XEvalLowerRight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT2_XEvalLowerRight2_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT2_XEvalLowerRight2_MASK) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_YEvalLowerRight2_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_YEvalLowerRight2_SHIFT (16U) /*! YEvalLowerRight2 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_YEvalLowerRight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT2_YEvalLowerRight2_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT2_YEvalLowerRight2_MASK) /*! @} */ /*! @name SIG1_SIGCRCREDREF2 - Reference signature of red channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCREDREF2_SigCRCRedRef2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCREDREF2_SigCRCRedRef2_SHIFT (0U) /*! SigCRCRedRef2 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG1_SIGCRCREDREF2_SigCRCRedRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF2_SigCRCRedRef2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF2_SigCRCRedRef2_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREENREF2 - Reference signature of green channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF2_SigCRCGreenRef2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREENREF2_SigCRCGreenRef2_SHIFT (0U) /*! SigCRCGreenRef2 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF2_SigCRCGreenRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF2_SigCRCGreenRef2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF2_SigCRCGreenRef2_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUEREF2 - Reference signature of blue channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF2_SigCRCBlueRef2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUEREF2_SigCRCBlueRef2_SHIFT (0U) /*! SigCRCBlueRef2 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF2_SigCRCBlueRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF2_SigCRCBlueRef2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF2_SigCRCBlueRef2_MASK) /*! @} */ /*! @name SIG1_SIGCRCRED2 - Measured signature of red channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCRED2_SigCRCRed2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCRED2_SigCRCRed2_SHIFT (0U) /*! SigCRCRed2 - See SigCRCRed0. */ #define IRIS_MVPL_SIG1_SIGCRCRED2_SigCRCRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED2_SigCRCRed2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED2_SigCRCRed2_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREEN2 - Measured signature of green channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREEN2_SigCRCGreen2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREEN2_SigCRCGreen2_SHIFT (0U) /*! SigCRCGreen2 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG1_SIGCRCGREEN2_SigCRCGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN2_SigCRCGreen2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN2_SigCRCGreen2_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUE2 - Measured signature of blue channel for evaluation window 2. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUE2_SigCRCBlue2_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUE2_SigCRCBlue2_SHIFT (0U) /*! SigCRCBlue2 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUE2_SigCRCBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE2_SigCRCBlue2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE2_SigCRCBlue2_MASK) /*! @} */ /*! @name SIG1_EVALCONTROL3 - Control settings for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALCONTROL3_EnEvalWin3_MASK (0x1U) #define IRIS_MVPL_SIG1_EVALCONTROL3_EnEvalWin3_SHIFT (0U) /*! EnEvalWin3 - See EnEvalWin0. */ #define IRIS_MVPL_SIG1_EVALCONTROL3_EnEvalWin3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_EnEvalWin3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_EnEvalWin3_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL3_EnCRC3_MASK (0x2U) #define IRIS_MVPL_SIG1_EVALCONTROL3_EnCRC3_SHIFT (1U) /*! EnCRC3 - See EnCRC0. */ #define IRIS_MVPL_SIG1_EVALCONTROL3_EnCRC3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_EnCRC3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_EnCRC3_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaMask3_MASK (0x100U) #define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaMask3_SHIFT (8U) /*! AlphaMask3 - See AlphaMask0. */ #define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaMask3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_AlphaMask3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_AlphaMask3_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaInv3_MASK (0x200U) #define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaInv3_SHIFT (9U) /*! AlphaInv3 - See AlphaInv0. */ #define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaInv3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_AlphaInv3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_AlphaInv3_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL3_EnLocalPanic3_MASK (0x10000U) #define IRIS_MVPL_SIG1_EVALCONTROL3_EnLocalPanic3_SHIFT (16U) /*! EnLocalPanic3 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL3_EnLocalPanic3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_EnLocalPanic3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_EnLocalPanic3_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL3_EnGlobalPanic3_MASK (0x20000U) #define IRIS_MVPL_SIG1_EVALCONTROL3_EnGlobalPanic3_SHIFT (17U) /*! EnGlobalPanic3 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL3_EnGlobalPanic3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_EnGlobalPanic3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_EnGlobalPanic3_MASK) /*! @} */ /*! @name SIG1_EVALUPPERLEFT3 - Upper left corner of evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT3_XEvalUpperLeft3_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALUPPERLEFT3_XEvalUpperLeft3_SHIFT (0U) /*! XEvalUpperLeft3 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT3_XEvalUpperLeft3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT3_XEvalUpperLeft3_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT3_XEvalUpperLeft3_MASK) #define IRIS_MVPL_SIG1_EVALUPPERLEFT3_YEvalUpperLeft3_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALUPPERLEFT3_YEvalUpperLeft3_SHIFT (16U) /*! YEvalUpperLeft3 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT3_YEvalUpperLeft3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT3_YEvalUpperLeft3_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT3_YEvalUpperLeft3_MASK) /*! @} */ /*! @name SIG1_EVALLOWERRIGHT3 - Lower right corner of evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_XEvalLowerRight3_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_XEvalLowerRight3_SHIFT (0U) /*! XEvalLowerRight3 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_XEvalLowerRight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT3_XEvalLowerRight3_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT3_XEvalLowerRight3_MASK) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_YEvalLowerRight3_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_YEvalLowerRight3_SHIFT (16U) /*! YEvalLowerRight3 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_YEvalLowerRight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT3_YEvalLowerRight3_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT3_YEvalLowerRight3_MASK) /*! @} */ /*! @name SIG1_SIGCRCREDREF3 - Reference signature of red channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCREDREF3_SigCRCRedRef3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCREDREF3_SigCRCRedRef3_SHIFT (0U) /*! SigCRCRedRef3 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG1_SIGCRCREDREF3_SigCRCRedRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF3_SigCRCRedRef3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF3_SigCRCRedRef3_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREENREF3 - Reference signature of green channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF3_SigCRCGreenRef3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREENREF3_SigCRCGreenRef3_SHIFT (0U) /*! SigCRCGreenRef3 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF3_SigCRCGreenRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF3_SigCRCGreenRef3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF3_SigCRCGreenRef3_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUEREF3 - Reference signature of blue channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF3_SigCRCBlueRef3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUEREF3_SigCRCBlueRef3_SHIFT (0U) /*! SigCRCBlueRef3 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF3_SigCRCBlueRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF3_SigCRCBlueRef3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF3_SigCRCBlueRef3_MASK) /*! @} */ /*! @name SIG1_SIGCRCRED3 - Measured signature of red channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCRED3_SigCRCRed3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCRED3_SigCRCRed3_SHIFT (0U) /*! SigCRCRed3 - See SigCRCRed0. */ #define IRIS_MVPL_SIG1_SIGCRCRED3_SigCRCRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED3_SigCRCRed3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED3_SigCRCRed3_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREEN3 - Measured signature of green channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREEN3_SigCRCGreen3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREEN3_SigCRCGreen3_SHIFT (0U) /*! SigCRCGreen3 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG1_SIGCRCGREEN3_SigCRCGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN3_SigCRCGreen3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN3_SigCRCGreen3_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUE3 - Measured signature of blue channel for evaluation window 3. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUE3_SigCRCBlue3_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUE3_SigCRCBlue3_SHIFT (0U) /*! SigCRCBlue3 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUE3_SigCRCBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE3_SigCRCBlue3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE3_SigCRCBlue3_MASK) /*! @} */ /*! @name SIG1_EVALCONTROL4 - Control settings for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALCONTROL4_EnEvalWin4_MASK (0x1U) #define IRIS_MVPL_SIG1_EVALCONTROL4_EnEvalWin4_SHIFT (0U) /*! EnEvalWin4 - See EnEvalWin0. */ #define IRIS_MVPL_SIG1_EVALCONTROL4_EnEvalWin4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_EnEvalWin4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_EnEvalWin4_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL4_EnCRC4_MASK (0x2U) #define IRIS_MVPL_SIG1_EVALCONTROL4_EnCRC4_SHIFT (1U) /*! EnCRC4 - See EnCRC0. */ #define IRIS_MVPL_SIG1_EVALCONTROL4_EnCRC4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_EnCRC4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_EnCRC4_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaMask4_MASK (0x100U) #define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaMask4_SHIFT (8U) /*! AlphaMask4 - See AlphaMask0. */ #define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaMask4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_AlphaMask4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_AlphaMask4_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaInv4_MASK (0x200U) #define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaInv4_SHIFT (9U) /*! AlphaInv4 - See AlphaInv0. */ #define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaInv4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_AlphaInv4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_AlphaInv4_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL4_EnLocalPanic4_MASK (0x10000U) #define IRIS_MVPL_SIG1_EVALCONTROL4_EnLocalPanic4_SHIFT (16U) /*! EnLocalPanic4 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL4_EnLocalPanic4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_EnLocalPanic4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_EnLocalPanic4_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL4_EnGlobalPanic4_MASK (0x20000U) #define IRIS_MVPL_SIG1_EVALCONTROL4_EnGlobalPanic4_SHIFT (17U) /*! EnGlobalPanic4 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL4_EnGlobalPanic4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_EnGlobalPanic4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_EnGlobalPanic4_MASK) /*! @} */ /*! @name SIG1_EVALUPPERLEFT4 - Upper left corner of evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT4_XEvalUpperLeft4_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALUPPERLEFT4_XEvalUpperLeft4_SHIFT (0U) /*! XEvalUpperLeft4 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT4_XEvalUpperLeft4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT4_XEvalUpperLeft4_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT4_XEvalUpperLeft4_MASK) #define IRIS_MVPL_SIG1_EVALUPPERLEFT4_YEvalUpperLeft4_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALUPPERLEFT4_YEvalUpperLeft4_SHIFT (16U) /*! YEvalUpperLeft4 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT4_YEvalUpperLeft4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT4_YEvalUpperLeft4_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT4_YEvalUpperLeft4_MASK) /*! @} */ /*! @name SIG1_EVALLOWERRIGHT4 - Lower right corner of evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_XEvalLowerRight4_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_XEvalLowerRight4_SHIFT (0U) /*! XEvalLowerRight4 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_XEvalLowerRight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT4_XEvalLowerRight4_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT4_XEvalLowerRight4_MASK) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_YEvalLowerRight4_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_YEvalLowerRight4_SHIFT (16U) /*! YEvalLowerRight4 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_YEvalLowerRight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT4_YEvalLowerRight4_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT4_YEvalLowerRight4_MASK) /*! @} */ /*! @name SIG1_SIGCRCREDREF4 - Reference signature of red channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCREDREF4_SigCRCRedRef4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCREDREF4_SigCRCRedRef4_SHIFT (0U) /*! SigCRCRedRef4 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG1_SIGCRCREDREF4_SigCRCRedRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF4_SigCRCRedRef4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF4_SigCRCRedRef4_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREENREF4 - Reference signature of green channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF4_SigCRCGreenRef4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREENREF4_SigCRCGreenRef4_SHIFT (0U) /*! SigCRCGreenRef4 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF4_SigCRCGreenRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF4_SigCRCGreenRef4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF4_SigCRCGreenRef4_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUEREF4 - Reference signature of blue channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF4_SigCRCBlueRef4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUEREF4_SigCRCBlueRef4_SHIFT (0U) /*! SigCRCBlueRef4 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF4_SigCRCBlueRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF4_SigCRCBlueRef4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF4_SigCRCBlueRef4_MASK) /*! @} */ /*! @name SIG1_SIGCRCRED4 - Measured signature of red channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCRED4_SigCRCRed4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCRED4_SigCRCRed4_SHIFT (0U) /*! SigCRCRed4 - See SigCRCRed0. */ #define IRIS_MVPL_SIG1_SIGCRCRED4_SigCRCRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED4_SigCRCRed4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED4_SigCRCRed4_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREEN4 - Measured signature of green channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREEN4_SigCRCGreen4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREEN4_SigCRCGreen4_SHIFT (0U) /*! SigCRCGreen4 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG1_SIGCRCGREEN4_SigCRCGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN4_SigCRCGreen4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN4_SigCRCGreen4_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUE4 - Measured signature of blue channel for evaluation window 4. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUE4_SigCRCBlue4_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUE4_SigCRCBlue4_SHIFT (0U) /*! SigCRCBlue4 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUE4_SigCRCBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE4_SigCRCBlue4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE4_SigCRCBlue4_MASK) /*! @} */ /*! @name SIG1_EVALCONTROL5 - Control settings for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALCONTROL5_EnEvalWin5_MASK (0x1U) #define IRIS_MVPL_SIG1_EVALCONTROL5_EnEvalWin5_SHIFT (0U) /*! EnEvalWin5 - See EnEvalWin0. */ #define IRIS_MVPL_SIG1_EVALCONTROL5_EnEvalWin5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_EnEvalWin5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_EnEvalWin5_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL5_EnCRC5_MASK (0x2U) #define IRIS_MVPL_SIG1_EVALCONTROL5_EnCRC5_SHIFT (1U) /*! EnCRC5 - See EnCRC0. */ #define IRIS_MVPL_SIG1_EVALCONTROL5_EnCRC5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_EnCRC5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_EnCRC5_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaMask5_MASK (0x100U) #define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaMask5_SHIFT (8U) /*! AlphaMask5 - See AlphaMask0. */ #define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaMask5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_AlphaMask5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_AlphaMask5_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaInv5_MASK (0x200U) #define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaInv5_SHIFT (9U) /*! AlphaInv5 - See AlphaInv0. */ #define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaInv5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_AlphaInv5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_AlphaInv5_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL5_EnLocalPanic5_MASK (0x10000U) #define IRIS_MVPL_SIG1_EVALCONTROL5_EnLocalPanic5_SHIFT (16U) /*! EnLocalPanic5 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL5_EnLocalPanic5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_EnLocalPanic5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_EnLocalPanic5_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL5_EnGlobalPanic5_MASK (0x20000U) #define IRIS_MVPL_SIG1_EVALCONTROL5_EnGlobalPanic5_SHIFT (17U) /*! EnGlobalPanic5 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL5_EnGlobalPanic5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_EnGlobalPanic5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_EnGlobalPanic5_MASK) /*! @} */ /*! @name SIG1_EVALUPPERLEFT5 - Upper left corner of evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT5_XEvalUpperLeft5_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALUPPERLEFT5_XEvalUpperLeft5_SHIFT (0U) /*! XEvalUpperLeft5 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT5_XEvalUpperLeft5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT5_XEvalUpperLeft5_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT5_XEvalUpperLeft5_MASK) #define IRIS_MVPL_SIG1_EVALUPPERLEFT5_YEvalUpperLeft5_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALUPPERLEFT5_YEvalUpperLeft5_SHIFT (16U) /*! YEvalUpperLeft5 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT5_YEvalUpperLeft5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT5_YEvalUpperLeft5_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT5_YEvalUpperLeft5_MASK) /*! @} */ /*! @name SIG1_EVALLOWERRIGHT5 - Lower right corner of evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_XEvalLowerRight5_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_XEvalLowerRight5_SHIFT (0U) /*! XEvalLowerRight5 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_XEvalLowerRight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT5_XEvalLowerRight5_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT5_XEvalLowerRight5_MASK) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_YEvalLowerRight5_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_YEvalLowerRight5_SHIFT (16U) /*! YEvalLowerRight5 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_YEvalLowerRight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT5_YEvalLowerRight5_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT5_YEvalLowerRight5_MASK) /*! @} */ /*! @name SIG1_SIGCRCREDREF5 - Reference signature of red channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCREDREF5_SigCRCRedRef5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCREDREF5_SigCRCRedRef5_SHIFT (0U) /*! SigCRCRedRef5 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG1_SIGCRCREDREF5_SigCRCRedRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF5_SigCRCRedRef5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF5_SigCRCRedRef5_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREENREF5 - Reference signature of green channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF5_SigCRCGreenRef5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREENREF5_SigCRCGreenRef5_SHIFT (0U) /*! SigCRCGreenRef5 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF5_SigCRCGreenRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF5_SigCRCGreenRef5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF5_SigCRCGreenRef5_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUEREF5 - Reference signature of blue channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF5_SigCRCBlueRef5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUEREF5_SigCRCBlueRef5_SHIFT (0U) /*! SigCRCBlueRef5 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF5_SigCRCBlueRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF5_SigCRCBlueRef5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF5_SigCRCBlueRef5_MASK) /*! @} */ /*! @name SIG1_SIGCRCRED5 - Measured signature of red channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCRED5_SigCRCRed5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCRED5_SigCRCRed5_SHIFT (0U) /*! SigCRCRed5 - See SigCRCRed0. */ #define IRIS_MVPL_SIG1_SIGCRCRED5_SigCRCRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED5_SigCRCRed5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED5_SigCRCRed5_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREEN5 - Measured signature of green channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREEN5_SigCRCGreen5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREEN5_SigCRCGreen5_SHIFT (0U) /*! SigCRCGreen5 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG1_SIGCRCGREEN5_SigCRCGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN5_SigCRCGreen5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN5_SigCRCGreen5_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUE5 - Measured signature of blue channel for evaluation window 5. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUE5_SigCRCBlue5_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUE5_SigCRCBlue5_SHIFT (0U) /*! SigCRCBlue5 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUE5_SigCRCBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE5_SigCRCBlue5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE5_SigCRCBlue5_MASK) /*! @} */ /*! @name SIG1_EVALCONTROL6 - Control settings for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALCONTROL6_EnEvalWin6_MASK (0x1U) #define IRIS_MVPL_SIG1_EVALCONTROL6_EnEvalWin6_SHIFT (0U) /*! EnEvalWin6 - See EnEvalWin0. */ #define IRIS_MVPL_SIG1_EVALCONTROL6_EnEvalWin6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_EnEvalWin6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_EnEvalWin6_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL6_EnCRC6_MASK (0x2U) #define IRIS_MVPL_SIG1_EVALCONTROL6_EnCRC6_SHIFT (1U) /*! EnCRC6 - See EnCRC0. */ #define IRIS_MVPL_SIG1_EVALCONTROL6_EnCRC6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_EnCRC6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_EnCRC6_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaMask6_MASK (0x100U) #define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaMask6_SHIFT (8U) /*! AlphaMask6 - See AlphaMask0. */ #define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaMask6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_AlphaMask6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_AlphaMask6_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaInv6_MASK (0x200U) #define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaInv6_SHIFT (9U) /*! AlphaInv6 - See AlphaInv0. */ #define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaInv6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_AlphaInv6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_AlphaInv6_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL6_EnLocalPanic6_MASK (0x10000U) #define IRIS_MVPL_SIG1_EVALCONTROL6_EnLocalPanic6_SHIFT (16U) /*! EnLocalPanic6 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL6_EnLocalPanic6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_EnLocalPanic6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_EnLocalPanic6_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL6_EnGlobalPanic6_MASK (0x20000U) #define IRIS_MVPL_SIG1_EVALCONTROL6_EnGlobalPanic6_SHIFT (17U) /*! EnGlobalPanic6 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL6_EnGlobalPanic6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_EnGlobalPanic6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_EnGlobalPanic6_MASK) /*! @} */ /*! @name SIG1_EVALUPPERLEFT6 - Upper left corner of evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT6_XEvalUpperLeft6_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALUPPERLEFT6_XEvalUpperLeft6_SHIFT (0U) /*! XEvalUpperLeft6 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT6_XEvalUpperLeft6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT6_XEvalUpperLeft6_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT6_XEvalUpperLeft6_MASK) #define IRIS_MVPL_SIG1_EVALUPPERLEFT6_YEvalUpperLeft6_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALUPPERLEFT6_YEvalUpperLeft6_SHIFT (16U) /*! YEvalUpperLeft6 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT6_YEvalUpperLeft6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT6_YEvalUpperLeft6_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT6_YEvalUpperLeft6_MASK) /*! @} */ /*! @name SIG1_EVALLOWERRIGHT6 - Lower right corner of evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_XEvalLowerRight6_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_XEvalLowerRight6_SHIFT (0U) /*! XEvalLowerRight6 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_XEvalLowerRight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT6_XEvalLowerRight6_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT6_XEvalLowerRight6_MASK) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_YEvalLowerRight6_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_YEvalLowerRight6_SHIFT (16U) /*! YEvalLowerRight6 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_YEvalLowerRight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT6_YEvalLowerRight6_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT6_YEvalLowerRight6_MASK) /*! @} */ /*! @name SIG1_SIGCRCREDREF6 - Reference signature of red channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCREDREF6_SigCRCRedRef6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCREDREF6_SigCRCRedRef6_SHIFT (0U) /*! SigCRCRedRef6 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG1_SIGCRCREDREF6_SigCRCRedRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF6_SigCRCRedRef6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF6_SigCRCRedRef6_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREENREF6 - Reference signature of green channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF6_SigCRCGreenRef6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREENREF6_SigCRCGreenRef6_SHIFT (0U) /*! SigCRCGreenRef6 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF6_SigCRCGreenRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF6_SigCRCGreenRef6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF6_SigCRCGreenRef6_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUEREF6 - Reference signature of blue channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF6_SigCRCBlueRef6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUEREF6_SigCRCBlueRef6_SHIFT (0U) /*! SigCRCBlueRef6 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF6_SigCRCBlueRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF6_SigCRCBlueRef6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF6_SigCRCBlueRef6_MASK) /*! @} */ /*! @name SIG1_SIGCRCRED6 - Measured signature of red channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCRED6_SigCRCRed6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCRED6_SigCRCRed6_SHIFT (0U) /*! SigCRCRed6 - See SigCRCRed0. */ #define IRIS_MVPL_SIG1_SIGCRCRED6_SigCRCRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED6_SigCRCRed6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED6_SigCRCRed6_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREEN6 - Measured signature of green channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREEN6_SigCRCGreen6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREEN6_SigCRCGreen6_SHIFT (0U) /*! SigCRCGreen6 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG1_SIGCRCGREEN6_SigCRCGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN6_SigCRCGreen6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN6_SigCRCGreen6_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUE6 - Measured signature of blue channel for evaluation window 6. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUE6_SigCRCBlue6_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUE6_SigCRCBlue6_SHIFT (0U) /*! SigCRCBlue6 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUE6_SigCRCBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE6_SigCRCBlue6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE6_SigCRCBlue6_MASK) /*! @} */ /*! @name SIG1_EVALCONTROL7 - Control settings for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALCONTROL7_EnEvalWin7_MASK (0x1U) #define IRIS_MVPL_SIG1_EVALCONTROL7_EnEvalWin7_SHIFT (0U) /*! EnEvalWin7 - See EnEvalWin0. */ #define IRIS_MVPL_SIG1_EVALCONTROL7_EnEvalWin7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_EnEvalWin7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_EnEvalWin7_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL7_EnCRC7_MASK (0x2U) #define IRIS_MVPL_SIG1_EVALCONTROL7_EnCRC7_SHIFT (1U) /*! EnCRC7 - See EnCRC0. */ #define IRIS_MVPL_SIG1_EVALCONTROL7_EnCRC7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_EnCRC7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_EnCRC7_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaMask7_MASK (0x100U) #define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaMask7_SHIFT (8U) /*! AlphaMask7 - See AlphaMask0. */ #define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaMask7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_AlphaMask7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_AlphaMask7_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaInv7_MASK (0x200U) #define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaInv7_SHIFT (9U) /*! AlphaInv7 - See AlphaInv0. */ #define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaInv7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_AlphaInv7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_AlphaInv7_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL7_EnLocalPanic7_MASK (0x10000U) #define IRIS_MVPL_SIG1_EVALCONTROL7_EnLocalPanic7_SHIFT (16U) /*! EnLocalPanic7 - See EnLocalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL7_EnLocalPanic7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_EnLocalPanic7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_EnLocalPanic7_MASK) #define IRIS_MVPL_SIG1_EVALCONTROL7_EnGlobalPanic7_MASK (0x20000U) #define IRIS_MVPL_SIG1_EVALCONTROL7_EnGlobalPanic7_SHIFT (17U) /*! EnGlobalPanic7 - See EnGlobalPanic0. */ #define IRIS_MVPL_SIG1_EVALCONTROL7_EnGlobalPanic7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_EnGlobalPanic7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_EnGlobalPanic7_MASK) /*! @} */ /*! @name SIG1_EVALUPPERLEFT7 - Upper left corner of evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT7_XEvalUpperLeft7_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALUPPERLEFT7_XEvalUpperLeft7_SHIFT (0U) /*! XEvalUpperLeft7 - See XEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT7_XEvalUpperLeft7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT7_XEvalUpperLeft7_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT7_XEvalUpperLeft7_MASK) #define IRIS_MVPL_SIG1_EVALUPPERLEFT7_YEvalUpperLeft7_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALUPPERLEFT7_YEvalUpperLeft7_SHIFT (16U) /*! YEvalUpperLeft7 - See YEvalUpperLeft0. */ #define IRIS_MVPL_SIG1_EVALUPPERLEFT7_YEvalUpperLeft7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT7_YEvalUpperLeft7_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT7_YEvalUpperLeft7_MASK) /*! @} */ /*! @name SIG1_EVALLOWERRIGHT7 - Lower right corner of evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_XEvalLowerRight7_MASK (0x3FFFU) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_XEvalLowerRight7_SHIFT (0U) /*! XEvalLowerRight7 - See XEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_XEvalLowerRight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT7_XEvalLowerRight7_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT7_XEvalLowerRight7_MASK) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_YEvalLowerRight7_MASK (0x3FFF0000U) #define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_YEvalLowerRight7_SHIFT (16U) /*! YEvalLowerRight7 - See YEvalLowerRight0. */ #define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_YEvalLowerRight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT7_YEvalLowerRight7_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT7_YEvalLowerRight7_MASK) /*! @} */ /*! @name SIG1_SIGCRCREDREF7 - Reference signature of red channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCREDREF7_SigCRCRedRef7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCREDREF7_SigCRCRedRef7_SHIFT (0U) /*! SigCRCRedRef7 - See SigCRCRedRef0. */ #define IRIS_MVPL_SIG1_SIGCRCREDREF7_SigCRCRedRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF7_SigCRCRedRef7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF7_SigCRCRedRef7_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREENREF7 - Reference signature of green channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF7_SigCRCGreenRef7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREENREF7_SigCRCGreenRef7_SHIFT (0U) /*! SigCRCGreenRef7 - See SigCRCGreenRef0. */ #define IRIS_MVPL_SIG1_SIGCRCGREENREF7_SigCRCGreenRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF7_SigCRCGreenRef7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF7_SigCRCGreenRef7_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUEREF7 - Reference signature of blue channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF7_SigCRCBlueRef7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUEREF7_SigCRCBlueRef7_SHIFT (0U) /*! SigCRCBlueRef7 - See SigCRCBlueRef0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUEREF7_SigCRCBlueRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF7_SigCRCBlueRef7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF7_SigCRCBlueRef7_MASK) /*! @} */ /*! @name SIG1_SIGCRCRED7 - Measured signature of red channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCRED7_SigCRCRed7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCRED7_SigCRCRed7_SHIFT (0U) /*! SigCRCRed7 - See SigCRCRed0. */ #define IRIS_MVPL_SIG1_SIGCRCRED7_SigCRCRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED7_SigCRCRed7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED7_SigCRCRed7_MASK) /*! @} */ /*! @name SIG1_SIGCRCGREEN7 - Measured signature of green channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCGREEN7_SigCRCGreen7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCGREEN7_SigCRCGreen7_SHIFT (0U) /*! SigCRCGreen7 - See SigCRCGreen0. */ #define IRIS_MVPL_SIG1_SIGCRCGREEN7_SigCRCGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN7_SigCRCGreen7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN7_SigCRCGreen7_MASK) /*! @} */ /*! @name SIG1_SIGCRCBLUE7 - Measured signature of blue channel for evaluation window 7. */ /*! @{ */ #define IRIS_MVPL_SIG1_SIGCRCBLUE7_SigCRCBlue7_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SIG1_SIGCRCBLUE7_SigCRCBlue7_SHIFT (0U) /*! SigCRCBlue7 - See SigCRCBlue0. */ #define IRIS_MVPL_SIG1_SIGCRCBLUE7_SigCRCBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE7_SigCRCBlue7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE7_SigCRCBlue7_MASK) /*! @} */ /*! @name SIG1_SHADOWLOAD - Shadow load control register. */ /*! @{ */ #define IRIS_MVPL_SIG1_SHADOWLOAD_ShdLdReq_MASK (0xFFU) #define IRIS_MVPL_SIG1_SHADOWLOAD_ShdLdReq_SHIFT (0U) /*! ShdLdReq - Shadow load request for each evaluation window (bit index = window index). */ #define IRIS_MVPL_SIG1_SHADOWLOAD_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SHADOWLOAD_ShdLdReq_SHIFT)) & IRIS_MVPL_SIG1_SHADOWLOAD_ShdLdReq_MASK) /*! @} */ /*! @name SIG1_CONTINUOUSMODE - Signature operation mode control. */ /*! @{ */ #define IRIS_MVPL_SIG1_CONTINUOUSMODE_EnCont_MASK (0x1U) #define IRIS_MVPL_SIG1_CONTINUOUSMODE_EnCont_SHIFT (0U) /*! EnCont - EnCont = 0: disables continuous mode. */ #define IRIS_MVPL_SIG1_CONTINUOUSMODE_EnCont(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_CONTINUOUSMODE_EnCont_SHIFT)) & IRIS_MVPL_SIG1_CONTINUOUSMODE_EnCont_MASK) /*! @} */ /*! @name SIG1_SOFTWAREKICK - Signature measurement trigger. */ /*! @{ */ #define IRIS_MVPL_SIG1_SOFTWAREKICK_Kick_MASK (0x1U) #define IRIS_MVPL_SIG1_SOFTWAREKICK_Kick_SHIFT (0U) /*! Kick - ContinueMode.EnCont=0: Write '1' to this field in order to start signature computation with next frame. */ #define IRIS_MVPL_SIG1_SOFTWAREKICK_Kick(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SOFTWAREKICK_Kick_SHIFT)) & IRIS_MVPL_SIG1_SOFTWAREKICK_Kick_MASK) /*! @} */ /*! @name SIG1_STATUS - Module status. */ /*! @{ */ #define IRIS_MVPL_SIG1_STATUS_StsSigError_MASK (0xFFU) #define IRIS_MVPL_SIG1_STATUS_StsSigError_SHIFT (0U) /*! StsSigError - Error status bits for all evaluation windows (bit index = window index). */ #define IRIS_MVPL_SIG1_STATUS_StsSigError(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATUS_StsSigError_SHIFT)) & IRIS_MVPL_SIG1_STATUS_StsSigError_MASK) #define IRIS_MVPL_SIG1_STATUS_StsSigValid_MASK (0x10000U) #define IRIS_MVPL_SIG1_STATUS_StsSigValid_SHIFT (16U) /*! StsSigValid - Measured signature values are valid. */ #define IRIS_MVPL_SIG1_STATUS_StsSigValid(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATUS_StsSigValid_SHIFT)) & IRIS_MVPL_SIG1_STATUS_StsSigValid_MASK) #define IRIS_MVPL_SIG1_STATUS_StsSigIdle_MASK (0x100000U) #define IRIS_MVPL_SIG1_STATUS_StsSigIdle_SHIFT (20U) /*! StsSigIdle - StsSigIdle = 1: Signature is in Idle state. */ #define IRIS_MVPL_SIG1_STATUS_StsSigIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATUS_StsSigIdle_SHIFT)) & IRIS_MVPL_SIG1_STATUS_StsSigIdle_MASK) /*! @} */ /*! @name CONTROL - Measurement Control Register */ /*! @{ */ #define IRIS_MVPL_CONTROL_Enable_MASK (0x1U) #define IRIS_MVPL_CONTROL_Enable_SHIFT (0U) /*! Enable - Measurement enable */ #define IRIS_MVPL_CONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONTROL_Enable_SHIFT)) & IRIS_MVPL_CONTROL_Enable_MASK) #define IRIS_MVPL_CONTROL_Mode_MASK (0x6U) #define IRIS_MVPL_CONTROL_Mode_SHIFT (1U) /*! Mode - Measurement mode * 0b00..Manual measurement end * 0b01..Timer controlled measurement end * 0b10..Continuous measurement; retriggered by reading SW_Tag register */ #define IRIS_MVPL_CONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONTROL_Mode_SHIFT)) & IRIS_MVPL_CONTROL_Mode_MASK) #define IRIS_MVPL_CONTROL_IncrementMode_MASK (0x40000000U) #define IRIS_MVPL_CONTROL_IncrementMode_SHIFT (30U) /*! IncrementMode - Enable increment mode for latency measurement */ #define IRIS_MVPL_CONTROL_IncrementMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONTROL_IncrementMode_SHIFT)) & IRIS_MVPL_CONTROL_IncrementMode_MASK) #define IRIS_MVPL_CONTROL_OTCDisable_MASK (0x80000000U) #define IRIS_MVPL_CONTROL_OTCDisable_SHIFT (31U) /*! OTCDisable - Disable OTC Counters */ #define IRIS_MVPL_CONTROL_OTCDisable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONTROL_OTCDisable_SHIFT)) & IRIS_MVPL_CONTROL_OTCDisable_MASK) /*! @} */ /*! @name TIMER - Timer Register */ /*! @{ */ #define IRIS_MVPL_TIMER_Load_MASK (0xFFFFFFFU) #define IRIS_MVPL_TIMER_Load_SHIFT (0U) #define IRIS_MVPL_TIMER_Load(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TIMER_Load_SHIFT)) & IRIS_MVPL_TIMER_Load_MASK) #define IRIS_MVPL_TIMER_Divider_MASK (0xF0000000U) #define IRIS_MVPL_TIMER_Divider_SHIFT (28U) #define IRIS_MVPL_TIMER_Divider(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TIMER_Divider_SHIFT)) & IRIS_MVPL_TIMER_Divider_MASK) /*! @} */ /*! @name MEASUREMENTTIMECONTROL - Timer Control Register */ /*! @{ */ #define IRIS_MVPL_MEASUREMENTTIMECONTROL_MTDivider_MASK (0xFFFFFU) #define IRIS_MVPL_MEASUREMENTTIMECONTROL_MTDivider_SHIFT (0U) #define IRIS_MVPL_MEASUREMENTTIMECONTROL_MTDivider(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MEASUREMENTTIMECONTROL_MTDivider_SHIFT)) & IRIS_MVPL_MEASUREMENTTIMECONTROL_MTDivider_MASK) #define IRIS_MVPL_MEASUREMENTTIMECONTROL_MTEnable_MASK (0x80000000U) #define IRIS_MVPL_MEASUREMENTTIMECONTROL_MTEnable_SHIFT (31U) #define IRIS_MVPL_MEASUREMENTTIMECONTROL_MTEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MEASUREMENTTIMECONTROL_MTEnable_SHIFT)) & IRIS_MVPL_MEASUREMENTTIMECONTROL_MTEnable_MASK) /*! @} */ /*! @name SW_TAG - Software Tag Register */ /*! @{ */ #define IRIS_MVPL_SW_TAG_Tag_MASK (0xFFFFFFFFU) #define IRIS_MVPL_SW_TAG_Tag_SHIFT (0U) #define IRIS_MVPL_SW_TAG_Tag(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SW_TAG_Tag_SHIFT)) & IRIS_MVPL_SW_TAG_Tag_MASK) /*! @} */ /*! @name MEASUREMENTTIME - Measurement Time Register */ /*! @{ */ #define IRIS_MVPL_MEASUREMENTTIME_Time_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MEASUREMENTTIME_Time_SHIFT (0U) #define IRIS_MVPL_MEASUREMENTTIME_Time(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MEASUREMENTTIME_Time_SHIFT)) & IRIS_MVPL_MEASUREMENTTIME_Time_MASK) /*! @} */ /*! @name GLOBAL_COUNTER - Global Counter Register */ /*! @{ */ #define IRIS_MVPL_GLOBAL_COUNTER_Global_MASK (0xFFFFFFFFU) #define IRIS_MVPL_GLOBAL_COUNTER_Global_SHIFT (0U) #define IRIS_MVPL_GLOBAL_COUNTER_Global(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GLOBAL_COUNTER_Global_SHIFT)) & IRIS_MVPL_GLOBAL_COUNTER_Global_MASK) /*! @} */ /*! @name MU00_SWITCH - Measurement Unit 0 Source Select Register */ /*! @{ */ #define IRIS_MVPL_MU00_SWITCH_MU00_Select_MASK (0xFU) #define IRIS_MVPL_MU00_SWITCH_MU00_Select_SHIFT (0U) /*! MU00_Select * 0b0000..cmdseq read direction (ACLK clock) * 0b0001..cmdseq write direction (ACLK clock) * 0b1010..fetcheco1 read direction (ACLK clock) * 0b1011..fetchlayer0 read direction (ACLK clock) * 0b1100..store9 write direction (ACLK clock) * 0b0010..fetchdecode9 read direction (ACLK clock) * 0b0011..fetchwarp9 read direction (ACLK clock) * 0b0100..fetcheco9 read direction (ACLK clock) * 0b0101..fetchwarp2 read direction (ACLK clock) * 0b0110..fetcheco2 read direction (ACLK clock) * 0b0111..fetchdecode0 read direction (ACLK clock) * 0b1000..fetcheco0 read direction (ACLK clock) * 0b1001..fetchdecode1 read direction (ACLK clock) */ #define IRIS_MVPL_MU00_SWITCH_MU00_Select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU00_SWITCH_MU00_Select_SHIFT)) & IRIS_MVPL_MU00_SWITCH_MU00_Select_MASK) /*! @} */ /*! @name MU00_DATA_COUNTER - Measurement Unit 0 Data Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU00_DATA_COUNTER_MU00_Data_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU00_DATA_COUNTER_MU00_Data_SHIFT (0U) #define IRIS_MVPL_MU00_DATA_COUNTER_MU00_Data(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU00_DATA_COUNTER_MU00_Data_SHIFT)) & IRIS_MVPL_MU00_DATA_COUNTER_MU00_Data_MASK) /*! @} */ /*! @name MU00_BUSY_COUNTER - Measurement Unit 0 Busy Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU00_BUSY_COUNTER_MU00_Busy_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU00_BUSY_COUNTER_MU00_Busy_SHIFT (0U) #define IRIS_MVPL_MU00_BUSY_COUNTER_MU00_Busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU00_BUSY_COUNTER_MU00_Busy_SHIFT)) & IRIS_MVPL_MU00_BUSY_COUNTER_MU00_Busy_MASK) /*! @} */ /*! @name MU00_TRANSFER_COUNTER - Measurement Unit 0 Transfer Counter */ /*! @{ */ #define IRIS_MVPL_MU00_TRANSFER_COUNTER_MU00_Transfer_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU00_TRANSFER_COUNTER_MU00_Transfer_SHIFT (0U) #define IRIS_MVPL_MU00_TRANSFER_COUNTER_MU00_Transfer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU00_TRANSFER_COUNTER_MU00_Transfer_SHIFT)) & IRIS_MVPL_MU00_TRANSFER_COUNTER_MU00_Transfer_MASK) /*! @} */ /*! @name MU00_ADDRBUSY_COUNTER - Measurement Unit 0 Address Busy Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU00_ADDRBUSY_COUNTER_MU00_Addrbusy_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU00_ADDRBUSY_COUNTER_MU00_Addrbusy_SHIFT (0U) #define IRIS_MVPL_MU00_ADDRBUSY_COUNTER_MU00_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU00_ADDRBUSY_COUNTER_MU00_Addrbusy_SHIFT)) & IRIS_MVPL_MU00_ADDRBUSY_COUNTER_MU00_Addrbusy_MASK) /*! @} */ /*! @name MU00_LATENCY_COUNTER - Measurement Unit 0 Latency Counter */ /*! @{ */ #define IRIS_MVPL_MU00_LATENCY_COUNTER_MU00_Latency_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU00_LATENCY_COUNTER_MU00_Latency_SHIFT (0U) #define IRIS_MVPL_MU00_LATENCY_COUNTER_MU00_Latency(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU00_LATENCY_COUNTER_MU00_Latency_SHIFT)) & IRIS_MVPL_MU00_LATENCY_COUNTER_MU00_Latency_MASK) /*! @} */ /*! @name MU01_SWITCH - Measurement Unit 1 Source Select Register */ /*! @{ */ #define IRIS_MVPL_MU01_SWITCH_MU01_Select_MASK (0xFU) #define IRIS_MVPL_MU01_SWITCH_MU01_Select_SHIFT (0U) /*! MU01_Select * 0b0000..cmdseq read direction (ACLK clock) * 0b0001..cmdseq write direction (ACLK clock) * 0b1010..fetcheco1 read direction (ACLK clock) * 0b1011..fetchlayer0 read direction (ACLK clock) * 0b1100..store9 write direction (ACLK clock) * 0b0010..fetchdecode9 read direction (ACLK clock) * 0b0011..fetchwarp9 read direction (ACLK clock) * 0b0100..fetcheco9 read direction (ACLK clock) * 0b0101..fetchwarp2 read direction (ACLK clock) * 0b0110..fetcheco2 read direction (ACLK clock) * 0b0111..fetchdecode0 read direction (ACLK clock) * 0b1000..fetcheco0 read direction (ACLK clock) * 0b1001..fetchdecode1 read direction (ACLK clock) */ #define IRIS_MVPL_MU01_SWITCH_MU01_Select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU01_SWITCH_MU01_Select_SHIFT)) & IRIS_MVPL_MU01_SWITCH_MU01_Select_MASK) /*! @} */ /*! @name MU01_DATA_COUNTER - Measurement Unit 1 Data Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU01_DATA_COUNTER_MU01_Data_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU01_DATA_COUNTER_MU01_Data_SHIFT (0U) #define IRIS_MVPL_MU01_DATA_COUNTER_MU01_Data(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU01_DATA_COUNTER_MU01_Data_SHIFT)) & IRIS_MVPL_MU01_DATA_COUNTER_MU01_Data_MASK) /*! @} */ /*! @name MU01_BUSY_COUNTER - Measurement Unit 1 Busy Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU01_BUSY_COUNTER_MU01_Busy_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU01_BUSY_COUNTER_MU01_Busy_SHIFT (0U) #define IRIS_MVPL_MU01_BUSY_COUNTER_MU01_Busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU01_BUSY_COUNTER_MU01_Busy_SHIFT)) & IRIS_MVPL_MU01_BUSY_COUNTER_MU01_Busy_MASK) /*! @} */ /*! @name MU01_TRANSFER_COUNTER - Measurement Unit 1 Transfer Counter */ /*! @{ */ #define IRIS_MVPL_MU01_TRANSFER_COUNTER_MU01_Transfer_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU01_TRANSFER_COUNTER_MU01_Transfer_SHIFT (0U) #define IRIS_MVPL_MU01_TRANSFER_COUNTER_MU01_Transfer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU01_TRANSFER_COUNTER_MU01_Transfer_SHIFT)) & IRIS_MVPL_MU01_TRANSFER_COUNTER_MU01_Transfer_MASK) /*! @} */ /*! @name MU01_ADDRBUSY_COUNTER - Measurement Unit 1 Address Busy Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU01_ADDRBUSY_COUNTER_MU01_Addrbusy_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU01_ADDRBUSY_COUNTER_MU01_Addrbusy_SHIFT (0U) #define IRIS_MVPL_MU01_ADDRBUSY_COUNTER_MU01_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU01_ADDRBUSY_COUNTER_MU01_Addrbusy_SHIFT)) & IRIS_MVPL_MU01_ADDRBUSY_COUNTER_MU01_Addrbusy_MASK) /*! @} */ /*! @name MU01_LATENCY_COUNTER - Measurement Unit 1 Latency Counter */ /*! @{ */ #define IRIS_MVPL_MU01_LATENCY_COUNTER_MU01_Latency_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU01_LATENCY_COUNTER_MU01_Latency_SHIFT (0U) #define IRIS_MVPL_MU01_LATENCY_COUNTER_MU01_Latency(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU01_LATENCY_COUNTER_MU01_Latency_SHIFT)) & IRIS_MVPL_MU01_LATENCY_COUNTER_MU01_Latency_MASK) /*! @} */ /*! @name MU02_SWITCH - Measurement Unit 2 Source Select Register */ /*! @{ */ #define IRIS_MVPL_MU02_SWITCH_MU02_Select_MASK (0xFU) #define IRIS_MVPL_MU02_SWITCH_MU02_Select_SHIFT (0U) /*! MU02_Select * 0b0000..cmdseq read direction (ACLK clock) * 0b0001..cmdseq write direction (ACLK clock) * 0b1010..fetcheco1 read direction (ACLK clock) * 0b1011..fetchlayer0 read direction (ACLK clock) * 0b1100..store9 write direction (ACLK clock) * 0b0010..fetchdecode9 read direction (ACLK clock) * 0b0011..fetchwarp9 read direction (ACLK clock) * 0b0100..fetcheco9 read direction (ACLK clock) * 0b0101..fetchwarp2 read direction (ACLK clock) * 0b0110..fetcheco2 read direction (ACLK clock) * 0b0111..fetchdecode0 read direction (ACLK clock) * 0b1000..fetcheco0 read direction (ACLK clock) * 0b1001..fetchdecode1 read direction (ACLK clock) */ #define IRIS_MVPL_MU02_SWITCH_MU02_Select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU02_SWITCH_MU02_Select_SHIFT)) & IRIS_MVPL_MU02_SWITCH_MU02_Select_MASK) /*! @} */ /*! @name MU02_DATA_COUNTER - Measurement Unit 2 Data Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU02_DATA_COUNTER_MU02_Data_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU02_DATA_COUNTER_MU02_Data_SHIFT (0U) #define IRIS_MVPL_MU02_DATA_COUNTER_MU02_Data(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU02_DATA_COUNTER_MU02_Data_SHIFT)) & IRIS_MVPL_MU02_DATA_COUNTER_MU02_Data_MASK) /*! @} */ /*! @name MU02_BUSY_COUNTER - Measurement Unit 2 Busy Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU02_BUSY_COUNTER_MU02_Busy_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU02_BUSY_COUNTER_MU02_Busy_SHIFT (0U) #define IRIS_MVPL_MU02_BUSY_COUNTER_MU02_Busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU02_BUSY_COUNTER_MU02_Busy_SHIFT)) & IRIS_MVPL_MU02_BUSY_COUNTER_MU02_Busy_MASK) /*! @} */ /*! @name MU02_TRANSFER_COUNTER - Measurement Unit 2 Transfer Counter */ /*! @{ */ #define IRIS_MVPL_MU02_TRANSFER_COUNTER_MU02_Transfer_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU02_TRANSFER_COUNTER_MU02_Transfer_SHIFT (0U) #define IRIS_MVPL_MU02_TRANSFER_COUNTER_MU02_Transfer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU02_TRANSFER_COUNTER_MU02_Transfer_SHIFT)) & IRIS_MVPL_MU02_TRANSFER_COUNTER_MU02_Transfer_MASK) /*! @} */ /*! @name MU02_ADDRBUSY_COUNTER - Measurement Unit 2 Address Busy Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU02_ADDRBUSY_COUNTER_MU02_Addrbusy_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU02_ADDRBUSY_COUNTER_MU02_Addrbusy_SHIFT (0U) #define IRIS_MVPL_MU02_ADDRBUSY_COUNTER_MU02_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU02_ADDRBUSY_COUNTER_MU02_Addrbusy_SHIFT)) & IRIS_MVPL_MU02_ADDRBUSY_COUNTER_MU02_Addrbusy_MASK) /*! @} */ /*! @name MU02_LATENCY_COUNTER - Measurement Unit 2 Latency Counter */ /*! @{ */ #define IRIS_MVPL_MU02_LATENCY_COUNTER_MU02_Latency_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU02_LATENCY_COUNTER_MU02_Latency_SHIFT (0U) #define IRIS_MVPL_MU02_LATENCY_COUNTER_MU02_Latency(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU02_LATENCY_COUNTER_MU02_Latency_SHIFT)) & IRIS_MVPL_MU02_LATENCY_COUNTER_MU02_Latency_MASK) /*! @} */ /*! @name MU03_SWITCH - Measurement Unit 3 Source Select Register */ /*! @{ */ #define IRIS_MVPL_MU03_SWITCH_MU03_Select_MASK (0xFU) #define IRIS_MVPL_MU03_SWITCH_MU03_Select_SHIFT (0U) /*! MU03_Select * 0b0000..cmdseq read direction (ACLK clock) * 0b0001..cmdseq write direction (ACLK clock) * 0b1010..fetcheco1 read direction (ACLK clock) * 0b1011..fetchlayer0 read direction (ACLK clock) * 0b1100..store9 write direction (ACLK clock) * 0b0010..fetchdecode9 read direction (ACLK clock) * 0b0011..fetchwarp9 read direction (ACLK clock) * 0b0100..fetcheco9 read direction (ACLK clock) * 0b0101..fetchwarp2 read direction (ACLK clock) * 0b0110..fetcheco2 read direction (ACLK clock) * 0b0111..fetchdecode0 read direction (ACLK clock) * 0b1000..fetcheco0 read direction (ACLK clock) * 0b1001..fetchdecode1 read direction (ACLK clock) */ #define IRIS_MVPL_MU03_SWITCH_MU03_Select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU03_SWITCH_MU03_Select_SHIFT)) & IRIS_MVPL_MU03_SWITCH_MU03_Select_MASK) /*! @} */ /*! @name MU03_DATA_COUNTER - Measurement Unit 3 Data Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU03_DATA_COUNTER_MU03_Data_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU03_DATA_COUNTER_MU03_Data_SHIFT (0U) #define IRIS_MVPL_MU03_DATA_COUNTER_MU03_Data(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU03_DATA_COUNTER_MU03_Data_SHIFT)) & IRIS_MVPL_MU03_DATA_COUNTER_MU03_Data_MASK) /*! @} */ /*! @name MU03_BUSY_COUNTER - Measurement Unit 3 Busy Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU03_BUSY_COUNTER_MU03_Busy_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU03_BUSY_COUNTER_MU03_Busy_SHIFT (0U) #define IRIS_MVPL_MU03_BUSY_COUNTER_MU03_Busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU03_BUSY_COUNTER_MU03_Busy_SHIFT)) & IRIS_MVPL_MU03_BUSY_COUNTER_MU03_Busy_MASK) /*! @} */ /*! @name MU03_TRANSFER_COUNTER - Measurement Unit 3 Transfer Counter */ /*! @{ */ #define IRIS_MVPL_MU03_TRANSFER_COUNTER_MU03_Transfer_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU03_TRANSFER_COUNTER_MU03_Transfer_SHIFT (0U) #define IRIS_MVPL_MU03_TRANSFER_COUNTER_MU03_Transfer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU03_TRANSFER_COUNTER_MU03_Transfer_SHIFT)) & IRIS_MVPL_MU03_TRANSFER_COUNTER_MU03_Transfer_MASK) /*! @} */ /*! @name MU03_ADDRBUSY_COUNTER - Measurement Unit 3 Address Busy Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU03_ADDRBUSY_COUNTER_MU03_Addrbusy_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU03_ADDRBUSY_COUNTER_MU03_Addrbusy_SHIFT (0U) #define IRIS_MVPL_MU03_ADDRBUSY_COUNTER_MU03_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU03_ADDRBUSY_COUNTER_MU03_Addrbusy_SHIFT)) & IRIS_MVPL_MU03_ADDRBUSY_COUNTER_MU03_Addrbusy_MASK) /*! @} */ /*! @name MU03_LATENCY_COUNTER - Measurement Unit 3 Latency Counter */ /*! @{ */ #define IRIS_MVPL_MU03_LATENCY_COUNTER_MU03_Latency_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU03_LATENCY_COUNTER_MU03_Latency_SHIFT (0U) #define IRIS_MVPL_MU03_LATENCY_COUNTER_MU03_Latency(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU03_LATENCY_COUNTER_MU03_Latency_SHIFT)) & IRIS_MVPL_MU03_LATENCY_COUNTER_MU03_Latency_MASK) /*! @} */ /*! @name MU04_SWITCH - Measurement Unit 4 Source Select Register */ /*! @{ */ #define IRIS_MVPL_MU04_SWITCH_MU04_Select_MASK (0xFU) #define IRIS_MVPL_MU04_SWITCH_MU04_Select_SHIFT (0U) /*! MU04_Select * 0b0000..cmdseq read direction (ACLK clock) * 0b0001..cmdseq write direction (ACLK clock) * 0b1010..fetcheco1 read direction (ACLK clock) * 0b1011..fetchlayer0 read direction (ACLK clock) * 0b1100..store9 write direction (ACLK clock) * 0b0010..fetchdecode9 read direction (ACLK clock) * 0b0011..fetchwarp9 read direction (ACLK clock) * 0b0100..fetcheco9 read direction (ACLK clock) * 0b0101..fetchwarp2 read direction (ACLK clock) * 0b0110..fetcheco2 read direction (ACLK clock) * 0b0111..fetchdecode0 read direction (ACLK clock) * 0b1000..fetcheco0 read direction (ACLK clock) * 0b1001..fetchdecode1 read direction (ACLK clock) */ #define IRIS_MVPL_MU04_SWITCH_MU04_Select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU04_SWITCH_MU04_Select_SHIFT)) & IRIS_MVPL_MU04_SWITCH_MU04_Select_MASK) /*! @} */ /*! @name MU04_DATA_COUNTER - Measurement Unit 4 Data Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU04_DATA_COUNTER_MU04_Data_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU04_DATA_COUNTER_MU04_Data_SHIFT (0U) #define IRIS_MVPL_MU04_DATA_COUNTER_MU04_Data(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU04_DATA_COUNTER_MU04_Data_SHIFT)) & IRIS_MVPL_MU04_DATA_COUNTER_MU04_Data_MASK) /*! @} */ /*! @name MU04_BUSY_COUNTER - Measurement Unit 4 Busy Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU04_BUSY_COUNTER_MU04_Busy_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU04_BUSY_COUNTER_MU04_Busy_SHIFT (0U) #define IRIS_MVPL_MU04_BUSY_COUNTER_MU04_Busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU04_BUSY_COUNTER_MU04_Busy_SHIFT)) & IRIS_MVPL_MU04_BUSY_COUNTER_MU04_Busy_MASK) /*! @} */ /*! @name MU04_TRANSFER_COUNTER - Measurement Unit 4 Transfer Counter */ /*! @{ */ #define IRIS_MVPL_MU04_TRANSFER_COUNTER_MU04_Transfer_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU04_TRANSFER_COUNTER_MU04_Transfer_SHIFT (0U) #define IRIS_MVPL_MU04_TRANSFER_COUNTER_MU04_Transfer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU04_TRANSFER_COUNTER_MU04_Transfer_SHIFT)) & IRIS_MVPL_MU04_TRANSFER_COUNTER_MU04_Transfer_MASK) /*! @} */ /*! @name MU04_ADDRBUSY_COUNTER - Measurement Unit 4 Address Busy Cycle Counter */ /*! @{ */ #define IRIS_MVPL_MU04_ADDRBUSY_COUNTER_MU04_Addrbusy_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU04_ADDRBUSY_COUNTER_MU04_Addrbusy_SHIFT (0U) #define IRIS_MVPL_MU04_ADDRBUSY_COUNTER_MU04_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU04_ADDRBUSY_COUNTER_MU04_Addrbusy_SHIFT)) & IRIS_MVPL_MU04_ADDRBUSY_COUNTER_MU04_Addrbusy_MASK) /*! @} */ /*! @name MU04_LATENCY_COUNTER - Measurement Unit 4 Latency Counter */ /*! @{ */ #define IRIS_MVPL_MU04_LATENCY_COUNTER_MU04_Latency_MASK (0xFFFFFFFFU) #define IRIS_MVPL_MU04_LATENCY_COUNTER_MU04_Latency_SHIFT (0U) #define IRIS_MVPL_MU04_LATENCY_COUNTER_MU04_Latency(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MU04_LATENCY_COUNTER_MU04_Latency_SHIFT)) & IRIS_MVPL_MU04_LATENCY_COUNTER_MU04_Latency_MASK) /*! @} */ /*! @name TCON1_SSQCNTS - The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field */ /*! @{ */ #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQY_MASK (0x7FFFU) #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQY_SHIFT (0U) /*! SSQCNTS_SEQY - Y scan position */ #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQY_SHIFT)) & IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQY_MASK) #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_FIELD_MASK (0x8000U) #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_FIELD_SHIFT (15U) /*! SSQCNTS_FIELD - Field: 0b=odd field, 1b=even field */ #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_FIELD_SHIFT)) & IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_FIELD_MASK) #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQX_MASK (0x7FFF0000U) #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQX_SHIFT (16U) /*! SSQCNTS_SEQX - X scan position */ #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQX_SHIFT)) & IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQX_MASK) #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_OUT_MASK (0x80000000U) #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_OUT_SHIFT (31U) /*! SSQCNTS_OUT - This bit holds the value (0,1) to be output when the X/Y scan position is reached. */ #define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_OUT(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_OUT_SHIFT)) & IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_OUT_MASK) /*! @} */ /*! * @} */ /* end of group IRIS_MVPL_Register_Masks */ /* IRIS_MVPL - Peripheral instance base addresses */ /** Peripheral DC__IRIS_MVPL base address */ #define DC__IRIS_MVPL_BASE (0x561B0000u) /** Peripheral DC__IRIS_MVPL base pointer */ #define DC__IRIS_MVPL ((IRIS_MVPL_Type *)DC__IRIS_MVPL_BASE) /** Array initializer of IRIS_MVPL peripheral base addresses */ #define IRIS_MVPL_BASE_ADDRS { DC__IRIS_MVPL_BASE } /** Array initializer of IRIS_MVPL peripheral base pointers */ #define IRIS_MVPL_BASE_PTRS { DC__IRIS_MVPL } /*! * @} */ /* end of group IRIS_MVPL_Peripheral_Access_Layer */ /*! * @brief DPU IRQn. */ typedef enum DPU_IRQSTEER_IRQn { /* DISPLAY_INT_OUT0 */ CmdSeqError_DPU_IRQn = 0, SoftwareInt0_DPU_IRQn = 1, SoftwareInt1_DPU_IRQn = 2, SoftwareInt2_DPU_IRQn = 3, SoftwareInt3_DPU_IRQn = 4, /* DISPLAY_INT_OUT2 */ ExtDst0ShadowLoad_DPU_IRQn = 128, ExtDst0FrameComplete_DPU_IRQn = 129, ExtDst0SeqComplete_DPU_IRQn = 130, ExtDst4ShadowLoad_DPU_IRQn = 131, ExtDst4FrameComplete_DPU_IRQn = 132, ExtDst4SeqComplete_DPU_IRQn = 133, Display0ShadowLoad_DPU_IRQn = 136, Display0FrameComplete_DPU_IRQn = 137, Display0SeqComplete_DPU_IRQn = 138, FrameGen0Int0_DPU_IRQn = 139, FrameGen0Int1_DPU_IRQn = 140, FrameGen0Int2_DPU_IRQn = 141, FrameGen0Int3_DPU_IRQn = 142, Sig0ShadowLoad_DPU_IRQn = 143, Sig0Valid_DPU_IRQn = 144, Sig0Error_DPU_IRQn = 145, FrameGen0PrimSyncOn_DPU_IRQn = 146, FrameGen0PrimSyncOff_DPU_IRQn = 147, FrameGen0SecSyncOn_DPU_IRQn = 148, FrameGen0SecSyncOff_DPU_IRQn = 149, /* DISPLAY_INT_OUT4 */ ExtDst1ShadowLoad_DPU_IRQn = 256, ExtDst1FrameComplete_DPU_IRQn = 257, ExtDst1SeqComplete_DPU_IRQn = 258, ExtDst5ShadowLoad_DPU_IRQn = 259, ExtDst5FrameComplete_DPU_IRQn = 260, ExtDst5SeqComplete_DPU_IRQn = 261, Display1ShadowLoad_DPU_IRQn = 263, Display1FrameComplete_DPU_IRQn = 264, Display1SeqComplete_DPU_IRQn = 265, FrameGen1Int0_DPU_IRQn = 266, FrameGen1Int1_DPU_IRQn = 267, FrameGen1Int2_DPU_IRQn = 268, FrameGen1Int3_DPU_IRQn = 269, Sig1ShadowLoad_DPU_IRQn = 270, Sig1Valid_DPU_IRQn = 271, Sig1Error_DPU_IRQn = 272, FrameGen1PrimSyncOn_DPU_IRQn = 273, FrameGen1PrimSyncOff_DPU_IRQn = 274, FrameGen1SecSyncOn_DPU_IRQn = 275, FrameGen1SecSyncOff_DPU_IRQn = 276, /* DISPLAY_INT_OUT7 */ Store9ShadowLoad_DPU_IRQn = 448, Store9FrameComplete_DPU_IRQn = 449, Store9SeqComplete_DPU_IRQn = 450, } DPU_IRQSTEER_IRQn_Type; /* ---------------------------------------------------------------------------- -- IRQSTEER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IRQSTEER_Peripheral_Access_Layer IRQSTEER Peripheral Access Layer * @{ */ /** IRQSTEER - Register Layout Typedef */ typedef struct { __IO uint32_t CHANnCTL; /**< Channel n Control Register, offset: 0x0 */ __IO uint32_t CHn_MASK[16]; /**< Channel n Interrupt Mask Register, array offset: 0x4, array step: 0x4 */ __IO uint32_t CHn_SET[16]; /**< Channel n Interrupt Set Register, array offset: 0x44, array step: 0x4 */ __I uint32_t CHn_STATUS[16]; /**< Channel n Interrupt Status Register, array offset: 0x84, array step: 0x4 */ __IO uint32_t CHn_MINTDIS; /**< Channel n Master Interrupt Disable Register, offset: 0xC4 */ __I uint32_t CHn_MSTRSTAT; /**< Channel n Master Status Register, offset: 0xC8 */ } IRQSTEER_Type; /* ---------------------------------------------------------------------------- -- IRQSTEER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IRQSTEER_Register_Masks IRQSTEER Register Masks * @{ */ /*! @name CHANnCTL - Channel n Control Register */ /*! @{ */ #define IRQSTEER_CHANnCTL_CH0_MASK (0x1U) #define IRQSTEER_CHANnCTL_CH0_SHIFT (0U) /*! CH0 - Channel 0 control * 0b0..Disable channel 0 * 0b1..Enable channel 0 */ #define IRQSTEER_CHANnCTL_CH0(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH0_SHIFT)) & IRQSTEER_CHANnCTL_CH0_MASK) #define IRQSTEER_CHANnCTL_CH1_MASK (0x2U) #define IRQSTEER_CHANnCTL_CH1_SHIFT (1U) /*! CH1 - Channel 1 control * 0b0..Disable channel 1 * 0b1..Enable channel 1 */ #define IRQSTEER_CHANnCTL_CH1(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH1_SHIFT)) & IRQSTEER_CHANnCTL_CH1_MASK) #define IRQSTEER_CHANnCTL_CH2_MASK (0x4U) #define IRQSTEER_CHANnCTL_CH2_SHIFT (2U) /*! CH2 - Channel 2 control * 0b0..Disable channel 2 * 0b1..Enable channel 2 */ #define IRQSTEER_CHANnCTL_CH2(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH2_SHIFT)) & IRQSTEER_CHANnCTL_CH2_MASK) #define IRQSTEER_CHANnCTL_CH3_MASK (0x8U) #define IRQSTEER_CHANnCTL_CH3_SHIFT (3U) /*! CH3 - Channel 3 control * 0b0..Disable channel 3 * 0b1..Enable channel 3 */ #define IRQSTEER_CHANnCTL_CH3(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH3_SHIFT)) & IRQSTEER_CHANnCTL_CH3_MASK) #define IRQSTEER_CHANnCTL_CH4_MASK (0x10U) #define IRQSTEER_CHANnCTL_CH4_SHIFT (4U) /*! CH4 - Channel 4 control * 0b0..Disable channel 4 * 0b1..Enable channel 4 */ #define IRQSTEER_CHANnCTL_CH4(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH4_SHIFT)) & IRQSTEER_CHANnCTL_CH4_MASK) /*! @} */ /*! @name CHn_MASK - Channel n Interrupt Mask Register */ /*! @{ */ #define IRQSTEER_CHn_MASK_MASKFLD_MASK (0xFFFFFFFFU) #define IRQSTEER_CHn_MASK_MASKFLD_SHIFT (0U) /*! MASKFLD - Mask bits * 0b00000000000000000000000000000000..Mask interrupt * 0b00000000000000000000000000000001..Do not mask interrupt */ #define IRQSTEER_CHn_MASK_MASKFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MASK_MASKFLD_SHIFT)) & IRQSTEER_CHn_MASK_MASKFLD_MASK) /*! @} */ /* The count of IRQSTEER_CHn_MASK */ #define IRQSTEER_CHn_MASK_COUNT (16U) /*! @name CHn_SET - Channel n Interrupt Set Register */ /*! @{ */ #define IRQSTEER_CHn_SET_FORCEFLD_MASK (0xFFFFFFFFU) #define IRQSTEER_CHn_SET_FORCEFLD_SHIFT (0U) /*! FORCEFLD - Brief bitfield description. * 0b00000000000000000000000000000000..Normal operation * 0b00000000000000000000000000000001..Force interrupt */ #define IRQSTEER_CHn_SET_FORCEFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_SET_FORCEFLD_SHIFT)) & IRQSTEER_CHn_SET_FORCEFLD_MASK) /*! @} */ /* The count of IRQSTEER_CHn_SET */ #define IRQSTEER_CHn_SET_COUNT (16U) /*! @name CHn_STATUS - Channel n Interrupt Status Register */ /*! @{ */ #define IRQSTEER_CHn_STATUS_STATUS_MASK (0xFFFFFFFFU) #define IRQSTEER_CHn_STATUS_STATUS_SHIFT (0U) /*! STATUS - Status of an interrupt * 0b00000000000000000000000000000000..Interrupt is not set. * 0b00000000000000000000000000000001..Interrupt is set. */ #define IRQSTEER_CHn_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_STATUS_STATUS_SHIFT)) & IRQSTEER_CHn_STATUS_STATUS_MASK) /*! @} */ /* The count of IRQSTEER_CHn_STATUS */ #define IRQSTEER_CHn_STATUS_COUNT (16U) /*! @name CHn_MINTDIS - Channel n Master Interrupt Disable Register */ /*! @{ */ #define IRQSTEER_CHn_MINTDIS_DISABLE_MASK (0xFFU) #define IRQSTEER_CHn_MINTDIS_DISABLE_SHIFT (0U) /*! DISABLE - Each bit of this field disables the corresponding interrupts in table above. * 0b00000000..Enable interrupts * 0b00000001..Disable interrupts */ #define IRQSTEER_CHn_MINTDIS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MINTDIS_DISABLE_SHIFT)) & IRQSTEER_CHn_MINTDIS_DISABLE_MASK) /*! @} */ /*! @name CHn_MSTRSTAT - Channel n Master Status Register */ /*! @{ */ #define IRQSTEER_CHn_MSTRSTAT_STATUS_MASK (0x1U) #define IRQSTEER_CHn_MSTRSTAT_STATUS_SHIFT (0U) /*! STATUS - Status of all interrupts * 0b0..No interrupts are asserted. * 0b1..At least one interrupt is asserted. */ #define IRQSTEER_CHn_MSTRSTAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MSTRSTAT_STATUS_SHIFT)) & IRQSTEER_CHn_MSTRSTAT_STATUS_MASK) /*! @} */ /*! * @} */ /* end of group IRQSTEER_Register_Masks */ /* IRQSTEER - Peripheral instance base addresses */ /** Peripheral IRQSTEER base address */ #define IRQSTEER_BASE (0x51070000u) /** Peripheral IRQSTEER base pointer */ #define IRQSTEER ((IRQSTEER_Type *)IRQSTEER_BASE) /** Array initializer of IRQSTEER peripheral base addresses */ #define IRQSTEER_BASE_ADDRS { IRQSTEER_BASE } /** Array initializer of IRQSTEER peripheral base pointers */ #define IRQSTEER_BASE_PTRS { IRQSTEER } /* Backward compatibility */ #define DPU0_IRQSTEER_BASE (0x56000000u) #define DPU0_IRQSTEER ((IRQSTEER_Type *)DPU0_IRQSTEER_BASE) #define IRQSTEER_IRQS { IRQSTEER_0_IRQn, IRQSTEER_1_IRQn, IRQSTEER_2_IRQn, IRQSTEER_3_IRQn, IRQSTEER_4_IRQn, IRQSTEER_5_IRQn, IRQSTEER_6_IRQn, IRQSTEER_7_IRQn } /*! * @} */ /* end of group IRQSTEER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ISI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer * @{ */ /** ISI - Register Layout Typedef */ typedef struct { __IO uint32_t CHNL_CTRL; /**< Channel Control Register, offset: 0x0 */ __IO uint32_t CHNL_IMG_CTRL; /**< Channel Image Control Register, offset: 0x4 */ __IO uint32_t CHNL_OUT_BUF_CTRL; /**< Channel Output Buffer Control Register, offset: 0x8 */ __IO uint32_t CHNL_IMG_CFG; /**< Channel Image Configuration, offset: 0xC */ __IO uint32_t CHNL_IER; /**< Channel Interrupt Enable Register, offset: 0x10 */ __IO uint32_t CHNL_STS; /**< Channel Status Register, offset: 0x14 */ __IO uint32_t CHNL_SCALE_FACTOR; /**< Channel Scale Factor Register, offset: 0x18 */ __IO uint32_t CHNL_SCALE_OFFSET; /**< Channel Scale Offset Register, offset: 0x1C */ __IO uint32_t CHNL_CROP_ULC; /**< Channel Crop Upper Left Corner Coordinate Register, offset: 0x20 */ __IO uint32_t CHNL_CROP_LRC; /**< Channel Crop Lower Right Corner Coordinate Register, offset: 0x24 */ __IO uint32_t CHNL_CSC_COEFF0; /**< Channel Color Space Conversion Coefficient Register 0, offset: 0x28 */ __IO uint32_t CHNL_CSC_COEFF1; /**< Channel Color Space Conversion Coefficient Register 1, offset: 0x2C */ __IO uint32_t CHNL_CSC_COEFF2; /**< Channel Color Space Conversion Coefficient Register 2, offset: 0x30 */ __IO uint32_t CHNL_CSC_COEFF3; /**< Channel Color Space Conversion Coefficient Register 3, offset: 0x34 */ __IO uint32_t CHNL_CSC_COEFF4; /**< Channel Color Space Conversion Coefficient Register 4, offset: 0x38 */ __IO uint32_t CHNL_CSC_COEFF5; /**< Channel Color Space Conversion Coefficient Register 5, offset: 0x3C */ struct { /* offset: 0x40, array step: 0xC */ __IO uint32_t CHNL_ROI_ALPHA; /**< Channel Alpha Value Register for Region of Interest 0..Channel Alpha Value Register for Region of Interest 3, array offset: 0x40, array step: 0xC */ __IO uint32_t CHNL_ROI_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 0..Channel Upper Left Coordinate Register for Region of Interest 3, array offset: 0x44, array step: 0xC */ __IO uint32_t CHNL_ROI_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 0..Channel Lower Right Coordinate Register for Region of Interest 3, array offset: 0x48, array step: 0xC */ } ROI[4]; __IO uint32_t CHNL_OUT_BUF1_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */ __IO uint32_t CHNL_OUT_BUF1_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */ __IO uint32_t CHNL_OUT_BUF1_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */ __IO uint32_t CHNL_OUT_BUF_PITCH; /**< Channel Output Buffer Pitch, offset: 0x7C */ __IO uint32_t CHNL_IN_BUF_ADDR; /**< Channel Input Buffer Address, offset: 0x80 */ __IO uint32_t CHNL_IN_BUF_PITCH; /**< Channel Input Buffer Pitch, offset: 0x84 */ __IO uint32_t CHNL_MEM_RD_CTRL; /**< Channel Memory Read Control, offset: 0x88 */ __IO uint32_t CHNL_OUT_BUF2_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */ __IO uint32_t CHNL_OUT_BUF2_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */ __IO uint32_t CHNL_OUT_BUF2_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */ __IO uint32_t CHNL_SCL_IMG_CFG; /**< Channel Scaled Image Configuration, offset: 0x98 */ } ISI_Type; /* ---------------------------------------------------------------------------- -- ISI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ISI_Register_Masks ISI Register Masks * @{ */ /*! @name CHNL_CTRL - Channel Control Register */ /*! @{ */ #define ISI_CHNL_CTRL_SRC_MASK (0x7U) #define ISI_CHNL_CTRL_SRC_SHIFT (0U) /*! SRC - Input image source port selection * 0b000..Image will be sourced from input port 0 of the Pixel Link Crossbar * 0b001..Image will be sourced from input port 1 of the Pixel Link Crossbar * 0b010..Image will be sourced from input port 2 of the Pixel Link Crossbar * 0b011..Image will be sourced from input port 3 of the Pixel Link Crossbar * 0b100..Image will be sourced from input port 4 of the Pixel Link Crossbar * 0b101..Image will be sourced from input port 5 of the Pixel Link Crossbar (Input port 5 connected to AXI read) * 0b110..Reserved * 0b111..Reserved */ #define ISI_CHNL_CTRL_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK) #define ISI_CHNL_CTRL_SRC_TYPE_MASK (0x10U) #define ISI_CHNL_CTRL_SRC_TYPE_SHIFT (4U) /*! SRC_TYPE - Type of selected input image source * 0b0..Image input source is MIPI CSI, Display Controller or HDMI Rx * 0b1..Image input source is Memory */ #define ISI_CHNL_CTRL_SRC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK) #define ISI_CHNL_CTRL_MIPI_VC_ID_MASK (0xC0U) #define ISI_CHNL_CTRL_MIPI_VC_ID_SHIFT (6U) /*! MIPI_VC_ID - Virtual channel ID * 0b00..Virtual Channel 0 selected or no virtual channel used * 0b01..Virtual Channel 1 selected * 0b10..Virtual Channel 2 selected * 0b11..Virtual Channel 3 selected */ #define ISI_CHNL_CTRL_MIPI_VC_ID(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_MIPI_VC_ID_SHIFT)) & ISI_CHNL_CTRL_MIPI_VC_ID_MASK) #define ISI_CHNL_CTRL_SEC_LB_SRC_MASK (0x700U) #define ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT (8U) /*! SEC_LB_SRC - Secondary line buffer source */ #define ISI_CHNL_CTRL_SEC_LB_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT)) & ISI_CHNL_CTRL_SEC_LB_SRC_MASK) #define ISI_CHNL_CTRL_BLANK_PXL_MASK (0xFF0000U) #define ISI_CHNL_CTRL_BLANK_PXL_SHIFT (16U) /*! BLANK_PXL - Blank pixel value * 0b11111111..Default value * 0b00000000..Black color */ #define ISI_CHNL_CTRL_BLANK_PXL(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_BLANK_PXL_SHIFT)) & ISI_CHNL_CTRL_BLANK_PXL_MASK) #define ISI_CHNL_CTRL_SW_RST_MASK (0x1000000U) #define ISI_CHNL_CTRL_SW_RST_SHIFT (24U) /*! SW_RST - Software reset bit * 0b0..No Reset * 0b1..Channel pipeline is under software reset */ #define ISI_CHNL_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK) #define ISI_CHNL_CTRL_CHAIN_BUF_MASK (0x6000000U) #define ISI_CHNL_CTRL_CHAIN_BUF_SHIFT (25U) /*! CHAIN_BUF - Chain line buffer control * 0b00..No line buffers chained (supports 2048 or less horizontal resolution) * 0b01..2 line buffers chained (supports 4096 horizontal resolution). Line buffers of channels 'n' and 'n+1' are chained. * 0b10..Reserved for future use * 0b11..Reserved for future use */ #define ISI_CHNL_CTRL_CHAIN_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHAIN_BUF_SHIFT)) & ISI_CHNL_CTRL_CHAIN_BUF_MASK) #define ISI_CHNL_CTRL_CHNL_BYPASS_MASK (0x20000000U) #define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT (29U) /*! CHNL_BYPASS - Channel bypass enable * 0b0..Channel is not bypassed * 0b1..Channel is bypassed */ #define ISI_CHNL_CTRL_CHNL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK) #define ISI_CHNL_CTRL_CLK_EN_MASK (0x40000000U) #define ISI_CHNL_CTRL_CLK_EN_SHIFT (30U) /*! CLK_EN - Channel clock enable * 0b0..Channel processing clock is disabled * 0b1..Channel processing clock is enabled */ #define ISI_CHNL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK) #define ISI_CHNL_CTRL_CHNL_EN_MASK (0x80000000U) #define ISI_CHNL_CTRL_CHNL_EN_SHIFT (31U) /*! CHNL_EN - Enable channel processing * 0b0..Processing channel is disabled * 0b1..Processing channel is enabled */ #define ISI_CHNL_CTRL_CHNL_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK) /*! @} */ /*! @name CHNL_IMG_CTRL - Channel Image Control Register */ /*! @{ */ #define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK (0x1U) #define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT (0U) /*! CSC_BYP - Color Space Conversion bypass control * 0b0..CSC is operational * 0b1..CSC is bypassed */ #define ISI_CHNL_IMG_CTRL_CSC_BYP(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK) #define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK (0x6U) #define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT (1U) /*! CSC_MODE - Color Space Conversion operating mode * 0b00..Convert from YUV to RGB * 0b01..Convert from YCbCr to RGB * 0b10..Convert from RGB to YUV * 0b11..Convert from RGB to YCbCr */ #define ISI_CHNL_IMG_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK) #define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK (0x8U) #define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT (3U) /*! YCBCR_MODE - YCbCr Mode * 0b0..YCbCr mode is disabled * 0b1..YCbCr mode is enabled */ #define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK) #define ISI_CHNL_IMG_CTRL_RSVD2_MASK (0x10U) #define ISI_CHNL_IMG_CTRL_RSVD2_SHIFT (4U) /*! RSVD2 - Reserved field. Reads only zeros */ #define ISI_CHNL_IMG_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD2_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD2_MASK) #define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK (0x20U) #define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT (5U) /*! HFLIP_EN - Horizontal flip control * 0b0..Horizantal image flip disabled * 0b1..Horizontal image flip enabled */ #define ISI_CHNL_IMG_CTRL_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK) #define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK (0x40U) #define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT (6U) /*! VFLIP_EN - Veritical flip control * 0b0..Vertical image flip disabled * 0b1..Vertical image flip enabled */ #define ISI_CHNL_IMG_CTRL_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK) #define ISI_CHNL_IMG_CTRL_CROP_EN_MASK (0x80U) #define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT (7U) /*! CROP_EN - Output image cropping enable * 0b0..Image cropping is disabled * 0b1..Image cropping is enabled */ #define ISI_CHNL_IMG_CTRL_CROP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK) #define ISI_CHNL_IMG_CTRL_DEC_Y_MASK (0x300U) #define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT (8U) /*! DEC_Y - Vertical pre-decimation control * 0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational. * 0b01..Decimate by 2 * 0b10..Decimate by 4 * 0b11..Decimate by 8 */ #define ISI_CHNL_IMG_CTRL_DEC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK) #define ISI_CHNL_IMG_CTRL_DEC_X_MASK (0xC00U) #define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT (10U) /*! DEC_X - Horizontal pre-decimation control * 0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational. * 0b01..Decimate by 2 * 0b10..Decimate by 4 * 0b11..Decimate by 8 */ #define ISI_CHNL_IMG_CTRL_DEC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK) #define ISI_CHNL_IMG_CTRL_DEINT_MASK (0x7000U) #define ISI_CHNL_IMG_CTRL_DEINT_SHIFT (12U) /*! DEINT - De-interlace control * 0b000, 0b001..No de-interlacing done * 0b010..Weave de-interlacing (Odd, Even) method used * 0b011..Weave de-interlacing (Even, Odd) method used * 0b100..Blending or linear interpolation (Odd + Even) de-interlacing method used * 0b101..Blending or linear interpolation (Even + Odd) de-interlacing method used * 0b110, 0b111..Line doubling de-interlacing method used. Both Odd and Even fields are doubled. */ #define ISI_CHNL_IMG_CTRL_DEINT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK (0x8000U) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT (15U) /*! GBL_ALPHA_EN - Global alpha value insertion enable * 0b0..Global Alpha value insertion is disabled * 0b1..Global Alpha value insertion is enabled */ #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK (0xFF0000U) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT (16U) /*! GBL_ALPHA_VAL - Global alpha value * 0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels */ #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK) #define ISI_CHNL_IMG_CTRL_FORMAT_MASK (0x3F000000U) #define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT (24U) /*! FORMAT - Output image format * 0b000000..RGBA8888 - RGB format with alpha in LSB; 8-bits per component. 'A' indicates alpha value. * 0b000001..ABGR8888 - BGR format with alpha in MSB; 8-bits per component. 'A' indicates alpha value. * 0b000010..ARGB8888 - RGB format with alpha in MSB; 8-bits per component. 'A' indicates alpha value. * 0b000011..RGBX888 - RGB format with 8-bits per color component (unpacked and MSB-alinged in 32-bit DWORD). 'X' indicates the waste bits. * 0b000100..XBGR888 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits. * 0b000101..XRGB888 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits. * 0b000110..RGB888P - RGB format with 8-bits per color component (packed into 24-bits). No waste bits. * 0b000111..BGR888P - BGR format with 8-bits per color component (packed into 24-bits). No waste bits. * 0b001000..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value. * 0b001001..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value. * 0b001010..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 16-bits WORD). No waste bits. * 0b001011..RAW8 - 8-bit RAW data packed into 32-bit DWORD * 0b001100..RAW10 - 10-bit RAW data packed into 16-bit WORD with 6 LSBs waste bits * 0b001101..RAW10P - 10-bit RAW data packed into 32-bit DWORD * 0b001110..RAW12 - 12-bit RAW data packed into 16-bit DWORD with 4 LSBs waste bits * 0b001111..RAW16 - 16-bit RAW data packed into 32-bit DWORD * 0b010000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes * 0b010001..YUV444_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes * 0b010010..YUV444_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes * 0b010011..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD) * 0b010100..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) * 0b010101..YUV444_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) * 0b010110..YUV444_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) * 0b010111..Reserved for future use * 0b011000..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD) * 0b011001..YUV444_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD) * 0b011010..YUV444_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD) * 0b011011..Reserved for future use * 0b011100..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b011101..YUV444_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b011110..YUV444_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b011111..Reserved for future use * 0b100000..YUV422_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes * 0b100001..YUV422_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes * 0b100010..YUV422_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes * 0b100011..Reserved for future use * 0b100100..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) * 0b100101..YUV422_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) * 0b100110..YUV422_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) * 0b100111..Reserved for future use * 0b101000..YUV422_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD) * 0b101001..YUV422_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD) * 0b101010..YUV422_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD) * 0b101011..Reserved for future use * 0b101100..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b101101..YUV422_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b101110..YUV422_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b101111..Reserved for future use * 0b110000..Reserved for future use * 0b110001..YUV420_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes * 0b110010..YUV420_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes * 0b110011..Reserved for future use * 0b110100..Reserved for future use * 0b110101..YUV420_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) * 0b110110..YUV420_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) * 0b110111..Reserved for future use * 0b111000..Reserved for future use * 0b111001..YUV420_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD) * 0b111010..YUV420_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD) * 0b111011..Reserved for future use * 0b111100..Reserved for future use * 0b111101..YUV420_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b111110..YUV420_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b111111..Reserved for future use */ #define ISI_CHNL_IMG_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK) #define ISI_CHNL_IMG_CTRL_RSVD0_MASK (0xC0000000U) #define ISI_CHNL_IMG_CTRL_RSVD0_SHIFT (30U) /*! RSVD0 - Reserved field. Reads only zeros */ #define ISI_CHNL_IMG_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD0_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD0_MASK) /*! @} */ /*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control Register */ /*! @{ */ #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK (0x3U) #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_SHIFT (0U) /*! OFLW_PANIC_SET_THD_Y - Overflow panic set threshold value for Y/RGB output buffer * 0b00..No panic alert will be asserted * 0b01..Panic will assert when the buffers are 25% full (i.e. have 128 bytes) * 0b10..Panic will assert when the buffers are 50% full (i.e. have 256 bytes) * 0b11..Panic will assert when the buffers are 75% full (i.e. have 384 bytes) */ #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK) #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK (0x18U) #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_SHIFT (3U) /*! OFLW_PANIC_SET_THD_U - Overflow panic set threshold value for U output buffer * 0b00..No panic alert will be asserted * 0b01..Panic will assert when the buffers are 25% full (i.e. have 128 bytes) * 0b10..Panic will assert when the buffers are 50% full (i.e. have 256 bytes) * 0b11..Panic will assert when the buffers are 75% full (i.e. have 384 bytes) */ #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK) #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK (0xC0U) #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_SHIFT (6U) /*! OFLW_PANIC_SET_THD_V - Overflow panic set threshold value for V output buffer * 0b00..No panic alert will be asserted * 0b01..Panic will assert when the buffers are 25% full (i.e. have 128 bytes) * 0b10..Panic will assert when the buffers are 50% full (i.e. have 256 bytes) * 0b11..Panic will assert when the buffers are 75% full (i.e. have 384 bytes) */ #define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U) /*! LOAD_BUF1_ADDR - Load Buffer 1 Address from CHNLOUT_BUF1_ADDR_* registers */ #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U) /*! LOAD_BUF2_ADDR - Load Buffer 2 Address from CHNLOUT_BUF2_ADDR_* registers */ #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK) /*! @} */ /*! @name CHNL_IMG_CFG - Channel Image Configuration */ /*! @{ */ #define ISI_CHNL_IMG_CFG_WIDTH_MASK (0x1FFFU) #define ISI_CHNL_IMG_CFG_WIDTH_SHIFT (0U) /*! WIDTH - Input image width (pixels) */ #define ISI_CHNL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK) #define ISI_CHNL_IMG_CFG_RSVD0_MASK (0xE000U) #define ISI_CHNL_IMG_CFG_RSVD0_SHIFT (13U) /*! RSVD0 - Reserved field. Reads only zeros. */ #define ISI_CHNL_IMG_CFG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD0_MASK) #define ISI_CHNL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U) #define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT (16U) /*! HEIGHT - Input image height (lines) */ #define ISI_CHNL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK) #define ISI_CHNL_IMG_CFG_RSVD1_MASK (0xE0000000U) #define ISI_CHNL_IMG_CFG_RSVD1_SHIFT (29U) /*! RSVD1 - Reserved field. Reads only zeros. */ #define ISI_CHNL_IMG_CFG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD1_MASK) /*! @} */ /*! @name CHNL_IER - Channel Interrupt Enable Register */ /*! @{ */ #define ISI_CHNL_IER_RSVD0_MASK (0x3FFFU) #define ISI_CHNL_IER_RSVD0_SHIFT (0U) /*! RSVD0 - Reserved field. Reads only zeros. */ #define ISI_CHNL_IER_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_RSVD0_SHIFT)) & ISI_CHNL_IER_RSVD0_MASK) #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK (0x4000U) #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT (14U) /*! LATE_VSYNC_ERR_EN - VSYNC timing (Late) error interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK) #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK (0x8000U) #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT (15U) /*! EARLY_VSYNC_ERR_EN - VSYNC timing (Early) error interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK) #define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK (0x10000U) #define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT (16U) /*! OFLW_Y_BUF_EN - Y output buffer overflow interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_OFLW_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK) #define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_MASK (0x20000U) #define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_SHIFT (17U) /*! EXCS_OFLW_Y_BUF_EN - Y output buffer excess overflow interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_MASK) #define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_MASK (0x40000U) #define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_SHIFT (18U) /*! OFLW_PANIC_Y_BUF_EN - Y output buffer potential overflow panic interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_MASK) #define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK (0x80000U) #define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT (19U) /*! OFLW_U_BUF_EN - U output buffer overflow interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_OFLW_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK) #define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_MASK (0x100000U) #define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_SHIFT (20U) /*! EXCS_OFLW_U_BUF_EN - U output buffer excess overflow interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_MASK) #define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_MASK (0x200000U) #define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_SHIFT (21U) /*! OFLW_PANIC_U_BUF_EN - U output buffer potential overflow panic interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_MASK) #define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK (0x400000U) #define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT (22U) /*! OFLW_V_BUF_EN - V output buffer overflow interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_OFLW_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK) #define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_MASK (0x800000U) #define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_SHIFT (23U) /*! EXCS_OFLW_V_BUF_EN - V output buffer excess overflow interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_MASK) #define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_MASK (0x1000000U) #define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_SHIFT (24U) /*! OFLW_PANIC_V_BUF_EN - V output buffer potential overflow panic interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_MASK) #define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK (0x2000000U) #define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT (25U) /*! AXI_RD_ERR_EN - AXI bus read error interrupt enable bit (Channel 0 only) * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_AXI_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK) #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK (0x4000000U) #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT (26U) /*! AXI_WR_ERR_Y_EN - AXI bus read error interrupt enable bit for Y/RGB data buffer * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK) #define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK (0x8000000U) #define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT (27U) /*! AXI_WR_ERR_U_EN - AXI bus read error interrupt enable bit for U data buffer * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK) #define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK (0x10000000U) #define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT (28U) /*! AXI_WR_ERR_V_EN - AXI bus read error interrupt enable bit for V data buffer * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK) #define ISI_CHNL_IER_FRM_RCVD_EN_MASK (0x20000000U) #define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT (29U) /*! FRM_RCVD_EN - Frame received interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_FRM_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK) #define ISI_CHNL_IER_LINE_RCVD_EN_MASK (0x40000000U) #define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT (30U) /*! LINE_RCVD_EN - Line received interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_LINE_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK) #define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK (0x80000000U) #define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT (31U) /*! MEM_RD_DONE_EN - Memory read complete interrupt enable bit * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ISI_CHNL_IER_MEM_RD_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK) /*! @} */ /*! @name CHNL_STS - Channel Status Register */ /*! @{ */ #define ISI_CHNL_STS_OFLW_BYTES_MASK (0xFFU) #define ISI_CHNL_STS_OFLW_BYTES_SHIFT (0U) /*! OFLW_BYTES - Number of bytes lost during an overflow event * 0b00000000..No overflow * 0b00000001-0b11111111..Total bytes lost during an overflow event */ #define ISI_CHNL_STS_OFLW_BYTES(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_BYTES_SHIFT)) & ISI_CHNL_STS_OFLW_BYTES_MASK) #define ISI_CHNL_STS_BUF1_ACTIVE_MASK (0x100U) #define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT (8U) /*! BUF1_ACTIVE - Current frame being stored in Buffer 1 Address * 0b0..Buffer 1 Address inactive * 0b1..Buffer 1 Address in use */ #define ISI_CHNL_STS_BUF1_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK) #define ISI_CHNL_STS_BUF2_ACTIVE_MASK (0x200U) #define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT (9U) /*! BUF2_ACTIVE - Current frame being stored in Buffer 2 Address * 0b0..Buffer 2 Address inactive * 0b1..Buffer 2 Address in use */ #define ISI_CHNL_STS_BUF2_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK) #define ISI_CHNL_STS_MEM_RD_OFLOW_MASK (0x400U) #define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT (10U) /*! MEM_RD_OFLOW - Memory read FIFO overflow error status * 0b0..No overflow occurred during memory read * 0b1..FIFO overflow occurred during memory read */ #define ISI_CHNL_STS_MEM_RD_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK) #define ISI_CHNL_STS_RSVD1_MASK (0x3800U) #define ISI_CHNL_STS_RSVD1_SHIFT (11U) /*! RSVD1 - Reserved field. Reads only zeros. */ #define ISI_CHNL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_RSVD1_SHIFT)) & ISI_CHNL_STS_RSVD1_MASK) #define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK (0x4000U) #define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT (14U) /*! LATE_VSYNC_ERR - VSYNC timing (Late) error interrupt flag * 0b0..No error * 0b1..VSYNC detected later than expected */ #define ISI_CHNL_STS_LATE_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK) #define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK (0x8000U) #define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT (15U) /*! EARLY_VSYNC_ERR - VSYNC timing (Early) error interrupt flag * 0b0..No error * 0b1..VSYNC detected earlier than expected */ #define ISI_CHNL_STS_EARLY_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK) #define ISI_CHNL_STS_OFLW_Y_BUF_MASK (0x10000U) #define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT (16U) /*! OFLW_Y_BUF - Overflow in Y/RGB output buffer interrupt flag * 0b0..No overflow * 0b1..Overflow has occured in the channel */ #define ISI_CHNL_STS_OFLW_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK) #define ISI_CHNL_STS_EXCS_OFLW_Y_BUF_MASK (0x20000U) #define ISI_CHNL_STS_EXCS_OFLW_Y_BUF_SHIFT (17U) /*! EXCS_OFLW_Y_BUF - Y/RGB output buffer excess overflow interrupt flag * 0b0..No overflow or overflow condition within recoverable limits * 0b1..Overflow confition beyond recoverable limits */ #define ISI_CHNL_STS_EXCS_OFLW_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_Y_BUF_MASK) #define ISI_CHNL_STS_OFLW_PANIC_Y_BUF_MASK (0x40000U) #define ISI_CHNL_STS_OFLW_PANIC_Y_BUF_SHIFT (18U) /*! OFLW_PANIC_Y_BUF - Y/RGB output buffer potential overflow panic alert interrupt flag * 0b0..Buffer has not crossed the panic threshold limit * 0b1..Panic threshold limit crossed. Software must take action. */ #define ISI_CHNL_STS_OFLW_PANIC_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_Y_BUF_MASK) #define ISI_CHNL_STS_OFLW_U_BUF_MASK (0x80000U) #define ISI_CHNL_STS_OFLW_U_BUF_SHIFT (19U) /*! OFLW_U_BUF - Overflow in U output buffer interrupt flag * 0b0..No overflow * 0b1..Overflow has occured in the channel */ #define ISI_CHNL_STS_OFLW_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK) #define ISI_CHNL_STS_EXCS_OFLW_U_BUF_MASK (0x100000U) #define ISI_CHNL_STS_EXCS_OFLW_U_BUF_SHIFT (20U) /*! EXCS_OFLW_U_BUF - U output buffer excess overflow interrupt flag * 0b0..No overflow or overflow condition within recoverable limits * 0b1..Overflow confition beyond recoverable limits */ #define ISI_CHNL_STS_EXCS_OFLW_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_U_BUF_MASK) #define ISI_CHNL_STS_OFLW_PANIC_U_BUF_MASK (0x200000U) #define ISI_CHNL_STS_OFLW_PANIC_U_BUF_SHIFT (21U) /*! OFLW_PANIC_U_BUF - U output buffer potential overflow panic alert interrupt flag * 0b0..Buffer has not crossed the panic threshold limit * 0b1..Panic threshold limit crossed. Software must take action. */ #define ISI_CHNL_STS_OFLW_PANIC_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_U_BUF_MASK) #define ISI_CHNL_STS_OFLW_V_BUF_MASK (0x400000U) #define ISI_CHNL_STS_OFLW_V_BUF_SHIFT (22U) /*! OFLW_V_BUF - Overflow in U output buffer interrupt flag * 0b0..No overflow * 0b1..Overflow has occured in the channel */ #define ISI_CHNL_STS_OFLW_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK) #define ISI_CHNL_STS_EXCS_OFLW_V_BUF_MASK (0x800000U) #define ISI_CHNL_STS_EXCS_OFLW_V_BUF_SHIFT (23U) /*! EXCS_OFLW_V_BUF - V output buffer excess overflow interrupt flag * 0b0..No overflow or overflow condition within recoverable limits * 0b1..Overflow confition beyond recoverable limits */ #define ISI_CHNL_STS_EXCS_OFLW_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_V_BUF_MASK) #define ISI_CHNL_STS_OFLW_PANIC_V_BUF_MASK (0x1000000U) #define ISI_CHNL_STS_OFLW_PANIC_V_BUF_SHIFT (24U) /*! OFLW_PANIC_V_BUF - V output buffer potential overflow panic alert interrupt flag * 0b0..Buffer has not crossed the panic threshold limit * 0b1..Panic threshold limit crossed. Software must take action. */ #define ISI_CHNL_STS_OFLW_PANIC_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_V_BUF_MASK) #define ISI_CHNL_STS_AXI_RD_ERR_MASK (0x2000000U) #define ISI_CHNL_STS_AXI_RD_ERR_SHIFT (25U) /*! AXI_RD_ERR - AXI Bus read error interrupt flag (Channel 0 only) * 0b0..No error * 0b1..Error occured during read */ #define ISI_CHNL_STS_AXI_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK) #define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK (0x4000000U) #define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT (26U) /*! AXI_WR_ERR_Y - AXI Bus write error interrupt flag for Y/RGB data buffer * 0b0..No error * 0b1..Error occured during write */ #define ISI_CHNL_STS_AXI_WR_ERR_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK) #define ISI_CHNL_STS_AXI_WR_ERR_U_MASK (0x8000000U) #define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT (27U) /*! AXI_WR_ERR_U - AXI Bus write error interrupt flag for U data buffer * 0b0..No error * 0b1..Error occured during write */ #define ISI_CHNL_STS_AXI_WR_ERR_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK) #define ISI_CHNL_STS_AXI_WR_ERR_V_MASK (0x10000000U) #define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT (28U) /*! AXI_WR_ERR_V - AXI Bus write error interrupt flag for V data buffer * 0b0..No error * 0b1..Error occured during write */ #define ISI_CHNL_STS_AXI_WR_ERR_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK) #define ISI_CHNL_STS_FRM_STRD_MASK (0x20000000U) #define ISI_CHNL_STS_FRM_STRD_SHIFT (29U) /*! FRM_STRD - Frame stored successfully interrupt flag * 0b0..No frame being received or in progress * 0b1..One full frame has been received and stored in memory */ #define ISI_CHNL_STS_FRM_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK) #define ISI_CHNL_STS_LINE_STRD_MASK (0x40000000U) #define ISI_CHNL_STS_LINE_STRD_SHIFT (30U) /*! LINE_STRD - Line received and stored interrupt flag * 0b0..No new line received * 0b1..New line received and stored into memory */ #define ISI_CHNL_STS_LINE_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK) #define ISI_CHNL_STS_MEM_RD_DONE_MASK (0x80000000U) #define ISI_CHNL_STS_MEM_RD_DONE_SHIFT (31U) /*! MEM_RD_DONE - Memory read complete interrupt flag * 0b0..Image read from memory not complete or not started * 0b1..Image read from memory completed */ #define ISI_CHNL_STS_MEM_RD_DONE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK) /*! @} */ /*! @name CHNL_SCALE_FACTOR - Channel Scale Factor Register */ /*! @{ */ #define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK (0x3FFFU) #define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT (0U) /*! X_SCALE - Horizontal scaling factor */ #define ISI_CHNL_SCALE_FACTOR_X_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK) #define ISI_CHNL_SCALE_FACTOR_RSVD1_MASK (0xC000U) #define ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT (14U) /*! RSVD1 - Reserved field. Reads only zeros */ #define ISI_CHNL_SCALE_FACTOR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD1_MASK) #define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK (0x3FFF0000U) #define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT (16U) /*! Y_SCALE - Vertical scaling factor */ #define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK) #define ISI_CHNL_SCALE_FACTOR_RSVD0_MASK (0xC0000000U) #define ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT (30U) /*! RSVD0 - Reserved field. Reads only zeros */ #define ISI_CHNL_SCALE_FACTOR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD0_MASK) /*! @} */ /*! @name CHNL_SCALE_OFFSET - Channel Scale Offset Register */ /*! @{ */ #define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK (0xFFFU) #define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT (0U) /*! X_OFFSET - Horizontal scaling offset */ #define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK) #define ISI_CHNL_SCALE_OFFSET_RSVD1_MASK (0xF000U) #define ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT (12U) /*! RSVD1 - Reserved field. Reads only zeros */ #define ISI_CHNL_SCALE_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD1_MASK) #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK (0xFFF0000U) #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT (16U) /*! Y_OFFSET - Vertical scaling offset */ #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK) #define ISI_CHNL_SCALE_OFFSET_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT (28U) /*! RSVD0 - Reserved field. Reads only zeros */ #define ISI_CHNL_SCALE_OFFSET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD0_MASK) /*! @} */ /*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate Register */ /*! @{ */ #define ISI_CHNL_CROP_ULC_Y_MASK (0xFFFU) #define ISI_CHNL_CROP_ULC_Y_SHIFT (0U) /*! Y - Upper Left Y-coordinate */ #define ISI_CHNL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK) #define ISI_CHNL_CROP_ULC_RSVD1_MASK (0xF000U) #define ISI_CHNL_CROP_ULC_RSVD1_SHIFT (12U) /*! RSVD1 - Reserved field. Reads only zeros */ #define ISI_CHNL_CROP_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD1_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD1_MASK) #define ISI_CHNL_CROP_ULC_X_MASK (0xFFF0000U) #define ISI_CHNL_CROP_ULC_X_SHIFT (16U) /*! X - Upper Left X-coordinate */ #define ISI_CHNL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK) #define ISI_CHNL_CROP_ULC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_CROP_ULC_RSVD0_SHIFT (28U) /*! RSVD0 - Reserved field. Reads only zeros */ #define ISI_CHNL_CROP_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD0_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD0_MASK) /*! @} */ /*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate Register */ /*! @{ */ #define ISI_CHNL_CROP_LRC_Y_MASK (0xFFFU) #define ISI_CHNL_CROP_LRC_Y_SHIFT (0U) /*! Y - Lower Right Y-coordinate */ #define ISI_CHNL_CROP_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK) #define ISI_CHNL_CROP_LRC_RSVD1_MASK (0xF000U) #define ISI_CHNL_CROP_LRC_RSVD1_SHIFT (12U) /*! RSVD1 - Reserved field. Reads only zeros */ #define ISI_CHNL_CROP_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD1_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD1_MASK) #define ISI_CHNL_CROP_LRC_X_MASK (0xFFF0000U) #define ISI_CHNL_CROP_LRC_X_SHIFT (16U) /*! X - Lower Right X-coordinate */ #define ISI_CHNL_CROP_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK) #define ISI_CHNL_CROP_LRC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_CROP_LRC_RSVD0_SHIFT (28U) /*! RSVD0 - Reserved field. Reads only zeros */ #define ISI_CHNL_CROP_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD0_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient Register 0 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF0_A1_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF0_A1_SHIFT (0U) /*! A1 - CSC Coefficient A1 value */ #define ISI_CHNL_CSC_COEFF0_A1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK) #define ISI_CHNL_CSC_COEFF0_RSVD1_MASK (0xF800U) #define ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT (11U) /*! RSVD1 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF0_A2_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF0_A2_SHIFT (16U) /*! A2 - CSC Coefficient A2 value */ #define ISI_CHNL_CSC_COEFF0_A2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK) #define ISI_CHNL_CSC_COEFF0_RSVD0_MASK (0xF8000000U) #define ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT (27U) /*! RSVD0 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient Register 1 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF1_A3_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF1_A3_SHIFT (0U) /*! A3 - CSC Coefficient A3 value */ #define ISI_CHNL_CSC_COEFF1_A3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK) #define ISI_CHNL_CSC_COEFF1_RSVD1_MASK (0xF800U) #define ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT (11U) /*! RSVD1 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF1_B1_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF1_B1_SHIFT (16U) /*! B1 - CSC Coefficient B1 value */ #define ISI_CHNL_CSC_COEFF1_B1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK) #define ISI_CHNL_CSC_COEFF1_RSVD0_MASK (0xF8000000U) #define ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT (27U) /*! RSVD0 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient Register 2 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF2_B2_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF2_B2_SHIFT (0U) /*! B2 - CSC Coefficient B2 value */ #define ISI_CHNL_CSC_COEFF2_B2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK) #define ISI_CHNL_CSC_COEFF2_RSVD1_MASK (0xF800U) #define ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT (11U) /*! RSVD1 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF2_B3_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF2_B3_SHIFT (16U) /*! B3 - CSC Coefficient B3 value */ #define ISI_CHNL_CSC_COEFF2_B3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK) #define ISI_CHNL_CSC_COEFF2_RSVD0_MASK (0xF8000000U) #define ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT (27U) /*! RSVD0 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient Register 3 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF3_C1_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF3_C1_SHIFT (0U) /*! C1 - CSC Coefficient C1 value */ #define ISI_CHNL_CSC_COEFF3_C1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK) #define ISI_CHNL_CSC_COEFF3_RSVD1_MASK (0xF800U) #define ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT (11U) /*! RSVD1 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF3_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF3_C2_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF3_C2_SHIFT (16U) /*! C2 - CSC Coefficient C2 value */ #define ISI_CHNL_CSC_COEFF3_C2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK) #define ISI_CHNL_CSC_COEFF3_RSVD0_MASK (0xF8000000U) #define ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT (27U) /*! RSVD0 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF3_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient Register 4 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF4_C3_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF4_C3_SHIFT (0U) /*! C3 - CSC Coefficient C3 value */ #define ISI_CHNL_CSC_COEFF4_C3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK) #define ISI_CHNL_CSC_COEFF4_RSVD1_MASK (0xF800U) #define ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT (11U) /*! RSVD1 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF4_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF4_D1_MASK (0x1FF0000U) #define ISI_CHNL_CSC_COEFF4_D1_SHIFT (16U) /*! D1 - CSC Coefficient D1 value */ #define ISI_CHNL_CSC_COEFF4_D1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK) #define ISI_CHNL_CSC_COEFF4_RSVD0_MASK (0xFE000000U) #define ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT (25U) /*! RSVD0 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF4_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD0_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient Register 5 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF5_D2_MASK (0x1FFU) #define ISI_CHNL_CSC_COEFF5_D2_SHIFT (0U) /*! D2 - CSC Coefficient D2 value */ #define ISI_CHNL_CSC_COEFF5_D2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK) #define ISI_CHNL_CSC_COEFF5_RSVD1_MASK (0xFE00U) #define ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT (9U) /*! RSVD1 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF5_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD1_MASK) #define ISI_CHNL_CSC_COEFF5_D3_MASK (0x1FF0000U) #define ISI_CHNL_CSC_COEFF5_D3_SHIFT (16U) /*! D3 - CSC Coefficient D3 value */ #define ISI_CHNL_CSC_COEFF5_D3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK) #define ISI_CHNL_CSC_COEFF5_RSVD0_MASK (0xFE000000U) #define ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT (25U) /*! RSVD0 - Reserved Field. Reads only zeros */ #define ISI_CHNL_CSC_COEFF5_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD0_MASK) /*! @} */ /*! @name CHNL_ROI_ALPHA - Channel Alpha Value Register for Region of Interest 0..Channel Alpha Value Register for Region of Interest 3 */ /*! @{ */ #define ISI_CHNL_ROI_ALPHA_RSVD1_MASK (0xFFFFU) #define ISI_CHNL_ROI_ALPHA_RSVD1_SHIFT (0U) /*! RSVD1 - Reserved field. Reads only zeros */ #define ISI_CHNL_ROI_ALPHA_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_ALPHA_RSVD1_MASK) #define ISI_CHNL_ROI_ALPHA_ALPHA_EN_MASK (0x10000U) #define ISI_CHNL_ROI_ALPHA_ALPHA_EN_SHIFT (16U) /*! ALPHA_EN - Alpha value insertion enable * 0b0..Alpha value insertion is disabled * 0b1..Alpha value insertion is enabled */ #define ISI_CHNL_ROI_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_ALPHA_ALPHA_EN_MASK) #define ISI_CHNL_ROI_ALPHA_RSVD0_MASK (0xFE0000U) #define ISI_CHNL_ROI_ALPHA_RSVD0_SHIFT (17U) /*! RSVD0 - Reserved field. Reads only zeros */ #define ISI_CHNL_ROI_ALPHA_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_ALPHA_RSVD0_MASK) #define ISI_CHNL_ROI_ALPHA_ALPHA_MASK (0xFF000000U) #define ISI_CHNL_ROI_ALPHA_ALPHA_SHIFT (24U) /*! ALPHA - Alpha Value to be inserted with image */ #define ISI_CHNL_ROI_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_ALPHA_ALPHA_MASK) /*! @} */ /* The count of ISI_CHNL_ROI_ALPHA */ #define ISI_CHNL_ROI_ALPHA_COUNT (4U) /*! @name CHNL_ROI_ULC - Channel Upper Left Coordinate Register for Region of Interest 0..Channel Upper Left Coordinate Register for Region of Interest 3 */ /*! @{ */ #define ISI_CHNL_ROI_ULC_Y_MASK (0xFFFU) #define ISI_CHNL_ROI_ULC_Y_SHIFT (0U) /*! Y - Upper Left Y-coordinate */ #define ISI_CHNL_ROI_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_Y_SHIFT)) & ISI_CHNL_ROI_ULC_Y_MASK) #define ISI_CHNL_ROI_ULC_RSVD1_MASK (0xF000U) #define ISI_CHNL_ROI_ULC_RSVD1_SHIFT (12U) /*! RSVD1 - Reserved field. Reads only zeros */ #define ISI_CHNL_ROI_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_ULC_RSVD1_MASK) #define ISI_CHNL_ROI_ULC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_ULC_X_SHIFT (16U) /*! X - Upper Left X-coordinate */ #define ISI_CHNL_ROI_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_X_SHIFT)) & ISI_CHNL_ROI_ULC_X_MASK) #define ISI_CHNL_ROI_ULC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_ROI_ULC_RSVD0_SHIFT (28U) /*! RSVD0 - Reserved field. Reads only zeros */ #define ISI_CHNL_ROI_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_ULC_RSVD0_MASK) /*! @} */ /* The count of ISI_CHNL_ROI_ULC */ #define ISI_CHNL_ROI_ULC_COUNT (4U) /*! @name CHNL_ROI_LRC - Channel Lower Right Coordinate Register for Region of Interest 0..Channel Lower Right Coordinate Register for Region of Interest 3 */ /*! @{ */ #define ISI_CHNL_ROI_LRC_Y_MASK (0xFFFU) #define ISI_CHNL_ROI_LRC_Y_SHIFT (0U) /*! Y - Lower Right Y-coordinate */ #define ISI_CHNL_ROI_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_Y_SHIFT)) & ISI_CHNL_ROI_LRC_Y_MASK) #define ISI_CHNL_ROI_LRC_RSVD1_MASK (0xF000U) #define ISI_CHNL_ROI_LRC_RSVD1_SHIFT (12U) /*! RSVD1 - Reserved field. Reads only zeros */ #define ISI_CHNL_ROI_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_LRC_RSVD1_MASK) #define ISI_CHNL_ROI_LRC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_LRC_X_SHIFT (16U) /*! X - Lower Right X-coordinate */ #define ISI_CHNL_ROI_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_X_SHIFT)) & ISI_CHNL_ROI_LRC_X_MASK) #define ISI_CHNL_ROI_LRC_RSVD0_MASK (0xF0000000U) #define ISI_CHNL_ROI_LRC_RSVD0_SHIFT (28U) /*! RSVD0 - Reserved field. Reads only zeros */ #define ISI_CHNL_ROI_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_LRC_RSVD0_MASK) /*! @} */ /* The count of ISI_CHNL_ROI_LRC */ #define ISI_CHNL_ROI_LRC_COUNT (4U) /*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT (0U) /*! ADDR - Starting address for the RGB or Y (luma) memory location */ #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT (0U) /*! ADDR - Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location */ #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT (0U) /*! ADDR - Starting address for the V/Cr memory location */ #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */ /*! @{ */ #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT (0U) /*! LINE_PITCH - Output Buffer Line Pitch */ #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK) /*! @} */ /*! @name CHNL_IN_BUF_ADDR - Channel Input Buffer Address */ /*! @{ */ #define ISI_CHNL_IN_BUF_ADDR_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT (0U) #define ISI_CHNL_IN_BUF_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT)) & ISI_CHNL_IN_BUF_ADDR_ADDR_MASK) /*! @} */ /*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */ /*! @{ */ #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT (0U) /*! LINE_PITCH - Line Pitch */ #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK) #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK (0xFFFF0000U) #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT (16U) /*! FRM_PITCH - Frame Pitch */ #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK) /*! @} */ /*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */ /*! @{ */ #define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK (0x1U) #define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT (0U) /*! READ_MEM - Initiate read from memory * 0b0..No reads from memory done * 0b1..Reads from memory initiated */ #define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK) #define ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK (0xFFFFFFEU) #define ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT (1U) /*! RSVD0 - Reserved field. Reads only zeros */ #define ISI_CHNL_MEM_RD_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK) #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK (0xF0000000U) #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT (28U) /*! IMG_TYPE - Input image format * 0b0000..BGR8P - BGR format with 8-bits per color component (packed into 32-bit DWORD) * 0b0001..RGB8P - RGB format with 8-bits per color component (packed into 32-bit DWORD) * 0b0010..XRGB8 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD) * 0b0011..RGBX8 - RGB format with 8-bits per color component (unpacked and MSBalinged in 32-bit DWORD) * 0b0100..XBGR8 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD) * 0b0101..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 32-bit DWORD) * 0b0110..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component * 0b0111..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component * 0b1000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes * 0b1001..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) * 0b1010..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit WORD) * 0b1011..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) * 0b1100..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD) * 0b1101..YUV422_1P8P with 8-bits per color component; 1-plane YUV interleaved packed bytes * 0b1110..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) * 0b1111..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved packed bytes (4 MSBs waste bits in 16-bit WORD) */ #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK) /*! @} */ /*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT (0U) /*! ADDR - Starting address for the RGB or Y (luma) memory location */ #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT (0U) /*! ADDR - Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location */ #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT (0U) /*! ADDR - Starting address for the V/Cr memory location */ #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK) /*! @} */ /*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */ /*! @{ */ #define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK (0x1FFFU) #define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT (0U) /*! WIDTH - Scaled image width (pixels) */ #define ISI_CHNL_SCL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK) #define ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK (0xE000U) #define ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT (13U) /*! RSVD0 - Reserved field. Reads only zeros. */ #define ISI_CHNL_SCL_IMG_CFG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK) #define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U) #define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT (16U) /*! HEIGHT - Scaled image height (lines) */ #define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK) #define ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK (0xE0000000U) #define ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT (29U) /*! RSVD1 - Reserved field. Reads only zeros. */ #define ISI_CHNL_SCL_IMG_CFG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK) /*! @} */ /*! * @} */ /* end of group ISI_Register_Masks */ /* ISI - Peripheral instance base addresses */ /** Peripheral IMAGING__ISI0 base address */ #define IMAGING__ISI0_BASE (0x58100000u) /** Peripheral IMAGING__ISI0 base pointer */ #define IMAGING__ISI0 ((ISI_Type *)IMAGING__ISI0_BASE) /** Peripheral IMAGING__ISI1 base address */ #define IMAGING__ISI1_BASE (0x58110000u) /** Peripheral IMAGING__ISI1 base pointer */ #define IMAGING__ISI1 ((ISI_Type *)IMAGING__ISI1_BASE) /** Peripheral IMAGING__ISI2 base address */ #define IMAGING__ISI2_BASE (0x58120000u) /** Peripheral IMAGING__ISI2 base pointer */ #define IMAGING__ISI2 ((ISI_Type *)IMAGING__ISI2_BASE) /** Peripheral IMAGING__ISI3 base address */ #define IMAGING__ISI3_BASE (0x58130000u) /** Peripheral IMAGING__ISI3 base pointer */ #define IMAGING__ISI3 ((ISI_Type *)IMAGING__ISI3_BASE) /** Peripheral IMAGING__ISI4 base address */ #define IMAGING__ISI4_BASE (0x58140000u) /** Peripheral IMAGING__ISI4 base pointer */ #define IMAGING__ISI4 ((ISI_Type *)IMAGING__ISI4_BASE) /** Peripheral IMAGING__ISI5 base address */ #define IMAGING__ISI5_BASE (0x58150000u) /** Peripheral IMAGING__ISI5 base pointer */ #define IMAGING__ISI5 ((ISI_Type *)IMAGING__ISI5_BASE) /** Array initializer of ISI peripheral base addresses */ #define ISI_BASE_ADDRS { IMAGING__ISI0_BASE, IMAGING__ISI1_BASE, IMAGING__ISI2_BASE, IMAGING__ISI3_BASE, IMAGING__ISI4_BASE, IMAGING__ISI5_BASE } /** Array initializer of ISI peripheral base pointers */ #define ISI_BASE_PTRS { IMAGING__ISI0, IMAGING__ISI1, IMAGING__ISI2, IMAGING__ISI3, IMAGING__ISI4, IMAGING__ISI5 } /** Interrupt vectors for the ISI peripheral type */ #define ISI_IRQS { IMAGING_PDMA_STREAM0_INT_IRQn, IMAGING_PDMA_STREAM1_INT_IRQn, IMAGING_PDMA_STREAM2_INT_IRQn, IMAGING_PDMA_STREAM3_INT_IRQn, IMAGING_PDMA_STREAM4_INT_IRQn, IMAGING_PDMA_STREAM5_INT_IRQn } /*! * @} */ /* end of group ISI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- JPEG_DEC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_DEC_Peripheral_Access_Layer JPEG_DEC Peripheral Access Layer * @{ */ /** JPEG_DEC - Register Layout Typedef */ typedef struct { union { /* offset: 0x0 */ struct { /* offset: 0x0 */ uint8_t RESERVED_0[52]; __IO uint32_t CTRL; /**< Control Register, offset: 0x34 */ } CONTROL; struct { /* offset: 0x0 */ __I uint32_t STATUS_0; /**< Status 0 Register, offset: 0x0 */ __I uint32_t STATUS_1; /**< Status 1 Register, offset: 0x4 */ __I uint32_t STATUS_2; /**< Status 2 Register, offset: 0x8 */ __I uint32_t STATUS_3; /**< Status 3 Register, offset: 0xC */ __I uint32_t STATUS_4; /**< Status 4 Register, offset: 0x10 */ __I uint32_t STATUS_5; /**< Status 5 Register, offset: 0x14 */ __I uint32_t STATUS_6; /**< Status 6 Register, offset: 0x18 */ __I uint32_t STATUS_7; /**< Status 7 Register, offset: 0x1C */ __I uint32_t STATUS_8; /**< Status 8 Register, offset: 0x20 */ __I uint32_t STATUS_9; /**< Status 9 Register, offset: 0x24 */ __I uint32_t STATUS_10; /**< Status 10 Register, offset: 0x28 */ __I uint32_t STATUS_11; /**< Status 11 Register, offset: 0x2C */ __I uint32_t STATUS_12; /**< Status 12 Register, offset: 0x30 */ } STATUS; }; } JPEG_DEC_Type; /* ---------------------------------------------------------------------------- -- JPEG_DEC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_DEC_Register_Masks JPEG_DEC Register Masks * @{ */ /*! @name CTRL - Control Register */ /*! @{ */ #define JPEG_DEC_CTRL_LP_MASK (0x1U) #define JPEG_DEC_CTRL_LP_SHIFT (0U) /*! LP - Low Power */ #define JPEG_DEC_CTRL_LP(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_CTRL_LP_SHIFT)) & JPEG_DEC_CTRL_LP_MASK) #define JPEG_DEC_CTRL_SWR_MASK (0x2U) #define JPEG_DEC_CTRL_SWR_SHIFT (1U) /*! SWR - Soft reset */ #define JPEG_DEC_CTRL_SWR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_CTRL_SWR_SHIFT)) & JPEG_DEC_CTRL_SWR_MASK) #define JPEG_DEC_CTRL_GO_MASK (0x4U) #define JPEG_DEC_CTRL_GO_SHIFT (2U) /*! GO - Low Power */ #define JPEG_DEC_CTRL_GO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_CTRL_GO_SHIFT)) & JPEG_DEC_CTRL_GO_MASK) /*! @} */ /*! @name STATUS_0 - Status 0 Register */ /*! @{ */ #define JPEG_DEC_STATUS_0_X_MASK (0xFFFFU) #define JPEG_DEC_STATUS_0_X_SHIFT (0U) /*! X - X */ #define JPEG_DEC_STATUS_0_X(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_0_X_SHIFT)) & JPEG_DEC_STATUS_0_X_MASK) /*! @} */ /*! @name STATUS_1 - Status 1 Register */ /*! @{ */ #define JPEG_DEC_STATUS_1_Y_MASK (0xFFFFU) #define JPEG_DEC_STATUS_1_Y_SHIFT (0U) /*! Y - Y */ #define JPEG_DEC_STATUS_1_Y(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_1_Y_SHIFT)) & JPEG_DEC_STATUS_1_Y_MASK) /*! @} */ /*! @name STATUS_2 - Status 2 Register */ /*! @{ */ #define JPEG_DEC_STATUS_2_HMCU_MASK (0xFFFFU) #define JPEG_DEC_STATUS_2_HMCU_SHIFT (0U) /*! HMCU - HMCU */ #define JPEG_DEC_STATUS_2_HMCU(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_2_HMCU_SHIFT)) & JPEG_DEC_STATUS_2_HMCU_MASK) /*! @} */ /*! @name STATUS_3 - Status 3 Register */ /*! @{ */ #define JPEG_DEC_STATUS_3_VMCU_MASK (0xFFFFU) #define JPEG_DEC_STATUS_3_VMCU_SHIFT (0U) /*! VMCU - VMCU */ #define JPEG_DEC_STATUS_3_VMCU(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_3_VMCU_SHIFT)) & JPEG_DEC_STATUS_3_VMCU_MASK) /*! @} */ /*! @name STATUS_4 - Status 4 Register */ /*! @{ */ #define JPEG_DEC_STATUS_4_Tq0_MASK (0x3U) #define JPEG_DEC_STATUS_4_Tq0_SHIFT (0U) /*! Tq0 - Tq0 */ #define JPEG_DEC_STATUS_4_Tq0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_4_Tq0_SHIFT)) & JPEG_DEC_STATUS_4_Tq0_MASK) #define JPEG_DEC_STATUS_4_V0_MASK (0x1CU) #define JPEG_DEC_STATUS_4_V0_SHIFT (2U) /*! V0 - V0 */ #define JPEG_DEC_STATUS_4_V0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_4_V0_SHIFT)) & JPEG_DEC_STATUS_4_V0_MASK) #define JPEG_DEC_STATUS_4_H0_MASK (0xE0U) #define JPEG_DEC_STATUS_4_H0_SHIFT (5U) /*! H0 - H0 */ #define JPEG_DEC_STATUS_4_H0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_4_H0_SHIFT)) & JPEG_DEC_STATUS_4_H0_MASK) #define JPEG_DEC_STATUS_4_C0_MASK (0xFF00U) #define JPEG_DEC_STATUS_4_C0_SHIFT (8U) /*! C0 - C0 */ #define JPEG_DEC_STATUS_4_C0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_4_C0_SHIFT)) & JPEG_DEC_STATUS_4_C0_MASK) /*! @} */ /*! @name STATUS_5 - Status 5 Register */ /*! @{ */ #define JPEG_DEC_STATUS_5_Tq1_MASK (0x3U) #define JPEG_DEC_STATUS_5_Tq1_SHIFT (0U) /*! Tq1 - Tq1 */ #define JPEG_DEC_STATUS_5_Tq1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_5_Tq1_SHIFT)) & JPEG_DEC_STATUS_5_Tq1_MASK) #define JPEG_DEC_STATUS_5_V1_MASK (0x1CU) #define JPEG_DEC_STATUS_5_V1_SHIFT (2U) /*! V1 - V1 */ #define JPEG_DEC_STATUS_5_V1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_5_V1_SHIFT)) & JPEG_DEC_STATUS_5_V1_MASK) #define JPEG_DEC_STATUS_5_H1_MASK (0xE0U) #define JPEG_DEC_STATUS_5_H1_SHIFT (5U) /*! H1 - H1 */ #define JPEG_DEC_STATUS_5_H1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_5_H1_SHIFT)) & JPEG_DEC_STATUS_5_H1_MASK) #define JPEG_DEC_STATUS_5_C1_MASK (0xFF00U) #define JPEG_DEC_STATUS_5_C1_SHIFT (8U) /*! C1 - C1 */ #define JPEG_DEC_STATUS_5_C1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_5_C1_SHIFT)) & JPEG_DEC_STATUS_5_C1_MASK) /*! @} */ /*! @name STATUS_6 - Status 6 Register */ /*! @{ */ #define JPEG_DEC_STATUS_6_Tq2_MASK (0x3U) #define JPEG_DEC_STATUS_6_Tq2_SHIFT (0U) /*! Tq2 - Tq2 */ #define JPEG_DEC_STATUS_6_Tq2(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_6_Tq2_SHIFT)) & JPEG_DEC_STATUS_6_Tq2_MASK) #define JPEG_DEC_STATUS_6_V2_MASK (0x1CU) #define JPEG_DEC_STATUS_6_V2_SHIFT (2U) /*! V2 - V2 */ #define JPEG_DEC_STATUS_6_V2(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_6_V2_SHIFT)) & JPEG_DEC_STATUS_6_V2_MASK) #define JPEG_DEC_STATUS_6_H2_MASK (0xE0U) #define JPEG_DEC_STATUS_6_H2_SHIFT (5U) /*! H2 - H2 */ #define JPEG_DEC_STATUS_6_H2(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_6_H2_SHIFT)) & JPEG_DEC_STATUS_6_H2_MASK) #define JPEG_DEC_STATUS_6_C2_MASK (0xFF00U) #define JPEG_DEC_STATUS_6_C2_SHIFT (8U) /*! C2 - C2 */ #define JPEG_DEC_STATUS_6_C2(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_6_C2_SHIFT)) & JPEG_DEC_STATUS_6_C2_MASK) /*! @} */ /*! @name STATUS_7 - Status 7 Register */ /*! @{ */ #define JPEG_DEC_STATUS_7_Tq3_MASK (0x3U) #define JPEG_DEC_STATUS_7_Tq3_SHIFT (0U) /*! Tq3 - Tq3 */ #define JPEG_DEC_STATUS_7_Tq3(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_7_Tq3_SHIFT)) & JPEG_DEC_STATUS_7_Tq3_MASK) #define JPEG_DEC_STATUS_7_V3_MASK (0x1CU) #define JPEG_DEC_STATUS_7_V3_SHIFT (2U) /*! V3 - V3 */ #define JPEG_DEC_STATUS_7_V3(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_7_V3_SHIFT)) & JPEG_DEC_STATUS_7_V3_MASK) #define JPEG_DEC_STATUS_7_H3_MASK (0xE0U) #define JPEG_DEC_STATUS_7_H3_SHIFT (5U) /*! H3 - H3 */ #define JPEG_DEC_STATUS_7_H3(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_7_H3_SHIFT)) & JPEG_DEC_STATUS_7_H3_MASK) #define JPEG_DEC_STATUS_7_C3_MASK (0xFF00U) #define JPEG_DEC_STATUS_7_C3_SHIFT (8U) /*! C3 - C3 */ #define JPEG_DEC_STATUS_7_C3(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_7_C3_SHIFT)) & JPEG_DEC_STATUS_7_C3_MASK) /*! @} */ /*! @name STATUS_8 - Status 8 Register */ /*! @{ */ #define JPEG_DEC_STATUS_8_Nf_MASK (0xFFU) #define JPEG_DEC_STATUS_8_Nf_SHIFT (0U) /*! Nf - Nf */ #define JPEG_DEC_STATUS_8_Nf(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_8_Nf_SHIFT)) & JPEG_DEC_STATUS_8_Nf_MASK) #define JPEG_DEC_STATUS_8_P_MASK (0xFF00U) #define JPEG_DEC_STATUS_8_P_SHIFT (8U) /*! P - P */ #define JPEG_DEC_STATUS_8_P(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_8_P_SHIFT)) & JPEG_DEC_STATUS_8_P_MASK) /*! @} */ /*! @name STATUS_9 - Status 9 Register */ /*! @{ */ #define JPEG_DEC_STATUS_9_DRI_MASK (0xFFFFU) #define JPEG_DEC_STATUS_9_DRI_SHIFT (0U) /*! DRI - DRI */ #define JPEG_DEC_STATUS_9_DRI(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_9_DRI_SHIFT)) & JPEG_DEC_STATUS_9_DRI_MASK) /*! @} */ /*! @name STATUS_10 - Status 10 Register */ /*! @{ */ #define JPEG_DEC_STATUS_10_Ns_MASK (0xFU) #define JPEG_DEC_STATUS_10_Ns_SHIFT (0U) /*! Ns - Ns */ #define JPEG_DEC_STATUS_10_Ns(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_10_Ns_SHIFT)) & JPEG_DEC_STATUS_10_Ns_MASK) #define JPEG_DEC_STATUS_10_NBMCU_MASK (0xF0U) #define JPEG_DEC_STATUS_10_NBMCU_SHIFT (4U) /*! NBMCU - NBMCU */ #define JPEG_DEC_STATUS_10_NBMCU(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_10_NBMCU_SHIFT)) & JPEG_DEC_STATUS_10_NBMCU_MASK) #define JPEG_DEC_STATUS_10_Vmax_MASK (0xF00U) #define JPEG_DEC_STATUS_10_Vmax_SHIFT (8U) /*! Vmax - Vmax */ #define JPEG_DEC_STATUS_10_Vmax(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_10_Vmax_SHIFT)) & JPEG_DEC_STATUS_10_Vmax_MASK) #define JPEG_DEC_STATUS_10_Hmax_MASK (0xF000U) #define JPEG_DEC_STATUS_10_Hmax_SHIFT (12U) /*! Hmax - Hmax */ #define JPEG_DEC_STATUS_10_Hmax(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_10_Hmax_SHIFT)) & JPEG_DEC_STATUS_10_Hmax_MASK) /*! @} */ /*! @name STATUS_11 - Status 11 Register */ /*! @{ */ #define JPEG_DEC_STATUS_11_VHS0_MASK (0xFU) #define JPEG_DEC_STATUS_11_VHS0_SHIFT (0U) /*! VHS0 - VHS0 */ #define JPEG_DEC_STATUS_11_VHS0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_11_VHS0_SHIFT)) & JPEG_DEC_STATUS_11_VHS0_MASK) #define JPEG_DEC_STATUS_11_VHS1_MASK (0xF0U) #define JPEG_DEC_STATUS_11_VHS1_SHIFT (4U) /*! VHS1 - VHS1 */ #define JPEG_DEC_STATUS_11_VHS1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_11_VHS1_SHIFT)) & JPEG_DEC_STATUS_11_VHS1_MASK) #define JPEG_DEC_STATUS_11_VHS2_MASK (0xF00U) #define JPEG_DEC_STATUS_11_VHS2_SHIFT (8U) /*! VHS2 - VHS2 */ #define JPEG_DEC_STATUS_11_VHS2(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_11_VHS2_SHIFT)) & JPEG_DEC_STATUS_11_VHS2_MASK) #define JPEG_DEC_STATUS_11_VHS3_MASK (0xF000U) #define JPEG_DEC_STATUS_11_VHS3_SHIFT (12U) /*! VHS3 - VHS3 */ #define JPEG_DEC_STATUS_11_VHS3(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_11_VHS3_SHIFT)) & JPEG_DEC_STATUS_11_VHS3_MASK) /*! @} */ /*! @name STATUS_12 - Status 12 Register */ /*! @{ */ #define JPEG_DEC_STATUS_12_COM_E_MASK (0x1U) #define JPEG_DEC_STATUS_12_COM_E_SHIFT (0U) /*! COM_E - COM_E */ #define JPEG_DEC_STATUS_12_COM_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_COM_E_SHIFT)) & JPEG_DEC_STATUS_12_COM_E_MASK) #define JPEG_DEC_STATUS_12_APPn_E_MASK (0x2U) #define JPEG_DEC_STATUS_12_APPn_E_SHIFT (1U) /*! APPn_E - APPn_E */ #define JPEG_DEC_STATUS_12_APPn_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_APPn_E_SHIFT)) & JPEG_DEC_STATUS_12_APPn_E_MASK) #define JPEG_DEC_STATUS_12_DRI_E_MASK (0x4U) #define JPEG_DEC_STATUS_12_DRI_E_SHIFT (2U) /*! DRI_E - DRI_E */ #define JPEG_DEC_STATUS_12_DRI_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_DRI_E_SHIFT)) & JPEG_DEC_STATUS_12_DRI_E_MASK) #define JPEG_DEC_STATUS_12_DNL_E_MASK (0x8U) #define JPEG_DEC_STATUS_12_DNL_E_SHIFT (3U) /*! DNL_E - DNL_E */ #define JPEG_DEC_STATUS_12_DNL_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_DNL_E_SHIFT)) & JPEG_DEC_STATUS_12_DNL_E_MASK) #define JPEG_DEC_STATUS_12_DHT_E_MASK (0x10U) #define JPEG_DEC_STATUS_12_DHT_E_SHIFT (4U) /*! DHT_E - DHT_E */ #define JPEG_DEC_STATUS_12_DHT_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_DHT_E_SHIFT)) & JPEG_DEC_STATUS_12_DHT_E_MASK) #define JPEG_DEC_STATUS_12_DQT_E_MASK (0x20U) #define JPEG_DEC_STATUS_12_DQT_E_SHIFT (5U) /*! DQT_E - DQT_E */ #define JPEG_DEC_STATUS_12_DQT_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_DQT_E_SHIFT)) & JPEG_DEC_STATUS_12_DQT_E_MASK) #define JPEG_DEC_STATUS_12_SOS_E_MASK (0x40U) #define JPEG_DEC_STATUS_12_SOS_E_SHIFT (6U) /*! SOS_E - SOS_E */ #define JPEG_DEC_STATUS_12_SOS_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_SOS_E_SHIFT)) & JPEG_DEC_STATUS_12_SOS_E_MASK) #define JPEG_DEC_STATUS_12_SOF_E_MASK (0x80U) #define JPEG_DEC_STATUS_12_SOF_E_SHIFT (7U) /*! SOF_E - SOF_E */ #define JPEG_DEC_STATUS_12_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_STATUS_12_SOF_E_SHIFT)) & JPEG_DEC_STATUS_12_SOF_E_MASK) /*! @} */ /*! * @} */ /* end of group JPEG_DEC_Register_Masks */ /* JPEG_DEC - Peripheral instance base addresses */ /** Peripheral IMAGING__DECODE_U_JPEG_D_X_NOMEM base address */ #define IMAGING__DECODE_U_JPEG_D_X_NOMEM_BASE (0x585D0000u) /** Peripheral IMAGING__DECODE_U_JPEG_D_X_NOMEM base pointer */ #define IMAGING__DECODE_U_JPEG_D_X_NOMEM ((JPEG_DEC_Type *)IMAGING__DECODE_U_JPEG_D_X_NOMEM_BASE) /** Array initializer of JPEG_DEC peripheral base addresses */ #define JPEG_DEC_BASE_ADDRS { IMAGING__DECODE_U_JPEG_D_X_NOMEM_BASE } /** Array initializer of JPEG_DEC peripheral base pointers */ #define JPEG_DEC_BASE_PTRS { IMAGING__DECODE_U_JPEG_D_X_NOMEM } /*! * @} */ /* end of group JPEG_DEC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- JPEG_DEC_WRAPPER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_DEC_WRAPPER_Peripheral_Access_Layer JPEG_DEC_WRAPPER Peripheral Access Layer * @{ */ /** JPEG_DEC_WRAPPER - Register Layout Typedef */ typedef struct { __IO uint32_t GLB_CTRL; /**< Global Control, offset: 0x0 */ __I uint32_t COM_STATUS; /**< Common Status, offset: 0x4 */ uint32_t RSVD_COM_IRQ_EN; /**< RSVD, offset: 0x8 */ uint32_t RSVD_CUR_DESCPT_PTR; /**< RSVD, offset: 0xC */ uint32_t RSVD_NXT_DESCPT_PTR; /**< RSVD, offset: 0x10 */ __IO uint32_t OUT_BUF_BASE0; /**< Output Image Frame Buffer0 Base Address, offset: 0x14 */ __IO uint32_t OUT_BUF_BASE1; /**< Output Image Frame Buffer1 Base Address, offset: 0x18 */ __IO uint32_t OUT_PITCH; /**< Image Output Buffer Pitch, offset: 0x1C */ __IO uint32_t STM_BUFBASE; /**< Input JPEG Stream Buffer Base Address, offset: 0x20 */ __IO uint32_t STM_BUFSIZE; /**< Input JPEG Stream Buffer Size, offset: 0x24 */ __IO uint32_t IMGSIZE; /**< Image Resolution, offset: 0x28 */ __IO uint32_t STM_CTRL; /**< Bit Stream and Switching Control, offset: 0x2C */ uint8_t RESERVED_0[65488]; struct { /* offset: 0x10000, array step: 0x10000 */ __IO uint32_t SLOT_STATUS; /**< Bitstream Status, array offset: 0x10000, array step: 0x10000 */ __IO uint32_t SLOT_IRQ_EN; /**< Bitstream Interrupt Eanble, array offset: 0x10004, array step: 0x10000 */ __I uint32_t SLOT_BUF_PTR; /**< Bitstream Buffer Pointer, array offset: 0x10008, array step: 0x10000 */ __I uint32_t SLOT_CUR_DESCPT_PTR; /**< Current Descriptors, array offset: 0x1000C, array step: 0x10000 */ __IO uint32_t SLOT_NXT_DESCPT_PTR; /**< Next Descriptors, array offset: 0x10010, array step: 0x10000 */ uint8_t RESERVED_0[65516]; } BITSTRM_SLOT_REGS[4]; } JPEG_DEC_WRAPPER_Type; /* ---------------------------------------------------------------------------- -- JPEG_DEC_WRAPPER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_DEC_WRAPPER_Register_Masks JPEG_DEC_WRAPPER Register Masks * @{ */ /*! @name GLB_CTRL - Global Control */ /*! @{ */ #define JPEG_DEC_WRAPPER_GLB_CTRL_JPG_DEC_EN_MASK (0x1U) #define JPEG_DEC_WRAPPER_GLB_CTRL_JPG_DEC_EN_SHIFT (0U) /*! JPG_DEC_EN - JPEG decoder and the wrapper enable bit. */ #define JPEG_DEC_WRAPPER_GLB_CTRL_JPG_DEC_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_GLB_CTRL_JPG_DEC_EN_SHIFT)) & JPEG_DEC_WRAPPER_GLB_CTRL_JPG_DEC_EN_MASK) #define JPEG_DEC_WRAPPER_GLB_CTRL_SFTRST_MASK (0x2U) #define JPEG_DEC_WRAPPER_GLB_CTRL_SFTRST_SHIFT (1U) /*! SFTRST - Engine Soft reset */ #define JPEG_DEC_WRAPPER_GLB_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_GLB_CTRL_SFTRST_SHIFT)) & JPEG_DEC_WRAPPER_GLB_CTRL_SFTRST_MASK) #define JPEG_DEC_WRAPPER_GLB_CTRL_DEC_GO_MASK (0x4U) #define JPEG_DEC_WRAPPER_GLB_CTRL_DEC_GO_SHIFT (2U) /*! DEC_GO - Start Decoding */ #define JPEG_DEC_WRAPPER_GLB_CTRL_DEC_GO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_GLB_CTRL_DEC_GO_SHIFT)) & JPEG_DEC_WRAPPER_GLB_CTRL_DEC_GO_MASK) #define JPEG_DEC_WRAPPER_GLB_CTRL_L_ENDIAN_MASK (0x8U) #define JPEG_DEC_WRAPPER_GLB_CTRL_L_ENDIAN_SHIFT (3U) /*! L_ENDIAN - JPEG Fileformat LITTLE ENDIAN FORMAT */ #define JPEG_DEC_WRAPPER_GLB_CTRL_L_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_GLB_CTRL_L_ENDIAN_SHIFT)) & JPEG_DEC_WRAPPER_GLB_CTRL_L_ENDIAN_MASK) #define JPEG_DEC_WRAPPER_GLB_CTRL_SLOT_EN_MASK (0xF0U) #define JPEG_DEC_WRAPPER_GLB_CTRL_SLOT_EN_SHIFT (4U) /*! SLOT_EN - Slots enable */ #define JPEG_DEC_WRAPPER_GLB_CTRL_SLOT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_GLB_CTRL_SLOT_EN_SHIFT)) & JPEG_DEC_WRAPPER_GLB_CTRL_SLOT_EN_MASK) /*! @} */ /*! @name COM_STATUS - Common Status */ /*! @{ */ #define JPEG_DEC_WRAPPER_COM_STATUS_CUR_SLOT_MASK (0x60000000U) #define JPEG_DEC_WRAPPER_COM_STATUS_CUR_SLOT_SHIFT (29U) /*! CUR_SLOT - Current executing bitstream slot */ #define JPEG_DEC_WRAPPER_COM_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_COM_STATUS_CUR_SLOT_SHIFT)) & JPEG_DEC_WRAPPER_COM_STATUS_CUR_SLOT_MASK) #define JPEG_DEC_WRAPPER_COM_STATUS_DEC_ONGOING_MASK (0x80000000U) #define JPEG_DEC_WRAPPER_COM_STATUS_DEC_ONGOING_SHIFT (31U) /*! DEC_ONGOING - Indicating the decoing is ongoing. */ #define JPEG_DEC_WRAPPER_COM_STATUS_DEC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_COM_STATUS_DEC_ONGOING_SHIFT)) & JPEG_DEC_WRAPPER_COM_STATUS_DEC_ONGOING_MASK) /*! @} */ /*! @name OUT_BUF_BASE0 - Output Image Frame Buffer0 Base Address */ /*! @{ */ #define JPEG_DEC_WRAPPER_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK (0xFFFFFFF0U) #define JPEG_DEC_WRAPPER_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT (4U) /*! OUT_BUF_BASE0 - PIXEL FRAME BUF0 BASE */ #define JPEG_DEC_WRAPPER_OUT_BUF_BASE0_OUT_BUF_BASE0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT)) & JPEG_DEC_WRAPPER_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK) /*! @} */ /*! @name OUT_BUF_BASE1 - Output Image Frame Buffer1 Base Address */ /*! @{ */ #define JPEG_DEC_WRAPPER_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK (0xFFFFFFF0U) #define JPEG_DEC_WRAPPER_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT (4U) /*! OUT_BUF_BASE1 - PIXEL FRAME BUF2 BASE */ #define JPEG_DEC_WRAPPER_OUT_BUF_BASE1_OUT_BUF_BASE1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT)) & JPEG_DEC_WRAPPER_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK) /*! @} */ /*! @name OUT_PITCH - Image Output Buffer Pitch */ /*! @{ */ #define JPEG_DEC_WRAPPER_OUT_PITCH_OUT_PITCH_MASK (0xFFFFU) #define JPEG_DEC_WRAPPER_OUT_PITCH_OUT_PITCH_SHIFT (0U) /*! OUT_PITCH - image line stride setting in the memory */ #define JPEG_DEC_WRAPPER_OUT_PITCH_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_OUT_PITCH_OUT_PITCH_SHIFT)) & JPEG_DEC_WRAPPER_OUT_PITCH_OUT_PITCH_MASK) /*! @} */ /*! @name STM_BUFBASE - Input JPEG Stream Buffer Base Address */ /*! @{ */ #define JPEG_DEC_WRAPPER_STM_BUFBASE_STM_BUFBASE_MASK (0xFFFFFFF0U) #define JPEG_DEC_WRAPPER_STM_BUFBASE_STM_BUFBASE_SHIFT (4U) /*! STM_BUFBASE - Bitstream BUF BASE */ #define JPEG_DEC_WRAPPER_STM_BUFBASE_STM_BUFBASE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_BUFBASE_STM_BUFBASE_SHIFT)) & JPEG_DEC_WRAPPER_STM_BUFBASE_STM_BUFBASE_MASK) /*! @} */ /*! @name STM_BUFSIZE - Input JPEG Stream Buffer Size */ /*! @{ */ #define JPEG_DEC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_MASK (0xFFFFFC00U) #define JPEG_DEC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_SHIFT (10U) /*! STM_BUFSIZE - Bitstream Buffer Size */ #define JPEG_DEC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & JPEG_DEC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_MASK) /*! @} */ /*! @name IMGSIZE - Image Resolution */ /*! @{ */ #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_HEIGHT_MASK (0x3FFFU) #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_HEIGHT_SHIFT (0U) /*! IMG_HEIGHT - image height */ #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_IMGSIZE_IMG_HEIGHT_SHIFT)) & JPEG_DEC_WRAPPER_IMGSIZE_IMG_HEIGHT_MASK) #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_WIDTH_MASK (0x3FFF0000U) #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_WIDTH_SHIFT (16U) /*! IMG_WIDTH - image width */ #define JPEG_DEC_WRAPPER_IMGSIZE_IMG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_IMGSIZE_IMG_WIDTH_SHIFT)) & JPEG_DEC_WRAPPER_IMGSIZE_IMG_WIDTH_MASK) /*! @} */ /*! @name STM_CTRL - Bit Stream and Switching Control */ /*! @{ */ #define JPEG_DEC_WRAPPER_STM_CTRL_PIXEL_PRECISION_MASK (0x4U) #define JPEG_DEC_WRAPPER_STM_CTRL_PIXEL_PRECISION_SHIFT (2U) /*! PIXEL_PRECISION - Current decoding precision: 8bit or 12bit. */ #define JPEG_DEC_WRAPPER_STM_CTRL_PIXEL_PRECISION(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_CTRL_PIXEL_PRECISION_SHIFT)) & JPEG_DEC_WRAPPER_STM_CTRL_PIXEL_PRECISION_MASK) #define JPEG_DEC_WRAPPER_STM_CTRL_IMAGE_FORMAT_MASK (0x78U) #define JPEG_DEC_WRAPPER_STM_CTRL_IMAGE_FORMAT_SHIFT (3U) /*! IMAGE_FORMAT - IMAGE FORMAT * 0b0000..Image format is YUV420 (2 Plannar, Y at the 1st plannar and UV at the second plannar). * 0b0001..Image format is YUV422 (1 Plannar in YUYV sequence) * 0b0010..Image format is RGB (RGBRGB packed format) * 0b0011..Image format is YUV444 ( 1 Plannar in YUVYUV sequence) * 0b0100..Image format is Gray(Y8 or Y12) or Single Component. * 0b0101..Reserved for Future usage. * 0b0110..Image format is ARGB */ #define JPEG_DEC_WRAPPER_STM_CTRL_IMAGE_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_CTRL_IMAGE_FORMAT_SHIFT)) & JPEG_DEC_WRAPPER_STM_CTRL_IMAGE_FORMAT_MASK) #define JPEG_DEC_WRAPPER_STM_CTRL_BITBUF_PTR_CLR_MASK (0x80U) #define JPEG_DEC_WRAPPER_STM_CTRL_BITBUF_PTR_CLR_SHIFT (7U) /*! BITBUF_PTR_CLR - Switched bit stream buffer pointer clear bit. */ #define JPEG_DEC_WRAPPER_STM_CTRL_BITBUF_PTR_CLR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_CTRL_BITBUF_PTR_CLR_SHIFT)) & JPEG_DEC_WRAPPER_STM_CTRL_BITBUF_PTR_CLR_MASK) #define JPEG_DEC_WRAPPER_STM_CTRL_AUTO_START_MASK (0x100U) #define JPEG_DEC_WRAPPER_STM_CTRL_AUTO_START_SHIFT (8U) /*! AUTO_START - Automatically write "GO" to Cast JPEG Decoder after context switch to start the new decoding. * 0b0..Will not write any CAST JPEG Decoder Control registers. * 0b1..Will write '1' to [Go] bit of Cast JPEG Decoder Control register */ #define JPEG_DEC_WRAPPER_STM_CTRL_AUTO_START(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_STM_CTRL_AUTO_START_SHIFT)) & JPEG_DEC_WRAPPER_STM_CTRL_AUTO_START_MASK) /*! @} */ /*! @name SLOT_STATUS - Bitstream Status */ /*! @{ */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_HALF_MASK (0x1U) #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_HALF_SHIFT (0U) /*! STMBUF_HALF - Indicating the stream buf pointer has come over half size of the buf size. */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_HALF(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_HALF_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_HALF_MASK) #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_RTND_MASK (0x2U) #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_RTND_SHIFT (1U) /*! STMBUF_RTND - Indicating the stream buf pointer has come over the top size of the stream buffer. */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_RTND(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_RTND_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_STMBUF_RTND_MASK) #define JPEG_DEC_WRAPPER_SLOT_STATUS_SWITCHED_IN_MASK (0x4U) #define JPEG_DEC_WRAPPER_SLOT_STATUS_SWITCHED_IN_SHIFT (2U) /*! SWITCHED_IN - Current SLOT is switched in during context switch */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_SWITCHED_IN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_SWITCHED_IN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_SWITCHED_IN_MASK) #define JPEG_DEC_WRAPPER_SLOT_STATUS_FRMDONE_MASK (0x8U) #define JPEG_DEC_WRAPPER_SLOT_STATUS_FRMDONE_SHIFT (3U) /*! FRMDONE - One frame of image decoding finished for current bitstrem (ID). */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_FRMDONE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_FRMDONE_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_FRMDONE_MASK) #define JPEG_DEC_WRAPPER_SLOT_STATUS_DECERR_MASK (0x100U) #define JPEG_DEC_WRAPPER_SLOT_STATUS_DECERR_SHIFT (8U) /*! DECERR - Decoding error status bit */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_DECERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_DECERR_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_DECERR_MASK) #define JPEG_DEC_WRAPPER_SLOT_STATUS_DES_RD_ERR_MASK (0x200U) #define JPEG_DEC_WRAPPER_SLOT_STATUS_DES_RD_ERR_SHIFT (9U) /*! DES_RD_ERR - AXI Read error status for descriptor fetching */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_DES_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_DES_RD_ERR_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_DES_RD_ERR_MASK) #define JPEG_DEC_WRAPPER_SLOT_STATUS_BIT_RD_ERR_MASK (0x400U) #define JPEG_DEC_WRAPPER_SLOT_STATUS_BIT_RD_ERR_SHIFT (10U) /*! BIT_RD_ERR - AXI Read error status for bitstream fetching */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_BIT_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_BIT_RD_ERR_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_BIT_RD_ERR_MASK) #define JPEG_DEC_WRAPPER_SLOT_STATUS_PIXEL_WT_ERR_MASK (0x800U) #define JPEG_DEC_WRAPPER_SLOT_STATUS_PIXEL_WT_ERR_SHIFT (11U) /*! PIXEL_WT_ERR - AXI Write error status for pixel storing */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_PIXEL_WT_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_PIXEL_WT_ERR_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_PIXEL_WT_ERR_MASK) #define JPEG_DEC_WRAPPER_SLOT_STATUS_CUR_SLOT_MASK (0x60000000U) #define JPEG_DEC_WRAPPER_SLOT_STATUS_CUR_SLOT_SHIFT (29U) /*! CUR_SLOT - Current Executing bitstream slot */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_CUR_SLOT_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_CUR_SLOT_MASK) #define JPEG_DEC_WRAPPER_SLOT_STATUS_DEC_ONGOING_MASK (0x80000000U) #define JPEG_DEC_WRAPPER_SLOT_STATUS_DEC_ONGOING_SHIFT (31U) /*! DEC_ONGOING - Indicating the decoing is ongoing. */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_DEC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_STATUS_DEC_ONGOING_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_STATUS_DEC_ONGOING_MASK) /*! @} */ /* The count of JPEG_DEC_WRAPPER_SLOT_STATUS */ #define JPEG_DEC_WRAPPER_SLOT_STATUS_COUNT (4U) /*! @name SLOT_IRQ_EN - Bitstream Interrupt Eanble */ /*! @{ */ #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK (0x1U) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT (0U) /*! STMBUF_HALF_IRQ_EN - Bitstream buffer pointer passing half size of buffer interrupt enable */ #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK (0x2U) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT (1U) /*! STMBUF_RTND_IRQ_EN - Bitstream buffer pointer passing top of buffer interrupt enable */ #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK (0x4U) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT (2U) /*! SWITCHED_IN_IRQ_EN - Context switched in for current bitstream ID interrupt enable */ #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK (0x8U) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT (3U) /*! FRMDONE_IRQ_EN - Frame decoding done for current bitstream ID interrupt enable */ #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_FRMDONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DECERR_irq_en_MASK (0x100U) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DECERR_irq_en_SHIFT (8U) /*! DECERR_irq_en - Decoding error status interrupt enable */ #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DECERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DECERR_irq_en_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DECERR_irq_en_MASK) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_MASK (0x200U) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_SHIFT (9U) /*! DES_RD_ERR_irq_en - AXI Read error status for descriptor fetching */ #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_MASK) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_MASK (0x400U) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_SHIFT (10U) /*! BIT_RD_ERR_irq_en - AXI Read error status for bitstream fetching */ #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_BIT_RD_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_MASK) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_MASK (0x800U) #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_SHIFT (11U) /*! PIXEL_WT_ERR_irq_en - AXI Write error status for pixel storing */ #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_MASK) /*! @} */ /* The count of JPEG_DEC_WRAPPER_SLOT_IRQ_EN */ #define JPEG_DEC_WRAPPER_SLOT_IRQ_EN_COUNT (4U) /*! @name SLOT_BUF_PTR - Bitstream Buffer Pointer */ /*! @{ */ #define JPEG_DEC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_MASK (0xFFFFFFFFU) #define JPEG_DEC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_SHIFT (0U) /*! stmbuf_ptr - stream buf pointer */ #define JPEG_DEC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_MASK) /*! @} */ /* The count of JPEG_DEC_WRAPPER_SLOT_BUF_PTR */ #define JPEG_DEC_WRAPPER_SLOT_BUF_PTR_COUNT (4U) /*! @name SLOT_CUR_DESCPT_PTR - Current Descriptors */ /*! @{ */ #define JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK (0xFFFFFFFCU) #define JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT (2U) /*! CUR_DESCPT_PRT - cur decoding descriptors pointer. */ #define JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK) /*! @} */ /* The count of JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR */ #define JPEG_DEC_WRAPPER_SLOT_CUR_DESCPT_PTR_COUNT (4U) /*! @name SLOT_NXT_DESCPT_PTR - Next Descriptors */ /*! @{ */ #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK (0x1U) #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT (0U) /*! NXT_DESCPT_EN - if next stream descriptor pointor are valid * 0b0..There is no more descriptor to be fetched, decoding will pause when current frame is finished. * 0b1..Current descriptor pointer is valid, and wrapper will fetch the descriptor and start next frame decoding * when current frame decoding is finished. */ #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK) #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK (0xFFFFFFFCU) #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT (2U) /*! NXT_DESCPT_PRT - next decoding descriptors pointer. */ #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT)) & JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK) /*! @} */ /* The count of JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR */ #define JPEG_DEC_WRAPPER_SLOT_NXT_DESCPT_PTR_COUNT (4U) /*! * @} */ /* end of group JPEG_DEC_WRAPPER_Register_Masks */ /* JPEG_DEC_WRAPPER - Peripheral instance base addresses */ /** Peripheral IMAGING__DECODE_U_JPEG_DEC_WRAPPER base address */ #define IMAGING__DECODE_U_JPEG_DEC_WRAPPER_BASE (0x58400000u) /** Peripheral IMAGING__DECODE_U_JPEG_DEC_WRAPPER base pointer */ #define IMAGING__DECODE_U_JPEG_DEC_WRAPPER ((JPEG_DEC_WRAPPER_Type *)IMAGING__DECODE_U_JPEG_DEC_WRAPPER_BASE) /** Array initializer of JPEG_DEC_WRAPPER peripheral base addresses */ #define JPEG_DEC_WRAPPER_BASE_ADDRS { IMAGING__DECODE_U_JPEG_DEC_WRAPPER_BASE } /** Array initializer of JPEG_DEC_WRAPPER peripheral base pointers */ #define JPEG_DEC_WRAPPER_BASE_PTRS { IMAGING__DECODE_U_JPEG_DEC_WRAPPER } /*! * @} */ /* end of group JPEG_DEC_WRAPPER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- JPEG_ENC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_ENC_Peripheral_Access_Layer JPEG_ENC Peripheral Access Layer * @{ */ /** JPEG_ENC - Register Layout Typedef */ typedef struct { union { /* offset: 0x0 */ struct { /* offset: 0x0 */ __IO uint32_t MODE; /**< MODE Control Register, offset: 0x0 */ __IO uint32_t CFG_MODE; /**< CFG_MODE Control Register, offset: 0x4 */ __IO uint32_t QUALITY; /**< , offset: 0x8 */ uint32_t RSVD; /**< , offset: 0xC */ __IO uint32_t REC_REGS_SEL; /**< Indirect Status Register Select, offset: 0x10 */ __IO uint32_t LUMTH; /**< LUMTH Register, offset: 0x14 */ __IO uint32_t CHRTH; /**< CHRTH Register, offset: 0x18 */ uint8_t RESERVED_0[36]; __IO uint32_t NOMFRSIZE_LO; /**< , offset: 0x40 */ __IO uint32_t NOMFRSIZE_HI; /**< , offset: 0x44 */ __IO uint32_t OFBSIZE_LO; /**< , offset: 0x48 */ __IO uint32_t OFBSIZE_HI; /**< , offset: 0x4C */ } CONTROL; struct { /* offset: 0x0 */ __IO uint32_t STATUS_0; /**< , offset: 0x0 */ __IO uint32_t STATUS_1; /**< , offset: 0x4 */ __IO uint32_t STATUS_2; /**< , offset: 0x8 */ __IO uint32_t STATUS_3; /**< , offset: 0xC */ __IO uint32_t STATUS_4; /**< , offset: 0x10 */ __IO uint32_t STATUS_5; /**< , offset: 0x14 */ __IO uint32_t STATUS_6; /**< , offset: 0x18 */ __IO uint32_t STATUS_7; /**< , offset: 0x1C */ __IO uint32_t STATUS_8; /**< , offset: 0x20 */ __IO uint32_t STATUS_9; /**< , offset: 0x24 */ __IO uint32_t STATUS_10; /**< , offset: 0x28 */ __IO uint32_t STATUS_11; /**< , offset: 0x2C */ __IO uint32_t STATUS_12; /**< , offset: 0x30 */ __IO uint32_t STATUS_13; /**< , offset: 0x34 */ __IO uint32_t STATUS_14; /**< , offset: 0x38 */ __IO uint32_t STATUS_15; /**< , offset: 0x3C */ __IO uint32_t STATUS_16; /**< , offset: 0x40 */ __IO uint32_t STATUS_17; /**< , offset: 0x44 */ __IO uint32_t STATUS_18; /**< , offset: 0x48 */ __IO uint32_t STATUS_19; /**< , offset: 0x4C */ } STATUS; }; } JPEG_ENC_Type; /* ---------------------------------------------------------------------------- -- JPEG_ENC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_ENC_Register_Masks JPEG_ENC Register Masks * @{ */ /*! @name MODE - MODE Control Register */ /*! @{ */ #define JPEG_ENC_MODE_LP_MASK (0x1U) #define JPEG_ENC_MODE_LP_SHIFT (0U) /*! LP - Low Power */ #define JPEG_ENC_MODE_LP(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_LP_SHIFT)) & JPEG_ENC_MODE_LP_MASK) #define JPEG_ENC_MODE_SWR_MASK (0x2U) #define JPEG_ENC_MODE_SWR_SHIFT (1U) /*! SWR - Soft reset */ #define JPEG_ENC_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_SWR_SHIFT)) & JPEG_ENC_MODE_SWR_MASK) #define JPEG_ENC_MODE_MS_MASK (0x8U) #define JPEG_ENC_MODE_MS_SHIFT (3U) /*! MS - Multi-scan JPEG */ #define JPEG_ENC_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_MS_SHIFT)) & JPEG_ENC_MODE_MS_MASK) #define JPEG_ENC_MODE_EXTSEQ_MASK (0x10U) #define JPEG_ENC_MODE_EXTSEQ_SHIFT (4U) /*! EXTSEQ - EXTSEQ */ #define JPEG_ENC_MODE_EXTSEQ(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_EXTSEQ_SHIFT)) & JPEG_ENC_MODE_EXTSEQ_MASK) #define JPEG_ENC_MODE_CONF_MASK (0x20U) #define JPEG_ENC_MODE_CONF_SHIFT (5U) /*! CONF - Configuration */ #define JPEG_ENC_MODE_CONF(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_CONF_SHIFT)) & JPEG_ENC_MODE_CONF_MASK) #define JPEG_ENC_MODE_GO_MASK (0x40U) #define JPEG_ENC_MODE_GO_SHIFT (6U) /*! GO - Low Power */ #define JPEG_ENC_MODE_GO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_GO_SHIFT)) & JPEG_ENC_MODE_GO_MASK) #define JPEG_ENC_MODE_AUTOCLR_CONF_MASK (0x80U) #define JPEG_ENC_MODE_AUTOCLR_CONF_SHIFT (7U) /*! AUTOCLR_CONF - AUTOCLR_CONF */ #define JPEG_ENC_MODE_AUTOCLR_CONF(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_AUTOCLR_CONF_SHIFT)) & JPEG_ENC_MODE_AUTOCLR_CONF_MASK) #define JPEG_ENC_MODE_AUTOCLR_GO_MASK (0x100U) #define JPEG_ENC_MODE_AUTOCLR_GO_SHIFT (8U) /*! AUTOCLR_GO - AUTOCLR_GO */ #define JPEG_ENC_MODE_AUTOCLR_GO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_MODE_AUTOCLR_GO_SHIFT)) & JPEG_ENC_MODE_AUTOCLR_GO_MASK) /*! @} */ /*! @name CFG_MODE - CFG_MODE Control Register */ /*! @{ */ #define JPEG_ENC_CFG_MODE_MSOF0_MASK (0x1U) #define JPEG_ENC_CFG_MODE_MSOF0_SHIFT (0U) /*! MSOF0 - MSOF0 */ #define JPEG_ENC_CFG_MODE_MSOF0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MSOF0_SHIFT)) & JPEG_ENC_CFG_MODE_MSOF0_MASK) #define JPEG_ENC_CFG_MODE_MDRI_MASK (0x2U) #define JPEG_ENC_CFG_MODE_MDRI_SHIFT (1U) /*! MDRI - Mask DRI */ #define JPEG_ENC_CFG_MODE_MDRI(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MDRI_SHIFT)) & JPEG_ENC_CFG_MODE_MDRI_MASK) #define JPEG_ENC_CFG_MODE_MDQT_MASK (0x4U) #define JPEG_ENC_CFG_MODE_MDQT_SHIFT (2U) /*! MDQT - Mask DQT */ #define JPEG_ENC_CFG_MODE_MDQT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MDQT_SHIFT)) & JPEG_ENC_CFG_MODE_MDQT_MASK) #define JPEG_ENC_CFG_MODE_MDHT_MASK (0x8U) #define JPEG_ENC_CFG_MODE_MDHT_SHIFT (3U) /*! MDHT - Mask DHT */ #define JPEG_ENC_CFG_MODE_MDHT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MDHT_SHIFT)) & JPEG_ENC_CFG_MODE_MDHT_MASK) #define JPEG_ENC_CFG_MODE_MSOS_MASK (0x10U) #define JPEG_ENC_CFG_MODE_MSOS_SHIFT (4U) /*! MSOS - Mask SOS */ #define JPEG_ENC_CFG_MODE_MSOS(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MSOS_SHIFT)) & JPEG_ENC_CFG_MODE_MSOS_MASK) #define JPEG_ENC_CFG_MODE_MDNL_MASK (0x20U) #define JPEG_ENC_CFG_MODE_MDNL_SHIFT (5U) /*! MDNL - Mask DNL */ #define JPEG_ENC_CFG_MODE_MDNL(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MDNL_SHIFT)) & JPEG_ENC_CFG_MODE_MDNL_MASK) #define JPEG_ENC_CFG_MODE_MAPP_MASK (0x40U) #define JPEG_ENC_CFG_MODE_MAPP_SHIFT (6U) /*! MAPP - Mask APP */ #define JPEG_ENC_CFG_MODE_MAPP(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MAPP_SHIFT)) & JPEG_ENC_CFG_MODE_MAPP_MASK) #define JPEG_ENC_CFG_MODE_MCOM_MASK (0x80U) #define JPEG_ENC_CFG_MODE_MCOM_SHIFT (7U) /*! MCOM - Mask COM */ #define JPEG_ENC_CFG_MODE_MCOM(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_MCOM_SHIFT)) & JPEG_ENC_CFG_MODE_MCOM_MASK) #define JPEG_ENC_CFG_MODE_COMB_DQT_MASK (0x100U) #define JPEG_ENC_CFG_MODE_COMB_DQT_SHIFT (8U) /*! COMB_DQT - COMB_DQT */ #define JPEG_ENC_CFG_MODE_COMB_DQT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_COMB_DQT_SHIFT)) & JPEG_ENC_CFG_MODE_COMB_DQT_MASK) #define JPEG_ENC_CFG_MODE_COMB_DHT_MASK (0x200U) #define JPEG_ENC_CFG_MODE_COMB_DHT_SHIFT (9U) /*! COMB_DHT - COMB_DHT */ #define JPEG_ENC_CFG_MODE_COMB_DHT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_COMB_DHT_SHIFT)) & JPEG_ENC_CFG_MODE_COMB_DHT_MASK) #define JPEG_ENC_CFG_MODE_DICOM_MASK (0x400U) #define JPEG_ENC_CFG_MODE_DICOM_SHIFT (10U) /*! DICOM - DICOM */ #define JPEG_ENC_CFG_MODE_DICOM(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CFG_MODE_DICOM_SHIFT)) & JPEG_ENC_CFG_MODE_DICOM_MASK) /*! @} */ /*! @name QUALITY - */ /*! @{ */ #define JPEG_ENC_QUALITY_QUALITY_MASK (0x7FU) #define JPEG_ENC_QUALITY_QUALITY_SHIFT (0U) /*! QUALITY - QUALITY */ #define JPEG_ENC_QUALITY_QUALITY(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_QUALITY_QUALITY_SHIFT)) & JPEG_ENC_QUALITY_QUALITY_MASK) /*! @} */ /*! @name REC_REGS_SEL - Indirect Status Register Select */ /*! @{ */ #define JPEG_ENC_REC_REGS_SEL_RC_REGS_SEL_MASK (0x3U) #define JPEG_ENC_REC_REGS_SEL_RC_REGS_SEL_SHIFT (0U) /*! RC_REGS_SEL - RC_REGS_SEL */ #define JPEG_ENC_REC_REGS_SEL_RC_REGS_SEL(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_REC_REGS_SEL_RC_REGS_SEL_SHIFT)) & JPEG_ENC_REC_REGS_SEL_RC_REGS_SEL_MASK) /*! @} */ /*! @name LUMTH - LUMTH Register */ /*! @{ */ #define JPEG_ENC_LUMTH_LUMTH_MASK (0xFFFFU) #define JPEG_ENC_LUMTH_LUMTH_SHIFT (0U) /*! LUMTH - LUMTH */ #define JPEG_ENC_LUMTH_LUMTH(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_LUMTH_LUMTH_SHIFT)) & JPEG_ENC_LUMTH_LUMTH_MASK) /*! @} */ /*! @name CHRTH - CHRTH Register */ /*! @{ */ #define JPEG_ENC_CHRTH_CHRTH_MASK (0xFFFFU) #define JPEG_ENC_CHRTH_CHRTH_SHIFT (0U) /*! CHRTH - CHRTH */ #define JPEG_ENC_CHRTH_CHRTH(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_CHRTH_CHRTH_SHIFT)) & JPEG_ENC_CHRTH_CHRTH_MASK) /*! @} */ /*! @name NOMFRSIZE_LO - */ /*! @{ */ #define JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_MASK (0xFFFFU) #define JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_SHIFT (0U) /*! NOMFRSIZE_LO - NOMFRSIZE_LO */ #define JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_SHIFT)) & JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_MASK) /*! @} */ /*! @name NOMFRSIZE_HI - */ /*! @{ */ #define JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_MASK (0xFFFFU) #define JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_SHIFT (0U) /*! NOMFRSIZE_HI - NOMFRSIZE_HI */ #define JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_SHIFT)) & JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_MASK) /*! @} */ /*! @name OFBSIZE_LO - */ /*! @{ */ #define JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_MASK (0xFFFFU) #define JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_SHIFT (0U) /*! OFBSIZE_LO - OFBSIZE_LO */ #define JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_SHIFT)) & JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_MASK) /*! @} */ /*! @name OFBSIZE_HI - */ /*! @{ */ #define JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_MASK (0xFFFFU) #define JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_SHIFT (0U) /*! OFBSIZE_HI - OFBSIZE_HI */ #define JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_SHIFT)) & JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_MASK) /*! @} */ /*! @name STATUS_0 - */ /*! @{ */ #define JPEG_ENC_STATUS_0_X_MASK (0xFFFFU) #define JPEG_ENC_STATUS_0_X_SHIFT (0U) /*! X - X */ #define JPEG_ENC_STATUS_0_X(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_0_X_SHIFT)) & JPEG_ENC_STATUS_0_X_MASK) /*! @} */ /*! @name STATUS_1 - */ /*! @{ */ #define JPEG_ENC_STATUS_1_Y_MASK (0xFFFFU) #define JPEG_ENC_STATUS_1_Y_SHIFT (0U) /*! Y - Y */ #define JPEG_ENC_STATUS_1_Y(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_1_Y_SHIFT)) & JPEG_ENC_STATUS_1_Y_MASK) /*! @} */ /*! @name STATUS_2 - */ /*! @{ */ #define JPEG_ENC_STATUS_2_HMCU_MASK (0xFFFFU) #define JPEG_ENC_STATUS_2_HMCU_SHIFT (0U) /*! HMCU - HMCU */ #define JPEG_ENC_STATUS_2_HMCU(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_2_HMCU_SHIFT)) & JPEG_ENC_STATUS_2_HMCU_MASK) /*! @} */ /*! @name STATUS_3 - */ /*! @{ */ #define JPEG_ENC_STATUS_3_VMCU_MASK (0xFFFFU) #define JPEG_ENC_STATUS_3_VMCU_SHIFT (0U) /*! VMCU - VMCU */ #define JPEG_ENC_STATUS_3_VMCU(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_3_VMCU_SHIFT)) & JPEG_ENC_STATUS_3_VMCU_MASK) /*! @} */ /*! @name STATUS_4 - */ /*! @{ */ #define JPEG_ENC_STATUS_4_Tq0_MASK (0x3U) #define JPEG_ENC_STATUS_4_Tq0_SHIFT (0U) /*! Tq0 - Tq0 */ #define JPEG_ENC_STATUS_4_Tq0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_4_Tq0_SHIFT)) & JPEG_ENC_STATUS_4_Tq0_MASK) #define JPEG_ENC_STATUS_4_V0_MASK (0x1CU) #define JPEG_ENC_STATUS_4_V0_SHIFT (2U) /*! V0 - V0 */ #define JPEG_ENC_STATUS_4_V0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_4_V0_SHIFT)) & JPEG_ENC_STATUS_4_V0_MASK) #define JPEG_ENC_STATUS_4_H0_MASK (0xE0U) #define JPEG_ENC_STATUS_4_H0_SHIFT (5U) /*! H0 - H0 */ #define JPEG_ENC_STATUS_4_H0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_4_H0_SHIFT)) & JPEG_ENC_STATUS_4_H0_MASK) #define JPEG_ENC_STATUS_4_C0_MASK (0xFF00U) #define JPEG_ENC_STATUS_4_C0_SHIFT (8U) /*! C0 - C0 */ #define JPEG_ENC_STATUS_4_C0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_4_C0_SHIFT)) & JPEG_ENC_STATUS_4_C0_MASK) /*! @} */ /*! @name STATUS_5 - */ /*! @{ */ #define JPEG_ENC_STATUS_5_Tq1_MASK (0x3U) #define JPEG_ENC_STATUS_5_Tq1_SHIFT (0U) /*! Tq1 - Tq1 */ #define JPEG_ENC_STATUS_5_Tq1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_5_Tq1_SHIFT)) & JPEG_ENC_STATUS_5_Tq1_MASK) #define JPEG_ENC_STATUS_5_V1_MASK (0x1CU) #define JPEG_ENC_STATUS_5_V1_SHIFT (2U) /*! V1 - V1 */ #define JPEG_ENC_STATUS_5_V1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_5_V1_SHIFT)) & JPEG_ENC_STATUS_5_V1_MASK) #define JPEG_ENC_STATUS_5_H1_MASK (0xE0U) #define JPEG_ENC_STATUS_5_H1_SHIFT (5U) /*! H1 - H1 */ #define JPEG_ENC_STATUS_5_H1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_5_H1_SHIFT)) & JPEG_ENC_STATUS_5_H1_MASK) #define JPEG_ENC_STATUS_5_C1_MASK (0xFF00U) #define JPEG_ENC_STATUS_5_C1_SHIFT (8U) /*! C1 - C1 */ #define JPEG_ENC_STATUS_5_C1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_5_C1_SHIFT)) & JPEG_ENC_STATUS_5_C1_MASK) /*! @} */ /*! @name STATUS_6 - */ /*! @{ */ #define JPEG_ENC_STATUS_6_Tq2_MASK (0x3U) #define JPEG_ENC_STATUS_6_Tq2_SHIFT (0U) /*! Tq2 - Tq2 */ #define JPEG_ENC_STATUS_6_Tq2(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_6_Tq2_SHIFT)) & JPEG_ENC_STATUS_6_Tq2_MASK) #define JPEG_ENC_STATUS_6_V2_MASK (0x1CU) #define JPEG_ENC_STATUS_6_V2_SHIFT (2U) /*! V2 - V2 */ #define JPEG_ENC_STATUS_6_V2(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_6_V2_SHIFT)) & JPEG_ENC_STATUS_6_V2_MASK) #define JPEG_ENC_STATUS_6_H2_MASK (0xE0U) #define JPEG_ENC_STATUS_6_H2_SHIFT (5U) /*! H2 - H2 */ #define JPEG_ENC_STATUS_6_H2(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_6_H2_SHIFT)) & JPEG_ENC_STATUS_6_H2_MASK) #define JPEG_ENC_STATUS_6_C2_MASK (0xFF00U) #define JPEG_ENC_STATUS_6_C2_SHIFT (8U) /*! C2 - C2 */ #define JPEG_ENC_STATUS_6_C2(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_6_C2_SHIFT)) & JPEG_ENC_STATUS_6_C2_MASK) /*! @} */ /*! @name STATUS_7 - */ /*! @{ */ #define JPEG_ENC_STATUS_7_Tq3_MASK (0x3U) #define JPEG_ENC_STATUS_7_Tq3_SHIFT (0U) /*! Tq3 - Tq3 */ #define JPEG_ENC_STATUS_7_Tq3(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_7_Tq3_SHIFT)) & JPEG_ENC_STATUS_7_Tq3_MASK) #define JPEG_ENC_STATUS_7_V3_MASK (0x1CU) #define JPEG_ENC_STATUS_7_V3_SHIFT (2U) /*! V3 - V3 */ #define JPEG_ENC_STATUS_7_V3(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_7_V3_SHIFT)) & JPEG_ENC_STATUS_7_V3_MASK) #define JPEG_ENC_STATUS_7_H3_MASK (0xE0U) #define JPEG_ENC_STATUS_7_H3_SHIFT (5U) /*! H3 - H3 */ #define JPEG_ENC_STATUS_7_H3(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_7_H3_SHIFT)) & JPEG_ENC_STATUS_7_H3_MASK) #define JPEG_ENC_STATUS_7_C3_MASK (0xFF00U) #define JPEG_ENC_STATUS_7_C3_SHIFT (8U) /*! C3 - C3 */ #define JPEG_ENC_STATUS_7_C3(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_7_C3_SHIFT)) & JPEG_ENC_STATUS_7_C3_MASK) /*! @} */ /*! @name STATUS_8 - */ /*! @{ */ #define JPEG_ENC_STATUS_8_Nf_MASK (0xFFU) #define JPEG_ENC_STATUS_8_Nf_SHIFT (0U) /*! Nf - Nf */ #define JPEG_ENC_STATUS_8_Nf(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_8_Nf_SHIFT)) & JPEG_ENC_STATUS_8_Nf_MASK) #define JPEG_ENC_STATUS_8_QUALITY_MASK (0xFF00U) #define JPEG_ENC_STATUS_8_QUALITY_SHIFT (8U) /*! QUALITY - QUALITY */ #define JPEG_ENC_STATUS_8_QUALITY(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_8_QUALITY_SHIFT)) & JPEG_ENC_STATUS_8_QUALITY_MASK) /*! @} */ /*! @name STATUS_9 - */ /*! @{ */ #define JPEG_ENC_STATUS_9_DRI_MASK (0xFFFFU) #define JPEG_ENC_STATUS_9_DRI_SHIFT (0U) /*! DRI - DRI */ #define JPEG_ENC_STATUS_9_DRI(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_9_DRI_SHIFT)) & JPEG_ENC_STATUS_9_DRI_MASK) /*! @} */ /*! @name STATUS_10 - */ /*! @{ */ #define JPEG_ENC_STATUS_10_Ns_MASK (0xFU) #define JPEG_ENC_STATUS_10_Ns_SHIFT (0U) /*! Ns - Ns */ #define JPEG_ENC_STATUS_10_Ns(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_10_Ns_SHIFT)) & JPEG_ENC_STATUS_10_Ns_MASK) #define JPEG_ENC_STATUS_10_NBMCU_MASK (0xF0U) #define JPEG_ENC_STATUS_10_NBMCU_SHIFT (4U) /*! NBMCU - NBMCU */ #define JPEG_ENC_STATUS_10_NBMCU(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_10_NBMCU_SHIFT)) & JPEG_ENC_STATUS_10_NBMCU_MASK) #define JPEG_ENC_STATUS_10_Vmax_MASK (0xF00U) #define JPEG_ENC_STATUS_10_Vmax_SHIFT (8U) /*! Vmax - Vmax */ #define JPEG_ENC_STATUS_10_Vmax(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_10_Vmax_SHIFT)) & JPEG_ENC_STATUS_10_Vmax_MASK) #define JPEG_ENC_STATUS_10_Hmax_MASK (0xF000U) #define JPEG_ENC_STATUS_10_Hmax_SHIFT (12U) /*! Hmax - Hmax */ #define JPEG_ENC_STATUS_10_Hmax(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_10_Hmax_SHIFT)) & JPEG_ENC_STATUS_10_Hmax_MASK) /*! @} */ /*! @name STATUS_11 - */ /*! @{ */ #define JPEG_ENC_STATUS_11_VHS0_MASK (0xFU) #define JPEG_ENC_STATUS_11_VHS0_SHIFT (0U) /*! VHS0 - VHS0 */ #define JPEG_ENC_STATUS_11_VHS0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_11_VHS0_SHIFT)) & JPEG_ENC_STATUS_11_VHS0_MASK) #define JPEG_ENC_STATUS_11_VHS1_MASK (0xF0U) #define JPEG_ENC_STATUS_11_VHS1_SHIFT (4U) /*! VHS1 - VHS1 */ #define JPEG_ENC_STATUS_11_VHS1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_11_VHS1_SHIFT)) & JPEG_ENC_STATUS_11_VHS1_MASK) #define JPEG_ENC_STATUS_11_VHS2_MASK (0xF00U) #define JPEG_ENC_STATUS_11_VHS2_SHIFT (8U) /*! VHS2 - VHS2 */ #define JPEG_ENC_STATUS_11_VHS2(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_11_VHS2_SHIFT)) & JPEG_ENC_STATUS_11_VHS2_MASK) #define JPEG_ENC_STATUS_11_VHS3_MASK (0xF000U) #define JPEG_ENC_STATUS_11_VHS3_SHIFT (12U) /*! VHS3 - VHS3 */ #define JPEG_ENC_STATUS_11_VHS3(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_11_VHS3_SHIFT)) & JPEG_ENC_STATUS_11_VHS3_MASK) /*! @} */ /*! @name STATUS_12 - */ /*! @{ */ #define JPEG_ENC_STATUS_12_COM_E_MASK (0x1U) #define JPEG_ENC_STATUS_12_COM_E_SHIFT (0U) /*! COM_E - COM_E */ #define JPEG_ENC_STATUS_12_COM_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_COM_E_SHIFT)) & JPEG_ENC_STATUS_12_COM_E_MASK) #define JPEG_ENC_STATUS_12_APPn_E_MASK (0x2U) #define JPEG_ENC_STATUS_12_APPn_E_SHIFT (1U) /*! APPn_E - APPn_E */ #define JPEG_ENC_STATUS_12_APPn_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_APPn_E_SHIFT)) & JPEG_ENC_STATUS_12_APPn_E_MASK) #define JPEG_ENC_STATUS_12_DRI_E_MASK (0x4U) #define JPEG_ENC_STATUS_12_DRI_E_SHIFT (2U) /*! DRI_E - DRI_E */ #define JPEG_ENC_STATUS_12_DRI_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_DRI_E_SHIFT)) & JPEG_ENC_STATUS_12_DRI_E_MASK) #define JPEG_ENC_STATUS_12_DNL_E_MASK (0x8U) #define JPEG_ENC_STATUS_12_DNL_E_SHIFT (3U) /*! DNL_E - DNL_E */ #define JPEG_ENC_STATUS_12_DNL_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_DNL_E_SHIFT)) & JPEG_ENC_STATUS_12_DNL_E_MASK) #define JPEG_ENC_STATUS_12_DHT_E_MASK (0x10U) #define JPEG_ENC_STATUS_12_DHT_E_SHIFT (4U) /*! DHT_E - DHT_E */ #define JPEG_ENC_STATUS_12_DHT_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_DHT_E_SHIFT)) & JPEG_ENC_STATUS_12_DHT_E_MASK) #define JPEG_ENC_STATUS_12_DQT_E_MASK (0x20U) #define JPEG_ENC_STATUS_12_DQT_E_SHIFT (5U) /*! DQT_E - DQT_E */ #define JPEG_ENC_STATUS_12_DQT_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_DQT_E_SHIFT)) & JPEG_ENC_STATUS_12_DQT_E_MASK) #define JPEG_ENC_STATUS_12_SOS_E_MASK (0x40U) #define JPEG_ENC_STATUS_12_SOS_E_SHIFT (6U) /*! SOS_E - SOS_E */ #define JPEG_ENC_STATUS_12_SOS_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_SOS_E_SHIFT)) & JPEG_ENC_STATUS_12_SOS_E_MASK) #define JPEG_ENC_STATUS_12_SOF_E_MASK (0x80U) #define JPEG_ENC_STATUS_12_SOF_E_SHIFT (7U) /*! SOF_E - SOF_E */ #define JPEG_ENC_STATUS_12_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_SOF_E_SHIFT)) & JPEG_ENC_STATUS_12_SOF_E_MASK) #define JPEG_ENC_STATUS_12_CONFIGERROR_MASK (0x100U) #define JPEG_ENC_STATUS_12_CONFIGERROR_SHIFT (8U) /*! CONFIGERROR - CONFIGERROR */ #define JPEG_ENC_STATUS_12_CONFIGERROR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_CONFIGERROR_SHIFT)) & JPEG_ENC_STATUS_12_CONFIGERROR_MASK) #define JPEG_ENC_STATUS_12_JPEGIN_RDY_MASK (0x200U) #define JPEG_ENC_STATUS_12_JPEGIN_RDY_SHIFT (9U) /*! JPEGIN_RDY - JPEGIN_RDY */ #define JPEG_ENC_STATUS_12_JPEGIN_RDY(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_JPEGIN_RDY_SHIFT)) & JPEG_ENC_STATUS_12_JPEGIN_RDY_MASK) #define JPEG_ENC_STATUS_12_PIXELIN_RDY_MASK (0x400U) #define JPEG_ENC_STATUS_12_PIXELIN_RDY_SHIFT (10U) /*! PIXELIN_RDY - PIXELIN_RDY */ #define JPEG_ENC_STATUS_12_PIXELIN_RDY(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_PIXELIN_RDY_SHIFT)) & JPEG_ENC_STATUS_12_PIXELIN_RDY_MASK) #define JPEG_ENC_STATUS_12_SCANACTIVE_MASK (0x800U) #define JPEG_ENC_STATUS_12_SCANACTIVE_SHIFT (11U) /*! SCANACTIVE - SCANACTIVE */ #define JPEG_ENC_STATUS_12_SCANACTIVE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_12_SCANACTIVE_SHIFT)) & JPEG_ENC_STATUS_12_SCANACTIVE_MASK) /*! @} */ /*! @name STATUS_13 - */ /*! @{ */ #define JPEG_ENC_STATUS_13_CFG_MODE_MASK (0xFFFFU) #define JPEG_ENC_STATUS_13_CFG_MODE_SHIFT (0U) /*! CFG_MODE - CFG_MODE */ #define JPEG_ENC_STATUS_13_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_13_CFG_MODE_SHIFT)) & JPEG_ENC_STATUS_13_CFG_MODE_MASK) /*! @} */ /*! @name STATUS_14 - */ /*! @{ */ #define JPEG_ENC_STATUS_14_RC_REGS0_MASK (0xFFFFU) #define JPEG_ENC_STATUS_14_RC_REGS0_SHIFT (0U) /*! RC_REGS0 - RC_REGS0 */ #define JPEG_ENC_STATUS_14_RC_REGS0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_14_RC_REGS0_SHIFT)) & JPEG_ENC_STATUS_14_RC_REGS0_MASK) /*! @} */ /*! @name STATUS_15 - */ /*! @{ */ #define JPEG_ENC_STATUS_15_RC_REGS1_MASK (0xFFFFU) #define JPEG_ENC_STATUS_15_RC_REGS1_SHIFT (0U) /*! RC_REGS1 - RC_REGS1 */ #define JPEG_ENC_STATUS_15_RC_REGS1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_15_RC_REGS1_SHIFT)) & JPEG_ENC_STATUS_15_RC_REGS1_MASK) /*! @} */ /*! @name STATUS_16 - */ /*! @{ */ #define JPEG_ENC_STATUS_16_NOMFRSIZE_LO_MASK (0xFFFFU) #define JPEG_ENC_STATUS_16_NOMFRSIZE_LO_SHIFT (0U) /*! NOMFRSIZE_LO - NOMFRSIZE_LO */ #define JPEG_ENC_STATUS_16_NOMFRSIZE_LO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_16_NOMFRSIZE_LO_SHIFT)) & JPEG_ENC_STATUS_16_NOMFRSIZE_LO_MASK) /*! @} */ /*! @name STATUS_17 - */ /*! @{ */ #define JPEG_ENC_STATUS_17_NOMFRSIZE_HI_MASK (0xFFFFU) #define JPEG_ENC_STATUS_17_NOMFRSIZE_HI_SHIFT (0U) /*! NOMFRSIZE_HI - NOMFRSIZE_HI */ #define JPEG_ENC_STATUS_17_NOMFRSIZE_HI(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_17_NOMFRSIZE_HI_SHIFT)) & JPEG_ENC_STATUS_17_NOMFRSIZE_HI_MASK) /*! @} */ /*! @name STATUS_18 - */ /*! @{ */ #define JPEG_ENC_STATUS_18_OFBSIZE_LO_MASK (0xFFFFU) #define JPEG_ENC_STATUS_18_OFBSIZE_LO_SHIFT (0U) /*! OFBSIZE_LO - OFBSIZE_LO */ #define JPEG_ENC_STATUS_18_OFBSIZE_LO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_18_OFBSIZE_LO_SHIFT)) & JPEG_ENC_STATUS_18_OFBSIZE_LO_MASK) /*! @} */ /*! @name STATUS_19 - */ /*! @{ */ #define JPEG_ENC_STATUS_19_OFBSIZE_HI_MASK (0xFFFFU) #define JPEG_ENC_STATUS_19_OFBSIZE_HI_SHIFT (0U) /*! OFBSIZE_HI - OFBSIZE_HI */ #define JPEG_ENC_STATUS_19_OFBSIZE_HI(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_STATUS_19_OFBSIZE_HI_SHIFT)) & JPEG_ENC_STATUS_19_OFBSIZE_HI_MASK) /*! @} */ /*! * @} */ /* end of group JPEG_ENC_Register_Masks */ /* JPEG_ENC - Peripheral instance base addresses */ /** Peripheral IMAGING__ENCODE_U_JPEG_E_X_NOMEM base address */ #define IMAGING__ENCODE_U_JPEG_E_X_NOMEM_BASE (0x585F0000u) /** Peripheral IMAGING__ENCODE_U_JPEG_E_X_NOMEM base pointer */ #define IMAGING__ENCODE_U_JPEG_E_X_NOMEM ((JPEG_ENC_Type *)IMAGING__ENCODE_U_JPEG_E_X_NOMEM_BASE) /** Array initializer of JPEG_ENC peripheral base addresses */ #define JPEG_ENC_BASE_ADDRS { IMAGING__ENCODE_U_JPEG_E_X_NOMEM_BASE } /** Array initializer of JPEG_ENC peripheral base pointers */ #define JPEG_ENC_BASE_PTRS { IMAGING__ENCODE_U_JPEG_E_X_NOMEM } /*! * @} */ /* end of group JPEG_ENC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- JPEG_ENC_WRAPPER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_ENC_WRAPPER_Peripheral_Access_Layer JPEG_ENC_WRAPPER Peripheral Access Layer * @{ */ /** JPEG_ENC_WRAPPER - Register Layout Typedef */ typedef struct { __IO uint32_t GLB_CTRL; /**< Global Control, offset: 0x0 */ __I uint32_t COM_STATUS; /**< Common Status, offset: 0x4 */ uint32_t RSVD_COM_IRQ_EN; /**< RSVD, offset: 0x8 */ uint32_t RSVD_CUR_DESCPT_PTR; /**< RSVD, offset: 0xC */ uint32_t RSVD_NXT_DESCPT_PTR; /**< RSVD, offset: 0x10 */ __IO uint32_t IN_BUF_BASE0; /**< Input Image Frame Buffer0 Base Address, offset: 0x14 */ __IO uint32_t IN_BUF_BASE1; /**< Input Image Frame Buffer1 Base Address, offset: 0x18 */ __IO uint32_t IN_LINE_PITCH; /**< Image Input Buffer Line Pitch, offset: 0x1C */ __IO uint32_t STM_BUFBASE; /**< Output JPEG Stream Buffer Base Address, offset: 0x20 */ __IO uint32_t STM_BUFSIZE; /**< Output JPEG Stream Buffer Size, offset: 0x24 */ __IO uint32_t IMGSIZE; /**< Image Resolution, offset: 0x28 */ __IO uint32_t STM_CTRL; /**< Bit Stream Switch and Control, offset: 0x2C */ uint8_t RESERVED_0[65488]; struct { /* offset: 0x10000, array step: 0x10000 */ __IO uint32_t SLOT_STATUS; /**< Bit Stream SLOT Status, array offset: 0x10000, array step: 0x10000 */ __IO uint32_t SLOT_IRQ_EN; /**< Bit Stream Interrupt Enable Register, array offset: 0x10004, array step: 0x10000 */ __I uint32_t SLOT_BUF_PTR; /**< Bit Stream Buffer Pointer, array offset: 0x10008, array step: 0x10000 */ __I uint32_t SLOT_CUR_DESCPT_PTR; /**< Current Encoding Descriptor Pointer, array offset: 0x1000C, array step: 0x10000 */ __IO uint32_t SLOT_NXT_DESCPT_PTR; /**< Next Encoding Descriptor Pointer, array offset: 0x10010, array step: 0x10000 */ uint8_t RESERVED_0[65516]; } BIT_STREAM[4]; } JPEG_ENC_WRAPPER_Type; /* ---------------------------------------------------------------------------- -- JPEG_ENC_WRAPPER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_ENC_WRAPPER_Register_Masks JPEG_ENC_WRAPPER Register Masks * @{ */ /*! @name GLB_CTRL - Global Control */ /*! @{ */ #define JPEG_ENC_WRAPPER_GLB_CTRL_JPG_ENC_EN_MASK (0x1U) #define JPEG_ENC_WRAPPER_GLB_CTRL_JPG_ENC_EN_SHIFT (0U) /*! JPG_ENC_EN - JPEG Encoder and the wrapper enable bit */ #define JPEG_ENC_WRAPPER_GLB_CTRL_JPG_ENC_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_GLB_CTRL_JPG_ENC_EN_SHIFT)) & JPEG_ENC_WRAPPER_GLB_CTRL_JPG_ENC_EN_MASK) #define JPEG_ENC_WRAPPER_GLB_CTRL_SFTRST_MASK (0x2U) #define JPEG_ENC_WRAPPER_GLB_CTRL_SFTRST_SHIFT (1U) /*! SFTRST - Engine Soft reset */ #define JPEG_ENC_WRAPPER_GLB_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_GLB_CTRL_SFTRST_SHIFT)) & JPEG_ENC_WRAPPER_GLB_CTRL_SFTRST_MASK) #define JPEG_ENC_WRAPPER_GLB_CTRL_ENC_GO_MASK (0x4U) #define JPEG_ENC_WRAPPER_GLB_CTRL_ENC_GO_SHIFT (2U) /*! ENC_GO - Start Encoding */ #define JPEG_ENC_WRAPPER_GLB_CTRL_ENC_GO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_GLB_CTRL_ENC_GO_SHIFT)) & JPEG_ENC_WRAPPER_GLB_CTRL_ENC_GO_MASK) #define JPEG_ENC_WRAPPER_GLB_CTRL_L_ENDIAN_MASK (0x8U) #define JPEG_ENC_WRAPPER_GLB_CTRL_L_ENDIAN_SHIFT (3U) /*! L_ENDIAN - Little Endian */ #define JPEG_ENC_WRAPPER_GLB_CTRL_L_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_GLB_CTRL_L_ENDIAN_SHIFT)) & JPEG_ENC_WRAPPER_GLB_CTRL_L_ENDIAN_MASK) #define JPEG_ENC_WRAPPER_GLB_CTRL_SLOT_EN_MASK (0xF0U) #define JPEG_ENC_WRAPPER_GLB_CTRL_SLOT_EN_SHIFT (4U) /*! SLOT_EN - Slot Enable */ #define JPEG_ENC_WRAPPER_GLB_CTRL_SLOT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_GLB_CTRL_SLOT_EN_SHIFT)) & JPEG_ENC_WRAPPER_GLB_CTRL_SLOT_EN_MASK) /*! @} */ /*! @name COM_STATUS - Common Status */ /*! @{ */ #define JPEG_ENC_WRAPPER_COM_STATUS_CUR_SLOT_MASK (0x60000000U) #define JPEG_ENC_WRAPPER_COM_STATUS_CUR_SLOT_SHIFT (29U) /*! CUR_SLOT - Current executing bitstream slot */ #define JPEG_ENC_WRAPPER_COM_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_COM_STATUS_CUR_SLOT_SHIFT)) & JPEG_ENC_WRAPPER_COM_STATUS_CUR_SLOT_MASK) #define JPEG_ENC_WRAPPER_COM_STATUS_ENC_ONGOING_MASK (0x80000000U) #define JPEG_ENC_WRAPPER_COM_STATUS_ENC_ONGOING_SHIFT (31U) /*! ENC_ONGOING - Indicating the encoding is ongoing. */ #define JPEG_ENC_WRAPPER_COM_STATUS_ENC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_COM_STATUS_ENC_ONGOING_SHIFT)) & JPEG_ENC_WRAPPER_COM_STATUS_ENC_ONGOING_MASK) /*! @} */ /*! @name IN_BUF_BASE0 - Input Image Frame Buffer0 Base Address */ /*! @{ */ #define JPEG_ENC_WRAPPER_IN_BUF_BASE0_IN_BUF_BASE0_MASK (0xFFFFFFF0U) #define JPEG_ENC_WRAPPER_IN_BUF_BASE0_IN_BUF_BASE0_SHIFT (4U) /*! IN_BUF_BASE0 - Frame Buffer0 Base Address */ #define JPEG_ENC_WRAPPER_IN_BUF_BASE0_IN_BUF_BASE0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_IN_BUF_BASE0_IN_BUF_BASE0_SHIFT)) & JPEG_ENC_WRAPPER_IN_BUF_BASE0_IN_BUF_BASE0_MASK) /*! @} */ /*! @name IN_BUF_BASE1 - Input Image Frame Buffer1 Base Address */ /*! @{ */ #define JPEG_ENC_WRAPPER_IN_BUF_BASE1_IN_BUF_BASE1_MASK (0xFFFFFFF0U) #define JPEG_ENC_WRAPPER_IN_BUF_BASE1_IN_BUF_BASE1_SHIFT (4U) /*! IN_BUF_BASE1 - JPEG Encoder and the wrapper enable bit. */ #define JPEG_ENC_WRAPPER_IN_BUF_BASE1_IN_BUF_BASE1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_IN_BUF_BASE1_IN_BUF_BASE1_SHIFT)) & JPEG_ENC_WRAPPER_IN_BUF_BASE1_IN_BUF_BASE1_MASK) /*! @} */ /*! @name IN_LINE_PITCH - Image Input Buffer Line Pitch */ /*! @{ */ #define JPEG_ENC_WRAPPER_IN_LINE_PITCH_In_line_pitch_MASK (0xFFFFU) #define JPEG_ENC_WRAPPER_IN_LINE_PITCH_In_line_pitch_SHIFT (0U) /*! In_line_pitch - image line stride setting in the memory */ #define JPEG_ENC_WRAPPER_IN_LINE_PITCH_In_line_pitch(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_IN_LINE_PITCH_In_line_pitch_SHIFT)) & JPEG_ENC_WRAPPER_IN_LINE_PITCH_In_line_pitch_MASK) /*! @} */ /*! @name STM_BUFBASE - Output JPEG Stream Buffer Base Address */ /*! @{ */ #define JPEG_ENC_WRAPPER_STM_BUFBASE_STM_BUFBASE_MASK (0xFFFFFFF0U) #define JPEG_ENC_WRAPPER_STM_BUFBASE_STM_BUFBASE_SHIFT (4U) /*! STM_BUFBASE - Bitstream BUF BASE */ #define JPEG_ENC_WRAPPER_STM_BUFBASE_STM_BUFBASE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_BUFBASE_STM_BUFBASE_SHIFT)) & JPEG_ENC_WRAPPER_STM_BUFBASE_STM_BUFBASE_MASK) /*! @} */ /*! @name STM_BUFSIZE - Output JPEG Stream Buffer Size */ /*! @{ */ #define JPEG_ENC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_MASK (0xFFFFFC00U) #define JPEG_ENC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_SHIFT (10U) /*! STM_BUFSIZE - Bitstream Buffer Size */ #define JPEG_ENC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & JPEG_ENC_WRAPPER_STM_BUFSIZE_STM_BUFSIZE_MASK) /*! @} */ /*! @name IMGSIZE - Image Resolution */ /*! @{ */ #define JPEG_ENC_WRAPPER_IMGSIZE_img_height_MASK (0x3FFFU) #define JPEG_ENC_WRAPPER_IMGSIZE_img_height_SHIFT (0U) /*! img_height - image height */ #define JPEG_ENC_WRAPPER_IMGSIZE_img_height(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_IMGSIZE_img_height_SHIFT)) & JPEG_ENC_WRAPPER_IMGSIZE_img_height_MASK) #define JPEG_ENC_WRAPPER_IMGSIZE_img_width_MASK (0x3FFF0000U) #define JPEG_ENC_WRAPPER_IMGSIZE_img_width_SHIFT (16U) /*! img_width - image width */ #define JPEG_ENC_WRAPPER_IMGSIZE_img_width(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_IMGSIZE_img_width_SHIFT)) & JPEG_ENC_WRAPPER_IMGSIZE_img_width_MASK) /*! @} */ /*! @name STM_CTRL - Bit Stream Switch and Control */ /*! @{ */ #define JPEG_ENC_WRAPPER_STM_CTRL_pixel_precision_MASK (0x4U) #define JPEG_ENC_WRAPPER_STM_CTRL_pixel_precision_SHIFT (2U) /*! pixel_precision - Current encoding precision: 8bit or 12bit. */ #define JPEG_ENC_WRAPPER_STM_CTRL_pixel_precision(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_CTRL_pixel_precision_SHIFT)) & JPEG_ENC_WRAPPER_STM_CTRL_pixel_precision_MASK) #define JPEG_ENC_WRAPPER_STM_CTRL_image_format_MASK (0x78U) #define JPEG_ENC_WRAPPER_STM_CTRL_image_format_SHIFT (3U) /*! image_format - Image format for encoding * 0b0000..Image format is YUV420 (2 Plannar, Y at the 1st plannar and UV at the second plannar). * 0b0001..Image format is YUV422 (1 Plannar in YUYV sequence) * 0b0010..Image format is RGB (RGBRGB packed format) * 0b0011..Image format is YUV444 ( 1 Plannar in YUVYUV sequence) * 0b0100..Image format is Gray (Y8 or Y12) or Single Component * 0b0101..Reserved for Future Usage. * 0b0110..Image format is ARGB (ARGBARGB packed format) */ #define JPEG_ENC_WRAPPER_STM_CTRL_image_format(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_CTRL_image_format_SHIFT)) & JPEG_ENC_WRAPPER_STM_CTRL_image_format_MASK) #define JPEG_ENC_WRAPPER_STM_CTRL_bitbuf_ptr_clr_MASK (0x80U) #define JPEG_ENC_WRAPPER_STM_CTRL_bitbuf_ptr_clr_SHIFT (7U) /*! bitbuf_ptr_clr - Clear the bitstream buffer pointer for current ID * 0b0..After the context switching, the bitstream buffer point is restored to last time when the bitstream is switched out. * 0b1..Clear the bitstream buffer pointer after the context switching, and encoding output start from base of bit buffer. */ #define JPEG_ENC_WRAPPER_STM_CTRL_bitbuf_ptr_clr(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_CTRL_bitbuf_ptr_clr_SHIFT)) & JPEG_ENC_WRAPPER_STM_CTRL_bitbuf_ptr_clr_MASK) #define JPEG_ENC_WRAPPER_STM_CTRL_AUTO_START_MASK (0x100U) #define JPEG_ENC_WRAPPER_STM_CTRL_AUTO_START_SHIFT (8U) /*! AUTO_START - Automatically write "GO" to Cast Encoder after context switching * 0b0..Will not write any CAST JPEG Encoder Control register. * 0b1..Will write "1" to Cast JPEG Encoder [Go] Control Register. */ #define JPEG_ENC_WRAPPER_STM_CTRL_AUTO_START(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_CTRL_AUTO_START_SHIFT)) & JPEG_ENC_WRAPPER_STM_CTRL_AUTO_START_MASK) #define JPEG_ENC_WRAPPER_STM_CTRL_Config_Mod_MASK (0x200U) #define JPEG_ENC_WRAPPER_STM_CTRL_Config_Mod_SHIFT (9U) /*! Config_Mod - Current Encoding precision: 8bit or 12bit. */ #define JPEG_ENC_WRAPPER_STM_CTRL_Config_Mod(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_STM_CTRL_Config_Mod_SHIFT)) & JPEG_ENC_WRAPPER_STM_CTRL_Config_Mod_MASK) /*! @} */ /*! @name SLOT_STATUS - Bit Stream SLOT Status */ /*! @{ */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_HALF_MASK (0x1U) #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_HALF_SHIFT (0U) /*! STMBUF_HALF - Indicating the stream buf pointer has come over half size of the buf size. */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_HALF(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_HALF_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_HALF_MASK) #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_RTND_MASK (0x2U) #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_RTND_SHIFT (1U) /*! STMBUF_RTND - Indicating the stream buf pointer has come over the top size of the stream buffer. */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_RTND(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_RTND_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_STMBUF_RTND_MASK) #define JPEG_ENC_WRAPPER_SLOT_STATUS_SWITCHED_IN_MASK (0x4U) #define JPEG_ENC_WRAPPER_SLOT_STATUS_SWITCHED_IN_SHIFT (2U) /*! SWITCHED_IN - Descriptor fetched completed during for this bitstream ID */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_SWITCHED_IN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_SWITCHED_IN_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_SWITCHED_IN_MASK) #define JPEG_ENC_WRAPPER_SLOT_STATUS_FRMDONE_MASK (0x8U) #define JPEG_ENC_WRAPPER_SLOT_STATUS_FRMDONE_SHIFT (3U) /*! FRMDONE - One frame of image Encoding finished */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_FRMDONE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_FRMDONE_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_FRMDONE_MASK) #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_CONFG_ERR_MASK (0x100U) #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_CONFG_ERR_SHIFT (8U) /*! ENC_CONFG_ERR - Cast JPEG Encoder Configure error flag */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_CONFG_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_CONFG_ERR_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_CONFG_ERR_MASK) #define JPEG_ENC_WRAPPER_SLOT_STATUS_DES_RD_ERR_MASK (0x200U) #define JPEG_ENC_WRAPPER_SLOT_STATUS_DES_RD_ERR_SHIFT (9U) /*! DES_RD_ERR - AXI Read error status for descriptor fetching */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_DES_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_DES_RD_ERR_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_DES_RD_ERR_MASK) #define JPEG_ENC_WRAPPER_SLOT_STATUS_BIT_WT_ERR_MASK (0x400U) #define JPEG_ENC_WRAPPER_SLOT_STATUS_BIT_WT_ERR_SHIFT (10U) /*! BIT_WT_ERR - AXI Write error status for bitstream storing */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_BIT_WT_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_BIT_WT_ERR_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_BIT_WT_ERR_MASK) #define JPEG_ENC_WRAPPER_SLOT_STATUS_IMG_RD_ERR_MASK (0x800U) #define JPEG_ENC_WRAPPER_SLOT_STATUS_IMG_RD_ERR_SHIFT (11U) /*! IMG_RD_ERR - AXI Read error status for image or configuration bitstream fetching */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_IMG_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_IMG_RD_ERR_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_IMG_RD_ERR_MASK) #define JPEG_ENC_WRAPPER_SLOT_STATUS_CUR_SLOT_MASK (0x60000000U) #define JPEG_ENC_WRAPPER_SLOT_STATUS_CUR_SLOT_SHIFT (29U) /*! CUR_SLOT - Current Executing bitstream slot */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_CUR_SLOT_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_CUR_SLOT_MASK) #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_ONGOING_MASK (0x80000000U) #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_ONGOING_SHIFT (31U) /*! ENC_ONGOING - Indicating the encoding is ongoing. */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_ONGOING_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_STATUS_ENC_ONGOING_MASK) /*! @} */ /* The count of JPEG_ENC_WRAPPER_SLOT_STATUS */ #define JPEG_ENC_WRAPPER_SLOT_STATUS_COUNT (4U) /*! @name SLOT_IRQ_EN - Bit Stream Interrupt Enable Register */ /*! @{ */ #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_irq_en_MASK (0x1U) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_irq_en_SHIFT (0U) /*! STMBUF_HALF_irq_en - Interrupt enable for current buf pointer over half size of the buf size. */ #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_HALF_irq_en_MASK) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_irq_en_MASK (0x2U) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_irq_en_SHIFT (1U) /*! STMBUF_RTND_irq_en - Interrupt enable for current buf pointer wrapper over the top size of the stream buffer. */ #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_STMBUF_RTND_irq_en_MASK) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_SWITHCED_IN_irq_en_MASK (0x4U) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_SWITHCED_IN_irq_en_SHIFT (2U) /*! SWITHCED_IN_irq_en - Indicating the stream buf pointer has come over half size of the buf size. */ #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_SWITHCED_IN_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_SWITHCED_IN_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_SWITHCED_IN_irq_en_MASK) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_FRMDONE_irq_en_MASK (0x8U) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_FRMDONE_irq_en_SHIFT (3U) /*! FRMDONE_irq_en - Frame encoding finished interrupt enable */ #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_FRMDONE_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_FRMDONE_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_FRMDONE_irq_en_MASK) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_ENC_CONFG_ERR_irq_en_MASK (0x100U) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_ENC_CONFG_ERR_irq_en_SHIFT (8U) /*! ENC_CONFG_ERR_irq_en - Encoder Configure Error Interrupt Enable */ #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_ENC_CONFG_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_ENC_CONFG_ERR_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_ENC_CONFG_ERR_irq_en_MASK) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_MASK (0x200U) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_SHIFT (9U) /*! DES_RD_ERR_irq_en - AXI read error interrupt enable */ #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_DES_RD_ERR_irq_en_MASK) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_BIT_WT_ERR_irq_en_MASK (0x400U) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_BIT_WT_ERR_irq_en_SHIFT (10U) /*! BIT_WT_ERR_irq_en - AXI write error interrupt enable */ #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_BIT_WT_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_BIT_WT_ERR_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_BIT_WT_ERR_irq_en_MASK) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_IMG_RD_ERR_irq_en_MASK (0x800U) #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_IMG_RD_ERR_irq_en_SHIFT (11U) /*! IMG_RD_ERR_irq_en - AXI write error interrupt enable */ #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_IMG_RD_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_IRQ_EN_IMG_RD_ERR_irq_en_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_IRQ_EN_IMG_RD_ERR_irq_en_MASK) /*! @} */ /* The count of JPEG_ENC_WRAPPER_SLOT_IRQ_EN */ #define JPEG_ENC_WRAPPER_SLOT_IRQ_EN_COUNT (4U) /*! @name SLOT_BUF_PTR - Bit Stream Buffer Pointer */ /*! @{ */ #define JPEG_ENC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_MASK (0xFFFFFFFFU) #define JPEG_ENC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_SHIFT (0U) /*! stmbuf_ptr - stream0 buf pointer */ #define JPEG_ENC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_BUF_PTR_stmbuf_ptr_MASK) /*! @} */ /* The count of JPEG_ENC_WRAPPER_SLOT_BUF_PTR */ #define JPEG_ENC_WRAPPER_SLOT_BUF_PTR_COUNT (4U) /*! @name SLOT_CUR_DESCPT_PTR - Current Encoding Descriptor Pointer */ /*! @{ */ #define JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK (0xFFFFFFFCU) #define JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT (2U) /*! CUR_DESCPT_PRT - current slot the fetched descriptors pointer. */ #define JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK) /*! @} */ /* The count of JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR */ #define JPEG_ENC_WRAPPER_SLOT_CUR_DESCPT_PTR_COUNT (4U) /*! @name SLOT_NXT_DESCPT_PTR - Next Encoding Descriptor Pointer */ /*! @{ */ #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_MASK (0x1U) #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_SHIFT (0U) /*! NXT_DESCPT_PTR_EN - slot next stream descriptor pointor enable */ #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_MASK) #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK (0xFFFFFFFCU) #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT (2U) /*! NXT_DESCPT_PRT - slot next encoding descriptors pointer */ #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT)) & JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK) /*! @} */ /* The count of JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR */ #define JPEG_ENC_WRAPPER_SLOT_NXT_DESCPT_PTR_COUNT (4U) /*! * @} */ /* end of group JPEG_ENC_WRAPPER_Register_Masks */ /* JPEG_ENC_WRAPPER - Peripheral instance base addresses */ /** Peripheral IMAGING__ENCODE_U_JPEG_ENC_WRAPPER base address */ #define IMAGING__ENCODE_U_JPEG_ENC_WRAPPER_BASE (0x58450000u) /** Peripheral IMAGING__ENCODE_U_JPEG_ENC_WRAPPER base pointer */ #define IMAGING__ENCODE_U_JPEG_ENC_WRAPPER ((JPEG_ENC_WRAPPER_Type *)IMAGING__ENCODE_U_JPEG_ENC_WRAPPER_BASE) /** Array initializer of JPEG_ENC_WRAPPER peripheral base addresses */ #define JPEG_ENC_WRAPPER_BASE_ADDRS { IMAGING__ENCODE_U_JPEG_ENC_WRAPPER_BASE } /** Array initializer of JPEG_ENC_WRAPPER peripheral base pointers */ #define JPEG_ENC_WRAPPER_BASE_PTRS { IMAGING__ENCODE_U_JPEG_ENC_WRAPPER } /*! * @} */ /* end of group JPEG_ENC_WRAPPER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- KPP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer * @{ */ /** KPP - Register Layout Typedef */ typedef struct { __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ } KPP_Type; /* ---------------------------------------------------------------------------- -- KPP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup KPP_Register_Masks KPP Register Masks * @{ */ /*! @name KPCR - Keypad Control Register */ /*! @{ */ #define KPP_KPCR_KRE_MASK (0xFFU) #define KPP_KPCR_KRE_SHIFT (0U) /*! KRE - KRE * 0b00000000..Row is not included in the keypad key press detect. * 0b00000001..Row is included in the keypad key press detect. */ #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) #define KPP_KPCR_KCO_MASK (0xFF00U) #define KPP_KPCR_KCO_SHIFT (8U) /*! KCO - KCO * 0b00000000..Column strobe output is totem pole drive. * 0b00000001..Column strobe output is open drain. */ #define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) /*! @} */ /*! @name KPSR - Keypad Status Register */ /*! @{ */ #define KPP_KPSR_KPKD_MASK (0x1U) #define KPP_KPSR_KPKD_SHIFT (0U) /*! KPKD - KPKD * 0b0..No key presses detected * 0b1..A key has been depressed */ #define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) #define KPP_KPSR_KPKR_MASK (0x2U) #define KPP_KPSR_KPKR_SHIFT (1U) /*! KPKR - KPKR * 0b0..No key release detected * 0b1..All keys have been released */ #define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) #define KPP_KPSR_KDSC_MASK (0x4U) #define KPP_KPSR_KDSC_SHIFT (2U) /*! KDSC - KDSC * 0b0..No effect * 0b1..Set bits that clear the keypad depress synchronizer chain */ #define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) #define KPP_KPSR_KRSS_MASK (0x8U) #define KPP_KPSR_KRSS_SHIFT (3U) /*! KRSS - KRSS * 0b0..No effect * 0b1..Set bits which sets keypad release synchronizer chain */ #define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) #define KPP_KPSR_KDIE_MASK (0x100U) #define KPP_KPSR_KDIE_SHIFT (8U) /*! KDIE - KDIE * 0b0..No interrupt request is generated when KPKD is set. * 0b1..An interrupt request is generated when KPKD is set. */ #define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) #define KPP_KPSR_KRIE_MASK (0x200U) #define KPP_KPSR_KRIE_SHIFT (9U) /*! KRIE - KRIE * 0b0..No interrupt request is generated when KPKR is set. * 0b1..An interrupt request is generated when KPKR is set. */ #define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) /*! @} */ /*! @name KDDR - Keypad Data Direction Register */ /*! @{ */ #define KPP_KDDR_KRDD_MASK (0xFFU) #define KPP_KDDR_KRDD_SHIFT (0U) /*! KRDD - KRDD * 0b00000000..ROWn pin configured as an input. * 0b00000001..ROWn pin configured as an output. */ #define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) #define KPP_KDDR_KCDD_MASK (0xFF00U) #define KPP_KDDR_KCDD_SHIFT (8U) /*! KCDD - KCDD * 0b00000000..COLn pin is configured as an input. * 0b00000001..COLn pin is configured as an output. */ #define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) /*! @} */ /*! @name KPDR - Keypad Data Register */ /*! @{ */ #define KPP_KPDR_KRD_MASK (0xFFU) #define KPP_KPDR_KRD_SHIFT (0U) /*! KRD - KRD */ #define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) #define KPP_KPDR_KCD_MASK (0xFF00U) #define KPP_KPDR_KCD_SHIFT (8U) /*! KCD - KCD */ #define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) /*! @} */ /*! * @} */ /* end of group KPP_Register_Masks */ /* KPP - Peripheral instance base addresses */ /** Peripheral LSIO__KPP base address */ #define LSIO__KPP_BASE (0x5D1A0000u) /** Peripheral LSIO__KPP base pointer */ #define LSIO__KPP ((KPP_Type *)LSIO__KPP_BASE) /** Array initializer of KPP peripheral base addresses */ #define KPP_BASE_ADDRS { LSIO__KPP_BASE } /** Array initializer of KPP peripheral base pointers */ #define KPP_BASE_PTRS { LSIO__KPP } /** Interrupt vectors for the KPP peripheral type */ #define KPP_IRQS { LSIO_KPP_INT_IRQn } /*! * @} */ /* end of group KPP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LCDIF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer * @{ */ /** LCDIF - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */ __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */ __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */ __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */ __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */ __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */ __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */ __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */ __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */ __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */ __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */ __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */ __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ uint8_t RESERVED_1[12]; __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ uint8_t RESERVED_2[12]; __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ uint8_t RESERVED_3[12]; __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ uint8_t RESERVED_4[12]; __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ uint8_t RESERVED_5[12]; __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ uint8_t RESERVED_6[12]; __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ uint8_t RESERVED_7[12]; __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */ uint8_t RESERVED_8[12]; __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */ uint8_t RESERVED_9[12]; __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */ uint8_t RESERVED_10[12]; __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */ uint8_t RESERVED_11[12]; __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */ uint8_t RESERVED_12[12]; __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */ uint8_t RESERVED_13[12]; __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */ uint8_t RESERVED_14[12]; __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */ uint8_t RESERVED_15[12]; __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */ uint8_t RESERVED_16[12]; __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */ uint8_t RESERVED_17[12]; __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */ uint8_t RESERVED_18[12]; __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */ uint8_t RESERVED_19[12]; __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */ uint8_t RESERVED_20[12]; __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ uint8_t RESERVED_21[12]; __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ uint8_t RESERVED_22[12]; __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ uint8_t RESERVED_23[76]; __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ uint8_t RESERVED_24[12]; __IO uint32_t AS_CTRL; /**< LCDIF AS Buffer Control Register, offset: 0x210 */ uint8_t RESERVED_25[12]; __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ uint8_t RESERVED_26[12]; __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ uint8_t RESERVED_27[12]; __IO uint32_t AS_CLRKEYLOW; /**< LCDIF Overlay Color Key Low, offset: 0x240 */ uint8_t RESERVED_28[12]; __IO uint32_t AS_CLRKEYHIGH; /**< LCDIF Overlay Color Key High, offset: 0x250 */ uint8_t RESERVED_29[12]; __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ } LCDIF_Type; /* ---------------------------------------------------------------------------- -- LCDIF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LCDIF_Register_Masks LCDIF Register Masks * @{ */ /*! @name CTRL - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_RUN_MASK (0x1U) #define LCDIF_CTRL_RUN_SHIFT (0U) #define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) #define LCDIF_CTRL_MASTER_MASK (0x20U) #define LCDIF_CTRL_MASTER_SHIFT (5U) #define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK (0x80U) #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT (7U) #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK) #define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_DATA_SELECT_MASK (0x10000U) #define LCDIF_CTRL_DATA_SELECT_SHIFT (16U) /*! DATA_SELECT * 0b0..Command Mode. LCD_RS signal is Low. * 0b1..Data Mode. LCD_RS signal is High. */ #define LCDIF_CTRL_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK) #define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) #define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U) #define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U) #define LCDIF_CTRL_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK) #define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) #define LCDIF_CTRL_DVI_MODE_MASK (0x100000U) #define LCDIF_CTRL_DVI_MODE_SHIFT (20U) #define LCDIF_CTRL_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK) #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK) #define LCDIF_CTRL_READ_WRITEB_MASK (0x10000000U) #define LCDIF_CTRL_READ_WRITEB_SHIFT (28U) #define LCDIF_CTRL_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK) #define LCDIF_CTRL_YCBCR422_INPUT_MASK (0x20000000U) #define LCDIF_CTRL_YCBCR422_INPUT_SHIFT (29U) #define LCDIF_CTRL_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK) #define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) #define LCDIF_CTRL_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) /*! @} */ /*! @name CTRL_SET - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_SET_RUN_MASK (0x1U) #define LCDIF_CTRL_SET_RUN_SHIFT (0U) #define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) #define LCDIF_CTRL_SET_MASTER_MASK (0x20U) #define LCDIF_CTRL_SET_MASTER_SHIFT (5U) #define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK (0x80U) #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U) #define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK) #define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_SET_DATA_SELECT_MASK (0x10000U) #define LCDIF_CTRL_SET_DATA_SELECT_SHIFT (16U) /*! DATA_SELECT * 0b0..Command Mode. LCD_RS signal is Low. * 0b1..Data Mode. LCD_RS signal is High. */ #define LCDIF_CTRL_SET_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK) #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) #define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U) #define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U) #define LCDIF_CTRL_SET_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK) #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) #define LCDIF_CTRL_SET_DVI_MODE_MASK (0x100000U) #define LCDIF_CTRL_SET_DVI_MODE_SHIFT (20U) #define LCDIF_CTRL_SET_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) #define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK) #define LCDIF_CTRL_SET_READ_WRITEB_MASK (0x10000000U) #define LCDIF_CTRL_SET_READ_WRITEB_SHIFT (28U) #define LCDIF_CTRL_SET_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK) #define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK (0x20000000U) #define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT (29U) #define LCDIF_CTRL_SET_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK) #define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) #define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL_CLR - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_CLR_RUN_MASK (0x1U) #define LCDIF_CTRL_CLR_RUN_SHIFT (0U) #define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) #define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) #define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) #define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK (0x80U) #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U) #define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK) #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_CLR_DATA_SELECT_MASK (0x10000U) #define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT (16U) /*! DATA_SELECT * 0b0..Command Mode. LCD_RS signal is Low. * 0b1..Data Mode. LCD_RS signal is High. */ #define LCDIF_CTRL_CLR_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK) #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) #define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U) #define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U) #define LCDIF_CTRL_CLR_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK) #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) #define LCDIF_CTRL_CLR_DVI_MODE_MASK (0x100000U) #define LCDIF_CTRL_CLR_DVI_MODE_SHIFT (20U) #define LCDIF_CTRL_CLR_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) #define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK) #define LCDIF_CTRL_CLR_READ_WRITEB_MASK (0x10000000U) #define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT (28U) #define LCDIF_CTRL_CLR_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK) #define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK (0x20000000U) #define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT (29U) #define LCDIF_CTRL_CLR_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK) #define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) #define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) #define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL_TOG - LCDIF General Control Register */ /*! @{ */ #define LCDIF_CTRL_TOG_RUN_MASK (0x1U) #define LCDIF_CTRL_TOG_RUN_SHIFT (0U) #define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) #define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) #define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) #define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) #define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK (0x80U) #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U) #define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK) #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH * 0b00..Input data is 16 bits per pixel. * 0b01..Input data is 8 bits wide. * 0b10..Input data is 18 bits per pixel. * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH * 0b00..16-bit data bus mode. * 0b01..8-bit data bus mode. * 0b10..18-bit data bus mode. * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE * 0b00..No byte swapping.(Little endian) * 0b00..Little Endian byte ordering (same as NO_SWAP). * 0b01..Big Endian swap (swap bytes 0,3 and 1,2). * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). * 0b10..Swap half-words. * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_CTRL_TOG_DATA_SELECT_MASK (0x10000U) #define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT (16U) /*! DATA_SELECT * 0b0..Command Mode. LCD_RS signal is Low. * 0b1..Data Mode. LCD_RS signal is High. */ #define LCDIF_CTRL_TOG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK) #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) #define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U) #define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U) #define LCDIF_CTRL_TOG_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK) #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) #define LCDIF_CTRL_TOG_DVI_MODE_MASK (0x100000U) #define LCDIF_CTRL_TOG_DVI_MODE_SHIFT (20U) #define LCDIF_CTRL_TOG_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) #define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK) #define LCDIF_CTRL_TOG_READ_WRITEB_MASK (0x10000000U) #define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT (28U) #define LCDIF_CTRL_TOG_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK) #define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK (0x20000000U) #define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT (29U) #define LCDIF_CTRL_TOG_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK) #define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) #define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) #define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) /*! @} */ /*! @name CTRL1 - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_RESET_MASK (0x1U) #define LCDIF_CTRL1_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK) #define LCDIF_CTRL1_MODE86_MASK (0x2U) #define LCDIF_CTRL1_MODE86_SHIFT (1U) /*! MODE86 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. */ #define LCDIF_CTRL1_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK) #define LCDIF_CTRL1_BUSY_ENABLE_MASK (0x4U) #define LCDIF_CTRL1_BUSY_ENABLE_SHIFT (2U) /*! BUSY_ENABLE * 0b0..The busy signal from the LCD controller will be ignored. * 0b1..Enable the use of the busy signal from the LCD controller. */ #define LCDIF_CTRL1_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK) #define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK (0x8000000U) #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT (27U) #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK) /*! @} */ /*! @name CTRL1_SET - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_SET_RESET_MASK (0x1U) #define LCDIF_CTRL1_SET_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK) #define LCDIF_CTRL1_SET_MODE86_MASK (0x2U) #define LCDIF_CTRL1_SET_MODE86_SHIFT (1U) /*! MODE86 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. */ #define LCDIF_CTRL1_SET_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK) #define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK (0x4U) #define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT (2U) /*! BUSY_ENABLE * 0b0..The busy signal from the LCD controller will be ignored. * 0b1..Enable the use of the busy signal from the LCD controller. */ #define LCDIF_CTRL1_SET_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK) #define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U) #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U) #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK) /*! @} */ /*! @name CTRL1_CLR - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_CLR_RESET_MASK (0x1U) #define LCDIF_CTRL1_CLR_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK) #define LCDIF_CTRL1_CLR_MODE86_MASK (0x2U) #define LCDIF_CTRL1_CLR_MODE86_SHIFT (1U) /*! MODE86 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. */ #define LCDIF_CTRL1_CLR_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK) #define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK (0x4U) #define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT (2U) /*! BUSY_ENABLE * 0b0..The busy signal from the LCD controller will be ignored. * 0b1..Enable the use of the busy signal from the LCD controller. */ #define LCDIF_CTRL1_CLR_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK) #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U) #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U) #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK) /*! @} */ /*! @name CTRL1_TOG - LCDIF General Control1 Register */ /*! @{ */ #define LCDIF_CTRL1_TOG_RESET_MASK (0x1U) #define LCDIF_CTRL1_TOG_RESET_SHIFT (0U) /*! RESET * 0b0..LCD_RESET output signal is low. * 0b1..LCD_RESET output signal is high. */ #define LCDIF_CTRL1_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK) #define LCDIF_CTRL1_TOG_MODE86_MASK (0x2U) #define LCDIF_CTRL1_TOG_MODE86_SHIFT (1U) /*! MODE86 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively. */ #define LCDIF_CTRL1_TOG_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK) #define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK (0x4U) #define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT (2U) /*! BUSY_ENABLE * 0b0..The busy signal from the LCD controller will be ignored. * 0b1..Enable the use of the busy signal from the LCD controller. */ #define LCDIF_CTRL1_TOG_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK) #define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ * 0b0..No Interrupt Request Pending. * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U) #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U) #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK) /*! @} */ /*! @name CTRL2 - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_RSRVD0_MASK (0x1U) #define LCDIF_CTRL2_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0xEU) #define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT (1U) #define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK) #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK) #define LCDIF_CTRL2_RSRVD1_MASK (0x80U) #define LCDIF_CTRL2_RSRVD1_SHIFT (7U) #define LCDIF_CTRL2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK) #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK (0x100U) #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT (8U) #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK) #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) #define LCDIF_CTRL2_READ_PACK_DIR_MASK (0x400U) #define LCDIF_CTRL2_READ_PACK_DIR_SHIFT (10U) #define LCDIF_CTRL2_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK) #define LCDIF_CTRL2_RSRVD2_MASK (0x800U) #define LCDIF_CTRL2_RSRVD2_SHIFT (11U) #define LCDIF_CTRL2_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) #define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) /*! @} */ /*! @name CTRL2_SET - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_SET_RSRVD0_MASK (0x1U) #define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK (0xEU) #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U) #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK) #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK) #define LCDIF_CTRL2_SET_RSRVD1_MASK (0x80U) #define LCDIF_CTRL2_SET_RSRVD1_SHIFT (7U) #define LCDIF_CTRL2_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK) #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U) #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U) #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK) #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) #define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK (0x400U) #define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT (10U) #define LCDIF_CTRL2_SET_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK) #define LCDIF_CTRL2_SET_RSRVD2_MASK (0x800U) #define LCDIF_CTRL2_SET_RSRVD2_SHIFT (11U) #define LCDIF_CTRL2_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK) #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) /*! @} */ /*! @name CTRL2_CLR - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_CLR_RSRVD0_MASK (0x1U) #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK (0xEU) #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U) #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK) #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK) #define LCDIF_CTRL2_CLR_RSRVD1_MASK (0x80U) #define LCDIF_CTRL2_CLR_RSRVD1_SHIFT (7U) #define LCDIF_CTRL2_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK) #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U) #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U) #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK) #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) #define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK (0x400U) #define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT (10U) #define LCDIF_CTRL2_CLR_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK) #define LCDIF_CTRL2_CLR_RSRVD2_MASK (0x800U) #define LCDIF_CTRL2_CLR_RSRVD2_SHIFT (11U) #define LCDIF_CTRL2_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK) #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) /*! @} */ /*! @name CTRL2_TOG - LCDIF General Control2 Register */ /*! @{ */ #define LCDIF_CTRL2_TOG_RSRVD0_MASK (0x1U) #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK (0xEU) #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U) #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK) #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK) #define LCDIF_CTRL2_TOG_RSRVD1_MASK (0x80U) #define LCDIF_CTRL2_TOG_RSRVD1_SHIFT (7U) #define LCDIF_CTRL2_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK) #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U) #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U) #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK) #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) #define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK (0x400U) #define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT (10U) #define LCDIF_CTRL2_TOG_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK) #define LCDIF_CTRL2_TOG_RSRVD2_MASK (0x800U) #define LCDIF_CTRL2_TOG_RSRVD2_SHIFT (11U) #define LCDIF_CTRL2_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK) #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) #define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN * 0b000..RGB * 0b001..RBG * 0b010..GBR * 0b011..GRB * 0b100..BRG * 0b101..BGR */ #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) #define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS * 0b000..REQ_1 * 0b001..REQ_2 * 0b010..REQ_4 * 0b011..REQ_8 * 0b100..REQ_16 */ #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) /*! @} */ /*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ /*! @{ */ #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) #define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) #define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) /*! @} */ /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ /*! @{ */ #define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_CUR_BUF_ADDR_SHIFT (0U) #define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) /*! @} */ /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ /*! @{ */ #define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) #define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) /*! @} */ /*! @name TIMING - LCD Interface Timing Register */ /*! @{ */ #define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU) #define LCDIF_TIMING_DATA_SETUP_SHIFT (0U) #define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK) #define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U) #define LCDIF_TIMING_DATA_HOLD_SHIFT (8U) #define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK) #define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U) #define LCDIF_TIMING_CMD_SETUP_SHIFT (16U) #define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK) #define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U) #define LCDIF_TIMING_CMD_HOLD_SHIFT (24U) #define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK) /*! @} */ /*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) #define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) /*! @} */ /*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ /*! @{ */ #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) /*! @} */ /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ /*! @{ */ #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) /*! @} */ /*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ /*! @{ */ #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) #define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) #define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) #define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) /*! @} */ /*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ /*! @{ */ #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) #define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) #define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) #define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) /*! @} */ /*! @name DVICTRL0 - Digital Video Interface Control0 Register */ /*! @{ */ #define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK (0xFFFU) #define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT (0U) #define LCDIF_DVICTRL0_H_BLANKING_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK) #define LCDIF_DVICTRL0_RSRVD0_MASK (0xF000U) #define LCDIF_DVICTRL0_RSRVD0_SHIFT (12U) #define LCDIF_DVICTRL0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK) #define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK (0xFFF0000U) #define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT (16U) #define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK) #define LCDIF_DVICTRL0_RSRVD1_MASK (0xF0000000U) #define LCDIF_DVICTRL0_RSRVD1_SHIFT (28U) #define LCDIF_DVICTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK) /*! @} */ /*! @name DVICTRL1 - Digital Video Interface Control1 Register */ /*! @{ */ #define LCDIF_DVICTRL1_F2_START_LINE_MASK (0x3FFU) #define LCDIF_DVICTRL1_F2_START_LINE_SHIFT (0U) #define LCDIF_DVICTRL1_F2_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK) #define LCDIF_DVICTRL1_F1_END_LINE_MASK (0xFFC00U) #define LCDIF_DVICTRL1_F1_END_LINE_SHIFT (10U) #define LCDIF_DVICTRL1_F1_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK) #define LCDIF_DVICTRL1_F1_START_LINE_MASK (0x3FF00000U) #define LCDIF_DVICTRL1_F1_START_LINE_SHIFT (20U) #define LCDIF_DVICTRL1_F1_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK) #define LCDIF_DVICTRL1_RSRVD0_MASK (0xC0000000U) #define LCDIF_DVICTRL1_RSRVD0_SHIFT (30U) #define LCDIF_DVICTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK) /*! @} */ /*! @name DVICTRL2 - Digital Video Interface Control2 Register */ /*! @{ */ #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK (0x3FFU) #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT (0U) #define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK) #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK (0xFFC00U) #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U) #define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK) #define LCDIF_DVICTRL2_F2_END_LINE_MASK (0x3FF00000U) #define LCDIF_DVICTRL2_F2_END_LINE_SHIFT (20U) #define LCDIF_DVICTRL2_F2_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK) #define LCDIF_DVICTRL2_RSRVD0_MASK (0xC0000000U) #define LCDIF_DVICTRL2_RSRVD0_SHIFT (30U) #define LCDIF_DVICTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK) /*! @} */ /*! @name DVICTRL3 - Digital Video Interface Control3 Register */ /*! @{ */ #define LCDIF_DVICTRL3_V_LINES_CNT_MASK (0x3FFU) #define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT (0U) #define LCDIF_DVICTRL3_V_LINES_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK) #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK (0xFFC00U) #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT (10U) #define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK) #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK (0x3FF00000U) #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U) #define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK) #define LCDIF_DVICTRL3_RSRVD0_MASK (0xC0000000U) #define LCDIF_DVICTRL3_RSRVD0_SHIFT (30U) #define LCDIF_DVICTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK) /*! @} */ /*! @name DVICTRL4 - Digital Video Interface Control4 Register */ /*! @{ */ #define LCDIF_DVICTRL4_H_FILL_CNT_MASK (0xFFU) #define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT (0U) #define LCDIF_DVICTRL4_H_FILL_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK) #define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK (0xFF00U) #define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT (8U) #define LCDIF_DVICTRL4_CR_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK) #define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK (0xFF0000U) #define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT (16U) #define LCDIF_DVICTRL4_CB_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK) #define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK (0xFF000000U) #define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT (24U) #define LCDIF_DVICTRL4_Y_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK) /*! @} */ /*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */ /*! @{ */ #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U) #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U) /*! CSC_SUBSAMPLE_FILTER * 0b00..No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with all samples numbered 2n+1. * 0b01..Reserved * 0b10..Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) and that chroma value replaces the * two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway between the two luma samples. * 0b11..Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4, 1/2, 1/4) and that chroma value * exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are discarded. */ #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK) #define LCDIF_CSC_COEFF0_RSRVD0_MASK (0xFFFCU) #define LCDIF_CSC_COEFF0_RSRVD0_SHIFT (2U) #define LCDIF_CSC_COEFF0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK) #define LCDIF_CSC_COEFF0_C0_MASK (0x3FF0000U) #define LCDIF_CSC_COEFF0_C0_SHIFT (16U) #define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK) #define LCDIF_CSC_COEFF0_RSRVD1_MASK (0xFC000000U) #define LCDIF_CSC_COEFF0_RSRVD1_SHIFT (26U) #define LCDIF_CSC_COEFF0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK) /*! @} */ /*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */ /*! @{ */ #define LCDIF_CSC_COEFF1_C1_MASK (0x3FFU) #define LCDIF_CSC_COEFF1_C1_SHIFT (0U) #define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK) #define LCDIF_CSC_COEFF1_RSRVD0_MASK (0xFC00U) #define LCDIF_CSC_COEFF1_RSRVD0_SHIFT (10U) #define LCDIF_CSC_COEFF1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK) #define LCDIF_CSC_COEFF1_C2_MASK (0x3FF0000U) #define LCDIF_CSC_COEFF1_C2_SHIFT (16U) #define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK) #define LCDIF_CSC_COEFF1_RSRVD1_MASK (0xFC000000U) #define LCDIF_CSC_COEFF1_RSRVD1_SHIFT (26U) #define LCDIF_CSC_COEFF1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK) /*! @} */ /*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */ /*! @{ */ #define LCDIF_CSC_COEFF2_C3_MASK (0x3FFU) #define LCDIF_CSC_COEFF2_C3_SHIFT (0U) #define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK) #define LCDIF_CSC_COEFF2_RSRVD0_MASK (0xFC00U) #define LCDIF_CSC_COEFF2_RSRVD0_SHIFT (10U) #define LCDIF_CSC_COEFF2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK) #define LCDIF_CSC_COEFF2_C4_MASK (0x3FF0000U) #define LCDIF_CSC_COEFF2_C4_SHIFT (16U) #define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK) #define LCDIF_CSC_COEFF2_RSRVD1_MASK (0xFC000000U) #define LCDIF_CSC_COEFF2_RSRVD1_SHIFT (26U) #define LCDIF_CSC_COEFF2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK) /*! @} */ /*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */ /*! @{ */ #define LCDIF_CSC_COEFF3_C5_MASK (0x3FFU) #define LCDIF_CSC_COEFF3_C5_SHIFT (0U) #define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK) #define LCDIF_CSC_COEFF3_RSRVD0_MASK (0xFC00U) #define LCDIF_CSC_COEFF3_RSRVD0_SHIFT (10U) #define LCDIF_CSC_COEFF3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK) #define LCDIF_CSC_COEFF3_C6_MASK (0x3FF0000U) #define LCDIF_CSC_COEFF3_C6_SHIFT (16U) #define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK) #define LCDIF_CSC_COEFF3_RSRVD1_MASK (0xFC000000U) #define LCDIF_CSC_COEFF3_RSRVD1_SHIFT (26U) #define LCDIF_CSC_COEFF3_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK) /*! @} */ /*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */ /*! @{ */ #define LCDIF_CSC_COEFF4_C7_MASK (0x3FFU) #define LCDIF_CSC_COEFF4_C7_SHIFT (0U) #define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK) #define LCDIF_CSC_COEFF4_RSRVD0_MASK (0xFC00U) #define LCDIF_CSC_COEFF4_RSRVD0_SHIFT (10U) #define LCDIF_CSC_COEFF4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK) #define LCDIF_CSC_COEFF4_C8_MASK (0x3FF0000U) #define LCDIF_CSC_COEFF4_C8_SHIFT (16U) #define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK) #define LCDIF_CSC_COEFF4_RSRVD1_MASK (0xFC000000U) #define LCDIF_CSC_COEFF4_RSRVD1_SHIFT (26U) #define LCDIF_CSC_COEFF4_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK) /*! @} */ /*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */ /*! @{ */ #define LCDIF_CSC_OFFSET_Y_OFFSET_MASK (0x1FFU) #define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT (0U) #define LCDIF_CSC_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK) #define LCDIF_CSC_OFFSET_RSRVD0_MASK (0xFE00U) #define LCDIF_CSC_OFFSET_RSRVD0_SHIFT (9U) #define LCDIF_CSC_OFFSET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK) #define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK (0x1FF0000U) #define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT (16U) #define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK) #define LCDIF_CSC_OFFSET_RSRVD1_MASK (0xFE000000U) #define LCDIF_CSC_OFFSET_RSRVD1_SHIFT (25U) #define LCDIF_CSC_OFFSET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK) /*! @} */ /*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */ /*! @{ */ #define LCDIF_CSC_LIMIT_Y_MAX_MASK (0xFFU) #define LCDIF_CSC_LIMIT_Y_MAX_SHIFT (0U) #define LCDIF_CSC_LIMIT_Y_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK) #define LCDIF_CSC_LIMIT_Y_MIN_MASK (0xFF00U) #define LCDIF_CSC_LIMIT_Y_MIN_SHIFT (8U) #define LCDIF_CSC_LIMIT_Y_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK) #define LCDIF_CSC_LIMIT_CBCR_MAX_MASK (0xFF0000U) #define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT (16U) #define LCDIF_CSC_LIMIT_CBCR_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK) #define LCDIF_CSC_LIMIT_CBCR_MIN_MASK (0xFF000000U) #define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT (24U) #define LCDIF_CSC_LIMIT_CBCR_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK) /*! @} */ /*! @name DATA - LCD Interface Data Register */ /*! @{ */ #define LCDIF_DATA_DATA_ZERO_MASK (0xFFU) #define LCDIF_DATA_DATA_ZERO_SHIFT (0U) #define LCDIF_DATA_DATA_ZERO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK) #define LCDIF_DATA_DATA_ONE_MASK (0xFF00U) #define LCDIF_DATA_DATA_ONE_SHIFT (8U) #define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK) #define LCDIF_DATA_DATA_TWO_MASK (0xFF0000U) #define LCDIF_DATA_DATA_TWO_SHIFT (16U) #define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK) #define LCDIF_DATA_DATA_THREE_MASK (0xFF000000U) #define LCDIF_DATA_DATA_THREE_SHIFT (24U) #define LCDIF_DATA_DATA_THREE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK) /*! @} */ /*! @name BM_ERROR_STAT - Bus Master Error Status Register */ /*! @{ */ #define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) #define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) /*! @} */ /*! @name CRC_STAT - CRC Status Register */ /*! @{ */ #define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) #define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) /*! @} */ /*! @name STAT - LCD Interface Status Register */ /*! @{ */ #define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) #define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) #define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) #define LCDIF_STAT_RSRVD0_MASK (0xFFFE00U) #define LCDIF_STAT_RSRVD0_SHIFT (9U) #define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) #define LCDIF_STAT_DVI_CURRENT_FIELD_MASK (0x1000000U) #define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT (24U) #define LCDIF_STAT_DVI_CURRENT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK) #define LCDIF_STAT_BUSY_MASK (0x2000000U) #define LCDIF_STAT_BUSY_SHIFT (25U) #define LCDIF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK) #define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) #define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) #define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) #define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) #define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) #define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) #define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) #define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) #define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) #define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) #define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) #define LCDIF_STAT_PRESENT_MASK (0x80000000U) #define LCDIF_STAT_PRESENT_SHIFT (31U) #define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) /*! @} */ /*! @name THRES - LCDIF Threshold Register */ /*! @{ */ #define LCDIF_THRES_PANIC_MASK (0x1FFU) #define LCDIF_THRES_PANIC_SHIFT (0U) #define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) #define LCDIF_THRES_RSRVD1_MASK (0xFE00U) #define LCDIF_THRES_RSRVD1_SHIFT (9U) #define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) #define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) #define LCDIF_THRES_FASTCLOCK_SHIFT (16U) #define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) #define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) #define LCDIF_THRES_RSRVD2_SHIFT (25U) #define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) /*! @} */ /*! @name AS_CTRL - LCDIF AS Buffer Control Register */ /*! @{ */ #define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U) #define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U) #define LCDIF_AS_CTRL_AS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK) #define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U) #define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U) #define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK) #define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) #define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) #define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK) #define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U) #define LCDIF_AS_CTRL_FORMAT_SHIFT (4U) #define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK) #define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U) #define LCDIF_AS_CTRL_ALPHA_SHIFT (8U) #define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK) #define LCDIF_AS_CTRL_ROP_MASK (0xF0000U) #define LCDIF_AS_CTRL_ROP_SHIFT (16U) #define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK) #define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) #define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U) #define LCDIF_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK) #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U) #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U) #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) #define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U) #define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U) #define LCDIF_AS_CTRL_PS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK) #define LCDIF_AS_CTRL_RVDS1_MASK (0x7000000U) #define LCDIF_AS_CTRL_RVDS1_SHIFT (24U) #define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK (0x8000000U) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT (27U) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK (0x10000000U) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT (28U) #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK (0x20000000U) #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT (29U) #define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK) #define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK (0x40000000U) #define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT (30U) #define LCDIF_AS_CTRL_CSI_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK) #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK (0x80000000U) #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT (31U) #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK) /*! @} */ /*! @name AS_BUF - Alpha Surface Buffer Pointer */ /*! @{ */ #define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_AS_BUF_ADDR_SHIFT (0U) #define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK) /*! @} */ /*! @name AS_NEXT_BUF - */ /*! @{ */ #define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U) #define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK) /*! @} */ /*! @name AS_CLRKEYLOW - LCDIF Overlay Color Key Low */ /*! @{ */ #define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) #define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U) #define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK) #define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) #define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U) #define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK) /*! @} */ /*! @name AS_CLRKEYHIGH - LCDIF Overlay Color Key High */ /*! @{ */ #define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) #define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) #define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) #define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) #define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) #define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) /*! @} */ /*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */ /*! @{ */ #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU) #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U) #define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U) #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U) #define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) /*! @} */ /*! * @} */ /* end of group LCDIF_Register_Masks */ /* LCDIF - Peripheral instance base addresses */ /** Peripheral ADMA__LCDIF base address */ #define ADMA__LCDIF_BASE (0x5A180000u) /** Peripheral ADMA__LCDIF base pointer */ #define ADMA__LCDIF ((LCDIF_Type *)ADMA__LCDIF_BASE) /** Array initializer of LCDIF peripheral base addresses */ #define LCDIF_BASE_ADDRS { ADMA__LCDIF_BASE } /** Array initializer of LCDIF peripheral base pointers */ #define LCDIF_BASE_PTRS { ADMA__LCDIF } /*! * @} */ /* end of group LCDIF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LMEM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer * @{ */ /** LMEM - Register Layout Typedef */ typedef struct { __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */ __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */ __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */ __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */ uint8_t RESERVED_0[2032]; __IO uint32_t PSCCR; /**< Cache control register, offset: 0x800 */ __IO uint32_t PSCLCR; /**< Cache line control register, offset: 0x804 */ __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */ __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */ } LMEM_Type; /* ---------------------------------------------------------------------------- -- LMEM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LMEM_Register_Masks LMEM Register Masks * @{ */ /*! @name PCCCR - Cache control register */ /*! @{ */ #define LMEM_PCCCR_ENCACHE_MASK (0x1U) #define LMEM_PCCCR_ENCACHE_SHIFT (0U) /*! ENCACHE - Cache enable * 0b0..Cache disabled * 0b1..Cache enabled */ #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK) #define LMEM_PCCCR_ENWRBUF_MASK (0x2U) #define LMEM_PCCCR_ENWRBUF_SHIFT (1U) /*! ENWRBUF - Enable Write Buffer * 0b0..Write buffer disabled * 0b1..Write buffer enabled */ #define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK) #define LMEM_PCCCR_PCCR2_MASK (0x4U) #define LMEM_PCCCR_PCCR2_SHIFT (2U) /*! PCCR2 - Forces all cacheable spaces to write through */ #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK) #define LMEM_PCCCR_PCCR3_MASK (0x8U) #define LMEM_PCCCR_PCCR3_SHIFT (3U) /*! PCCR3 - Forces no allocation on cache misses (must also have PCCR2 asserted) */ #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK) #define LMEM_PCCCR_INVW0_MASK (0x1000000U) #define LMEM_PCCCR_INVW0_SHIFT (24U) /*! INVW0 - Invalidate Way 0 * 0b0..No operation * 0b1..When setting the GO bit, invalidate all lines in way 0. */ #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK) #define LMEM_PCCCR_PUSHW0_MASK (0x2000000U) #define LMEM_PCCCR_PUSHW0_SHIFT (25U) /*! PUSHW0 - Push Way 0 * 0b0..No operation * 0b1..When setting the GO bit, push all modified lines in way 0 */ #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK) #define LMEM_PCCCR_INVW1_MASK (0x4000000U) #define LMEM_PCCCR_INVW1_SHIFT (26U) /*! INVW1 - Invalidate Way 1 * 0b0..No operation * 0b1..When setting the GO bit, invalidate all lines in way 1 */ #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK) #define LMEM_PCCCR_PUSHW1_MASK (0x8000000U) #define LMEM_PCCCR_PUSHW1_SHIFT (27U) /*! PUSHW1 - Push Way 1 * 0b0..No operation * 0b1..When setting the GO bit, push all modified lines in way 1 */ #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK) #define LMEM_PCCCR_GO_MASK (0x80000000U) #define LMEM_PCCCR_GO_SHIFT (31U) /*! GO - Initiate Cache Command * 0b0..Write: no effect. Read: no cache command active. * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active. */ #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK) /*! @} */ /*! @name PCCLCR - Cache line control register */ /*! @{ */ #define LMEM_PCCLCR_LGO_MASK (0x1U) #define LMEM_PCCLCR_LGO_SHIFT (0U) /*! LGO - Initiate Cache Line Command * 0b0..Write: no effect. Read: no line command active. * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active. */ #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK) #define LMEM_PCCLCR_CACHEADDR_MASK (0x3FFCU) #define LMEM_PCCLCR_CACHEADDR_SHIFT (2U) /*! CACHEADDR - Cache address */ #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK) #define LMEM_PCCLCR_WSEL_MASK (0x4000U) #define LMEM_PCCLCR_WSEL_SHIFT (14U) /*! WSEL - Way select * 0b0..Way 0 * 0b1..Way 1 */ #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK) #define LMEM_PCCLCR_TDSEL_MASK (0x10000U) #define LMEM_PCCLCR_TDSEL_SHIFT (16U) /*! TDSEL - Tag/Data Select * 0b0..Data * 0b1..Tag */ #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK) #define LMEM_PCCLCR_LCIVB_MASK (0x100000U) #define LMEM_PCCLCR_LCIVB_SHIFT (20U) /*! LCIVB - Line Command Initial Valid Bit */ #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK) #define LMEM_PCCLCR_LCIMB_MASK (0x200000U) #define LMEM_PCCLCR_LCIMB_SHIFT (21U) /*! LCIMB - Line Command Initial Modified Bit */ #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK) #define LMEM_PCCLCR_LCWAY_MASK (0x400000U) #define LMEM_PCCLCR_LCWAY_SHIFT (22U) /*! LCWAY - Line Command Way */ #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK) #define LMEM_PCCLCR_LCMD_MASK (0x3000000U) #define LMEM_PCCLCR_LCMD_SHIFT (24U) /*! LCMD - Line Command * 0b00..Search and read or write * 0b01..Invalidate * 0b10..Push * 0b11..Clear */ #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK) #define LMEM_PCCLCR_LADSEL_MASK (0x4000000U) #define LMEM_PCCLCR_LADSEL_SHIFT (26U) /*! LADSEL - Line Address Select * 0b0..Cache address * 0b1..Physical address */ #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK) #define LMEM_PCCLCR_LACC_MASK (0x8000000U) #define LMEM_PCCLCR_LACC_SHIFT (27U) /*! LACC - Line access type * 0b0..Read * 0b1..Write */ #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK) /*! @} */ /*! @name PCCSAR - Cache search address register */ /*! @{ */ #define LMEM_PCCSAR_LGO_MASK (0x1U) #define LMEM_PCCSAR_LGO_SHIFT (0U) /*! LGO - Initiate Cache Line Command * 0b0..Write: no effect. Read: no line command active. * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. */ #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK) #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFEU) #define LMEM_PCCSAR_PHYADDR_SHIFT (1U) /*! PHYADDR - Physical Address */ #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK) /*! @} */ /*! @name PCCCVR - Cache read/write value register */ /*! @{ */ #define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU) #define LMEM_PCCCVR_DATA_SHIFT (0U) /*! DATA - Cache read/write Data */ #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK) /*! @} */ /*! @name PSCCR - Cache control register */ /*! @{ */ #define LMEM_PSCCR_ENCACHE_MASK (0x1U) #define LMEM_PSCCR_ENCACHE_SHIFT (0U) /*! ENCACHE - Cache enable * 0b0..Cache disabled * 0b1..Cache enabled */ #define LMEM_PSCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK) #define LMEM_PSCCR_ENWRBUF_MASK (0x2U) #define LMEM_PSCCR_ENWRBUF_SHIFT (1U) /*! ENWRBUF - Enable Write Buffer * 0b0..Write buffer disabled * 0b1..Write buffer enabled */ #define LMEM_PSCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK) #define LMEM_PSCCR_INVW0_MASK (0x1000000U) #define LMEM_PSCCR_INVW0_SHIFT (24U) /*! INVW0 - Invalidate Way 0 * 0b0..No operation * 0b1..When setting the GO bit, invalidate all lines in way 0. */ #define LMEM_PSCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK) #define LMEM_PSCCR_PUSHW0_MASK (0x2000000U) #define LMEM_PSCCR_PUSHW0_SHIFT (25U) /*! PUSHW0 - Push Way 0 * 0b0..No operation * 0b1..When setting the GO bit, push all modified lines in way 0 */ #define LMEM_PSCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK) #define LMEM_PSCCR_INVW1_MASK (0x4000000U) #define LMEM_PSCCR_INVW1_SHIFT (26U) /*! INVW1 - Invalidate Way 1 * 0b0..No operation * 0b1..When setting the GO bit, invalidate all lines in way 1 */ #define LMEM_PSCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK) #define LMEM_PSCCR_PUSHW1_MASK (0x8000000U) #define LMEM_PSCCR_PUSHW1_SHIFT (27U) /*! PUSHW1 - Push Way 1 * 0b0..No operation * 0b1..When setting the GO bit, push all modified lines in way 1 */ #define LMEM_PSCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK) #define LMEM_PSCCR_GO_MASK (0x80000000U) #define LMEM_PSCCR_GO_SHIFT (31U) /*! GO - Initiate Cache Command * 0b0..Write: no effect. Read: no cache command active. * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active. */ #define LMEM_PSCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK) /*! @} */ /*! @name PSCLCR - Cache line control register */ /*! @{ */ #define LMEM_PSCLCR_LGO_MASK (0x1U) #define LMEM_PSCLCR_LGO_SHIFT (0U) /*! LGO - Initiate Cache Line Command * 0b0..Write: no effect. Read: no line command active. * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active. */ #define LMEM_PSCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK) #define LMEM_PSCLCR_CACHEADDR_MASK (0x3FFCU) #define LMEM_PSCLCR_CACHEADDR_SHIFT (2U) /*! CACHEADDR - Cache address */ #define LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK) #define LMEM_PSCLCR_WSEL_MASK (0x4000U) #define LMEM_PSCLCR_WSEL_SHIFT (14U) /*! WSEL - Way select * 0b0..Way 0 * 0b1..Way 1 */ #define LMEM_PSCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK) #define LMEM_PSCLCR_TDSEL_MASK (0x10000U) #define LMEM_PSCLCR_TDSEL_SHIFT (16U) /*! TDSEL - Tag/Data Select * 0b0..Data * 0b1..Tag */ #define LMEM_PSCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK) #define LMEM_PSCLCR_LCIVB_MASK (0x100000U) #define LMEM_PSCLCR_LCIVB_SHIFT (20U) /*! LCIVB - Line Command Initial Valid Bit */ #define LMEM_PSCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK) #define LMEM_PSCLCR_LCIMB_MASK (0x200000U) #define LMEM_PSCLCR_LCIMB_SHIFT (21U) /*! LCIMB - Line Command Initial Modified Bit */ #define LMEM_PSCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK) #define LMEM_PSCLCR_LCWAY_MASK (0x400000U) #define LMEM_PSCLCR_LCWAY_SHIFT (22U) /*! LCWAY - Line Command Way */ #define LMEM_PSCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK) #define LMEM_PSCLCR_LCMD_MASK (0x3000000U) #define LMEM_PSCLCR_LCMD_SHIFT (24U) /*! LCMD - Line Command * 0b00..Search and read or write * 0b01..Invalidate * 0b10..Push * 0b11..Clear */ #define LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK) #define LMEM_PSCLCR_LADSEL_MASK (0x4000000U) #define LMEM_PSCLCR_LADSEL_SHIFT (26U) /*! LADSEL - Line Address Select * 0b0..Cache address * 0b1..Physical address */ #define LMEM_PSCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK) #define LMEM_PSCLCR_LACC_MASK (0x8000000U) #define LMEM_PSCLCR_LACC_SHIFT (27U) /*! LACC - Line access type * 0b0..Read * 0b1..Write */ #define LMEM_PSCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK) /*! @} */ /*! @name PSCSAR - Cache search address register */ /*! @{ */ #define LMEM_PSCSAR_LGO_MASK (0x1U) #define LMEM_PSCSAR_LGO_SHIFT (0U) /*! LGO - Initiate Cache Line Command * 0b0..Write: no effect. Read: no line command active. * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. */ #define LMEM_PSCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK) #define LMEM_PSCSAR_PHYADDR_MASK (0xFFFFFFFEU) #define LMEM_PSCSAR_PHYADDR_SHIFT (1U) /*! PHYADDR - Physical Address */ #define LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK) /*! @} */ /*! @name PSCCVR - Cache read/write value register */ /*! @{ */ #define LMEM_PSCCVR_DATA_MASK (0xFFFFFFFFU) #define LMEM_PSCCVR_DATA_SHIFT (0U) /*! DATA - Cache read/write Data */ #define LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group LMEM_Register_Masks */ /* LMEM - Peripheral instance base addresses */ /** Peripheral LMEM base address */ #define LMEM_BASE (0xE0082000u) /** Peripheral LMEM base pointer */ #define LMEM ((LMEM_Type *)LMEM_BASE) /** Array initializer of LMEM peripheral base addresses */ #define LMEM_BASE_ADDRS { LMEM_BASE } /** Array initializer of LMEM peripheral base pointers */ #define LMEM_BASE_PTRS { LMEM } /*! * @} */ /* end of group LMEM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPC_Peripheral_Access_Layer LPC Peripheral Access Layer * @{ */ /** LPC - Register Layout Typedef */ typedef struct { __IO uint32_t LPC_PC[7]; /**< LPC Power Control Register N, array offset: 0x0, array step: 0x4 */ __IO uint32_t LPC_CR; /**< LPC Configuration Register, offset: 0x1C */ __IO uint32_t LPC_ED[7]; /**< LPC Entry Delay Stage N, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t LPC_XD[6]; /**< LPC Exit Delay Stage N, array offset: 0x40, array step: 0x4 */ __IO uint32_t LPC_XD6; /**< LPC Exit Delay Stage 6, offset: 0x58 */ } LPC_Type; /* ---------------------------------------------------------------------------- -- LPC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPC_Register_Masks LPC Register Masks * @{ */ /*! @name LPC_PC - LPC Power Control Register N */ /*! @{ */ #define LPC_LPC_PC_PC_MASK (0xFFFFFFU) #define LPC_LPC_PC_PC_SHIFT (0U) /*! PC - Power Control bus */ #define LPC_LPC_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << LPC_LPC_PC_PC_SHIFT)) & LPC_LPC_PC_PC_MASK) /*! @} */ /* The count of LPC_LPC_PC */ #define LPC_LPC_PC_COUNT (7U) /*! @name LPC_CR - LPC Configuration Register */ /*! @{ */ #define LPC_LPC_CR_ROSCDIS_MASK (0x1U) #define LPC_LPC_CR_ROSCDIS_SHIFT (0U) /*! ROSCDIS - ROSC Disable * 0b0..ROSC enabled during low power mode. * 0b1..ROSC disabled during low power mode. */ #define LPC_LPC_CR_ROSCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_ROSCDIS_SHIFT)) & LPC_LPC_CR_ROSCDIS_MASK) #define LPC_LPC_CR_PMICSTDBY_MASK (0x2U) #define LPC_LPC_CR_PMICSTDBY_SHIFT (1U) /*! PMICSTDBY - PMIC Standby * 0b0..PMIC standby request deasserted during low power mode. * 0b1..PMIC standby request asserted during low power mode. */ #define LPC_LPC_CR_PMICSTDBY(x) (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_PMICSTDBY_SHIFT)) & LPC_LPC_CR_PMICSTDBY_MASK) #define LPC_LPC_CR_PCSEL_MASK (0x4U) #define LPC_LPC_CR_PCSEL_SHIFT (2U) /*! PCSEL - LPC/DSC Power Control Select * 0b0..Power controls driven by DSC. * 0b1..Power controls driven by LPC. */ #define LPC_LPC_CR_PCSEL(x) (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_PCSEL_SHIFT)) & LPC_LPC_CR_PCSEL_MASK) #define LPC_LPC_CR_CLKSEL_MASK (0x30U) #define LPC_LPC_CR_CLKSEL_SHIFT (4U) /*! CLKSEL - LPC Clock Select * 0b00..25MHz clock selected * 0b01..1MHz clock selected * 0b10..32kHz clock selected * 0b11..Reserved */ #define LPC_LPC_CR_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_CLKSEL_SHIFT)) & LPC_LPC_CR_CLKSEL_MASK) #define LPC_LPC_CR_CLKS_MASK (0x40U) #define LPC_LPC_CR_CLKS_SHIFT (6U) /*! CLKS - LPC Clock Status * 0b0..LPC Clock is not gated. * 0b1..LPC Clock is gated. */ #define LPC_LPC_CR_CLKS(x) (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_CLKS_SHIFT)) & LPC_LPC_CR_CLKS_MASK) #define LPC_LPC_CR_CLKG_MASK (0x80U) #define LPC_LPC_CR_CLKG_SHIFT (7U) /*! CLKG - LPC Clock Gate * 0b0..LPC Clock gate not requested. * 0b1..LPC Clock gate requested. */ #define LPC_LPC_CR_CLKG(x) (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_CLKG_SHIFT)) & LPC_LPC_CR_CLKG_MASK) /*! @} */ /*! @name LPC_ED - LPC Entry Delay Stage N */ /*! @{ */ #define LPC_LPC_ED_ED_MASK (0x1FU) #define LPC_LPC_ED_ED_SHIFT (0U) /*! ED - Entry Delay */ #define LPC_LPC_ED_ED(x) (((uint32_t)(((uint32_t)(x)) << LPC_LPC_ED_ED_SHIFT)) & LPC_LPC_ED_ED_MASK) /*! @} */ /* The count of LPC_LPC_ED */ #define LPC_LPC_ED_COUNT (7U) /*! @name LPC_XD - LPC Exit Delay Stage N */ /*! @{ */ #define LPC_LPC_XD_XD_MASK (0x1FU) #define LPC_LPC_XD_XD_SHIFT (0U) /*! XD - Exit Delay */ #define LPC_LPC_XD_XD(x) (((uint32_t)(((uint32_t)(x)) << LPC_LPC_XD_XD_SHIFT)) & LPC_LPC_XD_XD_MASK) /*! @} */ /* The count of LPC_LPC_XD */ #define LPC_LPC_XD_COUNT (6U) /*! @name LPC_XD6 - LPC Exit Delay Stage 6 */ /*! @{ */ #define LPC_LPC_XD6_XD_MASK (0xFFFFU) #define LPC_LPC_XD6_XD_SHIFT (0U) /*! XD - Exit Delay */ #define LPC_LPC_XD6_XD(x) (((uint32_t)(((uint32_t)(x)) << LPC_LPC_XD6_XD_SHIFT)) & LPC_LPC_XD6_XD_MASK) /*! @} */ /*! * @} */ /* end of group LPC_Register_Masks */ /* LPC - Peripheral instance base addresses */ /** Peripheral SCU__LPC base address */ #define SCU__LPC_BASE (0x32070000u) /** Peripheral SCU__LPC base pointer */ #define SCU__LPC ((LPC_Type *)SCU__LPC_BASE) /** Array initializer of LPC peripheral base addresses */ #define LPC_BASE_ADDRS { SCU__LPC_BASE } /** Array initializer of LPC peripheral base pointers */ #define LPC_BASE_PTRS { SCU__LPC } /*! * @} */ /* end of group LPC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_AVSD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_AVSD_Peripheral_Access_Layer LPCG_AVSD Peripheral Access Layer * @{ */ /** LPCG_AVSD - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_AVSD_0; /**< na, offset: 0x0 */ } LPCG_AVSD_Type; /* ---------------------------------------------------------------------------- -- LPCG_AVSD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_AVSD_Register_Masks LPCG_AVSD Register Masks * @{ */ /*! @name LPCG_AVSD_0 - na */ /*! @{ */ #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_0_MASK (0x1U) #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_0_SHIFT (0U) /*! LPCG_AVSD_0_reserved_0_0 - reserved */ #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_0_SHIFT)) & LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_0_MASK) #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_MASK (0x2U) #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_SHIFT (1U) /*! med_dec_mfd_avsd_clk_gated_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_SHIFT)) & LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_MASK) #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_2_2_MASK (0x4U) #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_2_2_SHIFT (2U) /*! LPCG_AVSD_0_reserved_2_2 - reserved */ #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_2_2_SHIFT)) & LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_2_2_MASK) #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_MASK (0x8U) #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_SHIFT (3U) /*! med_dec_mfd_avsd_clk_gated_STOP - show clock root status, 1 means clock stopped */ #define LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_SHIFT)) & LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_MASK) #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_4_31_SHIFT (4U) /*! LPCG_AVSD_0_reserved_4_31 - reserved */ #define LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_4_31_SHIFT)) & LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_AVSD_Register_Masks */ /* LPCG_AVSD - Peripheral instance base addresses */ /** Peripheral VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED base address */ #define VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED_BASE (0x2D0B0000u) /** Peripheral VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED base pointer */ #define VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED ((LPCG_AVSD_Type *)VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED_BASE) /** Array initializer of LPCG_AVSD peripheral base addresses */ #define LPCG_AVSD_BASE_ADDRS { VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED_BASE } /** Array initializer of LPCG_AVSD peripheral base pointers */ #define LPCG_AVSD_BASE_PTRS { VPU__LPCG__MED_DEC_MFD__AVSD_CLK_GATED } /*! * @} */ /* end of group LPCG_AVSD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_CI_PI_LPCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_CI_PI_LPCG_Peripheral_Access_Layer LPCG_CI_PI_LPCG Peripheral Access Layer * @{ */ /** LPCG_CI_PI_LPCG - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_CI_PI_LPCG_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_CI_PI_LPCG_4; /**< na, offset: 0x4 */ __IO uint32_t LPCG_CI_PI_LPCG_8; /**< na, offset: 0x8 */ __IO uint32_t LPCG_CI_PI_LPCG_12; /**< na, offset: 0xC */ __IO uint32_t LPCG_CI_PI_LPCG_16; /**< na, offset: 0x10 */ uint8_t RESERVED_0[4]; __IO uint32_t LPCG_CI_PI_LPCG_24; /**< na, offset: 0x18 */ __IO uint32_t LPCG_CI_PI_LPCG_28; /**< na, offset: 0x1C */ } LPCG_CI_PI_LPCG_Type; /* ---------------------------------------------------------------------------- -- LPCG_CI_PI_LPCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_CI_PI_LPCG_Register_Masks LPCG_CI_PI_LPCG Register Masks * @{ */ /*! @name LPCG_CI_PI_LPCG_0 - na */ /*! @{ */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_0_16_MASK (0x1FFFFU) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_0_16_SHIFT (0U) /*! LPCG_ci_pi_lpcg_0_reserved_0_16 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_0_16_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_0_16_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_SWEN_SHIFT (17U) /*! lis_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_18_18_MASK (0x40000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_18_18_SHIFT (18U) /*! LPCG_ci_pi_lpcg_0_reserved_18_18 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_18_18_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_18_18_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_STOP_MASK (0x80000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_STOP_SHIFT (19U) /*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_lis_ipg_clk_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_20_31_SHIFT (20U) /*! LPCG_ci_pi_lpcg_0_reserved_20_31 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_20_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_0_LPCG_ci_pi_lpcg_0_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_CI_PI_LPCG_4 - na */ /*! @{ */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_0_15_MASK (0xFFFFU) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_0_15_SHIFT (0U) /*! LPCG_ci_pi_lpcg_4_reserved_0_15 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_0_15_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_0_15_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_gatedclk_HWEN_MASK (0x10000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_gatedclk_HWEN_SHIFT (16U) /*! ci_pi_regs_ipg_gatedclk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_gatedclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_gatedclk_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_gatedclk_HWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN_MASK (0x20000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN_SHIFT (17U) /*! ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_SWEN_AND_ci_pi_regs_ipg_gatedclk_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_18_18_MASK (0x40000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_18_18_SHIFT (18U) /*! LPCG_ci_pi_lpcg_4_reserved_18_18 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_18_18_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_18_18_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP_MASK (0x80000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP_SHIFT (19U) /*! ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ci_pi_regs_ipg_clk_STOP_AND_ci_pi_regs_ipg_gatedclk_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_HWEN_MASK (0x100000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_HWEN_SHIFT (20U) /*! ipsync_ci_pi_regs_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_HWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_SWEN_MASK (0x200000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_SWEN_SHIFT (21U) /*! ipsync_ci_pi_regs_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_22_22_MASK (0x400000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_22_22_SHIFT (22U) /*! LPCG_ci_pi_lpcg_4_reserved_22_22 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_22_22_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_22_22_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_STOP_MASK (0x800000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_STOP_SHIFT (23U) /*! ipsync_ci_pi_regs_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_master_clk_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_24_24_MASK (0x1000000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_24_24_SHIFT (24U) /*! LPCG_ci_pi_lpcg_4_reserved_24_24 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_24_24_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_24_24_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_SWEN_MASK (0x2000000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_SWEN_SHIFT (25U) /*! ipsync_ci_pi_regs_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_26_26_MASK (0x4000000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_26_26_SHIFT (26U) /*! LPCG_ci_pi_lpcg_4_reserved_26_26 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_26_26_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_26_26_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_STOP_MASK (0x8000000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_STOP_SHIFT (27U) /*! ipsync_ci_pi_regs_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_ipsync_ci_pi_regs_ipg_slave_clk_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_28_31_MASK (0xF0000000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_28_31_SHIFT (28U) /*! LPCG_ci_pi_lpcg_4_reserved_28_31 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_28_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_4_LPCG_ci_pi_lpcg_4_reserved_28_31_MASK) /*! @} */ /*! @name LPCG_CI_PI_LPCG_8 - na */ /*! @{ */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_0_15_MASK (0xFFFFU) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_0_15_SHIFT (0U) /*! LPCG_ci_pi_lpcg_8_reserved_0_15 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_0_15_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_0_15_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_HWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_18_18_MASK (0x40000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_18_18_SHIFT (18U) /*! LPCG_ci_pi_lpcg_8_reserved_18_18 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_18_18_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_18_18_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT (19U) /*! gpio_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_gpio_ipg_clk_s_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_20_31_MASK (0xFFF00000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_20_31_SHIFT (20U) /*! LPCG_ci_pi_lpcg_8_reserved_20_31 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_20_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_8_LPCG_ci_pi_lpcg_8_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_CI_PI_LPCG_12 - na */ /*! @{ */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_0_0_MASK (0x1U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_0_0_SHIFT (0U) /*! LPCG_ci_pi_lpcg_12_reserved_0_0 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_0_0_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_0_0_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U) /*! pwm_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_2_2_MASK (0x4U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_2_2_SHIFT (2U) /*! LPCG_ci_pi_lpcg_12_reserved_2_2 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_2_2_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_2_2_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK (0x8U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT (3U) /*! pwm_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_4_4_MASK (0x10U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_4_4_SHIFT (4U) /*! LPCG_ci_pi_lpcg_12_reserved_4_4 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_4_4_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_4_4_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK (0x20U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT (5U) /*! ccm_ckil_sync_wrapper_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_6_6_MASK (0x40U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_6_6_SHIFT (6U) /*! LPCG_ci_pi_lpcg_12_reserved_6_6 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_6_6_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_6_6_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK (0x80U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT (7U) /*! ccm_ckil_sync_wrapper_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_8_15_MASK (0xFF00U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_8_15_SHIFT (8U) /*! LPCG_ci_pi_lpcg_12_reserved_8_15 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_8_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_8_15_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_8_15_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_18_18_MASK (0x40000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_18_18_SHIFT (18U) /*! LPCG_ci_pi_lpcg_12_reserved_18_18 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_18_18_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_18_18_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U) /*! pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK (0x100000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT (20U) /*! ipsync_pwm_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK (0x200000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT (21U) /*! ipsync_pwm_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_22_22_MASK (0x400000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_22_22_SHIFT (22U) /*! LPCG_ci_pi_lpcg_12_reserved_22_22 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_22_22_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_22_22_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK (0x800000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT (23U) /*! ipsync_pwm_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_24_24_MASK (0x1000000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_24_24_SHIFT (24U) /*! LPCG_ci_pi_lpcg_12_reserved_24_24 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_24_24_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_24_24_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK (0x2000000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT (25U) /*! ipsync_pwm_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_26_26_MASK (0x4000000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_26_26_SHIFT (26U) /*! LPCG_ci_pi_lpcg_12_reserved_26_26 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_26_26_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_26_26_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK (0x8000000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT (27U) /*! ipsync_pwm_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_28_31_MASK (0xF0000000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_28_31_SHIFT (28U) /*! LPCG_ci_pi_lpcg_12_reserved_28_31 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_28_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_12_LPCG_ci_pi_lpcg_12_reserved_28_31_MASK) /*! @} */ /*! @name LPCG_CI_PI_LPCG_16 - na */ /*! @{ */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK (0x1U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT (0U) /*! lpi2c0_lpi2c_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK (0x2U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT (1U) /*! lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_2_2_MASK (0x4U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_2_2_SHIFT (2U) /*! LPCG_ci_pi_lpcg_16_reserved_2_2 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_2_2_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_2_2_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK (0x8U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT (3U) /*! lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_4_15_MASK (0xFFF0U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_4_15_SHIFT (4U) /*! LPCG_ci_pi_lpcg_16_reserved_4_15 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_4_15_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_4_15_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT (16U) /*! lpi2c0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT (17U) /*! lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_18_18_MASK (0x40000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_18_18_SHIFT (18U) /*! LPCG_ci_pi_lpcg_16_reserved_18_18 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_18_18_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_18_18_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT (19U) /*! lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_20_31_MASK (0xFFF00000U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_20_31_SHIFT (20U) /*! LPCG_ci_pi_lpcg_16_reserved_20_31 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_20_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_16_LPCG_ci_pi_lpcg_16_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_CI_PI_LPCG_24 - na */ /*! @{ */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_0_0_MASK (0x1U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_0_0_SHIFT (0U) /*! LPCG_ci_pi_lpcg_24_reserved_0_0 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_0_0_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_0_0_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN_MASK (0x2U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN_SHIFT (1U) /*! csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_SWEN_AND_pixel_link_mst_clk_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_2_2_MASK (0x4U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_2_2_SHIFT (2U) /*! LPCG_ci_pi_lpcg_24_reserved_2_2 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_2_2_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_2_2_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP_MASK (0x8U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP_SHIFT (3U) /*! csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_csi_interface_clk_STOP_AND_pixel_link_mst_clk_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_4_31_SHIFT (4U) /*! LPCG_ci_pi_lpcg_24_reserved_4_31 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_4_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_24_LPCG_ci_pi_lpcg_24_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_CI_PI_LPCG_28 - na */ /*! @{ */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_0_0_MASK (0x1U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_0_0_SHIFT (0U) /*! LPCG_ci_pi_lpcg_28_reserved_0_0 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_0_0_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_0_0_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_SWEN_MASK (0x2U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_SWEN_SHIFT (1U) /*! MCLK_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_SWEN_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_SWEN_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_2_2_MASK (0x4U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_2_2_SHIFT (2U) /*! LPCG_ci_pi_lpcg_28_reserved_2_2 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_2_2_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_2_2_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_STOP_MASK (0x8U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_STOP_SHIFT (3U) /*! MCLK_STOP - show clock root status, 1 means clock stopped */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_STOP_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_MCLK_STOP_MASK) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_4_31_SHIFT (4U) /*! LPCG_ci_pi_lpcg_28_reserved_4_31 - reserved */ #define LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_4_31_SHIFT)) & LPCG_CI_PI_LPCG_LPCG_CI_PI_LPCG_28_LPCG_ci_pi_lpcg_28_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_CI_PI_LPCG_Register_Masks */ /* LPCG_CI_PI_LPCG - Peripheral instance base addresses */ /** Peripheral CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK base address */ #define CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK_BASE (0x58263000u) /** Peripheral CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK base pointer */ #define CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK ((LPCG_CI_PI_LPCG_Type *)CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK_BASE) /** Array initializer of LPCG_CI_PI_LPCG peripheral base addresses */ #define LPCG_CI_PI_LPCG_BASE_ADDRS { CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK_BASE } /** Array initializer of LPCG_CI_PI_LPCG peripheral base pointers */ #define LPCG_CI_PI_LPCG_BASE_PTRS { CI_PI__LPCG_HDP_I2C_LPI2C_DIV_CLK } /*! * @} */ /* end of group LPCG_CI_PI_LPCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_DI_MIPI_DSI_LVDS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_DI_MIPI_DSI_LVDS_Peripheral_Access_Layer LPCG_DI_MIPI_DSI_LVDS Peripheral Access Layer * @{ */ /** LPCG_DI_MIPI_DSI_LVDS - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_4; /**< na, offset: 0x4 */ __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_8; /**< na, offset: 0x8 */ __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_12; /**< na, offset: 0xC */ __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_16; /**< na, offset: 0x10 */ __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_20; /**< na, offset: 0x14 */ __IO uint32_t LPCG_DI_MIPI_DSI_LVDS_LPCG_24; /**< na, offset: 0x18 */ } LPCG_DI_MIPI_DSI_LVDS_Type; /* ---------------------------------------------------------------------------- -- LPCG_DI_MIPI_DSI_LVDS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_DI_MIPI_DSI_LVDS_Register_Masks LPCG_DI_MIPI_DSI_LVDS Register Masks * @{ */ /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_0 - na */ /*! @{ */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16_MASK (0x1FFFFU) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16_SHIFT (0U) /*! LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_0_16_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_SWEN_SHIFT (17U) /*! lis_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18_MASK (0x40000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18_SHIFT (18U) /*! LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_18_18_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_STOP_MASK (0x80000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_STOP_SHIFT (19U) /*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_lis_ipg_clk_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31_SHIFT (20U) /*! LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_0_LPCG_di_mipi_dsi_lvds_lpcg_0_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_4 - na */ /*! @{ */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16_MASK (0x1FFFFU) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16_SHIFT (0U) /*! LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_0_16_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_SWEN_SHIFT (17U) /*! di_mipi_dsi_lvds_regs_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18_MASK (0x40000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18_SHIFT (18U) /*! LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_18_18_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_STOP_MASK (0x80000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_STOP_SHIFT (19U) /*! di_mipi_dsi_lvds_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_di_mipi_dsi_lvds_regs_ipg_clk_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31_MASK (0xFFF00000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31_SHIFT (20U) /*! LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_4_LPCG_di_mipi_dsi_lvds_lpcg_4_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_8 - na */ /*! @{ */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15_MASK (0xFFFFU) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15_SHIFT (0U) /*! LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_0_15_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18_MASK (0x40000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18_SHIFT (18U) /*! LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_18_18_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT (19U) /*! gpio_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31_MASK (0xFFF00000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31_SHIFT (20U) /*! LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_8_LPCG_di_mipi_dsi_lvds_lpcg_8_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_12 - na */ /*! @{ */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0_MASK (0x1U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0_SHIFT (0U) /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_0_0_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U) /*! pwm_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2_MASK (0x4U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2_SHIFT (2U) /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_2_2_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK (0x8U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT (3U) /*! pwm_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4_MASK (0x10U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4_SHIFT (4U) /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_4_4_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK (0x20U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT (5U) /*! ccm_ckil_sync_wrapper_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6_MASK (0x40U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6_SHIFT (6U) /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_6_6_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK (0x80U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT (7U) /*! ccm_ckil_sync_wrapper_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15_MASK (0xFF00U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15_SHIFT (8U) /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_8_15_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18_MASK (0x40000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18_SHIFT (18U) /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_18_18_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U) /*! pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK (0x100000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT (20U) /*! ipsync_pwm_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK (0x200000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT (21U) /*! ipsync_pwm_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22_MASK (0x400000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22_SHIFT (22U) /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_22_22_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK (0x800000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT (23U) /*! ipsync_pwm_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24_MASK (0x1000000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24_SHIFT (24U) /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_24_24_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK (0x2000000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT (25U) /*! ipsync_pwm_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26_MASK (0x4000000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26_SHIFT (26U) /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_26_26_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK (0x8000000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT (27U) /*! ipsync_pwm_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31_MASK (0xF0000000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31_SHIFT (28U) /*! LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_12_LPCG_di_mipi_dsi_lvds_lpcg_12_reserved_28_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_16 - na */ /*! @{ */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK (0x1U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT (0U) /*! lpi2c0_lpi2c_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK (0x2U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT (1U) /*! lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2_MASK (0x4U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2_SHIFT (2U) /*! LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_2_2_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK (0x8U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT (3U) /*! lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15_MASK (0xFFF0U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15_SHIFT (4U) /*! LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_4_15_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT (16U) /*! lpi2c0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT (17U) /*! lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18_MASK (0x40000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18_SHIFT (18U) /*! LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_18_18_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT (19U) /*! lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31_MASK (0xFFF00000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31_SHIFT (20U) /*! LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_16_LPCG_di_mipi_dsi_lvds_lpcg_16_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_20 - na */ /*! @{ */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U) /*! lpi2c1_lpi2c_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U) /*! lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2_MASK (0x4U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2_SHIFT (2U) /*! LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_2_2_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U) /*! lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15_MASK (0xFFF0U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15_SHIFT (4U) /*! LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_4_15_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_SHIFT (16U) /*! lpi2c1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT (17U) /*! lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18_MASK (0x40000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18_SHIFT (18U) /*! LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_18_18_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT (19U) /*! lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31_MASK (0xFFF00000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31_SHIFT (20U) /*! LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_20_LPCG_di_mipi_dsi_lvds_lpcg_20_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_DI_MIPI_DSI_LVDS_LPCG_24 - na */ /*! @{ */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0_MASK (0x1U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0_SHIFT (0U) /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_0_0_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_SWEN_MASK (0x2U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_SWEN_SHIFT (1U) /*! mipi_dsi_ctrl_TxClkEsc_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2_MASK (0x4U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2_SHIFT (2U) /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_2_2_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_STOP_MASK (0x8U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_STOP_SHIFT (3U) /*! mipi_dsi_ctrl_TxClkEsc_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_TxClkEsc_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4_MASK (0x10U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4_SHIFT (4U) /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_4_4_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_SWEN_MASK (0x20U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_SWEN_SHIFT (5U) /*! mipi_dsi_ctrl_RxClkEsc_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6_MASK (0x40U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6_SHIFT (6U) /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_6_6_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_STOP_MASK (0x80U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_STOP_SHIFT (7U) /*! mipi_dsi_ctrl_RxClkEsc_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_RxClkEsc_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8_MASK (0x100U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8_SHIFT (8U) /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_8_8_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_SWEN_MASK (0x200U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_SWEN_SHIFT (9U) /*! mipi_clkref_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10_MASK (0x400U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10_SHIFT (10U) /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_10_10_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_STOP_MASK (0x800U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_STOP_SHIFT (11U) /*! mipi_clkref_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_clkref_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16_MASK (0x1F000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16_SHIFT (12U) /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_12_16_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_SWEN_MASK (0x20000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_SWEN_SHIFT (17U) /*! mipi_dsi_ctrl_pclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_SWEN_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_SWEN_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18_MASK (0x40000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18_SHIFT (18U) /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_18_18_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_STOP_MASK (0x80000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_STOP_SHIFT (19U) /*! mipi_dsi_ctrl_pclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_STOP_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_mipi_dsi_ctrl_pclk_STOP_MASK) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31_MASK (0xFFF00000U) #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31_SHIFT (20U) /*! LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31 - reserved */ #define LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31_SHIFT)) & LPCG_DI_MIPI_DSI_LVDS_LPCG_DI_MIPI_DSI_LVDS_LPCG_24_LPCG_di_mipi_dsi_lvds_lpcg_24_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_DI_MIPI_DSI_LVDS_Register_Masks */ /* LPCG_DI_MIPI_DSI_LVDS - Peripheral instance base addresses */ /** Peripheral DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK base address */ #define DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK_BASE (0x56223000u) /** Peripheral DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK base pointer */ #define DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK ((LPCG_DI_MIPI_DSI_LVDS_Type *)DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK_BASE) /** Peripheral DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK base address */ #define DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK_BASE (0x56243000u) /** Peripheral DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK base pointer */ #define DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK ((LPCG_DI_MIPI_DSI_LVDS_Type *)DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK_BASE) /** Array initializer of LPCG_DI_MIPI_DSI_LVDS peripheral base addresses */ #define LPCG_DI_MIPI_DSI_LVDS_BASE_ADDRS { DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK_BASE, DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK_BASE } /** Array initializer of LPCG_DI_MIPI_DSI_LVDS peripheral base pointers */ #define LPCG_DI_MIPI_DSI_LVDS_BASE_PTRS { DI_MIPI_DSI_LVDS_0__LPCG_LIS_IPG_CLK, DI_MIPI_DSI_LVDS_1__LPCG_LIS_IPG_CLK } /*! * @} */ /* end of group LPCG_DI_MIPI_DSI_LVDS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_ENC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_ENC_Peripheral_Access_Layer LPCG_ENC Peripheral Access Layer * @{ */ /** LPCG_ENC - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_ENC_0; /**< na, offset: 0x0 */ } LPCG_ENC_Type; /* ---------------------------------------------------------------------------- -- LPCG_ENC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_ENC_Register_Masks LPCG_ENC Register Masks * @{ */ /*! @name LPCG_ENC_0 - na */ /*! @{ */ #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_0_0_MASK (0x1U) #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_0_0_SHIFT (0U) /*! LPCG_ENC_0_reserved_0_0 - reserved */ #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_0_0_SHIFT)) & LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_0_0_MASK) #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_SWEN_MASK (0x2U) #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_SWEN_SHIFT (1U) /*! avehd_xbus_top_wrapper_sys_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_SWEN_SHIFT)) & LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_SWEN_MASK) #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_2_2_MASK (0x4U) #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_2_2_SHIFT (2U) /*! LPCG_ENC_0_reserved_2_2 - reserved */ #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_2_2_SHIFT)) & LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_2_2_MASK) #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_STOP_MASK (0x8U) #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_STOP_SHIFT (3U) /*! avehd_xbus_top_wrapper_sys_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_STOP_SHIFT)) & LPCG_ENC_LPCG_ENC_0_avehd_xbus_top_wrapper_sys_clk_STOP_MASK) #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_4_31_SHIFT (4U) /*! LPCG_ENC_0_reserved_4_31 - reserved */ #define LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_4_31_SHIFT)) & LPCG_ENC_LPCG_ENC_0_LPCG_ENC_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_ENC_Register_Masks */ /* LPCG_ENC - Peripheral instance base addresses */ /** Peripheral VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK base address */ #define VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK_BASE (0x2D060000u) /** Peripheral VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK base pointer */ #define VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK ((LPCG_ENC_Type *)VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK_BASE) /** Array initializer of LPCG_ENC peripheral base addresses */ #define LPCG_ENC_BASE_ADDRS { VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK_BASE } /** Array initializer of LPCG_ENC peripheral base pointers */ #define LPCG_ENC_BASE_PTRS { VPU__LPCG_AVEHD_XBUS_TOP_WRAPPER_SYS_CLK } /*! * @} */ /* end of group LPCG_ENC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_GPIO_CLK Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_GPIO_CLK_Peripheral_Access_Layer LPCG_GPIO_CLK Peripheral Access Layer * @{ */ /** LPCG_GPIO_CLK - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_GPIO_CLK_0; /**< na, offset: 0x0 */ } LPCG_GPIO_CLK_Type; /* ---------------------------------------------------------------------------- -- LPCG_GPIO_CLK Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_GPIO_CLK_Register_Masks LPCG_GPIO_CLK Register Masks * @{ */ /*! @name LPCG_GPIO_CLK_0 - na */ /*! @{ */ #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_MASK (0xFFFFU) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_SHIFT (0U) /*! LPCG_GPIO_CLK_0_reserved_0_15 - reserved */ #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_MASK) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_MASK) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_MASK) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_MASK (0x40000U) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_SHIFT (18U) /*! LPCG_GPIO_CLK_0_reserved_18_18 - reserved */ #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_MASK) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_SHIFT (19U) /*! gpio_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_MASK) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_SHIFT (20U) /*! LPCG_GPIO_CLK_0_reserved_20_31 - reserved */ #define LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_SHIFT)) & LPCG_GPIO_CLK_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_GPIO_CLK_Register_Masks */ /* LPCG_GPIO_CLK - Peripheral instance base addresses */ /** Peripheral HSIO__LPCG_GPIO_IPG_CLK_S base address */ #define HSIO__LPCG_GPIO_IPG_CLK_S_BASE (0x5F100000u) /** Peripheral HSIO__LPCG_GPIO_IPG_CLK_S base pointer */ #define HSIO__LPCG_GPIO_IPG_CLK_S ((LPCG_GPIO_CLK_Type *)HSIO__LPCG_GPIO_IPG_CLK_S_BASE) /** Array initializer of LPCG_GPIO_CLK peripheral base addresses */ #define LPCG_GPIO_CLK_BASE_ADDRS { HSIO__LPCG_GPIO_IPG_CLK_S_BASE } /** Array initializer of LPCG_GPIO_CLK peripheral base pointers */ #define LPCG_GPIO_CLK_BASE_PTRS { HSIO__LPCG_GPIO_IPG_CLK_S } /*! * @} */ /* end of group LPCG_GPIO_CLK_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_H264 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_H264_Peripheral_Access_Layer LPCG_H264 Peripheral Access Layer * @{ */ /** LPCG_H264 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_H264_0; /**< na, offset: 0x0 */ } LPCG_H264_Type; /* ---------------------------------------------------------------------------- -- LPCG_H264 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_H264_Register_Masks LPCG_H264 Register Masks * @{ */ /*! @name LPCG_H264_0 - na */ /*! @{ */ #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_0_MASK (0x1U) #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_0_SHIFT (0U) /*! LPCG_H264_0_reserved_0_0 - reserved */ #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_0_SHIFT)) & LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_0_MASK) #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_MASK (0x2U) #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_SHIFT (1U) /*! med_dec_mfd_h264_clk_gated_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_SHIFT)) & LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_MASK) #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_2_2_MASK (0x4U) #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_2_2_SHIFT (2U) /*! LPCG_H264_0_reserved_2_2 - reserved */ #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_2_2_SHIFT)) & LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_2_2_MASK) #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_MASK (0x8U) #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_SHIFT (3U) /*! med_dec_mfd_h264_clk_gated_STOP - show clock root status, 1 means clock stopped */ #define LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_SHIFT)) & LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_MASK) #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_4_31_SHIFT (4U) /*! LPCG_H264_0_reserved_4_31 - reserved */ #define LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_4_31_SHIFT)) & LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_H264_Register_Masks */ /* LPCG_H264 - Peripheral instance base addresses */ /** Peripheral VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED base address */ #define VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED_BASE (0x2D080000u) /** Peripheral VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED base pointer */ #define VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED ((LPCG_H264_Type *)VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED_BASE) /** Array initializer of LPCG_H264 peripheral base addresses */ #define LPCG_H264_BASE_ADDRS { VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED_BASE } /** Array initializer of LPCG_H264 peripheral base pointers */ #define LPCG_H264_BASE_PTRS { VPU__LPCG_MED_DEC_MFD_H264_CLK_GATED } /*! * @} */ /* end of group LPCG_H264_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_0_Peripheral_Access_Layer LPCG_LPCG_0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_0_Register_Masks LPCG_LPCG_0 Register Masks * @{ */ /*! @name LPCG_LPCG_0_0 - na */ /*! @{ */ #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_0_0_reserved_0_0 - reserved */ #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_MASK) #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_SHIFT (1U) /*! ssi_port0_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_SHIFT)) & LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_MASK) #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_MASK) #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_MASK (0x8U) #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_SHIFT (3U) /*! ssi_port0_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_SHIFT)) & LPCG_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_MASK) #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_0_0_reserved_4_31 - reserved */ #define LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_SHIFT)) & LPCG_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_0_Register_Masks */ /* LPCG_LPCG_0 - Peripheral instance base addresses */ /** Peripheral DRC__LPCG_SSI_PORT0_CLK base address */ #define DRC__LPCG_SSI_PORT0_CLK_BASE (0xB80C0000u) /** Peripheral DRC__LPCG_SSI_PORT0_CLK base pointer */ #define DRC__LPCG_SSI_PORT0_CLK ((LPCG_LPCG_0_Type *)DRC__LPCG_SSI_PORT0_CLK_BASE) /** Array initializer of LPCG_LPCG_0 peripheral base addresses */ #define LPCG_LPCG_0_BASE_ADDRS { DRC__LPCG_SSI_PORT0_CLK_BASE } /** Array initializer of LPCG_LPCG_0 peripheral base pointers */ #define LPCG_LPCG_0_BASE_PTRS { DRC__LPCG_SSI_PORT0_CLK } /*! * @} */ /* end of group LPCG_LPCG_0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_1_Peripheral_Access_Layer LPCG_LPCG_1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_1_Register_Masks LPCG_LPCG_1 Register Masks * @{ */ /*! @name LPCG_LPCG_1_0 - na */ /*! @{ */ #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_1_0_reserved_0_0 - reserved */ #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_MASK) #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_SHIFT (1U) /*! ddr_ctl_core_ddrc_core_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_SHIFT)) & LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_MASK) #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_MASK) #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_MASK (0x8U) #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_SHIFT (3U) /*! ddr_ctl_core_ddrc_core_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_SHIFT)) & LPCG_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_MASK) #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_1_0_reserved_4_31 - reserved */ #define LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_SHIFT)) & LPCG_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_1_Register_Masks */ /* LPCG_LPCG_1 - Peripheral instance base addresses */ /** Peripheral DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base address */ #define DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE (0xB80D0000u) /** Peripheral DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base pointer */ #define DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK ((LPCG_LPCG_1_Type *)DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE) /** Array initializer of LPCG_LPCG_1 peripheral base addresses */ #define LPCG_LPCG_1_BASE_ADDRS { DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE } /** Array initializer of LPCG_LPCG_1 peripheral base pointers */ #define LPCG_LPCG_1_BASE_PTRS { DRC__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK } /*! * @} */ /* end of group LPCG_LPCG_1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_3_Peripheral_Access_Layer LPCG_LPCG_3 Peripheral Access Layer * @{ */ /** LPCG_LPCG_3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_3_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_LPCG_3_4; /**< na, offset: 0x4 */ } LPCG_LPCG_3_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_3_Register_Masks LPCG_LPCG_3 Register Masks * @{ */ /*! @name LPCG_LPCG_3_0 - na */ /*! @{ */ #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_3_0_reserved_0_0 - reserved */ #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_MASK) #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_MASK (0x2U) #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT (1U) /*! ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_MASK) #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_3_0_reserved_2_2 - reserved */ #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_MASK) #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_MASK (0x8U) #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT (3U) /*! ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_MASK) #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_3_0_reserved_4_31 - reserved */ #define LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_LPCG_3_4 - na */ /*! @{ */ #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_3_4_reserved_0_0 - reserved */ #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_MASK) #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_MASK (0x2U) #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT (1U) /*! ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_MASK) #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_3_4_reserved_2_2 - reserved */ #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_MASK) #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_MASK (0x8U) #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT (3U) /*! ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_MASK) #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_3_4_reserved_4_31 - reserved */ #define LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_SHIFT)) & LPCG_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_3_Register_Masks */ /* LPCG_LPCG_3 - Peripheral instance base addresses */ /** Peripheral DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base address */ #define DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE (0xB80F0000u) /** Peripheral DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base pointer */ #define DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 ((LPCG_LPCG_3_Type *)DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE) /** Array initializer of LPCG_LPCG_3 peripheral base addresses */ #define LPCG_LPCG_3_BASE_ADDRS { DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE } /** Array initializer of LPCG_LPCG_3 peripheral base pointers */ #define LPCG_LPCG_3_BASE_PTRS { DRC__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 } /*! * @} */ /* end of group LPCG_LPCG_3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_4_Peripheral_Access_Layer LPCG_LPCG_4 Peripheral Access Layer * @{ */ /** LPCG_LPCG_4 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_4_0; /**< na, offset: 0x0 */ } LPCG_LPCG_4_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_4_Register_Masks LPCG_LPCG_4 Register Masks * @{ */ /*! @name LPCG_LPCG_4_0 - na */ /*! @{ */ #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_4_0_reserved_0_0 - reserved */ #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_0_0_SHIFT)) & LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_0_0_MASK) #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_SWEN_SHIFT (1U) /*! ddr_ctl_sbr_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_SWEN_SHIFT)) & LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_SWEN_MASK) #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_4_0_reserved_2_2 - reserved */ #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_2_2_SHIFT)) & LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_2_2_MASK) #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_STOP_MASK (0x8U) #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_STOP_SHIFT (3U) /*! ddr_ctl_sbr_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_STOP_SHIFT)) & LPCG_LPCG_4_LPCG_LPCG_4_0_ddr_ctl_sbr_clk_STOP_MASK) #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_4_0_reserved_4_31 - reserved */ #define LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_4_31_SHIFT)) & LPCG_LPCG_4_LPCG_LPCG_4_0_LPCG_lpcg_4_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_4_Register_Masks */ /* LPCG_LPCG_4 - Peripheral instance base addresses */ /** Peripheral DRC__LPCG_DDR_CTL_SBR_CLK base address */ #define DRC__LPCG_DDR_CTL_SBR_CLK_BASE (0xB80B0000u) /** Peripheral DRC__LPCG_DDR_CTL_SBR_CLK base pointer */ #define DRC__LPCG_DDR_CTL_SBR_CLK ((LPCG_LPCG_4_Type *)DRC__LPCG_DDR_CTL_SBR_CLK_BASE) /** Array initializer of LPCG_LPCG_4 peripheral base addresses */ #define LPCG_LPCG_4_BASE_ADDRS { DRC__LPCG_DDR_CTL_SBR_CLK_BASE } /** Array initializer of LPCG_LPCG_4 peripheral base pointers */ #define LPCG_LPCG_4_BASE_PTRS { DRC__LPCG_DDR_CTL_SBR_CLK } /*! * @} */ /* end of group LPCG_LPCG_4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_5_Peripheral_Access_Layer LPCG_LPCG_5 Peripheral Access Layer * @{ */ /** LPCG_LPCG_5 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_5_0; /**< na, offset: 0x0 */ } LPCG_LPCG_5_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_5_Register_Masks LPCG_LPCG_5 Register Masks * @{ */ /*! @name LPCG_LPCG_5_0 - na */ /*! @{ */ #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_5_0_reserved_0_0 - reserved */ #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_0_0_SHIFT)) & LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_0_0_MASK) #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN_MASK (0x2U) #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN_SHIFT (1U) /*! ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN_SHIFT)) & LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_SWEN_MASK) #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_5_0_reserved_2_2 - reserved */ #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_2_2_SHIFT)) & LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_2_2_MASK) #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP_MASK (0x8U) #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP_SHIFT (3U) /*! ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP_SHIFT)) & LPCG_LPCG_5_LPCG_LPCG_5_0_ddr_phy_phy_ctl_ref_lpddr_init_clk_cg_CP_STOP_MASK) #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_5_0_reserved_4_31 - reserved */ #define LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_4_31_SHIFT)) & LPCG_LPCG_5_LPCG_LPCG_5_0_LPCG_lpcg_5_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_5_Register_Masks */ /* LPCG_LPCG_5 - Peripheral instance base addresses */ /** Peripheral DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP base address */ #define DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP_BASE (0xB80A0000u) /** Peripheral DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP base pointer */ #define DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP ((LPCG_LPCG_5_Type *)DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP_BASE) /** Array initializer of LPCG_LPCG_5 peripheral base addresses */ #define LPCG_LPCG_5_BASE_ADDRS { DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP_BASE } /** Array initializer of LPCG_LPCG_5 peripheral base pointers */ #define LPCG_LPCG_5_BASE_PTRS { DRC__LPCG_DDR_PHY_PHY_CTL_REF_LPDDR_INIT_CLK_CG_CP } /*! * @} */ /* end of group LPCG_LPCG_5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_6 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_6_Peripheral_Access_Layer LPCG_LPCG_6 Peripheral Access Layer * @{ */ /** LPCG_LPCG_6 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_6_0; /**< na, offset: 0x0 */ } LPCG_LPCG_6_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_6 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_6_Register_Masks LPCG_LPCG_6 Register Masks * @{ */ /*! @name LPCG_LPCG_6_0 - na */ /*! @{ */ #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_6_0_reserved_0_0 - reserved */ #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_0_0_SHIFT)) & LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_0_0_MASK) #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_SWEN_MASK (0x2U) #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_SWEN_SHIFT (1U) /*! atpg_phy_pub_clk_clk_mux_D0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_SWEN_SHIFT)) & LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_SWEN_MASK) #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_6_0_reserved_2_2 - reserved */ #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_2_2_SHIFT)) & LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_2_2_MASK) #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_STOP_MASK (0x8U) #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_STOP_SHIFT (3U) /*! atpg_phy_pub_clk_clk_mux_D0_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_STOP_SHIFT)) & LPCG_LPCG_6_LPCG_LPCG_6_0_atpg_phy_pub_clk_clk_mux_D0_STOP_MASK) #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_6_0_reserved_4_31 - reserved */ #define LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_4_31_SHIFT)) & LPCG_LPCG_6_LPCG_LPCG_6_0_LPCG_lpcg_6_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_6_Register_Masks */ /* LPCG_LPCG_6 - Peripheral instance base addresses */ /** Peripheral DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0 base address */ #define DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0_BASE (0xB8090000u) /** Peripheral DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0 base pointer */ #define DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0 ((LPCG_LPCG_6_Type *)DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0_BASE) /** Array initializer of LPCG_LPCG_6 peripheral base addresses */ #define LPCG_LPCG_6_BASE_ADDRS { DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0_BASE } /** Array initializer of LPCG_LPCG_6 peripheral base pointers */ #define LPCG_LPCG_6_BASE_PTRS { DRC__LPCG_ATPG_PHY_PUB_CLK_CLK_MUX_D0 } /*! * @} */ /* end of group LPCG_LPCG_6_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_ACM_REGS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_ACM_REGS_Peripheral_Access_Layer LPCG_LPCG_ACM_REGS Peripheral Access Layer * @{ */ /** LPCG_LPCG_ACM_REGS - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ACM_REGS_0; /**< na, offset: 0x0 */ } LPCG_LPCG_ACM_REGS_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_ACM_REGS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_ACM_REGS_Register_Masks LPCG_LPCG_ACM_REGS Register Masks * @{ */ /*! @name LPCG_LPCG_ACM_REGS_0 - na */ /*! @{ */ #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_0_15_MASK (0xFFFFU) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_0_15_SHIFT (0U) /*! LPCG_lpcg_acm_regs_0_reserved_0_15 - reserved */ #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_0_15_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_0_15_MASK) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_MASK (0x10000U) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_SHIFT (16U) /*! acm_regs_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_MASK) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_SHIFT (17U) /*! acm_regs_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_MASK) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_acm_regs_0_reserved_18_18 - reserved */ #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_18_18_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_18_18_MASK) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_SHIFT (19U) /*! acm_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_MASK) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_acm_regs_0_reserved_20_31 - reserved */ #define LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_20_31_SHIFT)) & LPCG_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_ACM_REGS_Register_Masks */ /* LPCG_LPCG_ACM_REGS - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_ACM_REGS_IPG_CLK base address */ #define ADMA__LPCG_ACM_REGS_IPG_CLK_BASE (0x59C60000u) /** Peripheral ADMA__LPCG_ACM_REGS_IPG_CLK base pointer */ #define ADMA__LPCG_ACM_REGS_IPG_CLK ((LPCG_LPCG_ACM_REGS_Type *)ADMA__LPCG_ACM_REGS_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_ACM_REGS peripheral base addresses */ #define LPCG_LPCG_ACM_REGS_BASE_ADDRS { ADMA__LPCG_ACM_REGS_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_ACM_REGS peripheral base pointers */ #define LPCG_LPCG_ACM_REGS_BASE_PTRS { ADMA__LPCG_ACM_REGS_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_ACM_REGS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_ADC0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_ADC0_Peripheral_Access_Layer LPCG_LPCG_ADC0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_ADC0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ADC0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_ADC0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_ADC0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_ADC0_Register_Masks LPCG_LPCG_ADC0 Register Masks * @{ */ /*! @name LPCG_LPCG_ADC0_0 - na */ /*! @{ */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_adc0_0_reserved_0_0 - reserved */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_0_0_MASK) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_SWEN_MASK (0x2U) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_SWEN_SHIFT (1U) /*! anamix_adc_clk_adc0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_SWEN_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_SWEN_MASK) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_adc0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_2_2_MASK) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_STOP_MASK (0x8U) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_STOP_SHIFT (3U) /*! anamix_adc_clk_adc0_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_STOP_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_adc_clk_adc0_STOP_MASK) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_adc0_0_reserved_4_15 - reserved */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_4_15_MASK) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_MASK (0x10000U) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_SHIFT (16U) /*! anamix_ipg_clk_s_adc0_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_s_adc0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_MASK) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_MASK (0x20000U) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_SHIFT (17U) /*! anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_MASK) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_adc0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_18_18_MASK) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_MASK (0x80000U) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_SHIFT (19U) /*! anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_MASK) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_adc0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_ADC0_LPCG_LPCG_ADC0_0_LPCG_lpcg_adc0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_ADC0_Register_Masks */ /* LPCG_LPCG_ADC0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_ANAMIX_IPG_CLK_ADC0 base address */ #define ADMA__LPCG_ANAMIX_IPG_CLK_ADC0_BASE (0x5AC80000u) /** Peripheral ADMA__LPCG_ANAMIX_IPG_CLK_ADC0 base pointer */ #define ADMA__LPCG_ANAMIX_IPG_CLK_ADC0 ((LPCG_LPCG_ADC0_Type *)ADMA__LPCG_ANAMIX_IPG_CLK_ADC0_BASE) /** Array initializer of LPCG_LPCG_ADC0 peripheral base addresses */ #define LPCG_LPCG_ADC0_BASE_ADDRS { ADMA__LPCG_ANAMIX_IPG_CLK_ADC0_BASE } /** Array initializer of LPCG_LPCG_ADC0 peripheral base pointers */ #define LPCG_LPCG_ADC0_BASE_PTRS { ADMA__LPCG_ANAMIX_IPG_CLK_ADC0 } /*! * @} */ /* end of group LPCG_LPCG_ADC0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_AMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_AMIX_Peripheral_Access_Layer LPCG_LPCG_AMIX Peripheral Access Layer * @{ */ /** LPCG_LPCG_AMIX - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_AMIX_0; /**< na, offset: 0x0 */ } LPCG_LPCG_AMIX_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_AMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_AMIX_Register_Masks LPCG_LPCG_AMIX Register Masks * @{ */ /*! @name LPCG_LPCG_AMIX_0 - na */ /*! @{ */ #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_amix_0_reserved_0_0 - reserved */ #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_SHIFT)) & LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_MASK) #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_SHIFT (1U) /*! amix_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_MASK) #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_amix_0_reserved_2_2 - reserved */ #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_SHIFT)) & LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_MASK) #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_MASK (0x8U) #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_SHIFT (3U) /*! amix_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_MASK) #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_amix_0_reserved_4_31 - reserved */ #define LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_SHIFT)) & LPCG_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_AMIX_Register_Masks */ /* LPCG_LPCG_AMIX - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_AMIX_IPG_CLK base address */ #define ADMA__LPCG_AMIX_IPG_CLK_BASE (0x59C40000u) /** Peripheral ADMA__LPCG_AMIX_IPG_CLK base pointer */ #define ADMA__LPCG_AMIX_IPG_CLK ((LPCG_LPCG_AMIX_Type *)ADMA__LPCG_AMIX_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_AMIX peripheral base addresses */ #define LPCG_LPCG_AMIX_BASE_ADDRS { ADMA__LPCG_AMIX_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_AMIX peripheral base pointers */ #define LPCG_LPCG_AMIX_BASE_PTRS { ADMA__LPCG_AMIX_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_AMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_ASRC0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_ASRC0_Peripheral_Access_Layer LPCG_LPCG_ASRC0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_ASRC0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ASRC0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_ASRC0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_ASRC0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_ASRC0_Register_Masks LPCG_LPCG_ASRC0 Register Masks * @{ */ /*! @name LPCG_LPCG_ASRC0_0 - na */ /*! @{ */ #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_16_MASK (0x1FFFFU) #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_16_SHIFT (0U) /*! LPCG_lpcg_asrc0_0_reserved_0_16 - reserved */ #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_16_SHIFT)) & LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_16_MASK) #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_SHIFT (17U) /*! asrc0_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_MASK) #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_asrc0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_18_18_MASK) #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_SHIFT (19U) /*! asrc0_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_MASK) #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_asrc0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_ASRC0_Register_Masks */ /* LPCG_LPCG_ASRC0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_ASRC0_IPG_CLK base address */ #define ADMA__LPCG_ASRC0_IPG_CLK_BASE (0x59400000u) /** Peripheral ADMA__LPCG_ASRC0_IPG_CLK base pointer */ #define ADMA__LPCG_ASRC0_IPG_CLK ((LPCG_LPCG_ASRC0_Type *)ADMA__LPCG_ASRC0_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_ASRC0 peripheral base addresses */ #define LPCG_LPCG_ASRC0_BASE_ADDRS { ADMA__LPCG_ASRC0_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_ASRC0 peripheral base pointers */ #define LPCG_LPCG_ASRC0_BASE_PTRS { ADMA__LPCG_ASRC0_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_ASRC0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_ASRC1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_ASRC1_Peripheral_Access_Layer LPCG_LPCG_ASRC1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_ASRC1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ASRC1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_ASRC1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_ASRC1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_ASRC1_Register_Masks LPCG_LPCG_ASRC1 Register Masks * @{ */ /*! @name LPCG_LPCG_ASRC1_0 - na */ /*! @{ */ #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_16_MASK (0x1FFFFU) #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_16_SHIFT (0U) /*! LPCG_lpcg_asrc1_0_reserved_0_16 - reserved */ #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_16_SHIFT)) & LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_16_MASK) #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_SHIFT (17U) /*! asrc1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_MASK) #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_asrc1_0_reserved_18_18 - reserved */ #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_18_18_MASK) #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_SHIFT (19U) /*! asrc1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_MASK) #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_asrc1_0_reserved_20_31 - reserved */ #define LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_ASRC1_Register_Masks */ /* LPCG_LPCG_ASRC1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_ASRC1_IPG_CLK base address */ #define ADMA__LPCG_ASRC1_IPG_CLK_BASE (0x59C00000u) /** Peripheral ADMA__LPCG_ASRC1_IPG_CLK base pointer */ #define ADMA__LPCG_ASRC1_IPG_CLK ((LPCG_LPCG_ASRC1_Type *)ADMA__LPCG_ASRC1_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_ASRC1 peripheral base addresses */ #define LPCG_LPCG_ASRC1_BASE_ADDRS { ADMA__LPCG_ASRC1_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_ASRC1 peripheral base pointers */ #define LPCG_LPCG_ASRC1_BASE_PTRS { ADMA__LPCG_ASRC1_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_ASRC1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_AUD_PLL_DIV_CLK0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_AUD_PLL_DIV_CLK0_Peripheral_Access_Layer LPCG_LPCG_AUD_PLL_DIV_CLK0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_AUD_PLL_DIV_CLK0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_AUD_PLL_DIV_CLK0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_AUD_PLL_DIV_CLK0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_AUD_PLL_DIV_CLK0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_AUD_PLL_DIV_CLK0_Register_Masks LPCG_LPCG_AUD_PLL_DIV_CLK0 Register Masks * @{ */ /*! @name LPCG_LPCG_AUD_PLL_DIV_CLK0_0 - na */ /*! @{ */ #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0 - reserved */ #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_MASK) #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_MASK (0x2U) #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_SHIFT (1U) /*! acm_aud_pll_div_clk0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_MASK) #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_MASK) #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_MASK (0x8U) #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_SHIFT (3U) /*! acm_aud_pll_div_clk0_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_MASK) #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31 - reserved */ #define LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_AUD_PLL_DIV_CLK0_Register_Masks */ /* LPCG_LPCG_AUD_PLL_DIV_CLK0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0 base address */ #define ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE (0x59D20000u) /** Peripheral ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0 base pointer */ #define ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0 ((LPCG_LPCG_AUD_PLL_DIV_CLK0_Type *)ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE) /** Array initializer of LPCG_LPCG_AUD_PLL_DIV_CLK0 peripheral base addresses */ #define LPCG_LPCG_AUD_PLL_DIV_CLK0_BASE_ADDRS { ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE } /** Array initializer of LPCG_LPCG_AUD_PLL_DIV_CLK0 peripheral base pointers */ #define LPCG_LPCG_AUD_PLL_DIV_CLK0_BASE_PTRS { ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0 } /*! * @} */ /* end of group LPCG_LPCG_AUD_PLL_DIV_CLK0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_AUD_PLL_DIV_CLK1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_AUD_PLL_DIV_CLK1_Peripheral_Access_Layer LPCG_LPCG_AUD_PLL_DIV_CLK1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_AUD_PLL_DIV_CLK1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_AUD_PLL_DIV_CLK1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_AUD_PLL_DIV_CLK1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_AUD_PLL_DIV_CLK1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_AUD_PLL_DIV_CLK1_Register_Masks LPCG_LPCG_AUD_PLL_DIV_CLK1 Register Masks * @{ */ /*! @name LPCG_LPCG_AUD_PLL_DIV_CLK1_0 - na */ /*! @{ */ #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0 - reserved */ #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_MASK) #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_MASK (0x2U) #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_SHIFT (1U) /*! acm_aud_pll_div_clk1_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_MASK) #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_MASK) #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_MASK (0x8U) #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_SHIFT (3U) /*! acm_aud_pll_div_clk1_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_MASK) #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31 - reserved */ #define LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_SHIFT)) & LPCG_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_AUD_PLL_DIV_CLK1_Register_Masks */ /* LPCG_LPCG_AUD_PLL_DIV_CLK1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1 base address */ #define ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE (0x59D30000u) /** Peripheral ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1 base pointer */ #define ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1 ((LPCG_LPCG_AUD_PLL_DIV_CLK1_Type *)ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE) /** Array initializer of LPCG_LPCG_AUD_PLL_DIV_CLK1 peripheral base addresses */ #define LPCG_LPCG_AUD_PLL_DIV_CLK1_BASE_ADDRS { ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE } /** Array initializer of LPCG_LPCG_AUD_PLL_DIV_CLK1 peripheral base pointers */ #define LPCG_LPCG_AUD_PLL_DIV_CLK1_BASE_PTRS { ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1 } /*! * @} */ /* end of group LPCG_LPCG_AUD_PLL_DIV_CLK1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_AUD_REC_CLK0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_AUD_REC_CLK0_Peripheral_Access_Layer LPCG_LPCG_AUD_REC_CLK0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_AUD_REC_CLK0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_AUD_REC_CLK0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_AUD_REC_CLK0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_AUD_REC_CLK0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_AUD_REC_CLK0_Register_Masks LPCG_LPCG_AUD_REC_CLK0 Register Masks * @{ */ /*! @name LPCG_LPCG_AUD_REC_CLK0_0 - na */ /*! @{ */ #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_aud_rec_clk0_0_reserved_0_0 - reserved */ #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_MASK) #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_MASK (0x2U) #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_SHIFT (1U) /*! acm_aud_rec_clk0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_SHIFT)) & LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_MASK) #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_aud_rec_clk0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_MASK) #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_MASK (0x8U) #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_SHIFT (3U) /*! acm_aud_rec_clk0_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_SHIFT)) & LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_MASK) #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_aud_rec_clk0_0_reserved_4_31 - reserved */ #define LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_SHIFT)) & LPCG_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_AUD_REC_CLK0_Register_Masks */ /* LPCG_LPCG_AUD_REC_CLK0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_ACM_AUD_REC_CLK0 base address */ #define ADMA__LPCG_ACM_AUD_REC_CLK0_BASE (0x59D00000u) /** Peripheral ADMA__LPCG_ACM_AUD_REC_CLK0 base pointer */ #define ADMA__LPCG_ACM_AUD_REC_CLK0 ((LPCG_LPCG_AUD_REC_CLK0_Type *)ADMA__LPCG_ACM_AUD_REC_CLK0_BASE) /** Array initializer of LPCG_LPCG_AUD_REC_CLK0 peripheral base addresses */ #define LPCG_LPCG_AUD_REC_CLK0_BASE_ADDRS { ADMA__LPCG_ACM_AUD_REC_CLK0_BASE } /** Array initializer of LPCG_LPCG_AUD_REC_CLK0 peripheral base pointers */ #define LPCG_LPCG_AUD_REC_CLK0_BASE_PTRS { ADMA__LPCG_ACM_AUD_REC_CLK0 } /*! * @} */ /* end of group LPCG_LPCG_AUD_REC_CLK0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_AUD_REC_CLK1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_AUD_REC_CLK1_Peripheral_Access_Layer LPCG_LPCG_AUD_REC_CLK1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_AUD_REC_CLK1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_AUD_REC_CLK1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_AUD_REC_CLK1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_AUD_REC_CLK1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_AUD_REC_CLK1_Register_Masks LPCG_LPCG_AUD_REC_CLK1 Register Masks * @{ */ /*! @name LPCG_LPCG_AUD_REC_CLK1_0 - na */ /*! @{ */ #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_aud_rec_clk1_0_reserved_0_0 - reserved */ #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_MASK) #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_MASK (0x2U) #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_SHIFT (1U) /*! acm_aud_rec_clk1_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_SHIFT)) & LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_MASK) #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_aud_rec_clk1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_MASK) #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_MASK (0x8U) #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_SHIFT (3U) /*! acm_aud_rec_clk1_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_SHIFT)) & LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_MASK) #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_aud_rec_clk1_0_reserved_4_31 - reserved */ #define LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_SHIFT)) & LPCG_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_AUD_REC_CLK1_Register_Masks */ /* LPCG_LPCG_AUD_REC_CLK1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_ACM_AUD_REC_CLK1 base address */ #define ADMA__LPCG_ACM_AUD_REC_CLK1_BASE (0x59D10000u) /** Peripheral ADMA__LPCG_ACM_AUD_REC_CLK1 base pointer */ #define ADMA__LPCG_ACM_AUD_REC_CLK1 ((LPCG_LPCG_AUD_REC_CLK1_Type *)ADMA__LPCG_ACM_AUD_REC_CLK1_BASE) /** Array initializer of LPCG_LPCG_AUD_REC_CLK1 peripheral base addresses */ #define LPCG_LPCG_AUD_REC_CLK1_BASE_ADDRS { ADMA__LPCG_ACM_AUD_REC_CLK1_BASE } /** Array initializer of LPCG_LPCG_AUD_REC_CLK1 peripheral base pointers */ #define LPCG_LPCG_AUD_REC_CLK1_BASE_PTRS { ADMA__LPCG_ACM_AUD_REC_CLK1 } /*! * @} */ /* end of group LPCG_LPCG_AUD_REC_CLK1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_CAN0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_CAN0_Peripheral_Access_Layer LPCG_LPCG_CAN0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_CAN0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_CAN0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_CAN0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_CAN0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_CAN0_Register_Masks LPCG_LPCG_CAN0 Register Masks * @{ */ /*! @name LPCG_LPCG_CAN0_0 - na */ /*! @{ */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_MASK (0x1U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_SHIFT (0U) /*! can0_ipg_clk_pe_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN_MASK (0x2U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN_SHIFT (1U) /*! can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_can0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_2_2_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP_MASK (0x8U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP_SHIFT (3U) /*! can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_can0_0_reserved_4_15 - reserved */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_4_15_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_SHIFT (16U) /*! can0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_SHIFT (17U) /*! can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_can0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_18_18_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_SHIFT (19U) /*! can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_MASK (0x100000U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_SHIFT (20U) /*! can0_ipg_clk_chi_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_MASK (0x200000U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_SHIFT (21U) /*! can0_ipg_clk_chi_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_22_22_MASK (0x400000U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_can0_0_reserved_22_22 - reserved */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_22_22_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_22_22_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_MASK (0x800000U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_SHIFT (23U) /*! can0_ipg_clk_chi_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_MASK) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_24_31_MASK (0xFF000000U) #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_24_31_SHIFT (24U) /*! LPCG_lpcg_can0_0_reserved_24_31 - reserved */ #define LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_24_31_SHIFT)) & LPCG_LPCG_CAN0_LPCG_LPCG_CAN0_0_LPCG_lpcg_can0_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_CAN0_Register_Masks */ /* LPCG_LPCG_CAN0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_CAN0_IPG_CLK base address */ #define ADMA__LPCG_CAN0_IPG_CLK_BASE (0x5ACD0000u) /** Peripheral ADMA__LPCG_CAN0_IPG_CLK base pointer */ #define ADMA__LPCG_CAN0_IPG_CLK ((LPCG_LPCG_CAN0_Type *)ADMA__LPCG_CAN0_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_CAN0 peripheral base addresses */ #define LPCG_LPCG_CAN0_BASE_ADDRS { ADMA__LPCG_CAN0_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_CAN0 peripheral base pointers */ #define LPCG_LPCG_CAN0_BASE_PTRS { ADMA__LPCG_CAN0_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_CAN0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_CAN1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_CAN1_Peripheral_Access_Layer LPCG_LPCG_CAN1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_CAN1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_CAN1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_CAN1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_CAN1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_CAN1_Register_Masks LPCG_LPCG_CAN1 Register Masks * @{ */ /*! @name LPCG_LPCG_CAN1_0 - na */ /*! @{ */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_MASK (0x1U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_SHIFT (0U) /*! can1_ipg_clk_pe_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN_MASK (0x2U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN_SHIFT (1U) /*! can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_can1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_2_2_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP_MASK (0x8U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP_SHIFT (3U) /*! can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_can1_0_reserved_4_15 - reserved */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_4_15_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_SHIFT (16U) /*! can1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_SHIFT (17U) /*! can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_can1_0_reserved_18_18 - reserved */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_18_18_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_SHIFT (19U) /*! can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_MASK (0x100000U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_SHIFT (20U) /*! can1_ipg_clk_chi_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_MASK (0x200000U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_SHIFT (21U) /*! can1_ipg_clk_chi_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_22_22_MASK (0x400000U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_can1_0_reserved_22_22 - reserved */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_22_22_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_22_22_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_MASK (0x800000U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_SHIFT (23U) /*! can1_ipg_clk_chi_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_MASK) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_24_31_MASK (0xFF000000U) #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_24_31_SHIFT (24U) /*! LPCG_lpcg_can1_0_reserved_24_31 - reserved */ #define LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_24_31_SHIFT)) & LPCG_LPCG_CAN1_LPCG_LPCG_CAN1_0_LPCG_lpcg_can1_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_CAN1_Register_Masks */ /* LPCG_LPCG_CAN1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_CAN1_IPG_CLK base address */ #define ADMA__LPCG_CAN1_IPG_CLK_BASE (0x5ACE0000u) /** Peripheral ADMA__LPCG_CAN1_IPG_CLK base pointer */ #define ADMA__LPCG_CAN1_IPG_CLK ((LPCG_LPCG_CAN1_Type *)ADMA__LPCG_CAN1_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_CAN1 peripheral base addresses */ #define LPCG_LPCG_CAN1_BASE_ADDRS { ADMA__LPCG_CAN1_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_CAN1 peripheral base pointers */ #define LPCG_LPCG_CAN1_BASE_PTRS { ADMA__LPCG_CAN1_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_CAN1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_CAN2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_CAN2_Peripheral_Access_Layer LPCG_LPCG_CAN2 Peripheral Access Layer * @{ */ /** LPCG_LPCG_CAN2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_CAN2_0; /**< na, offset: 0x0 */ } LPCG_LPCG_CAN2_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_CAN2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_CAN2_Register_Masks LPCG_LPCG_CAN2 Register Masks * @{ */ /*! @name LPCG_LPCG_CAN2_0 - na */ /*! @{ */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_MASK (0x1U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_SHIFT (0U) /*! can2_ipg_clk_pe_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN_MASK (0x2U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN_SHIFT (1U) /*! can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_can2_0_reserved_2_2 - reserved */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_2_2_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP_MASK (0x8U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP_SHIFT (3U) /*! can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_can2_0_reserved_4_15 - reserved */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_4_15_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_SHIFT (16U) /*! can2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_SHIFT (17U) /*! can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_can2_0_reserved_18_18 - reserved */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_18_18_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_SHIFT (19U) /*! can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_MASK (0x100000U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_SHIFT (20U) /*! can2_ipg_clk_chi_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_MASK (0x200000U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_SHIFT (21U) /*! can2_ipg_clk_chi_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_22_22_MASK (0x400000U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_can2_0_reserved_22_22 - reserved */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_22_22_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_22_22_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_MASK (0x800000U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_SHIFT (23U) /*! can2_ipg_clk_chi_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_MASK) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_24_31_MASK (0xFF000000U) #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_24_31_SHIFT (24U) /*! LPCG_lpcg_can2_0_reserved_24_31 - reserved */ #define LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_24_31_SHIFT)) & LPCG_LPCG_CAN2_LPCG_LPCG_CAN2_0_LPCG_lpcg_can2_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_CAN2_Register_Masks */ /* LPCG_LPCG_CAN2 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_CAN2_IPG_CLK base address */ #define ADMA__LPCG_CAN2_IPG_CLK_BASE (0x5ACF0000u) /** Peripheral ADMA__LPCG_CAN2_IPG_CLK base pointer */ #define ADMA__LPCG_CAN2_IPG_CLK ((LPCG_LPCG_CAN2_Type *)ADMA__LPCG_CAN2_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_CAN2 peripheral base addresses */ #define LPCG_LPCG_CAN2_BASE_ADDRS { ADMA__LPCG_CAN2_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_CAN2 peripheral base pointers */ #define LPCG_LPCG_CAN2_BASE_PTRS { ADMA__LPCG_CAN2_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_CAN2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_EDMA0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_EDMA0_Peripheral_Access_Layer LPCG_LPCG_EDMA0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_EDMA0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_EDMA0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_EDMA0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_EDMA0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_EDMA0_Register_Masks LPCG_LPCG_EDMA0 Register Masks * @{ */ /*! @name LPCG_LPCG_EDMA0_0 - na */ /*! @{ */ #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_edma0_0_reserved_0_0 - reserved */ #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_MASK) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN_SHIFT (1U) /*! edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN_MASK) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_edma0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_MASK) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP_MASK (0x8U) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP_SHIFT (3U) /*! edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP_MASK) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_MASK (0x1FFF0U) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_SHIFT (4U) /*! LPCG_lpcg_edma0_0_reserved_4_16 - reserved */ #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_MASK) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_SHIFT (17U) /*! edma0_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_MASK) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_edma0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_MASK) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_SHIFT (19U) /*! edma0_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_MASK) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_edma0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_EDMA0_Register_Masks */ /* LPCG_LPCG_EDMA0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_EDMA0_HCLK base address */ #define ADMA__LPCG_EDMA0_HCLK_BASE (0x595F0000u) /** Peripheral ADMA__LPCG_EDMA0_HCLK base pointer */ #define ADMA__LPCG_EDMA0_HCLK ((LPCG_LPCG_EDMA0_Type *)ADMA__LPCG_EDMA0_HCLK_BASE) /** Array initializer of LPCG_LPCG_EDMA0 peripheral base addresses */ #define LPCG_LPCG_EDMA0_BASE_ADDRS { ADMA__LPCG_EDMA0_HCLK_BASE } /** Array initializer of LPCG_LPCG_EDMA0 peripheral base pointers */ #define LPCG_LPCG_EDMA0_BASE_PTRS { ADMA__LPCG_EDMA0_HCLK } /*! * @} */ /* end of group LPCG_LPCG_EDMA0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_EDMA1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_EDMA1_Peripheral_Access_Layer LPCG_LPCG_EDMA1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_EDMA1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_EDMA1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_EDMA1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_EDMA1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_EDMA1_Register_Masks LPCG_LPCG_EDMA1 Register Masks * @{ */ /*! @name LPCG_LPCG_EDMA1_0 - na */ /*! @{ */ #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_edma1_0_reserved_0_0 - reserved */ #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_MASK) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN_SHIFT (1U) /*! edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_AND_edma1_ipd_gasket_ipg_clk_SWEN_MASK) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_edma1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_MASK) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP_MASK (0x8U) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP_SHIFT (3U) /*! edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_AND_edma1_ipd_gasket_ipg_clk_STOP_MASK) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_MASK (0x1FFF0U) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_SHIFT (4U) /*! LPCG_lpcg_edma1_0_reserved_4_16 - reserved */ #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_MASK) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_SHIFT (17U) /*! edma1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_MASK) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_edma1_0_reserved_18_18 - reserved */ #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_MASK) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_SHIFT (19U) /*! edma1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_MASK) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_edma1_0_reserved_20_31 - reserved */ #define LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_EDMA1_Register_Masks */ /* LPCG_LPCG_EDMA1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_EDMA1_HCLK base address */ #define ADMA__LPCG_EDMA1_HCLK_BASE (0x59DF0000u) /** Peripheral ADMA__LPCG_EDMA1_HCLK base pointer */ #define ADMA__LPCG_EDMA1_HCLK ((LPCG_LPCG_EDMA1_Type *)ADMA__LPCG_EDMA1_HCLK_BASE) /** Array initializer of LPCG_LPCG_EDMA1 peripheral base addresses */ #define LPCG_LPCG_EDMA1_BASE_ADDRS { ADMA__LPCG_EDMA1_HCLK_BASE } /** Array initializer of LPCG_LPCG_EDMA1 peripheral base pointers */ #define LPCG_LPCG_EDMA1_BASE_PTRS { ADMA__LPCG_EDMA1_HCLK } /*! * @} */ /* end of group LPCG_LPCG_EDMA1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_EDMA2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_EDMA2_Peripheral_Access_Layer LPCG_LPCG_EDMA2 Peripheral Access Layer * @{ */ /** LPCG_LPCG_EDMA2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_EDMA2_0; /**< na, offset: 0x0 */ } LPCG_LPCG_EDMA2_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_EDMA2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_EDMA2_Register_Masks LPCG_LPCG_EDMA2 Register Masks * @{ */ /*! @name LPCG_LPCG_EDMA2_0 - na */ /*! @{ */ #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_edma2_0_reserved_0_0 - reserved */ #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_0_0_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_0_0_MASK) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN_MASK (0x2U) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN_SHIFT (1U) /*! edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN_AND_ipd_sync_1_hclk_SWEN_AND_ipd_sync_2_hclk_SWEN_AND_ipd_sync_3_hclk_SWEN_AND_ipd_req_latch_0_clock_SWEN_AND_ipd_req_latch_1_clock_SWEN_MASK) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_edma2_0_reserved_2_2 - reserved */ #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_2_2_MASK) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP_MASK (0x8U) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP_SHIFT (3U) /*! edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP_AND_ipd_sync_1_hclk_STOP_AND_ipd_sync_2_hclk_STOP_AND_ipd_sync_3_hclk_STOP_AND_ipd_req_latch_0_clock_STOP_AND_ipd_req_latch_1_clock_STOP_MASK) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_4_16_MASK (0x1FFF0U) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_4_16_SHIFT (4U) /*! LPCG_lpcg_edma2_0_reserved_4_16 - reserved */ #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_4_16_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_4_16_MASK) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_SWEN_SHIFT (17U) /*! edma2_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_SWEN_MASK) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_edma2_0_reserved_18_18 - reserved */ #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_18_18_MASK) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_STOP_SHIFT (19U) /*! edma2_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_edma2_ipg_clk_STOP_MASK) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_edma2_0_reserved_20_31 - reserved */ #define LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_EDMA2_LPCG_LPCG_EDMA2_0_LPCG_lpcg_edma2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_EDMA2_Register_Masks */ /* LPCG_LPCG_EDMA2 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_EDMA2_HCLK base address */ #define ADMA__LPCG_EDMA2_HCLK_BASE (0x5A5F0000u) /** Peripheral ADMA__LPCG_EDMA2_HCLK base pointer */ #define ADMA__LPCG_EDMA2_HCLK ((LPCG_LPCG_EDMA2_Type *)ADMA__LPCG_EDMA2_HCLK_BASE) /** Array initializer of LPCG_LPCG_EDMA2 peripheral base addresses */ #define LPCG_LPCG_EDMA2_BASE_ADDRS { ADMA__LPCG_EDMA2_HCLK_BASE } /** Array initializer of LPCG_LPCG_EDMA2 peripheral base pointers */ #define LPCG_LPCG_EDMA2_BASE_PTRS { ADMA__LPCG_EDMA2_HCLK } /*! * @} */ /* end of group LPCG_LPCG_EDMA2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_EDMA3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_EDMA3_Peripheral_Access_Layer LPCG_LPCG_EDMA3 Peripheral Access Layer * @{ */ /** LPCG_LPCG_EDMA3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_EDMA3_0; /**< na, offset: 0x0 */ } LPCG_LPCG_EDMA3_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_EDMA3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_EDMA3_Register_Masks LPCG_LPCG_EDMA3 Register Masks * @{ */ /*! @name LPCG_LPCG_EDMA3_0 - na */ /*! @{ */ #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_edma3_0_reserved_0_0 - reserved */ #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_0_0_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_0_0_MASK) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN_SHIFT (1U) /*! edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN_MASK) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_edma3_0_reserved_2_2 - reserved */ #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_2_2_MASK) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP_MASK (0x8U) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP_SHIFT (3U) /*! edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP_MASK) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_4_16_MASK (0x1FFF0U) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_4_16_SHIFT (4U) /*! LPCG_lpcg_edma3_0_reserved_4_16 - reserved */ #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_4_16_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_4_16_MASK) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_SWEN_SHIFT (17U) /*! edma3_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_SWEN_MASK) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_edma3_0_reserved_18_18 - reserved */ #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_18_18_MASK) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_STOP_SHIFT (19U) /*! edma3_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_edma3_ipg_clk_STOP_MASK) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_edma3_0_reserved_20_31 - reserved */ #define LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_EDMA3_LPCG_LPCG_EDMA3_0_LPCG_lpcg_edma3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_EDMA3_Register_Masks */ /* LPCG_LPCG_EDMA3 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_EDMA3_HCLK base address */ #define ADMA__LPCG_EDMA3_HCLK_BASE (0x5ADF0000u) /** Peripheral ADMA__LPCG_EDMA3_HCLK base pointer */ #define ADMA__LPCG_EDMA3_HCLK ((LPCG_LPCG_EDMA3_Type *)ADMA__LPCG_EDMA3_HCLK_BASE) /** Array initializer of LPCG_LPCG_EDMA3 peripheral base addresses */ #define LPCG_LPCG_EDMA3_BASE_ADDRS { ADMA__LPCG_EDMA3_HCLK_BASE } /** Array initializer of LPCG_LPCG_EDMA3 peripheral base pointers */ #define LPCG_LPCG_EDMA3_BASE_PTRS { ADMA__LPCG_EDMA3_HCLK } /*! * @} */ /* end of group LPCG_LPCG_EDMA3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_ESAI0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_ESAI0_Peripheral_Access_Layer LPCG_LPCG_ESAI0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_ESAI0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_ESAI0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_ESAI0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_ESAI0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_ESAI0_Register_Masks LPCG_LPCG_ESAI0 Register Masks * @{ */ /*! @name LPCG_LPCG_ESAI0_0 - na */ /*! @{ */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_esai0_0_reserved_0_0 - reserved */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_0_0_MASK) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_SHIFT (1U) /*! esai0_extal_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_MASK) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_esai0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_MASK) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_MASK (0x8U) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_SHIFT (3U) /*! esai0_extal_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_MASK) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_esai0_0_reserved_4_15 - reserved */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_15_MASK) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN_MASK (0x10000U) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN_SHIFT (16U) /*! esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_AND_esai0_ipg_clk_esai_HWEN_MASK) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN_MASK (0x20000U) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN_SHIFT (17U) /*! esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_AND_esai0_ipg_clk_esai_SWEN_MASK) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_esai0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_MASK) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP_MASK (0x80000U) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP_SHIFT (19U) /*! esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_AND_esai0_ipg_clk_esai_STOP_MASK) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_esai0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_ESAI0_Register_Masks */ /* LPCG_LPCG_ESAI0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_ESAI0_EXTAL_CLK base address */ #define ADMA__LPCG_ESAI0_EXTAL_CLK_BASE (0x59410000u) /** Peripheral ADMA__LPCG_ESAI0_EXTAL_CLK base pointer */ #define ADMA__LPCG_ESAI0_EXTAL_CLK ((LPCG_LPCG_ESAI0_Type *)ADMA__LPCG_ESAI0_EXTAL_CLK_BASE) /** Array initializer of LPCG_LPCG_ESAI0 peripheral base addresses */ #define LPCG_LPCG_ESAI0_BASE_ADDRS { ADMA__LPCG_ESAI0_EXTAL_CLK_BASE } /** Array initializer of LPCG_LPCG_ESAI0 peripheral base pointers */ #define LPCG_LPCG_ESAI0_BASE_PTRS { ADMA__LPCG_ESAI0_EXTAL_CLK } /*! * @} */ /* end of group LPCG_LPCG_ESAI0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_FTM0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_FTM0_Peripheral_Access_Layer LPCG_LPCG_FTM0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_FTM0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_FTM0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_FTM0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_FTM0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_FTM0_Register_Masks LPCG_LPCG_FTM0 Register Masks * @{ */ /*! @name LPCG_LPCG_FTM0_0 - na */ /*! @{ */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_MASK (0x1U) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_SHIFT (0U) /*! ftm0_ipp_ind_extclk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_MASK) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_MASK (0x2U) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_SHIFT (1U) /*! ftm0_ipp_ind_extclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_MASK) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_ftm0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_2_2_MASK) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_MASK (0x8U) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_SHIFT (3U) /*! ftm0_ipp_ind_extclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_MASK) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_ftm0_0_reserved_4_15 - reserved */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_4_15_MASK) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_SHIFT (16U) /*! ftm0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_SHIFT (17U) /*! ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_ftm0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_18_18_MASK) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_SHIFT (19U) /*! ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_ftm0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_FTM0_LPCG_LPCG_FTM0_0_LPCG_lpcg_ftm0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_FTM0_Register_Masks */ /* LPCG_LPCG_FTM0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_FTM0_IPG_CLK base address */ #define ADMA__LPCG_FTM0_IPG_CLK_BASE (0x5ACA0000u) /** Peripheral ADMA__LPCG_FTM0_IPG_CLK base pointer */ #define ADMA__LPCG_FTM0_IPG_CLK ((LPCG_LPCG_FTM0_Type *)ADMA__LPCG_FTM0_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_FTM0 peripheral base addresses */ #define LPCG_LPCG_FTM0_BASE_ADDRS { ADMA__LPCG_FTM0_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_FTM0 peripheral base pointers */ #define LPCG_LPCG_FTM0_BASE_PTRS { ADMA__LPCG_FTM0_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_FTM0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_FTM1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_FTM1_Peripheral_Access_Layer LPCG_LPCG_FTM1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_FTM1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_FTM1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_FTM1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_FTM1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_FTM1_Register_Masks LPCG_LPCG_FTM1 Register Masks * @{ */ /*! @name LPCG_LPCG_FTM1_0 - na */ /*! @{ */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_MASK (0x1U) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_SHIFT (0U) /*! ftm1_ipp_ind_extclk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_MASK) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_MASK (0x2U) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_SHIFT (1U) /*! ftm1_ipp_ind_extclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_MASK) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_ftm1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_2_2_MASK) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_MASK (0x8U) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_SHIFT (3U) /*! ftm1_ipp_ind_extclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_MASK) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_ftm1_0_reserved_4_15 - reserved */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_4_15_MASK) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_SHIFT (16U) /*! ftm1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_SHIFT (17U) /*! ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_ftm1_0_reserved_18_18 - reserved */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_18_18_MASK) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_SHIFT (19U) /*! ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_ftm1_0_reserved_20_31 - reserved */ #define LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_FTM1_LPCG_LPCG_FTM1_0_LPCG_lpcg_ftm1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_FTM1_Register_Masks */ /* LPCG_LPCG_FTM1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_FTM1_IPG_CLK base address */ #define ADMA__LPCG_FTM1_IPG_CLK_BASE (0x5ACB0000u) /** Peripheral ADMA__LPCG_FTM1_IPG_CLK base pointer */ #define ADMA__LPCG_FTM1_IPG_CLK ((LPCG_LPCG_FTM1_Type *)ADMA__LPCG_FTM1_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_FTM1 peripheral base addresses */ #define LPCG_LPCG_FTM1_BASE_ADDRS { ADMA__LPCG_FTM1_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_FTM1 peripheral base pointers */ #define LPCG_LPCG_FTM1_BASE_PTRS { ADMA__LPCG_FTM1_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_FTM1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT0_Peripheral_Access_Layer LPCG_LPCG_GPT0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_GPT0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_GPT0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT0_Register_Masks LPCG_LPCG_GPT0 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT0_0 - na */ /*! @{ */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_gpt0_0_reserved_0_0 - reserved */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_0_0_MASK) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_MASK (0x2U) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_SHIFT (1U) /*! gpt0_ipp_ind_clkin_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_MASK) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_gpt0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_MASK) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_MASK (0x8U) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_SHIFT (3U) /*! gpt0_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_MASK) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_gpt0_0_reserved_4_15 - reserved */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_15_MASK) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_gpt0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_MASK) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP_SHIFT (19U) /*! gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_gpt0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_GPT0_Register_Masks */ /* LPCG_LPCG_GPT0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_GPT0_IPG_CLK_24M base address */ #define ADMA__LPCG_GPT0_IPG_CLK_24M_BASE (0x594B0000u) /** Peripheral ADMA__LPCG_GPT0_IPG_CLK_24M base pointer */ #define ADMA__LPCG_GPT0_IPG_CLK_24M ((LPCG_LPCG_GPT0_Type *)ADMA__LPCG_GPT0_IPG_CLK_24M_BASE) /** Array initializer of LPCG_LPCG_GPT0 peripheral base addresses */ #define LPCG_LPCG_GPT0_BASE_ADDRS { ADMA__LPCG_GPT0_IPG_CLK_24M_BASE } /** Array initializer of LPCG_LPCG_GPT0 peripheral base pointers */ #define LPCG_LPCG_GPT0_BASE_PTRS { ADMA__LPCG_GPT0_IPG_CLK_24M } /*! * @} */ /* end of group LPCG_LPCG_GPT0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT1_Peripheral_Access_Layer LPCG_LPCG_GPT1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_GPT1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_GPT1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT1_Register_Masks LPCG_LPCG_GPT1 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT1_0 - na */ /*! @{ */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_gpt1_0_reserved_0_0 - reserved */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_0_0_MASK) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_MASK (0x2U) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_SHIFT (1U) /*! gpt1_ipp_ind_clkin_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_MASK) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_gpt1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_MASK) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_MASK (0x8U) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_SHIFT (3U) /*! gpt1_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_MASK) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_gpt1_0_reserved_4_15 - reserved */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_15_MASK) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_gpt1_0_reserved_18_18 - reserved */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_MASK) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP_SHIFT (19U) /*! gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_gpt1_0_reserved_20_31 - reserved */ #define LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_GPT1_Register_Masks */ /* LPCG_LPCG_GPT1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_GPT1_IPG_CLK_24M base address */ #define ADMA__LPCG_GPT1_IPG_CLK_24M_BASE (0x594C0000u) /** Peripheral ADMA__LPCG_GPT1_IPG_CLK_24M base pointer */ #define ADMA__LPCG_GPT1_IPG_CLK_24M ((LPCG_LPCG_GPT1_Type *)ADMA__LPCG_GPT1_IPG_CLK_24M_BASE) /** Array initializer of LPCG_LPCG_GPT1 peripheral base addresses */ #define LPCG_LPCG_GPT1_BASE_ADDRS { ADMA__LPCG_GPT1_IPG_CLK_24M_BASE } /** Array initializer of LPCG_LPCG_GPT1 peripheral base pointers */ #define LPCG_LPCG_GPT1_BASE_PTRS { ADMA__LPCG_GPT1_IPG_CLK_24M } /*! * @} */ /* end of group LPCG_LPCG_GPT1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT2_Peripheral_Access_Layer LPCG_LPCG_GPT2 Peripheral Access Layer * @{ */ /** LPCG_LPCG_GPT2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT2_0; /**< na, offset: 0x0 */ } LPCG_LPCG_GPT2_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT2_Register_Masks LPCG_LPCG_GPT2 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT2_0 - na */ /*! @{ */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_gpt2_0_reserved_0_0 - reserved */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_0_0_MASK) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_MASK (0x2U) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_SHIFT (1U) /*! gpt2_ipp_ind_clkin_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_MASK) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_gpt2_0_reserved_2_2 - reserved */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_MASK) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_MASK (0x8U) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_SHIFT (3U) /*! gpt2_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_MASK) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_gpt2_0_reserved_4_15 - reserved */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_15_MASK) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_gpt2_0_reserved_18_18 - reserved */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_MASK) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP_SHIFT (19U) /*! gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_gpt2_0_reserved_20_31 - reserved */ #define LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_GPT2_Register_Masks */ /* LPCG_LPCG_GPT2 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_GPT2_IPG_CLK_24M base address */ #define ADMA__LPCG_GPT2_IPG_CLK_24M_BASE (0x594D0000u) /** Peripheral ADMA__LPCG_GPT2_IPG_CLK_24M base pointer */ #define ADMA__LPCG_GPT2_IPG_CLK_24M ((LPCG_LPCG_GPT2_Type *)ADMA__LPCG_GPT2_IPG_CLK_24M_BASE) /** Array initializer of LPCG_LPCG_GPT2 peripheral base addresses */ #define LPCG_LPCG_GPT2_BASE_ADDRS { ADMA__LPCG_GPT2_IPG_CLK_24M_BASE } /** Array initializer of LPCG_LPCG_GPT2 peripheral base pointers */ #define LPCG_LPCG_GPT2_BASE_PTRS { ADMA__LPCG_GPT2_IPG_CLK_24M } /*! * @} */ /* end of group LPCG_LPCG_GPT2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT3_Peripheral_Access_Layer LPCG_LPCG_GPT3 Peripheral Access Layer * @{ */ /** LPCG_LPCG_GPT3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT3_0; /**< na, offset: 0x0 */ } LPCG_LPCG_GPT3_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT3_Register_Masks LPCG_LPCG_GPT3 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT3_0 - na */ /*! @{ */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_gpt3_0_reserved_0_0 - reserved */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_0_0_MASK) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_MASK (0x2U) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_SHIFT (1U) /*! gpt3_ipp_ind_clkin_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_MASK) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_gpt3_0_reserved_2_2 - reserved */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_MASK) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_MASK (0x8U) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_SHIFT (3U) /*! gpt3_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_MASK) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_gpt3_0_reserved_4_15 - reserved */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_15_MASK) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_gpt3_0_reserved_18_18 - reserved */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_MASK) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP_SHIFT (19U) /*! gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_gpt3_0_reserved_20_31 - reserved */ #define LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_GPT3_Register_Masks */ /* LPCG_LPCG_GPT3 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_GPT3_IPG_CLK_24M base address */ #define ADMA__LPCG_GPT3_IPG_CLK_24M_BASE (0x594E0000u) /** Peripheral ADMA__LPCG_GPT3_IPG_CLK_24M base pointer */ #define ADMA__LPCG_GPT3_IPG_CLK_24M ((LPCG_LPCG_GPT3_Type *)ADMA__LPCG_GPT3_IPG_CLK_24M_BASE) /** Array initializer of LPCG_LPCG_GPT3 peripheral base addresses */ #define LPCG_LPCG_GPT3_BASE_ADDRS { ADMA__LPCG_GPT3_IPG_CLK_24M_BASE } /** Array initializer of LPCG_LPCG_GPT3 peripheral base pointers */ #define LPCG_LPCG_GPT3_BASE_PTRS { ADMA__LPCG_GPT3_IPG_CLK_24M } /*! * @} */ /* end of group LPCG_LPCG_GPT3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT4_Peripheral_Access_Layer LPCG_LPCG_GPT4 Peripheral Access Layer * @{ */ /** LPCG_LPCG_GPT4 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT4_0; /**< na, offset: 0x0 */ } LPCG_LPCG_GPT4_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT4_Register_Masks LPCG_LPCG_GPT4 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT4_0 - na */ /*! @{ */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_gpt4_0_reserved_0_0 - reserved */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_0_0_MASK) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_MASK (0x2U) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_SHIFT (1U) /*! gpt4_ipp_ind_clkin_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_MASK) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_gpt4_0_reserved_2_2 - reserved */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_MASK) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_MASK (0x8U) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_SHIFT (3U) /*! gpt4_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_MASK) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_gpt4_0_reserved_4_15 - reserved */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_15_MASK) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_HWEN_AND_gpt4_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_SWEN_AND_gpt4_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_gpt4_0_reserved_18_18 - reserved */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_MASK) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP_SHIFT (19U) /*! gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_STOP_AND_gpt4_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_gpt4_0_reserved_20_31 - reserved */ #define LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_GPT4_Register_Masks */ /* LPCG_LPCG_GPT4 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_GPT4_IPG_CLK_24M base address */ #define ADMA__LPCG_GPT4_IPG_CLK_24M_BASE (0x594F0000u) /** Peripheral ADMA__LPCG_GPT4_IPG_CLK_24M base pointer */ #define ADMA__LPCG_GPT4_IPG_CLK_24M ((LPCG_LPCG_GPT4_Type *)ADMA__LPCG_GPT4_IPG_CLK_24M_BASE) /** Array initializer of LPCG_LPCG_GPT4 peripheral base addresses */ #define LPCG_LPCG_GPT4_BASE_ADDRS { ADMA__LPCG_GPT4_IPG_CLK_24M_BASE } /** Array initializer of LPCG_LPCG_GPT4 peripheral base pointers */ #define LPCG_LPCG_GPT4_BASE_PTRS { ADMA__LPCG_GPT4_IPG_CLK_24M } /*! * @} */ /* end of group LPCG_LPCG_GPT4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT5_Peripheral_Access_Layer LPCG_LPCG_GPT5 Peripheral Access Layer * @{ */ /** LPCG_LPCG_GPT5 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_GPT5_0; /**< na, offset: 0x0 */ } LPCG_LPCG_GPT5_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_GPT5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_GPT5_Register_Masks LPCG_LPCG_GPT5 Register Masks * @{ */ /*! @name LPCG_LPCG_GPT5_0 - na */ /*! @{ */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_gpt5_0_reserved_0_0 - reserved */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_0_0_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_0_0_MASK) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_MASK (0x2U) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_SHIFT (1U) /*! gpt5_ipp_ind_clkin_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_MASK) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_gpt5_0_reserved_2_2 - reserved */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_MASK) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_MASK (0x8U) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_SHIFT (3U) /*! gpt5_ipp_ind_clkin_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_MASK) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_gpt5_0_reserved_4_15 - reserved */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_15_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_15_MASK) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_HWEN_AND_gpt5_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_SWEN_AND_gpt5_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_gpt5_0_reserved_18_18 - reserved */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_MASK) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP_SHIFT (19U) /*! gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_STOP_AND_gpt5_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_gpt5_0_reserved_20_31 - reserved */ #define LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_31_SHIFT)) & LPCG_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_GPT5_Register_Masks */ /* LPCG_LPCG_GPT5 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_GPT5_IPG_CLK_24M base address */ #define ADMA__LPCG_GPT5_IPG_CLK_24M_BASE (0x59500000u) /** Peripheral ADMA__LPCG_GPT5_IPG_CLK_24M base pointer */ #define ADMA__LPCG_GPT5_IPG_CLK_24M ((LPCG_LPCG_GPT5_Type *)ADMA__LPCG_GPT5_IPG_CLK_24M_BASE) /** Array initializer of LPCG_LPCG_GPT5 peripheral base addresses */ #define LPCG_LPCG_GPT5_BASE_ADDRS { ADMA__LPCG_GPT5_IPG_CLK_24M_BASE } /** Array initializer of LPCG_LPCG_GPT5 peripheral base pointers */ #define LPCG_LPCG_GPT5_BASE_PTRS { ADMA__LPCG_GPT5_IPG_CLK_24M } /*! * @} */ /* end of group LPCG_LPCG_GPT5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_HIFI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_HIFI_Peripheral_Access_Layer LPCG_LPCG_HIFI Peripheral Access Layer * @{ */ /** LPCG_LPCG_HIFI - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_HIFI_0; /**< na, offset: 0x0 */ } LPCG_LPCG_HIFI_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_HIFI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_HIFI_Register_Masks LPCG_LPCG_HIFI Register Masks * @{ */ /*! @name LPCG_LPCG_HIFI_0 - na */ /*! @{ */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_0_16_MASK (0x1FFFFU) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_0_16_SHIFT (0U) /*! LPCG_lpcg_hifi_0_reserved_0_16 - reserved */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_0_16_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_0_16_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_MASK (0x20000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_SHIFT (17U) /*! adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic0nic1_mst_aclk_SWEN_AND_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_hifi_0_reserved_18_18 - reserved */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_18_18_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_18_18_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_MASK (0x80000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_SHIFT (19U) /*! adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic0nic1_mst_aclk_STOP_AND_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_20_20_MASK (0x100000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_20_20_SHIFT (20U) /*! LPCG_lpcg_hifi_0_reserved_20_20 - reserved */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_20_20_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_20_20_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN_MASK (0x200000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN_SHIFT (21U) /*! hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_SWEN_AND_hifi_mem_CLK_SWEN_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_22_22_MASK (0x400000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_hifi_0_reserved_22_22 - reserved */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_22_22_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_22_22_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP_MASK (0x800000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP_SHIFT (23U) /*! hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_CLK_STOP_AND_hifi_mem_CLK_STOP_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_24_28_MASK (0x1F000000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_24_28_SHIFT (24U) /*! LPCG_lpcg_hifi_0_reserved_24_28 - reserved */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_24_28(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_24_28_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_24_28_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN_MASK (0x20000000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN_SHIFT (29U) /*! hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_SWEN_AND_hifi_core_ATCLK_SWEN_AND_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_dbg_atbm_clks_SWEN_AND_hifi_dbg_cti_cticlk_SWEN_AND_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_dbg_romtable_apb_clk_SWEN_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_30_30_MASK (0x40000000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_30_30_SHIFT (30U) /*! LPCG_lpcg_hifi_0_reserved_30_30 - reserved */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_30_30_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_LPCG_lpcg_hifi_0_reserved_30_30_MASK) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP_MASK (0x80000000U) #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP_SHIFT (31U) /*! hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP_SHIFT)) & LPCG_LPCG_HIFI_LPCG_LPCG_HIFI_0_hifi_core_PBCLK_STOP_AND_hifi_core_ATCLK_STOP_AND_hifi_dbg_apbs_pclkm_STOP_AND_hifi_dbg_atbm_clks_STOP_AND_hifi_dbg_cti_cticlk_STOP_AND_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_dbg_romtable_apb_clk_STOP_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_HIFI_Register_Masks */ /* LPCG_LPCG_HIFI - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK base address */ #define ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK_BASE (0x59580000u) /** Peripheral ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK base pointer */ #define ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK ((LPCG_LPCG_HIFI_Type *)ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK_BASE) /** Array initializer of LPCG_LPCG_HIFI peripheral base addresses */ #define LPCG_LPCG_HIFI_BASE_ADDRS { ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK_BASE } /** Array initializer of LPCG_LPCG_HIFI peripheral base pointers */ #define LPCG_LPCG_HIFI_BASE_PTRS { ADMA__LPCG_ADB_NIC0NIC1_MST_ACLK } /*! * @} */ /* end of group LPCG_LPCG_HIFI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_I2C0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_I2C0_Peripheral_Access_Layer LPCG_LPCG_I2C0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_I2C0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_I2C0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_I2C0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_I2C0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_I2C0_Register_Masks LPCG_LPCG_I2C0 Register Masks * @{ */ /*! @name LPCG_LPCG_I2C0_0 - na */ /*! @{ */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_div_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_div_clk_HWEN_SHIFT (0U) /*! i2c0_lpi2c_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_div_clk_HWEN_MASK) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN_SHIFT (1U) /*! i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN_MASK) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_i2c0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_2_2_MASK) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP_MASK (0x8U) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP_SHIFT (3U) /*! i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP_MASK) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_i2c0_0_reserved_4_15 - reserved */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_4_15_MASK) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_s_HWEN_SHIFT (16U) /*! i2c0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN_SHIFT (17U) /*! i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_i2c0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_18_18_MASK) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP_SHIFT (19U) /*! i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_i2c0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_I2C0_LPCG_LPCG_I2C0_0_LPCG_lpcg_i2c0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_I2C0_Register_Masks */ /* LPCG_LPCG_I2C0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_I2C0_IPG_CLK base address */ #define ADMA__LPCG_I2C0_IPG_CLK_BASE (0x5AC00000u) /** Peripheral ADMA__LPCG_I2C0_IPG_CLK base pointer */ #define ADMA__LPCG_I2C0_IPG_CLK ((LPCG_LPCG_I2C0_Type *)ADMA__LPCG_I2C0_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_I2C0 peripheral base addresses */ #define LPCG_LPCG_I2C0_BASE_ADDRS { ADMA__LPCG_I2C0_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_I2C0 peripheral base pointers */ #define LPCG_LPCG_I2C0_BASE_PTRS { ADMA__LPCG_I2C0_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_I2C0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_I2C1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_I2C1_Peripheral_Access_Layer LPCG_LPCG_I2C1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_I2C1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_I2C1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_I2C1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_I2C1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_I2C1_Register_Masks LPCG_LPCG_I2C1 Register Masks * @{ */ /*! @name LPCG_LPCG_I2C1_0 - na */ /*! @{ */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_div_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_div_clk_HWEN_SHIFT (0U) /*! i2c1_lpi2c_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_div_clk_HWEN_MASK) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN_SHIFT (1U) /*! i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN_MASK) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_i2c1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_2_2_MASK) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP_MASK (0x8U) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP_SHIFT (3U) /*! i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP_MASK) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_i2c1_0_reserved_4_15 - reserved */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_4_15_MASK) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_s_HWEN_SHIFT (16U) /*! i2c1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN_SHIFT (17U) /*! i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_i2c1_0_reserved_18_18 - reserved */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_18_18_MASK) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP_SHIFT (19U) /*! i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_i2c1_0_reserved_20_31 - reserved */ #define LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_I2C1_LPCG_LPCG_I2C1_0_LPCG_lpcg_i2c1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_I2C1_Register_Masks */ /* LPCG_LPCG_I2C1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_I2C1_IPG_CLK base address */ #define ADMA__LPCG_I2C1_IPG_CLK_BASE (0x5AC10000u) /** Peripheral ADMA__LPCG_I2C1_IPG_CLK base pointer */ #define ADMA__LPCG_I2C1_IPG_CLK ((LPCG_LPCG_I2C1_Type *)ADMA__LPCG_I2C1_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_I2C1 peripheral base addresses */ #define LPCG_LPCG_I2C1_BASE_ADDRS { ADMA__LPCG_I2C1_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_I2C1 peripheral base pointers */ #define LPCG_LPCG_I2C1_BASE_PTRS { ADMA__LPCG_I2C1_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_I2C1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_I2C2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_I2C2_Peripheral_Access_Layer LPCG_LPCG_I2C2 Peripheral Access Layer * @{ */ /** LPCG_LPCG_I2C2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_I2C2_0; /**< na, offset: 0x0 */ } LPCG_LPCG_I2C2_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_I2C2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_I2C2_Register_Masks LPCG_LPCG_I2C2 Register Masks * @{ */ /*! @name LPCG_LPCG_I2C2_0 - na */ /*! @{ */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_div_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_div_clk_HWEN_SHIFT (0U) /*! i2c2_lpi2c_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_div_clk_HWEN_MASK) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN_SHIFT (1U) /*! i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN_MASK) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_i2c2_0_reserved_2_2 - reserved */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_2_2_MASK) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP_MASK (0x8U) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP_SHIFT (3U) /*! i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP_MASK) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_i2c2_0_reserved_4_15 - reserved */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_4_15_MASK) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_s_HWEN_SHIFT (16U) /*! i2c2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN_SHIFT (17U) /*! i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_i2c2_0_reserved_18_18 - reserved */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_18_18_MASK) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP_SHIFT (19U) /*! i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_i2c2_0_reserved_20_31 - reserved */ #define LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_I2C2_LPCG_LPCG_I2C2_0_LPCG_lpcg_i2c2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_I2C2_Register_Masks */ /* LPCG_LPCG_I2C2 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_I2C2_IPG_CLK base address */ #define ADMA__LPCG_I2C2_IPG_CLK_BASE (0x5AC20000u) /** Peripheral ADMA__LPCG_I2C2_IPG_CLK base pointer */ #define ADMA__LPCG_I2C2_IPG_CLK ((LPCG_LPCG_I2C2_Type *)ADMA__LPCG_I2C2_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_I2C2 peripheral base addresses */ #define LPCG_LPCG_I2C2_BASE_ADDRS { ADMA__LPCG_I2C2_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_I2C2 peripheral base pointers */ #define LPCG_LPCG_I2C2_BASE_PTRS { ADMA__LPCG_I2C2_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_I2C2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_I2C3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_I2C3_Peripheral_Access_Layer LPCG_LPCG_I2C3 Peripheral Access Layer * @{ */ /** LPCG_LPCG_I2C3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_I2C3_0; /**< na, offset: 0x0 */ } LPCG_LPCG_I2C3_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_I2C3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_I2C3_Register_Masks LPCG_LPCG_I2C3 Register Masks * @{ */ /*! @name LPCG_LPCG_I2C3_0 - na */ /*! @{ */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_div_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_div_clk_HWEN_SHIFT (0U) /*! i2c3_lpi2c_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_div_clk_HWEN_MASK) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN_SHIFT (1U) /*! i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN_MASK) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_i2c3_0_reserved_2_2 - reserved */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_2_2_MASK) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP_MASK (0x8U) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP_SHIFT (3U) /*! i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP_MASK) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_i2c3_0_reserved_4_15 - reserved */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_4_15_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_4_15_MASK) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_s_HWEN_SHIFT (16U) /*! i2c3_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN_SHIFT (17U) /*! i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_i2c3_0_reserved_18_18 - reserved */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_18_18_MASK) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP_SHIFT (19U) /*! i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_i2c3_0_reserved_20_31 - reserved */ #define LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_I2C3_LPCG_LPCG_I2C3_0_LPCG_lpcg_i2c3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_I2C3_Register_Masks */ /* LPCG_LPCG_I2C3 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_I2C3_IPG_CLK base address */ #define ADMA__LPCG_I2C3_IPG_CLK_BASE (0x5AC30000u) /** Peripheral ADMA__LPCG_I2C3_IPG_CLK base pointer */ #define ADMA__LPCG_I2C3_IPG_CLK ((LPCG_LPCG_I2C3_Type *)ADMA__LPCG_I2C3_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_I2C3 peripheral base addresses */ #define LPCG_LPCG_I2C3_BASE_ADDRS { ADMA__LPCG_I2C3_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_I2C3 peripheral base pointers */ #define LPCG_LPCG_I2C3_BASE_PTRS { ADMA__LPCG_I2C3_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_I2C3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_IRQ Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_IRQ_Peripheral_Access_Layer LPCG_LPCG_IRQ Peripheral Access Layer * @{ */ /** LPCG_LPCG_IRQ - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_IRQ_0; /**< na, offset: 0x0 */ } LPCG_LPCG_IRQ_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_IRQ Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_IRQ_Register_Masks LPCG_LPCG_IRQ Register Masks * @{ */ /*! @name LPCG_LPCG_IRQ_0 - na */ /*! @{ */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_irq_0_reserved_0_0 - reserved */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_0_0_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_0_0_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_SWEN_MASK (0x2U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_SWEN_SHIFT (1U) /*! adb_m0_aclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_SWEN_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_SWEN_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_irq_0_reserved_2_2 - reserved */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_2_2_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_2_2_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_STOP_MASK (0x8U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_STOP_SHIFT (3U) /*! adb_m0_aclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_STOP_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_m0_aclk_STOP_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_4_4_MASK (0x10U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_4_4_SHIFT (4U) /*! LPCG_lpcg_irq_0_reserved_4_4 - reserved */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_4_4_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_4_4_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_SWEN_MASK (0x20U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_SWEN_SHIFT (5U) /*! adb_s0_aclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_SWEN_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_SWEN_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_6_6_MASK (0x40U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_6_6_SHIFT (6U) /*! LPCG_lpcg_irq_0_reserved_6_6 - reserved */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_6_6_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_6_6_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_STOP_MASK (0x80U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_STOP_SHIFT (7U) /*! adb_s0_aclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_STOP_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_adb_s0_aclk_STOP_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_8_15_MASK (0xFF00U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_8_15_SHIFT (8U) /*! LPCG_lpcg_irq_0_reserved_8_15 - reserved */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_8_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_8_15_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_8_15_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_HWEN_MASK (0x10000U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_HWEN_SHIFT (16U) /*! irqstr_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_HWEN_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_HWEN_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_SWEN_SHIFT (17U) /*! irqstr_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_SWEN_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_irq_0_reserved_18_18 - reserved */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_18_18_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_18_18_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_STOP_SHIFT (19U) /*! irqstr_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_irqstr_ipg_clk_STOP_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_20_20_MASK (0x100000U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_20_20_SHIFT (20U) /*! LPCG_lpcg_irq_0_reserved_20_20 - reserved */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_20_20_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_20_20_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_SWEN_MASK (0x200000U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_SWEN_SHIFT (21U) /*! gic_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_SWEN_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_SWEN_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_22_22_MASK (0x400000U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_22_22_SHIFT (22U) /*! LPCG_lpcg_irq_0_reserved_22_22 - reserved */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_22_22_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_22_22_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_STOP_MASK (0x800000U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_STOP_SHIFT (23U) /*! gic_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_STOP_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_gic_clk_STOP_MASK) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_24_31_MASK (0xFF000000U) #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_24_31_SHIFT (24U) /*! LPCG_lpcg_irq_0_reserved_24_31 - reserved */ #define LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_24_31_SHIFT)) & LPCG_LPCG_IRQ_LPCG_LPCG_IRQ_0_LPCG_lpcg_irq_0_reserved_24_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_IRQ_Register_Masks */ /* LPCG_LPCG_IRQ - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_GIC_CLK base address */ #define ADMA__LPCG_GIC_CLK_BASE (0xD10F0000u) /** Peripheral ADMA__LPCG_GIC_CLK base pointer */ #define ADMA__LPCG_GIC_CLK ((LPCG_LPCG_IRQ_Type *)ADMA__LPCG_GIC_CLK_BASE) /** Array initializer of LPCG_LPCG_IRQ peripheral base addresses */ #define LPCG_LPCG_IRQ_BASE_ADDRS { ADMA__LPCG_GIC_CLK_BASE } /** Array initializer of LPCG_LPCG_IRQ peripheral base pointers */ #define LPCG_LPCG_IRQ_BASE_PTRS { ADMA__LPCG_GIC_CLK } /*! * @} */ /* end of group LPCG_LPCG_IRQ_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_LCDIF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_LCDIF_Peripheral_Access_Layer LPCG_LPCG_LCDIF Peripheral Access Layer * @{ */ /** LPCG_LPCG_LCDIF - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_LCDIF_0; /**< na, offset: 0x0 */ } LPCG_LPCG_LCDIF_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_LCDIF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_LCDIF_Register_Masks LPCG_LPCG_LCDIF Register Masks * @{ */ /*! @name LPCG_LPCG_LCDIF_0 - na */ /*! @{ */ #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_lcdif_0_reserved_0_0 - reserved */ #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_0_0_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_0_0_MASK) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_SWEN_SHIFT (1U) /*! lcdif_pix_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_SWEN_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_SWEN_MASK) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_lcdif_0_reserved_2_2 - reserved */ #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_2_2_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_2_2_MASK) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_STOP_MASK (0x8U) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_STOP_SHIFT (3U) /*! lcdif_pix_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_STOP_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_pix_clk_STOP_MASK) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_4_16_MASK (0x1FFF0U) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_4_16_SHIFT (4U) /*! LPCG_lpcg_lcdif_0_reserved_4_16 - reserved */ #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_4_16_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_4_16_MASK) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_SWEN_SHIFT (17U) /*! lcdif_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_SWEN_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_SWEN_MASK) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_lcdif_0_reserved_18_18 - reserved */ #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_18_18_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_18_18_MASK) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_STOP_SHIFT (19U) /*! lcdif_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_STOP_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_lcdif_apb_clk_STOP_MASK) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_lcdif_0_reserved_20_31 - reserved */ #define LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_20_31_SHIFT)) & LPCG_LPCG_LCDIF_LPCG_LPCG_LCDIF_0_LPCG_lpcg_lcdif_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_LCDIF_Register_Masks */ /* LPCG_LPCG_LCDIF - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_LCDIF_APB_CLK base address */ #define ADMA__LPCG_LCDIF_APB_CLK_BASE (0x5A580000u) /** Peripheral ADMA__LPCG_LCDIF_APB_CLK base pointer */ #define ADMA__LPCG_LCDIF_APB_CLK ((LPCG_LPCG_LCDIF_Type *)ADMA__LPCG_LCDIF_APB_CLK_BASE) /** Array initializer of LPCG_LPCG_LCDIF peripheral base addresses */ #define LPCG_LPCG_LCDIF_BASE_ADDRS { ADMA__LPCG_LCDIF_APB_CLK_BASE } /** Array initializer of LPCG_LPCG_LCDIF peripheral base pointers */ #define LPCG_LPCG_LCDIF_BASE_PTRS { ADMA__LPCG_LCDIF_APB_CLK } /*! * @} */ /* end of group LPCG_LPCG_LCDIF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_LCDIF_MUX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_LCDIF_MUX_Peripheral_Access_Layer LPCG_LPCG_LCDIF_MUX Peripheral Access Layer * @{ */ /** LPCG_LPCG_LCDIF_MUX - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_LCDIF_MUX_0; /**< na, offset: 0x0 */ } LPCG_LPCG_LCDIF_MUX_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_LCDIF_MUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_LCDIF_MUX_Register_Masks LPCG_LPCG_LCDIF_MUX Register Masks * @{ */ /*! @name LPCG_LPCG_LCDIF_MUX_0 - na */ /*! @{ */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_lcdif_mux_0_reserved_0_0 - reserved */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_0_0_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_0_0_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_SWEN_SHIFT (1U) /*! pixel_link_slv_ingress_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_SWEN_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_SWEN_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_lcdif_mux_0_reserved_2_2 - reserved */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_2_2_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_2_2_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_STOP_MASK (0x8U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_STOP_SHIFT (3U) /*! pixel_link_slv_ingress_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_STOP_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_pixel_link_slv_ingress_clk_STOP_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_4_4_MASK (0x10U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_4_4_SHIFT (4U) /*! LPCG_lpcg_lcdif_mux_0_reserved_4_4 - reserved */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_4_4_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_4_4_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_SWEN_MASK (0x20U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_SWEN_SHIFT (5U) /*! lcdif_mux_pixel_link_slv_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_SWEN_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_SWEN_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_6_6_MASK (0x40U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_6_6_SHIFT (6U) /*! LPCG_lpcg_lcdif_mux_0_reserved_6_6 - reserved */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_6_6_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_6_6_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_STOP_MASK (0x80U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_STOP_SHIFT (7U) /*! lcdif_mux_pixel_link_slv_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_STOP_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_pixel_link_slv_clk_STOP_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_8_16_MASK (0x1FF00U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_8_16_SHIFT (8U) /*! LPCG_lpcg_lcdif_mux_0_reserved_8_16 - reserved */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_8_16_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_8_16_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_SWEN_SHIFT (17U) /*! lcdif_mux_regs_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_SWEN_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_lcdif_mux_0_reserved_18_18 - reserved */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_18_18_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_18_18_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_STOP_SHIFT (19U) /*! lcdif_mux_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_lcdif_mux_regs_ipg_clk_STOP_MASK) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_lcdif_mux_0_reserved_20_31 - reserved */ #define LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_20_31_SHIFT)) & LPCG_LPCG_LCDIF_MUX_LPCG_LPCG_LCDIF_MUX_0_LPCG_lpcg_lcdif_mux_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_LCDIF_MUX_Register_Masks */ /* LPCG_LPCG_LCDIF_MUX - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK base address */ #define ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK_BASE (0x5A570000u) /** Peripheral ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK base pointer */ #define ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK ((LPCG_LPCG_LCDIF_MUX_Type *)ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK_BASE) /** Array initializer of LPCG_LPCG_LCDIF_MUX peripheral base addresses */ #define LPCG_LPCG_LCDIF_MUX_BASE_ADDRS { ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK_BASE } /** Array initializer of LPCG_LPCG_LCDIF_MUX peripheral base pointers */ #define LPCG_LPCG_LCDIF_MUX_BASE_PTRS { ADMA__LPCG_PIXEL_LINK_SLV_INGRESS_CLK } /*! * @} */ /* end of group LPCG_LPCG_LCDIF_MUX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_MCLKOUT0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_MCLKOUT0_Peripheral_Access_Layer LPCG_LPCG_MCLKOUT0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_MCLKOUT0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_MCLKOUT0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_MCLKOUT0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_MCLKOUT0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_MCLKOUT0_Register_Masks LPCG_LPCG_MCLKOUT0 Register Masks * @{ */ /*! @name LPCG_LPCG_MCLKOUT0_0 - na */ /*! @{ */ #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_mclkout0_0_reserved_0_0 - reserved */ #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_MASK) #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_MASK (0x2U) #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_SHIFT (1U) /*! mclkout0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_SHIFT)) & LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_MASK) #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_mclkout0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_MASK) #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_MASK (0x8U) #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_SHIFT (3U) /*! mclkout0_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_SHIFT)) & LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_MASK) #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_mclkout0_0_reserved_4_31 - reserved */ #define LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_SHIFT)) & LPCG_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_MCLKOUT0_Register_Masks */ /* LPCG_LPCG_MCLKOUT0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_MCLKOUT0 base address */ #define ADMA__LPCG_MCLKOUT0_BASE (0x59D50000u) /** Peripheral ADMA__LPCG_MCLKOUT0 base pointer */ #define ADMA__LPCG_MCLKOUT0 ((LPCG_LPCG_MCLKOUT0_Type *)ADMA__LPCG_MCLKOUT0_BASE) /** Array initializer of LPCG_LPCG_MCLKOUT0 peripheral base addresses */ #define LPCG_LPCG_MCLKOUT0_BASE_ADDRS { ADMA__LPCG_MCLKOUT0_BASE } /** Array initializer of LPCG_LPCG_MCLKOUT0 peripheral base pointers */ #define LPCG_LPCG_MCLKOUT0_BASE_PTRS { ADMA__LPCG_MCLKOUT0 } /*! * @} */ /* end of group LPCG_LPCG_MCLKOUT0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_MCLKOUT1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_MCLKOUT1_Peripheral_Access_Layer LPCG_LPCG_MCLKOUT1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_MCLKOUT1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_MCLKOUT1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_MCLKOUT1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_MCLKOUT1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_MCLKOUT1_Register_Masks LPCG_LPCG_MCLKOUT1 Register Masks * @{ */ /*! @name LPCG_LPCG_MCLKOUT1_0 - na */ /*! @{ */ #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_mclkout1_0_reserved_0_0 - reserved */ #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_MASK) #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_MASK (0x2U) #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_SHIFT (1U) /*! mclkout1_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_SHIFT)) & LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_MASK) #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_mclkout1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_MASK) #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_MASK (0x8U) #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_SHIFT (3U) /*! mclkout1_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_SHIFT)) & LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_MASK) #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_SHIFT (4U) /*! LPCG_lpcg_mclkout1_0_reserved_4_31 - reserved */ #define LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_SHIFT)) & LPCG_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_MCLKOUT1_Register_Masks */ /* LPCG_LPCG_MCLKOUT1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_MCLKOUT1 base address */ #define ADMA__LPCG_MCLKOUT1_BASE (0x59D60000u) /** Peripheral ADMA__LPCG_MCLKOUT1 base pointer */ #define ADMA__LPCG_MCLKOUT1 ((LPCG_LPCG_MCLKOUT1_Type *)ADMA__LPCG_MCLKOUT1_BASE) /** Array initializer of LPCG_LPCG_MCLKOUT1 peripheral base addresses */ #define LPCG_LPCG_MCLKOUT1_BASE_ADDRS { ADMA__LPCG_MCLKOUT1_BASE } /** Array initializer of LPCG_LPCG_MCLKOUT1 peripheral base pointers */ #define LPCG_LPCG_MCLKOUT1_BASE_PTRS { ADMA__LPCG_MCLKOUT1 } /*! * @} */ /* end of group LPCG_LPCG_MCLKOUT1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_MQS_REGS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_MQS_REGS_Peripheral_Access_Layer LPCG_LPCG_MQS_REGS Peripheral Access Layer * @{ */ /** LPCG_LPCG_MQS_REGS - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_MQS_REGS_0; /**< na, offset: 0x0 */ } LPCG_LPCG_MQS_REGS_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_MQS_REGS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_MQS_REGS_Register_Masks LPCG_LPCG_MQS_REGS Register Masks * @{ */ /*! @name LPCG_LPCG_MQS_REGS_0 - na */ /*! @{ */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_mqs_regs_0_reserved_0_0 - reserved */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_0_0_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_0_0_MASK) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_MASK (0x2U) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_SHIFT (1U) /*! mqs_hmclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_MASK) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_mqs_regs_0_reserved_2_2 - reserved */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_MASK) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_MASK (0x8U) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_SHIFT (3U) /*! mqs_hmclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_MASK) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_mqs_regs_0_reserved_4_15 - reserved */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_15_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_15_MASK) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_MASK (0x10000U) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_SHIFT (16U) /*! mqs_regs_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_MASK) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_SHIFT (17U) /*! mqs_regs_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_MASK) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_mqs_regs_0_reserved_18_18 - reserved */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_MASK) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_SHIFT (19U) /*! mqs_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_MASK) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_mqs_regs_0_reserved_20_31 - reserved */ #define LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_SHIFT)) & LPCG_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_MQS_REGS_Register_Masks */ /* LPCG_LPCG_MQS_REGS - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_MQS_HMCLK base address */ #define ADMA__LPCG_MQS_HMCLK_BASE (0x59C50000u) /** Peripheral ADMA__LPCG_MQS_HMCLK base pointer */ #define ADMA__LPCG_MQS_HMCLK ((LPCG_LPCG_MQS_REGS_Type *)ADMA__LPCG_MQS_HMCLK_BASE) /** Array initializer of LPCG_LPCG_MQS_REGS peripheral base addresses */ #define LPCG_LPCG_MQS_REGS_BASE_ADDRS { ADMA__LPCG_MQS_HMCLK_BASE } /** Array initializer of LPCG_LPCG_MQS_REGS peripheral base pointers */ #define LPCG_LPCG_MQS_REGS_BASE_PTRS { ADMA__LPCG_MQS_HMCLK } /*! * @} */ /* end of group LPCG_LPCG_MQS_REGS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_OCRAM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_OCRAM_Peripheral_Access_Layer LPCG_LPCG_OCRAM Peripheral Access Layer * @{ */ /** LPCG_LPCG_OCRAM - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_OCRAM_0; /**< na, offset: 0x0 */ } LPCG_LPCG_OCRAM_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_OCRAM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_OCRAM_Register_Masks LPCG_LPCG_OCRAM Register Masks * @{ */ /*! @name LPCG_LPCG_OCRAM_0 - na */ /*! @{ */ #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_0_16_MASK (0x1FFFFU) #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_0_16_SHIFT (0U) /*! LPCG_lpcg_ocram_0_reserved_0_16 - reserved */ #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_0_16_SHIFT)) & LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_0_16_MASK) #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN_MASK (0x20000U) #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN_SHIFT (17U) /*! ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN_SHIFT)) & LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_AND_ocram_mem_clk_SWEN_MASK) #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_ocram_0_reserved_18_18 - reserved */ #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_18_18_SHIFT)) & LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_18_18_MASK) #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP_MASK (0x80000U) #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP_SHIFT (19U) /*! ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP_SHIFT)) & LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_AND_ocram_mem_clk_STOP_MASK) #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_ocram_0_reserved_20_31 - reserved */ #define LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_20_31_SHIFT)) & LPCG_LPCG_OCRAM_LPCG_LPCG_OCRAM_0_LPCG_lpcg_ocram_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_OCRAM_Register_Masks */ /* LPCG_LPCG_OCRAM - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_OCRAM_MEM_CLK base address */ #define ADMA__LPCG_OCRAM_MEM_CLK_BASE (0x59590000u) /** Peripheral ADMA__LPCG_OCRAM_MEM_CLK base pointer */ #define ADMA__LPCG_OCRAM_MEM_CLK ((LPCG_LPCG_OCRAM_Type *)ADMA__LPCG_OCRAM_MEM_CLK_BASE) /** Array initializer of LPCG_LPCG_OCRAM peripheral base addresses */ #define LPCG_LPCG_OCRAM_BASE_ADDRS { ADMA__LPCG_OCRAM_MEM_CLK_BASE } /** Array initializer of LPCG_LPCG_OCRAM peripheral base pointers */ #define LPCG_LPCG_OCRAM_BASE_PTRS { ADMA__LPCG_OCRAM_MEM_CLK } /*! * @} */ /* end of group LPCG_LPCG_OCRAM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_PWM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_PWM_Peripheral_Access_Layer LPCG_LPCG_PWM Peripheral Access Layer * @{ */ /** LPCG_LPCG_PWM - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_PWM_0; /**< na, offset: 0x0 */ } LPCG_LPCG_PWM_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_PWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_PWM_Register_Masks LPCG_LPCG_PWM Register Masks * @{ */ /*! @name LPCG_LPCG_PWM_0 - na */ /*! @{ */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_pwm_0_reserved_0_0 - reserved */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_0_0_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_0_0_MASK) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U) /*! pwm_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_SWEN_MASK) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_pwm_0_reserved_2_2 - reserved */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_2_2_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_2_2_MASK) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_STOP_MASK (0x8U) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_STOP_SHIFT (3U) /*! pwm_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_STOP_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_highfreq_STOP_MASK) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_pwm_0_reserved_4_15 - reserved */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_4_15_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_4_15_MASK) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_pwm_0_reserved_18_18 - reserved */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_18_18_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_18_18_MASK) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U) /*! pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_pwm_0_reserved_20_31 - reserved */ #define LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_20_31_SHIFT)) & LPCG_LPCG_PWM_LPCG_LPCG_PWM_0_LPCG_lpcg_pwm_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_PWM_Register_Masks */ /* LPCG_LPCG_PWM - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_PWM_IPG_CLK base address */ #define ADMA__LPCG_PWM_IPG_CLK_BASE (0x5A590000u) /** Peripheral ADMA__LPCG_PWM_IPG_CLK base pointer */ #define ADMA__LPCG_PWM_IPG_CLK ((LPCG_LPCG_PWM_Type *)ADMA__LPCG_PWM_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_PWM peripheral base addresses */ #define LPCG_LPCG_PWM_BASE_ADDRS { ADMA__LPCG_PWM_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_PWM peripheral base pointers */ #define LPCG_LPCG_PWM_BASE_PTRS { ADMA__LPCG_PWM_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_PWM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI0_Peripheral_Access_Layer LPCG_LPCG_SAI0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SAI0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SAI0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI0_Register_Masks LPCG_LPCG_SAI0 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI0_0 - na */ /*! @{ */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_sai0_0_reserved_0_0 - reserved */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_MASK) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U) /*! sai0_ipg_clk_sai_mclk_1_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_MASK) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_sai0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_MASK) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_MASK (0x8U) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_SHIFT (3U) /*! sai0_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_MASK) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_sai0_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_15_MASK) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_SHIFT (16U) /*! sai0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN_SHIFT (17U) /*! sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_sai0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_MASK) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP_SHIFT (19U) /*! sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_sai0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SAI0_Register_Masks */ /* LPCG_LPCG_SAI0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SAI0_IPG_CLK base address */ #define ADMA__LPCG_SAI0_IPG_CLK_BASE (0x59440000u) /** Peripheral ADMA__LPCG_SAI0_IPG_CLK base pointer */ #define ADMA__LPCG_SAI0_IPG_CLK ((LPCG_LPCG_SAI0_Type *)ADMA__LPCG_SAI0_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_SAI0 peripheral base addresses */ #define LPCG_LPCG_SAI0_BASE_ADDRS { ADMA__LPCG_SAI0_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_SAI0 peripheral base pointers */ #define LPCG_LPCG_SAI0_BASE_PTRS { ADMA__LPCG_SAI0_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_SAI0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI1_Peripheral_Access_Layer LPCG_LPCG_SAI1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SAI1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SAI1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI1_Register_Masks LPCG_LPCG_SAI1 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI1_0 - na */ /*! @{ */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_sai1_0_reserved_0_0 - reserved */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_MASK) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U) /*! sai1_ipg_clk_sai_mclk_1_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_MASK) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_sai1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_MASK) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_MASK (0x8U) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_SHIFT (3U) /*! sai1_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_MASK) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_sai1_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_15_MASK) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_SHIFT (16U) /*! sai1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN_SHIFT (17U) /*! sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_sai1_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_MASK) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP_SHIFT (19U) /*! sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_sai1_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SAI1_Register_Masks */ /* LPCG_LPCG_SAI1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SAI1_IPG_CLK base address */ #define ADMA__LPCG_SAI1_IPG_CLK_BASE (0x59450000u) /** Peripheral ADMA__LPCG_SAI1_IPG_CLK base pointer */ #define ADMA__LPCG_SAI1_IPG_CLK ((LPCG_LPCG_SAI1_Type *)ADMA__LPCG_SAI1_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_SAI1 peripheral base addresses */ #define LPCG_LPCG_SAI1_BASE_ADDRS { ADMA__LPCG_SAI1_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_SAI1 peripheral base pointers */ #define LPCG_LPCG_SAI1_BASE_PTRS { ADMA__LPCG_SAI1_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_SAI1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI2_Peripheral_Access_Layer LPCG_LPCG_SAI2 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SAI2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI2_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SAI2_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI2_Register_Masks LPCG_LPCG_SAI2 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI2_0 - na */ /*! @{ */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_sai2_0_reserved_0_0 - reserved */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_MASK) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U) /*! sai2_ipg_clk_sai_mclk_1_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_MASK) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_sai2_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_MASK) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_MASK (0x8U) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_SHIFT (3U) /*! sai2_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_MASK) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_sai2_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_15_MASK) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_SHIFT (16U) /*! sai2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN_SHIFT (17U) /*! sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_sai2_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_MASK) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP_SHIFT (19U) /*! sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_sai2_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SAI2_Register_Masks */ /* LPCG_LPCG_SAI2 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SAI2_IPG_CLK base address */ #define ADMA__LPCG_SAI2_IPG_CLK_BASE (0x59460000u) /** Peripheral ADMA__LPCG_SAI2_IPG_CLK base pointer */ #define ADMA__LPCG_SAI2_IPG_CLK ((LPCG_LPCG_SAI2_Type *)ADMA__LPCG_SAI2_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_SAI2 peripheral base addresses */ #define LPCG_LPCG_SAI2_BASE_ADDRS { ADMA__LPCG_SAI2_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_SAI2 peripheral base pointers */ #define LPCG_LPCG_SAI2_BASE_PTRS { ADMA__LPCG_SAI2_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_SAI2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI3_Peripheral_Access_Layer LPCG_LPCG_SAI3 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SAI3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI3_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SAI3_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI3_Register_Masks LPCG_LPCG_SAI3 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI3_0 - na */ /*! @{ */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_sai3_0_reserved_0_0 - reserved */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_MASK) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U) /*! sai3_ipg_clk_sai_mclk_1_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_MASK) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_sai3_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_MASK) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_MASK (0x8U) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_SHIFT (3U) /*! sai3_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_MASK) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_sai3_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_15_MASK) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_SHIFT (16U) /*! sai3_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN_SHIFT (17U) /*! sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_sai3_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_MASK) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP_SHIFT (19U) /*! sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_sai3_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SAI3_Register_Masks */ /* LPCG_LPCG_SAI3 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SAI3_IPG_CLK base address */ #define ADMA__LPCG_SAI3_IPG_CLK_BASE (0x59470000u) /** Peripheral ADMA__LPCG_SAI3_IPG_CLK base pointer */ #define ADMA__LPCG_SAI3_IPG_CLK ((LPCG_LPCG_SAI3_Type *)ADMA__LPCG_SAI3_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_SAI3 peripheral base addresses */ #define LPCG_LPCG_SAI3_BASE_ADDRS { ADMA__LPCG_SAI3_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_SAI3 peripheral base pointers */ #define LPCG_LPCG_SAI3_BASE_PTRS { ADMA__LPCG_SAI3_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_SAI3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI4_Peripheral_Access_Layer LPCG_LPCG_SAI4 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SAI4 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI4_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SAI4_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI4_Register_Masks LPCG_LPCG_SAI4 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI4_0 - na */ /*! @{ */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_sai4_0_reserved_0_0 - reserved */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_0_0_MASK) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U) /*! sai4_ipg_clk_sai_mclk_1_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_SWEN_MASK) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_sai4_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_2_2_MASK) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_STOP_MASK (0x8U) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_STOP_SHIFT (3U) /*! sai4_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_sai_mclk_1_STOP_MASK) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_sai4_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_4_15_MASK) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_s_HWEN_SHIFT (16U) /*! sai4_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN_SHIFT (17U) /*! sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_SWEN_AND_sai4_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_sai4_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_18_18_MASK) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP_SHIFT (19U) /*! sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_sai4_ipg_clk_STOP_AND_sai4_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_sai4_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI4_LPCG_LPCG_SAI4_0_LPCG_lpcg_sai4_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SAI4_Register_Masks */ /* LPCG_LPCG_SAI4 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SAI4_IPG_CLK base address */ #define ADMA__LPCG_SAI4_IPG_CLK_BASE (0x59C20000u) /** Peripheral ADMA__LPCG_SAI4_IPG_CLK base pointer */ #define ADMA__LPCG_SAI4_IPG_CLK ((LPCG_LPCG_SAI4_Type *)ADMA__LPCG_SAI4_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_SAI4 peripheral base addresses */ #define LPCG_LPCG_SAI4_BASE_ADDRS { ADMA__LPCG_SAI4_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_SAI4 peripheral base pointers */ #define LPCG_LPCG_SAI4_BASE_PTRS { ADMA__LPCG_SAI4_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_SAI4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI5_Peripheral_Access_Layer LPCG_LPCG_SAI5 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SAI5 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SAI5_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SAI5_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SAI5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SAI5_Register_Masks LPCG_LPCG_SAI5 Register Masks * @{ */ /*! @name LPCG_LPCG_SAI5_0 - na */ /*! @{ */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_sai5_0_reserved_0_0 - reserved */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_0_0_MASK) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_SWEN_MASK (0x2U) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_SWEN_SHIFT (1U) /*! sai5_ipg_clk_sai_mclk_1_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_SWEN_MASK) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_sai5_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_2_2_MASK) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_STOP_MASK (0x8U) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_STOP_SHIFT (3U) /*! sai5_ipg_clk_sai_mclk_1_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_STOP_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_sai_mclk_1_STOP_MASK) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_sai5_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_4_15_MASK) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_s_HWEN_SHIFT (16U) /*! sai5_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN_SHIFT (17U) /*! sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_SWEN_AND_sai5_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_sai5_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_18_18_MASK) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP_SHIFT (19U) /*! sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_sai5_ipg_clk_STOP_AND_sai5_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_sai5_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SAI5_LPCG_LPCG_SAI5_0_LPCG_lpcg_sai5_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SAI5_Register_Masks */ /* LPCG_LPCG_SAI5 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SAI5_IPG_CLK base address */ #define ADMA__LPCG_SAI5_IPG_CLK_BASE (0x59C30000u) /** Peripheral ADMA__LPCG_SAI5_IPG_CLK base pointer */ #define ADMA__LPCG_SAI5_IPG_CLK ((LPCG_LPCG_SAI5_Type *)ADMA__LPCG_SAI5_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_SAI5 peripheral base addresses */ #define LPCG_LPCG_SAI5_BASE_ADDRS { ADMA__LPCG_SAI5_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_SAI5 peripheral base pointers */ #define LPCG_LPCG_SAI5_BASE_PTRS { ADMA__LPCG_SAI5_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_SAI5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SPDIF0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SPDIF0_Peripheral_Access_Layer LPCG_LPCG_SPDIF0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SPDIF0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SPDIF0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SPDIF0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SPDIF0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SPDIF0_Register_Masks LPCG_LPCG_SPDIF0 Register Masks * @{ */ /*! @name LPCG_LPCG_SPDIF0_0 - na */ /*! @{ */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_0_0_MASK (0x1U) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_0_0_SHIFT (0U) /*! LPCG_lpcg_spdif0_0_reserved_0_0 - reserved */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_0_0_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_0_0_MASK) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_SHIFT (1U) /*! spdif0_tx_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_MASK) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_spdif0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_MASK) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_MASK (0x8U) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_SHIFT (3U) /*! spdif0_tx_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_MASK) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_spdif0_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_15_MASK) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_SHIFT (16U) /*! spdif0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN_MASK (0x20000U) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN_SHIFT (17U) /*! spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN_MASK) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_spdif0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_MASK) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP_MASK (0x80000U) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP_SHIFT (19U) /*! spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP_MASK) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_spdif0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SPDIF0_Register_Masks */ /* LPCG_LPCG_SPDIF0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SPDIF0_GCLKW_T0 base address */ #define ADMA__LPCG_SPDIF0_GCLKW_T0_BASE (0x59420000u) /** Peripheral ADMA__LPCG_SPDIF0_GCLKW_T0 base pointer */ #define ADMA__LPCG_SPDIF0_GCLKW_T0 ((LPCG_LPCG_SPDIF0_Type *)ADMA__LPCG_SPDIF0_GCLKW_T0_BASE) /** Array initializer of LPCG_LPCG_SPDIF0 peripheral base addresses */ #define LPCG_LPCG_SPDIF0_BASE_ADDRS { ADMA__LPCG_SPDIF0_GCLKW_T0_BASE } /** Array initializer of LPCG_LPCG_SPDIF0 peripheral base pointers */ #define LPCG_LPCG_SPDIF0_BASE_PTRS { ADMA__LPCG_SPDIF0_GCLKW_T0 } /*! * @} */ /* end of group LPCG_LPCG_SPDIF0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SPI0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SPI0_Peripheral_Access_Layer LPCG_LPCG_SPI0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SPI0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SPI0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SPI0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SPI0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SPI0_Register_Masks LPCG_LPCG_SPI0 Register Masks * @{ */ /*! @name LPCG_LPCG_SPI0_0 - na */ /*! @{ */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_div_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_div_clk_HWEN_SHIFT (0U) /*! spi0_lpspi_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_div_clk_HWEN_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_div_clk_HWEN_MASK) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN_SHIFT (1U) /*! spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN_MASK) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_spi0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_2_2_MASK) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP_MASK (0x8U) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP_SHIFT (3U) /*! spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP_MASK) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_spi0_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_4_15_MASK) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_s_HWEN_SHIFT (16U) /*! spi0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN_SHIFT (17U) /*! spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_spi0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_18_18_MASK) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP_SHIFT (19U) /*! spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_spi0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SPI0_LPCG_LPCG_SPI0_0_LPCG_lpcg_spi0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SPI0_Register_Masks */ /* LPCG_LPCG_SPI0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SPI0_IPG_CLK base address */ #define ADMA__LPCG_SPI0_IPG_CLK_BASE (0x5A400000u) /** Peripheral ADMA__LPCG_SPI0_IPG_CLK base pointer */ #define ADMA__LPCG_SPI0_IPG_CLK ((LPCG_LPCG_SPI0_Type *)ADMA__LPCG_SPI0_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_SPI0 peripheral base addresses */ #define LPCG_LPCG_SPI0_BASE_ADDRS { ADMA__LPCG_SPI0_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_SPI0 peripheral base pointers */ #define LPCG_LPCG_SPI0_BASE_PTRS { ADMA__LPCG_SPI0_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_SPI0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SPI1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SPI1_Peripheral_Access_Layer LPCG_LPCG_SPI1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SPI1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SPI1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SPI1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SPI1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SPI1_Register_Masks LPCG_LPCG_SPI1 Register Masks * @{ */ /*! @name LPCG_LPCG_SPI1_0 - na */ /*! @{ */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_div_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_div_clk_HWEN_SHIFT (0U) /*! spi1_lpspi_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_div_clk_HWEN_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_div_clk_HWEN_MASK) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN_SHIFT (1U) /*! spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN_MASK) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_spi1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_2_2_MASK) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP_MASK (0x8U) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP_SHIFT (3U) /*! spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP_MASK) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_spi1_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_4_15_MASK) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_s_HWEN_SHIFT (16U) /*! spi1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN_SHIFT (17U) /*! spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_spi1_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_18_18_MASK) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP_SHIFT (19U) /*! spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_spi1_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SPI1_LPCG_LPCG_SPI1_0_LPCG_lpcg_spi1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SPI1_Register_Masks */ /* LPCG_LPCG_SPI1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SPI1_IPG_CLK base address */ #define ADMA__LPCG_SPI1_IPG_CLK_BASE (0x5A410000u) /** Peripheral ADMA__LPCG_SPI1_IPG_CLK base pointer */ #define ADMA__LPCG_SPI1_IPG_CLK ((LPCG_LPCG_SPI1_Type *)ADMA__LPCG_SPI1_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_SPI1 peripheral base addresses */ #define LPCG_LPCG_SPI1_BASE_ADDRS { ADMA__LPCG_SPI1_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_SPI1 peripheral base pointers */ #define LPCG_LPCG_SPI1_BASE_PTRS { ADMA__LPCG_SPI1_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_SPI1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SPI2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SPI2_Peripheral_Access_Layer LPCG_LPCG_SPI2 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SPI2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SPI2_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SPI2_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SPI2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SPI2_Register_Masks LPCG_LPCG_SPI2 Register Masks * @{ */ /*! @name LPCG_LPCG_SPI2_0 - na */ /*! @{ */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_div_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_div_clk_HWEN_SHIFT (0U) /*! spi2_lpspi_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_div_clk_HWEN_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_div_clk_HWEN_MASK) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN_SHIFT (1U) /*! spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN_MASK) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_spi2_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_2_2_MASK) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP_MASK (0x8U) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP_SHIFT (3U) /*! spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP_MASK) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_spi2_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_4_15_MASK) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_s_HWEN_SHIFT (16U) /*! spi2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN_SHIFT (17U) /*! spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_spi2_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_18_18_MASK) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP_SHIFT (19U) /*! spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_spi2_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SPI2_LPCG_LPCG_SPI2_0_LPCG_lpcg_spi2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SPI2_Register_Masks */ /* LPCG_LPCG_SPI2 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SPI2_IPG_CLK base address */ #define ADMA__LPCG_SPI2_IPG_CLK_BASE (0x5A420000u) /** Peripheral ADMA__LPCG_SPI2_IPG_CLK base pointer */ #define ADMA__LPCG_SPI2_IPG_CLK ((LPCG_LPCG_SPI2_Type *)ADMA__LPCG_SPI2_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_SPI2 peripheral base addresses */ #define LPCG_LPCG_SPI2_BASE_ADDRS { ADMA__LPCG_SPI2_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_SPI2 peripheral base pointers */ #define LPCG_LPCG_SPI2_BASE_PTRS { ADMA__LPCG_SPI2_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_SPI2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SPI3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SPI3_Peripheral_Access_Layer LPCG_LPCG_SPI3 Peripheral Access Layer * @{ */ /** LPCG_LPCG_SPI3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_SPI3_0; /**< na, offset: 0x0 */ } LPCG_LPCG_SPI3_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_SPI3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_SPI3_Register_Masks LPCG_LPCG_SPI3 Register Masks * @{ */ /*! @name LPCG_LPCG_SPI3_0 - na */ /*! @{ */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_div_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_div_clk_HWEN_SHIFT (0U) /*! spi3_lpspi_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_div_clk_HWEN_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_div_clk_HWEN_MASK) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN_SHIFT (1U) /*! spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN_MASK) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_spi3_0_reserved_2_2 - reserved */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_2_2_MASK) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP_MASK (0x8U) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP_SHIFT (3U) /*! spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP_MASK) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_spi3_0_reserved_4_15 - reserved */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_4_15_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_4_15_MASK) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_s_HWEN_SHIFT (16U) /*! spi3_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN_SHIFT (17U) /*! spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_spi3_0_reserved_18_18 - reserved */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_18_18_MASK) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP_SHIFT (19U) /*! spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_spi3_0_reserved_20_31 - reserved */ #define LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_SPI3_LPCG_LPCG_SPI3_0_LPCG_lpcg_spi3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_SPI3_Register_Masks */ /* LPCG_LPCG_SPI3 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_SPI3_IPG_CLK base address */ #define ADMA__LPCG_SPI3_IPG_CLK_BASE (0x5A430000u) /** Peripheral ADMA__LPCG_SPI3_IPG_CLK base pointer */ #define ADMA__LPCG_SPI3_IPG_CLK ((LPCG_LPCG_SPI3_Type *)ADMA__LPCG_SPI3_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_SPI3 peripheral base addresses */ #define LPCG_LPCG_SPI3_BASE_ADDRS { ADMA__LPCG_SPI3_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_SPI3 peripheral base pointers */ #define LPCG_LPCG_SPI3_BASE_PTRS { ADMA__LPCG_SPI3_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_SPI3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_UART0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_UART0_Peripheral_Access_Layer LPCG_LPCG_UART0 Peripheral Access Layer * @{ */ /** LPCG_LPCG_UART0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_UART0_0; /**< na, offset: 0x0 */ } LPCG_LPCG_UART0_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_UART0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_UART0_Register_Masks LPCG_LPCG_UART0 Register Masks * @{ */ /*! @name LPCG_LPCG_UART0_0 - na */ /*! @{ */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_gated_clk_HWEN_SHIFT (0U) /*! uart0_lpuart_baud_gated_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_gated_clk_HWEN_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_gated_clk_HWEN_MASK) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN_SHIFT (1U) /*! uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN_MASK) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_uart0_0_reserved_2_2 - reserved */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_2_2_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_2_2_MASK) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP_SHIFT (3U) /*! uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP_MASK) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_uart0_0_reserved_4_15 - reserved */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_4_15_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_4_15_MASK) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_s_HWEN_SHIFT (16U) /*! uart0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN_SHIFT (17U) /*! uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_uart0_0_reserved_18_18 - reserved */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_18_18_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_18_18_MASK) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP_SHIFT (19U) /*! uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_uart0_0_reserved_20_31 - reserved */ #define LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_20_31_SHIFT)) & LPCG_LPCG_UART0_LPCG_LPCG_UART0_0_LPCG_lpcg_uart0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_UART0_Register_Masks */ /* LPCG_LPCG_UART0 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_UART0_IPG_CLK base address */ #define ADMA__LPCG_UART0_IPG_CLK_BASE (0x5A460000u) /** Peripheral ADMA__LPCG_UART0_IPG_CLK base pointer */ #define ADMA__LPCG_UART0_IPG_CLK ((LPCG_LPCG_UART0_Type *)ADMA__LPCG_UART0_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_UART0 peripheral base addresses */ #define LPCG_LPCG_UART0_BASE_ADDRS { ADMA__LPCG_UART0_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_UART0 peripheral base pointers */ #define LPCG_LPCG_UART0_BASE_PTRS { ADMA__LPCG_UART0_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_UART0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_UART1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_UART1_Peripheral_Access_Layer LPCG_LPCG_UART1 Peripheral Access Layer * @{ */ /** LPCG_LPCG_UART1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_UART1_0; /**< na, offset: 0x0 */ } LPCG_LPCG_UART1_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_UART1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_UART1_Register_Masks LPCG_LPCG_UART1 Register Masks * @{ */ /*! @name LPCG_LPCG_UART1_0 - na */ /*! @{ */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U) /*! uart1_lpuart_baud_gated_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_gated_clk_HWEN_MASK) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U) /*! uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN_MASK) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_uart1_0_reserved_2_2 - reserved */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_2_2_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_2_2_MASK) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP_SHIFT (3U) /*! uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP_MASK) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_uart1_0_reserved_4_15 - reserved */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_4_15_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_4_15_MASK) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_s_HWEN_SHIFT (16U) /*! uart1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN_SHIFT (17U) /*! uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_uart1_0_reserved_18_18 - reserved */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_18_18_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_18_18_MASK) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP_SHIFT (19U) /*! uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_uart1_0_reserved_20_31 - reserved */ #define LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_20_31_SHIFT)) & LPCG_LPCG_UART1_LPCG_LPCG_UART1_0_LPCG_lpcg_uart1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_UART1_Register_Masks */ /* LPCG_LPCG_UART1 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_UART1_IPG_CLK base address */ #define ADMA__LPCG_UART1_IPG_CLK_BASE (0x5A470000u) /** Peripheral ADMA__LPCG_UART1_IPG_CLK base pointer */ #define ADMA__LPCG_UART1_IPG_CLK ((LPCG_LPCG_UART1_Type *)ADMA__LPCG_UART1_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_UART1 peripheral base addresses */ #define LPCG_LPCG_UART1_BASE_ADDRS { ADMA__LPCG_UART1_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_UART1 peripheral base pointers */ #define LPCG_LPCG_UART1_BASE_PTRS { ADMA__LPCG_UART1_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_UART1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_UART2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_UART2_Peripheral_Access_Layer LPCG_LPCG_UART2 Peripheral Access Layer * @{ */ /** LPCG_LPCG_UART2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_UART2_0; /**< na, offset: 0x0 */ } LPCG_LPCG_UART2_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_UART2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_UART2_Register_Masks LPCG_LPCG_UART2 Register Masks * @{ */ /*! @name LPCG_LPCG_UART2_0 - na */ /*! @{ */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_gated_clk_HWEN_SHIFT (0U) /*! uart2_lpuart_baud_gated_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_gated_clk_HWEN_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_gated_clk_HWEN_MASK) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN_SHIFT (1U) /*! uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN_MASK) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_uart2_0_reserved_2_2 - reserved */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_2_2_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_2_2_MASK) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP_SHIFT (3U) /*! uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP_MASK) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_uart2_0_reserved_4_15 - reserved */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_4_15_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_4_15_MASK) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_s_HWEN_SHIFT (16U) /*! uart2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN_SHIFT (17U) /*! uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_uart2_0_reserved_18_18 - reserved */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_18_18_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_18_18_MASK) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP_SHIFT (19U) /*! uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_uart2_0_reserved_20_31 - reserved */ #define LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_20_31_SHIFT)) & LPCG_LPCG_UART2_LPCG_LPCG_UART2_0_LPCG_lpcg_uart2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_UART2_Register_Masks */ /* LPCG_LPCG_UART2 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_UART2_IPG_CLK base address */ #define ADMA__LPCG_UART2_IPG_CLK_BASE (0x5A480000u) /** Peripheral ADMA__LPCG_UART2_IPG_CLK base pointer */ #define ADMA__LPCG_UART2_IPG_CLK ((LPCG_LPCG_UART2_Type *)ADMA__LPCG_UART2_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_UART2 peripheral base addresses */ #define LPCG_LPCG_UART2_BASE_ADDRS { ADMA__LPCG_UART2_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_UART2 peripheral base pointers */ #define LPCG_LPCG_UART2_BASE_PTRS { ADMA__LPCG_UART2_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_UART2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPCG_UART3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_UART3_Peripheral_Access_Layer LPCG_LPCG_UART3 Peripheral Access Layer * @{ */ /** LPCG_LPCG_UART3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPCG_UART3_0; /**< na, offset: 0x0 */ } LPCG_LPCG_UART3_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPCG_UART3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPCG_UART3_Register_Masks LPCG_LPCG_UART3 Register Masks * @{ */ /*! @name LPCG_LPCG_UART3_0 - na */ /*! @{ */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_gated_clk_HWEN_SHIFT (0U) /*! uart3_lpuart_baud_gated_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_gated_clk_HWEN_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_gated_clk_HWEN_MASK) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN_SHIFT (1U) /*! uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN_MASK) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_2_2_MASK (0x4U) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_2_2_SHIFT (2U) /*! LPCG_lpcg_uart3_0_reserved_2_2 - reserved */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_2_2_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_2_2_MASK) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP_SHIFT (3U) /*! uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP_MASK) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_4_15_MASK (0xFFF0U) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_4_15_SHIFT (4U) /*! LPCG_lpcg_uart3_0_reserved_4_15 - reserved */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_4_15_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_4_15_MASK) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_s_HWEN_MASK (0x10000U) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_s_HWEN_SHIFT (16U) /*! uart3_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_s_HWEN_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_s_HWEN_MASK) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN_MASK (0x20000U) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN_SHIFT (17U) /*! uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN_MASK) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_18_18_MASK (0x40000U) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_18_18_SHIFT (18U) /*! LPCG_lpcg_uart3_0_reserved_18_18 - reserved */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_18_18_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_18_18_MASK) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP_MASK (0x80000U) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP_SHIFT (19U) /*! uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP_MASK) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_20_31_SHIFT (20U) /*! LPCG_lpcg_uart3_0_reserved_20_31 - reserved */ #define LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_20_31_SHIFT)) & LPCG_LPCG_UART3_LPCG_LPCG_UART3_0_LPCG_lpcg_uart3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPCG_UART3_Register_Masks */ /* LPCG_LPCG_UART3 - Peripheral instance base addresses */ /** Peripheral ADMA__LPCG_UART3_IPG_CLK base address */ #define ADMA__LPCG_UART3_IPG_CLK_BASE (0x5A490000u) /** Peripheral ADMA__LPCG_UART3_IPG_CLK base pointer */ #define ADMA__LPCG_UART3_IPG_CLK ((LPCG_LPCG_UART3_Type *)ADMA__LPCG_UART3_IPG_CLK_BASE) /** Array initializer of LPCG_LPCG_UART3 peripheral base addresses */ #define LPCG_LPCG_UART3_BASE_ADDRS { ADMA__LPCG_UART3_IPG_CLK_BASE } /** Array initializer of LPCG_LPCG_UART3 peripheral base pointers */ #define LPCG_LPCG_UART3_BASE_PTRS { ADMA__LPCG_UART3_IPG_CLK } /*! * @} */ /* end of group LPCG_LPCG_UART3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPI2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPI2C_Peripheral_Access_Layer LPCG_LPI2C Peripheral Access Layer * @{ */ /** LPCG_LPI2C - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPI2C_0; /**< na, offset: 0x0 */ } LPCG_LPI2C_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPI2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPI2C_Register_Masks LPCG_LPI2C Register Masks * @{ */ /*! @name LPCG_LPI2C_0 - na */ /*! @{ */ #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U) #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U) /*! lpi2c1_lpi2c_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK) #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U) #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U) /*! lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK) #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U) #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U) /*! LPCG_LPI2C_0_reserved_2_2 - reserved */ #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK) #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U) #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U) /*! lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK) #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U) #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U) /*! LPCG_LPI2C_0_reserved_4_4 - reserved */ #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK) #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U) #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U) /*! lpi2c1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK) #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U) #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U) /*! LPCG_LPI2C_0_reserved_6_6 - reserved */ #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK) #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U) #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U) /*! lpi2c1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK) #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U) #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U) /*! LPCG_LPI2C_0_reserved_8_31 - reserved */ #define LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPI2C_Register_Masks */ /* LPCG_LPI2C - Peripheral instance base addresses */ /** Peripheral SCU__LPCG_LPI2C base address */ #define SCU__LPCG_LPI2C_BASE (0x33630000u) /** Peripheral SCU__LPCG_LPI2C base pointer */ #define SCU__LPCG_LPI2C ((LPCG_LPI2C_Type *)SCU__LPCG_LPI2C_BASE) /** Array initializer of LPCG_LPI2C peripheral base addresses */ #define LPCG_LPI2C_BASE_ADDRS { SCU__LPCG_LPI2C_BASE } /** Array initializer of LPCG_LPI2C peripheral base pointers */ #define LPCG_LPI2C_BASE_PTRS { SCU__LPCG_LPI2C } /*! * @} */ /* end of group LPCG_LPI2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPIT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPIT_Peripheral_Access_Layer LPCG_LPIT Peripheral Access Layer * @{ */ /** LPCG_LPIT - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPIT_0; /**< na, offset: 0x0 */ } LPCG_LPIT_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPIT_Register_Masks LPCG_LPIT Register Masks * @{ */ /*! @name LPCG_LPIT_0 - na */ /*! @{ */ #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U) #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U) /*! lpit1_ipg_per_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK) #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U) #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U) /*! lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK) #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U) #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U) /*! LPCG_LPIT_0_reserved_2_2 - reserved */ #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK) #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U) #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U) /*! lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK) #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U) #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U) /*! LPCG_LPIT_0_reserved_4_4 - reserved */ #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK) #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U) #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U) /*! lpit1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK) #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U) #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U) /*! LPCG_LPIT_0_reserved_6_6 - reserved */ #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK) #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U) #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U) /*! lpit1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK) #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U) #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U) /*! LPCG_LPIT_0_reserved_8_31 - reserved */ #define LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPIT_Register_Masks */ /* LPCG_LPIT - Peripheral instance base addresses */ /** Peripheral SCU__LPCG_LPIT base address */ #define SCU__LPCG_LPIT_BASE (0x33610000u) /** Peripheral SCU__LPCG_LPIT base pointer */ #define SCU__LPCG_LPIT ((LPCG_LPIT_Type *)SCU__LPCG_LPIT_BASE) /** Array initializer of LPCG_LPIT peripheral base addresses */ #define LPCG_LPIT_BASE_ADDRS { SCU__LPCG_LPIT_BASE } /** Array initializer of LPCG_LPIT peripheral base pointers */ #define LPCG_LPIT_BASE_PTRS { SCU__LPCG_LPIT } /*! * @} */ /* end of group LPCG_LPIT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_LPUART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPUART_Peripheral_Access_Layer LPCG_LPUART Peripheral Access Layer * @{ */ /** LPCG_LPUART - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_LPUART_0; /**< na, offset: 0x0 */ } LPCG_LPUART_Type; /* ---------------------------------------------------------------------------- -- LPCG_LPUART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_LPUART_Register_Masks LPCG_LPUART Register Masks * @{ */ /*! @name LPCG_LPUART_0 - na */ /*! @{ */ #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U) #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U) /*! lpuart1_lpuart_baud_gated_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK) #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U) #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U) /*! lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK) #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U) #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U) /*! LPCG_LPUART_0_reserved_2_2 - reserved */ #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK) #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U) #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U) /*! lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK) #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U) #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U) /*! LPCG_LPUART_0_reserved_4_4 - reserved */ #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK) #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U) #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U) /*! lpuart1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK) #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U) #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U) /*! LPCG_LPUART_0_reserved_6_6 - reserved */ #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK) #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U) #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U) /*! lpuart1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK) #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U) #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U) /*! LPCG_LPUART_0_reserved_8_31 - reserved */ #define LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_LPUART_Register_Masks */ /* LPCG_LPUART - Peripheral instance base addresses */ /** Peripheral SCU__LPCG_LPUART base address */ #define SCU__LPCG_LPUART_BASE (0x33620000u) /** Peripheral SCU__LPCG_LPUART base pointer */ #define SCU__LPCG_LPUART ((LPCG_LPUART_Type *)SCU__LPCG_LPUART_BASE) /** Array initializer of LPCG_LPUART peripheral base addresses */ #define LPCG_LPUART_BASE_ADDRS { SCU__LPCG_LPUART_BASE } /** Array initializer of LPCG_LPUART peripheral base pointers */ #define LPCG_LPUART_BASE_PTRS { SCU__LPCG_LPUART } /*! * @} */ /* end of group LPCG_LPUART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_MFD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_MFD_Peripheral_Access_Layer LPCG_MFD Peripheral Access Layer * @{ */ /** LPCG_MFD - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MFD_0; /**< na, offset: 0x0 */ } LPCG_MFD_Type; /* ---------------------------------------------------------------------------- -- LPCG_MFD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_MFD_Register_Masks LPCG_MFD Register Masks * @{ */ /*! @name LPCG_MFD_0 - na */ /*! @{ */ #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_0_MASK (0x1U) #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_0_SHIFT (0U) /*! LPCG_MFD_0_reserved_0_0 - reserved */ #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_0_SHIFT)) & LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_0_MASK) #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_SWEN_MASK (0x2U) #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_SWEN_SHIFT (1U) /*! med_dec_mfd_sys_clk_gated_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_SWEN_SHIFT)) & LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_SWEN_MASK) #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_2_2_MASK (0x4U) #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_2_2_SHIFT (2U) /*! LPCG_MFD_0_reserved_2_2 - reserved */ #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_2_2_SHIFT)) & LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_2_2_MASK) #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_STOP_MASK (0x8U) #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_STOP_SHIFT (3U) /*! med_dec_mfd_sys_clk_gated_STOP - show clock root status, 1 means clock stopped */ #define LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_STOP_SHIFT)) & LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_gated_STOP_MASK) #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_4_31_SHIFT (4U) /*! LPCG_MFD_0_reserved_4_31 - reserved */ #define LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_4_31_SHIFT)) & LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_MFD_Register_Masks */ /* LPCG_MFD - Peripheral instance base addresses */ /** Peripheral VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED base address */ #define VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED_BASE (0x2D070000u) /** Peripheral VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED base pointer */ #define VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED ((LPCG_MFD_Type *)VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED_BASE) /** Array initializer of LPCG_MFD peripheral base addresses */ #define LPCG_MFD_BASE_ADDRS { VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED_BASE } /** Array initializer of LPCG_MFD peripheral base pointers */ #define LPCG_MFD_BASE_PTRS { VPU__LPCG_MED_DEC_MFD_SYS_CLK_GATED } /*! * @} */ /* end of group LPCG_MFD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_MISC_CRR5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_MISC_CRR5_Peripheral_Access_Layer LPCG_MISC_CRR5 Peripheral Access Layer * @{ */ /** LPCG_MISC_CRR5 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MISC_CRR5_0; /**< na, offset: 0x0 */ } LPCG_MISC_CRR5_Type; /* ---------------------------------------------------------------------------- -- LPCG_MISC_CRR5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_MISC_CRR5_Register_Masks LPCG_MISC_CRR5 Register Masks * @{ */ /*! @name LPCG_MISC_CRR5_0 - na */ /*! @{ */ #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_MASK (0xFFFFU) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_SHIFT (0U) /*! LPCG_MISC_CRR5_0_reserved_0_15 - reserved */ #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_MASK) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_MASK (0x10000U) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_SHIFT (16U) /*! hsio_misc_regs_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_MASK) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_SHIFT (17U) /*! hsio_misc_regs_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_MASK) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_MASK (0x40000U) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_SHIFT (18U) /*! LPCG_MISC_CRR5_0_reserved_18_18 - reserved */ #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_MASK) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_MASK (0x80000U) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_SHIFT (19U) /*! hsio_misc_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_MASK) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_SHIFT (20U) /*! LPCG_MISC_CRR5_0_reserved_20_31 - reserved */ #define LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_SHIFT)) & LPCG_MISC_CRR5_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_MISC_CRR5_Register_Masks */ /* LPCG_MISC_CRR5 - Peripheral instance base addresses */ /** Peripheral HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK base address */ #define HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK_BASE (0x5F0F0000u) /** Peripheral HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK base pointer */ #define HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK ((LPCG_MISC_CRR5_Type *)HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK_BASE) /** Array initializer of LPCG_MISC_CRR5 peripheral base addresses */ #define LPCG_MISC_CRR5_BASE_ADDRS { HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK_BASE } /** Array initializer of LPCG_MISC_CRR5 peripheral base pointers */ #define LPCG_MISC_CRR5_BASE_PTRS { HSIO__LPCG_HSIO_MISC_REGS_IPG_CLK } /*! * @} */ /* end of group LPCG_MISC_CRR5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_MMCAU_HCLK Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_MMCAU_HCLK_Peripheral_Access_Layer LPCG_MMCAU_HCLK Peripheral Access Layer * @{ */ /** LPCG_MMCAU_HCLK - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MMCAU_HCLK_0; /**< na, offset: 0x0 */ } LPCG_MMCAU_HCLK_Type; /* ---------------------------------------------------------------------------- -- LPCG_MMCAU_HCLK Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_MMCAU_HCLK_Register_Masks LPCG_MMCAU_HCLK Register Masks * @{ */ /*! @name LPCG_MMCAU_HCLK_0 - na */ /*! @{ */ #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U) #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U) /*! LPCG_MMCAU_HCLK_0_reserved_0_0 - reserved */ #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK) #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U) #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U) /*! cm4_mmcau_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK) #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U) #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U) /*! LPCG_MMCAU_HCLK_0_reserved_2_2 - reserved */ #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK) #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U) #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U) /*! cm4_mmcau_hclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK) #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U) /*! LPCG_MMCAU_HCLK_0_reserved_4_31 - reserved */ #define LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_MMCAU_HCLK_Register_Masks */ /* LPCG_MMCAU_HCLK - Peripheral instance base addresses */ /** Peripheral SCU__LPCG_MMCAU_HCLK base address */ #define SCU__LPCG_MMCAU_HCLK_BASE (0x335F0000u) /** Peripheral SCU__LPCG_MMCAU_HCLK base pointer */ #define SCU__LPCG_MMCAU_HCLK ((LPCG_MMCAU_HCLK_Type *)SCU__LPCG_MMCAU_HCLK_BASE) /** Array initializer of LPCG_MMCAU_HCLK peripheral base addresses */ #define LPCG_MMCAU_HCLK_BASE_ADDRS { SCU__LPCG_MMCAU_HCLK_BASE } /** Array initializer of LPCG_MMCAU_HCLK peripheral base pointers */ #define LPCG_MMCAU_HCLK_BASE_PTRS { SCU__LPCG_MMCAU_HCLK } /*! * @} */ /* end of group LPCG_MMCAU_HCLK_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_MPGD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_MPGD_Peripheral_Access_Layer LPCG_MPGD Peripheral Access Layer * @{ */ /** LPCG_MPGD - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MPGD_0; /**< na, offset: 0x0 */ } LPCG_MPGD_Type; /* ---------------------------------------------------------------------------- -- LPCG_MPGD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_MPGD_Register_Masks LPCG_MPGD Register Masks * @{ */ /*! @name LPCG_MPGD_0 - na */ /*! @{ */ #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_0_MASK (0x1U) #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_0_SHIFT (0U) /*! LPCG_MPGD_0_reserved_0_0 - reserved */ #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_0_SHIFT)) & LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_0_MASK) #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_MASK (0x2U) #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_SHIFT (1U) /*! med_dec_mfd_mpgd_clk_gated_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_SHIFT)) & LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_MASK) #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_2_2_MASK (0x4U) #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_2_2_SHIFT (2U) /*! LPCG_MPGD_0_reserved_2_2 - reserved */ #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_2_2_SHIFT)) & LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_2_2_MASK) #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_MASK (0x8U) #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_SHIFT (3U) /*! med_dec_mfd_mpgd_clk_gated_STOP - show clock root status, 1 means clock stopped */ #define LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_SHIFT)) & LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_MASK) #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_4_31_SHIFT (4U) /*! LPCG_MPGD_0_reserved_4_31 - reserved */ #define LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_4_31_SHIFT)) & LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_MPGD_Register_Masks */ /* LPCG_MPGD - Peripheral instance base addresses */ /** Peripheral VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED base address */ #define VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED_BASE (0x2D0A0000u) /** Peripheral VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED base pointer */ #define VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED ((LPCG_MPGD_Type *)VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED_BASE) /** Array initializer of LPCG_MPGD peripheral base addresses */ #define LPCG_MPGD_BASE_ADDRS { VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED_BASE } /** Array initializer of LPCG_MPGD peripheral base pointers */ #define LPCG_MPGD_BASE_PTRS { VPU__LPCG_MED_DEC_MFD_MPGD_CLK_GATED } /*! * @} */ /* end of group LPCG_MPGD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_PCIEX1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_PCIEX1_Peripheral_Access_Layer LPCG_PCIEX1 Peripheral Access Layer * @{ */ /** LPCG_PCIEX1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PCIEX1_0; /**< na, offset: 0x0 */ } LPCG_PCIEX1_Type; /* ---------------------------------------------------------------------------- -- LPCG_PCIEX1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_PCIEX1_Register_Masks LPCG_PCIEX1 Register Masks * @{ */ /*! @name LPCG_PCIEX1_0 - na */ /*! @{ */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_15_MASK (0xFFFFU) #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_15_SHIFT (0U) /*! LPCG_PCIEX1_0_reserved_0_15 - reserved */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_15_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_15_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_HWEN_MASK (0x10000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_HWEN_SHIFT (16U) /*! pcie_clk_rst_mstr_axi_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_HWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_HWEN_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_SWEN_MASK (0x20000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_SWEN_SHIFT (17U) /*! pcie_clk_rst_mstr_axi_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_SWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_SWEN_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_MASK (0x40000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_SHIFT (18U) /*! LPCG_PCIEX1_0_reserved_18_18 - reserved */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_STOP_MASK (0x80000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_STOP_SHIFT (19U) /*! pcie_clk_rst_mstr_axi_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_STOP_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_mstr_axi_clk_STOP_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_HWEN_MASK (0x100000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_HWEN_SHIFT (20U) /*! pcie_clk_rst_slv_axi_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_HWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_HWEN_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_SWEN_MASK (0x200000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_SWEN_SHIFT (21U) /*! pcie_clk_rst_slv_axi_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_SWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_SWEN_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_MASK (0x400000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_SHIFT (22U) /*! LPCG_PCIEX1_0_reserved_22_22 - reserved */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_STOP_MASK (0x800000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_STOP_SHIFT (23U) /*! pcie_clk_rst_slv_axi_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_STOP_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_slv_axi_clk_STOP_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_HWEN_MASK (0x1000000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_HWEN_SHIFT (24U) /*! pcie_clk_rst_dbi_axi_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_HWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_HWEN_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_SWEN_MASK (0x2000000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_SWEN_SHIFT (25U) /*! pcie_clk_rst_dbi_axi_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_SWEN_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_SWEN_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_MASK (0x4000000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_SHIFT (26U) /*! LPCG_PCIEX1_0_reserved_26_26 - reserved */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_STOP_MASK (0x8000000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_STOP_SHIFT (27U) /*! pcie_clk_rst_dbi_axi_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_STOP_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_dbi_axi_clk_STOP_MASK) #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_MASK (0xF0000000U) #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_SHIFT (28U) /*! LPCG_PCIEX1_0_reserved_28_31 - reserved */ #define LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_SHIFT)) & LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_PCIEX1_Register_Masks */ /* LPCG_PCIEX1 - Peripheral instance base addresses */ /** Peripheral HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK base address */ #define HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK_BASE (0x5F060000u) /** Peripheral HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK base pointer */ #define HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK ((LPCG_PCIEX1_Type *)HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK_BASE) /** Array initializer of LPCG_PCIEX1 peripheral base addresses */ #define LPCG_PCIEX1_BASE_ADDRS { HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK_BASE } /** Array initializer of LPCG_PCIEX1 peripheral base pointers */ #define LPCG_PCIEX1_BASE_PTRS { HSIO__LPCG_PCIE_CLK_RST_A_MSTR_AXI_CLK } /*! * @} */ /* end of group LPCG_PCIEX1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_PCIEX1_CRR3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_PCIEX1_CRR3_Peripheral_Access_Layer LPCG_PCIEX1_CRR3 Peripheral Access Layer * @{ */ /** LPCG_PCIEX1_CRR3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PCIEX1_CRR3_0; /**< na, offset: 0x0 */ } LPCG_PCIEX1_CRR3_Type; /* ---------------------------------------------------------------------------- -- LPCG_PCIEX1_CRR3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_PCIEX1_CRR3_Register_Masks LPCG_PCIEX1_CRR3 Register Masks * @{ */ /*! @name LPCG_PCIEX1_CRR3_0 - na */ /*! @{ */ #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_MASK (0xFFFFU) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_SHIFT (0U) /*! LPCG_PCIEX1_CRR3_0_reserved_0_15 - reserved */ #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_MASK) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_MASK (0x10000U) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_SHIFT (16U) /*! hsio_pciex1_regs_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_MASK) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_SHIFT (17U) /*! hsio_pciex1_regs_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_MASK) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_MASK (0x40000U) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_SHIFT (18U) /*! LPCG_PCIEX1_CRR3_0_reserved_18_18 - reserved */ #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_MASK) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_MASK (0x80000U) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_SHIFT (19U) /*! hsio_pciex1_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_MASK) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_SHIFT (20U) /*! LPCG_PCIEX1_CRR3_0_reserved_20_31 - reserved */ #define LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_SHIFT)) & LPCG_PCIEX1_CRR3_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_PCIEX1_CRR3_Register_Masks */ /* LPCG_PCIEX1_CRR3 - Peripheral instance base addresses */ /** Peripheral HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK base address */ #define HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK_BASE (0x5F0D0000u) /** Peripheral HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK base pointer */ #define HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK ((LPCG_PCIEX1_CRR3_Type *)HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK_BASE) /** Array initializer of LPCG_PCIEX1_CRR3 peripheral base addresses */ #define LPCG_PCIEX1_CRR3_BASE_ADDRS { HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK_BASE } /** Array initializer of LPCG_PCIEX1_CRR3 peripheral base pointers */ #define LPCG_PCIEX1_CRR3_BASE_PTRS { HSIO__LPCG_HSIO_PCIEX1_REGS_IPG_CLK } /*! * @} */ /* end of group LPCG_PCIEX1_CRR3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_PHYX1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_PHYX1_Peripheral_Access_Layer LPCG_PHYX1 Peripheral Access Layer * @{ */ /** LPCG_PHYX1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PHYX1_0; /**< na, offset: 0x0 */ } LPCG_PHYX1_Type; /* ---------------------------------------------------------------------------- -- LPCG_PHYX1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_PHYX1_Register_Masks LPCG_PHYX1 Register Masks * @{ */ /*! @name LPCG_PHYX1_0 - na */ /*! @{ */ #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_15_MASK (0xFFFFU) #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_15_SHIFT (0U) /*! LPCG_PHYX1_0_reserved_0_15 - reserved */ #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_15_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_15_MASK) #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_HWEN_MASK (0x10000U) #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_HWEN_SHIFT (16U) /*! pcs_phy_x1_apb_pclk_0_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_HWEN_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_HWEN_MASK) #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_MASK (0x20000U) #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_SHIFT (17U) /*! pcs_phy_x1_apb_pclk_0_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_MASK) #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_MASK (0x40000U) #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_SHIFT (18U) /*! LPCG_PHYX1_0_reserved_18_18 - reserved */ #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_MASK) #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_MASK (0x80000U) #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_SHIFT (19U) /*! pcs_phy_x1_apb_pclk_0_STOP - show clock root status, 1 means clock stopped */ #define LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_MASK) #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_SHIFT (20U) /*! LPCG_PHYX1_0_reserved_20_31 - reserved */ #define LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_SHIFT)) & LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_PHYX1_Register_Masks */ /* LPCG_PHYX1 - Peripheral instance base addresses */ /** Peripheral HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0 base address */ #define HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0_BASE (0x5F090000u) /** Peripheral HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0 base pointer */ #define HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0 ((LPCG_PHYX1_Type *)HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0_BASE) /** Array initializer of LPCG_PHYX1 peripheral base addresses */ #define LPCG_PHYX1_BASE_ADDRS { HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0_BASE } /** Array initializer of LPCG_PHYX1 peripheral base pointers */ #define LPCG_PHYX1_BASE_PTRS { HSIO__LPCG_PCS_PHY_X1_APB_PCLK_0 } /*! * @} */ /* end of group LPCG_PHYX1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_PHYX1_CRR1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_PHYX1_CRR1_Peripheral_Access_Layer LPCG_PHYX1_CRR1 Peripheral Access Layer * @{ */ /** LPCG_PHYX1_CRR1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_PHYX1_CRR1_0; /**< na, offset: 0x0 */ } LPCG_PHYX1_CRR1_Type; /* ---------------------------------------------------------------------------- -- LPCG_PHYX1_CRR1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_PHYX1_CRR1_Register_Masks LPCG_PHYX1_CRR1 Register Masks * @{ */ /*! @name LPCG_PHYX1_CRR1_0 - na */ /*! @{ */ #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_MASK (0xFFFFU) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_SHIFT (0U) /*! LPCG_PHYX1_CRR1_0_reserved_0_15 - reserved */ #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_MASK) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_MASK (0x10000U) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_SHIFT (16U) /*! hsio_phyx1_regs_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_MASK) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_MASK (0x20000U) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_SHIFT (17U) /*! hsio_phyx1_regs_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_MASK) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_MASK (0x40000U) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_SHIFT (18U) /*! LPCG_PHYX1_CRR1_0_reserved_18_18 - reserved */ #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_MASK) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_MASK (0x80000U) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_SHIFT (19U) /*! hsio_phyx1_regs_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_MASK) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_MASK (0xFFF00000U) #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_SHIFT (20U) /*! LPCG_PHYX1_CRR1_0_reserved_20_31 - reserved */ #define LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_SHIFT)) & LPCG_PHYX1_CRR1_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_PHYX1_CRR1_Register_Masks */ /* LPCG_PHYX1_CRR1 - Peripheral instance base addresses */ /** Peripheral HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK base address */ #define HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK_BASE (0x5F0B0000u) /** Peripheral HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK base pointer */ #define HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK ((LPCG_PHYX1_CRR1_Type *)HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK_BASE) /** Array initializer of LPCG_PHYX1_CRR1 peripheral base addresses */ #define LPCG_PHYX1_CRR1_BASE_ADDRS { HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK_BASE } /** Array initializer of LPCG_PHYX1_CRR1 peripheral base pointers */ #define LPCG_PHYX1_CRR1_BASE_PTRS { HSIO__LPCG_HSIO_PHYX1_REGS_IPG_CLK } /*! * @} */ /* end of group LPCG_PHYX1_CRR1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_SSI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_SSI_Peripheral_Access_Layer LPCG_SSI Peripheral Access Layer * @{ */ /** LPCG_SSI - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_SSI_0; /**< na, offset: 0x0 */ } LPCG_SSI_Type; /* ---------------------------------------------------------------------------- -- LPCG_SSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_SSI_Register_Masks LPCG_SSI Register Masks * @{ */ /*! @name LPCG_SSI_0 - na */ /*! @{ */ #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_HWEN_MASK (0x1U) #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_HWEN_SHIFT (0U) /*! ssi_pclk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_SSI_LPCG_SSI_0_ssi_pclk_HWEN_SHIFT)) & LPCG_SSI_LPCG_SSI_0_ssi_pclk_HWEN_MASK) #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_SWEN_MASK (0x2U) #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_SWEN_SHIFT (1U) /*! ssi_pclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_SSI_LPCG_SSI_0_ssi_pclk_SWEN_SHIFT)) & LPCG_SSI_LPCG_SSI_0_ssi_pclk_SWEN_MASK) #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_2_2_MASK (0x4U) #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_2_2_SHIFT (2U) /*! LPCG_SSI_0_reserved_2_2 - reserved */ #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_2_2_SHIFT)) & LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_2_2_MASK) #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_STOP_MASK (0x8U) #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_STOP_SHIFT (3U) /*! ssi_pclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_SSI_LPCG_SSI_0_ssi_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_SSI_LPCG_SSI_0_ssi_pclk_STOP_SHIFT)) & LPCG_SSI_LPCG_SSI_0_ssi_pclk_STOP_MASK) #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_4_31_SHIFT (4U) /*! LPCG_SSI_0_reserved_4_31 - reserved */ #define LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_4_31_SHIFT)) & LPCG_SSI_LPCG_SSI_0_LPCG_SSI_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_SSI_Register_Masks */ /* LPCG_SSI - Peripheral instance base addresses */ /** Peripheral HSIO__LPCG_SSI_PCLK base address */ #define HSIO__LPCG_SSI_PCLK_BASE (0x5F070000u) /** Peripheral HSIO__LPCG_SSI_PCLK base pointer */ #define HSIO__LPCG_SSI_PCLK ((LPCG_SSI_Type *)HSIO__LPCG_SSI_PCLK_BASE) /** Array initializer of LPCG_SSI peripheral base addresses */ #define LPCG_SSI_BASE_ADDRS { HSIO__LPCG_SSI_PCLK_BASE } /** Array initializer of LPCG_SSI peripheral base pointers */ #define LPCG_SSI_BASE_PTRS { HSIO__LPCG_SSI_PCLK } /*! * @} */ /* end of group LPCG_SSI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_TCMC_HCLK Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_TCMC_HCLK_Peripheral_Access_Layer LPCG_TCMC_HCLK Peripheral Access Layer * @{ */ /** LPCG_TCMC_HCLK - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_TCMC_HCLK_0; /**< na, offset: 0x0 */ } LPCG_TCMC_HCLK_Type; /* ---------------------------------------------------------------------------- -- LPCG_TCMC_HCLK Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_TCMC_HCLK_Register_Masks LPCG_TCMC_HCLK Register Masks * @{ */ /*! @name LPCG_TCMC_HCLK_0 - na */ /*! @{ */ #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U) #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U) /*! cm4_tcmc_hclk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK) #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U) #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U) /*! cm4_tcmc_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK) #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U) #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U) /*! LPCG_TCMC_HCLK_0_reserved_2_2 - reserved */ #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK) #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U) #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U) /*! cm4_tcmc_hclk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK) #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U) /*! LPCG_TCMC_HCLK_0_reserved_4_31 - reserved */ #define LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_TCMC_HCLK_Register_Masks */ /* LPCG_TCMC_HCLK - Peripheral instance base addresses */ /** Peripheral SCU__LPCG_TCMC_HCLK base address */ #define SCU__LPCG_TCMC_HCLK_BASE (0x335E0000u) /** Peripheral SCU__LPCG_TCMC_HCLK base pointer */ #define SCU__LPCG_TCMC_HCLK ((LPCG_TCMC_HCLK_Type *)SCU__LPCG_TCMC_HCLK_BASE) /** Array initializer of LPCG_TCMC_HCLK peripheral base addresses */ #define LPCG_TCMC_HCLK_BASE_ADDRS { SCU__LPCG_TCMC_HCLK_BASE } /** Array initializer of LPCG_TCMC_HCLK peripheral base pointers */ #define LPCG_TCMC_HCLK_BASE_PTRS { SCU__LPCG_TCMC_HCLK } /*! * @} */ /* end of group LPCG_TCMC_HCLK_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_TPM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_TPM_Peripheral_Access_Layer LPCG_TPM Peripheral Access Layer * @{ */ /** LPCG_TPM - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_TPM_0; /**< na, offset: 0x0 */ } LPCG_TPM_Type; /* ---------------------------------------------------------------------------- -- LPCG_TPM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_TPM_Register_Masks LPCG_TPM Register Masks * @{ */ /*! @name LPCG_TPM_0 - na */ /*! @{ */ #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U) #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U) /*! LPCG_TPM_0_reserved_0_0 - reserved */ #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK) #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U) #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U) /*! tpm1_lptpm_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK) #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U) #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U) /*! LPCG_TPM_0_reserved_2_2 - reserved */ #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK) #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U) #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U) /*! tpm1_lptpm_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK) #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U) #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U) /*! LPCG_TPM_0_reserved_4_4 - reserved */ #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK) #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U) #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U) /*! tpm1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK) #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U) #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U) /*! LPCG_TPM_0_reserved_6_6 - reserved */ #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK) #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U) #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U) /*! tpm1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK) #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U) #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U) /*! LPCG_TPM_0_reserved_8_31 - reserved */ #define LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_TPM_Register_Masks */ /* LPCG_TPM - Peripheral instance base addresses */ /** Peripheral SCU__LPCG_TPM base address */ #define SCU__LPCG_TPM_BASE (0x33600000u) /** Peripheral SCU__LPCG_TPM base pointer */ #define SCU__LPCG_TPM ((LPCG_TPM_Type *)SCU__LPCG_TPM_BASE) /** Array initializer of LPCG_TPM peripheral base addresses */ #define LPCG_TPM_BASE_ADDRS { SCU__LPCG_TPM_BASE } /** Array initializer of LPCG_TPM peripheral base pointers */ #define LPCG_TPM_BASE_PTRS { SCU__LPCG_TPM } /*! * @} */ /* end of group LPCG_TPM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPCG_VC1D Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_VC1D_Peripheral_Access_Layer LPCG_VC1D Peripheral Access Layer * @{ */ /** LPCG_VC1D - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_VC1D_0; /**< na, offset: 0x0 */ } LPCG_VC1D_Type; /* ---------------------------------------------------------------------------- -- LPCG_VC1D Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPCG_VC1D_Register_Masks LPCG_VC1D Register Masks * @{ */ /*! @name LPCG_VC1D_0 - na */ /*! @{ */ #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_0_MASK (0x1U) #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_0_SHIFT (0U) /*! LPCG_VC1D_0_reserved_0_0 - reserved */ #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_0_SHIFT)) & LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_0_MASK) #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_MASK (0x2U) #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_SHIFT (1U) /*! med_dec_mfd_vc1d_clk_gated_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_SHIFT)) & LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_MASK) #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_2_2_MASK (0x4U) #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_2_2_SHIFT (2U) /*! LPCG_VC1D_0_reserved_2_2 - reserved */ #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_2_2_SHIFT)) & LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_2_2_MASK) #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_MASK (0x8U) #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_SHIFT (3U) /*! med_dec_mfd_vc1d_clk_gated_STOP - show clock root status, 1 means clock stopped */ #define LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_SHIFT)) & LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_MASK) #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_4_31_MASK (0xFFFFFFF0U) #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_4_31_SHIFT (4U) /*! LPCG_VC1D_0_reserved_4_31 - reserved */ #define LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_4_31_SHIFT)) & LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group LPCG_VC1D_Register_Masks */ /* LPCG_VC1D - Peripheral instance base addresses */ /** Peripheral VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED base address */ #define VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED_BASE (0x2D090000u) /** Peripheral VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED base pointer */ #define VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED ((LPCG_VC1D_Type *)VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED_BASE) /** Array initializer of LPCG_VC1D peripheral base addresses */ #define LPCG_VC1D_BASE_ADDRS { VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED_BASE } /** Array initializer of LPCG_VC1D peripheral base pointers */ #define LPCG_VC1D_BASE_PTRS { VPU__LPCG_MED_DEC_MFD_VC1D_CLK_GATED } /*! * @} */ /* end of group LPCG_VC1D_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPI2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer * @{ */ /** LPI2C - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ uint8_t RESERVED_1[16]; __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ uint8_t RESERVED_2[4]; __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ uint8_t RESERVED_3[4]; __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ uint8_t RESERVED_4[4]; __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ uint8_t RESERVED_5[12]; __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ uint8_t RESERVED_6[156]; __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ uint8_t RESERVED_7[4]; __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ uint8_t RESERVED_8[20]; __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ uint8_t RESERVED_9[12]; __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ uint8_t RESERVED_10[8]; __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ uint8_t RESERVED_11[12]; __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ } LPI2C_Type; /* ---------------------------------------------------------------------------- -- LPI2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPI2C_Register_Masks LPI2C Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) #define LPI2C_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000010..Master only, with standard feature set * 0b0000000000000011..Master and slave, with standard feature set */ #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) #define LPI2C_VERID_MINOR_MASK (0xFF0000U) #define LPI2C_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) #define LPI2C_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) /*! MTXFIFO - Master Transmit FIFO Size */ #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) /*! MRXFIFO - Master Receive FIFO Size */ #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) /*! @} */ /*! @name MCR - Master Control Register */ /*! @{ */ #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) /*! MEN - Master Enable * 0b0..Master logic is disabled * 0b1..Master logic is enabled */ #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) #define LPI2C_MCR_RST_MASK (0x2U) #define LPI2C_MCR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Master logic is not reset * 0b1..Master logic is reset */ #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) #define LPI2C_MCR_DOZEN_MASK (0x4U) #define LPI2C_MCR_DOZEN_SHIFT (2U) /*! DOZEN - Doze mode enable * 0b0..Master is enabled in Doze mode * 0b1..Master is disabled in Doze mode */ #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) #define LPI2C_MCR_DBGEN_MASK (0x8U) #define LPI2C_MCR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable * 0b0..Master is disabled in debug mode * 0b1..Master is enabled in debug mode */ #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) #define LPI2C_MCR_RTF_MASK (0x100U) #define LPI2C_MCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..Transmit FIFO is reset */ #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) #define LPI2C_MCR_RRF_MASK (0x200U) #define LPI2C_MCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..Receive FIFO is reset */ #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) /*! @} */ /*! @name MSR - Master Status Register */ /*! @{ */ #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data is not requested * 0b1..Transmit data is requested */ #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) #define LPI2C_MSR_RDF_MASK (0x2U) #define LPI2C_MSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive Data is not ready * 0b1..Receive data is ready */ #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) #define LPI2C_MSR_EPF_MASK (0x100U) #define LPI2C_MSR_EPF_SHIFT (8U) /*! EPF - End Packet Flag * 0b0..Master has not generated a STOP or Repeated START condition * 0b1..Master has generated a STOP or Repeated START condition */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) #define LPI2C_MSR_SDF_MASK (0x200U) #define LPI2C_MSR_SDF_SHIFT (9U) /*! SDF - STOP Detect Flag * 0b0..Master has not generated a STOP condition * 0b1..Master has generated a STOP condition */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) /*! NDF - NACK Detect Flag * 0b0..Unexpected NACK was not detected * 0b1..Unexpected NACK was detected */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) #define LPI2C_MSR_ALF_MASK (0x800U) #define LPI2C_MSR_ALF_SHIFT (11U) /*! ALF - Arbitration Lost Flag * 0b0..Master has not lost arbitration * 0b1..Master has lost arbitration */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) #define LPI2C_MSR_FEF_MASK (0x1000U) #define LPI2C_MSR_FEF_SHIFT (12U) /*! FEF - FIFO Error Flag * 0b0..No error * 0b1..Master sending or receiving data without a START condition */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) /*! PLTF - Pin Low Timeout Flag * 0b0..Pin low timeout has not occurred or is disabled * 0b1..Pin low timeout has occurred */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) #define LPI2C_MSR_DMF_MASK (0x4000U) #define LPI2C_MSR_DMF_SHIFT (14U) /*! DMF - Data Match Flag * 0b0..Have not received matching data * 0b1..Have received matching data */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_MBF_MASK (0x1000000U) #define LPI2C_MSR_MBF_SHIFT (24U) /*! MBF - Master Busy Flag * 0b0..I2C Master is idle * 0b1..I2C Master is busy */ #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) #define LPI2C_MSR_BBF_MASK (0x2000000U) #define LPI2C_MSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag * 0b0..I2C Bus is idle * 0b1..I2C Bus is busy */ #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) /*! @} */ /*! @name MIER - Master Interrupt Enable Register */ /*! @{ */ #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) #define LPI2C_MIER_RDIE_MASK (0x2U) #define LPI2C_MIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) #define LPI2C_MIER_EPIE_MASK (0x100U) #define LPI2C_MIER_EPIE_SHIFT (8U) /*! EPIE - End Packet Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) #define LPI2C_MIER_SDIE_MASK (0x200U) #define LPI2C_MIER_SDIE_SHIFT (9U) /*! SDIE - STOP Detect Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) #define LPI2C_MIER_NDIE_MASK (0x400U) #define LPI2C_MIER_NDIE_SHIFT (10U) /*! NDIE - NACK Detect Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) #define LPI2C_MIER_ALIE_MASK (0x800U) #define LPI2C_MIER_ALIE_SHIFT (11U) /*! ALIE - Arbitration Lost Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Enabled * 0b1..Disabled */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) #define LPI2C_MIER_PLTIE_MASK (0x2000U) #define LPI2C_MIER_PLTIE_SHIFT (13U) /*! PLTIE - Pin Low Timeout Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) /*! DMIE - Data Match Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) /*! @} */ /*! @name MDER - Master DMA Enable Register */ /*! @{ */ #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) /*! @} */ /*! @name MCFGR0 - Master Configuration Register 0 */ /*! @{ */ #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) /*! HREN - Host Request Enable * 0b0..Host request input is disabled * 0b1..Host request input is enabled */ #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) /*! HRPOL - Host Request Polarity * 0b0..Active low * 0b1..Active high */ #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) /*! HRSEL - Host Request Select * 0b0..Host request input is pin HREQ * 0b1..Host request input is input trigger */ #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable * 0b0..Circular FIFO is disabled * 0b1..Circular FIFO is enabled */ #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO * 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set */ #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) /*! @} */ /*! @name MCFGR1 - Master Configuration Register 1 */ /*! @{ */ #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) /*! PRESCALE - Prescaler * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) /*! AUTOSTOP - Automatic STOP Generation * 0b0..No effect * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy */ #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) /*! IGNACK - IGNACK * 0b0..LPI2C Master will receive ACK and NACK normally * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK */ #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) /*! TIMECFG - Timeout Configuration * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout */ #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001..Reserved * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) */ #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b000..2-pin open drain mode * 0b001..2-pin output only mode (ultra-fast mode) * 0b010..2-pin push-pull mode * 0b011..4-pin push-pull mode * 0b100..2-pin open drain mode with separate LPI2C slave * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave * 0b110..2-pin push-pull mode with separate LPI2C slave * 0b111..4-pin push-pull mode (inverted outputs) */ #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) /*! @} */ /*! @name MCFGR2 - Master Configuration Register 2 */ /*! @{ */ #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) /*! BUSIDLE - Bus Idle Timeout */ #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA */ #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) /*! @} */ /*! @name MCFGR3 - Master Configuration Register 3 */ /*! @{ */ #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) /*! PINLOW - Pin Low Timeout */ #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) /*! @} */ /*! @name MDMR - Master Data Match Register */ /*! @{ */ #define LPI2C_MDMR_MATCH0_MASK (0xFFU) #define LPI2C_MDMR_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) #define LPI2C_MDMR_MATCH1_SHIFT (16U) /*! MATCH1 - Match 1 Value */ #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) /*! @} */ /*! @name MCCR0 - Master Clock Configuration Register 0 */ /*! @{ */ #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) #define LPI2C_MCCR0_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR0_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR0_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay */ #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) /*! @} */ /*! @name MCCR1 - Master Clock Configuration Register 1 */ /*! @{ */ #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) #define LPI2C_MCCR1_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR1_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR1_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay */ #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) /*! @} */ /*! @name MFCR - Master FIFO Control Register */ /*! @{ */ #define LPI2C_MFCR_TXWATER_MASK (0xFU) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define LPI2C_MFCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define LPI2C_MFCR_RXWATER_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ #define LPI2C_MFCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark */ #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ /*! @} */ /*! @name MFSR - Master FIFO Status Register */ /*! @{ */ #define LPI2C_MFSR_TXCOUNT_MASK (0x1FU) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define LPI2C_MFSR_RXCOUNT_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count */ #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ /*! @} */ /*! @name MTDR - Master Transmit Data Register */ /*! @{ */ #define LPI2C_MTDR_DATA_MASK (0xFFU) #define LPI2C_MTDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) /*! CMD - Command Data * 0b000..Transmit DATA[7:0] * 0b001..Receive (DATA[7:0] + 1) bytes * 0b010..Generate STOP condition * 0b011..Receive and discard (DATA[7:0] + 1) bytes * 0b100..Generate (repeated) START and transmit address in DATA[7:0] * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. */ #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) /*! @} */ /*! @name MRDR - Master Receive Data Register */ /*! @{ */ #define LPI2C_MRDR_DATA_MASK (0xFFU) #define LPI2C_MRDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty * 0b0..Receive FIFO is not empty * 0b1..Receive FIFO is empty */ #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) /*! @} */ /*! @name SCR - Slave Control Register */ /*! @{ */ #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) /*! SEN - Slave Enable * 0b0..I2C Slave mode is disabled * 0b1..I2C Slave mode is enabled */ #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) #define LPI2C_SCR_RST_MASK (0x2U) #define LPI2C_SCR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Slave mode logic is not reset * 0b1..Slave mode logic is reset */ #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) #define LPI2C_SCR_FILTEN_MASK (0x10U) #define LPI2C_SCR_FILTEN_SHIFT (4U) /*! FILTEN - Filter Enable * 0b0..Disable digital filter and output delay counter for slave mode * 0b1..Enable digital filter and output delay counter for slave mode */ #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) #define LPI2C_SCR_FILTDZ_MASK (0x20U) #define LPI2C_SCR_FILTDZ_SHIFT (5U) /*! FILTDZ - Filter Doze Enable * 0b0..Filter remains enabled in Doze mode * 0b1..Filter is disabled in Doze mode */ #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) #define LPI2C_SCR_RTF_MASK (0x100U) #define LPI2C_SCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..Transmit Data Register is now empty */ #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) #define LPI2C_SCR_RRF_MASK (0x200U) #define LPI2C_SCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..Receive Data Register is now empty */ #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) /*! @} */ /*! @name SSR - Slave Status Register */ /*! @{ */ #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data is requested */ #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) #define LPI2C_SSR_RDF_MASK (0x2U) #define LPI2C_SSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive data is not ready * 0b1..Receive data is ready */ #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) #define LPI2C_SSR_AVF_MASK (0x4U) #define LPI2C_SSR_AVF_SHIFT (2U) /*! AVF - Address Valid Flag * 0b0..Address Status Register is not valid * 0b1..Address Status Register is valid */ #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) #define LPI2C_SSR_TAF_MASK (0x8U) #define LPI2C_SSR_TAF_SHIFT (3U) /*! TAF - Transmit ACK Flag * 0b0..Transmit ACK/NACK is not required * 0b1..Transmit ACK/NACK is required */ #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) /*! RSF - Repeated Start Flag * 0b0..Slave has not detected a Repeated START condition * 0b1..Slave has detected a Repeated START condition */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) #define LPI2C_SSR_SDF_MASK (0x200U) #define LPI2C_SSR_SDF_SHIFT (9U) /*! SDF - STOP Detect Flag * 0b0..Slave has not detected a STOP condition * 0b1..Slave has detected a STOP condition */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) #define LPI2C_SSR_BEF_MASK (0x400U) #define LPI2C_SSR_BEF_SHIFT (10U) /*! BEF - Bit Error Flag * 0b0..Slave has not detected a bit error * 0b1..Slave has detected a bit error */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) #define LPI2C_SSR_FEF_MASK (0x800U) #define LPI2C_SSR_FEF_SHIFT (11U) /*! FEF - FIFO Error Flag * 0b0..FIFO underflow or overflow was not detected * 0b1..FIFO underflow or overflow was detected */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) #define LPI2C_SSR_AM0F_MASK (0x1000U) #define LPI2C_SSR_AM0F_SHIFT (12U) /*! AM0F - Address Match 0 Flag * 0b0..Have not received an ADDR0 matching address * 0b1..Have received an ADDR0 matching address */ #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) #define LPI2C_SSR_AM1F_MASK (0x2000U) #define LPI2C_SSR_AM1F_SHIFT (13U) /*! AM1F - Address Match 1 Flag * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address */ #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) #define LPI2C_SSR_GCF_MASK (0x4000U) #define LPI2C_SSR_GCF_SHIFT (14U) /*! GCF - General Call Flag * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled * 0b1..Slave has detected the General Call Address */ #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) #define LPI2C_SSR_SARF_MASK (0x8000U) #define LPI2C_SSR_SARF_SHIFT (15U) /*! SARF - SMBus Alert Response Flag * 0b0..SMBus Alert Response is disabled or not detected * 0b1..SMBus Alert Response is enabled and detected */ #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) #define LPI2C_SSR_SBF_MASK (0x1000000U) #define LPI2C_SSR_SBF_SHIFT (24U) /*! SBF - Slave Busy Flag * 0b0..I2C Slave is idle * 0b1..I2C Slave is busy */ #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag * 0b0..I2C Bus is idle * 0b1..I2C Bus is busy */ #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) /*! @} */ /*! @name SIER - Slave Interrupt Enable Register */ /*! @{ */ #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) #define LPI2C_SIER_RDIE_MASK (0x2U) #define LPI2C_SIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) #define LPI2C_SIER_AVIE_MASK (0x4U) #define LPI2C_SIER_AVIE_SHIFT (2U) /*! AVIE - Address Valid Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) #define LPI2C_SIER_TAIE_MASK (0x8U) #define LPI2C_SIER_TAIE_SHIFT (3U) /*! TAIE - Transmit ACK Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) #define LPI2C_SIER_RSIE_MASK (0x100U) #define LPI2C_SIER_RSIE_SHIFT (8U) /*! RSIE - Repeated Start Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) #define LPI2C_SIER_SDIE_MASK (0x200U) #define LPI2C_SIER_SDIE_SHIFT (9U) /*! SDIE - STOP Detect Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) #define LPI2C_SIER_BEIE_MASK (0x400U) #define LPI2C_SIER_BEIE_SHIFT (10U) /*! BEIE - Bit Error Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) #define LPI2C_SIER_FEIE_MASK (0x800U) #define LPI2C_SIER_FEIE_SHIFT (11U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) #define LPI2C_SIER_AM0IE_MASK (0x1000U) #define LPI2C_SIER_AM0IE_SHIFT (12U) /*! AM0IE - Address Match 0 Interrupt Enable * 0b0..Enabled * 0b1..Disabled */ #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) #define LPI2C_SIER_AM1F_MASK (0x2000U) #define LPI2C_SIER_AM1F_SHIFT (13U) /*! AM1F - Address Match 1 Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) #define LPI2C_SIER_GCIE_MASK (0x4000U) #define LPI2C_SIER_GCIE_SHIFT (14U) /*! GCIE - General Call Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) /*! SARIE - SMBus Alert Response Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) /*! @} */ /*! @name SDER - Slave DMA Enable Register */ /*! @{ */ #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) #define LPI2C_SDER_RDDE_MASK (0x2U) #define LPI2C_SDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) /*! AVDE - Address Valid DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) #define LPI2C_SDER_RSDE_MASK (0x100U) #define LPI2C_SDER_RSDE_SHIFT (8U) /*! RSDE - Repeated Start DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) #define LPI2C_SDER_SDDE_MASK (0x200U) #define LPI2C_SDER_SDDE_SHIFT (9U) /*! SDDE - Stop Detect DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) /*! @} */ /*! @name SCFGR1 - Slave Configuration Register 1 */ /*! @{ */ #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) /*! ADRSTALL - Address SCL Stall * 0b0..Clock stretching is disabled * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) /*! RXSTALL - RX SCL Stall * 0b0..Clock stretching is disabled * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) /*! TXDSTALL - TX Data SCL Stall * 0b0..Clock stretching is disabled * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) /*! ACKSTALL - ACK SCL Stall * 0b0..Clock stretching is disabled * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) #define LPI2C_SCFGR1_GCEN_MASK (0x100U) #define LPI2C_SCFGR1_GCEN_SHIFT (8U) /*! GCEN - General Call Enable * 0b0..General Call address is disabled * 0b1..General Call address is enabled */ #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) #define LPI2C_SCFGR1_SAEN_MASK (0x200U) #define LPI2C_SCFGR1_SAEN_SHIFT (9U) /*! SAEN - SMBus Alert Enable * 0b0..Disables match on SMBus Alert * 0b1..Enables match on SMBus Alert */ #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) /*! TXCFG - Transmit Flag Configuration * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address * Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid * flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) /*! IGNACK - Ignore NACK * 0b0..Slave will end transfer when NACK is detected * 0b1..Slave will not end transfer when NACK detected */ #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) /*! HSMEN - High Speed Mode Enable * 0b0..Disables detection of HS-mode master code * 0b1..Enables detection of HS-mode master code */ #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) /*! ADDRCFG - Address Configuration * 0b000..Address match 0 (7-bit) * 0b001..Address match 0 (10-bit) * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) */ #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) /*! @} */ /*! @name SCFGR2 - Slave Configuration Register 2 */ /*! @{ */ #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) /*! CLKHOLD - Clock Hold Time */ #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) /*! DATAVD - Data Valid Delay */ #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA */ #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) /*! @} */ /*! @name SAMR - Slave Address Match Register */ /*! @{ */ #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) /*! ADDR0 - Address 0 Value */ #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) /*! ADDR1 - Address 1 Value */ #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) /*! @} */ /*! @name SASR - Slave Address Status Register */ /*! @{ */ #define LPI2C_SASR_RADDR_MASK (0x7FFU) #define LPI2C_SASR_RADDR_SHIFT (0U) /*! RADDR - Received Address */ #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) /*! ANV - Address Not Valid * 0b0..Received Address (RADDR) is valid * 0b1..Received Address (RADDR) is not valid */ #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) /*! @} */ /*! @name STAR - Slave Transmit ACK Register */ /*! @{ */ #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) /*! TXNACK - Transmit NACK * 0b0..Write a Transmit ACK for each received word * 0b1..Write a Transmit NACK for each received word */ #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) /*! @} */ /*! @name STDR - Slave Transmit Data Register */ /*! @{ */ #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) /*! @} */ /*! @name SRDR - Slave Receive Data Register */ /*! @{ */ #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty * 0b0..The Receive Data Register is not empty * 0b1..The Receive Data Register is empty */ #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) /*! SOF - Start Of Frame * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition */ #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) /*! @} */ /*! * @} */ /* end of group LPI2C_Register_Masks */ /* LPI2C - Peripheral instance base addresses */ /** Peripheral ADMA__LPI2C0 base address */ #define ADMA__LPI2C0_BASE (0x5A800000u) /** Peripheral ADMA__LPI2C0 base pointer */ #define ADMA__LPI2C0 ((LPI2C_Type *)ADMA__LPI2C0_BASE) /** Peripheral ADMA__LPI2C1 base address */ #define ADMA__LPI2C1_BASE (0x5A810000u) /** Peripheral ADMA__LPI2C1 base pointer */ #define ADMA__LPI2C1 ((LPI2C_Type *)ADMA__LPI2C1_BASE) /** Peripheral ADMA__LPI2C2 base address */ #define ADMA__LPI2C2_BASE (0x5A820000u) /** Peripheral ADMA__LPI2C2 base pointer */ #define ADMA__LPI2C2 ((LPI2C_Type *)ADMA__LPI2C2_BASE) /** Peripheral ADMA__LPI2C3 base address */ #define ADMA__LPI2C3_BASE (0x5A830000u) /** Peripheral ADMA__LPI2C3 base pointer */ #define ADMA__LPI2C3 ((LPI2C_Type *)ADMA__LPI2C3_BASE) /** Peripheral CI_PI__LPI2C0 base address */ #define CI_PI__LPI2C0_BASE (0x58266000u) /** Peripheral CI_PI__LPI2C0 base pointer */ #define CI_PI__LPI2C0 ((LPI2C_Type *)CI_PI__LPI2C0_BASE) /** Peripheral CM4__LPI2C base address */ #define CM4__LPI2C_BASE (0x41230000u) /** Peripheral CM4__LPI2C base pointer */ #define CM4__LPI2C ((LPI2C_Type *)CM4__LPI2C_BASE) /** Peripheral DI_MIPI_DSI_LVDS_0__LPI2C0 base address */ #define DI_MIPI_DSI_LVDS_0__LPI2C0_BASE (0x56226000u) /** Peripheral DI_MIPI_DSI_LVDS_0__LPI2C0 base pointer */ #define DI_MIPI_DSI_LVDS_0__LPI2C0 ((LPI2C_Type *)DI_MIPI_DSI_LVDS_0__LPI2C0_BASE) /** Peripheral DI_MIPI_DSI_LVDS_0__LPI2C1 base address */ #define DI_MIPI_DSI_LVDS_0__LPI2C1_BASE (0x56227000u) /** Peripheral DI_MIPI_DSI_LVDS_0__LPI2C1 base pointer */ #define DI_MIPI_DSI_LVDS_0__LPI2C1 ((LPI2C_Type *)DI_MIPI_DSI_LVDS_0__LPI2C1_BASE) /** Peripheral DI_MIPI_DSI_LVDS_1__LPI2C0 base address */ #define DI_MIPI_DSI_LVDS_1__LPI2C0_BASE (0x56246000u) /** Peripheral DI_MIPI_DSI_LVDS_1__LPI2C0 base pointer */ #define DI_MIPI_DSI_LVDS_1__LPI2C0 ((LPI2C_Type *)DI_MIPI_DSI_LVDS_1__LPI2C0_BASE) /** Peripheral DI_MIPI_DSI_LVDS_1__LPI2C1 base address */ #define DI_MIPI_DSI_LVDS_1__LPI2C1_BASE (0x56247000u) /** Peripheral DI_MIPI_DSI_LVDS_1__LPI2C1 base pointer */ #define DI_MIPI_DSI_LVDS_1__LPI2C1 ((LPI2C_Type *)DI_MIPI_DSI_LVDS_1__LPI2C1_BASE) /** Peripheral MIPI_CSI__LPI2C base address */ #define MIPI_CSI__LPI2C_BASE (0x58226000u) /** Peripheral MIPI_CSI__LPI2C base pointer */ #define MIPI_CSI__LPI2C ((LPI2C_Type *)MIPI_CSI__LPI2C_BASE) /** Peripheral SCU__LPI2C base address */ #define SCU__LPI2C_BASE (0x33230000u) /** Peripheral SCU__LPI2C base pointer */ #define SCU__LPI2C ((LPI2C_Type *)SCU__LPI2C_BASE) /** Array initializer of LPI2C peripheral base addresses */ #define LPI2C_BASE_ADDRS { ADMA__LPI2C0_BASE, ADMA__LPI2C1_BASE, ADMA__LPI2C2_BASE, ADMA__LPI2C3_BASE, CI_PI__LPI2C0_BASE, CM4__LPI2C_BASE, DI_MIPI_DSI_LVDS_0__LPI2C0_BASE, DI_MIPI_DSI_LVDS_0__LPI2C1_BASE, DI_MIPI_DSI_LVDS_1__LPI2C0_BASE, DI_MIPI_DSI_LVDS_1__LPI2C1_BASE, MIPI_CSI__LPI2C_BASE, SCU__LPI2C_BASE } /** Array initializer of LPI2C peripheral base pointers */ #define LPI2C_BASE_PTRS { ADMA__LPI2C0, ADMA__LPI2C1, ADMA__LPI2C2, ADMA__LPI2C3, CI_PI__LPI2C0, CM4__LPI2C, DI_MIPI_DSI_LVDS_0__LPI2C0, DI_MIPI_DSI_LVDS_0__LPI2C1, DI_MIPI_DSI_LVDS_1__LPI2C0, DI_MIPI_DSI_LVDS_1__LPI2C1, MIPI_CSI__LPI2C, SCU__LPI2C } /** Interrupt vectors for the LPI2C peripheral type */ #define LPI2C_IRQS { ADMA_I2C0_INT_IRQn, ADMA_I2C1_INT_IRQn, ADMA_I2C2_INT_IRQn, ADMA_I2C3_INT_IRQn, NotAvail_IRQn, M4_LPI2C_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group LPI2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPIT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer * @{ */ /** LPIT - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */ __IO uint32_t MSR; /**< Module Status Register, offset: 0xC */ __IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */ __IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */ __O uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */ uint8_t RESERVED_0[4]; struct { /* offset: 0x20, array step: 0x10 */ __IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */ __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */ uint8_t RESERVED_0[4]; } CHANNEL[4]; } LPIT_Type; /* ---------------------------------------------------------------------------- -- LPIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPIT_Register_Masks LPIT Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPIT_VERID_FEATURE_MASK (0xFFFFU) #define LPIT_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Number */ #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) #define LPIT_VERID_MINOR_MASK (0xFF0000U) #define LPIT_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) #define LPIT_VERID_MAJOR_MASK (0xFF000000U) #define LPIT_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPIT_PARAM_CHANNEL_MASK (0xFFU) #define LPIT_PARAM_CHANNEL_SHIFT (0U) /*! CHANNEL - Number of Timer Channels */ #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) #define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) #define LPIT_PARAM_EXT_TRIG_SHIFT (8U) /*! EXT_TRIG - Number of External Trigger Inputs */ #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) /*! @} */ /*! @name MCR - Module Control Register */ /*! @{ */ #define LPIT_MCR_M_CEN_MASK (0x1U) #define LPIT_MCR_M_CEN_SHIFT (0U) /*! M_CEN - Module Clock Enable * 0b0..Disable peripheral clock to timers * 0b1..Enable peripheral clock to timers */ #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) #define LPIT_MCR_SW_RST_MASK (0x2U) #define LPIT_MCR_SW_RST_SHIFT (1U) /*! SW_RST - Software Reset Bit * 0b0..Timer channels and registers are not reset * 0b1..Reset timer channels and registers */ #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) #define LPIT_MCR_DOZE_EN_MASK (0x4U) #define LPIT_MCR_DOZE_EN_SHIFT (2U) /*! DOZE_EN - DOZE Mode Enable Bit * 0b0..Stop timer channels in DOZE mode * 0b1..Allow timer channels to continue to run in DOZE mode */ #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) #define LPIT_MCR_DBG_EN_MASK (0x8U) #define LPIT_MCR_DBG_EN_SHIFT (3U) /*! DBG_EN - Debug Enable Bit * 0b0..Stop timer channels in Debug mode * 0b1..Allow timer channels to continue to run in Debug mode */ #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) /*! @} */ /*! @name MSR - Module Status Register */ /*! @{ */ #define LPIT_MSR_TIF0_MASK (0x1U) #define LPIT_MSR_TIF0_SHIFT (0U) /*! TIF0 - Channel 0 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred (timer has timed out) */ #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) #define LPIT_MSR_TIF1_MASK (0x2U) #define LPIT_MSR_TIF1_SHIFT (1U) /*! TIF1 - Channel 1 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred (timer has timed out) */ #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) #define LPIT_MSR_TIF2_MASK (0x4U) #define LPIT_MSR_TIF2_SHIFT (2U) /*! TIF2 - Channel 2 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred (timer has timed out) */ #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) #define LPIT_MSR_TIF3_MASK (0x8U) #define LPIT_MSR_TIF3_SHIFT (3U) /*! TIF3 - Channel 3 Timer Interrupt Flag * 0b0..Timer has not timed out * 0b1..Timeout has occurred (timer has timed out) */ #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) /*! @} */ /*! @name MIER - Module Interrupt Enable Register */ /*! @{ */ #define LPIT_MIER_TIE0_MASK (0x1U) #define LPIT_MIER_TIE0_SHIFT (0U) /*! TIE0 - Channel 0 Timer Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) #define LPIT_MIER_TIE1_MASK (0x2U) #define LPIT_MIER_TIE1_SHIFT (1U) /*! TIE1 - Channel 1 Timer Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) #define LPIT_MIER_TIE2_MASK (0x4U) #define LPIT_MIER_TIE2_SHIFT (2U) /*! TIE2 - Channel 2 Timer Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) #define LPIT_MIER_TIE3_MASK (0x8U) #define LPIT_MIER_TIE3_SHIFT (3U) /*! TIE3 - Channel 3 Timer Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) /*! @} */ /*! @name SETTEN - Set Timer Enable Register */ /*! @{ */ #define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) #define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) /*! SET_T_EN_0 - Set Timer 0 Enable * 0b0..No effect * 0b1..Enables Timer Channel 0 */ #define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) #define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) #define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) /*! SET_T_EN_1 - Set Timer 1 Enable * 0b0..No Effect * 0b1..Enables Timer Channel 1 */ #define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) #define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) #define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) /*! SET_T_EN_2 - Set Timer 2 Enable * 0b0..No Effect * 0b1..Enables Timer Channel 2 */ #define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) #define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) #define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) /*! SET_T_EN_3 - Set Timer 3 Enable * 0b0..No effect * 0b1..Enables Timer Channel 3 */ #define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) /*! @} */ /*! @name CLRTEN - Clear Timer Enable Register */ /*! @{ */ #define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) /*! CLR_T_EN_0 - Clear Timer 0 Enable * 0b0..No action * 0b1..Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0 */ #define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) #define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) /*! CLR_T_EN_1 - Clear Timer 1 Enable * 0b0..No Action * 0b1..Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1 */ #define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) #define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) /*! CLR_T_EN_2 - Clear Timer 2 Enable * 0b0..No Action * 0b1..Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2 */ #define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) #define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) /*! CLR_T_EN_3 - Clear Timer 3 Enable * 0b0..No Action * 0b1..Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3 */ #define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) /*! @} */ /*! @name TVAL - Timer Value Register */ /*! @{ */ #define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) #define LPIT_TVAL_TMR_VAL_SHIFT (0U) /*! TMR_VAL - Timer Value * 0b00000000000000000000000000000000..Invalid load value in compare mode * 0b00000000000000000000000000000001..Invalid load value in compare mode * 0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the value to be loaded; in capture mode, the value of the timer */ #define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK) /*! @} */ /* The count of LPIT_TVAL */ #define LPIT_TVAL_COUNT (4U) /*! @name CVAL - Current Timer Value */ /*! @{ */ #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) #define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U) /*! TMR_CUR_VAL - Current Timer Value */ #define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK) /*! @} */ /* The count of LPIT_CVAL */ #define LPIT_CVAL_COUNT (4U) /*! @name TCTRL - Timer Control Register */ /*! @{ */ #define LPIT_TCTRL_T_EN_MASK (0x1U) #define LPIT_TCTRL_T_EN_SHIFT (0U) /*! T_EN - Timer Enable * 0b0..Timer Channel is disabled * 0b1..Timer Channel is enabled */ #define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK) #define LPIT_TCTRL_CHAIN_MASK (0x2U) #define LPIT_TCTRL_CHAIN_SHIFT (1U) /*! CHAIN - Chain Channel * 0b0..Channel Chaining is disabled. The channel timer runs independently. * 0b1..Channel Chaining is enabled. The timer decrements on the previous channel's timeout. */ #define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK) #define LPIT_TCTRL_MODE_MASK (0xCU) #define LPIT_TCTRL_MODE_SHIFT (2U) /*! MODE - Timer Operation Mode * 0b00..32-bit Periodic Counter * 0b01..Dual 16-bit Periodic Counter * 0b10..32-bit Trigger Accumulator * 0b11..32-bit Trigger Input Capture */ #define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK) #define LPIT_TCTRL_TSOT_MASK (0x10000U) #define LPIT_TCTRL_TSOT_SHIFT (16U) /*! TSOT - Timer Start On Trigger * 0b0..Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) * 0b1..Timer starts to decrement when a rising edge on a selected trigger is detected */ #define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK) #define LPIT_TCTRL_TSOI_MASK (0x20000U) #define LPIT_TCTRL_TSOI_SHIFT (17U) /*! TSOI - Timer Stop On Interrupt * 0b0..The channel timer does not stop after timeout * 0b1..The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On * Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable * bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, * the channel timer will restart after a rising edge on the selected trigger is detected. */ #define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK) #define LPIT_TCTRL_TROT_MASK (0x40000U) #define LPIT_TCTRL_TROT_SHIFT (18U) /*! TROT - Timer Reload On Trigger * 0b0..Timer will not reload on the selected trigger * 0b1..Timer will reload on the selected trigger */ #define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK) #define LPIT_TCTRL_TRG_SRC_MASK (0x800000U) #define LPIT_TCTRL_TRG_SRC_SHIFT (23U) /*! TRG_SRC - Trigger Source * 0b0..Selects external triggers * 0b1..Selects internal triggers */ #define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK) #define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U) #define LPIT_TCTRL_TRG_SEL_SHIFT (24U) /*! TRG_SEL - Trigger Select * 0b0000-0b0011..Timer channel 0 - 3 trigger source is selected * 0b0100-0b1111..Reserved */ #define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK) /*! @} */ /* The count of LPIT_TCTRL */ #define LPIT_TCTRL_COUNT (4U) /*! * @} */ /* end of group LPIT_Register_Masks */ /* LPIT - Peripheral instance base addresses */ /** Peripheral CM4__LPIT base address */ #define CM4__LPIT_BASE (0x41210000u) /** Peripheral CM4__LPIT base pointer */ #define CM4__LPIT ((LPIT_Type *)CM4__LPIT_BASE) /** Peripheral SCU__LPIT base address */ #define SCU__LPIT_BASE (0x33210000u) /** Peripheral SCU__LPIT base pointer */ #define SCU__LPIT ((LPIT_Type *)SCU__LPIT_BASE) /** Array initializer of LPIT peripheral base addresses */ #define LPIT_BASE_ADDRS { CM4__LPIT_BASE, SCU__LPIT_BASE } /** Array initializer of LPIT peripheral base pointers */ #define LPIT_BASE_PTRS { CM4__LPIT, SCU__LPIT } /** Interrupt vectors for the LPIT peripheral type */ #define LPIT_IRQS { { M4_LPIT_IRQn, M4_LPIT_IRQn, M4_LPIT_IRQn, M4_LPIT_IRQn }, { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } } /*! * @} */ /* end of group LPIT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer * @{ */ /** LPSPI - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t CR; /**< Control Register, offset: 0x10 */ __IO uint32_t SR; /**< Status Register, offset: 0x14 */ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ uint8_t RESERVED_2[8]; __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ uint8_t RESERVED_3[20]; __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ uint8_t RESERVED_4[8]; __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ } LPSPI_Type; /* ---------------------------------------------------------------------------- -- LPSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPSPI_Register_Masks LPSPI Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) #define LPSPI_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Module Identification Number * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. */ #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) #define LPSPI_VERID_MINOR_MASK (0xFF0000U) #define LPSPI_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) #define LPSPI_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) #define LPSPI_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) #define LPSPI_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) /*! @} */ /*! @name CR - Control Register */ /*! @{ */ #define LPSPI_CR_MEN_MASK (0x1U) #define LPSPI_CR_MEN_SHIFT (0U) /*! MEN - Module Enable * 0b0..Module is disabled * 0b1..Module is enabled */ #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) #define LPSPI_CR_RST_MASK (0x2U) #define LPSPI_CR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Module is not reset * 0b1..Module is reset */ #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) #define LPSPI_CR_DOZEN_MASK (0x4U) #define LPSPI_CR_DOZEN_SHIFT (2U) /*! DOZEN - Doze Mode Enable * 0b0..LPSPI module is enabled in Doze mode * 0b1..LPSPI module is disabled in Doze mode */ #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) #define LPSPI_CR_DBGEN_MASK (0x8U) #define LPSPI_CR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable * 0b0..LPSPI module is disabled in debug mode * 0b1..LPSPI module is enabled in debug mode */ #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) #define LPSPI_CR_RTF_MASK (0x100U) #define LPSPI_CR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..Transmit FIFO is reset */ #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) #define LPSPI_CR_RRF_MASK (0x200U) #define LPSPI_CR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..Receive FIFO is reset */ #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define LPSPI_SR_TDF_MASK (0x1U) #define LPSPI_SR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data is requested */ #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) #define LPSPI_SR_RDF_MASK (0x2U) #define LPSPI_SR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive Data is not ready * 0b1..Receive data is ready */ #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) #define LPSPI_SR_WCF_MASK (0x100U) #define LPSPI_SR_WCF_SHIFT (8U) /*! WCF - Word Complete Flag * 0b0..Transfer of a received word has not yet completed * 0b1..Transfer of a received word has completed */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) #define LPSPI_SR_FCF_MASK (0x200U) #define LPSPI_SR_FCF_SHIFT (9U) /*! FCF - Frame Complete Flag * 0b0..Frame transfer has not completed * 0b1..Frame transfer has completed */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) #define LPSPI_SR_TCF_MASK (0x400U) #define LPSPI_SR_TCF_SHIFT (10U) /*! TCF - Transfer Complete Flag * 0b0..All transfers have not completed * 0b1..All transfers have completed */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) #define LPSPI_SR_TEF_MASK (0x800U) #define LPSPI_SR_TEF_SHIFT (11U) /*! TEF - Transmit Error Flag * 0b0..Transmit FIFO underrun has not occurred * 0b1..Transmit FIFO underrun has occurred */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) #define LPSPI_SR_REF_MASK (0x1000U) #define LPSPI_SR_REF_SHIFT (12U) /*! REF - Receive Error Flag * 0b0..Receive FIFO has not overflowed * 0b1..Receive FIFO has overflowed */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) #define LPSPI_SR_DMF_MASK (0x2000U) #define LPSPI_SR_DMF_SHIFT (13U) /*! DMF - Data Match Flag * 0b0..Have not received matching data * 0b1..Have received matching data */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) #define LPSPI_SR_MBF_MASK (0x1000000U) #define LPSPI_SR_MBF_SHIFT (24U) /*! MBF - Module Busy Flag * 0b0..LPSPI is idle * 0b1..LPSPI is busy */ #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) /*! @} */ /*! @name IER - Interrupt Enable Register */ /*! @{ */ #define LPSPI_IER_TDIE_MASK (0x1U) #define LPSPI_IER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) #define LPSPI_IER_RDIE_MASK (0x2U) #define LPSPI_IER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) #define LPSPI_IER_WCIE_MASK (0x100U) #define LPSPI_IER_WCIE_SHIFT (8U) /*! WCIE - Word Complete Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) #define LPSPI_IER_FCIE_MASK (0x200U) #define LPSPI_IER_FCIE_SHIFT (9U) /*! FCIE - Frame Complete Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) #define LPSPI_IER_TCIE_MASK (0x400U) #define LPSPI_IER_TCIE_SHIFT (10U) /*! TCIE - Transfer Complete Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) #define LPSPI_IER_TEIE_MASK (0x800U) #define LPSPI_IER_TEIE_SHIFT (11U) /*! TEIE - Transmit Error Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) #define LPSPI_IER_REIE_MASK (0x1000U) #define LPSPI_IER_REIE_SHIFT (12U) /*! REIE - Receive Error Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) #define LPSPI_IER_DMIE_MASK (0x2000U) #define LPSPI_IER_DMIE_SHIFT (13U) /*! DMIE - Data Match Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) /*! @} */ /*! @name DER - DMA Enable Register */ /*! @{ */ #define LPSPI_DER_TDDE_MASK (0x1U) #define LPSPI_DER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) #define LPSPI_DER_RDDE_MASK (0x2U) #define LPSPI_DER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) #define LPSPI_DER_FCDE_MASK (0x200U) #define LPSPI_DER_FCDE_SHIFT (9U) /*! FCDE - Frame Complete DMA Enable * 0b0..DMA request is disabled * 0b1..DMA request is enabled */ #define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) /*! @} */ /*! @name CFGR0 - Configuration Register 0 */ /*! @{ */ #define LPSPI_CFGR0_HREN_MASK (0x1U) #define LPSPI_CFGR0_HREN_SHIFT (0U) /*! HREN - Host Request Enable * 0b0..Host request is disabled * 0b1..Host request is enabled */ #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) #define LPSPI_CFGR0_HRPOL_MASK (0x2U) #define LPSPI_CFGR0_HRPOL_SHIFT (1U) /*! HRPOL - Host Request Polarity * 0b0..Active low * 0b1..Active high */ #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) #define LPSPI_CFGR0_HRSEL_MASK (0x4U) #define LPSPI_CFGR0_HRSEL_SHIFT (2U) /*! HRSEL - Host Request Select * 0b0..Host request input is the LPSPI_HREQ pin * 0b1..Host request input is the input trigger */ #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable * 0b0..Circular FIFO is disabled * 0b1..Circular FIFO is enabled */ #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) #define LPSPI_CFGR0_RDMO_MASK (0x200U) #define LPSPI_CFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO as in normal operations * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set */ #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) /*! @} */ /*! @name CFGR1 - Configuration Register 1 */ /*! @{ */ #define LPSPI_CFGR1_MASTER_MASK (0x1U) #define LPSPI_CFGR1_MASTER_SHIFT (0U) /*! MASTER - Master Mode * 0b0..Slave mode * 0b1..Master mode */ #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) /*! SAMPLE - Sample Point * 0b0..Input data is sampled on SCK edge * 0b1..Input data is sampled on delayed SCK edge */ #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) /*! AUTOPCS - Automatic PCS * 0b0..Automatic PCS generation is disabled * 0b1..Automatic PCS generation is enabled */ #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) /*! NOSTALL - No Stall * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur */ #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) /*! PCSPOL - Peripheral Chip Select Polarity */ #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) #define LPSPI_CFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001..Reserved * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st * data word = MATCH0) * (2nd data word = MATCH1)] * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., * [(any data word = MATCH0) * (next data word = MATCH1)] * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] */ #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) #define LPSPI_CFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b00..SIN is used for input data and SOUT is used for output data * 0b01..SIN is used for both input and output data * 0b10..SOUT is used for both input and output data * 0b11..SOUT is used for input data and SIN is used for output data */ #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) /*! OUTCFG - Output Configuration * 0b0..Output data retains last value when chip select is negated * 0b1..Output data is tristated when chip select is negated */ #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) /*! PCSCFG - Peripheral Chip Select Configuration * 0b0..PCS[3:2] are enabled * 0b1..PCS[3:2] are disabled */ #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) /*! @} */ /*! @name DMR0 - Data Match Register 0 */ /*! @{ */ #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) #define LPSPI_DMR0_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) /*! @} */ /*! @name DMR1 - Data Match Register 1 */ /*! @{ */ #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) #define LPSPI_DMR1_MATCH1_SHIFT (0U) /*! MATCH1 - Match 1 Value */ #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) /*! @} */ /*! @name CCR - Clock Configuration Register */ /*! @{ */ #define LPSPI_CCR_SCKDIV_MASK (0xFFU) #define LPSPI_CCR_SCKDIV_SHIFT (0U) /*! SCKDIV - SCK Divider */ #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) #define LPSPI_CCR_DBT_MASK (0xFF00U) #define LPSPI_CCR_DBT_SHIFT (8U) /*! DBT - Delay Between Transfers */ #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) #define LPSPI_CCR_PCSSCK_SHIFT (16U) /*! PCSSCK - PCS-to-SCK Delay */ #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) #define LPSPI_CCR_SCKPCS_SHIFT (24U) /*! SCKPCS - SCK-to-PCS Delay */ #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) /*! @} */ /*! @name FCR - FIFO Control Register */ /*! @{ */ #define LPSPI_FCR_TXWATER_MASK (0x3FU) #define LPSPI_FCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) #define LPSPI_FCR_RXWATER_MASK (0x3F0000U) #define LPSPI_FCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark */ #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) /*! @} */ /*! @name FSR - FIFO Status Register */ /*! @{ */ #define LPSPI_FSR_TXCOUNT_MASK (0x7FU) #define LPSPI_FSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) #define LPSPI_FSR_RXCOUNT_MASK (0x7F0000U) #define LPSPI_FSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count */ #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) /*! @} */ /*! @name TCR - Transmit Command Register */ /*! @{ */ #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) #define LPSPI_TCR_FRAMESZ_SHIFT (0U) /*! FRAMESZ - Frame Size */ #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) #define LPSPI_TCR_WIDTH_MASK (0x30000U) #define LPSPI_TCR_WIDTH_SHIFT (16U) /*! WIDTH - Transfer Width * 0b00..1 bit transfer * 0b01..2 bit transfer * 0b10..4 bit transfer * 0b11..Reserved */ #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) #define LPSPI_TCR_TXMSK_MASK (0x40000U) #define LPSPI_TCR_TXMSK_SHIFT (18U) /*! TXMSK - Transmit Data Mask * 0b0..Normal transfer * 0b1..Mask transmit data */ #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) #define LPSPI_TCR_RXMSK_MASK (0x80000U) #define LPSPI_TCR_RXMSK_SHIFT (19U) /*! RXMSK - Receive Data Mask * 0b0..Normal transfer * 0b1..Receive data is masked */ #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) #define LPSPI_TCR_CONTC_MASK (0x100000U) #define LPSPI_TCR_CONTC_SHIFT (20U) /*! CONTC - Continuing Command * 0b0..Command word for start of new transfer * 0b1..Command word for continuing transfer */ #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) #define LPSPI_TCR_CONT_MASK (0x200000U) #define LPSPI_TCR_CONT_SHIFT (21U) /*! CONT - Continuous Transfer * 0b0..Continuous transfer is disabled * 0b1..Continuous transfer is enabled */ #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) #define LPSPI_TCR_BYSW_MASK (0x400000U) #define LPSPI_TCR_BYSW_SHIFT (22U) /*! BYSW - Byte Swap * 0b0..Byte swap is disabled * 0b1..Byte swap is enabled */ #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) #define LPSPI_TCR_LSBF_MASK (0x800000U) #define LPSPI_TCR_LSBF_SHIFT (23U) /*! LSBF - LSB First * 0b0..Data is transferred MSB first * 0b1..Data is transferred LSB first */ #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) #define LPSPI_TCR_PCS_MASK (0x3000000U) #define LPSPI_TCR_PCS_SHIFT (24U) /*! PCS - Peripheral Chip Select * 0b00..Transfer using LPSPI_PCS[0] * 0b01..Transfer using LPSPI_PCS[1] * 0b10..Transfer using LPSPI_PCS[2] * 0b11..Transfer using LPSPI_PCS[3] */ #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) #define LPSPI_TCR_PRESCALE_SHIFT (27U) /*! PRESCALE - Prescaler Value * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) #define LPSPI_TCR_CPHA_MASK (0x40000000U) #define LPSPI_TCR_CPHA_SHIFT (30U) /*! CPHA - Clock Phase * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK */ #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) #define LPSPI_TCR_CPOL_MASK (0x80000000U) #define LPSPI_TCR_CPOL_SHIFT (31U) /*! CPOL - Clock Polarity * 0b0..The inactive state value of SCK is low * 0b1..The inactive state value of SCK is high */ #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) /*! @} */ /*! @name TDR - Transmit Data Register */ /*! @{ */ #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) /*! @} */ /*! @name RSR - Receive Status Register */ /*! @{ */ #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) /*! SOF - Start Of Frame * 0b0..Subsequent data word received after LPSPI_PCS assertion * 0b1..First data word received after LPSPI_PCS assertion */ #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) #define LPSPI_RSR_RXEMPTY_MASK (0x2U) #define LPSPI_RSR_RXEMPTY_SHIFT (1U) /*! RXEMPTY - RX FIFO Empty * 0b0..RX FIFO is not empty * 0b1..RX FIFO is empty */ #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) /*! @} */ /*! @name RDR - Receive Data Register */ /*! @{ */ #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group LPSPI_Register_Masks */ /* LPSPI - Peripheral instance base addresses */ /** Peripheral ADMA__LPSPI0 base address */ #define ADMA__LPSPI0_BASE (0x5A000000u) /** Peripheral ADMA__LPSPI0 base pointer */ #define ADMA__LPSPI0 ((LPSPI_Type *)ADMA__LPSPI0_BASE) /** Peripheral ADMA__LPSPI1 base address */ #define ADMA__LPSPI1_BASE (0x5A010000u) /** Peripheral ADMA__LPSPI1 base pointer */ #define ADMA__LPSPI1 ((LPSPI_Type *)ADMA__LPSPI1_BASE) /** Peripheral ADMA__LPSPI2 base address */ #define ADMA__LPSPI2_BASE (0x5A020000u) /** Peripheral ADMA__LPSPI2 base pointer */ #define ADMA__LPSPI2 ((LPSPI_Type *)ADMA__LPSPI2_BASE) /** Peripheral ADMA__LPSPI3 base address */ #define ADMA__LPSPI3_BASE (0x5A030000u) /** Peripheral ADMA__LPSPI3 base pointer */ #define ADMA__LPSPI3 ((LPSPI_Type *)ADMA__LPSPI3_BASE) /** Array initializer of LPSPI peripheral base addresses */ #define LPSPI_BASE_ADDRS { ADMA__LPSPI0_BASE, ADMA__LPSPI1_BASE, ADMA__LPSPI2_BASE, ADMA__LPSPI3_BASE } /** Array initializer of LPSPI peripheral base pointers */ #define LPSPI_BASE_PTRS { ADMA__LPSPI0, ADMA__LPSPI1, ADMA__LPSPI2, ADMA__LPSPI3 } /** Interrupt vectors for the LPSPI peripheral type */ #define LPSPI_IRQS { ADMA_SPI0_INT_IRQn, ADMA_SPI1_INT_IRQn, ADMA_SPI2_INT_IRQn, ADMA_SPI3_INT_IRQn } /*! * @} */ /* end of group LPSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPUART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer * @{ */ /** LPUART - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ } LPUART_Type; /* ---------------------------------------------------------------------------- -- LPUART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Register_Masks LPUART Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define LPUART_VERID_FEATURE_MASK (0xFFFFU) #define LPUART_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number * 0b0000000000000001..Standard feature set. * 0b0000000000000011..Standard feature set with MODEM/IrDA support. */ #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) #define LPUART_VERID_MINOR_MASK (0xFF0000U) #define LPUART_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) #define LPUART_VERID_MAJOR_MASK (0xFF000000U) #define LPUART_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define LPUART_PARAM_TXFIFO_MASK (0xFFU) #define LPUART_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) #define LPUART_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) /*! @} */ /*! @name GLOBAL - LPUART Global Register */ /*! @{ */ #define LPUART_GLOBAL_RST_MASK (0x2U) #define LPUART_GLOBAL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Module is not reset. * 0b1..Module is reset. */ #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) /*! @} */ /*! @name PINCFG - LPUART Pin Configuration Register */ /*! @{ */ #define LPUART_PINCFG_TRGSEL_MASK (0x3U) #define LPUART_PINCFG_TRGSEL_SHIFT (0U) /*! TRGSEL - Trigger Select * 0b00..Input trigger is disabled. * 0b01..Input trigger is used instead of RX pin input. * 0b10..Input trigger is used instead of CTS_B pin input. * 0b11..Input trigger is used to modulate the TX pin output. The TX pin output (after TXINV configuration) is ANDed with the input trigger. */ #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) /*! @} */ /*! @name BAUD - LPUART Baud Rate Register */ /*! @{ */ #define LPUART_BAUD_SBR_MASK (0x1FFFU) #define LPUART_BAUD_SBR_SHIFT (0U) /*! SBR - Baud Rate Modulo Divisor. */ #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) #define LPUART_BAUD_SBNS_MASK (0x2000U) #define LPUART_BAUD_SBNS_SHIFT (13U) /*! SBNS - Stop Bit Number Select * 0b0..One stop bit. * 0b1..Two stop bits. */ #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) #define LPUART_BAUD_RXEDGIE_SHIFT (14U) /*! RXEDGIE - RX Input Active Edge Interrupt Enable * 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. */ #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) #define LPUART_BAUD_LBKDIE_MASK (0x8000U) #define LPUART_BAUD_LBKDIE_SHIFT (15U) /*! LBKDIE - LIN Break Detect Interrupt Enable * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1. */ #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) /*! RESYNCDIS - Resynchronization Disable * 0b0..Resynchronization during received data word is supported * 0b1..Resynchronization during received data word is disabled */ #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) /*! BOTHEDGE - Both Edge Sampling * 0b0..Receiver samples input data using the rising edge of the baud rate clock. * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. */ #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) /*! MATCFG - Match Configuration * 0b00..Address Match Wakeup * 0b01..Idle Match Wakeup * 0b10..Match On and Match Off * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) #define LPUART_BAUD_RIDMAE_MASK (0x100000U) #define LPUART_BAUD_RIDMAE_SHIFT (20U) /*! RIDMAE - Receiver Idle DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) /*! RDMAE - Receiver Full DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) #define LPUART_BAUD_TDMAE_MASK (0x800000U) #define LPUART_BAUD_TDMAE_SHIFT (23U) /*! TDMAE - Transmitter DMA Enable * 0b0..DMA request disabled. * 0b1..DMA request enabled. */ #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) #define LPUART_BAUD_OSR_MASK (0x1F000000U) #define LPUART_BAUD_OSR_SHIFT (24U) /*! OSR - Oversampling Ratio * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 * 0b00001..Reserved * 0b00010..Reserved * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. * 0b00111..Oversampling ratio of 8. * 0b01000..Oversampling ratio of 9. * 0b01001..Oversampling ratio of 10. * 0b01010..Oversampling ratio of 11. * 0b01011..Oversampling ratio of 12. * 0b01100..Oversampling ratio of 13. * 0b01101..Oversampling ratio of 14. * 0b01110..Oversampling ratio of 15. * 0b01111..Oversampling ratio of 16. * 0b10000..Oversampling ratio of 17. * 0b10001..Oversampling ratio of 18. * 0b10010..Oversampling ratio of 19. * 0b10011..Oversampling ratio of 20. * 0b10100..Oversampling ratio of 21. * 0b10101..Oversampling ratio of 22. * 0b10110..Oversampling ratio of 23. * 0b10111..Oversampling ratio of 24. * 0b11000..Oversampling ratio of 25. * 0b11001..Oversampling ratio of 26. * 0b11010..Oversampling ratio of 27. * 0b11011..Oversampling ratio of 28. * 0b11100..Oversampling ratio of 29. * 0b11101..Oversampling ratio of 30. * 0b11110..Oversampling ratio of 31. * 0b11111..Oversampling ratio of 32. */ #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) #define LPUART_BAUD_M10_MASK (0x20000000U) #define LPUART_BAUD_M10_SHIFT (29U) /*! M10 - 10-bit Mode select * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. * 0b1..Receiver and transmitter use 10-bit data characters. */ #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) #define LPUART_BAUD_MAEN2_MASK (0x40000000U) #define LPUART_BAUD_MAEN2_SHIFT (30U) /*! MAEN2 - Match Address Mode Enable 2 * 0b0..Normal operation. * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. */ #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) /*! MAEN1 - Match Address Mode Enable 1 * 0b0..Normal operation. * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. */ #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) /*! @} */ /*! @name STAT - LPUART Status Register */ /*! @{ */ #define LPUART_STAT_MA2F_MASK (0x4000U) #define LPUART_STAT_MA2F_SHIFT (14U) /*! MA2F - Match 2 Flag * 0b0..Received data is not equal to MA2 * 0b1..Received data is equal to MA2 */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) #define LPUART_STAT_MA1F_MASK (0x8000U) #define LPUART_STAT_MA1F_SHIFT (15U) /*! MA1F - Match 1 Flag * 0b0..Received data is not equal to MA1 * 0b1..Received data is equal to MA1 */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) /*! PF - Parity Error Flag * 0b0..No parity error. * 0b1..Parity error. */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) /*! FE - Framing Error Flag * 0b0..No framing error detected. This does not guarantee the framing is correct. * 0b1..Framing error. */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) /*! NF - Noise Flag * 0b0..No noise detected. * 0b1..Noise detected in the received character in the DATA register. */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) #define LPUART_STAT_OR_MASK (0x80000U) #define LPUART_STAT_OR_SHIFT (19U) /*! OR - Receiver Overrun Flag * 0b0..No overrun. * 0b1..Receive overrun (new LPUART data lost). */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) #define LPUART_STAT_IDLE_MASK (0x100000U) #define LPUART_STAT_IDLE_SHIFT (20U) /*! IDLE - Idle Line Flag * 0b0..No idle line detected. * 0b1..Idle line was detected. */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) #define LPUART_STAT_RDRF_MASK (0x200000U) #define LPUART_STAT_RDRF_SHIFT (21U) /*! RDRF - Receive Data Register Full Flag * 0b0..Receive data buffer empty. * 0b1..Receive data buffer full. */ #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) #define LPUART_STAT_TC_MASK (0x400000U) #define LPUART_STAT_TC_SHIFT (22U) /*! TC - Transmission Complete Flag * 0b0..Transmitter active (sending data, a preamble, or a break). * 0b1..Transmitter idle (transmission activity complete). */ #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) #define LPUART_STAT_TDRE_MASK (0x800000U) #define LPUART_STAT_TDRE_SHIFT (23U) /*! TDRE - Transmit Data Register Empty Flag * 0b0..Transmit data buffer full. * 0b1..Transmit data buffer empty. */ #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) #define LPUART_STAT_RAF_MASK (0x1000000U) #define LPUART_STAT_RAF_SHIFT (24U) /*! RAF - Receiver Active Flag * 0b0..LPUART receiver idle waiting for a start bit. * 0b1..LPUART receiver active (RX input not idle). */ #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) #define LPUART_STAT_LBKDE_MASK (0x2000000U) #define LPUART_STAT_LBKDE_SHIFT (25U) /*! LBKDE - LIN Break Detection Enable * 0b0..LIN break detect is disabled, normal break character can be detected. * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). */ #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) #define LPUART_STAT_BRK13_MASK (0x4000000U) #define LPUART_STAT_BRK13_SHIFT (26U) /*! BRK13 - Break Character Generation Length * 0b0..Break character is transmitted with length of 9 to 13 bit times. * 0b1..Break character is transmitted with length of 12 to 15 bit times. */ #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) #define LPUART_STAT_RWUID_MASK (0x8000000U) #define LPUART_STAT_RWUID_SHIFT (27U) /*! RWUID - Receive Wake Up Idle Detect * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle * character. During address match wakeup, the IDLE bit does not set when an address does not match. * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During * address match wakeup, the IDLE bit does set when an address does not match. */ #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) #define LPUART_STAT_RXINV_MASK (0x10000000U) #define LPUART_STAT_RXINV_SHIFT (28U) /*! RXINV - Receive Data Inversion * 0b0..Receive data not inverted. * 0b1..Receive data inverted. */ #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) #define LPUART_STAT_MSBF_MASK (0x20000000U) #define LPUART_STAT_MSBF_SHIFT (29U) /*! MSBF - MSB First * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received * after the start bit is identified as bit0. * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on * the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is * identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. */ #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) #define LPUART_STAT_RXEDGIF_SHIFT (30U) /*! RXEDGIF - RX Pin Active Edge Interrupt Flag * 0b0..No active edge on the receive pin has occurred. * 0b1..An active edge on the receive pin has occurred. */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) #define LPUART_STAT_LBKDIF_MASK (0x80000000U) #define LPUART_STAT_LBKDIF_SHIFT (31U) /*! LBKDIF - LIN Break Detect Interrupt Flag * 0b0..No LIN break character has been detected. * 0b1..LIN break character has been detected. */ #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) /*! @} */ /*! @name CTRL - LPUART Control Register */ /*! @{ */ #define LPUART_CTRL_PT_MASK (0x1U) #define LPUART_CTRL_PT_SHIFT (0U) /*! PT - Parity Type * 0b0..Even parity. * 0b1..Odd parity. */ #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) #define LPUART_CTRL_PE_MASK (0x2U) #define LPUART_CTRL_PE_SHIFT (1U) /*! PE - Parity Enable * 0b0..No hardware parity generation or checking. * 0b1..Parity enabled. */ #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) #define LPUART_CTRL_ILT_MASK (0x4U) #define LPUART_CTRL_ILT_SHIFT (2U) /*! ILT - Idle Line Type Select * 0b0..Idle character bit count starts after start bit. * 0b1..Idle character bit count starts after stop bit. */ #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) #define LPUART_CTRL_WAKE_MASK (0x8U) #define LPUART_CTRL_WAKE_SHIFT (3U) /*! WAKE - Receiver Wakeup Method Select * 0b0..Configures RWU for idle-line wakeup. * 0b1..Configures RWU with address-mark wakeup. */ #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) #define LPUART_CTRL_M_MASK (0x10U) #define LPUART_CTRL_M_SHIFT (4U) /*! M - 9-Bit or 8-Bit Mode Select * 0b0..Receiver and transmitter use 8-bit data characters. * 0b1..Receiver and transmitter use 9-bit data characters. */ #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) #define LPUART_CTRL_RSRC_MASK (0x20U) #define LPUART_CTRL_RSRC_SHIFT (5U) /*! RSRC - Receiver Source Select * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RX pin. * 0b1..Single-wire LPUART mode where the TX pin is connected to the transmitter output and receiver input. */ #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) #define LPUART_CTRL_DOZEEN_MASK (0x40U) #define LPUART_CTRL_DOZEEN_SHIFT (6U) /*! DOZEEN - Doze Enable * 0b0..LPUART is enabled in Doze mode. * 0b1..LPUART is disabled in Doze mode. */ #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) #define LPUART_CTRL_LOOPS_MASK (0x80U) #define LPUART_CTRL_LOOPS_SHIFT (7U) /*! LOOPS - Loop Mode Select * 0b0..Normal operation - RX and TX use separate pins. * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). */ #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) #define LPUART_CTRL_IDLECFG_MASK (0x700U) #define LPUART_CTRL_IDLECFG_SHIFT (8U) /*! IDLECFG - Idle Configuration * 0b000..1 idle character * 0b001..2 idle characters * 0b010..4 idle characters * 0b011..8 idle characters * 0b100..16 idle characters * 0b101..32 idle characters * 0b110..64 idle characters * 0b111..128 idle characters */ #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) #define LPUART_CTRL_M7_MASK (0x800U) #define LPUART_CTRL_M7_SHIFT (11U) /*! M7 - 7-Bit Mode Select * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. * 0b1..Receiver and transmitter use 7-bit data characters. */ #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) #define LPUART_CTRL_MA2IE_MASK (0x4000U) #define LPUART_CTRL_MA2IE_SHIFT (14U) /*! MA2IE - Match 2 Interrupt Enable * 0b0..MA2F interrupt disabled * 0b1..MA2F interrupt enabled */ #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) #define LPUART_CTRL_MA1IE_MASK (0x8000U) #define LPUART_CTRL_MA1IE_SHIFT (15U) /*! MA1IE - Match 1 Interrupt Enable * 0b0..MA1F interrupt disabled * 0b1..MA1F interrupt enabled */ #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) #define LPUART_CTRL_SBK_MASK (0x10000U) #define LPUART_CTRL_SBK_SHIFT (16U) /*! SBK - Send Break * 0b0..Normal transmitter operation. * 0b1..Queue break character(s) to be sent. */ #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) #define LPUART_CTRL_RWU_MASK (0x20000U) #define LPUART_CTRL_RWU_SHIFT (17U) /*! RWU - Receiver Wakeup Control * 0b0..Normal receiver operation. * 0b1..LPUART receiver in standby waiting for wakeup condition. */ #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) #define LPUART_CTRL_RE_MASK (0x40000U) #define LPUART_CTRL_RE_SHIFT (18U) /*! RE - Receiver Enable * 0b0..Receiver disabled. * 0b1..Receiver enabled. */ #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) #define LPUART_CTRL_TE_MASK (0x80000U) #define LPUART_CTRL_TE_SHIFT (19U) /*! TE - Transmitter Enable * 0b0..Transmitter disabled. * 0b1..Transmitter enabled. */ #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) #define LPUART_CTRL_ILIE_MASK (0x100000U) #define LPUART_CTRL_ILIE_SHIFT (20U) /*! ILIE - Idle Line Interrupt Enable * 0b0..Hardware interrupts from IDLE disabled; use polling. * 0b1..Hardware interrupt requested when IDLE flag is 1. */ #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) #define LPUART_CTRL_RIE_MASK (0x200000U) #define LPUART_CTRL_RIE_SHIFT (21U) /*! RIE - Receiver Interrupt Enable * 0b0..Hardware interrupts from RDRF disabled; use polling. * 0b1..Hardware interrupt requested when RDRF flag is 1. */ #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) #define LPUART_CTRL_TCIE_MASK (0x400000U) #define LPUART_CTRL_TCIE_SHIFT (22U) /*! TCIE - Transmission Complete Interrupt Enable for * 0b0..Hardware interrupts from TC disabled; use polling. * 0b1..Hardware interrupt requested when TC flag is 1. */ #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) #define LPUART_CTRL_TIE_MASK (0x800000U) #define LPUART_CTRL_TIE_SHIFT (23U) /*! TIE - Transmit Interrupt Enable * 0b0..Hardware interrupts from TDRE disabled; use polling. * 0b1..Hardware interrupt requested when TDRE flag is 1. */ #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) #define LPUART_CTRL_PEIE_MASK (0x1000000U) #define LPUART_CTRL_PEIE_SHIFT (24U) /*! PEIE - Parity Error Interrupt Enable * 0b0..PF interrupts disabled; use polling). * 0b1..Hardware interrupt requested when PF is set. */ #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) #define LPUART_CTRL_FEIE_MASK (0x2000000U) #define LPUART_CTRL_FEIE_SHIFT (25U) /*! FEIE - Framing Error Interrupt Enable * 0b0..FE interrupts disabled; use polling. * 0b1..Hardware interrupt requested when FE is set. */ #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) #define LPUART_CTRL_NEIE_MASK (0x4000000U) #define LPUART_CTRL_NEIE_SHIFT (26U) /*! NEIE - Noise Error Interrupt Enable * 0b0..NF interrupts disabled; use polling. * 0b1..Hardware interrupt requested when NF is set. */ #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) #define LPUART_CTRL_ORIE_MASK (0x8000000U) #define LPUART_CTRL_ORIE_SHIFT (27U) /*! ORIE - Overrun Interrupt Enable * 0b0..OR interrupts disabled; use polling. * 0b1..Hardware interrupt requested when OR is set. */ #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) #define LPUART_CTRL_TXINV_MASK (0x10000000U) #define LPUART_CTRL_TXINV_SHIFT (28U) /*! TXINV - Transmit Data Inversion * 0b0..Transmit data not inverted. * 0b1..Transmit data inverted. */ #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) #define LPUART_CTRL_TXDIR_MASK (0x20000000U) #define LPUART_CTRL_TXDIR_SHIFT (29U) /*! TXDIR - TX Pin Direction in Single-Wire Mode * 0b0..TX pin is an input in single-wire mode. * 0b1..TX pin is an output in single-wire mode. */ #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) #define LPUART_CTRL_R9T8_MASK (0x40000000U) #define LPUART_CTRL_R9T8_SHIFT (30U) /*! R9T8 - Receive Bit 9 / Transmit Bit 8 */ #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) #define LPUART_CTRL_R8T9_MASK (0x80000000U) #define LPUART_CTRL_R8T9_SHIFT (31U) /*! R8T9 - Receive Bit 8 / Transmit Bit 9 */ #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) /*! @} */ /*! @name DATA - LPUART Data Register */ /*! @{ */ #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) /*! R0T0 - R0T0 */ #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) #define LPUART_DATA_R1T1_MASK (0x2U) #define LPUART_DATA_R1T1_SHIFT (1U) /*! R1T1 - R1T1 */ #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) #define LPUART_DATA_R2T2_MASK (0x4U) #define LPUART_DATA_R2T2_SHIFT (2U) /*! R2T2 - R2T2 */ #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) #define LPUART_DATA_R3T3_MASK (0x8U) #define LPUART_DATA_R3T3_SHIFT (3U) /*! R3T3 - R3T3 */ #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) #define LPUART_DATA_R4T4_MASK (0x10U) #define LPUART_DATA_R4T4_SHIFT (4U) /*! R4T4 - R4T4 */ #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) #define LPUART_DATA_R5T5_MASK (0x20U) #define LPUART_DATA_R5T5_SHIFT (5U) /*! R5T5 - R5T5 */ #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) #define LPUART_DATA_R6T6_MASK (0x40U) #define LPUART_DATA_R6T6_SHIFT (6U) /*! R6T6 - R6T6 */ #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) #define LPUART_DATA_R7T7_MASK (0x80U) #define LPUART_DATA_R7T7_SHIFT (7U) /*! R7T7 - R7T7 */ #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) #define LPUART_DATA_R8T8_MASK (0x100U) #define LPUART_DATA_R8T8_SHIFT (8U) /*! R8T8 - R8T8 */ #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) #define LPUART_DATA_R9T9_MASK (0x200U) #define LPUART_DATA_R9T9_SHIFT (9U) /*! R9T9 - R9T9 */ #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) #define LPUART_DATA_IDLINE_MASK (0x800U) #define LPUART_DATA_IDLINE_SHIFT (11U) /*! IDLINE - Idle Line * 0b0..Receiver was not idle before receiving this character. * 0b1..Receiver was idle before receiving this character. */ #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) #define LPUART_DATA_RXEMPT_MASK (0x1000U) #define LPUART_DATA_RXEMPT_SHIFT (12U) /*! RXEMPT - Receive Buffer Empty * 0b0..Receive buffer contains valid data. * 0b1..Receive buffer is empty, data returned on read is not valid. */ #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) #define LPUART_DATA_FRETSC_MASK (0x2000U) #define LPUART_DATA_FRETSC_SHIFT (13U) /*! FRETSC - Frame Error / Transmit Special Character * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. */ #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) #define LPUART_DATA_PARITYE_MASK (0x4000U) #define LPUART_DATA_PARITYE_SHIFT (14U) /*! PARITYE - PARITYE * 0b0..The dataword was received without a parity error. * 0b1..The dataword was received with a parity error. */ #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) #define LPUART_DATA_NOISY_MASK (0x8000U) #define LPUART_DATA_NOISY_SHIFT (15U) /*! NOISY - NOISY * 0b0..The dataword was received without noise. * 0b1..The data was received with noise. */ #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) /*! @} */ /*! @name MATCH - LPUART Match Address Register */ /*! @{ */ #define LPUART_MATCH_MA1_MASK (0x3FFU) #define LPUART_MATCH_MA1_SHIFT (0U) /*! MA1 - Match Address 1 */ #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) #define LPUART_MATCH_MA2_MASK (0x3FF0000U) #define LPUART_MATCH_MA2_SHIFT (16U) /*! MA2 - Match Address 2 */ #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) /*! @} */ /*! @name MODIR - LPUART Modem IrDA Register */ /*! @{ */ #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) /*! TXCTSE - Transmitter clear-to-send enable * 0b0..CTS has no effect on the transmitter. * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a * character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the * mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent * do not affect its transmission. */ #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) #define LPUART_MODIR_TXRTSE_MASK (0x2U) #define LPUART_MODIR_TXRTSE_SHIFT (1U) /*! TXRTSE - Transmitter request-to-send enable * 0b0..The transmitter has no effect on RTS. * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and * shift register are completely sent, including the last stop bit. */ #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) /*! TXRTSPOL - Transmitter request-to-send polarity * 0b0..Transmitter RTS is active low. * 0b1..Transmitter RTS is active high. */ #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) #define LPUART_MODIR_RXRTSE_MASK (0x8U) #define LPUART_MODIR_RXRTSE_SHIFT (3U) /*! RXRTSE - Receiver request-to-send enable * 0b0..The receiver has no effect on RTS. * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause * the receiver data register to become full. RTS is asserted if the receiver data register is not full and * has not detected a start bit that would cause the receiver data register to become full. */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) #define LPUART_MODIR_TXCTSC_MASK (0x10U) #define LPUART_MODIR_TXCTSC_SHIFT (4U) /*! TXCTSC - Transmit CTS Configuration * 0b0..CTS input is sampled at the start of each character. * 0b1..CTS input is sampled when the transmitter is idle. */ #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) /*! TXCTSSRC - Transmit CTS Source * 0b0..CTS input is the CTS_B pin. * 0b1..CTS input is the inverted Receiver Match result. */ #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) #define LPUART_MODIR_RTSWATER_MASK (0x3F00U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define LPUART_MODIR_RTSWATER_SHIFT (8U) /*! RTSWATER - Receive RTS Configuration */ #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define LPUART_MODIR_TNP_MASK (0x30000U) #define LPUART_MODIR_TNP_SHIFT (16U) /*! TNP - Transmitter narrow pulse * 0b00..1/OSR. * 0b01..2/OSR. * 0b10..3/OSR. * 0b11..4/OSR. */ #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) /*! IREN - Infrared enable * 0b0..IR disabled. * 0b1..IR enabled. */ #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) /*! @} */ /*! @name FIFO - LPUART FIFO Register */ /*! @{ */ #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - Receive FIFO Buffer Depth * 0b000..Receive FIFO/Buffer depth = 1 dataword. * 0b001..Receive FIFO/Buffer depth = 4 datawords. * 0b010..Receive FIFO/Buffer depth = 8 datawords. * 0b011..Receive FIFO/Buffer depth = 16 datawords. * 0b100..Receive FIFO/Buffer depth = 32 datawords. * 0b101..Receive FIFO/Buffer depth = 64 datawords. * 0b110..Receive FIFO/Buffer depth = 128 datawords. * 0b111..Receive FIFO/Buffer depth = 256 datawords. */ #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) #define LPUART_FIFO_RXFE_MASK (0x8U) #define LPUART_FIFO_RXFE_SHIFT (3U) /*! RXFE - Receive FIFO Enable * 0b0..Receive FIFO is not enabled. Buffer is depth 1. * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. */ #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) /*! TXFIFOSIZE - Transmit FIFO Buffer Depth * 0b000..Transmit FIFO/Buffer depth = 1 dataword. * 0b001..Transmit FIFO/Buffer depth = 4 datawords. * 0b010..Transmit FIFO/Buffer depth = 8 datawords. * 0b011..Transmit FIFO/Buffer depth = 16 datawords. * 0b100..Transmit FIFO/Buffer depth = 32 datawords. * 0b101..Transmit FIFO/Buffer depth = 64 datawords. * 0b110..Transmit FIFO/Buffer depth = 128 datawords. * 0b111..Transmit FIFO/Buffer depth = 256 datawords */ #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) #define LPUART_FIFO_TXFE_MASK (0x80U) #define LPUART_FIFO_TXFE_SHIFT (7U) /*! TXFE - Transmit FIFO Enable * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. */ #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) #define LPUART_FIFO_RXUFE_MASK (0x100U) #define LPUART_FIFO_RXUFE_SHIFT (8U) /*! RXUFE - Receive FIFO Underflow Interrupt Enable * 0b0..RXUF flag does not generate an interrupt to the host. * 0b1..RXUF flag generates an interrupt to the host. */ #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) #define LPUART_FIFO_TXOFE_MASK (0x200U) #define LPUART_FIFO_TXOFE_SHIFT (9U) /*! TXOFE - Transmit FIFO Overflow Interrupt Enable * 0b0..TXOF flag does not generate an interrupt to the host. * 0b1..TXOF flag generates an interrupt to the host. */ #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) #define LPUART_FIFO_RXIDEN_SHIFT (10U) /*! RXIDEN - Receiver Idle Empty Enable * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. */ #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) #define LPUART_FIFO_RXFLUSH_SHIFT (14U) /*! RXFLUSH - Receive FIFO/Buffer Flush * 0b0..No flush operation occurs. * 0b1..All data in the receive FIFO/buffer is cleared out. */ #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) #define LPUART_FIFO_TXFLUSH_SHIFT (15U) /*! TXFLUSH - Transmit FIFO/Buffer Flush * 0b0..No flush operation occurs. * 0b1..All data in the transmit FIFO/Buffer is cleared out. */ #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) #define LPUART_FIFO_RXUF_MASK (0x10000U) #define LPUART_FIFO_RXUF_SHIFT (16U) /*! RXUF - Receiver Buffer Underflow Flag * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) #define LPUART_FIFO_TXOF_MASK (0x20000U) #define LPUART_FIFO_TXOF_SHIFT (17U) /*! TXOF - Transmitter Buffer Overflow Flag * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) #define LPUART_FIFO_RXEMPT_MASK (0x400000U) #define LPUART_FIFO_RXEMPT_SHIFT (22U) /*! RXEMPT - Receive Buffer/FIFO Empty * 0b0..Receive buffer is not empty. * 0b1..Receive buffer is empty. */ #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) #define LPUART_FIFO_TXEMPT_MASK (0x800000U) #define LPUART_FIFO_TXEMPT_SHIFT (23U) /*! TXEMPT - Transmit Buffer/FIFO Empty * 0b0..Transmit buffer is not empty. * 0b1..Transmit buffer is empty. */ #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) /*! @} */ /*! @name WATER - LPUART Watermark Register */ /*! @{ */ #define LPUART_WATER_TXWATER_MASK (0x3FU) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define LPUART_WATER_TXWATER_SHIFT (0U) /*! TXWATER - Transmit Watermark */ #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define LPUART_WATER_TXCOUNT_MASK (0x7F00U) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define LPUART_WATER_TXCOUNT_SHIFT (8U) /*! TXCOUNT - Transmit Counter */ #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define LPUART_WATER_RXWATER_MASK (0x3F0000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define LPUART_WATER_RXWATER_SHIFT (16U) /*! RXWATER - Receive Watermark */ #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define LPUART_WATER_RXCOUNT_MASK (0x7F000000U) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define LPUART_WATER_RXCOUNT_SHIFT (24U) /*! RXCOUNT - Receive Counter */ #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ /*! @} */ /*! * @} */ /* end of group LPUART_Register_Masks */ /* LPUART - Peripheral instance base addresses */ /** Peripheral ADMA__LPUART0 base address */ #define ADMA__LPUART0_BASE (0x5A060000u) /** Peripheral ADMA__LPUART0 base pointer */ #define ADMA__LPUART0 ((LPUART_Type *)ADMA__LPUART0_BASE) /** Peripheral ADMA__LPUART1 base address */ #define ADMA__LPUART1_BASE (0x5A070000u) /** Peripheral ADMA__LPUART1 base pointer */ #define ADMA__LPUART1 ((LPUART_Type *)ADMA__LPUART1_BASE) /** Peripheral ADMA__LPUART2 base address */ #define ADMA__LPUART2_BASE (0x5A080000u) /** Peripheral ADMA__LPUART2 base pointer */ #define ADMA__LPUART2 ((LPUART_Type *)ADMA__LPUART2_BASE) /** Peripheral ADMA__LPUART3 base address */ #define ADMA__LPUART3_BASE (0x5A090000u) /** Peripheral ADMA__LPUART3 base pointer */ #define ADMA__LPUART3 ((LPUART_Type *)ADMA__LPUART3_BASE) /** Peripheral CM4__LPUART base address */ #define CM4__LPUART_BASE (0x41220000u) /** Peripheral CM4__LPUART base pointer */ #define CM4__LPUART ((LPUART_Type *)CM4__LPUART_BASE) /** Peripheral SCU__LPUART base address */ #define SCU__LPUART_BASE (0x33220000u) /** Peripheral SCU__LPUART base pointer */ #define SCU__LPUART ((LPUART_Type *)SCU__LPUART_BASE) /** Array initializer of LPUART peripheral base addresses */ #define LPUART_BASE_ADDRS { ADMA__LPUART0_BASE, ADMA__LPUART1_BASE, ADMA__LPUART2_BASE, ADMA__LPUART3_BASE, CM4__LPUART_BASE, SCU__LPUART_BASE } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS { ADMA__LPUART0, ADMA__LPUART1, ADMA__LPUART2, ADMA__LPUART3, CM4__LPUART, SCU__LPUART } /** Interrupt vectors for the LPUART peripheral type */ #define LPUART_RX_TX_IRQS { ADMA_UART0_INT_IRQn, ADMA_UART1_INT_IRQn, ADMA_UART2_INT_IRQn, ADMA_UART3_INT_IRQn, M4_LPUART_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group LPUART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO0_Peripheral_Access_Layer LSIO_LPCG_GPIO0 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPIO0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_GPIO0_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPIO0_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO0_Register_Masks LSIO_LPCG_GPIO0 Register Masks * @{ */ /*! @name LPCG_GPIO0_0 - na */ /*! @{ */ #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_MASK (0xFFFFU) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_SHIFT (0U) /*! LPCG_GPIO0_0_reserved_0_15 - reserved */ #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_MASK) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_SHIFT (18U) /*! LPCG_GPIO0_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_MASK) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_SHIFT (19U) /*! gpio0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_SHIFT (20U) /*! LPCG_GPIO0_0_reserved_20_31 - reserved */ #define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPIO0_Register_Masks */ /* LSIO_LPCG_GPIO0 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPIO0 base address */ #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) /** Peripheral LSIO__LPCG_GPIO0 base pointer */ #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE) /** Array initializer of LSIO_LPCG_GPIO0 peripheral base addresses */ #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE } /** Array initializer of LSIO_LPCG_GPIO0 peripheral base pointers */ #define LSIO_LPCG_GPIO0_BASE_PTRS { LSIO__LPCG_GPIO0 } /*! * @} */ /* end of group LSIO_LPCG_GPIO0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO1_Peripheral_Access_Layer LSIO_LPCG_GPIO1 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPIO1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_GPIO1_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPIO1_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO1_Register_Masks LSIO_LPCG_GPIO1 Register Masks * @{ */ /*! @name LPCG_GPIO1_0 - na */ /*! @{ */ #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_MASK (0xFFFFU) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_SHIFT (0U) /*! LPCG_GPIO1_0_reserved_0_15 - reserved */ #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_MASK) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_SHIFT (18U) /*! LPCG_GPIO1_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_MASK) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_SHIFT (19U) /*! gpio1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_SHIFT (20U) /*! LPCG_GPIO1_0_reserved_20_31 - reserved */ #define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPIO1_Register_Masks */ /* LSIO_LPCG_GPIO1 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPIO1 base address */ #define LSIO__LPCG_GPIO1_BASE (0x5D490000u) /** Peripheral LSIO__LPCG_GPIO1 base pointer */ #define LSIO__LPCG_GPIO1 ((LSIO_LPCG_GPIO1_Type *)LSIO__LPCG_GPIO1_BASE) /** Array initializer of LSIO_LPCG_GPIO1 peripheral base addresses */ #define LSIO_LPCG_GPIO1_BASE_ADDRS { LSIO__LPCG_GPIO1_BASE } /** Array initializer of LSIO_LPCG_GPIO1 peripheral base pointers */ #define LSIO_LPCG_GPIO1_BASE_PTRS { LSIO__LPCG_GPIO1 } /*! * @} */ /* end of group LSIO_LPCG_GPIO1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO2_Peripheral_Access_Layer LSIO_LPCG_GPIO2 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPIO2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_GPIO2_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPIO2_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO2_Register_Masks LSIO_LPCG_GPIO2 Register Masks * @{ */ /*! @name LPCG_GPIO2_0 - na */ /*! @{ */ #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_MASK (0xFFFFU) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_SHIFT (0U) /*! LPCG_GPIO2_0_reserved_0_15 - reserved */ #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_MASK) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio2_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_SHIFT (18U) /*! LPCG_GPIO2_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_MASK) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_SHIFT (19U) /*! gpio2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_SHIFT (20U) /*! LPCG_GPIO2_0_reserved_20_31 - reserved */ #define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPIO2_Register_Masks */ /* LSIO_LPCG_GPIO2 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPIO2 base address */ #define LSIO__LPCG_GPIO2_BASE (0x5D4A0000u) /** Peripheral LSIO__LPCG_GPIO2 base pointer */ #define LSIO__LPCG_GPIO2 ((LSIO_LPCG_GPIO2_Type *)LSIO__LPCG_GPIO2_BASE) /** Array initializer of LSIO_LPCG_GPIO2 peripheral base addresses */ #define LSIO_LPCG_GPIO2_BASE_ADDRS { LSIO__LPCG_GPIO2_BASE } /** Array initializer of LSIO_LPCG_GPIO2 peripheral base pointers */ #define LSIO_LPCG_GPIO2_BASE_PTRS { LSIO__LPCG_GPIO2 } /*! * @} */ /* end of group LSIO_LPCG_GPIO2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO3_Peripheral_Access_Layer LSIO_LPCG_GPIO3 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPIO3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_GPIO3_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPIO3_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO3_Register_Masks LSIO_LPCG_GPIO3 Register Masks * @{ */ /*! @name LPCG_GPIO3_0 - na */ /*! @{ */ #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_MASK (0xFFFFU) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_SHIFT (0U) /*! LPCG_GPIO3_0_reserved_0_15 - reserved */ #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_MASK) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio3_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio3_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_SHIFT (18U) /*! LPCG_GPIO3_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_MASK) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_SHIFT (19U) /*! gpio3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_SHIFT (20U) /*! LPCG_GPIO3_0_reserved_20_31 - reserved */ #define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPIO3_Register_Masks */ /* LSIO_LPCG_GPIO3 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPIO3 base address */ #define LSIO__LPCG_GPIO3_BASE (0x5D4B0000u) /** Peripheral LSIO__LPCG_GPIO3 base pointer */ #define LSIO__LPCG_GPIO3 ((LSIO_LPCG_GPIO3_Type *)LSIO__LPCG_GPIO3_BASE) /** Array initializer of LSIO_LPCG_GPIO3 peripheral base addresses */ #define LSIO_LPCG_GPIO3_BASE_ADDRS { LSIO__LPCG_GPIO3_BASE } /** Array initializer of LSIO_LPCG_GPIO3 peripheral base pointers */ #define LSIO_LPCG_GPIO3_BASE_PTRS { LSIO__LPCG_GPIO3 } /*! * @} */ /* end of group LSIO_LPCG_GPIO3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO4_Peripheral_Access_Layer LSIO_LPCG_GPIO4 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPIO4 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_GPIO4_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPIO4_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO4_Register_Masks LSIO_LPCG_GPIO4 Register Masks * @{ */ /*! @name LPCG_GPIO4_0 - na */ /*! @{ */ #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_MASK (0xFFFFU) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_SHIFT (0U) /*! LPCG_GPIO4_0_reserved_0_15 - reserved */ #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_MASK) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio4_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio4_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_SHIFT (18U) /*! LPCG_GPIO4_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_MASK) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_SHIFT (19U) /*! gpio4_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_SHIFT (20U) /*! LPCG_GPIO4_0_reserved_20_31 - reserved */ #define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPIO4_Register_Masks */ /* LSIO_LPCG_GPIO4 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPIO4 base address */ #define LSIO__LPCG_GPIO4_BASE (0x5D4C0000u) /** Peripheral LSIO__LPCG_GPIO4 base pointer */ #define LSIO__LPCG_GPIO4 ((LSIO_LPCG_GPIO4_Type *)LSIO__LPCG_GPIO4_BASE) /** Array initializer of LSIO_LPCG_GPIO4 peripheral base addresses */ #define LSIO_LPCG_GPIO4_BASE_ADDRS { LSIO__LPCG_GPIO4_BASE } /** Array initializer of LSIO_LPCG_GPIO4 peripheral base pointers */ #define LSIO_LPCG_GPIO4_BASE_PTRS { LSIO__LPCG_GPIO4 } /*! * @} */ /* end of group LSIO_LPCG_GPIO4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO5_Peripheral_Access_Layer LSIO_LPCG_GPIO5 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPIO5 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_GPIO5_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPIO5_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO5_Register_Masks LSIO_LPCG_GPIO5 Register Masks * @{ */ /*! @name LPCG_GPIO5_0 - na */ /*! @{ */ #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_MASK (0xFFFFU) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_SHIFT (0U) /*! LPCG_GPIO5_0_reserved_0_15 - reserved */ #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_MASK) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio5_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio5_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_SHIFT (18U) /*! LPCG_GPIO5_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_MASK) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_SHIFT (19U) /*! gpio5_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_SHIFT (20U) /*! LPCG_GPIO5_0_reserved_20_31 - reserved */ #define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPIO5_Register_Masks */ /* LSIO_LPCG_GPIO5 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPIO5 base address */ #define LSIO__LPCG_GPIO5_BASE (0x5D4D0000u) /** Peripheral LSIO__LPCG_GPIO5 base pointer */ #define LSIO__LPCG_GPIO5 ((LSIO_LPCG_GPIO5_Type *)LSIO__LPCG_GPIO5_BASE) /** Array initializer of LSIO_LPCG_GPIO5 peripheral base addresses */ #define LSIO_LPCG_GPIO5_BASE_ADDRS { LSIO__LPCG_GPIO5_BASE } /** Array initializer of LSIO_LPCG_GPIO5 peripheral base pointers */ #define LSIO_LPCG_GPIO5_BASE_PTRS { LSIO__LPCG_GPIO5 } /*! * @} */ /* end of group LSIO_LPCG_GPIO5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO6 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO6_Peripheral_Access_Layer LSIO_LPCG_GPIO6 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPIO6 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_GPIO6_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPIO6_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO6 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO6_Register_Masks LSIO_LPCG_GPIO6 Register Masks * @{ */ /*! @name LPCG_GPIO6_0 - na */ /*! @{ */ #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_MASK (0xFFFFU) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_SHIFT (0U) /*! LPCG_GPIO6_0_reserved_0_15 - reserved */ #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_MASK) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio6_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio6_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_SHIFT (18U) /*! LPCG_GPIO6_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_MASK) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_SHIFT (19U) /*! gpio6_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_SHIFT (20U) /*! LPCG_GPIO6_0_reserved_20_31 - reserved */ #define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPIO6_Register_Masks */ /* LSIO_LPCG_GPIO6 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPIO6 base address */ #define LSIO__LPCG_GPIO6_BASE (0x5D4E0000u) /** Peripheral LSIO__LPCG_GPIO6 base pointer */ #define LSIO__LPCG_GPIO6 ((LSIO_LPCG_GPIO6_Type *)LSIO__LPCG_GPIO6_BASE) /** Array initializer of LSIO_LPCG_GPIO6 peripheral base addresses */ #define LSIO_LPCG_GPIO6_BASE_ADDRS { LSIO__LPCG_GPIO6_BASE } /** Array initializer of LSIO_LPCG_GPIO6 peripheral base pointers */ #define LSIO_LPCG_GPIO6_BASE_PTRS { LSIO__LPCG_GPIO6 } /*! * @} */ /* end of group LSIO_LPCG_GPIO6_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO7 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO7_Peripheral_Access_Layer LSIO_LPCG_GPIO7 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPIO7 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_GPIO7_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPIO7_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPIO7 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPIO7_Register_Masks LSIO_LPCG_GPIO7 Register Masks * @{ */ /*! @name LPCG_GPIO7_0 - na */ /*! @{ */ #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_MASK (0xFFFFU) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_SHIFT (0U) /*! LPCG_GPIO7_0_reserved_0_15 - reserved */ #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_MASK) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio7_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio7_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_SHIFT (18U) /*! LPCG_GPIO7_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_MASK) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_SHIFT (19U) /*! gpio7_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_SHIFT (20U) /*! LPCG_GPIO7_0_reserved_20_31 - reserved */ #define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPIO7_Register_Masks */ /* LSIO_LPCG_GPIO7 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPIO7 base address */ #define LSIO__LPCG_GPIO7_BASE (0x5D4F0000u) /** Peripheral LSIO__LPCG_GPIO7 base pointer */ #define LSIO__LPCG_GPIO7 ((LSIO_LPCG_GPIO7_Type *)LSIO__LPCG_GPIO7_BASE) /** Array initializer of LSIO_LPCG_GPIO7 peripheral base addresses */ #define LSIO_LPCG_GPIO7_BASE_ADDRS { LSIO__LPCG_GPIO7_BASE } /** Array initializer of LSIO_LPCG_GPIO7 peripheral base pointers */ #define LSIO_LPCG_GPIO7_BASE_PTRS { LSIO__LPCG_GPIO7 } /*! * @} */ /* end of group LSIO_LPCG_GPIO7_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPT0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPT0_Peripheral_Access_Layer LSIO_LPCG_GPT0 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPT0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_GPT0_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPT0_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPT0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPT0_Register_Masks LSIO_LPCG_GPT0 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_GPT0_0 - na */ /*! @{ */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_SHIFT (0U) /*! gpt0_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_SHIFT (1U) /*! gpt0_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_2_2 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_SHIFT (3U) /*! gpt0_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_4_4 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! gpt0_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_6_6 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_SHIFT (7U) /*! gpt0_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_8_8 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper0_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_10_10 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper0_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_12_15 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_SHIFT (19U) /*! gpt0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_20_20 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_gpt0_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_22_22 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_gpt0_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_gpt0_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_gpt0_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_26_26 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_gpt0_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_GPT0_0_reserved_28_31 - reserved */ #define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPT0_Register_Masks */ /* LSIO_LPCG_GPT0 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPT0 base address */ #define LSIO__LPCG_GPT0_BASE (0x5D540000u) /** Peripheral LSIO__LPCG_GPT0 base pointer */ #define LSIO__LPCG_GPT0 ((LSIO_LPCG_GPT0_Type *)LSIO__LPCG_GPT0_BASE) /** Array initializer of LSIO_LPCG_GPT0 peripheral base addresses */ #define LSIO_LPCG_GPT0_BASE_ADDRS { LSIO__LPCG_GPT0_BASE } /** Array initializer of LSIO_LPCG_GPT0 peripheral base pointers */ #define LSIO_LPCG_GPT0_BASE_PTRS { LSIO__LPCG_GPT0 } /*! * @} */ /* end of group LSIO_LPCG_GPT0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPT1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPT1_Peripheral_Access_Layer LSIO_LPCG_GPT1 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPT1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_GPT1_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPT1_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPT1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPT1_Register_Masks LSIO_LPCG_GPT1 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_GPT1_0 - na */ /*! @{ */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_SHIFT (0U) /*! gpt1_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_SHIFT (1U) /*! gpt1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_2_2 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_SHIFT (3U) /*! gpt1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_4_4 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! gpt1_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_6_6 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_SHIFT (7U) /*! gpt1_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_8_8 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper1_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_10_10 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper1_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_12_15 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_SHIFT (19U) /*! gpt1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_20_20 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_gpt1_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_22_22 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_gpt1_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_gpt1_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_gpt1_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_26_26 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_gpt1_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_GPT1_0_reserved_28_31 - reserved */ #define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPT1_Register_Masks */ /* LSIO_LPCG_GPT1 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPT1 base address */ #define LSIO__LPCG_GPT1_BASE (0x5D550000u) /** Peripheral LSIO__LPCG_GPT1 base pointer */ #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE) /** Array initializer of LSIO_LPCG_GPT1 peripheral base addresses */ #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE } /** Array initializer of LSIO_LPCG_GPT1 peripheral base pointers */ #define LSIO_LPCG_GPT1_BASE_PTRS { LSIO__LPCG_GPT1 } /*! * @} */ /* end of group LSIO_LPCG_GPT1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPT2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPT2_Peripheral_Access_Layer LSIO_LPCG_GPT2 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPT2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_GPT2_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPT2_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPT2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPT2_Register_Masks LSIO_LPCG_GPT2 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_GPT2_0 - na */ /*! @{ */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_SHIFT (0U) /*! gpt2_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_SHIFT (1U) /*! gpt2_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_2_2 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_SHIFT (3U) /*! gpt2_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_4_4 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! gpt2_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_6_6 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_SHIFT (7U) /*! gpt2_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_8_8 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper2_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_10_10 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper2_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_12_15 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt2_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_SHIFT (19U) /*! gpt2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_20_20 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_gpt2_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_22_22 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_gpt2_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_gpt2_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_gpt2_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_26_26 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_gpt2_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_GPT2_0_reserved_28_31 - reserved */ #define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPT2_Register_Masks */ /* LSIO_LPCG_GPT2 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPT2 base address */ #define LSIO__LPCG_GPT2_BASE (0x5D560000u) /** Peripheral LSIO__LPCG_GPT2 base pointer */ #define LSIO__LPCG_GPT2 ((LSIO_LPCG_GPT2_Type *)LSIO__LPCG_GPT2_BASE) /** Array initializer of LSIO_LPCG_GPT2 peripheral base addresses */ #define LSIO_LPCG_GPT2_BASE_ADDRS { LSIO__LPCG_GPT2_BASE } /** Array initializer of LSIO_LPCG_GPT2 peripheral base pointers */ #define LSIO_LPCG_GPT2_BASE_PTRS { LSIO__LPCG_GPT2 } /*! * @} */ /* end of group LSIO_LPCG_GPT2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPT3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPT3_Peripheral_Access_Layer LSIO_LPCG_GPT3 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPT3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_GPT3_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPT3_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPT3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPT3_Register_Masks LSIO_LPCG_GPT3 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_GPT3_0 - na */ /*! @{ */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_SHIFT (0U) /*! gpt3_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_SHIFT (1U) /*! gpt3_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_2_2 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_SHIFT (3U) /*! gpt3_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_4_4 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! gpt3_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_6_6 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_SHIFT (7U) /*! gpt3_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_8_8 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper3_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_10_10 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper3_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_12_15 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt3_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt3_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_SHIFT (19U) /*! gpt3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_20_20 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_gpt3_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_22_22 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_gpt3_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_gpt3_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_gpt3_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_26_26 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_gpt3_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_GPT3_0_reserved_28_31 - reserved */ #define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPT3_Register_Masks */ /* LSIO_LPCG_GPT3 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPT3 base address */ #define LSIO__LPCG_GPT3_BASE (0x5D570000u) /** Peripheral LSIO__LPCG_GPT3 base pointer */ #define LSIO__LPCG_GPT3 ((LSIO_LPCG_GPT3_Type *)LSIO__LPCG_GPT3_BASE) /** Array initializer of LSIO_LPCG_GPT3 peripheral base addresses */ #define LSIO_LPCG_GPT3_BASE_ADDRS { LSIO__LPCG_GPT3_BASE } /** Array initializer of LSIO_LPCG_GPT3 peripheral base pointers */ #define LSIO_LPCG_GPT3_BASE_PTRS { LSIO__LPCG_GPT3 } /*! * @} */ /* end of group LSIO_LPCG_GPT3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPT4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPT4_Peripheral_Access_Layer LSIO_LPCG_GPT4 Peripheral Access Layer * @{ */ /** LSIO_LPCG_GPT4 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_GPT4_0; /**< na, offset: 0x0 */ } LSIO_LPCG_GPT4_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_GPT4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_GPT4_Register_Masks LSIO_LPCG_GPT4 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_GPT4_0 - na */ /*! @{ */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_SHIFT (0U) /*! gpt4_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_SHIFT (1U) /*! gpt4_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_2_2 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_SHIFT (3U) /*! gpt4_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_4_4 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! gpt4_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_6_6 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_SHIFT (7U) /*! gpt4_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_8_8 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper4_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_10_10 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper4_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_12_15 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_SHIFT (16U) /*! gpt4_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_SHIFT (17U) /*! gpt4_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_18_18 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_SHIFT (19U) /*! gpt4_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_20_20 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_gpt4_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_22_22 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_gpt4_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_gpt4_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_gpt4_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_26_26 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_gpt4_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_GPT4_0_reserved_28_31 - reserved */ #define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_GPT4_Register_Masks */ /* LSIO_LPCG_GPT4 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_GPT4 base address */ #define LSIO__LPCG_GPT4_BASE (0x5D580000u) /** Peripheral LSIO__LPCG_GPT4 base pointer */ #define LSIO__LPCG_GPT4 ((LSIO_LPCG_GPT4_Type *)LSIO__LPCG_GPT4_BASE) /** Array initializer of LSIO_LPCG_GPT4 peripheral base addresses */ #define LSIO_LPCG_GPT4_BASE_ADDRS { LSIO__LPCG_GPT4_BASE } /** Array initializer of LSIO_LPCG_GPT4 peripheral base pointers */ #define LSIO_LPCG_GPT4_BASE_PTRS { LSIO__LPCG_GPT4 } /*! * @} */ /* end of group LSIO_LPCG_GPT4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_KPP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_KPP_Peripheral_Access_Layer LSIO_LPCG_KPP Peripheral Access Layer * @{ */ /** LSIO_LPCG_KPP - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_KPP_0; /**< na, offset: 0x0 */ } LSIO_LPCG_KPP_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_KPP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_KPP_Register_Masks LSIO_LPCG_KPP Register Masks * @{ */ /*! @name LPCG_KPP_0 - na */ /*! @{ */ #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_SHIFT (0U) /*! LPCG_KPP_0_reserved_0_0 - reserved */ #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_MASK) #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_MASK (0x2U) #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_SHIFT (1U) /*! ccm_ckil_sync_wrapper13_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_MASK) #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_SHIFT (2U) /*! LPCG_KPP_0_reserved_2_2 - reserved */ #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_MASK) #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_MASK (0x8U) #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_SHIFT (3U) /*! ccm_ckil_sync_wrapper13_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_MASK) #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_SHIFT (4U) /*! LPCG_KPP_0_reserved_4_15 - reserved */ #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_MASK) #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_SHIFT (16U) /*! kpp_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_SHIFT (17U) /*! kpp_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_SHIFT (18U) /*! LPCG_KPP_0_reserved_18_18 - reserved */ #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_MASK) #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_SHIFT (19U) /*! kpp_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_SHIFT (20U) /*! LPCG_KPP_0_reserved_20_31 - reserved */ #define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_KPP_Register_Masks */ /* LSIO_LPCG_KPP - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_KPP base address */ #define LSIO__LPCG_KPP_BASE (0x5D5A0000u) /** Peripheral LSIO__LPCG_KPP base pointer */ #define LSIO__LPCG_KPP ((LSIO_LPCG_KPP_Type *)LSIO__LPCG_KPP_BASE) /** Array initializer of LSIO_LPCG_KPP peripheral base addresses */ #define LSIO_LPCG_KPP_BASE_ADDRS { LSIO__LPCG_KPP_BASE } /** Array initializer of LSIO_LPCG_KPP peripheral base pointers */ #define LSIO_LPCG_KPP_BASE_PTRS { LSIO__LPCG_KPP } /*! * @} */ /* end of group LSIO_LPCG_KPP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU10_DSP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU10_DSP_Peripheral_Access_Layer LSIO_LPCG_MU10_DSP Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU10_DSP - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU10_DSP_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU10_DSP_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU10_DSP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU10_DSP_Register_Masks LSIO_LPCG_MU10_DSP Register Masks * @{ */ /*! @name LPCG_MU10_DSP_0 - na */ /*! @{ */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU10_DSP_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_MASK) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_MASK (0x2U) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_SHIFT (1U) /*! mu10_ipg_clk_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_MASK) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU10_DSP_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_MASK) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_MASK (0x8U) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_SHIFT (3U) /*! mu10_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_MASK) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU10_DSP_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_MASK) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_SHIFT (16U) /*! mu10_ipg_clk_s_dsp_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_MASK) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_SHIFT (17U) /*! mu10_ipg_clk_s_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_MASK) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU10_DSP_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_MASK) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_MASK (0x80000U) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_SHIFT (19U) /*! mu10_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_MASK) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU10_DSP_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU10_DSP_Register_Masks */ /* LSIO_LPCG_MU10_DSP - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU10_DSP base address */ #define LSIO__LPCG_MU10_DSP_BASE (0x5D6E0000u) /** Peripheral LSIO__LPCG_MU10_DSP base pointer */ #define LSIO__LPCG_MU10_DSP ((LSIO_LPCG_MU10_DSP_Type *)LSIO__LPCG_MU10_DSP_BASE) /** Array initializer of LSIO_LPCG_MU10_DSP peripheral base addresses */ #define LSIO_LPCG_MU10_DSP_BASE_ADDRS { LSIO__LPCG_MU10_DSP_BASE } /** Array initializer of LSIO_LPCG_MU10_DSP peripheral base pointers */ #define LSIO_LPCG_MU10_DSP_BASE_PTRS { LSIO__LPCG_MU10_DSP } /*! * @} */ /* end of group LSIO_LPCG_MU10_DSP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU10_MCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU10_MCU_Peripheral_Access_Layer LSIO_LPCG_MU10_MCU Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU10_MCU - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU10_MCU_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU10_MCU_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU10_MCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU10_MCU_Register_Masks LSIO_LPCG_MU10_MCU Register Masks * @{ */ /*! @name LPCG_MU10_MCU_0 - na */ /*! @{ */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU10_MCU_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_MASK) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_MASK (0x2U) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_SHIFT (1U) /*! mu10_ipg_clk_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_MASK) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU10_MCU_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_MASK) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_MASK (0x8U) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_SHIFT (3U) /*! mu10_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_MASK) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU10_MCU_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_MASK) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_SHIFT (16U) /*! mu10_ipg_clk_s_mcu_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_MASK) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_SHIFT (17U) /*! mu10_ipg_clk_s_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_MASK) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU10_MCU_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_MASK) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_MASK (0x80000U) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_SHIFT (19U) /*! mu10_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_MASK) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU10_MCU_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU10_MCU_Register_Masks */ /* LSIO_LPCG_MU10_MCU - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU10_MCU base address */ #define LSIO__LPCG_MU10_MCU_BASE (0x5D650000u) /** Peripheral LSIO__LPCG_MU10_MCU base pointer */ #define LSIO__LPCG_MU10_MCU ((LSIO_LPCG_MU10_MCU_Type *)LSIO__LPCG_MU10_MCU_BASE) /** Array initializer of LSIO_LPCG_MU10_MCU peripheral base addresses */ #define LSIO_LPCG_MU10_MCU_BASE_ADDRS { LSIO__LPCG_MU10_MCU_BASE } /** Array initializer of LSIO_LPCG_MU10_MCU peripheral base pointers */ #define LSIO_LPCG_MU10_MCU_BASE_PTRS { LSIO__LPCG_MU10_MCU } /*! * @} */ /* end of group LSIO_LPCG_MU10_MCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU11_DSP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU11_DSP_Peripheral_Access_Layer LSIO_LPCG_MU11_DSP Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU11_DSP - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU11_DSP_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU11_DSP_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU11_DSP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU11_DSP_Register_Masks LSIO_LPCG_MU11_DSP Register Masks * @{ */ /*! @name LPCG_MU11_DSP_0 - na */ /*! @{ */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU11_DSP_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_MASK) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_MASK (0x2U) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_SHIFT (1U) /*! mu11_ipg_clk_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_MASK) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU11_DSP_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_MASK) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_MASK (0x8U) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_SHIFT (3U) /*! mu11_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_MASK) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU11_DSP_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_MASK) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_SHIFT (16U) /*! mu11_ipg_clk_s_dsp_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_MASK) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_SHIFT (17U) /*! mu11_ipg_clk_s_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_MASK) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU11_DSP_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_MASK) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_MASK (0x80000U) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_SHIFT (19U) /*! mu11_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_MASK) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU11_DSP_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU11_DSP_Register_Masks */ /* LSIO_LPCG_MU11_DSP - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU11_DSP base address */ #define LSIO__LPCG_MU11_DSP_BASE (0x5D6F0000u) /** Peripheral LSIO__LPCG_MU11_DSP base pointer */ #define LSIO__LPCG_MU11_DSP ((LSIO_LPCG_MU11_DSP_Type *)LSIO__LPCG_MU11_DSP_BASE) /** Array initializer of LSIO_LPCG_MU11_DSP peripheral base addresses */ #define LSIO_LPCG_MU11_DSP_BASE_ADDRS { LSIO__LPCG_MU11_DSP_BASE } /** Array initializer of LSIO_LPCG_MU11_DSP peripheral base pointers */ #define LSIO_LPCG_MU11_DSP_BASE_PTRS { LSIO__LPCG_MU11_DSP } /*! * @} */ /* end of group LSIO_LPCG_MU11_DSP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU11_MCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU11_MCU_Peripheral_Access_Layer LSIO_LPCG_MU11_MCU Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU11_MCU - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU11_MCU_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU11_MCU_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU11_MCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU11_MCU_Register_Masks LSIO_LPCG_MU11_MCU Register Masks * @{ */ /*! @name LPCG_MU11_MCU_0 - na */ /*! @{ */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU11_MCU_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_MASK) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_MASK (0x2U) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_SHIFT (1U) /*! mu11_ipg_clk_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_MASK) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU11_MCU_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_MASK) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_MASK (0x8U) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_SHIFT (3U) /*! mu11_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_MASK) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU11_MCU_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_MASK) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_SHIFT (16U) /*! mu11_ipg_clk_s_mcu_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_MASK) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_SHIFT (17U) /*! mu11_ipg_clk_s_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_MASK) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU11_MCU_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_MASK) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_MASK (0x80000U) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_SHIFT (19U) /*! mu11_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_MASK) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU11_MCU_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU11_MCU_Register_Masks */ /* LSIO_LPCG_MU11_MCU - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU11_MCU base address */ #define LSIO__LPCG_MU11_MCU_BASE (0x5D660000u) /** Peripheral LSIO__LPCG_MU11_MCU base pointer */ #define LSIO__LPCG_MU11_MCU ((LSIO_LPCG_MU11_MCU_Type *)LSIO__LPCG_MU11_MCU_BASE) /** Array initializer of LSIO_LPCG_MU11_MCU peripheral base addresses */ #define LSIO_LPCG_MU11_MCU_BASE_ADDRS { LSIO__LPCG_MU11_MCU_BASE } /** Array initializer of LSIO_LPCG_MU11_MCU peripheral base pointers */ #define LSIO_LPCG_MU11_MCU_BASE_PTRS { LSIO__LPCG_MU11_MCU } /*! * @} */ /* end of group LSIO_LPCG_MU11_MCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU12_DSP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU12_DSP_Peripheral_Access_Layer LSIO_LPCG_MU12_DSP Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU12_DSP - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU12_DSP_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU12_DSP_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU12_DSP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU12_DSP_Register_Masks LSIO_LPCG_MU12_DSP Register Masks * @{ */ /*! @name LPCG_MU12_DSP_0 - na */ /*! @{ */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU12_DSP_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_MASK) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_MASK (0x2U) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_SHIFT (1U) /*! mu12_ipg_clk_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_MASK) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU12_DSP_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_MASK) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_MASK (0x8U) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_SHIFT (3U) /*! mu12_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_MASK) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU12_DSP_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_MASK) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_SHIFT (16U) /*! mu12_ipg_clk_s_dsp_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_MASK) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_SHIFT (17U) /*! mu12_ipg_clk_s_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_MASK) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU12_DSP_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_MASK) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_MASK (0x80000U) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_SHIFT (19U) /*! mu12_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_MASK) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU12_DSP_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU12_DSP_Register_Masks */ /* LSIO_LPCG_MU12_DSP - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU12_DSP base address */ #define LSIO__LPCG_MU12_DSP_BASE (0x5D700000u) /** Peripheral LSIO__LPCG_MU12_DSP base pointer */ #define LSIO__LPCG_MU12_DSP ((LSIO_LPCG_MU12_DSP_Type *)LSIO__LPCG_MU12_DSP_BASE) /** Array initializer of LSIO_LPCG_MU12_DSP peripheral base addresses */ #define LSIO_LPCG_MU12_DSP_BASE_ADDRS { LSIO__LPCG_MU12_DSP_BASE } /** Array initializer of LSIO_LPCG_MU12_DSP peripheral base pointers */ #define LSIO_LPCG_MU12_DSP_BASE_PTRS { LSIO__LPCG_MU12_DSP } /*! * @} */ /* end of group LSIO_LPCG_MU12_DSP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU12_MCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU12_MCU_Peripheral_Access_Layer LSIO_LPCG_MU12_MCU Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU12_MCU - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU12_MCU_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU12_MCU_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU12_MCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU12_MCU_Register_Masks LSIO_LPCG_MU12_MCU Register Masks * @{ */ /*! @name LPCG_MU12_MCU_0 - na */ /*! @{ */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU12_MCU_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_MASK) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_MASK (0x2U) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_SHIFT (1U) /*! mu12_ipg_clk_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_MASK) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU12_MCU_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_MASK) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_MASK (0x8U) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_SHIFT (3U) /*! mu12_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_MASK) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU12_MCU_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_MASK) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_SHIFT (16U) /*! mu12_ipg_clk_s_mcu_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_MASK) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_SHIFT (17U) /*! mu12_ipg_clk_s_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_MASK) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU12_MCU_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_MASK) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_MASK (0x80000U) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_SHIFT (19U) /*! mu12_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_MASK) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU12_MCU_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU12_MCU_Register_Masks */ /* LSIO_LPCG_MU12_MCU - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU12_MCU base address */ #define LSIO__LPCG_MU12_MCU_BASE (0x5D670000u) /** Peripheral LSIO__LPCG_MU12_MCU base pointer */ #define LSIO__LPCG_MU12_MCU ((LSIO_LPCG_MU12_MCU_Type *)LSIO__LPCG_MU12_MCU_BASE) /** Array initializer of LSIO_LPCG_MU12_MCU peripheral base addresses */ #define LSIO_LPCG_MU12_MCU_BASE_ADDRS { LSIO__LPCG_MU12_MCU_BASE } /** Array initializer of LSIO_LPCG_MU12_MCU peripheral base pointers */ #define LSIO_LPCG_MU12_MCU_BASE_PTRS { LSIO__LPCG_MU12_MCU } /*! * @} */ /* end of group LSIO_LPCG_MU12_MCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU13_DSP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU13_DSP_Peripheral_Access_Layer LSIO_LPCG_MU13_DSP Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU13_DSP - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU13_DSP_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU13_DSP_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU13_DSP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU13_DSP_Register_Masks LSIO_LPCG_MU13_DSP Register Masks * @{ */ /*! @name LPCG_MU13_DSP_0 - na */ /*! @{ */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU13_DSP_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_MASK) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_MASK (0x2U) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_SHIFT (1U) /*! mu13_ipg_clk_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_MASK) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU13_DSP_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_MASK) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_MASK (0x8U) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_SHIFT (3U) /*! mu13_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_MASK) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU13_DSP_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_MASK) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_SHIFT (16U) /*! mu13_ipg_clk_s_dsp_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_MASK) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_SHIFT (17U) /*! mu13_ipg_clk_s_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_MASK) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU13_DSP_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_MASK) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_MASK (0x80000U) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_SHIFT (19U) /*! mu13_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_MASK) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU13_DSP_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU13_DSP_Register_Masks */ /* LSIO_LPCG_MU13_DSP - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU13_DSP base address */ #define LSIO__LPCG_MU13_DSP_BASE (0x5D710000u) /** Peripheral LSIO__LPCG_MU13_DSP base pointer */ #define LSIO__LPCG_MU13_DSP ((LSIO_LPCG_MU13_DSP_Type *)LSIO__LPCG_MU13_DSP_BASE) /** Array initializer of LSIO_LPCG_MU13_DSP peripheral base addresses */ #define LSIO_LPCG_MU13_DSP_BASE_ADDRS { LSIO__LPCG_MU13_DSP_BASE } /** Array initializer of LSIO_LPCG_MU13_DSP peripheral base pointers */ #define LSIO_LPCG_MU13_DSP_BASE_PTRS { LSIO__LPCG_MU13_DSP } /*! * @} */ /* end of group LSIO_LPCG_MU13_DSP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU13_MCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU13_MCU_Peripheral_Access_Layer LSIO_LPCG_MU13_MCU Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU13_MCU - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU13_MCU_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU13_MCU_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU13_MCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU13_MCU_Register_Masks LSIO_LPCG_MU13_MCU Register Masks * @{ */ /*! @name LPCG_MU13_MCU_0 - na */ /*! @{ */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU13_MCU_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_MASK) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_MASK (0x2U) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_SHIFT (1U) /*! mu13_ipg_clk_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_MASK) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU13_MCU_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_MASK) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_MASK (0x8U) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_SHIFT (3U) /*! mu13_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_MASK) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU13_MCU_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_MASK) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_SHIFT (16U) /*! mu13_ipg_clk_s_mcu_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_MASK) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_SHIFT (17U) /*! mu13_ipg_clk_s_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_MASK) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU13_MCU_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_MASK) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_MASK (0x80000U) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_SHIFT (19U) /*! mu13_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_MASK) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU13_MCU_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU13_MCU_Register_Masks */ /* LSIO_LPCG_MU13_MCU - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU13_MCU base address */ #define LSIO__LPCG_MU13_MCU_BASE (0x5D680000u) /** Peripheral LSIO__LPCG_MU13_MCU base pointer */ #define LSIO__LPCG_MU13_MCU ((LSIO_LPCG_MU13_MCU_Type *)LSIO__LPCG_MU13_MCU_BASE) /** Array initializer of LSIO_LPCG_MU13_MCU peripheral base addresses */ #define LSIO_LPCG_MU13_MCU_BASE_ADDRS { LSIO__LPCG_MU13_MCU_BASE } /** Array initializer of LSIO_LPCG_MU13_MCU peripheral base pointers */ #define LSIO_LPCG_MU13_MCU_BASE_PTRS { LSIO__LPCG_MU13_MCU } /*! * @} */ /* end of group LSIO_LPCG_MU13_MCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU5_DSP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU5_DSP_Peripheral_Access_Layer LSIO_LPCG_MU5_DSP Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU5_DSP - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU5_DSP_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU5_DSP_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU5_DSP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU5_DSP_Register_Masks LSIO_LPCG_MU5_DSP Register Masks * @{ */ /*! @name LPCG_MU5_DSP_0 - na */ /*! @{ */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU5_DSP_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_MASK) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_MASK (0x2U) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_SHIFT (1U) /*! mu5_ipg_clk_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_MASK) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU5_DSP_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_MASK) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_MASK (0x8U) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_SHIFT (3U) /*! mu5_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_MASK) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU5_DSP_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_MASK) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_SHIFT (16U) /*! mu5_ipg_clk_s_dsp_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_MASK) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_SHIFT (17U) /*! mu5_ipg_clk_s_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_MASK) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU5_DSP_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_MASK) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_MASK (0x80000U) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_SHIFT (19U) /*! mu5_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_MASK) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU5_DSP_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU5_DSP_Register_Masks */ /* LSIO_LPCG_MU5_DSP - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU5_DSP base address */ #define LSIO__LPCG_MU5_DSP_BASE (0x5D690000u) /** Peripheral LSIO__LPCG_MU5_DSP base pointer */ #define LSIO__LPCG_MU5_DSP ((LSIO_LPCG_MU5_DSP_Type *)LSIO__LPCG_MU5_DSP_BASE) /** Array initializer of LSIO_LPCG_MU5_DSP peripheral base addresses */ #define LSIO_LPCG_MU5_DSP_BASE_ADDRS { LSIO__LPCG_MU5_DSP_BASE } /** Array initializer of LSIO_LPCG_MU5_DSP peripheral base pointers */ #define LSIO_LPCG_MU5_DSP_BASE_PTRS { LSIO__LPCG_MU5_DSP } /*! * @} */ /* end of group LSIO_LPCG_MU5_DSP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU5_MCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU5_MCU_Peripheral_Access_Layer LSIO_LPCG_MU5_MCU Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU5_MCU - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU5_MCU_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU5_MCU_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU5_MCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU5_MCU_Register_Masks LSIO_LPCG_MU5_MCU Register Masks * @{ */ /*! @name LPCG_MU5_MCU_0 - na */ /*! @{ */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU5_MCU_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_MASK) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_MASK (0x2U) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_SHIFT (1U) /*! mu5_ipg_clk_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_MASK) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU5_MCU_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_MASK) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_MASK (0x8U) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_SHIFT (3U) /*! mu5_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_MASK) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU5_MCU_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_MASK) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_SHIFT (16U) /*! mu5_ipg_clk_s_mcu_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_MASK) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_SHIFT (17U) /*! mu5_ipg_clk_s_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_MASK) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU5_MCU_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_MASK) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_MASK (0x80000U) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_SHIFT (19U) /*! mu5_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_MASK) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU5_MCU_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU5_MCU_Register_Masks */ /* LSIO_LPCG_MU5_MCU - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU5_MCU base address */ #define LSIO__LPCG_MU5_MCU_BASE (0x5D600000u) /** Peripheral LSIO__LPCG_MU5_MCU base pointer */ #define LSIO__LPCG_MU5_MCU ((LSIO_LPCG_MU5_MCU_Type *)LSIO__LPCG_MU5_MCU_BASE) /** Array initializer of LSIO_LPCG_MU5_MCU peripheral base addresses */ #define LSIO_LPCG_MU5_MCU_BASE_ADDRS { LSIO__LPCG_MU5_MCU_BASE } /** Array initializer of LSIO_LPCG_MU5_MCU peripheral base pointers */ #define LSIO_LPCG_MU5_MCU_BASE_PTRS { LSIO__LPCG_MU5_MCU } /*! * @} */ /* end of group LSIO_LPCG_MU5_MCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU6_DSP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU6_DSP_Peripheral_Access_Layer LSIO_LPCG_MU6_DSP Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU6_DSP - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU6_DSP_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU6_DSP_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU6_DSP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU6_DSP_Register_Masks LSIO_LPCG_MU6_DSP Register Masks * @{ */ /*! @name LPCG_MU6_DSP_0 - na */ /*! @{ */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU6_DSP_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_MASK) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_MASK (0x2U) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_SHIFT (1U) /*! mu6_ipg_clk_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_MASK) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU6_DSP_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_MASK) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_MASK (0x8U) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_SHIFT (3U) /*! mu6_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_MASK) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU6_DSP_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_MASK) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_SHIFT (16U) /*! mu6_ipg_clk_s_dsp_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_MASK) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_SHIFT (17U) /*! mu6_ipg_clk_s_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_MASK) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU6_DSP_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_MASK) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_MASK (0x80000U) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_SHIFT (19U) /*! mu6_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_MASK) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU6_DSP_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU6_DSP_Register_Masks */ /* LSIO_LPCG_MU6_DSP - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU6_DSP base address */ #define LSIO__LPCG_MU6_DSP_BASE (0x5D6A0000u) /** Peripheral LSIO__LPCG_MU6_DSP base pointer */ #define LSIO__LPCG_MU6_DSP ((LSIO_LPCG_MU6_DSP_Type *)LSIO__LPCG_MU6_DSP_BASE) /** Array initializer of LSIO_LPCG_MU6_DSP peripheral base addresses */ #define LSIO_LPCG_MU6_DSP_BASE_ADDRS { LSIO__LPCG_MU6_DSP_BASE } /** Array initializer of LSIO_LPCG_MU6_DSP peripheral base pointers */ #define LSIO_LPCG_MU6_DSP_BASE_PTRS { LSIO__LPCG_MU6_DSP } /*! * @} */ /* end of group LSIO_LPCG_MU6_DSP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU6_MCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU6_MCU_Peripheral_Access_Layer LSIO_LPCG_MU6_MCU Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU6_MCU - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU6_MCU_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU6_MCU_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU6_MCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU6_MCU_Register_Masks LSIO_LPCG_MU6_MCU Register Masks * @{ */ /*! @name LPCG_MU6_MCU_0 - na */ /*! @{ */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU6_MCU_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_MASK) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_MASK (0x2U) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_SHIFT (1U) /*! mu6_ipg_clk_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_MASK) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU6_MCU_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_MASK) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_MASK (0x8U) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_SHIFT (3U) /*! mu6_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_MASK) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU6_MCU_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_MASK) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_SHIFT (16U) /*! mu6_ipg_clk_s_mcu_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_MASK) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_SHIFT (17U) /*! mu6_ipg_clk_s_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_MASK) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU6_MCU_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_MASK) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_MASK (0x80000U) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_SHIFT (19U) /*! mu6_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_MASK) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU6_MCU_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU6_MCU_Register_Masks */ /* LSIO_LPCG_MU6_MCU - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU6_MCU base address */ #define LSIO__LPCG_MU6_MCU_BASE (0x5D610000u) /** Peripheral LSIO__LPCG_MU6_MCU base pointer */ #define LSIO__LPCG_MU6_MCU ((LSIO_LPCG_MU6_MCU_Type *)LSIO__LPCG_MU6_MCU_BASE) /** Array initializer of LSIO_LPCG_MU6_MCU peripheral base addresses */ #define LSIO_LPCG_MU6_MCU_BASE_ADDRS { LSIO__LPCG_MU6_MCU_BASE } /** Array initializer of LSIO_LPCG_MU6_MCU peripheral base pointers */ #define LSIO_LPCG_MU6_MCU_BASE_PTRS { LSIO__LPCG_MU6_MCU } /*! * @} */ /* end of group LSIO_LPCG_MU6_MCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU7_DSP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU7_DSP_Peripheral_Access_Layer LSIO_LPCG_MU7_DSP Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU7_DSP - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU7_DSP_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU7_DSP_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU7_DSP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU7_DSP_Register_Masks LSIO_LPCG_MU7_DSP Register Masks * @{ */ /*! @name LPCG_MU7_DSP_0 - na */ /*! @{ */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU7_DSP_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_MASK) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_MASK (0x2U) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_SHIFT (1U) /*! mu7_ipg_clk_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_MASK) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU7_DSP_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_MASK) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_MASK (0x8U) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_SHIFT (3U) /*! mu7_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_MASK) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU7_DSP_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_MASK) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_SHIFT (16U) /*! mu7_ipg_clk_s_dsp_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_MASK) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_SHIFT (17U) /*! mu7_ipg_clk_s_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_MASK) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU7_DSP_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_MASK) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_MASK (0x80000U) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_SHIFT (19U) /*! mu7_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_MASK) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU7_DSP_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU7_DSP_Register_Masks */ /* LSIO_LPCG_MU7_DSP - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU7_DSP base address */ #define LSIO__LPCG_MU7_DSP_BASE (0x5D6B0000u) /** Peripheral LSIO__LPCG_MU7_DSP base pointer */ #define LSIO__LPCG_MU7_DSP ((LSIO_LPCG_MU7_DSP_Type *)LSIO__LPCG_MU7_DSP_BASE) /** Array initializer of LSIO_LPCG_MU7_DSP peripheral base addresses */ #define LSIO_LPCG_MU7_DSP_BASE_ADDRS { LSIO__LPCG_MU7_DSP_BASE } /** Array initializer of LSIO_LPCG_MU7_DSP peripheral base pointers */ #define LSIO_LPCG_MU7_DSP_BASE_PTRS { LSIO__LPCG_MU7_DSP } /*! * @} */ /* end of group LSIO_LPCG_MU7_DSP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU7_MCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU7_MCU_Peripheral_Access_Layer LSIO_LPCG_MU7_MCU Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU7_MCU - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU7_MCU_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU7_MCU_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU7_MCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU7_MCU_Register_Masks LSIO_LPCG_MU7_MCU Register Masks * @{ */ /*! @name LPCG_MU7_MCU_0 - na */ /*! @{ */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU7_MCU_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_MASK) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_MASK (0x2U) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_SHIFT (1U) /*! mu7_ipg_clk_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_MASK) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU7_MCU_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_MASK) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_MASK (0x8U) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_SHIFT (3U) /*! mu7_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_MASK) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU7_MCU_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_MASK) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_SHIFT (16U) /*! mu7_ipg_clk_s_mcu_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_MASK) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_SHIFT (17U) /*! mu7_ipg_clk_s_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_MASK) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU7_MCU_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_MASK) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_MASK (0x80000U) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_SHIFT (19U) /*! mu7_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_MASK) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU7_MCU_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU7_MCU_Register_Masks */ /* LSIO_LPCG_MU7_MCU - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU7_MCU base address */ #define LSIO__LPCG_MU7_MCU_BASE (0x5D620000u) /** Peripheral LSIO__LPCG_MU7_MCU base pointer */ #define LSIO__LPCG_MU7_MCU ((LSIO_LPCG_MU7_MCU_Type *)LSIO__LPCG_MU7_MCU_BASE) /** Array initializer of LSIO_LPCG_MU7_MCU peripheral base addresses */ #define LSIO_LPCG_MU7_MCU_BASE_ADDRS { LSIO__LPCG_MU7_MCU_BASE } /** Array initializer of LSIO_LPCG_MU7_MCU peripheral base pointers */ #define LSIO_LPCG_MU7_MCU_BASE_PTRS { LSIO__LPCG_MU7_MCU } /*! * @} */ /* end of group LSIO_LPCG_MU7_MCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU8_DSP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU8_DSP_Peripheral_Access_Layer LSIO_LPCG_MU8_DSP Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU8_DSP - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU8_DSP_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU8_DSP_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU8_DSP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU8_DSP_Register_Masks LSIO_LPCG_MU8_DSP Register Masks * @{ */ /*! @name LPCG_MU8_DSP_0 - na */ /*! @{ */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU8_DSP_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_MASK) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_MASK (0x2U) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_SHIFT (1U) /*! mu8_ipg_clk_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_MASK) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU8_DSP_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_MASK) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_MASK (0x8U) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_SHIFT (3U) /*! mu8_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_MASK) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU8_DSP_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_MASK) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_SHIFT (16U) /*! mu8_ipg_clk_s_dsp_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_MASK) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_SHIFT (17U) /*! mu8_ipg_clk_s_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_MASK) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU8_DSP_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_MASK) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_MASK (0x80000U) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_SHIFT (19U) /*! mu8_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_MASK) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU8_DSP_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU8_DSP_Register_Masks */ /* LSIO_LPCG_MU8_DSP - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU8_DSP base address */ #define LSIO__LPCG_MU8_DSP_BASE (0x5D6C0000u) /** Peripheral LSIO__LPCG_MU8_DSP base pointer */ #define LSIO__LPCG_MU8_DSP ((LSIO_LPCG_MU8_DSP_Type *)LSIO__LPCG_MU8_DSP_BASE) /** Array initializer of LSIO_LPCG_MU8_DSP peripheral base addresses */ #define LSIO_LPCG_MU8_DSP_BASE_ADDRS { LSIO__LPCG_MU8_DSP_BASE } /** Array initializer of LSIO_LPCG_MU8_DSP peripheral base pointers */ #define LSIO_LPCG_MU8_DSP_BASE_PTRS { LSIO__LPCG_MU8_DSP } /*! * @} */ /* end of group LSIO_LPCG_MU8_DSP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU8_MCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU8_MCU_Peripheral_Access_Layer LSIO_LPCG_MU8_MCU Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU8_MCU - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU8_MCU_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU8_MCU_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU8_MCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU8_MCU_Register_Masks LSIO_LPCG_MU8_MCU Register Masks * @{ */ /*! @name LPCG_MU8_MCU_0 - na */ /*! @{ */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU8_MCU_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_MASK) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_MASK (0x2U) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_SHIFT (1U) /*! mu8_ipg_clk_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_MASK) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU8_MCU_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_MASK) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_MASK (0x8U) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_SHIFT (3U) /*! mu8_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_MASK) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU8_MCU_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_MASK) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_SHIFT (16U) /*! mu8_ipg_clk_s_mcu_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_MASK) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_SHIFT (17U) /*! mu8_ipg_clk_s_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_MASK) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU8_MCU_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_MASK) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_MASK (0x80000U) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_SHIFT (19U) /*! mu8_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_MASK) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU8_MCU_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU8_MCU_Register_Masks */ /* LSIO_LPCG_MU8_MCU - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU8_MCU base address */ #define LSIO__LPCG_MU8_MCU_BASE (0x5D630000u) /** Peripheral LSIO__LPCG_MU8_MCU base pointer */ #define LSIO__LPCG_MU8_MCU ((LSIO_LPCG_MU8_MCU_Type *)LSIO__LPCG_MU8_MCU_BASE) /** Array initializer of LSIO_LPCG_MU8_MCU peripheral base addresses */ #define LSIO_LPCG_MU8_MCU_BASE_ADDRS { LSIO__LPCG_MU8_MCU_BASE } /** Array initializer of LSIO_LPCG_MU8_MCU peripheral base pointers */ #define LSIO_LPCG_MU8_MCU_BASE_PTRS { LSIO__LPCG_MU8_MCU } /*! * @} */ /* end of group LSIO_LPCG_MU8_MCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU9_DSP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU9_DSP_Peripheral_Access_Layer LSIO_LPCG_MU9_DSP Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU9_DSP - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU9_DSP_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU9_DSP_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU9_DSP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU9_DSP_Register_Masks LSIO_LPCG_MU9_DSP Register Masks * @{ */ /*! @name LPCG_MU9_DSP_0 - na */ /*! @{ */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU9_DSP_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_MASK) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_MASK (0x2U) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_SHIFT (1U) /*! mu9_ipg_clk_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_MASK) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU9_DSP_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_MASK) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_MASK (0x8U) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_SHIFT (3U) /*! mu9_ipg_clk_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_MASK) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU9_DSP_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_MASK) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_SHIFT (16U) /*! mu9_ipg_clk_s_dsp_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_MASK) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_SHIFT (17U) /*! mu9_ipg_clk_s_dsp_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_MASK) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU9_DSP_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_MASK) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_MASK (0x80000U) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_SHIFT (19U) /*! mu9_ipg_clk_s_dsp_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_MASK) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU9_DSP_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU9_DSP_Register_Masks */ /* LSIO_LPCG_MU9_DSP - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU9_DSP base address */ #define LSIO__LPCG_MU9_DSP_BASE (0x5D6D0000u) /** Peripheral LSIO__LPCG_MU9_DSP base pointer */ #define LSIO__LPCG_MU9_DSP ((LSIO_LPCG_MU9_DSP_Type *)LSIO__LPCG_MU9_DSP_BASE) /** Array initializer of LSIO_LPCG_MU9_DSP peripheral base addresses */ #define LSIO_LPCG_MU9_DSP_BASE_ADDRS { LSIO__LPCG_MU9_DSP_BASE } /** Array initializer of LSIO_LPCG_MU9_DSP peripheral base pointers */ #define LSIO_LPCG_MU9_DSP_BASE_PTRS { LSIO__LPCG_MU9_DSP } /*! * @} */ /* end of group LSIO_LPCG_MU9_DSP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU9_MCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU9_MCU_Peripheral_Access_Layer LSIO_LPCG_MU9_MCU Peripheral Access Layer * @{ */ /** LSIO_LPCG_MU9_MCU - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MU9_MCU_0; /**< na, offset: 0x0 */ } LSIO_LPCG_MU9_MCU_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_MU9_MCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_MU9_MCU_Register_Masks LSIO_LPCG_MU9_MCU Register Masks * @{ */ /*! @name LPCG_MU9_MCU_0 - na */ /*! @{ */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_SHIFT (0U) /*! LPCG_MU9_MCU_0_reserved_0_0 - reserved */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_MASK) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_MASK (0x2U) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_SHIFT (1U) /*! mu9_ipg_clk_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_MASK) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_SHIFT (2U) /*! LPCG_MU9_MCU_0_reserved_2_2 - reserved */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_MASK) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_MASK (0x8U) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_SHIFT (3U) /*! mu9_ipg_clk_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_MASK) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_MASK (0xFFF0U) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_SHIFT (4U) /*! LPCG_MU9_MCU_0_reserved_4_15 - reserved */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_MASK) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_MASK (0x10000U) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_SHIFT (16U) /*! mu9_ipg_clk_s_mcu_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_MASK) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_MASK (0x20000U) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_SHIFT (17U) /*! mu9_ipg_clk_s_mcu_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_MASK) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_SHIFT (18U) /*! LPCG_MU9_MCU_0_reserved_18_18 - reserved */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_MASK) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_MASK (0x80000U) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_SHIFT (19U) /*! mu9_ipg_clk_s_mcu_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_MASK) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_MASK (0xFFF00000U) #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_SHIFT (20U) /*! LPCG_MU9_MCU_0_reserved_20_31 - reserved */ #define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_MU9_MCU_Register_Masks */ /* LSIO_LPCG_MU9_MCU - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_MU9_MCU base address */ #define LSIO__LPCG_MU9_MCU_BASE (0x5D640000u) /** Peripheral LSIO__LPCG_MU9_MCU base pointer */ #define LSIO__LPCG_MU9_MCU ((LSIO_LPCG_MU9_MCU_Type *)LSIO__LPCG_MU9_MCU_BASE) /** Array initializer of LSIO_LPCG_MU9_MCU peripheral base addresses */ #define LSIO_LPCG_MU9_MCU_BASE_ADDRS { LSIO__LPCG_MU9_MCU_BASE } /** Array initializer of LSIO_LPCG_MU9_MCU peripheral base pointers */ #define LSIO_LPCG_MU9_MCU_BASE_PTRS { LSIO__LPCG_MU9_MCU } /*! * @} */ /* end of group LSIO_LPCG_MU9_MCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_OCRAM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_OCRAM_Peripheral_Access_Layer LSIO_LPCG_OCRAM Peripheral Access Layer * @{ */ /** LSIO_LPCG_OCRAM - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_OCRAM_0; /**< na, offset: 0x0 */ } LSIO_LPCG_OCRAM_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_OCRAM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_OCRAM_Register_Masks LSIO_LPCG_OCRAM Register Masks * @{ */ /*! @name LPCG_OCRAM_0 - na */ /*! @{ */ #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_SHIFT (0U) /*! LPCG_OCRAM_0_reserved_0_0 - reserved */ #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_MASK) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_SHIFT (1U) /*! ocram_ctrl_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_MASK) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_SHIFT (2U) /*! LPCG_OCRAM_0_reserved_2_2 - reserved */ #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_MASK) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_MASK (0x8U) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_SHIFT (3U) /*! ocram_ctrl_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_MASK) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_SHIFT (4U) /*! LPCG_OCRAM_0_reserved_4_4 - reserved */ #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_MASK) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_MASK (0x20U) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_SHIFT (5U) /*! ocram_mem_wrapper_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_MASK) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_SHIFT (6U) /*! LPCG_OCRAM_0_reserved_6_6 - reserved */ #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_MASK) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_MASK (0x80U) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_SHIFT (7U) /*! ocram_mem_wrapper_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_MASK) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_MASK (0xFFFFFF00U) #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_SHIFT (8U) /*! LPCG_OCRAM_0_reserved_8_31 - reserved */ #define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_OCRAM_Register_Masks */ /* LSIO_LPCG_OCRAM - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_OCRAM base address */ #define LSIO__LPCG_OCRAM_BASE (0x5D590000u) /** Peripheral LSIO__LPCG_OCRAM base pointer */ #define LSIO__LPCG_OCRAM ((LSIO_LPCG_OCRAM_Type *)LSIO__LPCG_OCRAM_BASE) /** Array initializer of LSIO_LPCG_OCRAM peripheral base addresses */ #define LSIO_LPCG_OCRAM_BASE_ADDRS { LSIO__LPCG_OCRAM_BASE } /** Array initializer of LSIO_LPCG_OCRAM peripheral base pointers */ #define LSIO_LPCG_OCRAM_BASE_PTRS { LSIO__LPCG_OCRAM } /*! * @} */ /* end of group LSIO_LPCG_OCRAM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM0_Peripheral_Access_Layer LSIO_LPCG_PWM0 Peripheral Access Layer * @{ */ /** LSIO_LPCG_PWM0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_PWM0_0; /**< na, offset: 0x0 */ } LSIO_LPCG_PWM0_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM0_Register_Masks LSIO_LPCG_PWM0 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_PWM0_0 - na */ /*! @{ */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_SHIFT (0U) /*! pwm0_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_SHIFT (1U) /*! pwm0_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_2_2 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_SHIFT (3U) /*! pwm0_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_4_4 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! pwm0_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_6_6 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_SHIFT (7U) /*! pwm0_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_8_8 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper5_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_10_10 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper5_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_12_15 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_18_18 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_SHIFT (19U) /*! pwm0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_20_20 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_pwm0_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_22_22 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_pwm0_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_pwm0_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_pwm0_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_26_26 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_pwm0_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_PWM0_0_reserved_28_31 - reserved */ #define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_PWM0_Register_Masks */ /* LSIO_LPCG_PWM0 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_PWM0 base address */ #define LSIO__LPCG_PWM0_BASE (0x5D400000u) /** Peripheral LSIO__LPCG_PWM0 base pointer */ #define LSIO__LPCG_PWM0 ((LSIO_LPCG_PWM0_Type *)LSIO__LPCG_PWM0_BASE) /** Array initializer of LSIO_LPCG_PWM0 peripheral base addresses */ #define LSIO_LPCG_PWM0_BASE_ADDRS { LSIO__LPCG_PWM0_BASE } /** Array initializer of LSIO_LPCG_PWM0 peripheral base pointers */ #define LSIO_LPCG_PWM0_BASE_PTRS { LSIO__LPCG_PWM0 } /*! * @} */ /* end of group LSIO_LPCG_PWM0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM1_Peripheral_Access_Layer LSIO_LPCG_PWM1 Peripheral Access Layer * @{ */ /** LSIO_LPCG_PWM1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_PWM1_0; /**< na, offset: 0x0 */ } LSIO_LPCG_PWM1_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM1_Register_Masks LSIO_LPCG_PWM1 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_PWM1_0 - na */ /*! @{ */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_SHIFT (0U) /*! pwm1_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_SHIFT (1U) /*! pwm1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_2_2 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_SHIFT (3U) /*! pwm1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_4_4 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! pwm1_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_6_6 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_SHIFT (7U) /*! pwm1_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_8_8 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper6_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_10_10 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper6_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_12_15 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_18_18 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_SHIFT (19U) /*! pwm1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_20_20 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_pwm1_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_22_22 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_pwm1_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_pwm1_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_pwm1_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_26_26 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_pwm1_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_PWM1_0_reserved_28_31 - reserved */ #define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_PWM1_Register_Masks */ /* LSIO_LPCG_PWM1 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_PWM1 base address */ #define LSIO__LPCG_PWM1_BASE (0x5D410000u) /** Peripheral LSIO__LPCG_PWM1 base pointer */ #define LSIO__LPCG_PWM1 ((LSIO_LPCG_PWM1_Type *)LSIO__LPCG_PWM1_BASE) /** Array initializer of LSIO_LPCG_PWM1 peripheral base addresses */ #define LSIO_LPCG_PWM1_BASE_ADDRS { LSIO__LPCG_PWM1_BASE } /** Array initializer of LSIO_LPCG_PWM1 peripheral base pointers */ #define LSIO_LPCG_PWM1_BASE_PTRS { LSIO__LPCG_PWM1 } /*! * @} */ /* end of group LSIO_LPCG_PWM1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM2_Peripheral_Access_Layer LSIO_LPCG_PWM2 Peripheral Access Layer * @{ */ /** LSIO_LPCG_PWM2 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_PWM2_0; /**< na, offset: 0x0 */ } LSIO_LPCG_PWM2_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM2_Register_Masks LSIO_LPCG_PWM2 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_PWM2_0 - na */ /*! @{ */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_SHIFT (0U) /*! pwm2_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_SHIFT (1U) /*! pwm2_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_2_2 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_SHIFT (3U) /*! pwm2_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_4_4 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! pwm2_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_6_6 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_SHIFT (7U) /*! pwm2_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_8_8 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper7_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_10_10 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper7_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_12_15 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm2_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm2_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_18_18 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_SHIFT (19U) /*! pwm2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_20_20 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_pwm2_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_22_22 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_pwm2_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_pwm2_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_pwm2_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_26_26 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_pwm2_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_PWM2_0_reserved_28_31 - reserved */ #define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_PWM2_Register_Masks */ /* LSIO_LPCG_PWM2 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_PWM2 base address */ #define LSIO__LPCG_PWM2_BASE (0x5D420000u) /** Peripheral LSIO__LPCG_PWM2 base pointer */ #define LSIO__LPCG_PWM2 ((LSIO_LPCG_PWM2_Type *)LSIO__LPCG_PWM2_BASE) /** Array initializer of LSIO_LPCG_PWM2 peripheral base addresses */ #define LSIO_LPCG_PWM2_BASE_ADDRS { LSIO__LPCG_PWM2_BASE } /** Array initializer of LSIO_LPCG_PWM2 peripheral base pointers */ #define LSIO_LPCG_PWM2_BASE_PTRS { LSIO__LPCG_PWM2 } /*! * @} */ /* end of group LSIO_LPCG_PWM2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM3_Peripheral_Access_Layer LSIO_LPCG_PWM3 Peripheral Access Layer * @{ */ /** LSIO_LPCG_PWM3 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_PWM3_0; /**< na, offset: 0x0 */ } LSIO_LPCG_PWM3_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM3_Register_Masks LSIO_LPCG_PWM3 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_PWM3_0 - na */ /*! @{ */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_SHIFT (0U) /*! pwm3_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_SHIFT (1U) /*! pwm3_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_2_2 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_SHIFT (3U) /*! pwm3_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_4_4 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! pwm3_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_6_6 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_SHIFT (7U) /*! pwm3_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_8_8 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper8_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_10_10 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper8_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_12_15 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm3_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm3_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_18_18 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_SHIFT (19U) /*! pwm3_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_20_20 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_pwm3_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_22_22 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_pwm3_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_pwm3_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_pwm3_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_26_26 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_pwm3_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_PWM3_0_reserved_28_31 - reserved */ #define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_PWM3_Register_Masks */ /* LSIO_LPCG_PWM3 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_PWM3 base address */ #define LSIO__LPCG_PWM3_BASE (0x5D430000u) /** Peripheral LSIO__LPCG_PWM3 base pointer */ #define LSIO__LPCG_PWM3 ((LSIO_LPCG_PWM3_Type *)LSIO__LPCG_PWM3_BASE) /** Array initializer of LSIO_LPCG_PWM3 peripheral base addresses */ #define LSIO_LPCG_PWM3_BASE_ADDRS { LSIO__LPCG_PWM3_BASE } /** Array initializer of LSIO_LPCG_PWM3 peripheral base pointers */ #define LSIO_LPCG_PWM3_BASE_PTRS { LSIO__LPCG_PWM3 } /*! * @} */ /* end of group LSIO_LPCG_PWM3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM4_Peripheral_Access_Layer LSIO_LPCG_PWM4 Peripheral Access Layer * @{ */ /** LSIO_LPCG_PWM4 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_PWM4_0; /**< na, offset: 0x0 */ } LSIO_LPCG_PWM4_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM4_Register_Masks LSIO_LPCG_PWM4 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_PWM4_0 - na */ /*! @{ */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_SHIFT (0U) /*! pwm4_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_SHIFT (1U) /*! pwm4_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_2_2 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_SHIFT (3U) /*! pwm4_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_4_4 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! pwm4_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_6_6 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_SHIFT (7U) /*! pwm4_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_8_8 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper9_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_10_10 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper9_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_12_15 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm4_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm4_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_18_18 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_SHIFT (19U) /*! pwm4_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_20_20 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_pwm4_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_22_22 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_pwm4_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_pwm4_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_pwm4_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_26_26 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_pwm4_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_PWM4_0_reserved_28_31 - reserved */ #define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_PWM4_Register_Masks */ /* LSIO_LPCG_PWM4 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_PWM4 base address */ #define LSIO__LPCG_PWM4_BASE (0x5D440000u) /** Peripheral LSIO__LPCG_PWM4 base pointer */ #define LSIO__LPCG_PWM4 ((LSIO_LPCG_PWM4_Type *)LSIO__LPCG_PWM4_BASE) /** Array initializer of LSIO_LPCG_PWM4 peripheral base addresses */ #define LSIO_LPCG_PWM4_BASE_ADDRS { LSIO__LPCG_PWM4_BASE } /** Array initializer of LSIO_LPCG_PWM4 peripheral base pointers */ #define LSIO_LPCG_PWM4_BASE_PTRS { LSIO__LPCG_PWM4 } /*! * @} */ /* end of group LSIO_LPCG_PWM4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM5_Peripheral_Access_Layer LSIO_LPCG_PWM5 Peripheral Access Layer * @{ */ /** LSIO_LPCG_PWM5 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_PWM5_0; /**< na, offset: 0x0 */ } LSIO_LPCG_PWM5_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM5_Register_Masks LSIO_LPCG_PWM5 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_PWM5_0 - na */ /*! @{ */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_SHIFT (0U) /*! pwm5_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_SHIFT (1U) /*! pwm5_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_2_2 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_SHIFT (3U) /*! pwm5_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_4_4 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! pwm5_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_6_6 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_SHIFT (7U) /*! pwm5_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_8_8 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper10_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_10_10 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper10_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_12_15 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm5_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm5_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_18_18 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_SHIFT (19U) /*! pwm5_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_20_20 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_pwm5_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_22_22 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_pwm5_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_pwm5_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_pwm5_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_26_26 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_pwm5_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_PWM5_0_reserved_28_31 - reserved */ #define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_PWM5_Register_Masks */ /* LSIO_LPCG_PWM5 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_PWM5 base address */ #define LSIO__LPCG_PWM5_BASE (0x5D450000u) /** Peripheral LSIO__LPCG_PWM5 base pointer */ #define LSIO__LPCG_PWM5 ((LSIO_LPCG_PWM5_Type *)LSIO__LPCG_PWM5_BASE) /** Array initializer of LSIO_LPCG_PWM5 peripheral base addresses */ #define LSIO_LPCG_PWM5_BASE_ADDRS { LSIO__LPCG_PWM5_BASE } /** Array initializer of LSIO_LPCG_PWM5 peripheral base pointers */ #define LSIO_LPCG_PWM5_BASE_PTRS { LSIO__LPCG_PWM5 } /*! * @} */ /* end of group LSIO_LPCG_PWM5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM6 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM6_Peripheral_Access_Layer LSIO_LPCG_PWM6 Peripheral Access Layer * @{ */ /** LSIO_LPCG_PWM6 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_PWM6_0; /**< na, offset: 0x0 */ } LSIO_LPCG_PWM6_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM6 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM6_Register_Masks LSIO_LPCG_PWM6 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_PWM6_0 - na */ /*! @{ */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_SHIFT (0U) /*! pwm6_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_SHIFT (1U) /*! pwm6_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_2_2 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_SHIFT (3U) /*! pwm6_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_4_4 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! pwm6_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_6_6 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_SHIFT (7U) /*! pwm6_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_8_8 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper11_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_10_10 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper11_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_12_15 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm6_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm6_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_18_18 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_SHIFT (19U) /*! pwm6_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_20_20 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_pwm6_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_22_22 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_pwm6_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_pwm6_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_pwm6_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_26_26 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_pwm6_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_PWM6_0_reserved_28_31 - reserved */ #define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_PWM6_Register_Masks */ /* LSIO_LPCG_PWM6 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_PWM6 base address */ #define LSIO__LPCG_PWM6_BASE (0x5D460000u) /** Peripheral LSIO__LPCG_PWM6 base pointer */ #define LSIO__LPCG_PWM6 ((LSIO_LPCG_PWM6_Type *)LSIO__LPCG_PWM6_BASE) /** Array initializer of LSIO_LPCG_PWM6 peripheral base addresses */ #define LSIO_LPCG_PWM6_BASE_ADDRS { LSIO__LPCG_PWM6_BASE } /** Array initializer of LSIO_LPCG_PWM6 peripheral base pointers */ #define LSIO_LPCG_PWM6_BASE_PTRS { LSIO__LPCG_PWM6 } /*! * @} */ /* end of group LSIO_LPCG_PWM6_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM7 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM7_Peripheral_Access_Layer LSIO_LPCG_PWM7 Peripheral Access Layer * @{ */ /** LSIO_LPCG_PWM7 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_IPS_SYNC_PWM7_0; /**< na, offset: 0x0 */ } LSIO_LPCG_PWM7_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_PWM7 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_PWM7_Register_Masks LSIO_LPCG_PWM7 Register Masks * @{ */ /*! @name LPCG_IPS_SYNC_PWM7_0 - na */ /*! @{ */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_MASK (0x1U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_SHIFT (0U) /*! pwm7_ipg_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_MASK (0x2U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_SHIFT (1U) /*! pwm7_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_SHIFT (2U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_2_2 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_MASK (0x8U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_SHIFT (3U) /*! pwm7_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_MASK (0x10U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_SHIFT (4U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_4_4 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_MASK (0x20U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_SHIFT (5U) /*! pwm7_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_MASK (0x40U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_SHIFT (6U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_6_6 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_MASK (0x80U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_SHIFT (7U) /*! pwm7_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_MASK (0x100U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_SHIFT (8U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_8_8 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_MASK (0x200U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_SHIFT (9U) /*! ccm_ckil_sync_wrapper12_clk_in_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_MASK (0x400U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_SHIFT (10U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_10_10 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_MASK (0x800U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_SHIFT (11U) /*! ccm_ckil_sync_wrapper12_clk_in_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_MASK (0xF000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_SHIFT (12U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_12_15 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_MASK (0x10000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm7_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_MASK (0x20000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm7_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_SHIFT (18U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_18_18 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_MASK (0x80000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_SHIFT (19U) /*! pwm7_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_SHIFT (20U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_20_20 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_SHIFT (21U) /*! ips_sync_pwm7_ipg_slave_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_SHIFT (22U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_22_22 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_SHIFT (23U) /*! ips_sync_pwm7_ipg_slave_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_MASK (0x1000000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_SHIFT (24U) /*! ips_sync_pwm7_ipg_master_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_MASK (0x2000000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_SHIFT (25U) /*! ips_sync_pwm7_ipg_master_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_SHIFT (26U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_26_26 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_MASK (0x8000000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_SHIFT (27U) /*! ips_sync_pwm7_ipg_master_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_MASK) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_SHIFT (28U) /*! LPCG_IPS_SYNC_PWM7_0_reserved_28_31 - reserved */ #define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_PWM7_Register_Masks */ /* LSIO_LPCG_PWM7 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_PWM7 base address */ #define LSIO__LPCG_PWM7_BASE (0x5D470000u) /** Peripheral LSIO__LPCG_PWM7 base pointer */ #define LSIO__LPCG_PWM7 ((LSIO_LPCG_PWM7_Type *)LSIO__LPCG_PWM7_BASE) /** Array initializer of LSIO_LPCG_PWM7 peripheral base addresses */ #define LSIO_LPCG_PWM7_BASE_ADDRS { LSIO__LPCG_PWM7_BASE } /** Array initializer of LSIO_LPCG_PWM7 peripheral base pointers */ #define LSIO_LPCG_PWM7_BASE_PTRS { LSIO__LPCG_PWM7 } /*! * @} */ /* end of group LSIO_LPCG_PWM7_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_QSPI0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_QSPI0_Peripheral_Access_Layer LSIO_LPCG_QSPI0 Peripheral Access Layer * @{ */ /** LSIO_LPCG_QSPI0 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_QSPI0_0; /**< na, offset: 0x0 */ } LSIO_LPCG_QSPI0_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_QSPI0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_QSPI0_Register_Masks LSIO_LPCG_QSPI0 Register Masks * @{ */ /*! @name LPCG_QSPI0_0 - na */ /*! @{ */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_SHIFT (0U) /*! LPCG_QSPI0_0_reserved_0_0 - reserved */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_MASK (0x2U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_SHIFT (1U) /*! qspi0_ipg_clk_sfck_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_SHIFT (2U) /*! LPCG_QSPI0_0_reserved_2_2 - reserved */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_MASK (0x8U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_SHIFT (3U) /*! qspi0_ipg_clk_sfck_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_MASK (0x1FFF0U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_SHIFT (4U) /*! LPCG_QSPI0_0_reserved_4_16 - reserved */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_MASK (0x20000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_SHIFT (17U) /*! qspi0_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_SHIFT (18U) /*! LPCG_QSPI0_0_reserved_18_18 - reserved */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_MASK (0x80000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_SHIFT (19U) /*! qspi0_hclk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_SHIFT (20U) /*! LPCG_QSPI0_0_reserved_20_20 - reserved */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_SHIFT (21U) /*! qspi0_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_SHIFT (22U) /*! LPCG_QSPI0_0_reserved_22_22 - reserved */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_SHIFT (23U) /*! qspi0_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_MASK (0x1000000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_SHIFT (24U) /*! qspi0_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_MASK (0x2000000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_SHIFT (25U) /*! qspi0_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_SHIFT (26U) /*! LPCG_QSPI0_0_reserved_26_26 - reserved */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_MASK (0x8000000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_SHIFT (27U) /*! qspi0_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_SHIFT (28U) /*! LPCG_QSPI0_0_reserved_28_31 - reserved */ #define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_QSPI0_Register_Masks */ /* LSIO_LPCG_QSPI0 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_QSPI0 base address */ #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) /** Peripheral LSIO__LPCG_QSPI0 base pointer */ #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE) /** Array initializer of LSIO_LPCG_QSPI0 peripheral base addresses */ #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE } /** Array initializer of LSIO_LPCG_QSPI0 peripheral base pointers */ #define LSIO_LPCG_QSPI0_BASE_PTRS { LSIO__LPCG_QSPI0 } /*! * @} */ /* end of group LSIO_LPCG_QSPI0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LSIO_LPCG_QSPI1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_QSPI1_Peripheral_Access_Layer LSIO_LPCG_QSPI1 Peripheral Access Layer * @{ */ /** LSIO_LPCG_QSPI1 - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_QSPI1_0; /**< na, offset: 0x0 */ } LSIO_LPCG_QSPI1_Type; /* ---------------------------------------------------------------------------- -- LSIO_LPCG_QSPI1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LSIO_LPCG_QSPI1_Register_Masks LSIO_LPCG_QSPI1 Register Masks * @{ */ /*! @name LPCG_QSPI1_0 - na */ /*! @{ */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_MASK (0x1U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_SHIFT (0U) /*! LPCG_QSPI1_0_reserved_0_0 - reserved */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_MASK (0x2U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_SHIFT (1U) /*! qspi1_ipg_clk_sfck_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_MASK (0x4U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_SHIFT (2U) /*! LPCG_QSPI1_0_reserved_2_2 - reserved */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_MASK (0x8U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_SHIFT (3U) /*! qspi1_ipg_clk_sfck_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_MASK (0x1FFF0U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_SHIFT (4U) /*! LPCG_QSPI1_0_reserved_4_16 - reserved */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_MASK (0x20000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_SHIFT (17U) /*! qspi1_hclk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_MASK (0x40000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_SHIFT (18U) /*! LPCG_QSPI1_0_reserved_18_18 - reserved */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_MASK (0x80000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_SHIFT (19U) /*! qspi1_hclk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_MASK (0x100000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_SHIFT (20U) /*! LPCG_QSPI1_0_reserved_20_20 - reserved */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_MASK (0x200000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_SHIFT (21U) /*! qspi1_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_MASK (0x400000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_SHIFT (22U) /*! LPCG_QSPI1_0_reserved_22_22 - reserved */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_MASK (0x800000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_SHIFT (23U) /*! qspi1_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_MASK (0x1000000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_SHIFT (24U) /*! qspi1_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_MASK (0x2000000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_SHIFT (25U) /*! qspi1_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_MASK (0x4000000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_SHIFT (26U) /*! LPCG_QSPI1_0_reserved_26_26 - reserved */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_MASK (0x8000000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_SHIFT (27U) /*! qspi1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_MASK) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_MASK (0xF0000000U) #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_SHIFT (28U) /*! LPCG_QSPI1_0_reserved_28_31 - reserved */ #define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_MASK) /*! @} */ /*! * @} */ /* end of group LSIO_LPCG_QSPI1_Register_Masks */ /* LSIO_LPCG_QSPI1 - Peripheral instance base addresses */ /** Peripheral LSIO__LPCG_QSPI1 base address */ #define LSIO__LPCG_QSPI1_BASE (0x5D530000u) /** Peripheral LSIO__LPCG_QSPI1 base pointer */ #define LSIO__LPCG_QSPI1 ((LSIO_LPCG_QSPI1_Type *)LSIO__LPCG_QSPI1_BASE) /** Array initializer of LSIO_LPCG_QSPI1 peripheral base addresses */ #define LSIO_LPCG_QSPI1_BASE_ADDRS { LSIO__LPCG_QSPI1_BASE } /** Array initializer of LSIO_LPCG_QSPI1 peripheral base pointers */ #define LSIO_LPCG_QSPI1_BASE_PTRS { LSIO__LPCG_QSPI1 } /*! * @} */ /* end of group LSIO_LPCG_QSPI1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LTS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LTS_Peripheral_Access_Layer LTS Peripheral Access Layer * @{ */ /** LTS - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< LTS Control Register, offset: 0x0 */ __IO uint32_t SET; /**< LTS Control Register, offset: 0x4 */ __IO uint32_t CLR; /**< LTS Control Register, offset: 0x8 */ __IO uint32_t TOG; /**< LTS Control Register, offset: 0xC */ } LTS_CTRL; struct { /* offset: 0x10 */ __IO uint32_t RW; /**< LTS IRQ Mask Register, offset: 0x10 */ __IO uint32_t SET; /**< LTS IRQ Mask Register, offset: 0x14 */ __IO uint32_t CLR; /**< LTS IRQ Mask Register, offset: 0x18 */ __IO uint32_t TOG; /**< LTS IRQ Mask Register, offset: 0x1C */ } LTS_IRQ_MASK; struct { /* offset: 0x20 */ __IO uint32_t RW; /**< LTS IRQ State Register, offset: 0x20 */ __IO uint32_t SET; /**< LTS IRQ State Register, offset: 0x24 */ __IO uint32_t CLR; /**< LTS IRQ State Register, offset: 0x28 */ __IO uint32_t TOG; /**< LTS IRQ State Register, offset: 0x2C */ } LTS_IRQ_STAT; struct { /* offset: 0x30 */ __IO uint32_t RW; /**< LTS BUF base address Register, offset: 0x30 */ __IO uint32_t SET; /**< LTS BUF base address Register, offset: 0x34 */ __IO uint32_t CLR; /**< LTS BUF base address Register, offset: 0x38 */ __IO uint32_t TOG; /**< LTS BUF base address Register, offset: 0x3C */ } LTS_BUF; struct { /* offset: 0x40 */ __IO uint32_t RW; /**< LTS BUS control Register, offset: 0x40 */ __IO uint32_t SET; /**< LTS BUS control Register, offset: 0x44 */ __IO uint32_t CLR; /**< LTS BUS control Register, offset: 0x48 */ __IO uint32_t TOG; /**< LTS BUS control Register, offset: 0x4C */ } LTS_BUS_CTRL; struct { /* offset: 0x50 */ __IO uint32_t RW; /**< LTS SIZE control Register, offset: 0x50 */ __IO uint32_t SET; /**< LTS SIZE control Register, offset: 0x54 */ __IO uint32_t CLR; /**< LTS SIZE control Register, offset: 0x58 */ __IO uint32_t TOG; /**< LTS SIZE control Register, offset: 0x5C */ } LTS_SIZE; struct { /* offset: 0x60 */ __IO uint32_t RW; /**< LTS SIZE control Register, offset: 0x60 */ __IO uint32_t SET; /**< LTS SIZE control Register, offset: 0x64 */ __IO uint32_t CLR; /**< LTS SIZE control Register, offset: 0x68 */ __IO uint32_t TOG; /**< LTS SIZE control Register, offset: 0x6C */ } LTS_OFFSET; struct { /* offset: 0x70 */ __IO uint32_t RW; /**< LTS SIZE control Register, offset: 0x70 */ __IO uint32_t SET; /**< LTS SIZE control Register, offset: 0x74 */ __IO uint32_t CLR; /**< LTS SIZE control Register, offset: 0x78 */ __IO uint32_t TOG; /**< LTS SIZE control Register, offset: 0x7C */ } LTS_PITCH; struct { /* offset: 0x80 */ __I uint32_t RW; /**< LTS version Register, offset: 0x80 */ __I uint32_t SET; /**< LTS version Register, offset: 0x84 */ __I uint32_t CLR; /**< LTS version Register, offset: 0x88 */ __I uint32_t TOG; /**< LTS version Register, offset: 0x8C */ } LTS_VERSION; struct { /* offset: 0x90 */ __IO uint32_t RW; /**< LTS DEBUG control Register, offset: 0x90 */ __IO uint32_t SET; /**< LTS DEBUG control Register, offset: 0x94 */ __IO uint32_t CLR; /**< LTS DEBUG control Register, offset: 0x98 */ __IO uint32_t TOG; /**< LTS DEBUG control Register, offset: 0x9C */ } LTS_DEBUG_CTRL; struct { /* offset: 0xA0 */ __I uint32_t RW; /**< LTS DEBUG data Register, offset: 0xA0 */ __I uint32_t SET; /**< LTS DEBUG data Register, offset: 0xA4 */ __I uint32_t CLR; /**< LTS DEBUG data Register, offset: 0xA8 */ __I uint32_t TOG; /**< LTS DEBUG data Register, offset: 0xAC */ } LTS_DEBUG; } LTS_Type; /* ---------------------------------------------------------------------------- -- LTS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LTS_Register_Masks LTS Register Masks * @{ */ /*! @name LTS_CTRL - LTS Control Register */ /*! @{ */ #define LTS_LTS_CTRL_ENABLE_MASK (0x1U) #define LTS_LTS_CTRL_ENABLE_SHIFT (0U) /*! ENABLE - Enables LTS operation with specified parameters. The ENABLE bit will be auto cleared * when LTS starting process, software can polling zero and update next operation parameters */ #define LTS_LTS_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_CTRL_ENABLE_SHIFT)) & LTS_LTS_CTRL_ENABLE_MASK) #define LTS_LTS_CTRL_CLKGATE_MASK (0x40000000U) #define LTS_LTS_CTRL_CLKGATE_SHIFT (30U) /*! CLKGATE - This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. */ #define LTS_LTS_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_CTRL_CLKGATE_SHIFT)) & LTS_LTS_CTRL_CLKGATE_MASK) #define LTS_LTS_CTRL_SFTRST_MASK (0x80000000U) #define LTS_LTS_CTRL_SFTRST_SHIFT (31U) /*! SFTRST - Set this bit to zero to enable normal LTS operation. Set this bit to one (default) to * disable clocking with the LTS and hold it in its reset (lowest power) state. This bit can be * turned on and then off to reset the LTS block to its default state. */ #define LTS_LTS_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_CTRL_SFTRST_SHIFT)) & LTS_LTS_CTRL_SFTRST_MASK) /*! @} */ /*! @name LTS_IRQ_MASK - LTS IRQ Mask Register */ /*! @{ */ #define LTS_LTS_IRQ_MASK_LTS_START_IRQ_EN_MASK (0x1U) #define LTS_LTS_IRQ_MASK_LTS_START_IRQ_EN_SHIFT (0U) /*! LTS_START_IRQ_EN - Enable LTS engine start interrupt detection */ #define LTS_LTS_IRQ_MASK_LTS_START_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_IRQ_MASK_LTS_START_IRQ_EN_SHIFT)) & LTS_LTS_IRQ_MASK_LTS_START_IRQ_EN_MASK) #define LTS_LTS_IRQ_MASK_LTS_DONE_IRQ_EN_MASK (0x2U) #define LTS_LTS_IRQ_MASK_LTS_DONE_IRQ_EN_SHIFT (1U) /*! LTS_DONE_IRQ_EN - Enable LTS engine done interrupt detection */ #define LTS_LTS_IRQ_MASK_LTS_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_IRQ_MASK_LTS_DONE_IRQ_EN_SHIFT)) & LTS_LTS_IRQ_MASK_LTS_DONE_IRQ_EN_MASK) #define LTS_LTS_IRQ_MASK_S_AXI_ERR_EN_MASK (0x4U) #define LTS_LTS_IRQ_MASK_S_AXI_ERR_EN_SHIFT (2U) /*! S_AXI_ERR_EN - Enable LTS engine S_AXI error interrupt detection */ #define LTS_LTS_IRQ_MASK_S_AXI_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_IRQ_MASK_S_AXI_ERR_EN_SHIFT)) & LTS_LTS_IRQ_MASK_S_AXI_ERR_EN_MASK) #define LTS_LTS_IRQ_MASK_M_AXI_ERR_EN_MASK (0x8U) #define LTS_LTS_IRQ_MASK_M_AXI_ERR_EN_SHIFT (3U) /*! M_AXI_ERR_EN - Enable LTS engine M_AXI error interrupt detection */ #define LTS_LTS_IRQ_MASK_M_AXI_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_IRQ_MASK_M_AXI_ERR_EN_SHIFT)) & LTS_LTS_IRQ_MASK_M_AXI_ERR_EN_MASK) /*! @} */ /*! @name LTS_IRQ_STAT - LTS IRQ State Register */ /*! @{ */ #define LTS_LTS_IRQ_STAT_LTS_START_IRQ_MASK (0x1U) #define LTS_LTS_IRQ_STAT_LTS_START_IRQ_SHIFT (0U) /*! LTS_START_IRQ - Enable LTS engine start interrupt detection */ #define LTS_LTS_IRQ_STAT_LTS_START_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_IRQ_STAT_LTS_START_IRQ_SHIFT)) & LTS_LTS_IRQ_STAT_LTS_START_IRQ_MASK) #define LTS_LTS_IRQ_STAT_LTS_DONE_IRQ_MASK (0x2U) #define LTS_LTS_IRQ_STAT_LTS_DONE_IRQ_SHIFT (1U) /*! LTS_DONE_IRQ - Enable LTS engine done interrupt detection */ #define LTS_LTS_IRQ_STAT_LTS_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_IRQ_STAT_LTS_DONE_IRQ_SHIFT)) & LTS_LTS_IRQ_STAT_LTS_DONE_IRQ_MASK) #define LTS_LTS_IRQ_STAT_S_AXI_ERROR_MASK (0x4U) #define LTS_LTS_IRQ_STAT_S_AXI_ERROR_SHIFT (2U) /*! S_AXI_ERROR - Enable LTS engine S_AXI error interrupt detection */ #define LTS_LTS_IRQ_STAT_S_AXI_ERROR(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_IRQ_STAT_S_AXI_ERROR_SHIFT)) & LTS_LTS_IRQ_STAT_S_AXI_ERROR_MASK) #define LTS_LTS_IRQ_STAT_M_AXI_ERROR_MASK (0x8U) #define LTS_LTS_IRQ_STAT_M_AXI_ERROR_SHIFT (3U) /*! M_AXI_ERROR - Enable LTS engine M_AXI error interrupt detection */ #define LTS_LTS_IRQ_STAT_M_AXI_ERROR(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_IRQ_STAT_M_AXI_ERROR_SHIFT)) & LTS_LTS_IRQ_STAT_M_AXI_ERROR_MASK) /*! @} */ /*! @name LTS_BUF - LTS BUF base address Register */ /*! @{ */ #define LTS_LTS_BUF_ADDR_MASK (0xFFFFFFFFU) #define LTS_LTS_BUF_ADDR_SHIFT (0U) /*! ADDR - Byte aligned start address of the destination buffer. For 32 bit pixels BaseAddress[1:0] * must be set 0 and for 16 bit pixels BaseAddress[0] must be set 0. */ #define LTS_LTS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_BUF_ADDR_SHIFT)) & LTS_LTS_BUF_ADDR_MASK) /*! @} */ /*! @name LTS_BUS_CTRL - LTS BUS control Register */ /*! @{ */ #define LTS_LTS_BUS_CTRL_TILE_FORMAT_MASK (0x1U) #define LTS_LTS_BUS_CTRL_TILE_FORMAT_SHIFT (0U) /*! TILE_FORMAT - Select tile format output 0x0: GPU 32-bit pixels, single buffer, GPU 4x4 Standard * tile 0x1: GPU 16-bit pixels, single buffer, GPU 8x4 Standard tile */ #define LTS_LTS_BUS_CTRL_TILE_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_BUS_CTRL_TILE_FORMAT_SHIFT)) & LTS_LTS_BUS_CTRL_TILE_FORMAT_MASK) #define LTS_LTS_BUS_CTRL_AXI_LEN_MASK (0x10000U) #define LTS_LTS_BUS_CTRL_AXI_LEN_SHIFT (16U) /*! AXI_LEN - Set this to the burst length that should be used on the AXI interface. 0x0: AXI burst * length is 8, one GPU Standard tile 0x1: AXI burst length is 16, two GPU Standard tiles */ #define LTS_LTS_BUS_CTRL_AXI_LEN(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_BUS_CTRL_AXI_LEN_SHIFT)) & LTS_LTS_BUS_CTRL_AXI_LEN_MASK) /*! @} */ /*! @name LTS_SIZE - LTS SIZE control Register */ /*! @{ */ #define LTS_LTS_SIZE_WIDTH_MASK (0x3FFFU) #define LTS_LTS_SIZE_WIDTH_SHIFT (0U) /*! WIDTH - Select tile format output */ #define LTS_LTS_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_SIZE_WIDTH_SHIFT)) & LTS_LTS_SIZE_WIDTH_MASK) #define LTS_LTS_SIZE_HEIGHT_MASK (0x3FFF0000U) #define LTS_LTS_SIZE_HEIGHT_SHIFT (16U) /*! HEIGHT - Select tile format output */ #define LTS_LTS_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_SIZE_HEIGHT_SHIFT)) & LTS_LTS_SIZE_HEIGHT_MASK) /*! @} */ /*! @name LTS_OFFSET - LTS SIZE control Register */ /*! @{ */ #define LTS_LTS_OFFSET_X_OFFSET_MASK (0x7FFFU) #define LTS_LTS_OFFSET_X_OFFSET_SHIFT (0U) /*! X_OFFSET - This field indicates the Vertical offset(Y) of the buffer */ #define LTS_LTS_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_OFFSET_X_OFFSET_SHIFT)) & LTS_LTS_OFFSET_X_OFFSET_MASK) #define LTS_LTS_OFFSET_Y_OFFSET_MASK (0x7FFF0000U) #define LTS_LTS_OFFSET_Y_OFFSET_SHIFT (16U) /*! Y_OFFSET - This field indicates the Horizontal offset(X) of the buffer */ #define LTS_LTS_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_OFFSET_Y_OFFSET_SHIFT)) & LTS_LTS_OFFSET_Y_OFFSET_MASK) /*! @} */ /*! @name LTS_PITCH - LTS SIZE control Register */ /*! @{ */ #define LTS_LTS_PITCH_STRIDE_MASK (0xFFFFFFFFU) #define LTS_LTS_PITCH_STRIDE_SHIFT (0U) /*! STRIDE - Destination buffer stride in bytes minus one, used for address generation. The stride * has to be dividable by 8 and given minus one. */ #define LTS_LTS_PITCH_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_PITCH_STRIDE_SHIFT)) & LTS_LTS_PITCH_STRIDE_MASK) /*! @} */ /*! @name LTS_VERSION - LTS version Register */ /*! @{ */ #define LTS_LTS_VERSION_STEP_MASK (0xFFFFU) #define LTS_LTS_VERSION_STEP_SHIFT (0U) /*! STEP - Fixed read-only value reflecting the stepping of the RTL version. */ #define LTS_LTS_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_VERSION_STEP_SHIFT)) & LTS_LTS_VERSION_STEP_MASK) #define LTS_LTS_VERSION_MINOR_MASK (0xFF0000U) #define LTS_LTS_VERSION_MINOR_SHIFT (16U) /*! MINOR - Fixed read-only value reflecting the stepping of the RTL version. */ #define LTS_LTS_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_VERSION_MINOR_SHIFT)) & LTS_LTS_VERSION_MINOR_MASK) #define LTS_LTS_VERSION_MAJOR_MASK (0xFF000000U) #define LTS_LTS_VERSION_MAJOR_SHIFT (24U) /*! MAJOR - Fixed read-only value reflecting the stepping of the RTL version. */ #define LTS_LTS_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_VERSION_MAJOR_SHIFT)) & LTS_LTS_VERSION_MAJOR_MASK) /*! @} */ /*! @name LTS_DEBUG_CTRL - LTS DEBUG control Register */ /*! @{ */ #define LTS_LTS_DEBUG_CTRL_SELECT_MASK (0xFU) #define LTS_LTS_DEBUG_CTRL_SELECT_SHIFT (0U) /*! SELECT - Index into one of the LTS debug registers. The data for the selected register will be returned. */ #define LTS_LTS_DEBUG_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_DEBUG_CTRL_SELECT_SHIFT)) & LTS_LTS_DEBUG_CTRL_SELECT_MASK) /*! @} */ /*! @name LTS_DEBUG - LTS DEBUG data Register */ /*! @{ */ #define LTS_LTS_DEBUG_DATA_MASK (0xFFFFFFFFU) #define LTS_LTS_DEBUG_DATA_SHIFT (0U) /*! DATA - The debug control register will select the desired debug field to be read through this * register offset. This register is not intended for customer use. */ #define LTS_LTS_DEBUG_DATA(x) (((uint32_t)(((uint32_t)(x)) << LTS_LTS_DEBUG_DATA_SHIFT)) & LTS_LTS_DEBUG_DATA_MASK) /*! @} */ /*! * @} */ /* end of group LTS_Register_Masks */ /* LTS - Peripheral instance base addresses */ /** Peripheral DC__LTS base address */ #define DC__LTS_BASE (0x56030000u) /** Peripheral DC__LTS base pointer */ #define DC__LTS ((LTS_Type *)DC__LTS_BASE) /** Array initializer of LTS peripheral base addresses */ #define LTS_BASE_ADDRS { DC__LTS_BASE } /** Array initializer of LTS peripheral base pointers */ #define LTS_BASE_PTRS { DC__LTS } /*! * @} */ /* end of group LTS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer * @{ */ /** MCM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */ uint8_t RESERVED_1[16]; __I uint32_t FADR; /**< Fault address register, offset: 0x20 */ __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */ __I uint32_t FDR; /**< Fault data register, offset: 0x28 */ } MCM_Type; /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Masks MCM Register Masks * @{ */ /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ /*! @{ */ #define MCM_PLASC_ASC_MASK (0xFFU) #define MCM_PLASC_ASC_SHIFT (0U) /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the * crossbar switch's slave input port. * 0b00000000..A bus slave connection to AXBS input port n is absent * 0b00000001..A bus slave connection to AXBS input port n is present */ #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) /*! @} */ /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ /*! @{ */ #define MCM_PLAMC_AMC_MASK (0xFFU) #define MCM_PLAMC_AMC_SHIFT (0U) /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. * 0b00000000..A bus master connection to AXBS input port n is absent * 0b00000001..A bus master connection to AXBS input port n is present */ #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) /*! @} */ /*! @name FADR - Fault address register */ /*! @{ */ #define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU) #define MCM_FADR_ADDRESS_SHIFT (0U) /*! ADDRESS - Fault address */ #define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK) /*! @} */ /*! @name FATR - Fault attributes register */ /*! @{ */ #define MCM_FATR_BEDA_MASK (0x1U) #define MCM_FATR_BEDA_SHIFT (0U) /*! BEDA - Bus error access type * 0b0..Instruction * 0b1..Data */ #define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK) #define MCM_FATR_BEMD_MASK (0x2U) #define MCM_FATR_BEMD_SHIFT (1U) /*! BEMD - Bus error privilege level * 0b0..User mode * 0b1..Supervisor/privileged mode */ #define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK) #define MCM_FATR_BESZ_MASK (0x30U) #define MCM_FATR_BESZ_SHIFT (4U) /*! BESZ - Bus error size * 0b00..8-bit access * 0b01..16-bit access * 0b10..32-bit access * 0b11..Reserved */ #define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK) #define MCM_FATR_BEWT_MASK (0x80U) #define MCM_FATR_BEWT_SHIFT (7U) /*! BEWT - Bus error write * 0b0..Read access * 0b1..Write access */ #define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK) #define MCM_FATR_BEMN_MASK (0xF00U) #define MCM_FATR_BEMN_SHIFT (8U) /*! BEMN - Bus error master number */ #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) #define MCM_FATR_BEOVR_MASK (0x80000000U) #define MCM_FATR_BEOVR_SHIFT (31U) /*! BEOVR - Bus error overrun * 0b0..No bus error overrun * 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error. */ #define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK) /*! @} */ /*! @name FDR - Fault data register */ /*! @{ */ #define MCM_FDR_DATA_MASK (0xFFFFFFFFU) #define MCM_FDR_DATA_SHIFT (0U) /*! DATA - Fault data */ #define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group MCM_Register_Masks */ /* MCM - Peripheral instance base addresses */ /** Peripheral MCM base address */ #define MCM_BASE (0xE0080000u) /** Peripheral MCM base pointer */ #define MCM ((MCM_Type *)MCM_BASE) /** Array initializer of MCM peripheral base addresses */ #define MCM_BASE_ADDRS { MCM_BASE } /** Array initializer of MCM peripheral base pointers */ #define MCM_BASE_PTRS { MCM } /*! * @} */ /* end of group MCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_CSI2RX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer * @{ */ /** MIPI_CSI2RX - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[256]; __IO uint32_t CSI2RX_CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ __IO uint32_t CSI2RX_CFG_DISABLE_DATA_LANES; /**< Disable Data Lane Register, offset: 0x104 */ __I uint32_t CSI2RX_BIT_ERR; /**< ECC and CRC Error Status Register, offset: 0x108 */ __I uint32_t CSI2RX_IRQ_STATUS; /**< IRQ Status Register, offset: 0x10C */ __IO uint32_t CSI2RX_IRQ_MASK; /**< IRQ Mask Setting Regsiter, offset: 0x110 */ __I uint32_t CSI2RX_ULPS_STATUS; /**< ULPS Status Register, offset: 0x114 */ __I uint32_t CSI2RX_PPI_ERRSOT_HS; /**< ERRSot HS Status Register, offset: 0x118 */ __I uint32_t CSI2RX_PPI_ERRSOTSYNC_HS; /**< ErrSotSync HS Status Register, offset: 0x11C */ __I uint32_t CSI2RX_PPI_ERRESC; /**< ErrEsc Status Register, offset: 0x120 */ __I uint32_t CSI2RX_PPI_ERRSYNCESC; /**< ErrSyncEsc Status Register, offset: 0x124 */ __I uint32_t CSI2RX_PPI_ERRCONTROL; /**< ErrControl Status Register, offset: 0x128 */ __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_0; /**< Disable Payload 0 Register, offset: 0x12C */ __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_1; /**< Disable Payload 1 Register, offset: 0x130 */ uint8_t RESERVED_1[76]; __IO uint32_t CSI2RX_CFG_IGNORE_VC; /**< Ignore Virtual Channel Register, offset: 0x180 */ __IO uint32_t CSI2RX_CFG_VID_VC; /**< Virtual Channel value Register, offset: 0x184 */ __IO uint32_t CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL; /**< FIFO Send Level Configuration Register, offset: 0x188 */ __IO uint32_t CSI2RX_CFG_VID_VSYNC; /**< VSYNC Configuration Register, offset: 0x18C */ __IO uint32_t CSI2RX_CFG_VID_HSYNC_FP; /**< Start of HSYNC Delay control Register, offset: 0x190 */ __IO uint32_t CSI2RX_CFG_VID_HSYNC; /**< HSYNC Configuration Register, offset: 0x194 */ __IO uint32_t CSI2RX_CFG_VID_HSYNC_BP; /**< End of HSYNC Delay Control Register, offset: 0x198 */ } MIPI_CSI2RX_Type; /* ---------------------------------------------------------------------------- -- MIPI_CSI2RX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks * @{ */ /*! @name CSI2RX_CFG_NUM_LANES - Lane Configuration Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U) #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U) /*! CFG_NUM_LANES - Sets the number of active lanes that are to be used for receiving data. * 0b00..1 Lane * 0b01..2 Lane * 0b10..3 Lane * 0b11..4 Lane */ #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK) /*! @} */ /*! @name CSI2RX_CFG_DISABLE_DATA_LANES - Disable Data Lane Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK (0xFU) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT (0U) /*! CFG_DISABLE_DATA_LANES - Setting bits to a '1' value causes the DPHY Enable signal to deassert. * 0b0001..Data Lane 0 * 0b0010..Data Lane 1 * 0b0100..Data Lane 2 * 0b1000..Data Lane 3 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK) /*! @} */ /*! @name CSI2RX_BIT_ERR - ECC and CRC Error Status Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_MASK (0x3FFU) #define MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_SHIFT (0U) /*! BIT_ERR - BIT_ERR: CSI-2 RX Controller ECC and CRC error status. */ #define MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_SHIFT)) & MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_MASK) /*! @} */ /*! @name CSI2RX_IRQ_STATUS - IRQ Status Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK (0x1FFU) #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT (0U) /*! IRQ_STATUS - CSI2 RX IRQ status */ #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK) /*! @} */ /*! @name CSI2RX_IRQ_MASK - IRQ Mask Setting Regsiter */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_MASK (0x1FFU) #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT (0U) /*! IRQ_MASK - CSI2 RX IRQ Mask setting */ #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_MASK) /*! @} */ /*! @name CSI2RX_ULPS_STATUS - ULPS Status Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_MASK (0x3FFU) #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_SHIFT (0U) /*! STATUS - Status of RX DPHY ULPS state */ #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_MASK) /*! @} */ /*! @name CSI2RX_PPI_ERRSOT_HS - ERRSot HS Status Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK (0xFU) #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT (0U) /*! STATUS - CSI2 RX DPHY PPI ErrSotHS captured status from the DPHY. */ #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK) /*! @} */ /*! @name CSI2RX_PPI_ERRSOTSYNC_HS - ErrSotSync HS Status Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK (0xFU) #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT (0U) /*! STATUS - CSI2 RX DPHY PPI ErrSotSync_HS captured status from the DPHY. */ #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK) /*! @} */ /*! @name CSI2RX_PPI_ERRESC - ErrEsc Status Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_MASK (0xFU) #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_SHIFT (0U) /*! STATUS - CSI2 RX DPHY PPI ErrEsc captured status from the DPHY. */ #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_MASK) /*! @} */ /*! @name CSI2RX_PPI_ERRSYNCESC - ErrSyncEsc Status Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK (0xFU) #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT (0U) /*! STATUS - CSI2 RX DPHY PPI ErrSyncEsc captured status from the DPHY. */ #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK) /*! @} */ /*! @name CSI2RX_PPI_ERRCONTROL - ErrControl Status Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_MASK (0xFU) #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT (0U) /*! STATUS - CSI2 RX DPHY PPI ErrControl captured status from the DPHY. */ #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_MASK) /*! @} */ /*! @name CSI2RX_CFG_DISABLE_PAYLOAD_0 - Disable Payload 0 Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK (0x1U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT (0U) /*! DIS_PAYLOAD_NULL - Null */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK (0x2U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT (1U) /*! DIS_PAYLOAD_BLANK - Blank */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK (0x4U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT (2U) /*! DIS_PAYLOAD_EMBEDDED - Embedded */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK (0x400U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT (10U) /*! DIS_PAYLOAD_YUV420 - Legacy YUV 420 8 bit */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK (0x4000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT (14U) /*! DIS_PAYLOAD_YUV422_8BIT - YUV422 8 bit */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_MASK (0x8000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_SHIFT (15U) /*! DIS_PAYLOAD_YUV422_10BIT - YUV422 10 bit */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_10BIT_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK (0x10000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT (16U) /*! DIS_PAYLOAD_RGB444 - RGB444 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK (0x20000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT (17U) /*! DIS_PAYLOAD_RGB555 - RGB555 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK (0x40000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT (18U) /*! DIS_PAYLOAD_RGB565 - RGB565 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK (0x80000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT (19U) /*! DIS_PAYLOAD_RGB666 - RGB666 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK (0x100000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT (20U) /*! DIS_PAYLOAD_RGB888 - RGB888 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_MASK (0x1000000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_SHIFT (24U) /*! DIS_PAYLOAD_RAW6 - RAW6 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW6_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW7_MASK (0x2000000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW7_SHIFT (25U) /*! DIS_PAYLOAD_RAW7 - RAW7 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW7(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW7_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW7_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_MASK (0x4000000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_SHIFT (26U) /*! DIS_PAYLOAD_RAW8 - RAW8 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW8_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_MASK (0x8000000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_SHIFT (27U) /*! DIS_PAYLOAD_RAW10 - RAW10 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW10_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_MASK (0x10000000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_SHIFT (28U) /*! DIS_PAYLOAD_RAW12 - RAW12 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW12_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW14_MASK (0x20000000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW14_SHIFT (29U) /*! DIS_PAYLOAD_RAW14 - RAW14 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW14_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RAW14_MASK) /*! @} */ /*! @name CSI2RX_CFG_DISABLE_PAYLOAD_1 - Disable Payload 1 Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK (0x1U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT (0U) /*! DIS_PAYLOAD_UDEF_30 - User defined type 0x31 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK (0x2U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT (1U) /*! DIS_PAYLOAD_UDEF_31 - User defined type 0x32 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK (0x4U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT (2U) /*! DIS_PAYLOAD_UDEF_32 - User defined type 0x33 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK (0x8U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT (3U) /*! DIS_PAYLOAD_UDEF_33 - User defined type 0x34 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK (0x10U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT (4U) /*! DIS_PAYLOAD_UDEF_34 - User defined type 0x35 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK (0x20U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT (5U) /*! DIS_PAYLOAD_UDEF_35 - User defined type 0x35 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK (0x40U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT (6U) /*! DIS_PAYLOAD_UDEF_36 - User defined type 0x36 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK (0x80U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT (7U) /*! DIS_PAYLOAD_UDEF_37 - User defined type 0x37 */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK (0x10000U) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT (16U) /*! DIS_PAYLOAD_UNSUPPORTED - Unsupported Data Types */ #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK) /*! @} */ /*! @name CSI2RX_CFG_IGNORE_VC - Ignore Virtual Channel Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK (0x1U) #define MIPI_CSI2RX_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT (0U) #define MIPI_CSI2RX_CSI2RX_CFG_IGNORE_VC_IGNORE_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK) /*! @} */ /*! @name CSI2RX_CFG_VID_VC - Virtual Channel value Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_VC_VID_VC_MASK (0x3U) #define MIPI_CSI2RX_CSI2RX_CFG_VID_VC_VID_VC_SHIFT (0U) #define MIPI_CSI2RX_CSI2RX_CFG_VID_VC_VID_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_VC_VID_VC_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_VC_VID_VC_MASK) /*! @} */ /*! @name CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL - FIFO Send Level Configuration Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK (0xFFFFU) #define MIPI_CSI2RX_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT (0U) /*! SEND_LEVEL - FIFO Send Level field */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK) /*! @} */ /*! @name CSI2RX_CFG_VID_VSYNC - VSYNC Configuration Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK (0xFFU) #define MIPI_CSI2RX_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT (0U) /*! WIDTH - Width of VSYNC */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_VSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK) /*! @} */ /*! @name CSI2RX_CFG_VID_HSYNC_FP - Start of HSYNC Delay control Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK (0xFFU) #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT (0U) /*! DELAY_CTL - Delay control for beginning of HSYNC pulse */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK) /*! @} */ /*! @name CSI2RX_CFG_VID_HSYNC - HSYNC Configuration Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK (0xFFU) #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT (0U) /*! WIDTH - Width of HSYNC */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK) /*! @} */ /*! @name CSI2RX_CFG_VID_HSYNC_BP - End of HSYNC Delay Control Register */ /*! @{ */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK (0xFFU) #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT (0U) /*! DELAY_CTL - Delay Control for end of HSYNC pulse */ #define MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_CSI2RX_Register_Masks */ /* MIPI_CSI2RX - Peripheral instance base addresses */ /** Peripheral MIPI_CSI__MIPI_CSI2RX base address */ #define MIPI_CSI__MIPI_CSI2RX_BASE (0x58227000u) /** Peripheral MIPI_CSI__MIPI_CSI2RX base pointer */ #define MIPI_CSI__MIPI_CSI2RX ((MIPI_CSI2RX_Type *)MIPI_CSI__MIPI_CSI2RX_BASE) /** Array initializer of MIPI_CSI2RX peripheral base addresses */ #define MIPI_CSI2RX_BASE_ADDRS { MIPI_CSI__MIPI_CSI2RX_BASE } /** Array initializer of MIPI_CSI2RX peripheral base pointers */ #define MIPI_CSI2RX_BASE_PTRS { MIPI_CSI__MIPI_CSI2RX } /* Backward compatibility */ #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes(x) MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT #define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes(x) MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) #define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_MASK #define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR_SHIFT #define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err(x) MIPI_CSI2RX_CSI2RX_BIT_ERR_BIT_ERR(x) #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT #define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status(x) MIPI_CSI2RX_CSI2RX_IRQ_STATUS_IRQ_STATUS(x) #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_MASK #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask(x) MIPI_CSI2RX_CSI2RX_IRQ_MASK_IRQ_MASK(x) #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_MASK #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS_SHIFT #define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status(x) MIPI_CSI2RX_CSI2RX_ULPS_STATUS_STATUS(x) #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs(x) MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_STATUS(x) #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT #define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs(x) MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x) #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_MASK #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS_SHIFT #define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc(x) MIPI_CSI2RX_CSI2RX_PPI_ERRESC_STATUS(x) #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT #define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc(x) MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_STATUS(x) #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_MASK #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT #define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol(x) MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_STATUS(x) /*! * @} */ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_CSI_CSR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_CSI_CSR_Peripheral_Access_Layer MIPI_CSI_CSR Peripheral Access Layer * @{ */ /** MIPI_CSI_CSR - Register Layout Typedef */ typedef struct { __IO uint32_t PLM_CTRL; /**< Pixel Link Master (PLM) Control, offset: 0x0 */ __IO uint32_t PHY_CTRL; /**< PHY_CTRL are outputs from CSR to the PHY or Controller., offset: 0x4 */ __I uint32_t PHY_STATUS; /**< , offset: 0x8 */ uint8_t RESERVED_0[4]; __I uint32_t PHY_TEST_STATUS; /**< , offset: 0x10 */ __I uint32_t PHY_TEST_STATUS_D0; /**< , offset: 0x14 */ __I uint32_t PHY_TEST_STATUS_D1; /**< , offset: 0x18 */ __I uint32_t PHY_TEST_STATUS_D2; /**< , offset: 0x1C */ __I uint32_t PHY_TEST_STATUS_D3; /**< , offset: 0x20 */ uint8_t RESERVED_1[12]; __IO uint32_t VC_INTERLACED; /**< , offset: 0x30 */ uint8_t RESERVED_2[4]; __IO uint32_t DATA_TYPE_DISABLE_BF; /**< , offset: 0x38 */ uint8_t RESERVED_3[4]; __IO uint32_t YUV420_FIRST_LINE_DATA_TYPE; /**< , offset: 0x40 */ __IO uint32_t CONTROLLER_CLOCK_RESET_CONTROL; /**< , offset: 0x44 */ __IO uint32_t STREAM_FENCING_CONTROL; /**< Stream Fencing Control (RW - to Pixel Reformatter), offset: 0x48 */ __I uint32_t STREAM_FENCING_STATUS; /**< Stream Fencing Status (RO - from Pixel Reformatter), offset: 0x4C */ } MIPI_CSI_CSR_Type; /* ---------------------------------------------------------------------------- -- MIPI_CSI_CSR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_CSI_CSR_Register_Masks MIPI_CSI_CSR Register Masks * @{ */ /*! @name PLM_CTRL - Pixel Link Master (PLM) Control */ /*! @{ */ #define MIPI_CSI_CSR_PLM_CTRL_ENABLE_MASK (0x1U) #define MIPI_CSI_CSR_PLM_CTRL_ENABLE_SHIFT (0U) /*! ENABLE - Enable - for pixel link */ #define MIPI_CSI_CSR_PLM_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_ENABLE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_ENABLE_MASK) #define MIPI_CSI_CSR_PLM_CTRL_ADDR_MASK (0x6U) #define MIPI_CSI_CSR_PLM_CTRL_ADDR_SHIFT (1U) /*! ADDR - For selecting the destination module that receives the data. Can be defaulted to 0. */ #define MIPI_CSI_CSR_PLM_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_ADDR_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_ADDR_MASK) #define MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_MASK (0x200U) #define MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_SHIFT (9U) /*! VSYNC_OVERIDE - Used to force the Pixel Link Master VSYNC input to be active (MUXed with the * functional VSync before entering the PL, e.g. in HVSync Generation module) */ #define MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERIDE_MASK) #define MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_MASK (0x400U) #define MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_SHIFT (10U) /*! HSYNC_OVERIDE - Used to force the Pixel Link Master HSYNC input to be active (MUXed with the * functional HSync before entering the PL, e.g. in HVSync Generation module) */ #define MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERIDE_MASK) #define MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_MASK (0x800U) #define MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_SHIFT (11U) /*! VALID_OVERRIDE - Used to drive valid on the Pixel Link (MUXed with the functional valid before * entering the PL, e.g. in HVSync Generation module) */ #define MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_MASK) #define MIPI_CSI_CSR_PLM_CTRL_POLARITY_MASK (0x1000U) #define MIPI_CSI_CSR_PLM_CTRL_POLARITY_SHIFT (12U) /*! POLARITY - POLARITY * 0b1..HSYNC and VSYNC signals should be active high * 0b0..HSYNC and VSYNC signals should be active low. Also a reset value (active low). */ #define MIPI_CSI_CSR_PLM_CTRL_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PLM_CTRL_POLARITY_SHIFT)) & MIPI_CSI_CSR_PLM_CTRL_POLARITY_MASK) /*! @} */ /*! @name PHY_CTRL - PHY_CTRL are outputs from CSR to the PHY or Controller. */ /*! @{ */ #define MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_MASK (0x1U) #define MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_SHIFT (0U) /*! RX_ENABLE - RX_ENABLE */ #define MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_MASK) #define MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_MASK (0x2U) #define MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_SHIFT (1U) /*! AUTO_PD_EN - AUTO_PD_EN */ #define MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_MASK) #define MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_MASK (0x4U) #define MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_SHIFT (2U) /*! DDRCLK_EN - DDRCLK_EN */ #define MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_MASK) #define MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_MASK (0x8U) #define MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_SHIFT (3U) /*! CONT_CLK_MODE - CONT_CLK_MODE */ #define MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_MASK) #define MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_MASK (0x3F0U) #define MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_SHIFT (4U) /*! S_PRG_RXHS_SETTLE - S_PRG_RXHS_SETTLE[5:0] */ #define MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE_MASK) #define MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_MASK (0x200000U) #define MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_SHIFT (21U) /*! RTERM_SEL - RTERM_SEL */ #define MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_MASK) #define MIPI_CSI_CSR_PHY_CTRL_PD_MASK (0x400000U) #define MIPI_CSI_CSR_PHY_CTRL_PD_SHIFT (22U) /*! PD - PD */ #define MIPI_CSI_CSR_PHY_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_CTRL_PD_SHIFT)) & MIPI_CSI_CSR_PHY_CTRL_PD_MASK) /*! @} */ /*! @name PHY_STATUS - */ /*! @{ */ #define MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_MASK (0x1U) #define MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_SHIFT (0U) /*! LANES_STOPPED - LANES_STOPPED (csi_controller.ulps_active[4:0] = 5'b0) */ #define MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_SHIFT)) & MIPI_CSI_CSR_PHY_STATUS_LANES_STOPPED_MASK) /*! @} */ /*! @name PHY_TEST_STATUS - */ /*! @{ */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_DC_TEST_OUT_MASK (0x3FFU) #define MIPI_CSI_CSR_PHY_TEST_STATUS_DC_TEST_OUT_SHIFT (0U) /*! DC_TEST_OUT - DC_TEST_OUT */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_DC_TEST_OUT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_DC_TEST_OUT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_DC_TEST_OUT_MASK) /*! @} */ /*! @name PHY_TEST_STATUS_D0 - */ /*! @{ */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_ERR_CNT_MASK (0x3FFU) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_ERR_CNT_SHIFT (0U) /*! LB_D0_ERR_CNT - LB_D0_ERR_CNT[9:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_ERR_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_ERR_CNT_MASK) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_BYTE_CNT_MASK (0xFFC00U) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_BYTE_CNT_SHIFT (10U) /*! LB_D0_BYTE_CNT - LB_D0_BYTE_CNT[9:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_BYTE_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D0_LB_D0_BYTE_CNT_MASK) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_D0_LB_PASS_MASK (0x300000U) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_D0_LB_PASS_SHIFT (20U) /*! D0_LB_PASS - D0_LB_PASS[1:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D0_D0_LB_PASS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D0_D0_LB_PASS_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D0_D0_LB_PASS_MASK) /*! @} */ /*! @name PHY_TEST_STATUS_D1 - */ /*! @{ */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_ERR_CNT_MASK (0x3FFU) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_ERR_CNT_SHIFT (0U) /*! LB_D1_ERR_CNT - LB_D1_ERR_CNT[9:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_ERR_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_ERR_CNT_MASK) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_BYTE_CNT_MASK (0xFFC00U) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_BYTE_CNT_SHIFT (10U) /*! LB_D1_BYTE_CNT - LB_D1_BYTE_CNT[9:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_BYTE_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D1_LB_D1_BYTE_CNT_MASK) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_D1_LB_PASS_MASK (0x300000U) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_D1_LB_PASS_SHIFT (20U) /*! D1_LB_PASS - D1_LB_PASS[1:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D1_D1_LB_PASS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D1_D1_LB_PASS_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D1_D1_LB_PASS_MASK) /*! @} */ /*! @name PHY_TEST_STATUS_D2 - */ /*! @{ */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_ERR_CNT_MASK (0x3FFU) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_ERR_CNT_SHIFT (0U) /*! LB_D2_ERR_CNT - LB_D2_ERR_CNT[9:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_ERR_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_ERR_CNT_MASK) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_BYTE_CNT_MASK (0xFFC00U) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_BYTE_CNT_SHIFT (10U) /*! LB_D2_BYTE_CNT - LB_D2_BYTE_CNT[9:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_BYTE_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D2_LB_D2_BYTE_CNT_MASK) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_D2_LB_PASS_MASK (0x300000U) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_D2_LB_PASS_SHIFT (20U) /*! D2_LB_PASS - D2_LB_PASS[1:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D2_D2_LB_PASS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D2_D2_LB_PASS_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D2_D2_LB_PASS_MASK) /*! @} */ /*! @name PHY_TEST_STATUS_D3 - */ /*! @{ */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_ERR_CNT_MASK (0x3FFU) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_ERR_CNT_SHIFT (0U) /*! LB_D3_ERR_CNT - LB_D3_ERR_CNT[9:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_ERR_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_ERR_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_ERR_CNT_MASK) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_BYTE_CNT_MASK (0xFFC00U) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_BYTE_CNT_SHIFT (10U) /*! LB_D3_BYTE_CNT - LB_D3_BYTE_CNT[9:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_BYTE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_BYTE_CNT_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D3_LB_D3_BYTE_CNT_MASK) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_D3_LB_PASS_MASK (0x300000U) #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_D3_LB_PASS_SHIFT (20U) /*! D3_LB_PASS - D3_LB_PASS[1:0] */ #define MIPI_CSI_CSR_PHY_TEST_STATUS_D3_D3_LB_PASS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_PHY_TEST_STATUS_D3_D3_LB_PASS_SHIFT)) & MIPI_CSI_CSR_PHY_TEST_STATUS_D3_D3_LB_PASS_MASK) /*! @} */ /*! @name VC_INTERLACED - */ /*! @{ */ #define MIPI_CSI_CSR_VC_INTERLACED_VC0_MASK (0x1U) #define MIPI_CSI_CSR_VC_INTERLACED_VC0_SHIFT (0U) /*! VC0 * 0b1..VC0 is interlaced * 0b0..Default */ #define MIPI_CSI_CSR_VC_INTERLACED_VC0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC0_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC0_MASK) #define MIPI_CSI_CSR_VC_INTERLACED_VC1_MASK (0x2U) #define MIPI_CSI_CSR_VC_INTERLACED_VC1_SHIFT (1U) /*! VC1 * 0b1..VC1 is interlaced * 0b0..Default */ #define MIPI_CSI_CSR_VC_INTERLACED_VC1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC1_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC1_MASK) #define MIPI_CSI_CSR_VC_INTERLACED_VC2_MASK (0x4U) #define MIPI_CSI_CSR_VC_INTERLACED_VC2_SHIFT (2U) /*! VC2 * 0b1..VC2 is interlaced * 0b0..Default */ #define MIPI_CSI_CSR_VC_INTERLACED_VC2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC2_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC2_MASK) #define MIPI_CSI_CSR_VC_INTERLACED_VC3_MASK (0x8U) #define MIPI_CSI_CSR_VC_INTERLACED_VC3_SHIFT (3U) /*! VC3 * 0b1..VC3 is interlaced * 0b0..Default */ #define MIPI_CSI_CSR_VC_INTERLACED_VC3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_VC_INTERLACED_VC3_SHIFT)) & MIPI_CSI_CSR_VC_INTERLACED_VC3_MASK) /*! @} */ /*! @name DATA_TYPE_DISABLE_BF - */ /*! @{ */ #define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_MASK (0xFFFFFFU) #define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_SHIFT (0U) /*! DATA_TYPE_DISABLE - Data Type Disable */ #define MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_SHIFT)) & MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_MASK) /*! @} */ /*! @name YUV420_FIRST_LINE_DATA_TYPE - */ /*! @{ */ #define MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_MASK (0x1U) #define MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_SHIFT (0U) /*! YUV420_FIRST_LINE_DATA_TYPE - YUV420_FIRST_LINE_DATA_TYPE * 0b0..Odd (reset value) * 0b1..Even */ #define MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_SHIFT)) & MIPI_CSI_CSR_YUV420_FIRST_LINE_DATA_TYPE_YUV420_FIRST_LINE_DATA_TYPE_MASK) /*! @} */ /*! @name CONTROLLER_CLOCK_RESET_CONTROL - */ /*! @{ */ #define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_MASK (0x3U) #define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_SHIFT (0U) /*! CONTROLLER_CLOCK_RESET_CONTROL - CONTROLLER_CLOCK_RESET_CONTROL * 0b00..SW_RESETN (reset value is 0) * 0b01..CTL_CLK_OFF (connect to LPCG) (reset value is 1) */ #define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_SHIFT)) & MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL_MASK) /*! @} */ /*! @name STREAM_FENCING_CONTROL - Stream Fencing Control (RW - to Pixel Reformatter) */ /*! @{ */ #define MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_MASK (0xFU) #define MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_SHIFT (0U) /*! STREAM_FENCING_CONTROL * 0b0000..Fence VC0 * 0b0001..Fence VC1 * 0b0010..Fence VC2 * 0b0011..Fence VC3 */ #define MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_SHIFT)) & MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_MASK) /*! @} */ /*! @name STREAM_FENCING_STATUS - Stream Fencing Status (RO - from Pixel Reformatter) */ /*! @{ */ #define MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_MASK (0xFU) #define MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_SHIFT (0U) /*! STREAM_FENCING_STATUS * 0b0000..VC0 is fenced * 0b0001..VC1 is fenced * 0b0010..VC2 is fenced * 0b0011..VC3 is fenced */ #define MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_SHIFT)) & MIPI_CSI_CSR_STREAM_FENCING_STATUS_STREAM_FENCING_STATUS_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_CSI_CSR_Register_Masks */ /* MIPI_CSI_CSR - Peripheral instance base addresses */ /** Peripheral MIPI_CSI_CSR base address */ #define MIPI_CSI_CSR_BASE (0x58221000u) /** Peripheral MIPI_CSI_CSR base pointer */ #define MIPI_CSI_CSR ((MIPI_CSI_CSR_Type *)MIPI_CSI_CSR_BASE) /** Array initializer of MIPI_CSI_CSR peripheral base addresses */ #define MIPI_CSI_CSR_BASE_ADDRS { MIPI_CSI_CSR_BASE } /** Array initializer of MIPI_CSI_CSR peripheral base pointers */ #define MIPI_CSI_CSR_BASE_PTRS { MIPI_CSI_CSR } /*! * @} */ /* end of group MIPI_CSI_CSR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_CSI_LPCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_CSI_LPCG_Peripheral_Access_Layer MIPI_CSI_LPCG Peripheral Access Layer * @{ */ /** MIPI_CSI_LPCG - Register Layout Typedef */ typedef struct { __IO uint32_t LPCG_MIPI_CSI_LPCG_0; /**< na, offset: 0x0 */ __IO uint32_t LPCG_MIPI_CSI_LPCG_4; /**< na, offset: 0x4 */ __IO uint32_t LPCG_MIPI_CSI_LPCG_8; /**< na, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t LPCG_MIPI_CSI_LPCG_16; /**< na, offset: 0x10 */ __IO uint32_t LPCG_MIPI_CSI_LPCG_20; /**< na, offset: 0x14 */ __IO uint32_t LPCG_MIPI_CSI_LPCG_24; /**< na, offset: 0x18 */ __IO uint32_t LPCG_MIPI_CSI_LPCG_28; /**< na, offset: 0x1C */ } MIPI_CSI_LPCG_Type; /* ---------------------------------------------------------------------------- -- MIPI_CSI_LPCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_CSI_LPCG_Register_Masks MIPI_CSI_LPCG Register Masks * @{ */ /*! @name LPCG_MIPI_CSI_LPCG_0 - na */ /*! @{ */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_MASK (0x1FFFFU) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_SHIFT (0U) /*! LPCG_mipi_csi_lpcg_0_reserved_0_16 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_MASK (0x20000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_SHIFT (17U) /*! lis_ipg_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_MASK (0x40000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_SHIFT (18U) /*! LPCG_mipi_csi_lpcg_0_reserved_18_18 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_MASK (0x80000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_SHIFT (19U) /*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_MASK (0xFFF00000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_SHIFT (20U) /*! LPCG_mipi_csi_lpcg_0_reserved_20_31 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_MIPI_CSI_LPCG_4 - na */ /*! @{ */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_MASK (0x1FFFFU) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_SHIFT (0U) /*! LPCG_mipi_csi_lpcg_4_reserved_0_16 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_MASK (0x20000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_SHIFT (17U) /*! mipi_csi_regs_apb_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_MASK (0x40000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_SHIFT (18U) /*! LPCG_mipi_csi_lpcg_4_reserved_18_18 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_MASK (0x80000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_SHIFT (19U) /*! mipi_csi_regs_apb_clk_STOP - show clock root status, 1 means clock stopped */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_MASK (0xFFF00000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_SHIFT (20U) /*! LPCG_mipi_csi_lpcg_4_reserved_20_31 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_MIPI_CSI_LPCG_8 - na */ /*! @{ */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_MASK (0xFFFFU) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_SHIFT (0U) /*! LPCG_mipi_csi_lpcg_8_reserved_0_15 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_MASK (0x10000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT (16U) /*! gpio_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_MASK (0x20000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT (17U) /*! gpio_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_MASK (0x40000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_SHIFT (18U) /*! LPCG_mipi_csi_lpcg_8_reserved_18_18 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_MASK (0x80000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT (19U) /*! gpio_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_MASK (0xFFF00000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_SHIFT (20U) /*! LPCG_mipi_csi_lpcg_8_reserved_20_31 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_MIPI_CSI_LPCG_16 - na */ /*! @{ */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_MASK (0x1U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_SHIFT (0U) /*! LPCG_mipi_csi_lpcg_16_reserved_0_0 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U) /*! pwm_ipg_clk_highfreq_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_MASK (0x4U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_SHIFT (2U) /*! LPCG_mipi_csi_lpcg_16_reserved_2_2 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_MASK (0x8U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_SHIFT (3U) /*! pwm_ipg_clk_highfreq_STOP - show clock root status, 1 means clock stopped */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_MASK (0xFFF0U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_SHIFT (4U) /*! LPCG_mipi_csi_lpcg_16_reserved_4_15 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK (0x10000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT (16U) /*! pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U) /*! pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_MASK (0x40000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_SHIFT (18U) /*! LPCG_mipi_csi_lpcg_16_reserved_18_18 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U) /*! pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_MASK (0xFFF00000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_SHIFT (20U) /*! LPCG_mipi_csi_lpcg_16_reserved_20_31 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_MIPI_CSI_LPCG_20 - na */ /*! @{ */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_MASK (0x1U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_SHIFT (0U) /*! lpi2c_lpi2c_div_clk_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_MASK (0x2U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_SHIFT (1U) /*! lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_MASK (0x4U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_SHIFT (2U) /*! LPCG_mipi_csi_lpcg_20_reserved_2_2 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_MASK (0x8U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_SHIFT (3U) /*! lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_MASK (0xFFF0U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_SHIFT (4U) /*! LPCG_mipi_csi_lpcg_20_reserved_4_15 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_MASK (0x10000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_SHIFT (16U) /*! lpi2c_ipg_clk_s_HWEN - Hardware Enable * 0b0..Ignore all HW signal (if swen!=0 it's always on) * 0b1..Enable HW automatic gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_MASK (0x20000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_SHIFT (17U) /*! lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_MASK (0x40000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_SHIFT (18U) /*! LPCG_mipi_csi_lpcg_20_reserved_18_18 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_MASK (0x80000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_SHIFT (19U) /*! lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP - show clock root status, 1 means clock stopped */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_MASK (0xFFF00000U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_SHIFT (20U) /*! LPCG_mipi_csi_lpcg_20_reserved_20_31 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_MASK) /*! @} */ /*! @name LPCG_MIPI_CSI_LPCG_24 - na */ /*! @{ */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_MASK (0x1U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_SHIFT (0U) /*! LPCG_mipi_csi_lpcg_24_reserved_0_0 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_MASK (0x2U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_SHIFT (1U) /*! csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_MASK (0x4U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_SHIFT (2U) /*! LPCG_mipi_csi_lpcg_24_reserved_2_2 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_MASK (0x8U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_SHIFT (3U) /*! csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP - show clock root status, 1 means clock stopped */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_MASK (0xFFFFFFF0U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_SHIFT (4U) /*! LPCG_mipi_csi_lpcg_24_reserved_4_31 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_MASK) /*! @} */ /*! @name LPCG_MIPI_CSI_LPCG_28 - na */ /*! @{ */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_MASK (0x1U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_SHIFT (0U) /*! LPCG_mipi_csi_lpcg_28_reserved_0_0 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_MASK (0x2U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_SHIFT (1U) /*! csi2_rx_top_clk_esc_SWEN - Software Enable * 0b0..Disable SW clock regardless of HWEN * 0b1..Enable SW clock gating */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_MASK (0x4U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_SHIFT (2U) /*! LPCG_mipi_csi_lpcg_28_reserved_2_2 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_MASK (0x8U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_SHIFT (3U) /*! csi2_rx_top_clk_esc_STOP - show clock root status, 1 means clock stopped */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_MASK) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U) #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_SHIFT (4U) /*! LPCG_mipi_csi_lpcg_28_reserved_4_31 - reserved */ #define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_CSI_LPCG_Register_Masks */ /* MIPI_CSI_LPCG - Peripheral instance base addresses */ /** Peripheral MIPI_CSI__LPCG_CLK base address */ #define MIPI_CSI__LPCG_CLK_BASE (0x58223000u) /** Peripheral MIPI_CSI__LPCG_CLK base pointer */ #define MIPI_CSI__LPCG_CLK ((MIPI_CSI_LPCG_Type *)MIPI_CSI__LPCG_CLK_BASE) /** Array initializer of MIPI_CSI_LPCG peripheral base addresses */ #define MIPI_CSI_LPCG_BASE_ADDRS { MIPI_CSI__LPCG_CLK_BASE } /** Array initializer of MIPI_CSI_LPCG peripheral base pointers */ #define MIPI_CSI_LPCG_BASE_PTRS { MIPI_CSI__LPCG_CLK } /*! * @} */ /* end of group MIPI_CSI_LPCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_DSI_HOST Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer * @{ */ /** MIPI_DSI_HOST - Register Layout Typedef */ typedef struct { __IO uint32_t DSI_HOST_CFG_NUM_LANES; /**< , offset: 0x0 */ __IO uint32_t DSI_HOST_CFG_NONCONTINUOUS_CLK; /**< , offset: 0x4 */ __IO uint32_t DSI_HOST_CFG_T_PRE; /**< , offset: 0x8 */ __IO uint32_t DSI_HOST_CFG_T_POST; /**< , offset: 0xC */ __IO uint32_t DSI_HOST_CFG_TX_GAP; /**< , offset: 0x10 */ __IO uint32_t DSI_HOST_CFG_AUTOINSERT_EOTP; /**< , offset: 0x14 */ __IO uint32_t DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP; /**< , offset: 0x18 */ __IO uint32_t DSI_HOST_CFG_HTX_TO_COUNT; /**< , offset: 0x1C */ __IO uint32_t DSI_HOST_CFG_LRX_H_TO_COUNT; /**< , offset: 0x20 */ __IO uint32_t DSI_HOST_CFG_BTA_H_TO_COUNT; /**< , offset: 0x24 */ __IO uint32_t DSI_HOST_CFG_TWAKEUP; /**< , offset: 0x28 */ __I uint32_t DSI_HOST_CFG_STATUS_OUT; /**< , offset: 0x2C */ __I uint32_t DSI_HOST_RX_ERROR_STATUS; /**< , offset: 0x30 */ uint8_t RESERVED_0[460]; __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE; /**< , offset: 0x200 */ __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x204 */ __IO uint32_t DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING; /**< , offset: 0x208 */ __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FORMAT; /**< , offset: 0x20C */ __IO uint32_t DSI_HOST_CFG_DPI_VSYNC_POLARITY; /**< , offset: 0x210 */ __IO uint32_t DSI_HOST_CFG_DPI_HSYNC_POLARITY; /**< , offset: 0x214 */ __IO uint32_t DSI_HOST_CFG_DPI_VIDEO_MODE; /**< , offset: 0x218 */ __IO uint32_t DSI_HOST_CFG_DPI_HFP; /**< , offset: 0x21C */ __IO uint32_t DSI_HOST_CFG_DPI_HBP; /**< , offset: 0x220 */ __IO uint32_t DSI_HOST_CFG_DPI_HSA; /**< , offset: 0x224 */ __IO uint32_t DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS; /**< , offset: 0x228 */ __IO uint32_t DSI_HOST_CFG_DPI_VBP; /**< , offset: 0x22C */ __IO uint32_t DSI_HOST_CFG_DPI_VFP; /**< , offset: 0x230 */ __IO uint32_t DSI_HOST_CFG_DPI_BLLP_MODE; /**< , offset: 0x234 */ __IO uint32_t DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP; /**< , offset: 0x238 */ __IO uint32_t DSI_HOST_CFG_DPI_VACTIVE; /**< , offset: 0x23C */ __IO uint32_t DSI_HOST_CFG_DPI_VC; /**< , offset: 0x240 */ uint8_t RESERVED_1[60]; __IO uint32_t DSI_HOST_TX_PAYLOAD; /**< , offset: 0x280 */ __IO uint32_t DSI_HOST_PKT_CONTROL; /**< , offset: 0x284 */ __IO uint32_t DSI_HOST_SEND_PACKET; /**< , offset: 0x288 */ __I uint32_t DSI_HOST_PKT_STATUS; /**< , offset: 0x28C */ __I uint32_t DSI_HOST_PKT_FIFO_WR_LEVEL; /**< , offset: 0x290 */ __I uint32_t DSI_HOST_PKT_FIFO_RD_LEVEL; /**< , offset: 0x294 */ __I uint32_t DSI_HOST_PKT_RX_PAYLOAD; /**< , offset: 0x298 */ __I uint32_t DSI_HOST_PKT_RX_PKT_HEADER; /**< , offset: 0x29C */ __I uint32_t DSI_HOST_IRQ_STATUS; /**< , offset: 0x2A0 */ __I uint32_t DSI_HOST_IRQ_STATUS2; /**< , offset: 0x2A4 */ __IO uint32_t DSI_HOST_IRQ_MASK; /**< , offset: 0x2A8 */ __IO uint32_t DSI_HOST_IRQ_MASK2; /**< , offset: 0x2AC */ uint8_t RESERVED_2[80]; __IO uint32_t DPHY_PD_TX; /**< , offset: 0x300 */ __IO uint32_t DPHY_M_PRG_HS_PREPARE; /**< , offset: 0x304 */ __IO uint32_t DPHY_MC_PRG_HS_PREPARE; /**< , offset: 0x308 */ __IO uint32_t DPHY_M_PRG_HS_ZERO; /**< , offset: 0x30C */ __IO uint32_t DPHY_MC_PRG_HS_ZERO; /**< , offset: 0x310 */ __IO uint32_t DPHY_M_PRG_HS_TRAIL; /**< , offset: 0x314 */ __IO uint32_t DPHY_MC_PRG_HS_TRAIL; /**< , offset: 0x318 */ __IO uint32_t DPHY_PD_PLL; /**< , offset: 0x31C */ __IO uint32_t DPHY_TST; /**< , offset: 0x320 */ __IO uint32_t DPHY_CN; /**< , offset: 0x324 */ __IO uint32_t DPHY_CM; /**< , offset: 0x328 */ __IO uint32_t DPHY_CO; /**< , offset: 0x32C */ __I uint32_t DPHY_LOCK; /**< , offset: 0x330 */ __IO uint32_t DPHY_LOCK_BYP; /**< , offset: 0x334 */ __IO uint32_t DPHY_TX_RCAL; /**< , offset: 0x338 */ __IO uint32_t DPHY_AUTO_PD_EN; /**< , offset: 0x33C */ __IO uint32_t DPHY_RXLPRP; /**< , offset: 0x340 */ __IO uint32_t DPHY_RXCDRP; /**< , offset: 0x344 */ } MIPI_DSI_HOST_Type; /* ---------------------------------------------------------------------------- -- MIPI_DSI_HOST Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks * @{ */ /*! @name DSI_HOST_CFG_NUM_LANES - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK (0x3U) #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT (0U) /*! dsi_host_cfg_num_lanes - Sets the number of active lanes that are to be used for transmitting data. * 0b00..1 lane * 0b01..2 lanes * 0b10..3 lanes * 0b11..4 lanes */ #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_MASK (0xFFFFFFFCU) #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_SHIFT (2U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_NONCONTINUOUS_CLK - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT (0U) /*! dsi_host_cfg_noncontinuous_clk - Sets the Host Controller into non-continuous MIPI clock mode. * When in non-continuous clock mode, the high speed clock will transistion into low power mode * between transmissions. * 0b0..Continuous high speed clock * 0b1..Non-Continuous high speed clock */ #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_T_PRE - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK (0xFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT (0U) /*! dsi_host_cfg_t_pre - Sets the number of byte clock periods ('clk_byte' input) that the * controller will wait after enabling the clock lane for HS operation before enabling the data lanes for * HS operation. This setting represents the TCLK-PRE DPHY timing parameter. The minimum value * for this port is 1. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_MASK (0xFFFFFF00U) #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_SHIFT (8U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_T_POST - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK (0xFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT (0U) /*! dsi_host_cfg_t_post - Sets the number of byte clock periods ('clk_byte' input) to wait before * putting the clock lane into LP mode after the data lanes have been detected to be in Stop State. * This setting represents the DPHY timing parameters TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE * requirement for the clock lane before the data lane is allowed to change from LP11 to start a * high speed transmission. The minimum value for this port is 1. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_MASK (0xFFFFFF00U) #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_SHIFT (8U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_TX_GAP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK (0xFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT (0U) /*! dsi_host_cfg_tx_gap - Sets the number of byte clock periods ('clk_byte' input) that the * controller will wait after the clock lane has been put into LP mode before enabling the clock lane for * HS mode again. This setting represents the THS-EXIT DPHY timing parameter. The minimum value * for this port is 1. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_MASK (0xFFFFFF00U) #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_SHIFT (8U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_AUTOINSERT_EOTP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT (0U) /*! dsi_host_cfg_autoinsert_eotp - Enables the Host Controller to automatically insert an EoTp short * packet when switching from HS to LP mode. 1'b0 - EoTp is not automatically inserted 1'b1 - * EoTp is automatically inserted */ #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK (0xFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT (0U) /*! dsi_host_cfg_extra_cmds_after_eotp - Configures the DSI Host Controller to send extra End Of * Transmission Packets after the end of a packet. The value is the number of extra EOTP packets * sent. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_MASK (0xFFFFFF00U) #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_SHIFT (8U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_HTX_TO_COUNT - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK (0xFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT (0U) /*! dsi_host_cfg_htx_to_count - Sets the value of the DSI Host High Speed TX timeout count in * clk_byte clock periods that once reached will initiate a timeout error and follow the recovery * procedure documented in the DSI specification. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_MASK (0xFF000000U) #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_SHIFT (24U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_LRX_H_TO_COUNT - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK (0xFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT (0U) /*! dsi_host_cfg_lrx_h_to_count - Sets the value of the DSI Host low power RX timeout count in * clk_byte clock periods that once reached will initiate a timeout error and follow the recovery * procedure documented in the DSI specification. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_MASK (0xFF000000U) #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_SHIFT (24U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_BTA_H_TO_COUNT - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK (0xFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT (0U) /*! dsi_host_cfg_bta_h_to_count - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in * clk_byte clock periods that once reached will initiate a timeout error. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_MASK (0xFF000000U) #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_SHIFT (24U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_TWAKEUP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK (0x7FFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT (0U) /*! dsi_host_cfg_twakeup - DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods * to keep a clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a * minimum of 1ms in Mark-1 state after leaving ULPS. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_MASK (0xFFF80000U) #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_SHIFT (19U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_STATUS_OUT - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK (0xFFFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT (0U) /*! dsi_host_cfg_status_out - Status Register */ #define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK) /*! @} */ /*! @name DSI_HOST_RX_ERROR_STATUS - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK (0x7FFU) #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT (0U) /*! dsi_host_rx_error_status - Status Register for Host receive error detection, ECC errors, CRC errors and for timeout indicators. * 0b00000000000..ECC single bit error detected * 0b00000000001..ECC multi bit error detected * 0b00000000010-0b00000000110..Errored bit position for single bit ECC error * 0b00000000111..CRC error detected * 0b00000001000..High Speed forward TX timeout detected * 0b00000001001..Reverse Low power data receive timeout detected * 0b00000001010..BTA timeout detected */ #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK) #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_MASK (0xFFFFF800U) #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_SHIFT (11U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK (0xFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT (0U) /*! dsi_host_cfg_dpi_pixel_payload_size - Maximum number of pixels that should be sent as one DSI * packet. Recommended to be evenly divisible by the line size (in pixels). */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_MASK (0xFFFF0000U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT (16U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK (0xFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT (0U) /*! dsi_host_cfg_dpi_pixel_fifo_send_level - In order to optimize DSI utility, the DPI bridge * buffers a cerntain number of DPI pixels before initiating a DSI packet. This configuration port * controls the level at which the DPI Host bridge begins sending pixels. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK (0xFFFF0000U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT (16U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK (0x7U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT (0U) /*! dsi_host_cfg_dpi_interface_color_coding - Sets the distribution of RGB bits within the 24-bit d * bus, as specified by the DPI specification. 0= 16-bit Configuration 1 1= 16-bit Configuration * 2 2= 16-bit Configuration 3 3= 18-bit Configuration 1 4= 18-bit Configuration 2 5= 24-bit * 0b000..16-bit Configuration 1 * 0b001..16-bit Configuration 2 * 0b010..16-bit Configuration 3 * 0b011..18-bit Configuration 1 * 0b100..18-bit Configuration 2 * 0b101..24-bit */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_MASK (0xFFFFFFF8U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_SHIFT (3U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_PIXEL_FORMAT - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK (0x3U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT (0U) /*! dsi_host_cfg_dpi_pixel_format - Sets the DSI packet type of the pixels. * 0b00..16 bit * 0b01..18 bit * 0b10..18 bit loosely packed * 0b11..24 bit */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_MASK (0xFFFFFFFCU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_SHIFT (2U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VSYNC_POLARITY - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT (0U) /*! dsi_host_cfg_dpi_vsync_polarity - Sets polarity of dpi_vsync_input 0 - active low 1 - active high */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_HSYNC_POLARITY - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT (0U) /*! dsi_host_cfg_dpi_hsync_polarity - Sets polarity of dpi_hsync_input. * 0b0..active low * 0b1..active high */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VIDEO_MODE - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK (0x3U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT (0U) /*! dsi_host_cfg_dpi_video_mode - Select DSI video mode that the host DPI module should generate packets for. * 0b00..Non-Burst mode with Sync Pulses * 0b01..Non-Burst mode with Sync Events * 0b10..Burst mode * 0b11..Reserved, not valid */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_MASK (0xFFFFFFFCU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_SHIFT (2U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_HFP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK (0xFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT (0U) /*! dsi_host_cfg_dpi_hfp - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_MASK (0xFFFF0000U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_SHIFT (16U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_HBP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK (0xFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT (0U) /*! dsi_host_cfg_dpi_hbp - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_MASK (0xFFFF0000U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_SHIFT (16U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_HSA - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK (0xFFFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT (0U) /*! dsi_host_cfg_dpi_hsa - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_MASK (0xFFFF0000U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_SHIFT (16U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT (0U) /*! dsi_host_cfg_dpi_enable_mult_pkts - Enable Multiple packets per video line. When enabled, * cfg_dpi_pixel_payload_size must be set to exactly half the size of the video line. * 0b0..Video Line is sent in a single packet * 0b1..Video Line is sent in two packets */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VBP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK (0xFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT (0U) /*! dsi_host_cfg_dpi_vbp - Sets the number of lines in the vertical back porch. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_MASK (0xFFFFFF00U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_SHIFT (8U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VFP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK (0xFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT (0U) /*! dsi_host_cfg_dpi_vfp - Sets the number of lines in the vertical front porch. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_MASK (0xFFFFFF00U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_SHIFT (8U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_BLLP_MODE - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT (0U) /*! dsi_host_cfg_dpi_bllp_mode - Optimize bllp periods to Low Power mode when possible. * 0b0..Blanking packets are sent during BLLP periods * 0b1..LP mode is used for BLLP periods */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT (0U) /*! dsi_host_cfg_dpi_use_null_pkt_bllp - Selects type of blanking packet to be sent during bllp region. * 0b0..Blanking packet used in bllp region 1 * 0b1..Null packet used in bllp region */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VACTIVE - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK (0x3FFFU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT (0U) /*! dsi_host_cfg_dpi_vactive - Sets the number of lines in the vertical active aread. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_MASK (0xFFFFC000U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_SHIFT (14U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_MASK) /*! @} */ /*! @name DSI_HOST_CFG_DPI_VC - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK (0x3U) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT (0U) /*! dsi_host_cfg_dpi_vc - Sets the Virtual Channel (VC) of packets that will be sent to the receive * packet interface. Packets with VC not equal to this value are discarded and the "DSI VC ID * Invalid" bit (bit 12) in the DSI error report is set. */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_MASK (0xFFFFFFFCU) #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_SHIFT (2U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_MASK) /*! @} */ /*! @name DSI_HOST_TX_PAYLOAD - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK (0xFFFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT (0U) /*! dsi_host_tx_payload - Tx Payload data write register. Writes to this registers load the payload fifo with 32 bit values. */ #define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK) /*! @} */ /*! @name DSI_HOST_PKT_CONTROL - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK (0x7FFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT (0U) /*! dsi_host_pkt_control - Tx packet control register. * 0b000000000000000000000000000-0b000000000000000000000001111..Packet word count * 0b000000000000000000000010000-0b000000000000000000000010001..Packet Virtual Channel * 0b000000000000000000000010010-0b000000000000000000000010111..Packet Header DSI Data Type * 0b000000000000000000000011000..Lp or HS select * 0b000000000000000000000011001..perform BTA after packet is sent * 0b000000000000000000000011010..perform BTA only, no packet tx */ #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK) #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_MASK (0xF8000000U) #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_SHIFT (27U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_MASK) /*! @} */ /*! @name DSI_HOST_SEND_PACKET - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK (0x1U) #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT (0U) /*! dsi_host_send_packet - Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent. */ #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK) #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_MASK) /*! @} */ /*! @name DSI_HOST_PKT_STATUS - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK (0x1FFU) #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT (0U) /*! dsi_host_pkt_status - Status of APB to packet interface. * 0b000000000..state machine not idle * 0b000000001..Tx packet done * 0b000000010..dphy direction * 0b000000011..tx fifo overflow * 0b000000100..tx fifo underflow * 0b000000101..rx fifo overflow * 0b000000110..rx fifo underflow * 0b000000111..rx packet header has been received * 0b000001000..all rx packet payload data has been received */ #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK) #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_MASK (0xFFFFFE00U) #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_SHIFT (9U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_MASK) /*! @} */ /*! @name DSI_HOST_PKT_FIFO_WR_LEVEL - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK (0xFFFFU) #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT (0U) /*! dsi_host_pkt_fifo_wr_level - Write level of APB to pkt interface fifo */ #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK) #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_MASK (0xFFFF0000U) #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_SHIFT (16U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_MASK) /*! @} */ /*! @name DSI_HOST_PKT_FIFO_RD_LEVEL - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK (0xFFFFU) #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT (0U) /*! dsi_host_pkt_fifo_rd_level - Read level of APB to pkt interface fifo */ #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK) #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_MASK (0xFFFF0000U) #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_SHIFT (16U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_MASK) /*! @} */ /*! @name DSI_HOST_PKT_RX_PAYLOAD - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK (0xFFFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT (0U) /*! dsi_host_pkt_rx_payload - APB to pkt interface rx payload read */ #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK) /*! @} */ /*! @name DSI_HOST_PKT_RX_PKT_HEADER - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK (0xFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT (0U) /*! dsi_host_pkt_rx_pkt_header - APB to pkt interface rx packet header. * 0b000000000000000000000000-0b000000000000000000001111..word count * 0b000000000000000000010000-0b000000000000000000010101..data type * 0b000000000000000000010110-0b000000000000000000010111..Virtual Channel */ #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK) #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_MASK (0xFF000000U) #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_SHIFT (24U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_MASK) /*! @} */ /*! @name DSI_HOST_IRQ_STATUS - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK (0xFFFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT (0U) /*! dsi_host_irq_status - Status of APB to packet interface. * 0b00000000000000000000000000000000..state machine not idle * 0b00000000000000000000000000000001..Tx packet done * 0b00000000000000000000000000000010..dphy direction * 0b00000000000000000000000000000011..tx fifo overflow * 0b00000000000000000000000000000100..tx fifo underflow * 0b00000000000000000000000000000101..rx fifo overflow * 0b00000000000000000000000000000110..rx fifo underflow * 0b00000000000000000000000000000111..rx packet header has been received * 0b00000000000000000000000000001000..all rx packet payload data has been received status_out port bit descriptions * 0b00000000000000000000000000001000-0b00000000000000000000000000011100..map directory to dsi host controller * 0b00000000000000000000000000011101..host bta timeout, host controller host_bta_timeout port * 0b00000000000000000000000000011110..low power rx timeout, host controller lp_rx_timeout port * 0b00000000000000000000000000011111..high speed tx timeout, host controller hs_tx_timeout port */ #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK) /*! @} */ /*! @name DSI_HOST_IRQ_STATUS2 - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK (0x7U) #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT (0U) /*! dsi_host_irq_status2 - Status of APB to packet interface part 2, read part 2 first then * dsi_host_irq_status. reading dsi_host_irq_status will clear both status and status2. * 0b000..single bit ecc error * 0b001..multi bit ecc error * 0b010..crc error */ #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK) #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_MASK (0xFFFFFFF8U) #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_SHIFT (3U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_MASK) /*! @} */ /*! @name DSI_HOST_IRQ_MASK - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK (0xFFFFFFFFU) #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT (0U) /*! dsi_host_irq_mask - irq mask * 0b00000000000000000000000000000000..state machine not idle * 0b00000000000000000000000000000001..Tx packet done * 0b00000000000000000000000000000010..dphy direction * 0b00000000000000000000000000000011..tx fifo overflow * 0b00000000000000000000000000000100..tx fifo underflow * 0b00000000000000000000000000000101..rx fifo overflow * 0b00000000000000000000000000000110..rx fifo underflow * 0b00000000000000000000000000000111..rx packet header has been received * 0b00000000000000000000000000001000..all rx packet payload data has been received * 0b00000000000000000000000000001000-0b00000000000000000000000000011100..map directory to dsi host controller status_out port bit descriptions * 0b00000000000000000000000000011101..high speed tx timeout, host controller hs_tx_timeout port * 0b00000000000000000000000000011110..low power rx timeout, host controller lp_rx_timeout port * 0b00000000000000000000000000011111..host bta timeout, host controller host_bta_timeout port */ #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK) /*! @} */ /*! @name DSI_HOST_IRQ_MASK2 - */ /*! @{ */ #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK (0x7U) #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT (0U) /*! dsi_host_irq_mask2 - irq mask 2 * 0b000..single bit ecc error * 0b001..multi bit ecc error * 0b010..crc error */ #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK) #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_MASK (0xFFFFFFF8U) #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_SHIFT (3U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_MASK) /*! @} */ /*! @name DPHY_PD_TX - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_MASK (0x1U) #define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_SHIFT (0U) /*! dphy_pd_tx - DPHY PD_TX input control */ #define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_MASK) #define MIPI_DSI_HOST_DPHY_PD_TX_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DPHY_PD_TX_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_PD_TX_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_TX_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_TX_reserved_MASK) /*! @} */ /*! @name DPHY_M_PRG_HS_PREPARE - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK (0x3U) #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT (0U) /*! dphy_m_prg_hs_prepare - DPHY m_PRG_HS_PREPARE input */ #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK) #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_MASK (0xFFFFFFFCU) #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_SHIFT (2U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_MASK) /*! @} */ /*! @name DPHY_MC_PRG_HS_PREPARE - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK (0x1U) #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT (0U) /*! dphy_mc_prg_hs_prepare - DPHY mc_PRG_HS_PREPARE input */ #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK) #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_MASK) /*! @} */ /*! @name DPHY_M_PRG_HS_ZERO - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK (0x1FU) #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT (0U) /*! dphy_m_prg_hs_zero - DPHY m_PRG_HS_ZERO input */ #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK) #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_MASK (0xFFFFFFE0U) #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_SHIFT (5U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_MASK) /*! @} */ /*! @name DPHY_MC_PRG_HS_ZERO - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK (0x3FU) #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT (0U) /*! dphy_mc_prg_hs_zero - DPHY mc_PRG_HS_ZERO input */ #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK) #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_MASK (0xFFFFFFC0U) #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_SHIFT (6U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_MASK) /*! @} */ /*! @name DPHY_M_PRG_HS_TRAIL - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK (0xFU) #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT (0U) /*! dphy_m_prg_hs_trail - DPHY m_PRG_HS_TRAIL input */ #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK) #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_MASK (0xFFFFFFF0U) #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_SHIFT (4U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_MASK) /*! @} */ /*! @name DPHY_MC_PRG_HS_TRAIL - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK (0xFU) #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT (0U) /*! dphy_mc_prg_hs_trail - DPHY mc_PRG_HS_TRAIL input */ #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK) #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_MASK (0xFFFFFFF0U) #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_SHIFT (4U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_MASK) /*! @} */ /*! @name DPHY_PD_PLL - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_MASK (0x1U) #define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_SHIFT (0U) /*! dphy_pd_pll - DPHY PD_PLL input */ #define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_MASK) #define MIPI_DSI_HOST_DPHY_PD_PLL_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DPHY_PD_PLL_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_PD_PLL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_PLL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_PLL_reserved_MASK) /*! @} */ /*! @name DPHY_TST - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK (0x3FU) #define MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT (0U) /*! dphy_tst - DPHY TST input */ #define MIPI_DSI_HOST_DPHY_TST_dphy_tst(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT)) & MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK) #define MIPI_DSI_HOST_DPHY_TST_reserved_MASK (0xFFFFFFC0U) #define MIPI_DSI_HOST_DPHY_TST_reserved_SHIFT (6U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_TST_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TST_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_TST_reserved_MASK) /*! @} */ /*! @name DPHY_CN - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_CN_dphy_cn_MASK (0x1FU) #define MIPI_DSI_HOST_DPHY_CN_dphy_cn_SHIFT (0U) /*! dphy_cn - DPHY CN input */ #define MIPI_DSI_HOST_DPHY_CN_dphy_cn(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CN_dphy_cn_SHIFT)) & MIPI_DSI_HOST_DPHY_CN_dphy_cn_MASK) #define MIPI_DSI_HOST_DPHY_CN_reserved_MASK (0xFFFFFFE0U) #define MIPI_DSI_HOST_DPHY_CN_reserved_SHIFT (5U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_CN_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CN_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_CN_reserved_MASK) /*! @} */ /*! @name DPHY_CM - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_CM_dphy_cm_MASK (0xFFU) #define MIPI_DSI_HOST_DPHY_CM_dphy_cm_SHIFT (0U) /*! dphy_cm - DPHY CM input */ #define MIPI_DSI_HOST_DPHY_CM_dphy_cm(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CM_dphy_cm_SHIFT)) & MIPI_DSI_HOST_DPHY_CM_dphy_cm_MASK) #define MIPI_DSI_HOST_DPHY_CM_reserved_MASK (0xFFFFFF00U) #define MIPI_DSI_HOST_DPHY_CM_reserved_SHIFT (8U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_CM_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CM_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_CM_reserved_MASK) /*! @} */ /*! @name DPHY_CO - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_CO_dphy_co_MASK (0x3U) #define MIPI_DSI_HOST_DPHY_CO_dphy_co_SHIFT (0U) /*! dphy_co - DPHY CO input */ #define MIPI_DSI_HOST_DPHY_CO_dphy_co(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CO_dphy_co_SHIFT)) & MIPI_DSI_HOST_DPHY_CO_dphy_co_MASK) #define MIPI_DSI_HOST_DPHY_CO_reserved_MASK (0xFFFFFFFCU) #define MIPI_DSI_HOST_DPHY_CO_reserved_SHIFT (2U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_CO_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CO_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_CO_reserved_MASK) /*! @} */ /*! @name DPHY_LOCK - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_MASK (0x1U) #define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_SHIFT (0U) /*! dphy_lock - DPHY PLL LOCK output */ #define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_MASK) #define MIPI_DSI_HOST_DPHY_LOCK_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DPHY_LOCK_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_LOCK_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_reserved_MASK) /*! @} */ /*! @name DPHY_LOCK_BYP - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_MASK (0x1U) #define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT (0U) /*! dphy_lock_byp - DPHY LOCK_BYP input */ #define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_MASK) #define MIPI_DSI_HOST_DPHY_LOCK_BYP_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DPHY_LOCK_BYP_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_LOCK_BYP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_BYP_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_BYP_reserved_MASK) /*! @} */ /*! @name DPHY_TX_RCAL - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_MASK (0x3U) #define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_SHIFT (0U) /*! dphy_tx_rcal - DPHY RTERM_SEL input */ #define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_SHIFT)) & MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_MASK) #define MIPI_DSI_HOST_DPHY_TX_RCAL_reserved_MASK (0xFFFFFFFCU) #define MIPI_DSI_HOST_DPHY_TX_RCAL_reserved_SHIFT (2U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_TX_RCAL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TX_RCAL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_TX_RCAL_reserved_MASK) /*! @} */ /*! @name DPHY_AUTO_PD_EN - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK (0x1U) #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT (0U) /*! dphy_auto_pd_en - DPHY AUTO_PD_EN input */ #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT)) & MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK) #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_MASK (0xFFFFFFFEU) #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_SHIFT (1U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_MASK) /*! @} */ /*! @name DPHY_RXLPRP - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK (0x3U) #define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT (0U) /*! dphy_rxlprp - DPHY RXLPRP input */ #define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK) #define MIPI_DSI_HOST_DPHY_RXLPRP_reserved_MASK (0xFFFFFFFCU) #define MIPI_DSI_HOST_DPHY_RXLPRP_reserved_SHIFT (2U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_RXLPRP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXLPRP_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_RXLPRP_reserved_MASK) /*! @} */ /*! @name DPHY_RXCDRP - */ /*! @{ */ #define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK (0x3U) #define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT (0U) /*! dphy_rxcdrp - DPHY RXCDRP input */ #define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK) #define MIPI_DSI_HOST_DPHY_RXCDRP_reserved_MASK (0xFFFFFFFCU) #define MIPI_DSI_HOST_DPHY_RXCDRP_reserved_SHIFT (2U) /*! reserved - reserved */ #define MIPI_DSI_HOST_DPHY_RXCDRP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXCDRP_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_RXCDRP_reserved_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_DSI_HOST_Register_Masks */ /* MIPI_DSI_HOST - Peripheral instance base addresses */ /** Peripheral DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST base address */ #define DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST_BASE (0x56228000u) /** Peripheral DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST base pointer */ #define DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST_BASE) /** Peripheral DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST base address */ #define DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST_BASE (0x56248000u) /** Peripheral DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST base pointer */ #define DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST_BASE) /** Array initializer of MIPI_DSI_HOST peripheral base addresses */ #define MIPI_DSI_HOST_BASE_ADDRS { DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST_BASE, DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST_BASE } /** Array initializer of MIPI_DSI_HOST peripheral base pointers */ #define MIPI_DSI_HOST_BASE_PTRS { DI_MIPI_DSI_LVDS_0__MIPI_DSI_HOST, DI_MIPI_DSI_LVDS_1__MIPI_DSI_HOST } /*! * @} */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_DSI_LVDS_COMBO_CSR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_LVDS_COMBO_CSR_Peripheral_Access_Layer MIPI_DSI_LVDS_COMBO_CSR Peripheral Access Layer * @{ */ /** MIPI_DSI_LVDS_COMBO_CSR - Register Layout Typedef */ typedef struct { __IO uint32_t LVDS_PHY_CTRL; /**< PHY in LVDS mode control register, offset: 0x0 */ uint8_t RESERVED_0[28]; __IO uint32_t SS_CRTL; /**< SS control register, offset: 0x20 */ uint8_t RESERVED_1[12]; __IO uint32_t ULPS_CTRL; /**< ULPS Control Register, offset: 0x30 */ uint8_t RESERVED_2[12]; __IO uint32_t PXL2DPI_CTRL; /**< PXL2DPI Control Register, offset: 0x40 */ uint8_t RESERVED_3[156]; __IO uint32_t PM_CTRL; /**< Pixel Mapper Control Register, offset: 0xE0 */ } MIPI_DSI_LVDS_COMBO_CSR_Type; /* ---------------------------------------------------------------------------- -- MIPI_DSI_LVDS_COMBO_CSR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_LVDS_COMBO_CSR_Register_Masks MIPI_DSI_LVDS_COMBO_CSR Register Masks * @{ */ /*! @name LVDS_PHY_CTRL - PHY in LVDS mode control register */ /*! @{ */ #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_LVDS_EN_MASK (0x1U) #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_LVDS_EN_SHIFT (0U) /*! LVDS_EN - LVDS TX enable * 0b0..LVDS TX disable * 0b1..LVDS TX enable */ #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_LVDS_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_LVDS_EN_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_LVDS_EN_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_RFB_MASK (0x2U) #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_RFB_SHIFT (1U) /*! RFB - Rising / falling edge clock selection * 0b0..Falling edge * 0b1..Rising edge */ #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_RFB(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_RFB_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_RFB_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CA_MASK (0x1CU) #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CA_SHIFT (2U) /*! CA - Driver output current * 0b100..Default setting */ #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CA(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CA_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CA_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CCM_MASK (0xE0U) #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CCM_SHIFT (5U) /*! CCM - Common mode voltage * 0b100..Default setting */ #define MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CCM(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CCM_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_LVDS_PHY_CTRL_CCM_MASK) /*! @} */ /*! @name SS_CRTL - SS control register */ /*! @{ */ #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_HSYNC_POL_MASK (0x1U) #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_HSYNC_POL_SHIFT (0U) /*! CH0_HSYNC_POL - HSYNC polarity control * 0b0..HSYNC is Low active * 0b1..HSYNC is High active */ #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_HSYNC_POL_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_HSYNC_POL_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_VSYNC_POL_MASK (0x2U) #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_VSYNC_POL_SHIFT (1U) /*! CH0_VSYNC_POL - VSYNC polarity control * 0b0..VSYNC is Low active * 0b1..VSYNC is High active */ #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_VSYNC_POL_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH0_VSYNC_POL_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_HSYNC_POL_MASK (0x4U) #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_HSYNC_POL_SHIFT (2U) /*! CH1_HSYNC_POL - HSYNC polarity control * 0b0..HSYNC is Low active * 0b1..HSYNC is High active */ #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_HSYNC_POL_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_HSYNC_POL_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_VSYNC_POL_MASK (0x8U) #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_VSYNC_POL_SHIFT (3U) /*! CH1_VSYNC_POL - VSYNC polarity control * 0b0..VSYNC is Low active * 0b1..VSYNC is High active */ #define MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_VSYNC_POL_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_SS_CRTL_CH1_VSYNC_POL_MASK) /*! @} */ /*! @name ULPS_CTRL - ULPS Control Register */ /*! @{ */ #define MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS_MASK (0x1FU) #define MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS_SHIFT (0U) /*! TX_ULPS - Low power control of DSI lanes */ #define MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_ULPS_CTRL_TX_ULPS_MASK) /*! @} */ /*! @name PXL2DPI_CTRL - PXL2DPI Control Register */ /*! @{ */ #define MIPI_DSI_LVDS_COMBO_CSR_PXL2DPI_CTRL_PXL2DPI_MASK (0x7U) #define MIPI_DSI_LVDS_COMBO_CSR_PXL2DPI_CTRL_PXL2DPI_SHIFT (0U) /*! PXL2DPI - pxl2dpi_config encoding */ #define MIPI_DSI_LVDS_COMBO_CSR_PXL2DPI_CTRL_PXL2DPI(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PXL2DPI_CTRL_PXL2DPI_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PXL2DPI_CTRL_PXL2DPI_MASK) /*! @} */ /*! @name PM_CTRL - Pixel Mapper Control Register */ /*! @{ */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_MODE_MASK (0x3U) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_MODE_SHIFT (0U) /*! CH0_MODE - LVDS Channel 0 operation mode * 0b00..Channel disabled * 0b01..Channel enabled, routed to DI0 * 0b10..Channel disabled * 0b11..Channel enabled, routed to DI1 */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_MODE_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_MODE_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_MODE_MASK (0xCU) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_MODE_SHIFT (2U) /*! CH1_MODE - LVDS Channel 1 operation mode * 0b00..Channel disabled * 0b01..Channel enabled, routed to DI0 * 0b10..Channel disabled * 0b11..Channel enabled, routed to DI1 */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_MODE_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_MODE_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_SPLIT_MODE_EN_MASK (0x10U) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_SPLIT_MODE_EN_SHIFT (4U) /*! SPLIT_MODE_EN - Enable split mode * 0b0..Split mode enabled */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_SPLIT_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_SPLIT_MODE_EN_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_SPLIT_MODE_EN_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_DATA_WIDTH_MASK (0x20U) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_DATA_WIDTH_SHIFT (5U) /*! CH0_DATA_WIDTH - Data width for LVDS channel 0 * 0b0..Data width is 18-bits wide * 0b1..Data width is 24-bits wide */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_DATA_WIDTH_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_DATA_WIDTH_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_BIT_MAPPING_MASK (0x40U) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_BIT_MAPPING_SHIFT (6U) /*! CH0_BIT_MAPPING - Data mapping to LVDS channel 0 * 0b0..Use VESA standard * 0b1..Use JEIDA standard */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_BIT_MAPPING_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH0_BIT_MAPPING_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_DATA_WIDTH_MASK (0x80U) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_DATA_WIDTH_SHIFT (7U) /*! CH1_DATA_WIDTH - Data width for LVDS channel 1 * 0b0..Data width is 18-bits wide * 0b1..Data width is 24-bits wide */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_DATA_WIDTH_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_DATA_WIDTH_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_BIT_MAPPING_MASK (0x100U) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_BIT_MAPPING_SHIFT (8U) /*! CH1_BIT_MAPPING - Data mapping to LVDS channel 1 * 0b0..Use SPWG standard * 0b1..Use JEIDA standard */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_BIT_MAPPING_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH1_BIT_MAPPING_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI0_VS_POLARITY_MASK (0x200U) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI0_VS_POLARITY_SHIFT (9U) /*! DI0_VS_POLARITY - Vsync polarity for DI0 interface * 0b0..Vsync is active low * 0b1..Vsync is active high */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI0_VS_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI0_VS_POLARITY_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI0_VS_POLARITY_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI1_VS_POLARITY_MASK (0x400U) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI1_VS_POLARITY_SHIFT (10U) /*! DI1_VS_POLARITY - Vsync polarity for DI1 interface * 0b0..Vsync is active low * 0b1..Vsync is active high */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI1_VS_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI1_VS_POLARITY_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_DI1_VS_POLARITY_MASK) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH_SEL_MASK (0x10000000U) #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH_SEL_SHIFT (28U) /*! CH_SEL * 0b0..Channel 0 (Even pixel) data output to LVDS PHY * 0b1..Channel 1 (Odd Pixel) data output to LVDS PHY */ #define MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH_SEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH_SEL_SHIFT)) & MIPI_DSI_LVDS_COMBO_CSR_PM_CTRL_CH_SEL_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_DSI_LVDS_COMBO_CSR_Register_Masks */ /* MIPI_DSI_LVDS_COMBO_CSR - Peripheral instance base addresses */ /** Peripheral MIPI_DSI_LVDS_COMBO0_CSR base address */ #define MIPI_DSI_LVDS_COMBO0_CSR_BASE (0x56221000u) /** Peripheral MIPI_DSI_LVDS_COMBO0_CSR base pointer */ #define MIPI_DSI_LVDS_COMBO0_CSR ((MIPI_DSI_LVDS_COMBO_CSR_Type *)MIPI_DSI_LVDS_COMBO0_CSR_BASE) /** Peripheral MIPI_DSI_LVDS_COMBO1_CSR base address */ #define MIPI_DSI_LVDS_COMBO1_CSR_BASE (0x56241000u) /** Peripheral MIPI_DSI_LVDS_COMBO1_CSR base pointer */ #define MIPI_DSI_LVDS_COMBO1_CSR ((MIPI_DSI_LVDS_COMBO_CSR_Type *)MIPI_DSI_LVDS_COMBO1_CSR_BASE) /** Array initializer of MIPI_DSI_LVDS_COMBO_CSR peripheral base addresses */ #define MIPI_DSI_LVDS_COMBO_CSR_BASE_ADDRS { MIPI_DSI_LVDS_COMBO0_CSR_BASE, MIPI_DSI_LVDS_COMBO1_CSR_BASE } /** Array initializer of MIPI_DSI_LVDS_COMBO_CSR peripheral base pointers */ #define MIPI_DSI_LVDS_COMBO_CSR_BASE_PTRS { MIPI_DSI_LVDS_COMBO0_CSR, MIPI_DSI_LVDS_COMBO1_CSR } /*! * @} */ /* end of group MIPI_DSI_LVDS_COMBO_CSR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIXER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIXER_Peripheral_Access_Layer MIXER Peripheral Access Layer * @{ */ /** MIXER - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[512]; __IO uint32_t CTR; /**< Mixer Control Register, offset: 0x200 */ __I uint32_t STR; /**< Mixer Status Register, offset: 0x204 */ struct { /* offset: 0x208, array step: 0x20 */ __IO uint32_t ATCR; /**< Attenuation Control Register, array offset: 0x208, array step: 0x20 */ __IO uint32_t ATIVAL; /**< Attenuation Initial value register, array offset: 0x20C, array step: 0x20 */ __IO uint32_t ATSTPUP; /**< Attenuation step up factor, array offset: 0x210, array step: 0x20 */ __IO uint32_t ATSTPDN; /**< Attenuation step down factor, array offset: 0x214, array step: 0x20 */ __IO uint32_t ATSTPTGT; /**< Attenuation step target, array offset: 0x218, array step: 0x20 */ __I uint32_t ATTNVAL; /**< Attenuation Value register, array offset: 0x21C, array step: 0x20 */ __I uint32_t ATSTP; /**< Attenuation step number register, array offset: 0x220, array step: 0x20 */ uint8_t RESERVED_0[4]; } AT[2]; } MIXER_Type; /* ---------------------------------------------------------------------------- -- MIXER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIXER_Register_Masks MIXER Register Masks * @{ */ /*! @name CTR - Mixer Control Register */ /*! @{ */ #define MIXER_CTR_MIXCLK_MASK (0x1U) #define MIXER_CTR_MIXCLK_SHIFT (0U) /*! MIXCLK - Mixing Clock source selection * 0b0..TDM 1 interface clock * 0b1..TDM 2 interface clock */ #define MIXER_CTR_MIXCLK(x) (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_MIXCLK_SHIFT)) & MIXER_CTR_MIXCLK_MASK) #define MIXER_CTR_OUTSRC_MASK (0x6U) #define MIXER_CTR_OUTSRC_SHIFT (1U) /*! OUTSRC - Output Source selection * 0b00..Disabled * 0b01..TDM 1 audio * 0b10..TDM 2 audio * 0b11..Mixed audio */ #define MIXER_CTR_OUTSRC(x) (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_OUTSRC_SHIFT)) & MIXER_CTR_OUTSRC_MASK) #define MIXER_CTR_OUTWIDTH_MASK (0x38U) #define MIXER_CTR_OUTWIDTH_SHIFT (3U) /*! OUTWIDTH - Audio sample width in TDM outgoing frame * 0b000..16 bit * 0b001..18 bit * 0b010..20 bit * 0b011..24 bit */ #define MIXER_CTR_OUTWIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_OUTWIDTH_SHIFT)) & MIXER_CTR_OUTWIDTH_MASK) #define MIXER_CTR_OUTCKPOL_MASK (0x40U) #define MIXER_CTR_OUTCKPOL_SHIFT (6U) /*! OUTCKPOL - Polarity of bit clock of TDM out interface * 0b0..positive edge * 0b1..Negative edge */ #define MIXER_CTR_OUTCKPOL(x) (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_OUTCKPOL_SHIFT)) & MIXER_CTR_OUTCKPOL_MASK) #define MIXER_CTR_MASKRTDF_MASK (0x80U) #define MIXER_CTR_MASKRTDF_SHIFT (7U) /*! MASKRTDF - Mask Frame rate difference error * 0b0..Unmask error, Frame rate mismatch error checked for mixing operation (Default) * 0b1..Mask error, Frame rate mismatch error not checked when entering into Mixing process */ #define MIXER_CTR_MASKRTDF(x) (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_MASKRTDF_SHIFT)) & MIXER_CTR_MASKRTDF_MASK) #define MIXER_CTR_MASKCKDF_MASK (0x100U) #define MIXER_CTR_MASKCKDF_SHIFT (8U) /*! MASKCKDF - Mask Clock frequency difference error * 0b0..Unmask error, Clock frequency mismatch error checked for mixing operation (Default) * 0b1..Mask error, Clock frequency mismatch error not checked when entering into Mixing process */ #define MIXER_CTR_MASKCKDF(x) (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_MASKCKDF_SHIFT)) & MIXER_CTR_MASKCKDF_MASK) #define MIXER_CTR_SYNCMODE_MASK (0x200U) #define MIXER_CTR_SYNCMODE_SHIFT (9U) /*! SYNCMODE - Sync mode configuration Enable * 0b0..Disable ; Attenuators work on their Own interface bit clock * 0b1..Enable; Any one Attenuator works on Ohters interface bit clock */ #define MIXER_CTR_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_SYNCMODE_SHIFT)) & MIXER_CTR_SYNCMODE_MASK) #define MIXER_CTR_SYNCSRC_MASK (0x400U) #define MIXER_CTR_SYNCSRC_SHIFT (10U) /*! SYNCSRC - Sync mode clock source * 0b0..TDM 1 interface * 0b1..TDM 2 interface */ #define MIXER_CTR_SYNCSRC(x) (((uint32_t)(((uint32_t)(x)) << MIXER_CTR_SYNCSRC_SHIFT)) & MIXER_CTR_SYNCSRC_MASK) /*! @} */ /*! @name STR - Mixer Status Register */ /*! @{ */ #define MIXER_STR_RATEDIFF_MASK (0x1U) #define MIXER_STR_RATEDIFF_SHIFT (0U) /*! RATEDIFF - Rate difference * 0b0..Frame rate matches between TDM1 and TDM2 * 0b1..Frame Rate mismatch between TDM1 and TDM2 */ #define MIXER_STR_RATEDIFF(x) (((uint32_t)(((uint32_t)(x)) << MIXER_STR_RATEDIFF_SHIFT)) & MIXER_STR_RATEDIFF_MASK) #define MIXER_STR_CLKDIFF_MASK (0x2U) #define MIXER_STR_CLKDIFF_SHIFT (1U) /*! CLKDIFF - Bit clock difference * 0b0..Bit clock frequency matches between TDM1 and TDM2 * 0b1..Bit clock frequency mismatch between TDM1 and TDM2 */ #define MIXER_STR_CLKDIFF(x) (((uint32_t)(((uint32_t)(x)) << MIXER_STR_CLKDIFF_SHIFT)) & MIXER_STR_CLKDIFF_MASK) #define MIXER_STR_MIXSTAT_MASK (0xCU) #define MIXER_STR_MIXSTAT_SHIFT (2U) /*! MIXSTAT - Mixer Status * 0b00..Mixer in DISABLED state (No output) * 0b01..Mixer in TDM_1 state (Output is TDM 1 stream) * 0b10..Mixer in TDM_2 state (Output is TDM 2 stream) * 0b11..Mixer in MIXED state (Output is MIXED stream of TDM 1 and TDM 2) */ #define MIXER_STR_MIXSTAT(x) (((uint32_t)(((uint32_t)(x)) << MIXER_STR_MIXSTAT_SHIFT)) & MIXER_STR_MIXSTAT_MASK) /*! @} */ /*! @name ATCR - Attenuation Control Register */ /*! @{ */ #define MIXER_ATCR_AT_EN_MASK (0x1U) #define MIXER_ATCR_AT_EN_SHIFT (0U) /*! AT_EN - Attenuation Enable * 0b0..Attenuation disabled * 0b1..Attenuation enabled */ #define MIXER_ATCR_AT_EN(x) (((uint32_t)(((uint32_t)(x)) << MIXER_ATCR_AT_EN_SHIFT)) & MIXER_ATCR_AT_EN_MASK) #define MIXER_ATCR_AT_UPDN_MASK (0x2U) #define MIXER_ATCR_AT_UPDN_SHIFT (1U) /*! AT_UPDN - Attenuation direction * 0b0..Downward attenuation * 0b1..Upward attenuation */ #define MIXER_ATCR_AT_UPDN(x) (((uint32_t)(((uint32_t)(x)) << MIXER_ATCR_AT_UPDN_SHIFT)) & MIXER_ATCR_AT_UPDN_MASK) #define MIXER_ATCR_ATSTPDIV_MASK (0x3FFCU) #define MIXER_ATCR_ATSTPDIV_SHIFT (2U) /*! ATSTPDIV - Step divider */ #define MIXER_ATCR_ATSTPDIV(x) (((uint32_t)(((uint32_t)(x)) << MIXER_ATCR_ATSTPDIV_SHIFT)) & MIXER_ATCR_ATSTPDIV_MASK) /*! @} */ /* The count of MIXER_ATCR */ #define MIXER_ATCR_COUNT (2U) /*! @name ATIVAL - Attenuation Initial value register */ /*! @{ */ #define MIXER_ATIVAL_ATINTVAL_MASK (0x3FFFFU) #define MIXER_ATIVAL_ATINTVAL_SHIFT (0U) /*! ATINTVAL - Attnuation Initial value * 0b100000000000000000..= 0.5 * 0b110000000000000000..= 0.75 * 0b111111111111111111..= 0.999996185 (default) */ #define MIXER_ATIVAL_ATINTVAL(x) (((uint32_t)(((uint32_t)(x)) << MIXER_ATIVAL_ATINTVAL_SHIFT)) & MIXER_ATIVAL_ATINTVAL_MASK) /*! @} */ /* The count of MIXER_ATIVAL */ #define MIXER_ATIVAL_COUNT (2U) /*! @name ATSTPUP - Attenuation step up factor */ /*! @{ */ #define MIXER_ATSTPUP_ATSTEPUP_MASK (0x3FFFFU) #define MIXER_ATSTPUP_ATSTEPUP_SHIFT (0U) /*! ATSTEPUP - Attnuation step up factor * 0b100000000000000000..= 0.5 * 0b110000000000000000..= 0.75 * 0b101010101010101010..= 0.666664124 (default) * 0b111111111111111111..= 0.999996185 */ #define MIXER_ATSTPUP_ATSTEPUP(x) (((uint32_t)(((uint32_t)(x)) << MIXER_ATSTPUP_ATSTEPUP_SHIFT)) & MIXER_ATSTPUP_ATSTEPUP_MASK) /*! @} */ /* The count of MIXER_ATSTPUP */ #define MIXER_ATSTPUP_COUNT (2U) /*! @name ATSTPDN - Attenuation step down factor */ /*! @{ */ #define MIXER_ATSTPDN_ATSTEPDN_MASK (0x3FFFFU) #define MIXER_ATSTPDN_ATSTEPDN_SHIFT (0U) /*! ATSTEPDN - Attnuation step down factor * 0b100000000000000000..= 0.5 * 0b110000000000000000..= 0.75 (default) * 0b111111111111111111..= 0.999996185 */ #define MIXER_ATSTPDN_ATSTEPDN(x) (((uint32_t)(((uint32_t)(x)) << MIXER_ATSTPDN_ATSTEPDN_SHIFT)) & MIXER_ATSTPDN_ATSTEPDN_MASK) /*! @} */ /* The count of MIXER_ATSTPDN */ #define MIXER_ATSTPDN_COUNT (2U) /*! @name ATSTPTGT - Attenuation step target */ /*! @{ */ #define MIXER_ATSTPTGT_ATSTPTG_MASK (0x3FFFFU) #define MIXER_ATSTPTGT_ATSTPTG_SHIFT (0U) /*! ATSTPTG - Attenuation step target value */ #define MIXER_ATSTPTGT_ATSTPTG(x) (((uint32_t)(((uint32_t)(x)) << MIXER_ATSTPTGT_ATSTPTG_SHIFT)) & MIXER_ATSTPTGT_ATSTPTG_MASK) /*! @} */ /* The count of MIXER_ATSTPTGT */ #define MIXER_ATSTPTGT_COUNT (2U) /*! @name ATTNVAL - Attenuation Value register */ /*! @{ */ #define MIXER_ATTNVAL_ATCURVAL_MASK (0x3FFFFU) #define MIXER_ATTNVAL_ATCURVAL_SHIFT (0U) /*! ATCURVAL - Current value of attenuation */ #define MIXER_ATTNVAL_ATCURVAL(x) (((uint32_t)(((uint32_t)(x)) << MIXER_ATTNVAL_ATCURVAL_SHIFT)) & MIXER_ATTNVAL_ATCURVAL_MASK) /*! @} */ /* The count of MIXER_ATTNVAL */ #define MIXER_ATTNVAL_COUNT (2U) /*! @name ATSTP - Attenuation step number register */ /*! @{ */ #define MIXER_ATSTP_STPCTR_MASK (0x3FFFFU) #define MIXER_ATSTP_STPCTR_SHIFT (0U) /*! STPCTR - Step counter value */ #define MIXER_ATSTP_STPCTR(x) (((uint32_t)(((uint32_t)(x)) << MIXER_ATSTP_STPCTR_SHIFT)) & MIXER_ATSTP_STPCTR_MASK) /*! @} */ /* The count of MIXER_ATSTP */ #define MIXER_ATSTP_COUNT (2U) /*! * @} */ /* end of group MIXER_Register_Masks */ /* MIXER - Peripheral instance base addresses */ /** Peripheral ADMA__MIXER base address */ #define ADMA__MIXER_BASE (0x59840000u) /** Peripheral ADMA__MIXER base pointer */ #define ADMA__MIXER ((MIXER_Type *)ADMA__MIXER_BASE) /** Array initializer of MIXER peripheral base addresses */ #define MIXER_BASE_ADDRS { ADMA__MIXER_BASE } /** Array initializer of MIXER peripheral base pointers */ #define MIXER_BASE_PTRS { ADMA__MIXER } /*! * @} */ /* end of group MIXER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMCAU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMCAU_Peripheral_Access_Layer MMCAU Peripheral Access Layer * @{ */ /** MMCAU - Register Layout Typedef */ typedef struct { __IO uint32_t CASR; /**< Status Register, offset: 0x0 */ __IO uint32_t CAA; /**< Accumulator, offset: 0x4 */ __IO uint32_t CA[9]; /**< General Purpose Register, array offset: 0x8, array step: 0x4 */ } MMCAU_Type; /* ---------------------------------------------------------------------------- -- MMCAU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMCAU_Register_Masks MMCAU Register Masks * @{ */ /*! @name CASR - Status Register */ /*! @{ */ #define MMCAU_CASR_IC_MASK (0x1U) #define MMCAU_CASR_IC_SHIFT (0U) /*! IC - Illegal Command * 0b0..No illegal commands issued. * 0b1..Illegal command issued. */ #define MMCAU_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_IC_SHIFT)) & MMCAU_CASR_IC_MASK) #define MMCAU_CASR_DPE_MASK (0x2U) #define MMCAU_CASR_DPE_SHIFT (1U) /*! DPE - DES Parity Error * 0b0..No error detected. * 0b1..DES key parity error detected. */ #define MMCAU_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_DPE_SHIFT)) & MMCAU_CASR_DPE_MASK) #define MMCAU_CASR_VER_MASK (0xF0000000U) #define MMCAU_CASR_VER_SHIFT (28U) /*! VER - CAU Version * 0b0001..Initial CAU version. * 0b0010..Second version, added support for SHA-256 algorithm (This is the value on this device). */ #define MMCAU_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_VER_SHIFT)) & MMCAU_CASR_VER_MASK) /*! @} */ /*! @name CAA - Accumulator */ /*! @{ */ #define MMCAU_CAA_ACC_MASK (0xFFFFFFFFU) #define MMCAU_CAA_ACC_SHIFT (0U) /*! ACC - Accumulator */ #define MMCAU_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CAA_ACC_SHIFT)) & MMCAU_CAA_ACC_MASK) /*! @} */ /*! @name CA - General Purpose Register */ /*! @{ */ #define MMCAU_CA_CAn_MASK (0xFFFFFFFFU) #define MMCAU_CA_CAn_SHIFT (0U) /*! CAn - General Purpose Registers */ #define MMCAU_CA_CAn(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CA_CAn_SHIFT)) & MMCAU_CA_CAn_MASK) /*! @} */ /* The count of MMCAU_CA */ #define MMCAU_CA_COUNT (9U) /*! * @} */ /* end of group MMCAU_Register_Masks */ /* MMCAU - Peripheral instance base addresses */ /** Peripheral MMCAU base address */ #define MMCAU_BASE (0xE0081000u) /** Peripheral MMCAU base pointer */ #define MMCAU ((MMCAU_Type *)MMCAU_BASE) /** Array initializer of MMCAU peripheral base addresses */ #define MMCAU_BASE_ADDRS { MMCAU_BASE } /** Array initializer of MMCAU peripheral base pointers */ #define MMCAU_BASE_PTRS { MMCAU } /*! * @} */ /* end of group MMCAU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MQS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MQS_Peripheral_Access_Layer MQS Peripheral Access Layer * @{ */ /** MQS - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< MQS Configuration Register, offset: 0x0 */ } MQS_Type; /* ---------------------------------------------------------------------------- -- MQS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MQS_Register_Masks MQS Register Masks * @{ */ /*! @name MCR - MQS Configuration Register */ /*! @{ */ #define MQS_MCR_DIV_MASK (0xFFU) #define MQS_MCR_DIV_SHIFT (0U) /*! DIV - Clock Divider Ratio * 0bxxxxxxxx..MQS clock = SAI output clock/(DIV+1) */ #define MQS_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << MQS_MCR_DIV_SHIFT)) & MQS_MCR_DIV_MASK) #define MQS_MCR_OVR_MASK (0x100000U) #define MQS_MCR_OVR_SHIFT (20U) /*! OVR - PWM Oversampling Ratio * 0b0..32 * 0b1..64 */ #define MQS_MCR_OVR(x) (((uint32_t)(((uint32_t)(x)) << MQS_MCR_OVR_SHIFT)) & MQS_MCR_OVR_MASK) #define MQS_MCR_RST_MASK (0x1000000U) #define MQS_MCR_RST_SHIFT (24U) /*! RST - Software Reset * 0b0..Negate Reset * 0b1..Assert Reset */ #define MQS_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << MQS_MCR_RST_SHIFT)) & MQS_MCR_RST_MASK) #define MQS_MCR_ENB_MASK (0x10000000U) #define MQS_MCR_ENB_SHIFT (28U) /*! ENB - MQS Module Enable * 0b0..Disable MQS * 0b1..Enable MQS */ #define MQS_MCR_ENB(x) (((uint32_t)(((uint32_t)(x)) << MQS_MCR_ENB_SHIFT)) & MQS_MCR_ENB_MASK) /*! @} */ /*! * @} */ /* end of group MQS_Register_Masks */ /* MQS - Peripheral instance base addresses */ /** Peripheral ADMA__MQS base address */ #define ADMA__MQS_BASE (0x59850000u) /** Peripheral ADMA__MQS base pointer */ #define ADMA__MQS ((MQS_Type *)ADMA__MQS_BASE) /** Array initializer of MQS peripheral base addresses */ #define MQS_BASE_ADDRS { ADMA__MQS_BASE } /** Array initializer of MQS peripheral base pointers */ #define MQS_BASE_PTRS { ADMA__MQS } /*! * @} */ /* end of group MQS_Peripheral_Access_Layer */ /*! * @brief Core B boot mode. */ typedef enum _mu_core_boot_mode { kMU_CoreBootFromAddr0 = 0x00U, /*!< Boot from 0x00. */ kMU_CoreBootFromDmem = 0x01U, /*!< Boot from DMEM base. */ kMU_CoreBootFromImem = 0x02U, /*!< Boot from IMEM base. */ } mu_core_boot_mode_t; /*! * @brief Power mode definition. */ typedef enum _mu_power_mode { kMU_PowerModeRun = 0x00U, /*!< Run mode. */ kMU_PowerModeWait = 0x01U, /*!< WAIT mode. */ kMU_PowerModeStop = 0x02U, /*!< STOP/VLPS mode. */ kMU_PowerModeDsm = 0x03U, /*!< DSM: LLS/VLLS mode. */ } mu_power_mode_t; /* ---------------------------------------------------------------------------- -- MU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer * @{ */ /** MU - Register Layout Typedef */ typedef struct { __IO uint32_t TR[4]; /**< Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4 */ __I uint32_t RR[4]; /**< Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4 */ __IO uint32_t SR; /**< Processor B Status Register, offset: 0x20 */ __IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */ } MU_Type; /* ---------------------------------------------------------------------------- -- MU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MU_Register_Masks MU Register Masks * @{ */ /*! @name TR - Processor B Transmit Register 0..Processor B Transmit Register 3 */ /*! @{ */ #define MU_TR_ATR0_MASK (0xFFFFFFFFU) #define MU_TR_ATR0_SHIFT (0U) /*! ATR0 - ATR0 */ #define MU_TR_ATR0(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_ATR0_SHIFT)) & MU_TR_ATR0_MASK) #define MU_TR_ATR1_MASK (0xFFFFFFFFU) #define MU_TR_ATR1_SHIFT (0U) /*! ATR1 - ATR1 */ #define MU_TR_ATR1(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_ATR1_SHIFT)) & MU_TR_ATR1_MASK) #define MU_TR_ATR2_MASK (0xFFFFFFFFU) #define MU_TR_ATR2_SHIFT (0U) /*! ATR2 - ATR2 */ #define MU_TR_ATR2(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_ATR2_SHIFT)) & MU_TR_ATR2_MASK) #define MU_TR_ATR3_MASK (0xFFFFFFFFU) #define MU_TR_ATR3_SHIFT (0U) /*! ATR3 - ATR3 */ #define MU_TR_ATR3(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_ATR3_SHIFT)) & MU_TR_ATR3_MASK) #define MU_TR_BTR0_MASK (0xFFFFFFFFU) #define MU_TR_BTR0_SHIFT (0U) /*! BTR0 - BTR0 */ #define MU_TR_BTR0(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR0_SHIFT)) & MU_TR_BTR0_MASK) #define MU_TR_BTR1_MASK (0xFFFFFFFFU) #define MU_TR_BTR1_SHIFT (0U) /*! BTR1 - BTR1 */ #define MU_TR_BTR1(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR1_SHIFT)) & MU_TR_BTR1_MASK) #define MU_TR_BTR2_MASK (0xFFFFFFFFU) #define MU_TR_BTR2_SHIFT (0U) /*! BTR2 - BTR2 */ #define MU_TR_BTR2(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK) #define MU_TR_BTR3_MASK (0xFFFFFFFFU) #define MU_TR_BTR3_SHIFT (0U) /*! BTR3 - BTR3 */ #define MU_TR_BTR3(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR3_SHIFT)) & MU_TR_BTR3_MASK) /*! @} */ /* The count of MU_TR */ #define MU_TR_COUNT (4U) /*! @name RR - Processor B Receive Register 0..Processor B Receive Register 3 */ /*! @{ */ #define MU_RR_ARR0_MASK (0xFFFFFFFFU) #define MU_RR_ARR0_SHIFT (0U) /*! ARR0 - ARR0 */ #define MU_RR_ARR0(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_ARR0_SHIFT)) & MU_RR_ARR0_MASK) #define MU_RR_ARR1_MASK (0xFFFFFFFFU) #define MU_RR_ARR1_SHIFT (0U) /*! ARR1 - ARR1 */ #define MU_RR_ARR1(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_ARR1_SHIFT)) & MU_RR_ARR1_MASK) #define MU_RR_ARR2_MASK (0xFFFFFFFFU) #define MU_RR_ARR2_SHIFT (0U) /*! ARR2 - ARR2 */ #define MU_RR_ARR2(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_ARR2_SHIFT)) & MU_RR_ARR2_MASK) #define MU_RR_ARR3_MASK (0xFFFFFFFFU) #define MU_RR_ARR3_SHIFT (0U) /*! ARR3 - ARR3 */ #define MU_RR_ARR3(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_ARR3_SHIFT)) & MU_RR_ARR3_MASK) #define MU_RR_BRR0_MASK (0xFFFFFFFFU) #define MU_RR_BRR0_SHIFT (0U) /*! BRR0 - BRR0 */ #define MU_RR_BRR0(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR0_SHIFT)) & MU_RR_BRR0_MASK) #define MU_RR_BRR1_MASK (0xFFFFFFFFU) #define MU_RR_BRR1_SHIFT (0U) /*! BRR1 - BRR1 */ #define MU_RR_BRR1(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR1_SHIFT)) & MU_RR_BRR1_MASK) #define MU_RR_BRR2_MASK (0xFFFFFFFFU) #define MU_RR_BRR2_SHIFT (0U) /*! BRR2 - BRR2 */ #define MU_RR_BRR2(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR2_SHIFT)) & MU_RR_BRR2_MASK) #define MU_RR_BRR3_MASK (0xFFFFFFFFU) #define MU_RR_BRR3_SHIFT (0U) /*! BRR3 - BRR3 */ #define MU_RR_BRR3(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR3_SHIFT)) & MU_RR_BRR3_MASK) /*! @} */ /* The count of MU_RR */ #define MU_RR_COUNT (4U) /*! @name SR - Processor B Status Register */ /*! @{ */ #define MU_SR_Fn_MASK (0x7U) #define MU_SR_Fn_SHIFT (0U) /*! Fn - Fn * 0b000..BAFn bit in BCR register is written 0 (default). * 0b001..BAFn bit in BCR register is written 1. */ #define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK) #define MU_SR_EP_MASK (0x10U) #define MU_SR_EP_SHIFT (4U) /*! EP - EP * 0b0..The Processor A-side event is not pending (default). * 0b1..The Processor A-side event is pending. */ #define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) #define MU_SR_APM_MASK (0x60U) #define MU_SR_APM_SHIFT (5U) /*! APM - APM * 0b00..The System is in Run Mode. * 0b01..The System is in WAIT Mode. * 0b10..Reserved. * 0b11..The System is in STOP Mode. */ #define MU_SR_APM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_APM_SHIFT)) & MU_SR_APM_MASK) #define MU_SR_ARS_MASK (0x80U) #define MU_SR_ARS_SHIFT (7U) /*! ARS - ARS * 0b0..The Processor A or the Processor A-side of the MU is not in reset. * 0b1..The Processor A or the Processor A-side of the MU is in reset. */ #define MU_SR_ARS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_ARS_SHIFT)) & MU_SR_ARS_MASK) #define MU_SR_BRS_MASK (0x80U) #define MU_SR_BRS_SHIFT (7U) /*! BRS - BRS * 0b0..The Processor B-side of the MU is not in reset. * 0b1..The Processor B-side of the MU is in reset. */ #define MU_SR_BRS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_BRS_SHIFT)) & MU_SR_BRS_MASK) #define MU_SR_FUP_MASK (0x100U) #define MU_SR_FUP_SHIFT (8U) /*! FUP - FUP * 0b0..No flags updated, initiated by the Processor A, in progress (default) * 0b1..Processor A initiated flags update, processing */ #define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) #define MU_SR_BRDIP_MASK (0x200U) #define MU_SR_BRDIP_SHIFT (9U) /*! BRDIP - BRDIP * 0b0..The Processor A general purpose interrupt 3, because of a Processor B-side reset de-assertion, is cleared (default). * 0b1..The Processor B-side is out of reset. */ #define MU_SR_BRDIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_BRDIP_SHIFT)) & MU_SR_BRDIP_MASK) #define MU_SR_TEn_MASK (0xF00000U) #define MU_SR_TEn_SHIFT (20U) /*! TEn - TEn * 0b0000..ATRn register is not empty. * 0b0001..ATRn register is empty (default). */ #define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK) #define MU_SR_RFn_MASK (0xF000000U) #define MU_SR_RFn_SHIFT (24U) /*! RFn - RFn * 0b0000..ARRn register is not full (default). * 0b0001..ARRn register has received data from BTRn register and is ready to be read by the Processor A. */ #define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK) #define MU_SR_GIPn_MASK (0xF0000000U) #define MU_SR_GIPn_SHIFT (28U) /*! GIPn - GIPn * 0b0000..Processor A general purpose interrupt n is not pending. (default) * 0b0001..Processor A general purpose interrupt n is pending. */ #define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK) /*! @} */ /*! @name CR - Processor B Control Register */ /*! @{ */ #define MU_CR_ABFn_MASK (0x7U) #define MU_CR_ABFn_SHIFT (0U) /*! ABFn - ABFn * 0b000..N/A. Self clearing bit (default). * 0b001..Asserts the Processor A MU reset. */ #define MU_CR_ABFn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_ABFn_SHIFT)) & MU_CR_ABFn_MASK) #define MU_CR_BAFn_MASK (0x7U) #define MU_CR_BAFn_SHIFT (0U) /*! BAFn - BAFn * 0b000..Clears the Fn bit in the ASR register. * 0b001..Sets the Fn bit in the ASR register. */ #define MU_CR_BAFn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BAFn_SHIFT)) & MU_CR_BAFn_MASK) #define MU_CR_BHR_MASK (0x10U) #define MU_CR_BHR_SHIFT (4U) /*! BHR - BHR * 0b0..De-assert Hardware reset to the Processor B. (default) * 0b1..Assert Hardware reset to the Processor B. */ #define MU_CR_BHR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BHR_SHIFT)) & MU_CR_BHR_MASK) #define MU_CR_HRM_MASK (0x10U) #define MU_CR_HRM_SHIFT (4U) /*! HRM - HRM * 0b0..BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset). * 0b1..BHR bit in ACR is masked, disables the hardware reset request to the Processor B. */ #define MU_CR_HRM(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_HRM_SHIFT)) & MU_CR_HRM_MASK) #define MU_CR_MUR_MASK (0x20U) #define MU_CR_MUR_SHIFT (5U) /*! MUR - MUR * 0b0..N/A. Self clearing bit (default). * 0b1..Asserts the Processor A MU reset. */ #define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) #define MU_CR_BRDIE_MASK (0x40U) #define MU_CR_BRDIE_SHIFT (6U) /*! BRDIE - BRDIE * 0b0..Disables the Processor A General Purpose Interrupt 3 request due to the Processor B reset de-assertion to * the Processor A. Processor B reset deassertion causes Processor B and MU-Processor B side to come out of * reset thus setting BRDIP bit to "1". * 0b1..Enables Processor A General Purpose Interrupt 3 request due to the Processor B reset de-assertion to the Processor A. */ #define MU_CR_BRDIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BRDIE_SHIFT)) & MU_CR_BRDIE_MASK) #define MU_CR_GIRn_MASK (0xF0000U) #define MU_CR_GIRn_SHIFT (16U) /*! GIRn - GIRn * 0b0000..Processor A General Interrupt n is not requested to the Processor B (default). * 0b0001..Processor A General Interrupt n is requested to the Processor B. */ #define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK) #define MU_CR_TIEn_MASK (0xF00000U) #define MU_CR_TIEn_SHIFT (20U) /*! TIEn - TIEn * 0b0000..Disables Processor A Transmit Interrupt n. (default) * 0b0001..Enables Processor A Transmit Interrupt n. */ #define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK) #define MU_CR_RIEn_MASK (0xF000000U) #define MU_CR_RIEn_SHIFT (24U) /*! RIEn - RIEn * 0b0000..Disables Processor A Receive Interrupt n. (default) * 0b0001..Enables Processor A Receive Interrupt n. */ #define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK) #define MU_CR_GIEn_MASK (0xF0000000U) #define MU_CR_GIEn_SHIFT (28U) /*! GIEn - GIEn * 0b0000..Disables Processor A General Interrupt n. (default) * 0b0001..Enables Processor A General Interrupt n. */ #define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK) /*! @} */ /*! * @} */ /* end of group MU_Register_Masks */ /* MU - Peripheral instance base addresses */ /** Peripheral CM4__MU0_A0 base address */ #define CM4__MU0_A0_BASE (0x41440000u) /** Peripheral CM4__MU0_A0 base pointer */ #define CM4__MU0_A0 ((MU_Type *)CM4__MU0_A0_BASE) /** Peripheral CM4__MU0_A1 base address */ #define CM4__MU0_A1_BASE (0x41450000u) /** Peripheral CM4__MU0_A1 base pointer */ #define CM4__MU0_A1 ((MU_Type *)CM4__MU0_A1_BASE) /** Peripheral CM4__MU0_A2 base address */ #define CM4__MU0_A2_BASE (0x41460000u) /** Peripheral CM4__MU0_A2 base pointer */ #define CM4__MU0_A2 ((MU_Type *)CM4__MU0_A2_BASE) /** Peripheral CM4__MU0_A3 base address */ #define CM4__MU0_A3_BASE (0x41470000u) /** Peripheral CM4__MU0_A3 base pointer */ #define CM4__MU0_A3 ((MU_Type *)CM4__MU0_A3_BASE) /** Peripheral CM4__MU0_B0 base address */ #define CM4__MU0_B0_BASE (0x41430000u) /** Peripheral CM4__MU0_B0 base pointer */ #define CM4__MU0_B0 ((MU_Type *)CM4__MU0_B0_BASE) /** Peripheral CM4__MU0_B1 base address */ #define CM4__MU0_B1_BASE (0x41430080u) /** Peripheral CM4__MU0_B1 base pointer */ #define CM4__MU0_B1 ((MU_Type *)CM4__MU0_B1_BASE) /** Peripheral CM4__MU0_B2 base address */ #define CM4__MU0_B2_BASE (0x41430100u) /** Peripheral CM4__MU0_B2 base pointer */ #define CM4__MU0_B2 ((MU_Type *)CM4__MU0_B2_BASE) /** Peripheral CM4__MU0_B3 base address */ #define CM4__MU0_B3_BASE (0x41430180u) /** Peripheral CM4__MU0_B3 base pointer */ #define CM4__MU0_B3 ((MU_Type *)CM4__MU0_B3_BASE) /** Peripheral CM4__MU1_A base address */ #define CM4__MU1_A_BASE (0x41480000u) /** Peripheral CM4__MU1_A base pointer */ #define CM4__MU1_A ((MU_Type *)CM4__MU1_A_BASE) /** Peripheral LSIO__MU0_A base address */ #define LSIO__MU0_A_BASE (0x5D1B0000u) /** Peripheral LSIO__MU0_A base pointer */ #define LSIO__MU0_A ((MU_Type *)LSIO__MU0_A_BASE) /** Peripheral LSIO__MU1_A base address */ #define LSIO__MU1_A_BASE (0x5D1C0000u) /** Peripheral LSIO__MU1_A base pointer */ #define LSIO__MU1_A ((MU_Type *)LSIO__MU1_A_BASE) /** Peripheral LSIO__MU2_A base address */ #define LSIO__MU2_A_BASE (0x5D1D0000u) /** Peripheral LSIO__MU2_A base pointer */ #define LSIO__MU2_A ((MU_Type *)LSIO__MU2_A_BASE) /** Peripheral LSIO__MU3_A base address */ #define LSIO__MU3_A_BASE (0x5D1E0000u) /** Peripheral LSIO__MU3_A base pointer */ #define LSIO__MU3_A ((MU_Type *)LSIO__MU3_A_BASE) /** Peripheral LSIO__MU4_A base address */ #define LSIO__MU4_A_BASE (0x5D1F0000u) /** Peripheral LSIO__MU4_A base pointer */ #define LSIO__MU4_A ((MU_Type *)LSIO__MU4_A_BASE) /** Peripheral LSIO__MU5_A base address */ #define LSIO__MU5_A_BASE (0x5D200000u) /** Peripheral LSIO__MU5_A base pointer */ #define LSIO__MU5_A ((MU_Type *)LSIO__MU5_A_BASE) /** Peripheral LSIO__MU5_B base address */ #define LSIO__MU5_B_BASE (0x5D290000u) /** Peripheral LSIO__MU5_B base pointer */ #define LSIO__MU5_B ((MU_Type *)LSIO__MU5_B_BASE) /** Peripheral LSIO__MU6_A base address */ #define LSIO__MU6_A_BASE (0x5D210000u) /** Peripheral LSIO__MU6_A base pointer */ #define LSIO__MU6_A ((MU_Type *)LSIO__MU6_A_BASE) /** Peripheral LSIO__MU6_B base address */ #define LSIO__MU6_B_BASE (0x5D2A0000u) /** Peripheral LSIO__MU6_B base pointer */ #define LSIO__MU6_B ((MU_Type *)LSIO__MU6_B_BASE) /** Peripheral LSIO__MU7_A base address */ #define LSIO__MU7_A_BASE (0x5D220000u) /** Peripheral LSIO__MU7_A base pointer */ #define LSIO__MU7_A ((MU_Type *)LSIO__MU7_A_BASE) /** Peripheral LSIO__MU7_B base address */ #define LSIO__MU7_B_BASE (0x5D2B0000u) /** Peripheral LSIO__MU7_B base pointer */ #define LSIO__MU7_B ((MU_Type *)LSIO__MU7_B_BASE) /** Peripheral LSIO__MU8_A base address */ #define LSIO__MU8_A_BASE (0x5D230000u) /** Peripheral LSIO__MU8_A base pointer */ #define LSIO__MU8_A ((MU_Type *)LSIO__MU8_A_BASE) /** Peripheral LSIO__MU8_B base address */ #define LSIO__MU8_B_BASE (0x5D2C0000u) /** Peripheral LSIO__MU8_B base pointer */ #define LSIO__MU8_B ((MU_Type *)LSIO__MU8_B_BASE) /** Peripheral LSIO__MU9_A base address */ #define LSIO__MU9_A_BASE (0x5D240000u) /** Peripheral LSIO__MU9_A base pointer */ #define LSIO__MU9_A ((MU_Type *)LSIO__MU9_A_BASE) /** Peripheral LSIO__MU9_B base address */ #define LSIO__MU9_B_BASE (0x5D2D0000u) /** Peripheral LSIO__MU9_B base pointer */ #define LSIO__MU9_B ((MU_Type *)LSIO__MU9_B_BASE) /** Peripheral LSIO__MU10_A base address */ #define LSIO__MU10_A_BASE (0x5D250000u) /** Peripheral LSIO__MU10_A base pointer */ #define LSIO__MU10_A ((MU_Type *)LSIO__MU10_A_BASE) /** Peripheral LSIO__MU10_B base address */ #define LSIO__MU10_B_BASE (0x5D2E0000u) /** Peripheral LSIO__MU10_B base pointer */ #define LSIO__MU10_B ((MU_Type *)LSIO__MU10_B_BASE) /** Peripheral LSIO__MU11_A base address */ #define LSIO__MU11_A_BASE (0x5D260000u) /** Peripheral LSIO__MU11_A base pointer */ #define LSIO__MU11_A ((MU_Type *)LSIO__MU11_A_BASE) /** Peripheral LSIO__MU11_B base address */ #define LSIO__MU11_B_BASE (0x5D2F0000u) /** Peripheral LSIO__MU11_B base pointer */ #define LSIO__MU11_B ((MU_Type *)LSIO__MU11_B_BASE) /** Peripheral LSIO__MU12_A base address */ #define LSIO__MU12_A_BASE (0x5D270000u) /** Peripheral LSIO__MU12_A base pointer */ #define LSIO__MU12_A ((MU_Type *)LSIO__MU12_A_BASE) /** Peripheral LSIO__MU12_B base address */ #define LSIO__MU12_B_BASE (0x5D300000u) /** Peripheral LSIO__MU12_B base pointer */ #define LSIO__MU12_B ((MU_Type *)LSIO__MU12_B_BASE) /** Peripheral LSIO__MU13_A base address */ #define LSIO__MU13_A_BASE (0x5D280000u) /** Peripheral LSIO__MU13_A base pointer */ #define LSIO__MU13_A ((MU_Type *)LSIO__MU13_A_BASE) /** Peripheral LSIO__MU13_B base address */ #define LSIO__MU13_B_BASE (0x5D310000u) /** Peripheral LSIO__MU13_B base pointer */ #define LSIO__MU13_B ((MU_Type *)LSIO__MU13_B_BASE) /** Peripheral SCU__MU0_A0 base address */ #define SCU__MU0_A0_BASE (0x33440000u) /** Peripheral SCU__MU0_A0 base pointer */ #define SCU__MU0_A0 ((MU_Type *)SCU__MU0_A0_BASE) /** Peripheral SCU__MU0_A1 base address */ #define SCU__MU0_A1_BASE (0x33450000u) /** Peripheral SCU__MU0_A1 base pointer */ #define SCU__MU0_A1 ((MU_Type *)SCU__MU0_A1_BASE) /** Peripheral SCU__MU0_A2 base address */ #define SCU__MU0_A2_BASE (0x33460000u) /** Peripheral SCU__MU0_A2 base pointer */ #define SCU__MU0_A2 ((MU_Type *)SCU__MU0_A2_BASE) /** Peripheral SCU__MU0_A3 base address */ #define SCU__MU0_A3_BASE (0x33470000u) /** Peripheral SCU__MU0_A3 base pointer */ #define SCU__MU0_A3 ((MU_Type *)SCU__MU0_A3_BASE) /** Peripheral SCU__MU0_B0 base address */ #define SCU__MU0_B0_BASE (0x33430000u) /** Peripheral SCU__MU0_B0 base pointer */ #define SCU__MU0_B0 ((MU_Type *)SCU__MU0_B0_BASE) /** Peripheral SCU__MU0_B1 base address */ #define SCU__MU0_B1_BASE (0x33430080u) /** Peripheral SCU__MU0_B1 base pointer */ #define SCU__MU0_B1 ((MU_Type *)SCU__MU0_B1_BASE) /** Peripheral SCU__MU0_B2 base address */ #define SCU__MU0_B2_BASE (0x33430100u) /** Peripheral SCU__MU0_B2 base pointer */ #define SCU__MU0_B2 ((MU_Type *)SCU__MU0_B2_BASE) /** Peripheral SCU__MU0_B3 base address */ #define SCU__MU0_B3_BASE (0x33430180u) /** Peripheral SCU__MU0_B3 base pointer */ #define SCU__MU0_B3 ((MU_Type *)SCU__MU0_B3_BASE) /** Peripheral SCU__MU1_A base address */ #define SCU__MU1_A_BASE (0x33480000u) /** Peripheral SCU__MU1_A base pointer */ #define SCU__MU1_A ((MU_Type *)SCU__MU1_A_BASE) /** Array initializer of MU peripheral base addresses */ #define MU_BASE_ADDRS { CM4__MU0_A0_BASE, CM4__MU0_A1_BASE, CM4__MU0_A2_BASE, CM4__MU0_A3_BASE, CM4__MU0_B0_BASE, CM4__MU0_B1_BASE, CM4__MU0_B2_BASE, CM4__MU0_B3_BASE, CM4__MU1_A_BASE, LSIO__MU0_A_BASE, LSIO__MU1_A_BASE, LSIO__MU2_A_BASE, LSIO__MU3_A_BASE, LSIO__MU4_A_BASE, LSIO__MU5_A_BASE, LSIO__MU5_B_BASE, LSIO__MU6_A_BASE, LSIO__MU6_B_BASE, LSIO__MU7_A_BASE, LSIO__MU7_B_BASE, LSIO__MU8_A_BASE, LSIO__MU8_B_BASE, LSIO__MU9_A_BASE, LSIO__MU9_B_BASE, LSIO__MU10_A_BASE, LSIO__MU10_B_BASE, LSIO__MU11_A_BASE, LSIO__MU11_B_BASE, LSIO__MU12_A_BASE, LSIO__MU12_B_BASE, LSIO__MU13_A_BASE, LSIO__MU13_B_BASE, SCU__MU0_A0_BASE, SCU__MU0_A1_BASE, SCU__MU0_A2_BASE, SCU__MU0_A3_BASE, SCU__MU0_B0_BASE, SCU__MU0_B1_BASE, SCU__MU0_B2_BASE, SCU__MU0_B3_BASE, SCU__MU1_A_BASE } /** Array initializer of MU peripheral base pointers */ #define MU_BASE_PTRS { CM4__MU0_A0, CM4__MU0_A1, CM4__MU0_A2, CM4__MU0_A3, CM4__MU0_B0, CM4__MU0_B1, CM4__MU0_B2, CM4__MU0_B3, CM4__MU1_A, LSIO__MU0_A, LSIO__MU1_A, LSIO__MU2_A, LSIO__MU3_A, LSIO__MU4_A, LSIO__MU5_A, LSIO__MU5_B, LSIO__MU6_A, LSIO__MU6_B, LSIO__MU7_A, LSIO__MU7_B, LSIO__MU8_A, LSIO__MU8_B, LSIO__MU9_A, LSIO__MU9_B, LSIO__MU10_A, LSIO__MU10_B, LSIO__MU11_A, LSIO__MU11_B, LSIO__MU12_A, LSIO__MU12_B, LSIO__MU13_A, LSIO__MU13_B, SCU__MU0_A0, SCU__MU0_A1, SCU__MU0_A2, SCU__MU0_A3, SCU__MU0_B0, SCU__MU0_B1, SCU__MU0_B2, SCU__MU0_B3, SCU__MU1_A } /* Backward compatibility */ #define MU_SR_PM_MASK MU_SR_APM_MASK #define MU_SR_PM_SHIFT MU_SR_APM_SHIFT #define MU_SR_PM(x) MU_SR_APM(x) #define MU_SR_RS_MASK MU_SR_ARS_MASK #define MU_SR_RS_SHIFT MU_SR_ARS_SHIFT #define MU_SR_RS(x) MU_SR_ARS(x) #define MU_CR_Fn_MASK MU_CR_BAFn_MASK #define MU_CR_Fn_SHIFT MU_CR_BAFn_SHIFT #define MU_CR_Fn(x) MU_CR_BAFn(x) /*! * @} */ /* end of group MU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PC_Peripheral_Access_Layer PC Peripheral Access Layer * @{ */ /** PC - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< Control Register, offset: 0x0 */ __IO uint32_t SET; /**< Control Register, offset: 0x4 */ __IO uint32_t CLR; /**< Control Register, offset: 0x8 */ __IO uint32_t TOG; /**< Control Register, offset: 0xC */ } CTRL; struct { /* offset: 0x10 */ __IO uint32_t RW; /**< Buffer Parameter Register, offset: 0x10 */ __IO uint32_t SET; /**< Buffer Parameter Register, offset: 0x14 */ __IO uint32_t CLR; /**< Buffer Parameter Register, offset: 0x18 */ __IO uint32_t TOG; /**< Buffer Parameter Register, offset: 0x1C */ } BUF_PARA; struct { /* offset: 0x20 */ __IO uint32_t RW; /**< Software Reset Register, offset: 0x20 */ __IO uint32_t SET; /**< Software Reset Register, offset: 0x24 */ __IO uint32_t CLR; /**< Software Reset Register, offset: 0x28 */ __IO uint32_t TOG; /**< Software Reset Register, offset: 0x2C */ } SW_RESET; } PC_Type; /* ---------------------------------------------------------------------------- -- PC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PC_Register_Masks PC Register Masks * @{ */ /*! @name CTRL - Control Register */ /*! @{ */ #define PC_CTRL_ENABLE_MASK (0x1U) #define PC_CTRL_ENABLE_SHIFT (0U) /*! ENABLE - Enable(1)/disable(0) pixel combine function */ #define PC_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_ENABLE_SHIFT)) & PC_CTRL_ENABLE_MASK) #define PC_CTRL_DISP0_BYPASS_MASK (0x2U) #define PC_CTRL_DISP0_BYPASS_SHIFT (1U) /*! DISP0_BYPASS - 1: bypass Display0 (Display0 data will not be modified) 0: Display0 will not bypass (Display0 data will be modified) */ #define PC_CTRL_DISP0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_DISP0_BYPASS_SHIFT)) & PC_CTRL_DISP0_BYPASS_MASK) #define PC_CTRL_DISP0_HSYNC_POLARITY_MASK (0x4U) #define PC_CTRL_DISP0_HSYNC_POLARITY_SHIFT (2U) /*! DISP0_HSYNC_POLARITY - HSYNC polarity, high(1)/low(0), it should be same with VSYNC polarity */ #define PC_CTRL_DISP0_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_DISP0_HSYNC_POLARITY_SHIFT)) & PC_CTRL_DISP0_HSYNC_POLARITY_MASK) #define PC_CTRL_DISP0_VSYNC_POLARITY_MASK (0x8U) #define PC_CTRL_DISP0_VSYNC_POLARITY_SHIFT (3U) /*! DISP0_VSYNC_POLARITY - Vsync polarity, high(1)/low(0), it should be same with HSYNC polarity */ #define PC_CTRL_DISP0_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_DISP0_VSYNC_POLARITY_SHIFT)) & PC_CTRL_DISP0_VSYNC_POLARITY_MASK) #define PC_CTRL_DISP0_DVALID_POLARITY_MASK (0x10U) #define PC_CTRL_DISP0_DVALID_POLARITY_SHIFT (4U) /*! DISP0_DVALID_POLARITY - Data enable polarity, high(1)/low(0) */ #define PC_CTRL_DISP0_DVALID_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_DISP0_DVALID_POLARITY_SHIFT)) & PC_CTRL_DISP0_DVALID_POLARITY_MASK) #define PC_CTRL_VSYNC_MASK_ENABLE_MASK (0x20U) #define PC_CTRL_VSYNC_MASK_ENABLE_SHIFT (5U) /*! VSYNC_MASK_ENABLE - Enable(1)/disable(0) the VSYNC mask function. It is used to mask the first frame output which may be incomplete. */ #define PC_CTRL_VSYNC_MASK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_VSYNC_MASK_ENABLE_SHIFT)) & PC_CTRL_VSYNC_MASK_ENABLE_MASK) #define PC_CTRL_SKIP_MODE_MASK (0x40U) #define PC_CTRL_SKIP_MODE_SHIFT (6U) /*! SKIP_MODE - Skip mode. The data enable of Disp0 and Disp1 is aligned(1) or unaligned(0) */ #define PC_CTRL_SKIP_MODE(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_SKIP_MODE_SHIFT)) & PC_CTRL_SKIP_MODE_MASK) #define PC_CTRL_SKIP_NUMBER_MASK (0x1F80U) #define PC_CTRL_SKIP_NUMBER_SHIFT (7U) /*! SKIP_NUMBER - The pixels being skipped. A maximum of 16 pixels is enough to eliminate the edge effects of the scaling. */ #define PC_CTRL_SKIP_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_SKIP_NUMBER_SHIFT)) & PC_CTRL_SKIP_NUMBER_MASK) #define PC_CTRL_DISP1_HSYNC_POLARITY_MASK (0x2000U) #define PC_CTRL_DISP1_HSYNC_POLARITY_SHIFT (13U) /*! DISP1_HSYNC_POLARITY - 1: HSYNC positive polarity in Display 1 0: HSYNC negative polarity in Display 1 */ #define PC_CTRL_DISP1_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_DISP1_HSYNC_POLARITY_SHIFT)) & PC_CTRL_DISP1_HSYNC_POLARITY_MASK) #define PC_CTRL_DISP1_VSYNC_POLARITY_MASK (0x4000U) #define PC_CTRL_DISP1_VSYNC_POLARITY_SHIFT (14U) /*! DISP1_VSYNC_POLARITY - 1: VSYNC positive polarity in Display 1 0: VSYNC negative polarity in Display 1 */ #define PC_CTRL_DISP1_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_DISP1_VSYNC_POLARITY_SHIFT)) & PC_CTRL_DISP1_VSYNC_POLARITY_MASK) #define PC_CTRL_DISP1_DVALID_POLARITY_MASK (0x8000U) #define PC_CTRL_DISP1_DVALID_POLARITY_SHIFT (15U) /*! DISP1_DVALID_POLARITY - 1: data enable positive polarity in Display 1 0: data enable negative polarity in Display 1 */ #define PC_CTRL_DISP1_DVALID_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_DISP1_DVALID_POLARITY_SHIFT)) & PC_CTRL_DISP1_DVALID_POLARITY_MASK) #define PC_CTRL_DISP0_PIX_DATA_FORMAT_MASK (0x70000U) #define PC_CTRL_DISP0_PIX_DATA_FORMAT_SHIFT (16U) /*! DISP0_PIX_DATA_FORMAT - 000: RGB/YUV444 001: YUV422 010: YUV420 011: two RGB stream */ #define PC_CTRL_DISP0_PIX_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_DISP0_PIX_DATA_FORMAT_SHIFT)) & PC_CTRL_DISP0_PIX_DATA_FORMAT_MASK) #define PC_CTRL_DISP1_PIX_DATA_FORMAT_MASK (0x380000U) #define PC_CTRL_DISP1_PIX_DATA_FORMAT_SHIFT (19U) /*! DISP1_PIX_DATA_FORMAT - 000: RGB/YUV444 001: YUV422 010: YUV420 011: two RGB stream */ #define PC_CTRL_DISP1_PIX_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_DISP1_PIX_DATA_FORMAT_SHIFT)) & PC_CTRL_DISP1_PIX_DATA_FORMAT_MASK) #define PC_CTRL_DISP1_BYPASS_MASK (0x400000U) #define PC_CTRL_DISP1_BYPASS_SHIFT (22U) /*! DISP1_BYPASS - 1: bypass Display1 (Display1 data will not be modified) 0: Display1 will not bypass (Display1 data will be modified) */ #define PC_CTRL_DISP1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PC_CTRL_DISP1_BYPASS_SHIFT)) & PC_CTRL_DISP1_BYPASS_MASK) /*! @} */ /*! @name BUF_PARA - Buffer Parameter Register */ /*! @{ */ #define PC_BUF_PARA_BUF_ACTIVE_DEPTH_MASK (0x7FFU) #define PC_BUF_PARA_BUF_ACTIVE_DEPTH_SHIFT (0U) /*! BUF_ACTIVE_DEPTH - Offset 0x4 [10:0] buffer active depth */ #define PC_BUF_PARA_BUF_ACTIVE_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << PC_BUF_PARA_BUF_ACTIVE_DEPTH_SHIFT)) & PC_BUF_PARA_BUF_ACTIVE_DEPTH_MASK) /*! @} */ /*! @name SW_RESET - Software Reset Register */ /*! @{ */ #define PC_SW_RESET_PC_SW_RESET_MASK (0x1U) #define PC_SW_RESET_PC_SW_RESET_SHIFT (0U) /*! PC_SW_RESET - Pixel combiner Software reset control */ #define PC_SW_RESET_PC_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PC_SW_RESET_PC_SW_RESET_SHIFT)) & PC_SW_RESET_PC_SW_RESET_MASK) #define PC_SW_RESET_DISP0_SW_RESET_MASK (0x2U) #define PC_SW_RESET_DISP0_SW_RESET_SHIFT (1U) /*! DISP0_SW_RESET - Display0 Software reset control */ #define PC_SW_RESET_DISP0_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PC_SW_RESET_DISP0_SW_RESET_SHIFT)) & PC_SW_RESET_DISP0_SW_RESET_MASK) #define PC_SW_RESET_DISP1_SW_RESET_MASK (0x4U) #define PC_SW_RESET_DISP1_SW_RESET_SHIFT (2U) /*! DISP1_SW_RESET - Display1 Software reset control */ #define PC_SW_RESET_DISP1_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PC_SW_RESET_DISP1_SW_RESET_SHIFT)) & PC_SW_RESET_DISP1_SW_RESET_MASK) /*! @} */ /*! * @} */ /* end of group PC_Register_Masks */ /* PC - Peripheral instance base addresses */ /** Peripheral DC__PC base address */ #define DC__PC_BASE (0x56020000u) /** Peripheral DC__PC base pointer */ #define DC__PC ((PC_Type *)DC__PC_BASE) /** Array initializer of PC peripheral base addresses */ #define PC_BASE_ADDRS { DC__PC_BASE } /** Array initializer of PC peripheral base pointers */ #define PC_BASE_PTRS { DC__PC } /*! * @} */ /* end of group PC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PRG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PRG_Peripheral_Access_Layer PRG Peripheral Access Layer * @{ */ /** PRG - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< PRG Control Register, offset: 0x0 */ __IO uint32_t SET; /**< PRG Control Register, offset: 0x4 */ __IO uint32_t CLR; /**< PRG Control Register, offset: 0x8 */ __IO uint32_t TOG; /**< PRG Control Register, offset: 0xC */ } PRG_CTRL; struct { /* offset: 0x10 */ __I uint32_t RW; /**< PRG Status Register, offset: 0x10 */ __I uint32_t SET; /**< PRG Status Register, offset: 0x14 */ __I uint32_t CLR; /**< PRG Status Register, offset: 0x18 */ __I uint32_t TOG; /**< PRG Status Register, offset: 0x1C */ } PRG_STATUS; struct { /* offset: 0x20 */ __IO uint32_t RW; /**< PRG REG update Register, offset: 0x20 */ __IO uint32_t SET; /**< PRG REG update Register, offset: 0x24 */ __IO uint32_t CLR; /**< PRG REG update Register, offset: 0x28 */ __IO uint32_t TOG; /**< PRG REG update Register, offset: 0x2C */ } PRG_REG_UPDATE; struct { /* offset: 0x30 */ __IO uint32_t RW; /**< PRG Stride Register, offset: 0x30 */ __IO uint32_t SET; /**< PRG Stride Register, offset: 0x34 */ __IO uint32_t CLR; /**< PRG Stride Register, offset: 0x38 */ __IO uint32_t TOG; /**< PRG Stride Register, offset: 0x3C */ } PRG_STRIDE; struct { /* offset: 0x40 */ __IO uint32_t RW; /**< PRG Height Register, offset: 0x40 */ __IO uint32_t SET; /**< PRG Height Register, offset: 0x44 */ __IO uint32_t CLR; /**< PRG Height Register, offset: 0x48 */ __IO uint32_t TOG; /**< PRG Height Register, offset: 0x4C */ } PRG_HEIGHT; struct { /* offset: 0x50 */ __IO uint32_t RW; /**< PRG Base Address Register, offset: 0x50 */ __IO uint32_t SET; /**< PRG Base Address Register, offset: 0x54 */ __IO uint32_t CLR; /**< PRG Base Address Register, offset: 0x58 */ __IO uint32_t TOG; /**< PRG Base Address Register, offset: 0x5C */ } PRG_BADDR; struct { /* offset: 0x60 */ __IO uint32_t RW; /**< PRG Offset Address Register, offset: 0x60 */ __IO uint32_t SET; /**< PRG Offset Address Register, offset: 0x64 */ __IO uint32_t CLR; /**< PRG Offset Address Register, offset: 0x68 */ __IO uint32_t TOG; /**< PRG Offset Address Register, offset: 0x6C */ } PRG_OFFSET; struct { /* offset: 0x70 */ __IO uint32_t RW; /**< PRG Width Register, offset: 0x70 */ __IO uint32_t SET; /**< PRG Width Register, offset: 0x74 */ __IO uint32_t CLR; /**< PRG Width Register, offset: 0x78 */ __IO uint32_t TOG; /**< PRG Width Register, offset: 0x7C */ } PRG_WIDTH; } PRG_Type; /* ---------------------------------------------------------------------------- -- PRG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PRG_Register_Masks PRG Register Masks * @{ */ /*! @name PRG_CTRL - PRG Control Register */ /*! @{ */ #define PRG_PRG_CTRL_BYPASS_MASK (0x1U) #define PRG_PRG_CTRL_BYPASS_SHIFT (0U) #define PRG_PRG_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_BYPASS_SHIFT)) & PRG_PRG_CTRL_BYPASS_MASK) #define PRG_PRG_CTRL_RESERVED_MASK (0x2U) #define PRG_PRG_CTRL_RESERVED_SHIFT (1U) #define PRG_PRG_CTRL_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_RESERVED_SHIFT)) & PRG_PRG_CTRL_RESERVED_MASK) #define PRG_PRG_CTRL_SC_DATA_TYPE_MASK (0x4U) #define PRG_PRG_CTRL_SC_DATA_TYPE_SHIFT (2U) #define PRG_PRG_CTRL_SC_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_SC_DATA_TYPE_SHIFT)) & PRG_PRG_CTRL_SC_DATA_TYPE_MASK) #define PRG_PRG_CTRL_UV_EN_MASK (0x8U) #define PRG_PRG_CTRL_UV_EN_SHIFT (3U) #define PRG_PRG_CTRL_UV_EN(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_UV_EN_SHIFT)) & PRG_PRG_CTRL_UV_EN_MASK) #define PRG_PRG_CTRL_HANDSHAKE_MODE_MASK (0x10U) #define PRG_PRG_CTRL_HANDSHAKE_MODE_SHIFT (4U) #define PRG_PRG_CTRL_HANDSHAKE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_HANDSHAKE_MODE_SHIFT)) & PRG_PRG_CTRL_HANDSHAKE_MODE_MASK) #define PRG_PRG_CTRL_SHADOW_LOAD_MODE_MASK (0x20U) #define PRG_PRG_CTRL_SHADOW_LOAD_MODE_SHIFT (5U) #define PRG_PRG_CTRL_SHADOW_LOAD_MODE(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_SHADOW_LOAD_MODE_SHIFT)) & PRG_PRG_CTRL_SHADOW_LOAD_MODE_MASK) #define PRG_PRG_CTRL_DES_DATA_TYPE_MASK (0x30000U) #define PRG_PRG_CTRL_DES_DATA_TYPE_SHIFT (16U) #define PRG_PRG_CTRL_DES_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_DES_DATA_TYPE_SHIFT)) & PRG_PRG_CTRL_DES_DATA_TYPE_MASK) #define PRG_PRG_CTRL_SOFTRST_MASK (0x40000000U) #define PRG_PRG_CTRL_SOFTRST_SHIFT (30U) #define PRG_PRG_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_SOFTRST_SHIFT)) & PRG_PRG_CTRL_SOFTRST_MASK) #define PRG_PRG_CTRL_SHADOW_EN_MASK (0x80000000U) #define PRG_PRG_CTRL_SHADOW_EN_SHIFT (31U) #define PRG_PRG_CTRL_SHADOW_EN(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_SHADOW_EN_SHIFT)) & PRG_PRG_CTRL_SHADOW_EN_MASK) /*! @} */ /*! @name PRG_STATUS - PRG Status Register */ /*! @{ */ #define PRG_PRG_STATUS_BUFFER_VALID_A_MASK (0x1U) #define PRG_PRG_STATUS_BUFFER_VALID_A_SHIFT (0U) #define PRG_PRG_STATUS_BUFFER_VALID_A(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_STATUS_BUFFER_VALID_A_SHIFT)) & PRG_PRG_STATUS_BUFFER_VALID_A_MASK) #define PRG_PRG_STATUS_BUFFER_VALID_B_MASK (0x2U) #define PRG_PRG_STATUS_BUFFER_VALID_B_SHIFT (1U) #define PRG_PRG_STATUS_BUFFER_VALID_B(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_STATUS_BUFFER_VALID_B_SHIFT)) & PRG_PRG_STATUS_BUFFER_VALID_B_MASK) /*! @} */ /*! @name PRG_REG_UPDATE - PRG REG update Register */ /*! @{ */ #define PRG_PRG_REG_UPDATE_REG_UPDATE_MASK (0x1U) #define PRG_PRG_REG_UPDATE_REG_UPDATE_SHIFT (0U) #define PRG_PRG_REG_UPDATE_REG_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_REG_UPDATE_REG_UPDATE_SHIFT)) & PRG_PRG_REG_UPDATE_REG_UPDATE_MASK) /*! @} */ /*! @name PRG_STRIDE - PRG Stride Register */ /*! @{ */ #define PRG_PRG_STRIDE_STRIDE_MASK (0xFFFFU) #define PRG_PRG_STRIDE_STRIDE_SHIFT (0U) #define PRG_PRG_STRIDE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_STRIDE_STRIDE_SHIFT)) & PRG_PRG_STRIDE_STRIDE_MASK) /*! @} */ /*! @name PRG_HEIGHT - PRG Height Register */ /*! @{ */ #define PRG_PRG_HEIGHT_HEIGHT_MASK (0xFFFFU) #define PRG_PRG_HEIGHT_HEIGHT_SHIFT (0U) #define PRG_PRG_HEIGHT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_HEIGHT_HEIGHT_SHIFT)) & PRG_PRG_HEIGHT_HEIGHT_MASK) /*! @} */ /*! @name PRG_BADDR - PRG Base Address Register */ /*! @{ */ #define PRG_PRG_BADDR_BADDR_MASK (0xFFFFFFFFU) #define PRG_PRG_BADDR_BADDR_SHIFT (0U) #define PRG_PRG_BADDR_BADDR(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_BADDR_BADDR_SHIFT)) & PRG_PRG_BADDR_BADDR_MASK) /*! @} */ /*! @name PRG_OFFSET - PRG Offset Address Register */ /*! @{ */ #define PRG_PRG_OFFSET_X_MASK (0xFFFFU) #define PRG_PRG_OFFSET_X_SHIFT (0U) #define PRG_PRG_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_OFFSET_X_SHIFT)) & PRG_PRG_OFFSET_X_MASK) #define PRG_PRG_OFFSET_Y_MASK (0x70000U) #define PRG_PRG_OFFSET_Y_SHIFT (16U) #define PRG_PRG_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_OFFSET_Y_SHIFT)) & PRG_PRG_OFFSET_Y_MASK) /*! @} */ /*! @name PRG_WIDTH - PRG Width Register */ /*! @{ */ #define PRG_PRG_WIDTH_WIDTH_MASK (0xFFFFU) #define PRG_PRG_WIDTH_WIDTH_SHIFT (0U) #define PRG_PRG_WIDTH_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PRG_PRG_WIDTH_WIDTH_SHIFT)) & PRG_PRG_WIDTH_WIDTH_MASK) /*! @} */ /*! * @} */ /* end of group PRG_Register_Masks */ /* PRG - Peripheral instance base addresses */ /** Peripheral DC__PRG0 base address */ #define DC__PRG0_BASE (0x56040000u) /** Peripheral DC__PRG0 base pointer */ #define DC__PRG0 ((PRG_Type *)DC__PRG0_BASE) /** Peripheral DC__PRG1 base address */ #define DC__PRG1_BASE (0x56050000u) /** Peripheral DC__PRG1 base pointer */ #define DC__PRG1 ((PRG_Type *)DC__PRG1_BASE) /** Peripheral DC__PRG2 base address */ #define DC__PRG2_BASE (0x56060000u) /** Peripheral DC__PRG2 base pointer */ #define DC__PRG2 ((PRG_Type *)DC__PRG2_BASE) /** Peripheral DC__PRG3 base address */ #define DC__PRG3_BASE (0x56070000u) /** Peripheral DC__PRG3 base pointer */ #define DC__PRG3 ((PRG_Type *)DC__PRG3_BASE) /** Peripheral DC__PRG4 base address */ #define DC__PRG4_BASE (0x56080000u) /** Peripheral DC__PRG4 base pointer */ #define DC__PRG4 ((PRG_Type *)DC__PRG4_BASE) /** Peripheral DC__PRG5 base address */ #define DC__PRG5_BASE (0x56090000u) /** Peripheral DC__PRG5 base pointer */ #define DC__PRG5 ((PRG_Type *)DC__PRG5_BASE) /** Peripheral DC__PRG6 base address */ #define DC__PRG6_BASE (0x560A0000u) /** Peripheral DC__PRG6 base pointer */ #define DC__PRG6 ((PRG_Type *)DC__PRG6_BASE) /** Peripheral DC__PRG7 base address */ #define DC__PRG7_BASE (0x560B0000u) /** Peripheral DC__PRG7 base pointer */ #define DC__PRG7 ((PRG_Type *)DC__PRG7_BASE) /** Peripheral DC__PRG8 base address */ #define DC__PRG8_BASE (0x560C0000u) /** Peripheral DC__PRG8 base pointer */ #define DC__PRG8 ((PRG_Type *)DC__PRG8_BASE) /** Array initializer of PRG peripheral base addresses */ #define PRG_BASE_ADDRS { DC__PRG0_BASE, DC__PRG1_BASE, DC__PRG2_BASE, DC__PRG3_BASE, DC__PRG4_BASE, DC__PRG5_BASE, DC__PRG6_BASE, DC__PRG7_BASE, DC__PRG8_BASE } /** Array initializer of PRG peripheral base pointers */ #define PRG_BASE_PTRS { DC__PRG0, DC__PRG1, DC__PRG2, DC__PRG3, DC__PRG4, DC__PRG5, DC__PRG6, DC__PRG7, DC__PRG8 } /*! * @} */ /* end of group PRG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PWM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer * @{ */ /** PWM - Register Layout Typedef */ typedef struct { __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */ __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */ __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */ __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */ __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ } PWM_Type; /* ---------------------------------------------------------------------------- -- PWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PWM_Register_Masks PWM Register Masks * @{ */ /*! @name PWMCR - PWM Control Register */ /*! @{ */ #define PWM_PWMCR_EN_MASK (0x1U) #define PWM_PWMCR_EN_SHIFT (0U) /*! EN - EN * 0b0..PWM disabled * 0b1..PWM enabled */ #define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK) #define PWM_PWMCR_REPEAT_MASK (0x6U) #define PWM_PWMCR_REPEAT_SHIFT (1U) /*! REPEAT - REPEAT * 0b00..Use each sample once * 0b01..Use each sample twice * 0b10..Use each sample four times * 0b11..Use each sample eight times */ #define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK) #define PWM_PWMCR_SWR_MASK (0x8U) #define PWM_PWMCR_SWR_SHIFT (3U) /*! SWR - SWR * 0b0..PWM is out of reset * 0b1..PWM is undergoing reset */ #define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK) #define PWM_PWMCR_PRESCALER_MASK (0xFFF0U) #define PWM_PWMCR_PRESCALER_SHIFT (4U) /*! PRESCALER - PRESCALER * 0b000000000000..Divide by 1 * 0b000000000001..Divide by 2 * 0b111111111111..Divide by 4096 */ #define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK) #define PWM_PWMCR_CLKSRC_MASK (0x30000U) #define PWM_PWMCR_CLKSRC_SHIFT (16U) /*! CLKSRC - CLKSRC * 0b00..Clock is off * 0b01..ipg_clk * 0b10..ipg_clk_highfreq * 0b11..ipg_clk_32k */ #define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK) #define PWM_PWMCR_POUTC_MASK (0xC0000U) #define PWM_PWMCR_POUTC_SHIFT (18U) /*! POUTC - POUTC * 0b00..Output pin is set at rollover and cleared at comparison * 0b01..Output pin is cleared at rollover and set at comparison * 0b10..PWM output is disconnected * 0b11..PWM output is disconnected */ #define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK) #define PWM_PWMCR_HCTR_MASK (0x100000U) #define PWM_PWMCR_HCTR_SHIFT (20U) /*! HCTR - HCTR * 0b0..Half word swapping does not take place * 0b1..Half words from write data bus are swapped */ #define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK) #define PWM_PWMCR_BCTR_MASK (0x200000U) #define PWM_PWMCR_BCTR_SHIFT (21U) /*! BCTR - BCTR * 0b0..byte ordering remains the same * 0b1..byte ordering is reversed */ #define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK) #define PWM_PWMCR_DBGEN_MASK (0x400000U) #define PWM_PWMCR_DBGEN_SHIFT (22U) /*! DBGEN - DBGEN * 0b0..Inactive in debug mode * 0b1..Active in debug mode */ #define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK) #define PWM_PWMCR_WAITEN_MASK (0x800000U) #define PWM_PWMCR_WAITEN_SHIFT (23U) /*! WAITEN - WAITEN * 0b0..Inactive in wait mode * 0b1..Active in wait mode */ #define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK) #define PWM_PWMCR_DOZEN_MASK (0x1000000U) #define PWM_PWMCR_DOZEN_SHIFT (24U) /*! DOZEN - DOZEN * 0b0..Inactive in doze mode * 0b1..Active in doze mode */ #define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK) #define PWM_PWMCR_STOPEN_MASK (0x2000000U) #define PWM_PWMCR_STOPEN_SHIFT (25U) /*! STOPEN - STOPEN * 0b0..Inactive in stop mode * 0b1..Active in stop mode */ #define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK) #define PWM_PWMCR_FWM_MASK (0xC000000U) #define PWM_PWMCR_FWM_SHIFT (26U) /*! FWM - FWM * 0b00..FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO * 0b01..FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO * 0b10..FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO * 0b11..FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO */ #define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK) /*! @} */ /*! @name PWMSR - PWM Status Register */ /*! @{ */ #define PWM_PWMSR_FIFOAV_MASK (0x7U) #define PWM_PWMSR_FIFOAV_SHIFT (0U) /*! FIFOAV - FIFOAV * 0b000..No data available * 0b001..1 word of data in FIFO * 0b010..2 words of data in FIFO * 0b011..3 words of data in FIFO * 0b100..4 words of data in FIFO * 0b101..unused * 0b110..unused * 0b111..unused */ #define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK) #define PWM_PWMSR_FE_MASK (0x8U) #define PWM_PWMSR_FE_SHIFT (3U) /*! FE - FE * 0b0..Data level is above water mark * 0b1..When the data level falls below the mark set by FWM field */ #define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK) #define PWM_PWMSR_ROV_MASK (0x10U) #define PWM_PWMSR_ROV_SHIFT (4U) /*! ROV - ROV * 0b0..Roll-over event not occurred * 0b1..Roll-over event occurred */ #define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK) #define PWM_PWMSR_CMP_MASK (0x20U) #define PWM_PWMSR_CMP_SHIFT (5U) /*! CMP - CMP * 0b0..Compare event not occurred * 0b1..Compare event occurred */ #define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK) #define PWM_PWMSR_FWE_MASK (0x40U) #define PWM_PWMSR_FWE_SHIFT (6U) /*! FWE - FWE * 0b0..FIFO write error not occurred * 0b1..FIFO write error occurred */ #define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK) /*! @} */ /*! @name PWMIR - PWM Interrupt Register */ /*! @{ */ #define PWM_PWMIR_FIE_MASK (0x1U) #define PWM_PWMIR_FIE_SHIFT (0U) /*! FIE - FIE * 0b0..FIFO Empty interrupt disabled * 0b1..FIFO Empty interrupt enabled */ #define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK) #define PWM_PWMIR_RIE_MASK (0x2U) #define PWM_PWMIR_RIE_SHIFT (1U) /*! RIE - RIE * 0b0..Roll-over interrupt not enabled * 0b1..Roll-over Interrupt enabled */ #define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK) #define PWM_PWMIR_CIE_MASK (0x4U) #define PWM_PWMIR_CIE_SHIFT (2U) /*! CIE - CIE * 0b0..Compare Interrupt not enabled * 0b1..Compare Interrupt enabled */ #define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK) /*! @} */ /*! @name PWMSAR - PWM Sample Register */ /*! @{ */ #define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU) #define PWM_PWMSAR_SAMPLE_SHIFT (0U) /*! SAMPLE - SAMPLE */ #define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK) /*! @} */ /*! @name PWMPR - PWM Period Register */ /*! @{ */ #define PWM_PWMPR_PERIOD_MASK (0xFFFFU) #define PWM_PWMPR_PERIOD_SHIFT (0U) /*! PERIOD - PERIOD */ #define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK) /*! @} */ /*! @name PWMCNR - PWM Counter Register */ /*! @{ */ #define PWM_PWMCNR_COUNT_MASK (0xFFFFU) #define PWM_PWMCNR_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK) /*! @} */ /*! * @} */ /* end of group PWM_Register_Masks */ /* PWM - Peripheral instance base addresses */ /** Peripheral ADMA__PWM base address */ #define ADMA__PWM_BASE (0x5A190000u) /** Peripheral ADMA__PWM base pointer */ #define ADMA__PWM ((PWM_Type *)ADMA__PWM_BASE) /** Peripheral CI_PI__PWM base address */ #define CI_PI__PWM_BASE (0x58264000u) /** Peripheral CI_PI__PWM base pointer */ #define CI_PI__PWM ((PWM_Type *)CI_PI__PWM_BASE) /** Peripheral DI_MIPI_DSI_LVDS_0__PWM base address */ #define DI_MIPI_DSI_LVDS_0__PWM_BASE (0x56224000u) /** Peripheral DI_MIPI_DSI_LVDS_0__PWM base pointer */ #define DI_MIPI_DSI_LVDS_0__PWM ((PWM_Type *)DI_MIPI_DSI_LVDS_0__PWM_BASE) /** Peripheral DI_MIPI_DSI_LVDS_1__PWM base address */ #define DI_MIPI_DSI_LVDS_1__PWM_BASE (0x56244000u) /** Peripheral DI_MIPI_DSI_LVDS_1__PWM base pointer */ #define DI_MIPI_DSI_LVDS_1__PWM ((PWM_Type *)DI_MIPI_DSI_LVDS_1__PWM_BASE) /** Peripheral LSIO__PWM0 base address */ #define LSIO__PWM0_BASE (0x5D000000u) /** Peripheral LSIO__PWM0 base pointer */ #define LSIO__PWM0 ((PWM_Type *)LSIO__PWM0_BASE) /** Peripheral LSIO__PWM1 base address */ #define LSIO__PWM1_BASE (0x5D010000u) /** Peripheral LSIO__PWM1 base pointer */ #define LSIO__PWM1 ((PWM_Type *)LSIO__PWM1_BASE) /** Peripheral LSIO__PWM2 base address */ #define LSIO__PWM2_BASE (0x5D020000u) /** Peripheral LSIO__PWM2 base pointer */ #define LSIO__PWM2 ((PWM_Type *)LSIO__PWM2_BASE) /** Peripheral LSIO__PWM3 base address */ #define LSIO__PWM3_BASE (0x5D030000u) /** Peripheral LSIO__PWM3 base pointer */ #define LSIO__PWM3 ((PWM_Type *)LSIO__PWM3_BASE) /** Peripheral LSIO__PWM4 base address */ #define LSIO__PWM4_BASE (0x5D040000u) /** Peripheral LSIO__PWM4 base pointer */ #define LSIO__PWM4 ((PWM_Type *)LSIO__PWM4_BASE) /** Peripheral LSIO__PWM5 base address */ #define LSIO__PWM5_BASE (0x5D050000u) /** Peripheral LSIO__PWM5 base pointer */ #define LSIO__PWM5 ((PWM_Type *)LSIO__PWM5_BASE) /** Peripheral LSIO__PWM6 base address */ #define LSIO__PWM6_BASE (0x5D060000u) /** Peripheral LSIO__PWM6 base pointer */ #define LSIO__PWM6 ((PWM_Type *)LSIO__PWM6_BASE) /** Peripheral LSIO__PWM7 base address */ #define LSIO__PWM7_BASE (0x5D070000u) /** Peripheral LSIO__PWM7 base pointer */ #define LSIO__PWM7 ((PWM_Type *)LSIO__PWM7_BASE) /** Peripheral MIPI_CSI__PWM base address */ #define MIPI_CSI__PWM_BASE (0x58224000u) /** Peripheral MIPI_CSI__PWM base pointer */ #define MIPI_CSI__PWM ((PWM_Type *)MIPI_CSI__PWM_BASE) /** Array initializer of PWM peripheral base addresses */ #define PWM_BASE_ADDRS { ADMA__PWM_BASE, CI_PI__PWM_BASE, DI_MIPI_DSI_LVDS_0__PWM_BASE, DI_MIPI_DSI_LVDS_1__PWM_BASE, LSIO__PWM0_BASE, LSIO__PWM1_BASE, LSIO__PWM2_BASE, LSIO__PWM3_BASE, LSIO__PWM4_BASE, LSIO__PWM5_BASE, LSIO__PWM6_BASE, LSIO__PWM7_BASE, MIPI_CSI__PWM_BASE } /** Array initializer of PWM peripheral base pointers */ #define PWM_BASE_PTRS { ADMA__PWM, CI_PI__PWM, DI_MIPI_DSI_LVDS_0__PWM, DI_MIPI_DSI_LVDS_1__PWM, LSIO__PWM0, LSIO__PWM1, LSIO__PWM2, LSIO__PWM3, LSIO__PWM4, LSIO__PWM5, LSIO__PWM6, LSIO__PWM7, MIPI_CSI__PWM } /** Interrupt vectors for the PWM peripheral type */ #define PWM_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, LSIO_PWM0_INT_IRQn, LSIO_PWM1_INT_IRQn, LSIO_PWM2_INT_IRQn, LSIO_PWM3_INT_IRQn, LSIO_PWM4_INT_IRQn, LSIO_PWM5_INT_IRQn, LSIO_PWM6_INT_IRQn, LSIO_PWM7_INT_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group PWM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RGPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RGPIO_Peripheral_Access_Layer RGPIO Peripheral Access Layer * @{ */ /** RGPIO - Register Layout Typedef */ typedef struct { __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ } RGPIO_Type; /* ---------------------------------------------------------------------------- -- RGPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RGPIO_Register_Masks RGPIO Register Masks * @{ */ /*! @name PDOR - Port Data Output Register */ /*! @{ */ #define RGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) #define RGPIO_PDOR_PDO_SHIFT (0U) /*! PDO - Port Data Output */ #define RGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO_SHIFT)) & RGPIO_PDOR_PDO_MASK) /*! @} */ /*! @name PSOR - Port Set Output Register */ /*! @{ */ #define RGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) #define RGPIO_PSOR_PTSO_SHIFT (0U) /*! PTSO - Port Set Output */ #define RGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO_SHIFT)) & RGPIO_PSOR_PTSO_MASK) /*! @} */ /*! @name PCOR - Port Clear Output Register */ /*! @{ */ #define RGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) #define RGPIO_PCOR_PTCO_SHIFT (0U) /*! PTCO - Port Clear Output */ #define RGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO_SHIFT)) & RGPIO_PCOR_PTCO_MASK) /*! @} */ /*! @name PTOR - Port Toggle Output Register */ /*! @{ */ #define RGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) #define RGPIO_PTOR_PTTO_SHIFT (0U) /*! PTTO - Port Toggle Output */ #define RGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO_SHIFT)) & RGPIO_PTOR_PTTO_MASK) /*! @} */ /*! @name PDIR - Port Data Input Register */ /*! @{ */ #define RGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) #define RGPIO_PDIR_PDI_SHIFT (0U) /*! PDI - Port Data Input */ #define RGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI_SHIFT)) & RGPIO_PDIR_PDI_MASK) /*! @} */ /*! @name PDDR - Port Data Direction Register */ /*! @{ */ #define RGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) #define RGPIO_PDDR_PDD_SHIFT (0U) /*! PDD - Port Data Direction */ #define RGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD_SHIFT)) & RGPIO_PDDR_PDD_MASK) /*! @} */ /*! * @} */ /* end of group RGPIO_Register_Masks */ /* RGPIO - Peripheral instance base addresses */ /** Peripheral CM4__RGPIO base address */ #define CM4__RGPIO_BASE (0x410F0000u) /** Peripheral CM4__RGPIO base pointer */ #define CM4__RGPIO ((RGPIO_Type *)CM4__RGPIO_BASE) /** Peripheral SCU__RGPIO base address */ #define SCU__RGPIO_BASE (0x330F0000u) /** Peripheral SCU__RGPIO base pointer */ #define SCU__RGPIO ((RGPIO_Type *)SCU__RGPIO_BASE) /** Array initializer of RGPIO peripheral base addresses */ #define RGPIO_BASE_ADDRS { CM4__RGPIO_BASE, SCU__RGPIO_BASE } /** Array initializer of RGPIO peripheral base pointers */ #define RGPIO_BASE_PTRS { CM4__RGPIO, SCU__RGPIO } /*! * @} */ /* end of group RGPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ROMCP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ROMCP_Peripheral_Access_Layer ROMCP Peripheral Access Layer * @{ */ /** ROMCP - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[212]; __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_1[200]; __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ } ROMCP_Type; /* ---------------------------------------------------------------------------- -- ROMCP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ROMCP_Register_Masks ROMCP Register Masks * @{ */ /*! @name ROMPATCHD - ROMC Data Registers */ /*! @{ */ #define ROMCP_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) #define ROMCP_ROMPATCHD_DATAX_SHIFT (0U) /*! DATAX - DATAX */ #define ROMCP_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHD_DATAX_SHIFT)) & ROMCP_ROMPATCHD_DATAX_MASK) /*! @} */ /* The count of ROMCP_ROMPATCHD */ #define ROMCP_ROMPATCHD_COUNT (8U) /*! @name ROMPATCHCNTL - ROMC Control Register */ /*! @{ */ #define ROMCP_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) #define ROMCP_ROMPATCHCNTL_DATAFIX_SHIFT (0U) /*! DATAFIX - DATAFIX * 0b00000000..Address comparator triggers a opcode patch * 0b00000001..Address comparator triggers a data fix */ #define ROMCP_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX_MASK) #define ROMCP_ROMPATCHCNTL_DIS_MASK (0x20000000U) #define ROMCP_ROMPATCHCNTL_DIS_SHIFT (29U) /*! DIS - DIS * 0b0..Does not affect any ROMC functions (default) * 0b1..Disable all ROMC functions: data fixing, and opcode patching */ #define ROMCP_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DIS_SHIFT)) & ROMCP_ROMPATCHCNTL_DIS_MASK) /*! @} */ /*! @name ROMPATCHENL - ROMC Enable Register Low */ /*! @{ */ #define ROMCP_ROMPATCHENL_ENABLE_MASK (0xFFFFU) #define ROMCP_ROMPATCHENL_ENABLE_SHIFT (0U) /*! ENABLE - ENABLE * 0b0000000000000000..Address comparator disabled * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address */ #define ROMCP_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE_MASK) /*! @} */ /*! @name ROMPATCHA - ROMC Address Registers */ /*! @{ */ #define ROMCP_ROMPATCHA_THUMBX_MASK (0x1U) #define ROMCP_ROMPATCHA_THUMBX_SHIFT (0U) /*! THUMBX - THUMBX * 0b0..ARM patch * 0b1..THUMB patch (ignore if data fix) */ #define ROMCP_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_THUMBX_SHIFT)) & ROMCP_ROMPATCHA_THUMBX_MASK) #define ROMCP_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) #define ROMCP_ROMPATCHA_ADDRX_SHIFT (1U) /*! ADDRX - ADDRX */ #define ROMCP_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_ADDRX_SHIFT)) & ROMCP_ROMPATCHA_ADDRX_MASK) /*! @} */ /* The count of ROMCP_ROMPATCHA */ #define ROMCP_ROMPATCHA_COUNT (16U) /*! @name ROMPATCHSR - ROMC Status Register */ /*! @{ */ #define ROMCP_ROMPATCHSR_SOURCE_MASK (0x3FU) #define ROMCP_ROMPATCHSR_SOURCE_SHIFT (0U) /*! SOURCE - SOURCE * 0b000000..Address Comparator 0 matched * 0b000001..Address Comparator 1 matched * 0b001111..Address Comparator 15 matched */ #define ROMCP_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SOURCE_SHIFT)) & ROMCP_ROMPATCHSR_SOURCE_MASK) #define ROMCP_ROMPATCHSR_SW_MASK (0x20000U) #define ROMCP_ROMPATCHSR_SW_SHIFT (17U) /*! SW - SW * 0b0..no event or comparator collisions * 0b1..a collision has occurred */ #define ROMCP_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SW_SHIFT)) & ROMCP_ROMPATCHSR_SW_MASK) /*! @} */ /*! * @} */ /* end of group ROMCP_Register_Masks */ /* ROMCP - Peripheral instance base addresses */ /** Peripheral SCU__ROMCP base address */ #define SCU__ROMCP_BASE (0x32060000u) /** Peripheral SCU__ROMCP base pointer */ #define SCU__ROMCP ((ROMCP_Type *)SCU__ROMCP_BASE) /** Array initializer of ROMCP peripheral base addresses */ #define ROMCP_BASE_ADDRS { SCU__ROMCP_BASE } /** Array initializer of ROMCP peripheral base pointers */ #define ROMCP_BASE_PTRS { SCU__ROMCP } /*! * @} */ /* end of group ROMCP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SEMA42 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer * @{ */ /** SEMA42 - Register Layout Typedef */ typedef struct { __IO uint8_t GATE3; /**< Gate Register, offset: 0x0 */ __IO uint8_t GATE2; /**< Gate Register, offset: 0x1 */ __IO uint8_t GATE1; /**< Gate Register, offset: 0x2 */ __IO uint8_t GATE0; /**< Gate Register, offset: 0x3 */ __IO uint8_t GATE7; /**< Gate Register, offset: 0x4 */ __IO uint8_t GATE6; /**< Gate Register, offset: 0x5 */ __IO uint8_t GATE5; /**< Gate Register, offset: 0x6 */ __IO uint8_t GATE4; /**< Gate Register, offset: 0x7 */ __IO uint8_t GATE11; /**< Gate Register, offset: 0x8 */ __IO uint8_t GATE10; /**< Gate Register, offset: 0x9 */ __IO uint8_t GATE9; /**< Gate Register, offset: 0xA */ __IO uint8_t GATE8; /**< Gate Register, offset: 0xB */ __IO uint8_t GATE15; /**< Gate Register, offset: 0xC */ __IO uint8_t GATE14; /**< Gate Register, offset: 0xD */ __IO uint8_t GATE13; /**< Gate Register, offset: 0xE */ __IO uint8_t GATE12; /**< Gate Register, offset: 0xF */ uint8_t RESERVED_0[50]; union { /* offset: 0x42 */ __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ }; } SEMA42_Type; /* ---------------------------------------------------------------------------- -- SEMA42 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks * @{ */ /*! @name GATE3 - Gate Register */ /*! @{ */ #define SEMA42_GATE3_GTFSM_MASK (0xFU) #define SEMA42_GATE3_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK) /*! @} */ /*! @name GATE2 - Gate Register */ /*! @{ */ #define SEMA42_GATE2_GTFSM_MASK (0xFU) #define SEMA42_GATE2_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK) /*! @} */ /*! @name GATE1 - Gate Register */ /*! @{ */ #define SEMA42_GATE1_GTFSM_MASK (0xFU) #define SEMA42_GATE1_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK) /*! @} */ /*! @name GATE0 - Gate Register */ /*! @{ */ #define SEMA42_GATE0_GTFSM_MASK (0xFU) #define SEMA42_GATE0_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK) /*! @} */ /*! @name GATE7 - Gate Register */ /*! @{ */ #define SEMA42_GATE7_GTFSM_MASK (0xFU) #define SEMA42_GATE7_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK) /*! @} */ /*! @name GATE6 - Gate Register */ /*! @{ */ #define SEMA42_GATE6_GTFSM_MASK (0xFU) #define SEMA42_GATE6_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK) /*! @} */ /*! @name GATE5 - Gate Register */ /*! @{ */ #define SEMA42_GATE5_GTFSM_MASK (0xFU) #define SEMA42_GATE5_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK) /*! @} */ /*! @name GATE4 - Gate Register */ /*! @{ */ #define SEMA42_GATE4_GTFSM_MASK (0xFU) #define SEMA42_GATE4_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK) /*! @} */ /*! @name GATE11 - Gate Register */ /*! @{ */ #define SEMA42_GATE11_GTFSM_MASK (0xFU) #define SEMA42_GATE11_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK) /*! @} */ /*! @name GATE10 - Gate Register */ /*! @{ */ #define SEMA42_GATE10_GTFSM_MASK (0xFU) #define SEMA42_GATE10_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK) /*! @} */ /*! @name GATE9 - Gate Register */ /*! @{ */ #define SEMA42_GATE9_GTFSM_MASK (0xFU) #define SEMA42_GATE9_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK) /*! @} */ /*! @name GATE8 - Gate Register */ /*! @{ */ #define SEMA42_GATE8_GTFSM_MASK (0xFU) #define SEMA42_GATE8_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK) /*! @} */ /*! @name GATE15 - Gate Register */ /*! @{ */ #define SEMA42_GATE15_GTFSM_MASK (0xFU) #define SEMA42_GATE15_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK) /*! @} */ /*! @name GATE14 - Gate Register */ /*! @{ */ #define SEMA42_GATE14_GTFSM_MASK (0xFU) #define SEMA42_GATE14_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK) /*! @} */ /*! @name GATE13 - Gate Register */ /*! @{ */ #define SEMA42_GATE13_GTFSM_MASK (0xFU) #define SEMA42_GATE13_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK) /*! @} */ /*! @name GATE12 - Gate Register */ /*! @{ */ #define SEMA42_GATE12_GTFSM_MASK (0xFU) #define SEMA42_GATE12_GTFSM_SHIFT (0U) /*! GTFSM - Gate finite state machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK) /*! @} */ /*! @name RSTGT_R - Reset Gate Read */ /*! @{ */ #define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU) #define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset gate number */ #define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK) #define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) #define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U) /*! RSTGMS - Reset gate domain */ #define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK) #define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U) #define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U) /*! RSTGSM - Reset gate finite state machine * 0b00..Idle, waiting for the first data pattern write. * 0b01..Waiting for the second data pattern write * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, * this machine returns to the idle (waiting for first data pattern write) state. * 0b11..This state encoding is never used and therefore reserved. */ #define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK) #define SEMA42_RSTGT_R_ROZ_MASK (0xC000U) #define SEMA42_RSTGT_R_ROZ_SHIFT (14U) /*! ROZ - ROZ */ #define SEMA42_RSTGT_R_ROZ(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK) /*! @} */ /*! @name RSTGT_W - Reset Gate Write */ /*! @{ */ #define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU) #define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset gate number */ #define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK) #define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U) #define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U) /*! RSTGDP - Reset gate data pattern */ #define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK) /*! @} */ /*! * @} */ /* end of group SEMA42_Register_Masks */ /* SEMA42 - Peripheral instance base addresses */ /** Peripheral CM4__SEMA42 base address */ #define CM4__SEMA42_BASE (0x411B0000u) /** Peripheral CM4__SEMA42 base pointer */ #define CM4__SEMA42 ((SEMA42_Type *)CM4__SEMA42_BASE) /** Peripheral SCU__SEMA42 base address */ #define SCU__SEMA42_BASE (0x331B0000u) /** Peripheral SCU__SEMA42 base pointer */ #define SCU__SEMA42 ((SEMA42_Type *)SCU__SEMA42_BASE) /** Array initializer of SEMA42 peripheral base addresses */ #define SEMA42_BASE_ADDRS { CM4__SEMA42_BASE, SCU__SEMA42_BASE } /** Array initializer of SEMA42 peripheral base pointers */ #define SEMA42_BASE_PTRS { CM4__SEMA42, SCU__SEMA42 } /*! * @} */ /* end of group SEMA42_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SPDIF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer * @{ */ /** SPDIF - Register Layout Typedef */ typedef struct { __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ union { /* offset: 0x10 */ __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ }; __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ uint8_t RESERVED_0[8]; __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ uint8_t RESERVED_1[8]; __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ } SPDIF_Type; /* ---------------------------------------------------------------------------- -- SPDIF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPDIF_Register_Masks SPDIF Register Masks * @{ */ /*! @name SCR - SPDIF Configuration Register */ /*! @{ */ #define SPDIF_SCR_USRC_SEL_MASK (0x3U) #define SPDIF_SCR_USRC_SEL_SHIFT (0U) /*! USrc_Sel - USrc_Sel * 0b00..No embedded U channel * 0b01..U channel from SPDIF receive block (CD mode) * 0b10..Reserved * 0b11..U channel from on chip transmitter */ #define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) #define SPDIF_SCR_TXSEL_MASK (0x1CU) #define SPDIF_SCR_TXSEL_SHIFT (2U) /*! TxSel - TxSel * 0b000..Off and output 0 * 0b001..Feed-through SPDIFIN * 0b101..Tx Normal operation */ #define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) #define SPDIF_SCR_VALCTRL_MASK (0x20U) #define SPDIF_SCR_VALCTRL_SHIFT (5U) /*! ValCtrl - ValCtrl * 0b0..Outgoing Validity always set * 0b1..Outgoing Validity always clear */ #define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) #define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) #define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) /*! DMA_TX_En - DMA_TX_En */ #define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) #define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) #define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) /*! DMA_Rx_En - DMA_Rx_En */ #define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) #define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) #define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) /*! TxFIFO_Ctrl - TxFIFO_Ctrl * 0b00..Send out digital zero on SPDIF Tx * 0b01..Tx Normal operation * 0b10..Reset to 1 sample remaining * 0b11..Reserved */ #define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) #define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) #define SPDIF_SCR_SOFT_RESET_SHIFT (12U) /*! soft_reset - soft_reset */ #define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) #define SPDIF_SCR_LOW_POWER_MASK (0x2000U) #define SPDIF_SCR_LOW_POWER_SHIFT (13U) /*! LOW_POWER - LOW_POWER */ #define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) /*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs */ #define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) #define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) #define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) /*! TxAutoSync - TxAutoSync * 0b0..Tx FIFO auto sync off * 0b1..Tx FIFO auto sync on */ #define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) #define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) #define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) /*! RxAutoSync - RxAutoSync * 0b0..Rx FIFO auto sync off * 0b1..RxFIFO auto sync on */ #define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) #define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) /*! RxFIFOFull_Sel - RxFIFOFull_Sel * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO */ #define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) #define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) #define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) /*! RxFIFO_Rst - RxFIFO_Rst * 0b0..Normal operation * 0b1..Reset register to 1 sample remaining */ #define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) #define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) /*! RxFIFO_Off_On - RxFIFO_Off_On * 0b0..SPDIF Rx FIFO is on * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface */ #define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) #define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) #define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) /*! RxFIFO_Ctrl - RxFIFO_Ctrl * 0b0..Normal operation * 0b1..Always read zero from Rx data register */ #define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) /*! @} */ /*! @name SRCD - CDText Control Register */ /*! @{ */ #define SPDIF_SRCD_USYNCMODE_MASK (0x2U) #define SPDIF_SRCD_USYNCMODE_SHIFT (1U) /*! USyncMode - USyncMode * 0b0..Non-CD data * 0b1..CD user channel subcode */ #define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) /*! @} */ /*! @name SRPC - PhaseConfig Register */ /*! @{ */ #define SPDIF_SRPC_GAINSEL_MASK (0x38U) #define SPDIF_SRPC_GAINSEL_SHIFT (3U) /*! GainSel - GainSel * 0b000..24*(2**10) * 0b001..16*(2**10) * 0b010..12*(2**10) * 0b011..8*(2**10) * 0b100..6*(2**10) * 0b101..4*(2**10) * 0b110..3*(2**10) */ #define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) #define SPDIF_SRPC_LOCK_MASK (0x40U) #define SPDIF_SRPC_LOCK_SHIFT (6U) /*! LOCK - LOCK */ #define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) #define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) #define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) /*! ClkSrc_Sel - ClkSrc_Sel * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK * 0b0101..REF_CLK_32K (XTALOSC) * 0b0110..tx_clk (SPDIF0_CLK_ROOT) * 0b1000..SPDIF_EXT_CLK */ #define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) /*! @} */ /*! @name SIE - InterruptEn Register */ /*! @{ */ #define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) /*! RxFIFOFul - RxFIFOFul */ #define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) #define SPDIF_SIE_TXEM_MASK (0x2U) #define SPDIF_SIE_TXEM_SHIFT (1U) /*! TxEm - TxEm */ #define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) #define SPDIF_SIE_LOCKLOSS_MASK (0x4U) #define SPDIF_SIE_LOCKLOSS_SHIFT (2U) /*! LockLoss - LockLoss */ #define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) #define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) #define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) /*! RxFIFOResyn - RxFIFOResyn */ #define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) #define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) #define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) /*! RxFIFOUnOv - RxFIFOUnOv */ #define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) #define SPDIF_SIE_UQERR_MASK (0x20U) #define SPDIF_SIE_UQERR_SHIFT (5U) /*! UQErr - UQErr */ #define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) #define SPDIF_SIE_UQSYNC_MASK (0x40U) #define SPDIF_SIE_UQSYNC_SHIFT (6U) /*! UQSync - UQSync */ #define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) #define SPDIF_SIE_QRXOV_MASK (0x80U) #define SPDIF_SIE_QRXOV_SHIFT (7U) /*! QRxOv - QRxOv */ #define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) #define SPDIF_SIE_QRXFUL_MASK (0x100U) #define SPDIF_SIE_QRXFUL_SHIFT (8U) /*! QRxFul - QRxFul */ #define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) #define SPDIF_SIE_URXOV_MASK (0x200U) #define SPDIF_SIE_URXOV_SHIFT (9U) /*! URxOv - URxOv */ #define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) #define SPDIF_SIE_URXFUL_MASK (0x400U) #define SPDIF_SIE_URXFUL_SHIFT (10U) /*! URxFul - URxFul */ #define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) #define SPDIF_SIE_BITERR_MASK (0x4000U) #define SPDIF_SIE_BITERR_SHIFT (14U) /*! BitErr - BitErr */ #define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) #define SPDIF_SIE_SYMERR_MASK (0x8000U) #define SPDIF_SIE_SYMERR_SHIFT (15U) /*! SymErr - SymErr */ #define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) #define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) #define SPDIF_SIE_VALNOGOOD_SHIFT (16U) /*! ValNoGood - ValNoGood */ #define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) #define SPDIF_SIE_CNEW_MASK (0x20000U) #define SPDIF_SIE_CNEW_SHIFT (17U) /*! CNew - CNew */ #define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) #define SPDIF_SIE_TXRESYN_MASK (0x40000U) #define SPDIF_SIE_TXRESYN_SHIFT (18U) /*! TxResyn - TxResyn */ #define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) #define SPDIF_SIE_TXUNOV_MASK (0x80000U) #define SPDIF_SIE_TXUNOV_SHIFT (19U) /*! TxUnOv - TxUnOv */ #define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) #define SPDIF_SIE_LOCK_MASK (0x100000U) #define SPDIF_SIE_LOCK_SHIFT (20U) /*! Lock - Lock */ #define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) /*! @} */ /*! @name SIC - InterruptClear Register */ /*! @{ */ #define SPDIF_SIC_LOCKLOSS_MASK (0x4U) #define SPDIF_SIC_LOCKLOSS_SHIFT (2U) /*! LockLoss - LockLoss */ #define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) #define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) #define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) /*! RxFIFOResyn - RxFIFOResyn */ #define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) #define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) #define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) /*! RxFIFOUnOv - RxFIFOUnOv */ #define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) #define SPDIF_SIC_UQERR_MASK (0x20U) #define SPDIF_SIC_UQERR_SHIFT (5U) /*! UQErr - UQErr */ #define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) #define SPDIF_SIC_UQSYNC_MASK (0x40U) #define SPDIF_SIC_UQSYNC_SHIFT (6U) /*! UQSync - UQSync */ #define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) #define SPDIF_SIC_QRXOV_MASK (0x80U) #define SPDIF_SIC_QRXOV_SHIFT (7U) /*! QRxOv - QRxOv */ #define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) #define SPDIF_SIC_URXOV_MASK (0x200U) #define SPDIF_SIC_URXOV_SHIFT (9U) /*! URxOv - URxOv */ #define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) #define SPDIF_SIC_BITERR_MASK (0x4000U) #define SPDIF_SIC_BITERR_SHIFT (14U) /*! BitErr - BitErr */ #define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) #define SPDIF_SIC_SYMERR_MASK (0x8000U) #define SPDIF_SIC_SYMERR_SHIFT (15U) /*! SymErr - SymErr */ #define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) #define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) #define SPDIF_SIC_VALNOGOOD_SHIFT (16U) /*! ValNoGood - ValNoGood */ #define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) #define SPDIF_SIC_CNEW_MASK (0x20000U) #define SPDIF_SIC_CNEW_SHIFT (17U) /*! CNew - CNew */ #define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) #define SPDIF_SIC_TXRESYN_MASK (0x40000U) #define SPDIF_SIC_TXRESYN_SHIFT (18U) /*! TxResyn - TxResyn */ #define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) #define SPDIF_SIC_TXUNOV_MASK (0x80000U) #define SPDIF_SIC_TXUNOV_SHIFT (19U) /*! TxUnOv - TxUnOv */ #define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) #define SPDIF_SIC_LOCK_MASK (0x100000U) #define SPDIF_SIC_LOCK_SHIFT (20U) /*! Lock - Lock */ #define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) /*! @} */ /*! @name SIS - InterruptStat Register */ /*! @{ */ #define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) /*! RxFIFOFul - RxFIFOFul */ #define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) #define SPDIF_SIS_TXEM_MASK (0x2U) #define SPDIF_SIS_TXEM_SHIFT (1U) /*! TxEm - TxEm */ #define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) #define SPDIF_SIS_LOCKLOSS_MASK (0x4U) #define SPDIF_SIS_LOCKLOSS_SHIFT (2U) /*! LockLoss - LockLoss */ #define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) #define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) #define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) /*! RxFIFOResyn - RxFIFOResyn */ #define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) #define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) #define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) /*! RxFIFOUnOv - RxFIFOUnOv */ #define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) #define SPDIF_SIS_UQERR_MASK (0x20U) #define SPDIF_SIS_UQERR_SHIFT (5U) /*! UQErr - UQErr */ #define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) #define SPDIF_SIS_UQSYNC_MASK (0x40U) #define SPDIF_SIS_UQSYNC_SHIFT (6U) /*! UQSync - UQSync */ #define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) #define SPDIF_SIS_QRXOV_MASK (0x80U) #define SPDIF_SIS_QRXOV_SHIFT (7U) /*! QRxOv - QRxOv */ #define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) #define SPDIF_SIS_QRXFUL_MASK (0x100U) #define SPDIF_SIS_QRXFUL_SHIFT (8U) /*! QRxFul - QRxFul */ #define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) #define SPDIF_SIS_URXOV_MASK (0x200U) #define SPDIF_SIS_URXOV_SHIFT (9U) /*! URxOv - URxOv */ #define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) #define SPDIF_SIS_URXFUL_MASK (0x400U) #define SPDIF_SIS_URXFUL_SHIFT (10U) /*! URxFul - URxFul */ #define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) #define SPDIF_SIS_BITERR_MASK (0x4000U) #define SPDIF_SIS_BITERR_SHIFT (14U) /*! BitErr - BitErr */ #define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) #define SPDIF_SIS_SYMERR_MASK (0x8000U) #define SPDIF_SIS_SYMERR_SHIFT (15U) /*! SymErr - SymErr */ #define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) #define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) #define SPDIF_SIS_VALNOGOOD_SHIFT (16U) /*! ValNoGood - ValNoGood */ #define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) #define SPDIF_SIS_CNEW_MASK (0x20000U) #define SPDIF_SIS_CNEW_SHIFT (17U) /*! CNew - CNew */ #define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) #define SPDIF_SIS_TXRESYN_MASK (0x40000U) #define SPDIF_SIS_TXRESYN_SHIFT (18U) /*! TxResyn - TxResyn */ #define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) #define SPDIF_SIS_TXUNOV_MASK (0x80000U) #define SPDIF_SIS_TXUNOV_SHIFT (19U) /*! TxUnOv - TxUnOv */ #define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) #define SPDIF_SIS_LOCK_MASK (0x100000U) #define SPDIF_SIS_LOCK_SHIFT (20U) /*! Lock - Lock */ #define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) /*! @} */ /*! @name SRL - SPDIFRxLeft Register */ /*! @{ */ #define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_SRL_RXDATALEFT_SHIFT (0U) /*! RxDataLeft - RxDataLeft */ #define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) /*! @} */ /*! @name SRR - SPDIFRxRight Register */ /*! @{ */ #define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) /*! RxDataRight - RxDataRight */ #define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) /*! @} */ /*! @name SRCSH - SPDIFRxCChannel_h Register */ /*! @{ */ #define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) /*! RxCChannel_h - RxCChannel_h */ #define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) /*! @} */ /*! @name SRCSL - SPDIFRxCChannel_l Register */ /*! @{ */ #define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) /*! RxCChannel_l - RxCChannel_l */ #define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) /*! @} */ /*! @name SRU - UchannelRx Register */ /*! @{ */ #define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) /*! RxUChannel - RxUChannel */ #define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) /*! @} */ /*! @name SRQ - QchannelRx Register */ /*! @{ */ #define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) /*! RxQChannel - RxQChannel */ #define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) /*! @} */ /*! @name STL - SPDIFTxLeft Register */ /*! @{ */ #define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_STL_TXDATALEFT_SHIFT (0U) /*! TxDataLeft - TxDataLeft */ #define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) /*! @} */ /*! @name STR - SPDIFTxRight Register */ /*! @{ */ #define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_STR_TXDATARIGHT_SHIFT (0U) /*! TxDataRight - TxDataRight */ #define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) /*! @} */ /*! @name STCSCH - SPDIFTxCChannelCons_h Register */ /*! @{ */ #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) /*! TxCChannelCons_h - TxCChannelCons_h */ #define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) /*! @} */ /*! @name STCSCL - SPDIFTxCChannelCons_l Register */ /*! @{ */ #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) /*! TxCChannelCons_l - TxCChannelCons_l */ #define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) /*! @} */ /*! @name SRFM - FreqMeas Register */ /*! @{ */ #define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) #define SPDIF_SRFM_FREQMEAS_SHIFT (0U) /*! FreqMeas - FreqMeas */ #define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) /*! @} */ /*! @name STC - SPDIFTxClk Register */ /*! @{ */ #define SPDIF_STC_TXCLK_DF_MASK (0x7FU) #define SPDIF_STC_TXCLK_DF_SHIFT (0U) /*! TxClk_DF - TxClk_DF * 0b0000000..divider factor is 1 * 0b0000001..divider factor is 2 * 0b1111111..divider factor is 128 */ #define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) #define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) /*! tx_all_clk_en - tx_all_clk_en * 0b0..disable transfer clock. * 0b1..enable transfer clock. */ #define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) #define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) #define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) /*! TxClk_Source - TxClk_Source * 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock) * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.) * 0b011..SPDIF_EXT_CLK, from pads * 0b101..ipg_clk input (frequency divided) */ #define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) #define SPDIF_STC_SYSCLK_DF_SHIFT (11U) /*! SYSCLK_DF - SYSCLK_DF * 0b000000000..no clock signal * 0b000000001..divider factor is 2 * 0b111111111..divider factor is 512 */ #define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) /*! @} */ /*! * @} */ /* end of group SPDIF_Register_Masks */ /* SPDIF - Peripheral instance base addresses */ /** Peripheral ADMA__SPDIF0 base address */ #define ADMA__SPDIF0_BASE (0x59020000u) /** Peripheral ADMA__SPDIF0 base pointer */ #define ADMA__SPDIF0 ((SPDIF_Type *)ADMA__SPDIF0_BASE) /** Array initializer of SPDIF peripheral base addresses */ #define SPDIF_BASE_ADDRS { ADMA__SPDIF0_BASE } /** Array initializer of SPDIF peripheral base pointers */ #define SPDIF_BASE_PTRS { ADMA__SPDIF0 } /*! * @} */ /* end of group SPDIF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TPM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer * @{ */ /** TPM - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t GLOBAL; /**< TPM Global Register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t SC; /**< Status and Control, offset: 0x10 */ __IO uint32_t CNT; /**< Counter, offset: 0x14 */ __IO uint32_t MOD; /**< Modulo, offset: 0x18 */ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */ struct { /* offset: 0x20, array step: 0x8 */ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */ } CONTROLS[6]; uint8_t RESERVED_1[20]; __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */ uint8_t RESERVED_2[4]; __IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */ __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ uint8_t RESERVED_3[4]; __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */ uint8_t RESERVED_4[4]; __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ } TPM_Type; /* ---------------------------------------------------------------------------- -- TPM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TPM_Register_Masks TPM Register Masks * @{ */ /*! @name VERID - Version ID Register */ /*! @{ */ #define TPM_VERID_FEATURE_MASK (0xFFFFU) #define TPM_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number * 0b0000000000000001..Standard feature set. * 0b0000000000000011..Standard feature set with Filter and Combine registers implemented. * 0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented. */ #define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK) #define TPM_VERID_MINOR_MASK (0xFF0000U) #define TPM_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK) #define TPM_VERID_MAJOR_MASK (0xFF000000U) #define TPM_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ #define TPM_PARAM_CHAN_MASK (0xFFU) #define TPM_PARAM_CHAN_SHIFT (0U) /*! CHAN - Channel Count */ #define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK) #define TPM_PARAM_TRIG_MASK (0xFF00U) #define TPM_PARAM_TRIG_SHIFT (8U) /*! TRIG - Trigger Count */ #define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK) #define TPM_PARAM_WIDTH_MASK (0xFF0000U) #define TPM_PARAM_WIDTH_SHIFT (16U) /*! WIDTH - Counter Width */ #define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK) /*! @} */ /*! @name GLOBAL - TPM Global Register */ /*! @{ */ #define TPM_GLOBAL_RST_MASK (0x2U) #define TPM_GLOBAL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Module is not reset. * 0b1..Module is reset. */ #define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK) /*! @} */ /*! @name SC - Status and Control */ /*! @{ */ #define TPM_SC_PS_MASK (0x7U) #define TPM_SC_PS_SHIFT (0U) /*! PS - Prescale Factor Selection * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) #define TPM_SC_CMOD_MASK (0x18U) #define TPM_SC_CMOD_SHIFT (3U) /*! CMOD - Clock Mode Selection * 0b00..TPM counter is disabled * 0b01..TPM counter increments on every TPM counter clock * 0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock * 0b11..TPM counter increments on rising edge of the selected external input trigger. */ #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) #define TPM_SC_CPWMS_MASK (0x20U) #define TPM_SC_CPWMS_SHIFT (5U) /*! CPWMS - Center-Aligned PWM Select * 0b0..TPM counter operates in up counting mode. * 0b1..TPM counter operates in up-down counting mode. */ #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) #define TPM_SC_TOIE_MASK (0x40U) #define TPM_SC_TOIE_SHIFT (6U) /*! TOIE - Timer Overflow Interrupt Enable * 0b0..Disable TOF interrupts. Use software polling or DMA request. * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. */ #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) #define TPM_SC_TOF_MASK (0x80U) #define TPM_SC_TOF_SHIFT (7U) /*! TOF - Timer Overflow Flag * 0b0..TPM counter has not overflowed. * 0b1..TPM counter has overflowed. */ #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) #define TPM_SC_DMA_MASK (0x100U) #define TPM_SC_DMA_SHIFT (8U) /*! DMA - DMA Enable * 0b0..Disables DMA transfers. * 0b1..Enables DMA transfers. */ #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) /*! @} */ /*! @name CNT - Counter */ /*! @{ */ #define TPM_CNT_COUNT_MASK (0xFFFFFFFFU) #define TPM_CNT_COUNT_SHIFT (0U) /*! COUNT - Counter value */ #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) /*! @} */ /*! @name MOD - Modulo */ /*! @{ */ #define TPM_MOD_MOD_MASK (0xFFFFFFFFU) #define TPM_MOD_MOD_SHIFT (0U) /*! MOD - Modulo value */ #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) /*! @} */ /*! @name STATUS - Capture and Compare Status */ /*! @{ */ #define TPM_STATUS_CH0F_MASK (0x1U) #define TPM_STATUS_CH0F_SHIFT (0U) /*! CH0F - Channel 0 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) #define TPM_STATUS_CH1F_MASK (0x2U) #define TPM_STATUS_CH1F_SHIFT (1U) /*! CH1F - Channel 1 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) #define TPM_STATUS_CH2F_MASK (0x4U) #define TPM_STATUS_CH2F_SHIFT (2U) /*! CH2F - Channel 2 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) #define TPM_STATUS_CH3F_MASK (0x8U) #define TPM_STATUS_CH3F_SHIFT (3U) /*! CH3F - Channel 3 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) #define TPM_STATUS_CH4F_MASK (0x10U) #define TPM_STATUS_CH4F_SHIFT (4U) /*! CH4F - Channel 4 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK) #define TPM_STATUS_CH5F_MASK (0x20U) #define TPM_STATUS_CH5F_SHIFT (5U) /*! CH5F - Channel 5 Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK) #define TPM_STATUS_TOF_MASK (0x100U) #define TPM_STATUS_TOF_SHIFT (8U) /*! TOF - Timer Overflow Flag * 0b0..TPM counter has not overflowed. * 0b1..TPM counter has overflowed. */ #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) /*! @} */ /*! @name CnSC - Channel (n) Status and Control */ /*! @{ */ #define TPM_CnSC_DMA_MASK (0x1U) #define TPM_CnSC_DMA_SHIFT (0U) /*! DMA - DMA Enable * 0b0..Disable DMA transfers. * 0b1..Enable DMA transfers. */ #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) #define TPM_CnSC_ELSA_MASK (0x4U) #define TPM_CnSC_ELSA_SHIFT (2U) /*! ELSA - Edge or Level Select */ #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) #define TPM_CnSC_ELSB_MASK (0x8U) #define TPM_CnSC_ELSB_SHIFT (3U) /*! ELSB - Edge or Level Select */ #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) #define TPM_CnSC_MSA_MASK (0x10U) #define TPM_CnSC_MSA_SHIFT (4U) /*! MSA - Channel Mode Select */ #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) #define TPM_CnSC_MSB_MASK (0x20U) #define TPM_CnSC_MSB_SHIFT (5U) /*! MSB - Channel Mode Select */ #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) #define TPM_CnSC_CHIE_MASK (0x40U) #define TPM_CnSC_CHIE_SHIFT (6U) /*! CHIE - Channel Interrupt Enable * 0b0..Disable channel interrupts. * 0b1..Enable channel interrupts. */ #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) #define TPM_CnSC_CHF_MASK (0x80U) #define TPM_CnSC_CHF_SHIFT (7U) /*! CHF - Channel Flag * 0b0..No channel event has occurred. * 0b1..A channel event has occurred. */ #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) /*! @} */ /* The count of TPM_CnSC */ #define TPM_CnSC_COUNT (6U) /*! @name CnV - Channel (n) Value */ /*! @{ */ #define TPM_CnV_VAL_MASK (0xFFFFFFFFU) #define TPM_CnV_VAL_SHIFT (0U) /*! VAL - Channel Value */ #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) /*! @} */ /* The count of TPM_CnV */ #define TPM_CnV_COUNT (6U) /*! @name COMBINE - Combine Channel Register */ /*! @{ */ #define TPM_COMBINE_COMBINE0_MASK (0x1U) #define TPM_COMBINE_COMBINE0_SHIFT (0U) /*! COMBINE0 - Combine Channels 0 and 1 * 0b0..Channels 0 and 1 are independent. * 0b1..Channels 0 and 1 are combined. */ #define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK) #define TPM_COMBINE_COMSWAP0_MASK (0x2U) #define TPM_COMBINE_COMSWAP0_SHIFT (1U) /*! COMSWAP0 - Combine Channel 0 and 1 Swap * 0b0..Even channel is used for input capture and 1st compare. * 0b1..Odd channel is used for input capture and 1st compare. */ #define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK) #define TPM_COMBINE_COMBINE1_MASK (0x100U) #define TPM_COMBINE_COMBINE1_SHIFT (8U) /*! COMBINE1 - Combine Channels 2 and 3 * 0b0..Channels 2 and 3 are independent. * 0b1..Channels 2 and 3 are combined. */ #define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK) #define TPM_COMBINE_COMSWAP1_MASK (0x200U) #define TPM_COMBINE_COMSWAP1_SHIFT (9U) /*! COMSWAP1 - Combine Channels 2 and 3 Swap * 0b0..Even channel is used for input capture and 1st compare. * 0b1..Odd channel is used for input capture and 1st compare. */ #define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK) #define TPM_COMBINE_COMBINE2_MASK (0x10000U) #define TPM_COMBINE_COMBINE2_SHIFT (16U) /*! COMBINE2 - Combine Channels 4 and 5 * 0b0..Channels 4 and 5 are independent. * 0b1..Channels 4 and 5 are combined. */ #define TPM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK) #define TPM_COMBINE_COMSWAP2_MASK (0x20000U) #define TPM_COMBINE_COMSWAP2_SHIFT (17U) /*! COMSWAP2 - Combine Channels 4 and 5 Swap * 0b0..Even channel is used for input capture and 1st compare. * 0b1..Odd channel is used for input capture and 1st compare. */ #define TPM_COMBINE_COMSWAP2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK) /*! @} */ /*! @name TRIG - Channel Trigger */ /*! @{ */ #define TPM_TRIG_TRIG0_MASK (0x1U) #define TPM_TRIG_TRIG0_SHIFT (0U) /*! TRIG0 - Channel 0 Trigger * 0b0..No effect. * 0b1..Configures trigger input 0 to be used by channel 0. */ #define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK) #define TPM_TRIG_TRIG1_MASK (0x2U) #define TPM_TRIG_TRIG1_SHIFT (1U) /*! TRIG1 - Channel 1 Trigger * 0b0..No effect. * 0b1..Configures trigger input 1 to be used by channel 1. */ #define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK) #define TPM_TRIG_TRIG2_MASK (0x4U) #define TPM_TRIG_TRIG2_SHIFT (2U) /*! TRIG2 - Channel 2 Trigger * 0b0..No effect. * 0b1..Configures trigger input 0 to be used by channel 2. */ #define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK) #define TPM_TRIG_TRIG3_MASK (0x8U) #define TPM_TRIG_TRIG3_SHIFT (3U) /*! TRIG3 - Channel 3 Trigger * 0b0..No effect. * 0b1..Configures trigger input 1 to be used by channel 3. */ #define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK) #define TPM_TRIG_TRIG4_MASK (0x10U) #define TPM_TRIG_TRIG4_SHIFT (4U) /*! TRIG4 - Channel 4 Trigger * 0b0..No effect. * 0b1..Configures trigger input 0 to be used by channel 4. */ #define TPM_TRIG_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK) #define TPM_TRIG_TRIG5_MASK (0x20U) #define TPM_TRIG_TRIG5_SHIFT (5U) /*! TRIG5 - Channel 5 Trigger * 0b0..No effect. * 0b1..Configures trigger input 1 to be used by channel 5. */ #define TPM_TRIG_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK) /*! @} */ /*! @name POL - Channel Polarity */ /*! @{ */ #define TPM_POL_POL0_MASK (0x1U) #define TPM_POL_POL0_SHIFT (0U) /*! POL0 - Channel 0 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) #define TPM_POL_POL1_MASK (0x2U) #define TPM_POL_POL1_SHIFT (1U) /*! POL1 - Channel 1 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) #define TPM_POL_POL2_MASK (0x4U) #define TPM_POL_POL2_SHIFT (2U) /*! POL2 - Channel 2 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) #define TPM_POL_POL3_MASK (0x8U) #define TPM_POL_POL3_SHIFT (3U) /*! POL3 - Channel 3 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) #define TPM_POL_POL4_MASK (0x10U) #define TPM_POL_POL4_SHIFT (4U) /*! POL4 - Channel 4 Polarity * 0b0..The channel polarity is active high * 0b1..The channel polarity is active low. */ #define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK) #define TPM_POL_POL5_MASK (0x20U) #define TPM_POL_POL5_SHIFT (5U) /*! POL5 - Channel 5 Polarity * 0b0..The channel polarity is active high. * 0b1..The channel polarity is active low. */ #define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK) /*! @} */ /*! @name FILTER - Filter Control */ /*! @{ */ #define TPM_FILTER_CH0FVAL_MASK (0xFU) #define TPM_FILTER_CH0FVAL_SHIFT (0U) /*! CH0FVAL - Channel 0 Filter Value */ #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK) #define TPM_FILTER_CH1FVAL_MASK (0xF0U) #define TPM_FILTER_CH1FVAL_SHIFT (4U) /*! CH1FVAL - Channel 1 Filter Value */ #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK) #define TPM_FILTER_CH2FVAL_MASK (0xF00U) #define TPM_FILTER_CH2FVAL_SHIFT (8U) /*! CH2FVAL - Channel 2 Filter Value */ #define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK) #define TPM_FILTER_CH3FVAL_MASK (0xF000U) #define TPM_FILTER_CH3FVAL_SHIFT (12U) /*! CH3FVAL - Channel 3 Filter Value */ #define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK) #define TPM_FILTER_CH4FVAL_MASK (0xF0000U) #define TPM_FILTER_CH4FVAL_SHIFT (16U) /*! CH4FVAL - Channel 4 Filter Value */ #define TPM_FILTER_CH4FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK) #define TPM_FILTER_CH5FVAL_MASK (0xF00000U) #define TPM_FILTER_CH5FVAL_SHIFT (20U) /*! CH5FVAL - Channel 5 Filter Value */ #define TPM_FILTER_CH5FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK) /*! @} */ /*! @name QDCTRL - Quadrature Decoder Control and Status */ /*! @{ */ #define TPM_QDCTRL_QUADEN_MASK (0x1U) #define TPM_QDCTRL_QUADEN_SHIFT (0U) /*! QUADEN - QUADEN * 0b0..Quadrature decoder mode is disabled. * 0b1..Quadrature decoder mode is enabled. */ #define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK) #define TPM_QDCTRL_TOFDIR_MASK (0x2U) #define TPM_QDCTRL_TOFDIR_SHIFT (1U) /*! TOFDIR - TOFDIR * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes * from its minimum value (zero) to its maximum value (MOD register). * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from * its maximum value (MOD register) to its minimum value (zero). */ #define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK) #define TPM_QDCTRL_QUADIR_MASK (0x4U) #define TPM_QDCTRL_QUADIR_SHIFT (2U) /*! QUADIR - Counter Direction in Quadrature Decode Mode * 0b0..Counter direction is decreasing (counter decrement). * 0b1..Counter direction is increasing (counter increment). */ #define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK) #define TPM_QDCTRL_QUADMODE_MASK (0x8U) #define TPM_QDCTRL_QUADMODE_SHIFT (3U) /*! QUADMODE - Quadrature Decoder Mode * 0b0..Phase encoding mode. * 0b1..Count and direction encoding mode. */ #define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK) /*! @} */ /*! @name CONF - Configuration */ /*! @{ */ #define TPM_CONF_DOZEEN_MASK (0x20U) #define TPM_CONF_DOZEEN_SHIFT (5U) /*! DOZEEN - Doze Enable * 0b0..Internal TPM counter continues in Doze mode. * 0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture * events are ignored, and PWM outputs are forced to their default state. */ #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) #define TPM_CONF_DBGMODE_MASK (0xC0U) #define TPM_CONF_DBGMODE_SHIFT (6U) /*! DBGMODE - Debug Mode * 0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events * are ignored, and PWM outputs are forced to their default state. * 0b11..TPM counter continues in debug mode. */ #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) #define TPM_CONF_GTBSYNC_MASK (0x100U) #define TPM_CONF_GTBSYNC_SHIFT (8U) /*! GTBSYNC - Global Time Base Synchronization * 0b0..Global timebase synchronization disabled. * 0b1..Global timebase synchronization enabled. */ #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) #define TPM_CONF_GTBEEN_MASK (0x200U) #define TPM_CONF_GTBEEN_SHIFT (9U) /*! GTBEEN - Global time base enable * 0b0..All channels use the internally generated TPM counter as their timebase * 0b1..All channels use an externally generated global timebase as their timebase */ #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) #define TPM_CONF_CSOT_MASK (0x10000U) #define TPM_CONF_CSOT_SHIFT (16U) /*! CSOT - Counter Start on Trigger * 0b0..TPM counter starts to increment immediately, once it is enabled. * 0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, * after it has been enabled or after it has stopped due to overflow. */ #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) #define TPM_CONF_CSOO_MASK (0x20000U) #define TPM_CONF_CSOO_SHIFT (17U) /*! CSOO - Counter Stop On Overflow * 0b0..TPM counter continues incrementing or decrementing after overflow * 0b1..TPM counter stops incrementing or decrementing after overflow. */ #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) #define TPM_CONF_CROT_MASK (0x40000U) #define TPM_CONF_CROT_SHIFT (18U) /*! CROT - Counter Reload On Trigger * 0b0..Counter is not reloaded due to a rising edge on the selected input trigger * 0b1..Counter is reloaded when a rising edge is detected on the selected input trigger */ #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) #define TPM_CONF_CPOT_MASK (0x80000U) #define TPM_CONF_CPOT_SHIFT (19U) /*! CPOT - Counter Pause On Trigger */ #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) #define TPM_CONF_TRGPOL_MASK (0x400000U) #define TPM_CONF_TRGPOL_SHIFT (22U) /*! TRGPOL - Trigger Polarity * 0b0..Trigger is active high. * 0b1..Trigger is active low. */ #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) #define TPM_CONF_TRGSRC_MASK (0x800000U) #define TPM_CONF_TRGSRC_SHIFT (23U) /*! TRGSRC - Trigger Source * 0b0..Trigger source selected by TRGSEL is external. * 0b1..Trigger source selected by TRGSEL is internal (channel pin input capture). */ #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) #define TPM_CONF_TRGSEL_MASK (0xF000000U) #define TPM_CONF_TRGSEL_SHIFT (24U) /*! TRGSEL - Trigger Select * 0b0001..Channel 0 pin input capture * 0b0010..Channel 1 pin input capture * 0b0011..Channel 0 or Channel 1 pin input capture * 0b0100..Channel 2 pin input capture * 0b0101..Channel 0 or Channel 2 pin input capture * 0b0110..Channel 1 or Channel 2 pin input capture * 0b0111..Channel 0 or Channel 1 or Channel 2 pin input capture * 0b1000..Channel 3 pin input capture * 0b1001..Channel 0 or Channel 3 pin input capture * 0b1010..Channel 1 or Channel 3 pin input capture * 0b1011..Channel 0 or Channel 1 or Channel 3 pin input capture * 0b1100..Channel 2 or Channel 3 pin input capture * 0b1101..Channel 0 or Channel 2 or Channel 3 pin input capture * 0b1110..Channel 1 or Channel 2 or Channel 3 pin input capture * 0b1111..Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture */ #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) /*! @} */ /*! * @} */ /* end of group TPM_Register_Masks */ /* TPM - Peripheral instance base addresses */ /** Peripheral CM4__TPM base address */ #define CM4__TPM_BASE (0x41200000u) /** Peripheral CM4__TPM base pointer */ #define CM4__TPM ((TPM_Type *)CM4__TPM_BASE) /** Peripheral SCU__TPM base address */ #define SCU__TPM_BASE (0x33200000u) /** Peripheral SCU__TPM base pointer */ #define SCU__TPM ((TPM_Type *)SCU__TPM_BASE) /** Array initializer of TPM peripheral base addresses */ #define TPM_BASE_ADDRS { CM4__TPM_BASE, SCU__TPM_BASE } /** Array initializer of TPM peripheral base pointers */ #define TPM_BASE_PTRS { CM4__TPM, SCU__TPM } /** Interrupt vectors for the TPM peripheral type */ #define TPM_IRQS { M4_TPM_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group TPM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TSTMR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer * @{ */ /** TSTMR - Register Layout Typedef */ typedef struct { __I uint32_t L; /**< Time Stamp Timer Register Low, offset: 0x0 */ __I uint32_t H; /**< Time Stamp Timer Register High, offset: 0x4 */ } TSTMR_Type; /* ---------------------------------------------------------------------------- -- TSTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TSTMR_Register_Masks TSTMR Register Masks * @{ */ /*! @name L - Time Stamp Timer Register Low */ /*! @{ */ #define TSTMR_L_VALUE_MASK (0xFFFFFFFFU) #define TSTMR_L_VALUE_SHIFT (0U) /*! VALUE - Time Stamp Timer Low */ #define TSTMR_L_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK) /*! @} */ /*! @name H - Time Stamp Timer Register High */ /*! @{ */ #define TSTMR_H_VALUE_MASK (0xFFFFFFFFU) #define TSTMR_H_VALUE_SHIFT (0U) /*! VALUE - Time Stamp Timer High */ #define TSTMR_H_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK) /*! @} */ /*! * @} */ /* end of group TSTMR_Register_Masks */ /* TSTMR - Peripheral instance base addresses */ /** Peripheral CM4__TSTMR base address */ #define CM4__TSTMR_BASE (0x414100F0u) /** Peripheral CM4__TSTMR base pointer */ #define CM4__TSTMR ((TSTMR_Type *)CM4__TSTMR_BASE) /** Peripheral SCU__TSTMR base address */ #define SCU__TSTMR_BASE (0x334100F0u) /** Peripheral SCU__TSTMR base pointer */ #define SCU__TSTMR ((TSTMR_Type *)SCU__TSTMR_BASE) /** Array initializer of TSTMR peripheral base addresses */ #define TSTMR_BASE_ADDRS { CM4__TSTMR_BASE, SCU__TSTMR_BASE } /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { CM4__TSTMR, SCU__TSTMR } /*! * @} */ /* end of group TSTMR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer * @{ */ /** USB - Register Layout Typedef */ typedef struct { __I uint32_t ID; /**< Identification register, offset: 0x0 */ __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ uint8_t RESERVED_0[104]; __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ uint8_t RESERVED_1[108]; __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ uint8_t RESERVED_2[1]; __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ uint8_t RESERVED_3[20]; __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ uint8_t RESERVED_4[2]; __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ uint8_t RESERVED_5[24]; __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ uint8_t RESERVED_6[4]; union { /* offset: 0x154 */ __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ }; union { /* offset: 0x158 */ __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ }; uint8_t RESERVED_7[4]; __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ uint8_t RESERVED_8[16]; __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ uint8_t RESERVED_9[28]; __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ } USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Masks USB Register Masks * @{ */ /*! @name ID - Identification register */ /*! @{ */ #define USB_ID_ID_MASK (0x3FU) #define USB_ID_ID_SHIFT (0U) #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) #define USB_ID_NID_MASK (0x3F00U) #define USB_ID_NID_SHIFT (8U) #define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) #define USB_ID_REVISION_MASK (0xFF0000U) #define USB_ID_REVISION_SHIFT (16U) #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) /*! @} */ /*! @name HWGENERAL - Hardware General */ /*! @{ */ #define USB_HWGENERAL_PHYW_MASK (0x30U) #define USB_HWGENERAL_PHYW_SHIFT (4U) /*! PHYW * 0b00..8 bit wide data bus Software non-programmable * 0b01..16 bit wide data bus Software non-programmable * 0b10..Reset to 8 bit wide data bus Software programmable * 0b11..Reset to 16 bit wide data bus Software programmable */ #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) #define USB_HWGENERAL_PHYM_MASK (0x1C0U) #define USB_HWGENERAL_PHYM_SHIFT (6U) /*! PHYM * 0b000..UTMI/UMTI+ * 0b001..ULPI DDR * 0b010..ULPI * 0b011..Serial Only * 0b100..Software programmable - reset to UTMI/UTMI+ * 0b101..Software programmable - reset to ULPI DDR * 0b110..Software programmable - reset to ULPI * 0b111..Software programmable - reset to Serial */ #define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) #define USB_HWGENERAL_SM_MASK (0x600U) #define USB_HWGENERAL_SM_SHIFT (9U) /*! SM * 0b00..No Serial Engine, always use parallel signalling. * 0b01..Serial Engine present, always use serial signalling for FS/LS. * 0b10..Software programmable - Reset to use parallel signalling for FS/LS * 0b11..Software programmable - Reset to use serial signalling for FS/LS */ #define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) /*! @} */ /*! @name HWHOST - Host Hardware Parameters */ /*! @{ */ #define USB_HWHOST_HC_MASK (0x1U) #define USB_HWHOST_HC_SHIFT (0U) /*! HC * 0b1..Supported * 0b0..Not supported */ #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) #define USB_HWHOST_NPORT_MASK (0xEU) #define USB_HWHOST_NPORT_SHIFT (1U) #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) /*! @} */ /*! @name HWDEVICE - Device Hardware Parameters */ /*! @{ */ #define USB_HWDEVICE_DC_MASK (0x1U) #define USB_HWDEVICE_DC_SHIFT (0U) /*! DC * 0b1..Supported * 0b0..Not supported */ #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) #define USB_HWDEVICE_DEVEP_MASK (0x3EU) #define USB_HWDEVICE_DEVEP_SHIFT (1U) #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) /*! @} */ /*! @name HWTXBUF - TX Buffer Hardware Parameters */ /*! @{ */ #define USB_HWTXBUF_TXBURST_MASK (0xFFU) #define USB_HWTXBUF_TXBURST_SHIFT (0U) #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USB_HWTXBUF_TXCHANADD_SHIFT (16U) #define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) /*! @} */ /*! @name HWRXBUF - RX Buffer Hardware Parameters */ /*! @{ */ #define USB_HWRXBUF_RXBURST_MASK (0xFFU) #define USB_HWRXBUF_RXBURST_SHIFT (0U) #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) #define USB_HWRXBUF_RXADD_MASK (0xFF00U) #define USB_HWRXBUF_RXADD_SHIFT (8U) #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) /*! @} */ /*! @name GPTIMER0LD - General Purpose Timer #0 Load */ /*! @{ */ #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER0LD_GPTLD_SHIFT (0U) #define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ /*! @{ */ #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) #define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) /*! GPTMODE * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) #define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) /*! GPTRST * 0b0..No action * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD */ #define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) /*! GPTRUN * 0b0..Stop counting * 0b1..Run */ #define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) /*! @} */ /*! @name GPTIMER1LD - General Purpose Timer #1 Load */ /*! @{ */ #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER1LD_GPTLD_SHIFT (0U) #define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ /*! @{ */ #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) #define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) #define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) /*! GPTMODE * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) #define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) /*! GPTRST * 0b0..No action * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD */ #define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) /*! GPTRUN * 0b0..Stop counting * 0b1..Run */ #define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) /*! @} */ /*! @name SBUSCFG - System Bus Config */ /*! @{ */ #define USB_SBUSCFG_AHBBRST_MASK (0x7U) #define USB_SBUSCFG_AHBBRST_SHIFT (0U) /*! AHBBRST * 0b000..Incremental burst of unspecified length only * 0b001..INCR4 burst, then single transfer * 0b010..INCR8 burst, INCR4 burst, then single transfer * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer * 0b100..Reserved, don't use * 0b101..INCR4 burst, then incremental burst of unspecified length * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length */ #define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) /*! @} */ /*! @name CAPLENGTH - Capability Registers Length */ /*! @{ */ #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) #define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) /*! @} */ /*! @name HCIVERSION - Host Controller Interface Version */ /*! @{ */ #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USB_HCIVERSION_HCIVERSION_SHIFT (0U) #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) /*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ /*! @{ */ #define USB_HCSPARAMS_N_PORTS_MASK (0xFU) #define USB_HCSPARAMS_N_PORTS_SHIFT (0U) #define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) #define USB_HCSPARAMS_PPC_MASK (0x10U) #define USB_HCSPARAMS_PPC_SHIFT (4U) #define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) #define USB_HCSPARAMS_N_PCC_MASK (0xF00U) #define USB_HCSPARAMS_N_PCC_SHIFT (8U) #define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) #define USB_HCSPARAMS_N_CC_MASK (0xF000U) #define USB_HCSPARAMS_N_CC_SHIFT (12U) /*! N_CC * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. */ #define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) #define USB_HCSPARAMS_PI_MASK (0x10000U) #define USB_HCSPARAMS_PI_SHIFT (16U) #define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) #define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) #define USB_HCSPARAMS_N_PTT_SHIFT (20U) #define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) #define USB_HCSPARAMS_N_TT_MASK (0xF000000U) #define USB_HCSPARAMS_N_TT_SHIFT (24U) #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) /*! @} */ /*! @name HCCPARAMS - Host Controller Capability Parameters */ /*! @{ */ #define USB_HCCPARAMS_ADC_MASK (0x1U) #define USB_HCCPARAMS_ADC_SHIFT (0U) #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) #define USB_HCCPARAMS_PFL_MASK (0x2U) #define USB_HCCPARAMS_PFL_SHIFT (1U) #define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) #define USB_HCCPARAMS_ASP_MASK (0x4U) #define USB_HCCPARAMS_ASP_SHIFT (2U) #define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) #define USB_HCCPARAMS_IST_MASK (0xF0U) #define USB_HCCPARAMS_IST_SHIFT (4U) #define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) #define USB_HCCPARAMS_EECP_MASK (0xFF00U) #define USB_HCCPARAMS_EECP_SHIFT (8U) #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) /*! @} */ /*! @name DCIVERSION - Device Controller Interface Version */ /*! @{ */ #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USB_DCIVERSION_DCIVERSION_SHIFT (0U) #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) /*! @} */ /*! @name DCCPARAMS - Device Controller Capability Parameters */ /*! @{ */ #define USB_DCCPARAMS_DEN_MASK (0x1FU) #define USB_DCCPARAMS_DEN_SHIFT (0U) #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) #define USB_DCCPARAMS_DC_MASK (0x80U) #define USB_DCCPARAMS_DC_SHIFT (7U) #define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) #define USB_DCCPARAMS_HC_MASK (0x100U) #define USB_DCCPARAMS_HC_SHIFT (8U) #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) /*! @} */ /*! @name USBCMD - USB Command Register */ /*! @{ */ #define USB_USBCMD_RS_MASK (0x1U) #define USB_USBCMD_RS_SHIFT (0U) #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) #define USB_USBCMD_RST_MASK (0x2U) #define USB_USBCMD_RST_SHIFT (1U) #define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) #define USB_USBCMD_FS_1_MASK (0xCU) #define USB_USBCMD_FS_1_SHIFT (2U) #define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) #define USB_USBCMD_PSE_MASK (0x10U) #define USB_USBCMD_PSE_SHIFT (4U) /*! PSE * 0b0..Do not process the Periodic Schedule * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. */ #define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) #define USB_USBCMD_ASE_MASK (0x20U) #define USB_USBCMD_ASE_SHIFT (5U) /*! ASE * 0b0..Do not process the Asynchronous Schedule. * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. */ #define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) #define USB_USBCMD_IAA_MASK (0x40U) #define USB_USBCMD_IAA_SHIFT (6U) #define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) #define USB_USBCMD_ASP_MASK (0x300U) #define USB_USBCMD_ASP_SHIFT (8U) #define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) #define USB_USBCMD_ASPE_MASK (0x800U) #define USB_USBCMD_ASPE_SHIFT (11U) #define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) #define USB_USBCMD_SUTW_MASK (0x2000U) #define USB_USBCMD_SUTW_SHIFT (13U) #define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) #define USB_USBCMD_ATDTW_MASK (0x4000U) #define USB_USBCMD_ATDTW_SHIFT (14U) #define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) #define USB_USBCMD_FS_2_MASK (0x8000U) #define USB_USBCMD_FS_2_SHIFT (15U) /*! FS_2 * 0b0..1024 elements (4096 bytes) Default value * 0b1..512 elements (2048 bytes) */ #define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) #define USB_USBCMD_ITC_MASK (0xFF0000U) #define USB_USBCMD_ITC_SHIFT (16U) /*! ITC * 0b00000000..Immediate (no threshold) * 0b00000001..1 micro-frame * 0b00000010..2 micro-frames * 0b00000100..4 micro-frames * 0b00001000..8 micro-frames * 0b00010000..16 micro-frames * 0b00100000..32 micro-frames * 0b01000000..64 micro-frames */ #define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) /*! @} */ /*! @name USBSTS - USB Status Register */ /*! @{ */ #define USB_USBSTS_UI_MASK (0x1U) #define USB_USBSTS_UI_SHIFT (0U) #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) #define USB_USBSTS_UEI_MASK (0x2U) #define USB_USBSTS_UEI_SHIFT (1U) #define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) #define USB_USBSTS_PCI_MASK (0x4U) #define USB_USBSTS_PCI_SHIFT (2U) #define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) #define USB_USBSTS_FRI_MASK (0x8U) #define USB_USBSTS_FRI_SHIFT (3U) #define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) #define USB_USBSTS_SEI_MASK (0x10U) #define USB_USBSTS_SEI_SHIFT (4U) #define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) #define USB_USBSTS_AAI_MASK (0x20U) #define USB_USBSTS_AAI_SHIFT (5U) #define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) #define USB_USBSTS_URI_MASK (0x40U) #define USB_USBSTS_URI_SHIFT (6U) #define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) #define USB_USBSTS_SRI_MASK (0x80U) #define USB_USBSTS_SRI_SHIFT (7U) #define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) #define USB_USBSTS_SLI_MASK (0x100U) #define USB_USBSTS_SLI_SHIFT (8U) #define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) #define USB_USBSTS_ULPII_MASK (0x400U) #define USB_USBSTS_ULPII_SHIFT (10U) #define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) #define USB_USBSTS_HCH_MASK (0x1000U) #define USB_USBSTS_HCH_SHIFT (12U) #define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) #define USB_USBSTS_RCL_MASK (0x2000U) #define USB_USBSTS_RCL_SHIFT (13U) #define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) #define USB_USBSTS_PS_MASK (0x4000U) #define USB_USBSTS_PS_SHIFT (14U) #define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) #define USB_USBSTS_AS_MASK (0x8000U) #define USB_USBSTS_AS_SHIFT (15U) #define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) #define USB_USBSTS_NAKI_MASK (0x10000U) #define USB_USBSTS_NAKI_SHIFT (16U) #define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) #define USB_USBSTS_TI0_MASK (0x1000000U) #define USB_USBSTS_TI0_SHIFT (24U) #define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) #define USB_USBSTS_TI1_MASK (0x2000000U) #define USB_USBSTS_TI1_SHIFT (25U) #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) /*! @} */ /*! @name USBINTR - Interrupt Enable Register */ /*! @{ */ #define USB_USBINTR_UE_MASK (0x1U) #define USB_USBINTR_UE_SHIFT (0U) #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) #define USB_USBINTR_UEE_MASK (0x2U) #define USB_USBINTR_UEE_SHIFT (1U) #define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) #define USB_USBINTR_PCE_MASK (0x4U) #define USB_USBINTR_PCE_SHIFT (2U) #define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) #define USB_USBINTR_FRE_MASK (0x8U) #define USB_USBINTR_FRE_SHIFT (3U) #define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) #define USB_USBINTR_SEE_MASK (0x10U) #define USB_USBINTR_SEE_SHIFT (4U) #define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) #define USB_USBINTR_AAE_MASK (0x20U) #define USB_USBINTR_AAE_SHIFT (5U) #define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) #define USB_USBINTR_URE_MASK (0x40U) #define USB_USBINTR_URE_SHIFT (6U) #define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) #define USB_USBINTR_SRE_MASK (0x80U) #define USB_USBINTR_SRE_SHIFT (7U) #define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) #define USB_USBINTR_SLE_MASK (0x100U) #define USB_USBINTR_SLE_SHIFT (8U) #define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) #define USB_USBINTR_ULPIE_MASK (0x400U) #define USB_USBINTR_ULPIE_SHIFT (10U) #define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) #define USB_USBINTR_NAKE_MASK (0x10000U) #define USB_USBINTR_NAKE_SHIFT (16U) #define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) #define USB_USBINTR_UAIE_MASK (0x40000U) #define USB_USBINTR_UAIE_SHIFT (18U) #define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) #define USB_USBINTR_UPIE_MASK (0x80000U) #define USB_USBINTR_UPIE_SHIFT (19U) #define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) #define USB_USBINTR_TIE0_MASK (0x1000000U) #define USB_USBINTR_TIE0_SHIFT (24U) #define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) #define USB_USBINTR_TIE1_MASK (0x2000000U) #define USB_USBINTR_TIE1_SHIFT (25U) #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) /*! @} */ /*! @name FRINDEX - USB Frame Index */ /*! @{ */ #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USB_FRINDEX_FRINDEX_SHIFT (0U) /*! FRINDEX * 0b00000000000000..(1024) 12 * 0b00000000000001..(512) 11 * 0b00000000000010..(256) 10 * 0b00000000000011..(128) 9 * 0b00000000000100..(64) 8 * 0b00000000000101..(32) 7 * 0b00000000000110..(16) 6 * 0b00000000000111..(8) 5 */ #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) /*! @} */ /*! @name DEVICEADDR - Device Address */ /*! @{ */ #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USB_DEVICEADDR_USBADRA_SHIFT (24U) #define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USB_DEVICEADDR_USBADR_SHIFT (25U) #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) /*! @} */ /*! @name PERIODICLISTBASE - Frame List Base Address */ /*! @{ */ #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) #define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) /*! @} */ /*! @name ASYNCLISTADDR - Next Asynch. Address */ /*! @{ */ #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) #define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) /*! @} */ /*! @name ENDPTLISTADDR - Endpoint List Address */ /*! @{ */ #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) #define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) /*! @} */ /*! @name BURSTSIZE - Programmable Burst Size */ /*! @{ */ #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USB_BURSTSIZE_RXPBURST_SHIFT (0U) #define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) #define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) #define USB_BURSTSIZE_TXPBURST_SHIFT (8U) #define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) /*! @} */ /*! @name TXFILLTUNING - TX FIFO Fill Tuning */ /*! @{ */ #define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) #define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) #define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) #define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) /*! @} */ /*! @name ENDPTNAK - Endpoint NAK */ /*! @{ */ #define USB_ENDPTNAK_EPRN_MASK (0xFFU) #define USB_ENDPTNAK_EPRN_SHIFT (0U) #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USB_ENDPTNAK_EPTN_SHIFT (16U) #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) /*! @} */ /*! @name ENDPTNAKEN - Endpoint NAK Enable */ /*! @{ */ #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) #define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) #define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) /*! @} */ /*! @name CONFIGFLAG - Configure Flag Register */ /*! @{ */ #define USB_CONFIGFLAG_CF_MASK (0x1U) #define USB_CONFIGFLAG_CF_SHIFT (0U) /*! CF * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. * 0b1..Port routing control logic default-routes all ports to this host controller. */ #define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) /*! @} */ /*! @name PORTSC1 - Port Status & Control */ /*! @{ */ #define USB_PORTSC1_CCS_MASK (0x1U) #define USB_PORTSC1_CCS_SHIFT (0U) #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) #define USB_PORTSC1_CSC_MASK (0x2U) #define USB_PORTSC1_CSC_SHIFT (1U) #define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) #define USB_PORTSC1_PE_MASK (0x4U) #define USB_PORTSC1_PE_SHIFT (2U) #define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) #define USB_PORTSC1_PEC_MASK (0x8U) #define USB_PORTSC1_PEC_SHIFT (3U) #define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) #define USB_PORTSC1_OCA_MASK (0x10U) #define USB_PORTSC1_OCA_SHIFT (4U) /*! OCA * 0b1..This port currently has an over-current condition * 0b0..This port does not have an over-current condition. */ #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) #define USB_PORTSC1_OCC_MASK (0x20U) #define USB_PORTSC1_OCC_SHIFT (5U) #define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) #define USB_PORTSC1_FPR_MASK (0x40U) #define USB_PORTSC1_FPR_SHIFT (6U) #define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) #define USB_PORTSC1_SUSP_MASK (0x80U) #define USB_PORTSC1_SUSP_SHIFT (7U) #define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) #define USB_PORTSC1_PR_MASK (0x100U) #define USB_PORTSC1_PR_SHIFT (8U) #define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) #define USB_PORTSC1_HSP_MASK (0x200U) #define USB_PORTSC1_HSP_SHIFT (9U) #define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) #define USB_PORTSC1_LS_MASK (0xC00U) #define USB_PORTSC1_LS_SHIFT (10U) /*! LS * 0b00..SE0 * 0b10..J-state * 0b01..K-state * 0b11..Undefined */ #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) #define USB_PORTSC1_PP_MASK (0x1000U) #define USB_PORTSC1_PP_SHIFT (12U) #define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) #define USB_PORTSC1_PO_MASK (0x2000U) #define USB_PORTSC1_PO_SHIFT (13U) #define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) #define USB_PORTSC1_PIC_MASK (0xC000U) #define USB_PORTSC1_PIC_SHIFT (14U) /*! PIC * 0b00..Port indicators are off * 0b01..Amber * 0b10..Green * 0b11..Undefined */ #define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) #define USB_PORTSC1_PTC_MASK (0xF0000U) #define USB_PORTSC1_PTC_SHIFT (16U) /*! PTC * 0b0000..TEST_MODE_DISABLE * 0b0001..J_STATE * 0b0010..K_STATE * 0b0011..SE0 (host) / NAK (device) * 0b0100..Packet * 0b0101..FORCE_ENABLE_HS * 0b0110..FORCE_ENABLE_FS * 0b0111..FORCE_ENABLE_LS */ #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) #define USB_PORTSC1_WKCN_MASK (0x100000U) #define USB_PORTSC1_WKCN_SHIFT (20U) #define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) #define USB_PORTSC1_WKDC_MASK (0x200000U) #define USB_PORTSC1_WKDC_SHIFT (21U) #define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) #define USB_PORTSC1_WKOC_MASK (0x400000U) #define USB_PORTSC1_WKOC_SHIFT (22U) #define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) #define USB_PORTSC1_PHCD_MASK (0x800000U) #define USB_PORTSC1_PHCD_SHIFT (23U) /*! PHCD * 0b1..Disable PHY clock * 0b0..Enable PHY clock */ #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) #define USB_PORTSC1_PFSC_MASK (0x1000000U) #define USB_PORTSC1_PFSC_SHIFT (24U) /*! PFSC * 0b1..Forced to full speed * 0b0..Normal operation */ #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) #define USB_PORTSC1_PTS_2_MASK (0x2000000U) #define USB_PORTSC1_PTS_2_SHIFT (25U) #define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) #define USB_PORTSC1_PSPD_MASK (0xC000000U) #define USB_PORTSC1_PSPD_SHIFT (26U) /*! PSPD * 0b00..Full Speed * 0b01..Low Speed * 0b10..High Speed * 0b11..Undefined */ #define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) #define USB_PORTSC1_PTW_MASK (0x10000000U) #define USB_PORTSC1_PTW_SHIFT (28U) /*! PTW * 0b0..Select the 8-bit UTMI interface [60MHz] * 0b1..Select the 16-bit UTMI interface [30MHz] */ #define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) #define USB_PORTSC1_STS_MASK (0x20000000U) #define USB_PORTSC1_STS_SHIFT (29U) #define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) #define USB_PORTSC1_PTS_1_MASK (0xC0000000U) #define USB_PORTSC1_PTS_1_SHIFT (30U) #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) /*! @} */ /*! @name OTGSC - On-The-Go Status & control */ /*! @{ */ #define USB_OTGSC_VD_MASK (0x1U) #define USB_OTGSC_VD_SHIFT (0U) #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) #define USB_OTGSC_VC_MASK (0x2U) #define USB_OTGSC_VC_SHIFT (1U) #define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) #define USB_OTGSC_OT_MASK (0x8U) #define USB_OTGSC_OT_SHIFT (3U) #define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) #define USB_OTGSC_DP_MASK (0x10U) #define USB_OTGSC_DP_SHIFT (4U) #define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) #define USB_OTGSC_IDPU_MASK (0x20U) #define USB_OTGSC_IDPU_SHIFT (5U) #define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) #define USB_OTGSC_ID_MASK (0x100U) #define USB_OTGSC_ID_SHIFT (8U) #define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) #define USB_OTGSC_AVV_MASK (0x200U) #define USB_OTGSC_AVV_SHIFT (9U) #define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) #define USB_OTGSC_ASV_MASK (0x400U) #define USB_OTGSC_ASV_SHIFT (10U) #define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) #define USB_OTGSC_BSV_MASK (0x800U) #define USB_OTGSC_BSV_SHIFT (11U) #define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) #define USB_OTGSC_BSE_MASK (0x1000U) #define USB_OTGSC_BSE_SHIFT (12U) #define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) #define USB_OTGSC_TOG_1MS_MASK (0x2000U) #define USB_OTGSC_TOG_1MS_SHIFT (13U) #define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) #define USB_OTGSC_DPS_MASK (0x4000U) #define USB_OTGSC_DPS_SHIFT (14U) #define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) #define USB_OTGSC_IDIS_MASK (0x10000U) #define USB_OTGSC_IDIS_SHIFT (16U) #define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) #define USB_OTGSC_AVVIS_MASK (0x20000U) #define USB_OTGSC_AVVIS_SHIFT (17U) #define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) #define USB_OTGSC_ASVIS_MASK (0x40000U) #define USB_OTGSC_ASVIS_SHIFT (18U) #define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) #define USB_OTGSC_BSVIS_MASK (0x80000U) #define USB_OTGSC_BSVIS_SHIFT (19U) #define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) #define USB_OTGSC_BSEIS_MASK (0x100000U) #define USB_OTGSC_BSEIS_SHIFT (20U) #define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) #define USB_OTGSC_STATUS_1MS_MASK (0x200000U) #define USB_OTGSC_STATUS_1MS_SHIFT (21U) #define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) #define USB_OTGSC_DPIS_MASK (0x400000U) #define USB_OTGSC_DPIS_SHIFT (22U) #define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) #define USB_OTGSC_IDIE_MASK (0x1000000U) #define USB_OTGSC_IDIE_SHIFT (24U) #define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) #define USB_OTGSC_AVVIE_MASK (0x2000000U) #define USB_OTGSC_AVVIE_SHIFT (25U) #define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) #define USB_OTGSC_ASVIE_MASK (0x4000000U) #define USB_OTGSC_ASVIE_SHIFT (26U) #define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) #define USB_OTGSC_BSVIE_MASK (0x8000000U) #define USB_OTGSC_BSVIE_SHIFT (27U) #define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) #define USB_OTGSC_BSEIE_MASK (0x10000000U) #define USB_OTGSC_BSEIE_SHIFT (28U) #define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) #define USB_OTGSC_EN_1MS_MASK (0x20000000U) #define USB_OTGSC_EN_1MS_SHIFT (29U) #define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) #define USB_OTGSC_DPIE_MASK (0x40000000U) #define USB_OTGSC_DPIE_SHIFT (30U) #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) /*! @} */ /*! @name USBMODE - USB Device Mode */ /*! @{ */ #define USB_USBMODE_CM_MASK (0x3U) #define USB_USBMODE_CM_SHIFT (0U) /*! CM * 0b00..Idle [Default for combination host/device] * 0b01..Reserved * 0b10..Device Controller [Default for device only controller] * 0b11..Host Controller [Default for host only controller] */ #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) #define USB_USBMODE_ES_MASK (0x4U) #define USB_USBMODE_ES_SHIFT (2U) /*! ES * 0b0..Little Endian [Default] * 0b1..Big Endian */ #define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) #define USB_USBMODE_SLOM_MASK (0x8U) #define USB_USBMODE_SLOM_SHIFT (3U) /*! SLOM * 0b0..Setup Lockouts On (default); * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . */ #define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) #define USB_USBMODE_SDIS_MASK (0x10U) #define USB_USBMODE_SDIS_SHIFT (4U) #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) /*! @} */ /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ /*! @{ */ #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) /*! @} */ /*! @name ENDPTPRIME - Endpoint Prime */ /*! @{ */ #define USB_ENDPTPRIME_PERB_MASK (0xFFU) #define USB_ENDPTPRIME_PERB_SHIFT (0U) #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USB_ENDPTPRIME_PETB_SHIFT (16U) #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) /*! @} */ /*! @name ENDPTFLUSH - Endpoint Flush */ /*! @{ */ #define USB_ENDPTFLUSH_FERB_MASK (0xFFU) #define USB_ENDPTFLUSH_FERB_SHIFT (0U) #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USB_ENDPTFLUSH_FETB_SHIFT (16U) #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) /*! @} */ /*! @name ENDPTSTAT - Endpoint Status */ /*! @{ */ #define USB_ENDPTSTAT_ERBR_MASK (0xFFU) #define USB_ENDPTSTAT_ERBR_SHIFT (0U) #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USB_ENDPTSTAT_ETBR_SHIFT (16U) #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) /*! @} */ /*! @name ENDPTCOMPLETE - Endpoint Complete */ /*! @{ */ #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) /*! @} */ /*! @name ENDPTCTRL0 - Endpoint Control0 */ /*! @{ */ #define USB_ENDPTCTRL0_RXS_MASK (0x1U) #define USB_ENDPTCTRL0_RXS_SHIFT (0U) #define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) #define USB_ENDPTCTRL0_RXT_MASK (0xCU) #define USB_ENDPTCTRL0_RXT_SHIFT (2U) #define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) #define USB_ENDPTCTRL0_RXE_MASK (0x80U) #define USB_ENDPTCTRL0_RXE_SHIFT (7U) #define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) #define USB_ENDPTCTRL0_TXS_MASK (0x10000U) #define USB_ENDPTCTRL0_TXS_SHIFT (16U) #define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) #define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) #define USB_ENDPTCTRL0_TXT_SHIFT (18U) #define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) #define USB_ENDPTCTRL0_TXE_MASK (0x800000U) #define USB_ENDPTCTRL0_TXE_SHIFT (23U) #define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) /*! @} */ /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ /*! @{ */ #define USB_ENDPTCTRL_RXS_MASK (0x1U) #define USB_ENDPTCTRL_RXS_SHIFT (0U) #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) #define USB_ENDPTCTRL_RXD_MASK (0x2U) #define USB_ENDPTCTRL_RXD_SHIFT (1U) #define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) #define USB_ENDPTCTRL_RXT_MASK (0xCU) #define USB_ENDPTCTRL_RXT_SHIFT (2U) #define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) #define USB_ENDPTCTRL_RXI_MASK (0x20U) #define USB_ENDPTCTRL_RXI_SHIFT (5U) #define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) #define USB_ENDPTCTRL_RXR_MASK (0x40U) #define USB_ENDPTCTRL_RXR_SHIFT (6U) #define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) #define USB_ENDPTCTRL_RXE_MASK (0x80U) #define USB_ENDPTCTRL_RXE_SHIFT (7U) #define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) #define USB_ENDPTCTRL_TXS_MASK (0x10000U) #define USB_ENDPTCTRL_TXS_SHIFT (16U) #define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) #define USB_ENDPTCTRL_TXD_MASK (0x20000U) #define USB_ENDPTCTRL_TXD_SHIFT (17U) #define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) #define USB_ENDPTCTRL_TXT_MASK (0xC0000U) #define USB_ENDPTCTRL_TXT_SHIFT (18U) #define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) #define USB_ENDPTCTRL_TXI_MASK (0x200000U) #define USB_ENDPTCTRL_TXI_SHIFT (21U) #define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) #define USB_ENDPTCTRL_TXR_MASK (0x400000U) #define USB_ENDPTCTRL_TXR_SHIFT (22U) #define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) #define USB_ENDPTCTRL_TXE_MASK (0x800000U) #define USB_ENDPTCTRL_TXE_SHIFT (23U) #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) /*! @} */ /* The count of USB_ENDPTCTRL */ #define USB_ENDPTCTRL_COUNT (7U) /*! * @} */ /* end of group USB_Register_Masks */ /* USB - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__USB2 base address */ #define CONNECTIVITY__USB2_BASE (0x5B0D0000u) /** Peripheral CONNECTIVITY__USB2 base pointer */ #define CONNECTIVITY__USB2 ((USB_Type *)CONNECTIVITY__USB2_BASE) /** Array initializer of USB peripheral base addresses */ #define USB_BASE_ADDRS { CONNECTIVITY__USB2_BASE } /** Array initializer of USB peripheral base pointers */ #define USB_BASE_PTRS { CONNECTIVITY__USB2 } /*! * @} */ /* end of group USB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB3_Peripheral_Access_Layer USB3 Peripheral Access Layer * @{ */ /** USB3 - Register Layout Typedef */ typedef struct { __IO uint32_t CORE_CTRL11; /**< Core Control, offset: 0x0 */ uint32_t CORE_CTRL12; /**< Core Control, offset: 0x4 */ __IO uint32_t INT; /**< Interrupt, offset: 0x8 */ __I uint32_t CORE_STATUS; /**< Core Status, offset: 0xC */ uint32_t RESERVED; /**< RESERVED, offset: 0x10 */ uint8_t RESERVED_0[65516]; __O uint32_t OTGCMD; /**< OTG Command, offset: 0x10000 */ __I uint32_t OTGSTS; /**< OTG Status, offset: 0x10004 */ __I uint32_t OTGSTATE; /**< OTG State, offset: 0x10008 */ __IO uint32_t OTGREFCLK; /**< OTG Reference Clock, offset: 0x1000C */ __IO uint32_t OTGIEN; /**< OTG Interrupt Enable, offset: 0x10010 */ __IO uint32_t OTGIVECT; /**< OTG Interrupt Vector, offset: 0x10014 */ uint8_t RESERVED_1[8]; __IO uint32_t CLK_FREQ; /**< Clock Frequency, offset: 0x10020 */ __O uint32_t OTGTMR; /**< OTG Timer, offset: 0x10024 */ uint8_t RESERVED_2[8]; __I uint32_t OTGVERSION; /**< OTG Version, offset: 0x10030 */ __I uint32_t OTGCAPABILITY; /**< OTG Capability, offset: 0x10034 */ uint8_t RESERVED_3[8]; __IO uint32_t OTGSIMULATE; /**< OTG Simulate, offset: 0x10040 */ uint8_t RESERVED_4[12]; __I uint32_t OTGANASTS; /**< OTG Attach Detection Protocol BC Status, offset: 0x10050 */ __I uint32_t ADP_RAMP_TIME; /**< Attach Detection Protocol Ramp Time, offset: 0x10054 */ __IO uint32_t OTGCTRL1; /**< OTG Control, offset: 0x10058 */ __IO uint32_t OTGCTRL2; /**< OTG Control, offset: 0x1005C */ uint8_t RESERVED_5[65440]; __I uint32_t HCIVERSION_CAPLENGTH; /**< HCI Version and CAPLENGTH, offset: 0x20000 */ __I uint32_t HCSPARAMS1; /**< Structural Parameters 1, offset: 0x20004 */ __I uint32_t HCSPARAMS2; /**< Structural Parameters 2, offset: 0x20008 */ __I uint32_t HCSPARAMS3; /**< Structural Parameters 3, offset: 0x2000C */ __I uint32_t HCCPARAMS; /**< Capability Parameters, offset: 0x20010 */ __I uint32_t DBOFF; /**< DoorBell Array Offset, offset: 0x20014 */ __I uint32_t RTSOFF; /**< xHCI Runtime Registers Offset, offset: 0x20018 */ uint8_t RESERVED_6[100]; __IO uint32_t USBCMD; /**< USB Command, offset: 0x20080 */ __IO uint32_t USBSTS; /**< USB Status, offset: 0x20084 */ __I uint32_t PAGESIZE; /**< Page Size, offset: 0x20088 */ uint8_t RESERVED_7[8]; __IO uint32_t DNCTRL; /**< Device Notification Control, offset: 0x20094 */ __IO uint32_t CRCR_LO; /**< Command Ring Control Register Low, offset: 0x20098 */ __IO uint32_t CRCR_HI; /**< Command Ring Control Register High, offset: 0x2009C */ uint8_t RESERVED_8[16]; __IO uint32_t DCBAAP_LO; /**< Device Context Base Address Array Pointer(LOW), offset: 0x200B0 */ __IO uint32_t DCBAAP_HI; /**< Device Context Base Address Array Pointer (HIGH), offset: 0x200B4 */ __IO uint32_t CONFIG; /**< Configure, offset: 0x200B8 */ uint8_t RESERVED_9[964]; __IO uint32_t PORTSC1USB2; /**< USB2 Port Status and Control, offset: 0x20480 */ __IO uint32_t PORTPMSC1USB2; /**< USB2 Port Power Management Status and Control, offset: 0x20484 */ uint8_t RESERVED_10[4]; __IO uint32_t PORT1HLPMC; /**< USB2 Port Hardware LPM Control register, offset: 0x2048C */ __IO uint32_t PORTSC1USB3; /**< USB3 Port Status and Control, offset: 0x20490 */ __IO uint32_t PORTPMSC1USB3; /**< USB3 Port Power Management Status and Control, offset: 0x20494 */ __I uint32_t PORTLI1; /**< USB3 Port Link Info, offset: 0x20498 */ uint8_t RESERVED_11[7012]; __I uint32_t MFINDEX; /**< MicroFrame Index, offset: 0x22000 */ uint8_t RESERVED_12[28]; __IO uint32_t IMAN0; /**< Interrupter Management, offset: 0x22020 */ __IO uint32_t IMOD0; /**< Interrupter Moderation, offset: 0x22024 */ __IO uint32_t ERSTSZ0; /**< Event Ring Segment Table Size, offset: 0x22028 */ uint32_t RSVD0; /**< Reserved, offset: 0x2202C */ __IO uint32_t ERSTBA0_LO; /**< Event Ring Segment Table Base Address (LOW), offset: 0x22030 */ __IO uint32_t ERSTBA00_HI; /**< Event Ring Segment Table Base Address (HIGH), offset: 0x22034 */ __IO uint32_t ERDP0_LO; /**< Event Ring Dequeue Pointer (LOW), offset: 0x22038 */ __IO uint32_t ERDP0_HI; /**< Event Ring Dequeue Pointer (HIGH), offset: 0x2203C */ __IO uint32_t IMAN1; /**< Interrupter Management, offset: 0x22040 */ __IO uint32_t IMOD1; /**< Interrupter Moderation, offset: 0x22044 */ __IO uint32_t ERSTSZ1; /**< Event Ring Segment Table Size, offset: 0x22048 */ uint32_t RSVD1; /**< Reserved, offset: 0x2204C */ __IO uint32_t ERSTBA1_LO; /**< Event Ring Segment Table Base Address (LOW), offset: 0x22050 */ __IO uint32_t ERSTBA01_HI; /**< Event Ring Segment Table Base Address (HIGH), offset: 0x22054 */ __IO uint32_t ERDP1_LO; /**< Event Ring Dequeue Pointer (LOW), offset: 0x22058 */ __IO uint32_t ERDP1_HI; /**< Event Ring Dequeue Pointer (HIGH), offset: 0x2205C */ __IO uint32_t IMAN2; /**< Interrupter Management, offset: 0x22060 */ __IO uint32_t IMOD2; /**< Interrupter Moderation, offset: 0x22064 */ __IO uint32_t ERSTSZ2; /**< Event Ring Segment Table Size, offset: 0x22068 */ uint32_t RSVD2; /**< Reserved, offset: 0x2206C */ __IO uint32_t ERSTBA2_LO; /**< Event Ring Segment Table Base Address (LOW), offset: 0x22070 */ __IO uint32_t ERSTBA02_HI; /**< Event Ring Segment Table Base Address (HIGH), offset: 0x22074 */ __IO uint32_t ERDP2_LO; /**< Event Ring Dequeue Pointer (LOW), offset: 0x22078 */ __IO uint32_t ERDP2_HI; /**< Event Ring Dequeue Pointer (HIGH), offset: 0x2207C */ __IO uint32_t IMAN3; /**< Interrupter Management, offset: 0x22080 */ __IO uint32_t IMOD3; /**< Interrupter Moderation, offset: 0x22084 */ __IO uint32_t ERSTSZ3; /**< Event Ring Segment Table Size, offset: 0x22088 */ uint32_t RSVD3; /**< Reserved, offset: 0x2208C */ __IO uint32_t ERSTBA3_LO; /**< Event Ring Segment Table Base Address (LOW), offset: 0x22090 */ __IO uint32_t ERSTBA03_HI; /**< Event Ring Segment Table Base Address (HIGH), offset: 0x22094 */ __IO uint32_t ERDP3_LO; /**< Event Ring Dequeue Pointer (LOW), offset: 0x22098 */ __IO uint32_t ERDP3_HI; /**< Event Ring Dequeue Pointer (HIGH), offset: 0x2209C */ __IO uint32_t IMAN4; /**< Interrupter Management, offset: 0x220A0 */ __IO uint32_t IMOD4; /**< Interrupter Moderation, offset: 0x220A4 */ __IO uint32_t ERSTSZ4; /**< Event Ring Segment Table Size, offset: 0x220A8 */ uint32_t RSVD4; /**< Reserved, offset: 0x220AC */ __IO uint32_t ERSTBA4_LO; /**< Event Ring Segment Table Base Address (LOW), offset: 0x220B0 */ __IO uint32_t ERSTBA04_HI; /**< Event Ring Segment Table Base Address (HIGH), offset: 0x220B4 */ __IO uint32_t ERDP4_LO; /**< Event Ring Dequeue Pointer (LOW), offset: 0x220B8 */ __IO uint32_t ERDP4_HI; /**< Event Ring Dequeue Pointer (HIGH), offset: 0x220BC */ __IO uint32_t IMAN5; /**< Interrupter Management, offset: 0x220C0 */ __IO uint32_t IMOD5; /**< Interrupter Moderation, offset: 0x220C4 */ __IO uint32_t ERSTSZ5; /**< Event Ring Segment Table Size, offset: 0x220C8 */ uint32_t RSVD5; /**< Reserved, offset: 0x220CC */ __IO uint32_t ERSTBA5_LO; /**< Event Ring Segment Table Base Address (LOW), offset: 0x220D0 */ __IO uint32_t ERSTBA05_HI; /**< Event Ring Segment Table Base Address (HIGH), offset: 0x220D4 */ __IO uint32_t ERDP5_LO; /**< Event Ring Dequeue Pointer (LOW), offset: 0x220D8 */ __IO uint32_t ERDP5_HI; /**< Event Ring Dequeue Pointer (HIGH), offset: 0x220DC */ __IO uint32_t IMAN6; /**< Interrupter Management, offset: 0x220E0 */ __IO uint32_t IMOD6; /**< Interrupter Moderation, offset: 0x220E4 */ __IO uint32_t ERSTSZ6; /**< Event Ring Segment Table Size, offset: 0x220E8 */ uint32_t RSVD6; /**< Reserved, offset: 0x220EC */ __IO uint32_t ERSTBA6_LO; /**< Event Ring Segment Table Base Address (LOW), offset: 0x220F0 */ __IO uint32_t ERSTBA06_HI; /**< Event Ring Segment Table Base Address (HIGH), offset: 0x220F4 */ __IO uint32_t ERDP6_LO; /**< Event Ring Dequeue Pointer (LOW), offset: 0x220F8 */ __IO uint32_t ERDP6_HI; /**< Event Ring Dequeue Pointer (HIGH), offset: 0x220FC */ __IO uint32_t IMAN7; /**< Interrupter Management, offset: 0x22100 */ __IO uint32_t IMOD7; /**< Interrupter Moderation, offset: 0x22104 */ __IO uint32_t ERSTSZ7; /**< Event Ring Segment Table Size, offset: 0x22108 */ uint32_t RSVD7; /**< Reserved, offset: 0x2210C */ __IO uint32_t ERSTBA7_LO; /**< Event Ring Segment Table Base Address (LOW), offset: 0x22110 */ __IO uint32_t ERSTBA07_HI; /**< Event Ring Segment Table Base Address (HIGH), offset: 0x22114 */ __IO uint32_t ERDP7_LO; /**< Event Ring Dequeue Pointer (LOW), offset: 0x22118 */ __IO uint32_t ERDP7_HI; /**< Event Ring Dequeue Pointer (HIGH), offset: 0x2211C */ uint8_t RESERVED_13[3808]; __IO uint32_t DB0; /**< Host Controller Doorbell, offset: 0x23000 */ __IO uint32_t DB1; /**< Doorbell Array, offset: 0x23004 */ __IO uint32_t DB2; /**< Doorbell Array, offset: 0x23008 */ __IO uint32_t DB3; /**< Doorbell Array, offset: 0x2300C */ __IO uint32_t DB4; /**< Doorbell Array, offset: 0x23010 */ __IO uint32_t DB5; /**< Doorbell Array, offset: 0x23014 */ __IO uint32_t DB6; /**< Doorbell Array, offset: 0x23018 */ __IO uint32_t DB7; /**< Doorbell Array, offset: 0x2301C */ __IO uint32_t DB8; /**< Doorbell Array, offset: 0x23020 */ __IO uint32_t DB9; /**< Doorbell Array, offset: 0x23024 */ __IO uint32_t DB10; /**< Doorbell Array, offset: 0x23028 */ __IO uint32_t DB11; /**< Doorbell Array, offset: 0x2302C */ __IO uint32_t DB12; /**< Doorbell Array, offset: 0x23030 */ __IO uint32_t DB13; /**< Doorbell Array, offset: 0x23034 */ __IO uint32_t DB14; /**< Doorbell Array, offset: 0x23038 */ __IO uint32_t DB15; /**< Doorbell Array, offset: 0x2303C */ __IO uint32_t DB16; /**< Doorbell Array, offset: 0x23040 */ __IO uint32_t DB17; /**< Doorbell Array, offset: 0x23044 */ __IO uint32_t DB18; /**< Doorbell Array, offset: 0x23048 */ __IO uint32_t DB19; /**< Doorbell Array, offset: 0x2304C */ __IO uint32_t DB20; /**< Doorbell Array, offset: 0x23050 */ __IO uint32_t DB21; /**< Doorbell Array, offset: 0x23054 */ __IO uint32_t DB22; /**< Doorbell Array, offset: 0x23058 */ __IO uint32_t DB23; /**< Doorbell Array, offset: 0x2305C */ __IO uint32_t DB24; /**< Doorbell Array, offset: 0x23060 */ __IO uint32_t DB25; /**< Doorbell Array, offset: 0x23064 */ __IO uint32_t DB26; /**< Doorbell Array, offset: 0x23068 */ __IO uint32_t DB27; /**< Doorbell Array, offset: 0x2306C */ __IO uint32_t DB28; /**< Doorbell Array, offset: 0x23070 */ __IO uint32_t DB29; /**< Doorbell Array, offset: 0x23074 */ __IO uint32_t DB30; /**< Doorbell Array, offset: 0x23078 */ __IO uint32_t DB31; /**< Doorbell Array, offset: 0x2307C */ __IO uint32_t DB32; /**< Doorbell Array, offset: 0x23080 */ uint8_t RESERVED_14[20348]; __IO uint32_t XECP_PORT_CAP_REG; /**< USB3 Extended capability, offset: 0x28000 */ __IO uint32_t XECP_PORT_1_REG; /**< USB3 Extended capability, offset: 0x28004 */ __IO uint32_t XECP_CDNS_DEBUG_BUS_CAP; /**< xHCI Debug Bus Capability, offset: 0x28008 */ __IO uint32_t XECP_CDNS_DEBUG_BUS_CTRL; /**< xHCI Debug Bus Control, offset: 0x2800C */ __I uint32_t XECP_CDNS_DEBUG_BUS_STATUS; /**< xHCI Debug Bus Status, offset: 0x28010 */ __IO uint32_t XECP_PM_CAP; /**< Extended Power Management capability, offset: 0x28014 */ __IO uint32_t XECP_PM_PMCSR; /**< Extended Power Management Control/Status, offset: 0x28018 */ __IO uint32_t XECP_MSI_CAP; /**< MSI configuration, offset: 0x2801C */ __IO uint32_t XECP_MSI_ADDR_L; /**< Message Lower Address, offset: 0x28020 */ __IO uint32_t XECP_MSI_ADDR_H; /**< Message Upper Address, offset: 0x28024 */ __IO uint32_t XECP_MSI_DATA; /**< Message data, offset: 0x28028 */ __IO uint32_t XECP_AXI_CAP; /**< AXI Master Wrapper Extended Capability, offset: 0x2802C */ __I uint32_t XECP_AXI_CFG0; /**< AXI Master Wrapper Extended Capability Configuration, offset: 0x28030 */ __IO uint32_t XECP_AXI_CTRL0; /**< AXI Master Wrapper Extended Capability Control, offset: 0x28034 */ __IO uint32_t XECP_AXI_CTRL1; /**< AXI Master Wrapper Extended Capability Control, offset: 0x28038 */ __IO uint32_t XECP_AXI_CTRL2; /**< AXI Master Wrapper Extended Capability Control, offset: 0x2803C */ __I uint32_t XECP_SUPP_USB2_CAP0; /**< xHCI Supported Protocol Capability, offset: 0x28040 */ __I uint32_t XECP_SUPP_USB2_CAP1; /**< xHCI Supported Protocol Capability, offset: 0x28044 */ __I uint32_t XECP_SUPP_USB2_CAP2; /**< xHCI Supported Protocol Capability, offset: 0x28048 */ __I uint32_t XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE; /**< Protocol Slot Type, offset: 0x2804C */ __I uint32_t XECP_PSI_FULL_SPEED; /**< Protocol Speed ID, offset: 0x28050 */ __I uint32_t XECP_PSI_LOW_SPEED; /**< Protocol Speed ID, offset: 0x28054 */ __I uint32_t XECP_PSI_HIGH_SPEED; /**< Protocol Speed ID, offset: 0x28058 */ uint8_t RESERVED_15[4]; __I uint32_t XECP_SUPP_USB3_CAP0; /**< xHCI Supported Protocol Capability, offset: 0x28060 */ __I uint32_t XECP_SUPP_USB3_CAP1; /**< xHCI Supported Protocol Capability, offset: 0x28064 */ __I uint32_t XECP_SUPP_USB3_CAP2; /**< xHCI Supported Protocol Capability; USB 3, offset: 0x28068 */ __I uint32_t XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE; /**< Protocol Slot Type, offset: 0x2806C */ __I uint32_t PSI_SUPER_SPEED; /**< Protocol Speed ID, offset: 0x28070 */ uint8_t RESERVED_16[12]; __I uint32_t XECP_CMDM_STS0; /**< Command Ring related status, offset: 0x28080 */ uint32_t RSVD01; /**< Reserved, offset: 0x28084 */ uint32_t RSVD02; /**< Reserved, offset: 0x28088 */ uint32_t RSVD03; /**< Reserved, offset: 0x2808C */ uint32_t RSVD04; /**< Reserved, offset: 0x28090 */ uint32_t RSVD05; /**< Reserved, offset: 0x28094 */ __IO uint32_t XECP_CMDM_CTRL_REG1; /**< Command Manager Control, offset: 0x28098 */ __IO uint32_t XECP_CMDM_CTRL_REG2; /**< Command Manager Control, offset: 0x2809C */ __IO uint32_t XECP_CMDM_CTRL_REG3; /**< Command Manager Control, offset: 0x280A0 */ uint8_t RESERVED_17[12]; __I uint32_t XECP_HOST_CTRL_CAP; /**< Host Control Capability, offset: 0x280B0 */ uint32_t XECP_HOST_CTRL_RSVD; /**< Reserved, offset: 0x280B4 */ __O uint32_t XECP_HOST_CLR_MASK_REG; /**< Override Endpoint Flow Control, offset: 0x280B8 */ __O uint32_t XECP_HOST_CLR_IN_EP_VALID_REG; /**< Clear Active IN EP ID Control, offset: 0x280BC */ __O uint32_t XECP_HOST_CLR_PMASK_REG; /**< Clear Poll Mask Control, offset: 0x280C0 */ __IO uint32_t XECP_HOST_CTRL_OCRD_REG; /**< Port Credit Control, offset: 0x280C4 */ __I uint32_t XECP_HOST_CTRL_TEST_BUS_LO; /**< Test Bus Low, offset: 0x280C8 */ __I uint32_t XECP_HOST_CTRL_TEST_BUS_HI; /**< Test Bus High, offset: 0x280CC */ __IO uint32_t XECP_HOST_CTRL_TRM_REG1; /**< Host Control Transfer Manager, offset: 0x280D0 */ __IO uint32_t XECP_HOST_CTRL_SCH_REG1; /**< Host Control Scheduler, offset: 0x280D4 */ __IO uint32_t XECP_HOST_CTRL_ODMA_REG; /**< Host Control ODMA, offset: 0x280D8 */ __IO uint32_t XECP_HOST_CTRL_IDMA_REG; /**< Host Control IDMA, offset: 0x280DC */ __IO uint32_t XECP_HOST_CTRL_PORT_CTRL; /**< Global Port Control, offset: 0x280E0 */ uint8_t RESERVED_18[28]; __IO uint32_t XECP_AUX_CTRL_REG; /**< AUX Reset Control, offset: 0x28100 */ __IO uint32_t XECP_HOST_BW_OV_SS_REG; /**< Super Speed Bandwidth Overload, offset: 0x28104 */ __IO uint32_t XECP_HOST_BW_OV_HS_REG; /**< High Speed TT Bandwidth Overload, offset: 0x28108 */ __IO uint32_t XECP_HOST_BW_OV_FS_LS_REG; /**< Bandwidth Overload Full and Low Speed, offset: 0x2810C */ __IO uint32_t XECP_HOST_BW_OV_SYS_REG; /**< System Bandwidth Overload, offset: 0x28110 */ __IO uint32_t XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG; /**< Scheduler Async Delay, offset: 0x28114 */ __O uint32_t XECP_UPORTS_PON_RST_REG; /**< AUX Power PHY Reset, offset: 0x28118 */ __IO uint32_t XECP_HOST_CTRL_TRM_REG3; /**< Host Control Transfer Manager (TRM), offset: 0x2811C */ __IO uint32_t XECP_AUX_CTRL_REG1; /**< AUX Power Management Control 1, offset: 0x28120 */ uint8_t RESERVED_19[4]; __IO uint32_t XECP_HOST_CTRL_WATERMARK_REG; /**< Port Watermark, offset: 0x28128 */ __IO uint32_t XECP_HOST_CTRL_PORT_LINK_REG; /**< SuperSpeed Port Link Control, offset: 0x2812C */ __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG1; /**< USB2 Port Link Control, offset: 0x28130 */ __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG2; /**< USB2 Port Link Control, offset: 0x28134 */ __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG3; /**< USB2 Port Link Control, offset: 0x28138 */ __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG4; /**< USB2 Port Link Control, offset: 0x2813C */ __IO uint32_t XECP_HOST_CTRL_BW_MAX_REG; /**< USB2 Max Bandwidth Control, offset: 0x28140 */ __I uint32_t XECP_FPGA_REVISION_REG; /**< FPGA_REVISION_REG, offset: 0x28144 */ __IO uint32_t XECP_HOST_INTF_CTRL_REG; /**< Host interface control, offset: 0x28148 */ uint8_t RESERVED_20[548]; __IO uint32_t XECP_USBLEGSUP; /**< USB Legacy Support Capability, offset: 0x28370 */ __IO uint32_t XECP_USBLEGCTLSTS; /**< USB Legacy Support Control Status, offset: 0x28374 */ uint8_t RESERVED_21[8]; __I uint32_t XECP_DCID; /**< Debug Capability ID, offset: 0x28380 */ __IO uint32_t XECP_DCDB; /**< Debug Capability Doorbell, offset: 0x28384 */ __IO uint32_t XECP_DCERSTSZ; /**< Debug Capability Event Ring Segment Table Size, offset: 0x28388 */ uint32_t XECP_RSVD_0C; /**< Reserved, offset: 0x2838C */ __IO uint32_t XECP_DCERSTBA_LOW; /**< Debug Capability Event Ring Segment Table Base Address, offset: 0x28390 */ __IO uint32_t XECP_DCERSTBA_HIGH; /**< Debug Capability Event Ring Segment Table Base Address, offset: 0x28394 */ __IO uint32_t XECP_DCERDP_LOW; /**< Debug Capability Event Ring Dequeue Pointer, offset: 0x28398 */ __IO uint32_t XECP_DCERDP_HIGH; /**< Debug Capability Event Ring Dequeue Pointer, offset: 0x2839C */ __IO uint32_t XECP_DCCTRL; /**< Debug Capability Control, offset: 0x283A0 */ __I uint32_t XECP_DCST; /**< Debug Capability Status, offset: 0x283A4 */ __IO uint32_t XECP_DCPORTSC; /**< Debug Capability Port Status and Control, offset: 0x283A8 */ uint32_t XECP_RSVD_2C; /**< Reserved, offset: 0x283AC */ __IO uint32_t XECP_DCCP_LOW; /**< Debug Capability Context Pointer, offset: 0x283B0 */ __IO uint32_t XECP_DCCP_HIGH; /**< Debug Capability Context Pointer, offset: 0x283B4 */ __IO uint32_t XECP_DCDDI1; /**< Debug Capability Device Descriptor Info, offset: 0x283B8 */ __IO uint32_t XECP_DCDDI2; /**< The Debug Capability Device Descriptor, offset: 0x283BC */ uint8_t RESERVED_22[31808]; __IO uint32_t USB_CONF; /**< Global Configuration, offset: 0x30000 */ __I uint32_t USB_STS; /**< Global Status, offset: 0x30004 */ __IO uint32_t USB_CMD; /**< Global Command, offset: 0x30008 */ __I uint32_t USB_IPTN; /**< ITP Number, offset: 0x3000C */ __I uint32_t USB_LPM; /**< Link Power Management, offset: 0x30010 */ __IO uint32_t USB_IEN; /**< Interrupt Enable, offset: 0x30014 */ __IO uint32_t USB_ISTS; /**< Interrupt Status, offset: 0x30018 */ __IO uint32_t EP_SEL; /**< Endpoint Select, offset: 0x3001C */ __IO uint32_t EP_TRADDR; /**< Endpoint Transfer Ring Address, offset: 0x30020 */ __IO uint32_t EP_CFG; /**< Endpoint Configuration, offset: 0x30024 */ __IO uint32_t EP_CMD; /**< Endpoint Command, offset: 0x30028 */ __IO uint32_t EP_STS; /**< Endpoint Status, offset: 0x3002C */ __I uint32_t EP_STS_SID; /**< Endpoint Status, offset: 0x30030 */ __IO uint32_t EP_STS_EN; /**< Endpoint Status Register Enable, offset: 0x30034 */ __IO uint32_t DRBL; /**< Doorbell Register, offset: 0x30038 */ __IO uint32_t EP_IEN; /**< Endpoints Interrupt Enable), offset: 0x3003C */ __I uint32_t EP_ISTS; /**< Endpoints Interrupt Status, offset: 0x30040 */ __IO uint32_t USB_PWR; /**< Global power configuration, offset: 0x30044 */ __IO uint32_t USB_CONF2; /**< USB configuration, offset: 0x30048 */ __I uint32_t USB_CAP1; /**< USB Capability, offset: 0x3004C */ __I uint32_t USB_CAP2; /**< USB Capability, offset: 0x30050 */ __I uint32_t USB_CAP3; /**< USB Capability, offset: 0x30054 */ __I uint32_t USB_CAP4; /**< ISO HW support, offset: 0x30058 */ __I uint32_t USB_CAP5; /**< Bulk Stream HW, offset: 0x3005C */ __I uint32_t USB_CAP6; /**< Device controller version, offset: 0x30060 */ __IO uint32_t USB_CPKT1; /**< Custom Packet value, offset: 0x30064 */ __IO uint32_t USB_CPKT2; /**< Custom Packet value, offset: 0x30068 */ __IO uint32_t USB_CPKT3; /**< Custom Packet value, offset: 0x3006C */ uint8_t RESERVED_23[144]; __IO uint32_t CFG_REG1; /**< VBUS debouncer Configuration, offset: 0x30100 */ __IO uint32_t DBG_LINK1; /**< Link, offset: 0x30104 */ __IO uint32_t DBG_LINK2; /**< Link, offset: 0x30108 */ __IO uint32_t CFG_REG4; /**< USB3 Configuration, offset: 0x3010C */ __IO uint32_t CFG_REG5; /**< USB3 Configuration, offset: 0x30110 */ __IO uint32_t CFG_REG6; /**< Configuration Register 6, offset: 0x30114 */ __IO uint32_t CFG_REG7; /**< USB3 Configuration, offset: 0x30118 */ __IO uint32_t CFG_REG8; /**< USB3 Configuration, offset: 0x3011C */ __IO uint32_t CFG_REG9; /**< USB3 Configuration, offset: 0x30120 */ __IO uint32_t CFG_REG10; /**< USB3 Configuration, offset: 0x30124 */ __IO uint32_t CFG_REG11; /**< USB3 Configuration, offset: 0x30128 */ __IO uint32_t CFG_REG12; /**< USB3 Configuration, offset: 0x3012C */ __IO uint32_t CFG_REG13; /**< USB3 Configuration, offset: 0x30130 */ __IO uint32_t CFG_REG14; /**< USB3 Configuration, offset: 0x30134 */ __IO uint32_t CFG_REG15; /**< USB3 Configuration, offset: 0x30138 */ __IO uint32_t CFG_REG16; /**< USB3 Configuration, offset: 0x3013C */ __IO uint32_t CFG_REG17; /**< USB3 Configuration, offset: 0x30140 */ __IO uint32_t CFG_REG18; /**< USB3 Configuration, offset: 0x30144 */ __IO uint32_t CFG_REG19; /**< USB3 Configuration, offset: 0x30148 */ __IO uint32_t CFG_REG20; /**< USB3 Configuration, offset: 0x3014C */ __IO uint32_t CFG_REG21; /**< USB3 Configuration, offset: 0x30150 */ __IO uint32_t CFG_REG22; /**< USB3 Configuration, offset: 0x30154 */ __IO uint32_t CFG_REG23; /**< USB3 Configuration, offset: 0x30158 */ __IO uint32_t CFG_REG24; /**< USB3 Configuration, offset: 0x3015C */ __IO uint32_t CFG_REG25; /**< USB3 Configuration, offset: 0x30160 */ __IO uint32_t CFG_REG26; /**< USB3 Configuration, offset: 0x30164 */ __IO uint32_t CFG_REG27; /**< USB3 Configuration, offset: 0x30168 */ __IO uint32_t CFG_REG28; /**< USB3 Configuration, offset: 0x3016C */ __IO uint32_t CFG_REG29; /**< USB3 Configuration, offset: 0x30170 */ __IO uint32_t CFG_REG30; /**< USB3 Configuration, offset: 0x30174 */ __IO uint32_t CFG_REG31; /**< USB3 Configuration, offset: 0x30178 */ __IO uint32_t CFG_REG32; /**< USB3 Configuration, offset: 0x3017C */ __IO uint32_t CFG_REG33; /**< USB3 Configuration, offset: 0x30180 */ __IO uint32_t CFG_REG34; /**< USB3 Configuration, offset: 0x30184 */ __IO uint32_t CFG_REG35; /**< USB3 Configuration, offset: 0x30188 */ uint8_t RESERVED_24[32]; __IO uint32_t CFG_REG36; /**< USB3 Configuration, offset: 0x301AC */ __IO uint32_t CFG_REG37; /**< USB3 Configuration, offset: 0x301B0 */ __IO uint32_t CFG_REG38; /**< USB3 Configuration, offset: 0x301B4 */ __IO uint32_t CFG_REG39; /**< USB3 Configuration, offset: 0x301B8 */ __IO uint32_t CFG_REG40; /**< USB3 Configuration, offset: 0x301BC */ __IO uint32_t CFG_REG41; /**< USB3 Configuration, offset: 0x301C0 */ __IO uint32_t CFG_REG42; /**< USB3 Configuration, offset: 0x301C4 */ __IO uint32_t CFG_REG43; /**< USB3 Configuration, offset: 0x301C8 */ __IO uint32_t CFG_REG44; /**< USB3 Configuration, offset: 0x301CC */ __IO uint32_t CFG_REG45; /**< USB3 Configuration, offset: 0x301D0 */ __IO uint32_t CFG_REG46; /**< USB3 Configuration, offset: 0x301D4 */ __IO uint32_t CFG_REG47; /**< USB3 Configuration, offset: 0x301D8 */ __IO uint32_t CFG_REG48; /**< USB2 Configuration, offset: 0x301DC */ __IO uint32_t CFG_REG49; /**< USB2 Configuration, offset: 0x301E0 */ __IO uint32_t CFG_REG50; /**< USB2 Configuration, offset: 0x301E4 */ __IO uint32_t CFG_REG51; /**< USB2 Configuration, offset: 0x301E8 */ __IO uint32_t CFG_REG52; /**< USB2 Configuration, offset: 0x301EC */ __IO uint32_t CFG_REG53; /**< USB2 Configuration, offset: 0x301F0 */ __IO uint32_t CFG_REG54; /**< USB2 Configuration, offset: 0x301F4 */ __IO uint32_t CFG_REG55; /**< USB2 Configuration, offset: 0x301F8 */ __IO uint32_t CFG_REG56; /**< USB2 Configuration, offset: 0x301FC */ __IO uint32_t CFG_REG57; /**< USB3 Configuration, offset: 0x30200 */ __IO uint32_t CFG_REG58; /**< USB3 Configuration, offset: 0x30204 */ __IO uint32_t CFG_REG59; /**< USB3 Configuration, offset: 0x30208 */ __IO uint32_t CFG_REG60; /**< USB3 Configuration, offset: 0x3020C */ __IO uint32_t CFG_REG61; /**< USB3 Configuration, offset: 0x30210 */ __IO uint32_t CFG_REG62; /**< USB3 Configuration, offset: 0x30214 */ __IO uint32_t CFG_REG63; /**< USB3 Configuration, offset: 0x30218 */ uint8_t RESERVED_25[4]; __IO uint32_t CFG_REG64; /**< USB2 Configuration, offset: 0x30220 */ __IO uint32_t CFG_REG65; /**< USB2 Configuration, offset: 0x30224 */ __IO uint32_t CFG_REG66; /**< USB2 Configuration, offset: 0x30228 */ uint8_t RESERVED_26[212]; __IO uint32_t DMA_AXI_CTRL; /**< DMA AXI Master Control, offset: 0x30300 */ __IO uint32_t DMA_AXI_ID; /**< DMA AXI Master ID, offset: 0x30304 */ __IO uint32_t DMA_AXI_CAP; /**< DMA AXI Master Extended Capability, offset: 0x30308 */ __IO uint32_t DMA_AXI_CTRL0; /**< DMA AXI Master Control, offset: 0x3030C */ __IO uint32_t DMA_AXI_CTRL1; /**< DMA AXI Master Control, offset: 0x30310 */ } USB3_Type; /* ---------------------------------------------------------------------------- -- USB3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB3_Register_Masks USB3 Register Masks * @{ */ /*! @name CORE_CTRL11 - Core Control */ /*! @{ */ #define USB3_CORE_CTRL11_MODE_STRAP_MASK (0x7U) #define USB3_CORE_CTRL11_MODE_STRAP_SHIFT (0U) /*! MODE_STRAP - Can only be changed when the pwr_sw_reset is 1. * 0b001..OTG mode (Default) * 0b010..xHCI mode * 0b100..DEV mode */ #define USB3_CORE_CTRL11_MODE_STRAP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_MODE_STRAP_SHIFT)) & USB3_CORE_CTRL11_MODE_STRAP_MASK) #define USB3_CORE_CTRL11_WAKEUP_INT_CLR_MASK (0x8U) #define USB3_CORE_CTRL11_WAKEUP_INT_CLR_SHIFT (3U) /*! WAKEUP_INT_CLR - Wakeup Interrupt Clear * 0b1..Wakeup interrupt is cleared. */ #define USB3_CORE_CTRL11_WAKEUP_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_WAKEUP_INT_CLR_SHIFT)) & USB3_CORE_CTRL11_WAKEUP_INT_CLR_MASK) #define USB3_CORE_CTRL11_APP_CLK_125_ALWAYSON_MASK (0x10U) #define USB3_CORE_CTRL11_APP_CLK_125_ALWAYSON_SHIFT (4U) /*! APP_CLK_125_ALWAYSON - Set to always enable the 125MHz Clock */ #define USB3_CORE_CTRL11_APP_CLK_125_ALWAYSON(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_APP_CLK_125_ALWAYSON_SHIFT)) & USB3_CORE_CTRL11_APP_CLK_125_ALWAYSON_MASK) #define USB3_CORE_CTRL11_LPM_CLK_ALWAYSON_MASK (0x20U) #define USB3_CORE_CTRL11_LPM_CLK_ALWAYSON_SHIFT (5U) /*! LPM_CLK_ALWAYSON - set to always enable lpm_clk */ #define USB3_CORE_CTRL11_LPM_CLK_ALWAYSON(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_LPM_CLK_ALWAYSON_SHIFT)) & USB3_CORE_CTRL11_LPM_CLK_ALWAYSON_MASK) #define USB3_CORE_CTRL11_XHC_D0_REQ_MASK (0x40U) #define USB3_CORE_CTRL11_XHC_D0_REQ_SHIFT (6U) /*! XHC_D0_REQ - Request Host mode transition to D0 state. Once asserted, shall be held high until xhc_d0_ack is asserted. */ #define USB3_CORE_CTRL11_XHC_D0_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_XHC_D0_REQ_SHIFT)) & USB3_CORE_CTRL11_XHC_D0_REQ_MASK) #define USB3_CORE_CTRL11_MDCTRL_CLK_SEL_MASK (0x80U) #define USB3_CORE_CTRL11_MDCTRL_CLK_SEL_SHIFT (7U) /*! MDCTRL_CLK_SEL - OTG logic clock select signal * 0b0..OTG logic shall operate on the otg_fast_clk. It is a default, after power-on reset value. * 0b1..OTG logic shall operate on the stb_clk_predft (32kHz) clock */ #define USB3_CORE_CTRL11_MDCTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_MDCTRL_CLK_SEL_SHIFT)) & USB3_CORE_CTRL11_MDCTRL_CLK_SEL_MASK) #define USB3_CORE_CTRL11_OVERCURRENT_POLARITY_MASK (0x100U) #define USB3_CORE_CTRL11_OVERCURRENT_POLARITY_SHIFT (8U) /*! OVERCURRENT_POLARITY - Over Current Polarity * 0b0..Active Low * 0b1..Active High */ #define USB3_CORE_CTRL11_OVERCURRENT_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_OVERCURRENT_POLARITY_SHIFT)) & USB3_CORE_CTRL11_OVERCURRENT_POLARITY_MASK) #define USB3_CORE_CTRL11_OVERCURRENT_DISABLE_MASK (0x200U) #define USB3_CORE_CTRL11_OVERCURRENT_DISABLE_SHIFT (9U) /*! OVERCURRENT_DISABLE - 1 to disable overcurrent, since core is active low, so set to 1 will always set overcurrent_n to core. */ #define USB3_CORE_CTRL11_OVERCURRENT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_OVERCURRENT_DISABLE_SHIFT)) & USB3_CORE_CTRL11_OVERCURRENT_DISABLE_MASK) #define USB3_CORE_CTRL11_OTG_ID_WAKEUP_EN_MASK (0x2000U) #define USB3_CORE_CTRL11_OTG_ID_WAKEUP_EN_SHIFT (13U) /*! OTG_ID_WAKEUP_EN - id wakeup interrupt enable, used only when usb3 controller is power down and usb2phy is power on. */ #define USB3_CORE_CTRL11_OTG_ID_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_OTG_ID_WAKEUP_EN_SHIFT)) & USB3_CORE_CTRL11_OTG_ID_WAKEUP_EN_MASK) #define USB3_CORE_CTRL11_OTG_VBUS_WAKEUP_EN_MASK (0x4000U) #define USB3_CORE_CTRL11_OTG_VBUS_WAKEUP_EN_SHIFT (14U) /*! OTG_VBUS_WAKEUP_EN - vbus/sessvalid wakeup interrupt enable, used only when usb3 controller is power down and usb2phy is power on */ #define USB3_CORE_CTRL11_OTG_VBUS_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_OTG_VBUS_WAKEUP_EN_SHIFT)) & USB3_CORE_CTRL11_OTG_VBUS_WAKEUP_EN_MASK) #define USB3_CORE_CTRL11_OTG_WKDPDMCHG_EN_MASK (0x8000U) #define USB3_CORE_CTRL11_OTG_WKDPDMCHG_EN_SHIFT (15U) /*! OTG_WKDPDMCHG_EN - dpdm wakeup interrupt enable, used only when usb3 controller is power down and usb2phy is power on */ #define USB3_CORE_CTRL11_OTG_WKDPDMCHG_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_OTG_WKDPDMCHG_EN_SHIFT)) & USB3_CORE_CTRL11_OTG_WKDPDMCHG_EN_MASK) #define USB3_CORE_CTRL11_WAKEUP_INT_STATUS_MASK (0x10000U) #define USB3_CORE_CTRL11_WAKEUP_INT_STATUS_SHIFT (16U) /*! WAKEUP_INT_STATUS - Wakeup_int_status is read. */ #define USB3_CORE_CTRL11_WAKEUP_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_WAKEUP_INT_STATUS_SHIFT)) & USB3_CORE_CTRL11_WAKEUP_INT_STATUS_MASK) #define USB3_CORE_CTRL11_PHYAPB_SW_RESET_MASK (0x4000000U) #define USB3_CORE_CTRL11_PHYAPB_SW_RESET_SHIFT (26U) /*! PHYAPB_SW_RESET - software reset for usb3phy apb bus * 0b1..Reset (Default) */ #define USB3_CORE_CTRL11_PHYAPB_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_PHYAPB_SW_RESET_SHIFT)) & USB3_CORE_CTRL11_PHYAPB_SW_RESET_MASK) #define USB3_CORE_CTRL11_PHY_SW_RESET_MASK (0x8000000U) #define USB3_CORE_CTRL11_PHY_SW_RESET_SHIFT (27U) /*! PHY_SW_RESET - Softwrae reset for usb3 PHY * 0b1..Reset (Default) */ #define USB3_CORE_CTRL11_PHY_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_PHY_SW_RESET_SHIFT)) & USB3_CORE_CTRL11_PHY_SW_RESET_MASK) #define USB3_CORE_CTRL11_AXI_SW_RESET_MASK (0x20000000U) #define USB3_CORE_CTRL11_AXI_SW_RESET_SHIFT (29U) /*! AXI_SW_RESET - software reset for usb3 axi bus * 0b1..Reset (Default) */ #define USB3_CORE_CTRL11_AXI_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_AXI_SW_RESET_SHIFT)) & USB3_CORE_CTRL11_AXI_SW_RESET_MASK) #define USB3_CORE_CTRL11_APB_SW_RESET_MASK (0x40000000U) #define USB3_CORE_CTRL11_APB_SW_RESET_SHIFT (30U) /*! APB_SW_RESET - software reset for usb3 core apb bus * 0b1..Reset (Default) */ #define USB3_CORE_CTRL11_APB_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_APB_SW_RESET_SHIFT)) & USB3_CORE_CTRL11_APB_SW_RESET_MASK) #define USB3_CORE_CTRL11_PWR_SW_RESET_MASK (0x80000000U) #define USB3_CORE_CTRL11_PWR_SW_RESET_SHIFT (31U) /*! PWR_SW_RESET - software reset for usb3 core * 0b1..Reset (Default) */ #define USB3_CORE_CTRL11_PWR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CTRL11_PWR_SW_RESET_SHIFT)) & USB3_CORE_CTRL11_PWR_SW_RESET_MASK) /*! @} */ /*! @name INT - Interrupt */ /*! @{ */ #define USB3_INT_XHCI_INT_EN_MASK (0xFFU) #define USB3_INT_XHCI_INT_EN_SHIFT (0U) /*! XHCI_INT_EN - xHCI Interrupt Enable */ #define USB3_INT_XHCI_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_XHCI_INT_EN_SHIFT)) & USB3_INT_XHCI_INT_EN_MASK) #define USB3_INT_DEV_INT_EN_MASK (0x300U) #define USB3_INT_DEV_INT_EN_SHIFT (8U) /*! DEV_INT_EN - Device Interrupts Enable */ #define USB3_INT_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_DEV_INT_EN_SHIFT)) & USB3_INT_DEV_INT_EN_MASK) #define USB3_INT_OTG_INT_EN_MASK (0x400U) #define USB3_INT_OTG_INT_EN_SHIFT (10U) /*! OTG_INT_EN - OTG Interrupt Enable */ #define USB3_INT_OTG_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_OTG_INT_EN_SHIFT)) & USB3_INT_OTG_INT_EN_MASK) #define USB3_INT_LTM_HOST_EN_MASK (0x800U) #define USB3_INT_LTM_HOST_EN_SHIFT (11U) /*! LTM_HOST_EN - LTM(Latency Tolerance messaging) request Interrupt Enable */ #define USB3_INT_LTM_HOST_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_LTM_HOST_EN_SHIFT)) & USB3_INT_LTM_HOST_EN_MASK) #define USB3_INT_OTG_WAKEUP_EN_MASK (0x1000U) #define USB3_INT_OTG_WAKEUP_EN_SHIFT (12U) /*! OTG_WAKEUP_EN - OTG Wakeup Enable */ #define USB3_INT_OTG_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_OTG_WAKEUP_EN_SHIFT)) & USB3_INT_OTG_WAKEUP_EN_MASK) #define USB3_INT_DEVU3_WAKEUP_EN_MASK (0x4000U) #define USB3_INT_DEVU3_WAKEUP_EN_SHIFT (14U) /*! DEVU3_WAKEUP_EN - Device U3 Wakeup Enable */ #define USB3_INT_DEVU3_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_DEVU3_WAKEUP_EN_SHIFT)) & USB3_INT_DEVU3_WAKEUP_EN_MASK) #define USB3_INT_DEV_WAKEUP_MASK (0x8000U) #define USB3_INT_DEV_WAKEUP_SHIFT (15U) /*! DEV_WAKEUP - connect to wakeup of device core */ #define USB3_INT_DEV_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_DEV_WAKEUP_SHIFT)) & USB3_INT_DEV_WAKEUP_MASK) #define USB3_INT_INTERRUPT_REQ_MASK (0xFF0000U) #define USB3_INT_INTERRUPT_REQ_SHIFT (16U) /*! INTERRUPT_REQ - xHCI Interrupts */ #define USB3_INT_INTERRUPT_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_INTERRUPT_REQ_SHIFT)) & USB3_INT_INTERRUPT_REQ_MASK) #define USB3_INT_DEV_IRQS_MASK (0x3000000U) #define USB3_INT_DEV_IRQS_SHIFT (24U) /*! DEV_IRQS - Device interrupts */ #define USB3_INT_DEV_IRQS(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_DEV_IRQS_SHIFT)) & USB3_INT_DEV_IRQS_MASK) #define USB3_INT_OTGIRQ_MASK (0x4000000U) #define USB3_INT_OTGIRQ_SHIFT (26U) /*! OTGIRQ - OTG interrupts */ #define USB3_INT_OTGIRQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_OTGIRQ_SHIFT)) & USB3_INT_OTGIRQ_MASK) #define USB3_INT_LTM_HOST_REQ_MASK (0x8000000U) #define USB3_INT_LTM_HOST_REQ_SHIFT (27U) /*! LTM_HOST_REQ - LTM Request Interrupt */ #define USB3_INT_LTM_HOST_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_LTM_HOST_REQ_SHIFT)) & USB3_INT_LTM_HOST_REQ_MASK) #define USB3_INT_LPM_HOST_REQ_MASK (0x10000000U) #define USB3_INT_LPM_HOST_REQ_SHIFT (28U) /*! LPM_HOST_REQ - indicate usb3core request lpm_clkc */ #define USB3_INT_LPM_HOST_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_LPM_HOST_REQ_SHIFT)) & USB3_INT_LPM_HOST_REQ_MASK) #define USB3_INT_CLK_125_REQ_MASK (0x20000000U) #define USB3_INT_CLK_125_REQ_SHIFT (29U) /*! CLK_125_REQ - indicate usb3core request 125MHz clock */ #define USB3_INT_CLK_125_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_CLK_125_REQ_SHIFT)) & USB3_INT_CLK_125_REQ_MASK) #define USB3_INT_PHY_REFCLK_REQ_MASK (0x40000000U) #define USB3_INT_PHY_REFCLK_REQ_SHIFT (30U) /*! PHY_REFCLK_REQ - indicate PHY request reference clock */ #define USB3_INT_PHY_REFCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_INT_PHY_REFCLK_REQ_SHIFT)) & USB3_INT_PHY_REFCLK_REQ_MASK) /*! @} */ /*! @name CORE_STATUS - Core Status */ /*! @{ */ #define USB3_CORE_STATUS_LOWEST_BELT_MASK (0xFFFU) #define USB3_CORE_STATUS_LOWEST_BELT_SHIFT (0U) /*! LOWEST_BELT - lowexst BELT value from xhci core */ #define USB3_CORE_STATUS_LOWEST_BELT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_STATUS_LOWEST_BELT_SHIFT)) & USB3_CORE_STATUS_LOWEST_BELT_MASK) #define USB3_CORE_STATUS_XHCI_POWER_ON_READY_MASK (0x1000U) #define USB3_CORE_STATUS_XHCI_POWER_ON_READY_SHIFT (12U) /*! XHCI_POWER_ON_READY - xhci ready, SW should wait it to be 1 before access any xhci registers */ #define USB3_CORE_STATUS_XHCI_POWER_ON_READY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_STATUS_XHCI_POWER_ON_READY_SHIFT)) & USB3_CORE_STATUS_XHCI_POWER_ON_READY_MASK) #define USB3_CORE_STATUS_USBDEV_POWER_ON_READY_MASK (0x2000U) #define USB3_CORE_STATUS_USBDEV_POWER_ON_READY_SHIFT (13U) /*! USBDEV_POWER_ON_READY - device ready, SW should wait it to be 1 before access any device registers */ #define USB3_CORE_STATUS_USBDEV_POWER_ON_READY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_STATUS_USBDEV_POWER_ON_READY_SHIFT)) & USB3_CORE_STATUS_USBDEV_POWER_ON_READY_MASK) #define USB3_CORE_STATUS_XHC_D0_ACK_MASK (0x4000U) #define USB3_CORE_STATUS_XHC_D0_ACK_SHIFT (14U) /*! XHC_D0_ACK - Acknowledge for D0 state entry request indicating that Host entered D0 state. Once * asserted, will be held high until xhc_d0_req is de-asserted */ #define USB3_CORE_STATUS_XHC_D0_ACK(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_STATUS_XHC_D0_ACK_SHIFT)) & USB3_CORE_STATUS_XHC_D0_ACK_MASK) #define USB3_CORE_STATUS_MDCTRL_CLK_STATUS_MASK (0x8000U) #define USB3_CORE_STATUS_MDCTRL_CLK_STATUS_SHIFT (15U) /*! MDCTRL_CLK_STATUS - Status from USBSS-DRD to indicate on which clock OTG logic is currently * running. Change on this signal can be considered as an acknowledge for the mdctrl_clk_sel. * 0b1..OTG logic is currently running on the stb_clk_predft (32Khz) clock * 0b0..OTG logic is currently running on the otg_fast_clk. */ #define USB3_CORE_STATUS_MDCTRL_CLK_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_STATUS_MDCTRL_CLK_STATUS_SHIFT)) & USB3_CORE_STATUS_MDCTRL_CLK_STATUS_MASK) /*! @} */ /*! @name OTGCMD - OTG Command */ /*! @{ */ #define USB3_OTGCMD_DEV_BUS_REQ_MASK (0x1U) #define USB3_OTGCMD_DEV_BUS_REQ_SHIFT (0U) /*! DEV_BUS_REQ - Request the bus for Device mode. It will set DEV_ACTIVE bit is OTGSTS */ #define USB3_OTGCMD_DEV_BUS_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_BUS_REQ_SHIFT)) & USB3_OTGCMD_DEV_BUS_REQ_MASK) #define USB3_OTGCMD_HOST_BUS_REQ_MASK (0x2U) #define USB3_OTGCMD_HOST_BUS_REQ_SHIFT (1U) /*! HOST_BUS_REQ - Request the bus for Host mode. It will set HOST_ACTIVE bit is OTGSTS */ #define USB3_OTGCMD_HOST_BUS_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_HOST_BUS_REQ_SHIFT)) & USB3_OTGCMD_HOST_BUS_REQ_MASK) #define USB3_OTGCMD_OTG_EN_MASK (0x4U) #define USB3_OTGCMD_OTG_EN_SHIFT (2U) /*! OTG_EN - Enable OTG mode. It will set OTG_IS_ENABLED bit is OTGSTS */ #define USB3_OTGCMD_OTG_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_OTG_EN_SHIFT)) & USB3_OTGCMD_OTG_EN_MASK) #define USB3_OTGCMD_OTG_DIS_MASK (0x8U) #define USB3_OTGCMD_OTG_DIS_SHIFT (3U) /*! OTG_DIS - Disable OTG mode. It will clear OTG_IS_ENABLED bit is OTGSTS */ #define USB3_OTGCMD_OTG_DIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_OTG_DIS_SHIFT)) & USB3_OTGCMD_OTG_DIS_MASK) #define USB3_OTGCMD_A_DEV_EN_MASK (0x10U) #define USB3_OTGCMD_A_DEV_EN_SHIFT (4U) /*! A_DEV_EN - Configure OTG as A-Device. It is only valid if OTG mode is enabled. This bit should be set in the same time when OTG_EN */ #define USB3_OTGCMD_A_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_DEV_EN_SHIFT)) & USB3_OTGCMD_A_DEV_EN_MASK) #define USB3_OTGCMD_A_DEV_DIS_MASK (0x20U) #define USB3_OTGCMD_A_DEV_DIS_SHIFT (5U) /*! A_DEV_DIS - Configure OTG as B-Device. It is only valid if OTG mode is enabled. This bit should be set in the same time when OTG_EN */ #define USB3_OTGCMD_A_DEV_DIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_DEV_DIS_SHIFT)) & USB3_OTGCMD_A_DEV_DIS_MASK) #define USB3_OTGCMD_DEV_SESS_VLD_USE_SET_MASK (0x40U) #define USB3_OTGCMD_DEV_SESS_VLD_USE_SET_SHIFT (6U) /*! DEV_SESS_VLD_USE_SET - Device should use b_sess_vld as vbus valid indication. This bit should be set in the same time when DEV_BUS_REQ */ #define USB3_OTGCMD_DEV_SESS_VLD_USE_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_SESS_VLD_USE_SET_SHIFT)) & USB3_OTGCMD_DEV_SESS_VLD_USE_SET_MASK) #define USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_MASK (0x80U) #define USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_SHIFT (7U) /*! DEV_SESS_VLD_USE_CLR - Device should use a_vbus_vld as vbus valid indication. This bit should be set in the same time when DEV_BUS_REQ */ #define USB3_OTGCMD_DEV_SESS_VLD_USE_CLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_SHIFT)) & USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_MASK) #define USB3_OTGCMD_DEV_BUS_DROP_MASK (0x100U) #define USB3_OTGCMD_DEV_BUS_DROP_SHIFT (8U) /*! DEV_BUS_DROP - Drop the bus for Device mode. This bit should be set when Device mode is no * longer needed. It will clear DEV_ACTIVE bit is OTGSTS */ #define USB3_OTGCMD_DEV_BUS_DROP(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_BUS_DROP_SHIFT)) & USB3_OTGCMD_DEV_BUS_DROP_MASK) #define USB3_OTGCMD_HOST_BUS_DROP_MASK (0x200U) #define USB3_OTGCMD_HOST_BUS_DROP_SHIFT (9U) /*! HOST_BUS_DROP - Drop the bus for Host mode. This bit should be set when Host mode is no longer * needed. It will clear HOST_ACTIVE bit is OTGSTS */ #define USB3_OTGCMD_HOST_BUS_DROP(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_HOST_BUS_DROP_SHIFT)) & USB3_OTGCMD_HOST_BUS_DROP_MASK) #define USB3_OTGCMD_DIS_VBUS_DROP_MASK (0x400U) #define USB3_OTGCMD_DIS_VBUS_DROP_SHIFT (10U) /*! DIS_VBUS_DROP - Do not disable vbus while bus is dropped. This bit is valid only if DEV_BUS_DROP or HOST_BUS_DROP are set */ #define USB3_OTGCMD_DIS_VBUS_DROP(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DIS_VBUS_DROP_SHIFT)) & USB3_OTGCMD_DIS_VBUS_DROP_MASK) #define USB3_OTGCMD_DEV_POWER_OFF_MASK (0x800U) #define USB3_OTGCMD_DEV_POWER_OFF_SHIFT (11U) /*! DEV_POWER_OFF - Power Down USBSS-DEV */ #define USB3_OTGCMD_DEV_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_POWER_OFF_SHIFT)) & USB3_OTGCMD_DEV_POWER_OFF_MASK) #define USB3_OTGCMD_HOST_POWER_OFF_MASK (0x1000U) #define USB3_OTGCMD_HOST_POWER_OFF_SHIFT (12U) /*! HOST_POWER_OFF - Power Down CDNSXHCI */ #define USB3_OTGCMD_HOST_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_HOST_POWER_OFF_SHIFT)) & USB3_OTGCMD_HOST_POWER_OFF_MASK) #define USB3_OTGCMD_DEV_DEVEN_FORCE_SET_MASK (0x2000U) #define USB3_OTGCMD_DEV_DEVEN_FORCE_SET_SHIFT (13U) /*! DEV_DEVEN_FORCE_SET - Set forcing Device DEVEN bit to 1. This bit may be set while switching * from Host to Device mode takes place. Setting this bit should be done in the same time when * Device mode is activated (DEV_BUS_REQ). Setting this bit causes DEV_DEVEN_FORCE bit in OTGSTS set */ #define USB3_OTGCMD_DEV_DEVEN_FORCE_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_DEVEN_FORCE_SET_SHIFT)) & USB3_OTGCMD_DEV_DEVEN_FORCE_SET_MASK) #define USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_MASK (0x4000U) #define USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_SHIFT (14U) /*! DEV_DEVEN_FORCE_CLR - Clear forcing Device DEVEN bit to 1. Setting this bit causes DEV_DEVEN_FORCE bit in OTGSTS clear */ #define USB3_OTGCMD_DEV_DEVEN_FORCE_CLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_SHIFT)) & USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_MASK) #define USB3_OTGCMD_H_WRST_FOR_SWAP_SET_MASK (0x8000U) #define USB3_OTGCMD_H_WRST_FOR_SWAP_SET_SHIFT (15U) /*! H_WRST_FOR_SWAP_SET - Upcoming Warm Reset will be generated for Role Swapping. This bit should * be set before Warm Reset for Role Swap is generated on the Port */ #define USB3_OTGCMD_H_WRST_FOR_SWAP_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_H_WRST_FOR_SWAP_SET_SHIFT)) & USB3_OTGCMD_H_WRST_FOR_SWAP_SET_MASK) #define USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_MASK (0x10000U) #define USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_SHIFT (16U) /*! H_WRST_FOR_SWAP_CLR - Upcoming Warm Reset will not be generated for Role Swapping. This bit * should be set after Warm Reset for Role Swap is generated on the Port */ #define USB3_OTGCMD_H_WRST_FOR_SWAP_CLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_SHIFT)) & USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_MASK) #define USB3_OTGCMD_D_WRST_FOR_SWAP_SET_MASK (0x20000U) #define USB3_OTGCMD_D_WRST_FOR_SWAP_SET_SHIFT (17U) /*! D_WRST_FOR_SWAP_SET - Upcoming Warm Reset will be received for Role Swapping. This bit should be * set before Warm Reset for Role Swap is received on the Port */ #define USB3_OTGCMD_D_WRST_FOR_SWAP_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_D_WRST_FOR_SWAP_SET_SHIFT)) & USB3_OTGCMD_D_WRST_FOR_SWAP_SET_MASK) #define USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_MASK (0x40000U) #define USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_SHIFT (18U) /*! D_WRST_FOR_SWAP_CLR - Upcoming received Warm Reset should not be treated as Role Swapping * indication. This bit should be set after Warm Reset for Role Swap is received on the Port */ #define USB3_OTGCMD_D_WRST_FOR_SWAP_CLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_SHIFT)) & USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_MASK) #define USB3_OTGCMD_SS_HOST_DISABLED_SET_MASK (0x80000U) #define USB3_OTGCMD_SS_HOST_DISABLED_SET_SHIFT (19U) /*! SS_HOST_DISABLED_SET - Disable SuperSpeed host functionality. Can be used only if Host mode is not active */ #define USB3_OTGCMD_SS_HOST_DISABLED_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_HOST_DISABLED_SET_SHIFT)) & USB3_OTGCMD_SS_HOST_DISABLED_SET_MASK) #define USB3_OTGCMD_SS_HOST_DISABLED_CLR_MASK (0x100000U) #define USB3_OTGCMD_SS_HOST_DISABLED_CLR_SHIFT (20U) /*! SS_HOST_DISABLED_CLR - Enable SuperSpeed host functionality */ #define USB3_OTGCMD_SS_HOST_DISABLED_CLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_HOST_DISABLED_CLR_SHIFT)) & USB3_OTGCMD_SS_HOST_DISABLED_CLR_MASK) #define USB3_OTGCMD_SS_PERIPH_DISABLED_SET_MASK (0x200000U) #define USB3_OTGCMD_SS_PERIPH_DISABLED_SET_SHIFT (21U) /*! SS_PERIPH_DISABLED_SET - Disable SuperSpeed peripheral device functionality. Can be used only if Peripheral mode is not active */ #define USB3_OTGCMD_SS_PERIPH_DISABLED_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_PERIPH_DISABLED_SET_SHIFT)) & USB3_OTGCMD_SS_PERIPH_DISABLED_SET_MASK) #define USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_MASK (0x400000U) #define USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_SHIFT (22U) /*! SS_PERIPH_DISABLED_CLR - Enable SuperSpeed peripheral device functionality */ #define USB3_OTGCMD_SS_PERIPH_DISABLED_CLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_SHIFT)) & USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_MASK) #define USB3_OTGCMD_A_SET_B_HNP_EN_SET_MASK (0x800000U) #define USB3_OTGCMD_A_SET_B_HNP_EN_SET_SHIFT (23U) /*! A_SET_B_HNP_EN_SET - This bit should be written if SetFeature(b_hnp_enable) has been sent */ #define USB3_OTGCMD_A_SET_B_HNP_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_SET_B_HNP_EN_SET_SHIFT)) & USB3_OTGCMD_A_SET_B_HNP_EN_SET_MASK) #define USB3_OTGCMD_A_SET_B_HNP_EN_CLR_MASK (0x1000000U) #define USB3_OTGCMD_A_SET_B_HNP_EN_CLR_SHIFT (24U) /*! A_SET_B_HNP_EN_CLR - This bit should be written if upcoming USB 2.0 bus suspend should not cause Role Swap */ #define USB3_OTGCMD_A_SET_B_HNP_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_SET_B_HNP_EN_CLR_SHIFT)) & USB3_OTGCMD_A_SET_B_HNP_EN_CLR_MASK) #define USB3_OTGCMD_B_HNP_EN_SET_MASK (0x2000000U) #define USB3_OTGCMD_B_HNP_EN_SET_SHIFT (25U) /*! B_HNP_EN_SET - This bit should be written if SetFeature(b_hnp_enable) has been accepted */ #define USB3_OTGCMD_B_HNP_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_B_HNP_EN_SET_SHIFT)) & USB3_OTGCMD_B_HNP_EN_SET_MASK) #define USB3_OTGCMD_B_HNP_EN_CLR_MASK (0x4000000U) #define USB3_OTGCMD_B_HNP_EN_CLR_SHIFT (26U) /*! B_HNP_EN_CLR - This bit should be written if software wants to clear b_hnp_enable */ #define USB3_OTGCMD_B_HNP_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_B_HNP_EN_CLR_SHIFT)) & USB3_OTGCMD_B_HNP_EN_CLR_MASK) #define USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_MASK (0x8000000U) #define USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_SHIFT (27U) /*! OTG2_SWITCH_TO_PERIPH - Switch to Peripheral mode when operating at USB 2.0 */ #define USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_SHIFT)) & USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_MASK) #define USB3_OTGCMD_INIT_SRP_MASK (0x10000000U) #define USB3_OTGCMD_INIT_SRP_SHIFT (28U) /*! INIT_SRP - Initiate SRP */ #define USB3_OTGCMD_INIT_SRP(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_INIT_SRP_SHIFT)) & USB3_OTGCMD_INIT_SRP_MASK) #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_MASK (0x20000000U) #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_SHIFT (29U) /*! DEV_VBUS_DEB_SHORT_SET - Enable forcing Device short VBUS debounce time. This bit should be set * while switching from Host to Device mode takes place. Setting this bit should be done in the * same time when Device mode is activated (DEV_BUS_REQ). Setting this bit causes * DEV_VBUS_DEB_SHORT bit in OTGSTS set */ #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_SHIFT)) & USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_MASK) #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_MASK (0x40000000U) #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_SHIFT (30U) /*! DEV_VBUS_DEB_SHORT_CLR - Disable forcing Device short VBUS debounce time. Setting this bit causes DEV_VBUS_DEB_SHORT bit in OTGSTS clear */ #define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_SHIFT)) & USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_MASK) /*! @} */ /*! @name OTGSTS - OTG Status */ /*! @{ */ #define USB3_OTGSTS_ID_VALUE_MASK (0x1U) #define USB3_OTGSTS_ID_VALUE_SHIFT (0U) /*! ID_VALUE - Current value of the ID pin. It is only valid when idpullup in OTGCTRL1_TYPE register * is set to '1'. ID_VALUE must be valid within 50ms after idpullup is set to '1' */ #define USB3_OTGSTS_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_ID_VALUE_SHIFT)) & USB3_OTGSTS_ID_VALUE_MASK) #define USB3_OTGSTS_VBUS_VALID_MASK (0x2U) #define USB3_OTGSTS_VBUS_VALID_SHIFT (1U) /*! VBUS_VALID - Current value of the vbus_valid */ #define USB3_OTGSTS_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_VBUS_VALID_SHIFT)) & USB3_OTGSTS_VBUS_VALID_MASK) #define USB3_OTGSTS_SESSION_VALID_MASK (0x4U) #define USB3_OTGSTS_SESSION_VALID_SHIFT (2U) /*! SESSION_VALID - Current value of the b_sess_vld */ #define USB3_OTGSTS_SESSION_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SESSION_VALID_SHIFT)) & USB3_OTGSTS_SESSION_VALID_MASK) #define USB3_OTGSTS_DEV_ACTIVE_MASK (0x8U) #define USB3_OTGSTS_DEV_ACTIVE_SHIFT (3U) /*! DEV_ACTIVE - Device mode is active. NOTE: It is possible that Device is in inactive state (even turned off) while DEV_ACTIVE is 1 */ #define USB3_OTGSTS_DEV_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_ACTIVE_SHIFT)) & USB3_OTGSTS_DEV_ACTIVE_MASK) #define USB3_OTGSTS_HOST_ACTIVE_MASK (0x10U) #define USB3_OTGSTS_HOST_ACTIVE_SHIFT (4U) /*! HOST_ACTIVE - Device mode is active. NOTE: It is possible that Host is in inactive state (even turned off) while HOST_ACTIVE is 1 */ #define USB3_OTGSTS_HOST_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_HOST_ACTIVE_SHIFT)) & USB3_OTGSTS_HOST_ACTIVE_MASK) #define USB3_OTGSTS_OTG_IS_ENABLED_MASK (0x20U) #define USB3_OTGSTS_OTG_IS_ENABLED_SHIFT (5U) /*! OTG_IS_ENABLED - OTG functionality is enabled */ #define USB3_OTGSTS_OTG_IS_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_OTG_IS_ENABLED_SHIFT)) & USB3_OTGSTS_OTG_IS_ENABLED_MASK) #define USB3_OTGSTS_OTG_MODE_MASK (0x40U) #define USB3_OTGSTS_OTG_MODE_SHIFT (6U) /*! OTG_MODE - OTG mode: 0 - A-Device 1 - B-Device Valid only if OTG_IS_ENABLED is 1 */ #define USB3_OTGSTS_OTG_MODE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_OTG_MODE_SHIFT)) & USB3_OTGSTS_OTG_MODE_MASK) #define USB3_OTGSTS_SS_HOST_DISABLED_MASK (0x80U) #define USB3_OTGSTS_SS_HOST_DISABLED_SHIFT (7U) /*! SS_HOST_DISABLED - SuperSpeed host functionality is disabled. Port will be operating at USB 2.0 speed */ #define USB3_OTGSTS_SS_HOST_DISABLED(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SS_HOST_DISABLED_SHIFT)) & USB3_OTGSTS_SS_HOST_DISABLED_MASK) #define USB3_OTGSTS_SS_PERIPH_DISABLED_MASK (0x100U) #define USB3_OTGSTS_SS_PERIPH_DISABLED_SHIFT (8U) /*! SS_PERIPH_DISABLED - SuperSpeed device functionality is disabled. Port will be operating at USB 2.0 speed */ #define USB3_OTGSTS_SS_PERIPH_DISABLED(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SS_PERIPH_DISABLED_SHIFT)) & USB3_OTGSTS_SS_PERIPH_DISABLED_MASK) #define USB3_OTGSTS_DEV_VBUS_DEB_SHORT_MASK (0x200U) #define USB3_OTGSTS_DEV_VBUS_DEB_SHORT_SHIFT (9U) /*! DEV_VBUS_DEB_SHORT - Device forcing short VBUS decounce is enabled */ #define USB3_OTGSTS_DEV_VBUS_DEB_SHORT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_VBUS_DEB_SHORT_SHIFT)) & USB3_OTGSTS_DEV_VBUS_DEB_SHORT_MASK) #define USB3_OTGSTS_DEV_SESS_VLD_USE_MASK (0x400U) #define USB3_OTGSTS_DEV_SESS_VLD_USE_SHIFT (10U) /*! DEV_SESS_VLD_USE - Device mode vbus valid indication: 0: a_vbus_vld is used as vbus valid 1: b_sess_vld is used as vbus valid */ #define USB3_OTGSTS_DEV_SESS_VLD_USE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_SESS_VLD_USE_SHIFT)) & USB3_OTGSTS_DEV_SESS_VLD_USE_MASK) #define USB3_OTGSTS_OTG_NRDY_MASK (0x800U) #define USB3_OTGSTS_OTG_NRDY_SHIFT (11U) /*! OTG_NRDY - OTG Controller not ready. Software shall not read nor write any register except OTGISTS if this bit is set */ #define USB3_OTGSTS_OTG_NRDY(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_OTG_NRDY_SHIFT)) & USB3_OTGSTS_OTG_NRDY_MASK) #define USB3_OTGSTS_STRAP_MASK (0x7000U) #define USB3_OTGSTS_STRAP_SHIFT (12U) /*! STRAP - Value of the strap pins. 000 - no default configuration 010 - Controller initiall * configured as Host 100 - Controller initially configured as Device other - Reserved (might be used * for Type-C) */ #define USB3_OTGSTS_STRAP(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_STRAP_SHIFT)) & USB3_OTGSTS_STRAP_MASK) #define USB3_OTGSTS_H_WRST_FOR_SWAP_MASK (0x8000U) #define USB3_OTGSTS_H_WRST_FOR_SWAP_SHIFT (15U) /*! H_WRST_FOR_SWAP - Upcoming Warm Reset will be generated for Role Swapping from Host to Peripheral */ #define USB3_OTGSTS_H_WRST_FOR_SWAP(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_H_WRST_FOR_SWAP_SHIFT)) & USB3_OTGSTS_H_WRST_FOR_SWAP_MASK) #define USB3_OTGSTS_DEV_DEVEN_FORCE_MASK (0x10000U) #define USB3_OTGSTS_DEV_DEVEN_FORCE_SHIFT (16U) /*! DEV_DEVEN_FORCE - Device forcing DEVEN bit is enabled */ #define USB3_OTGSTS_DEV_DEVEN_FORCE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_DEVEN_FORCE_SHIFT)) & USB3_OTGSTS_DEV_DEVEN_FORCE_MASK) #define USB3_OTGSTS_D_WRST_FOR_SWAP_MASK (0x20000U) #define USB3_OTGSTS_D_WRST_FOR_SWAP_SHIFT (17U) /*! D_WRST_FOR_SWAP - Upcoming Warm Reset will be received for Role Swapping from Peripheral to Host */ #define USB3_OTGSTS_D_WRST_FOR_SWAP(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_D_WRST_FOR_SWAP_SHIFT)) & USB3_OTGSTS_D_WRST_FOR_SWAP_MASK) #define USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_MASK (0x40000U) #define USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_SHIFT (18U) /*! SRP_INITIAL_CONDITION_MET - SRP initial condition are met. OTG B-device software should issue SRP puluse onli if this bit is set */ #define USB3_OTGSTS_SRP_INITIAL_CONDITION_MET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_SHIFT)) & USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_MASK) #define USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_MASK (0x80000U) #define USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_SHIFT (19U) /*! SRP_DET_NOT_COMPLIANT_DEV - OTG A-device detected not compilant device. If this bit is set then * OTG A-device should disable SRP detection until not compilant device is disconnected * (SRP_NOT_COMP_DEV_REMOVED_INT) */ #define USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_SHIFT)) & USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_MASK) #define USB3_OTGSTS_A_SET_B_HNP_EN_MASK (0x800000U) #define USB3_OTGSTS_A_SET_B_HNP_EN_SHIFT (23U) /*! A_SET_B_HNP_EN - SetFeature(b_hnp_enable) has been sent and is valid */ #define USB3_OTGSTS_A_SET_B_HNP_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_A_SET_B_HNP_EN_SHIFT)) & USB3_OTGSTS_A_SET_B_HNP_EN_MASK) #define USB3_OTGSTS_B_HNP_EN_MASK (0x2000000U) #define USB3_OTGSTS_B_HNP_EN_SHIFT (25U) /*! B_HNP_EN - SetFeature(b_hnp_enable) has been accepted */ #define USB3_OTGSTS_B_HNP_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_B_HNP_EN_SHIFT)) & USB3_OTGSTS_B_HNP_EN_MASK) #define USB3_OTGSTS_XHC_READY_MASK (0x4000000U) #define USB3_OTGSTS_XHC_READY_SHIFT (26U) /*! XHC_READY - Host mode is turned on; registers in CDNSXHCI AUX domain are accessible through APB */ #define USB3_OTGSTS_XHC_READY(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_XHC_READY_SHIFT)) & USB3_OTGSTS_XHC_READY_MASK) #define USB3_OTGSTS_DEV_READY_MASK (0x8000000U) #define USB3_OTGSTS_DEV_READY_SHIFT (27U) /*! DEV_READY - Device mode is turned on; registers in USBSS-DEV domain are accessible through APB */ #define USB3_OTGSTS_DEV_READY(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_READY_SHIFT)) & USB3_OTGSTS_DEV_READY_MASK) /*! @} */ /*! @name OTGSTATE - OTG State */ /*! @{ */ #define USB3_OTGSTATE_DEV_OTG_STATE_MASK (0x7U) #define USB3_OTGSTATE_DEV_OTG_STATE_SHIFT (0U) /*! DEV_OTG_STATE - Current state of the OTG Device FSM * 0b000..DEV_IDLE * 0b001..DEV_MODE * 0b010..DEV_SRP * 0b011..DEV_WAIT_VBUS_FALL * 0b100..DEV_SWITCH_TO_HOST * 0b101..DEV_WAIT_FOR_CONN */ #define USB3_OTGSTATE_DEV_OTG_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_DEV_OTG_STATE_SHIFT)) & USB3_OTGSTATE_DEV_OTG_STATE_MASK) #define USB3_OTGSTATE_HOST_OTG_STATE_MASK (0x38U) #define USB3_OTGSTATE_HOST_OTG_STATE_SHIFT (3U) /*! HOST_OTG_STATE - Current state of the OTG Host FSM * 0b000..H_IDLE * 0b001..H_VBUS_ON * 0b010..H_VBUS_FAILED * 0b011..H_OTG_HOST_MODE * 0b100..H_HOST_MODE * 0b101..H_SWITCH_TO_DEVICE * 0b110..H_A_SUSPEND * 0b111..H_WAIT_VBUS_FALL */ #define USB3_OTGSTATE_HOST_OTG_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_HOST_OTG_STATE_SHIFT)) & USB3_OTGSTATE_HOST_OTG_STATE_MASK) #define USB3_OTGSTATE_APB_AXI_CTRL_MASK (0x300U) #define USB3_OTGSTATE_APB_AXI_CTRL_SHIFT (8U) /*! APB_AXI_CTRL - Current state of the ABP/AXI mux selector * 0b00..Both modes off * 0b01..Host Active * 0b10..Device Active * 0b11..Illegal(Both modes off) */ #define USB3_OTGSTATE_APB_AXI_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_APB_AXI_CTRL_SHIFT)) & USB3_OTGSTATE_APB_AXI_CTRL_MASK) #define USB3_OTGSTATE_PIPE_CTRL_MASK (0xC00U) #define USB3_OTGSTATE_PIPE_CTRL_SHIFT (10U) /*! PIPE_CTRL - Current state of the USB3 PIPE mux selector * 0b00..Both modes off * 0b01..Host Active * 0b10..Device Active * 0b11..Illegal(both modes off) */ #define USB3_OTGSTATE_PIPE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PIPE_CTRL_SHIFT)) & USB3_OTGSTATE_PIPE_CTRL_MASK) #define USB3_OTGSTATE_UTMI_CTRL_MASK (0x3000U) #define USB3_OTGSTATE_UTMI_CTRL_SHIFT (12U) /*! UTMI_CTRL - Current state of the USB2 UTMI mux selector * 0b00..Both modes off, and OTG takes control over UTMI (SRP,BC) * 0b01..Host Active * 0b10..Device Active * 0b11..Illegal(both modes off) */ #define USB3_OTGSTATE_UTMI_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_UTMI_CTRL_SHIFT)) & USB3_OTGSTATE_UTMI_CTRL_MASK) #define USB3_OTGSTATE_DEV_POWER_STATE_MASK (0x70000U) #define USB3_OTGSTATE_DEV_POWER_STATE_SHIFT (16U) /*! DEV_POWER_STATE - Current state of the Device power controlling FSM * 0b000..POWER_IDLE * 0b001..POWER_OFF_ACK * 0b010..POWER_OFF_MAIN_ACK * 0b011..POWER_OFF * 0b100..POWER_ON_REQ * 0b101..POWER_ISO_DIS * 0b110..POWER_ON * 0b111..POWER_ON_READY */ #define USB3_OTGSTATE_DEV_POWER_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_DEV_POWER_STATE_SHIFT)) & USB3_OTGSTATE_DEV_POWER_STATE_MASK) #define USB3_OTGSTATE_HOST_POWER_STATE_MASK (0x380000U) #define USB3_OTGSTATE_HOST_POWER_STATE_SHIFT (19U) /*! HOST_POWER_STATE - Current state of the Host power controlling FSM * 0b000..POWER_IDLE * 0b001..POWER_OFF_ACK * 0b010..POWER_OFF_MAIN_ACK * 0b011..POWER_OFF * 0b100..POWER_ON_REQ * 0b101..POWER_ISO_DIS * 0b110..POWER_ON * 0b111..POWER_ON_READY */ #define USB3_OTGSTATE_HOST_POWER_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_HOST_POWER_STATE_SHIFT)) & USB3_OTGSTATE_HOST_POWER_STATE_MASK) #define USB3_OTGSTATE_PHY_REFCLK_REQ_MASK (0x1000000U) #define USB3_OTGSTATE_PHY_REFCLK_REQ_SHIFT (24U) /*! PHY_REFCLK_REQ - Value of the phy_refclk_req signal from the PHY Reference Clock Control interface */ #define USB3_OTGSTATE_PHY_REFCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PHY_REFCLK_REQ_SHIFT)) & USB3_OTGSTATE_PHY_REFCLK_REQ_MASK) #define USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_MASK (0x2000000U) #define USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_SHIFT (25U) /*! PHY_REFCLK_1PCT_VALID - Value of the phy_refclk_1pct_valid signal from the PHY Reference Clock Control interface */ #define USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_SHIFT)) & USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_MASK) #define USB3_OTGSTATE_PHY_REFCLK_VALID_MASK (0x4000000U) #define USB3_OTGSTATE_PHY_REFCLK_VALID_SHIFT (26U) /*! PHY_REFCLK_VALID - Value of the phy_refclk_valid signal from the PHY Reference Clock Control interface */ #define USB3_OTGSTATE_PHY_REFCLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PHY_REFCLK_VALID_SHIFT)) & USB3_OTGSTATE_PHY_REFCLK_VALID_MASK) #define USB3_OTGSTATE_REFCLK_FSM_MASK (0x38000000U) #define USB3_OTGSTATE_REFCLK_FSM_SHIFT (27U) /*! REFCLK_FSM - Reference Clock control FSM state * 0b000..IDLE * 0b001..SWITCH32_GATE_ON * 0b010..REFCLK_OFF * 0b011..REFCLK_REQ * 0b100..GATE_OFF * 0b101..REFCLK_ON_SWITCH32 * 0b110..REFCLK_ON_PHY3_AT_SLOW * 0b111..REFCLK_ON_SWITCH24 */ #define USB3_OTGSTATE_REFCLK_FSM(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_REFCLK_FSM_SHIFT)) & USB3_OTGSTATE_REFCLK_FSM_MASK) /*! @} */ /*! @name OTGREFCLK - OTG Reference Clock */ /*! @{ */ #define USB3_OTGREFCLK_P3_TO_REFCLK_REQ_MASK (0x3FFFU) #define USB3_OTGREFCLK_P3_TO_REFCLK_REQ_SHIFT (0U) /*! P3_TO_REFCLK_REQ - Time in stb_clk_predft clock period units within which the module won't be * requesting for Reference Clock to be off after USB 3.0 PHY powerdown changes to P3 */ #define USB3_OTGREFCLK_P3_TO_REFCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGREFCLK_P3_TO_REFCLK_REQ_SHIFT)) & USB3_OTGREFCLK_P3_TO_REFCLK_REQ_MASK) #define USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_MASK (0x3FFF0000U) #define USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_SHIFT (16U) /*! SUSPEND_TO_REFCLK_REQ - Time in stb_clk_predft clock period units within which the module won't * be requesting for Reference Clock to be off after USB 2.0 PHY is requested to enter suspend * (L2) state */ #define USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_SHIFT)) & USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_MASK) #define USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_MASK (0x80000000U) #define USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_SHIFT (31U) /*! OTG_STB_CLK_SWITCH_EN - Allow PHY Reference Clock sour to be either low frequency of turned-off when both modes (Host/Device) are disabled */ #define USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_SHIFT)) & USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_MASK) /*! @} */ /*! @name OTGIEN - OTG Interrupt Enable */ /*! @{ */ #define USB3_OTGIEN_ID_CHANGE_INT_EN_MASK (0x1U) #define USB3_OTGIEN_ID_CHANGE_INT_EN_SHIFT (0U) /*! ID_CHANGE_INT_EN - ID change interrupt enable */ #define USB3_OTGIEN_ID_CHANGE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_ID_CHANGE_INT_EN_SHIFT)) & USB3_OTGIEN_ID_CHANGE_INT_EN_MASK) #define USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_MASK (0x2U) #define USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_SHIFT (1U) /*! VBUS_ON_FAILED_INT_EN - Enabling Vbus by A-Device has failed interrupt enable */ #define USB3_OTGIEN_VBUS_ON_FAILED_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_SHIFT)) & USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_MASK) #define USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_MASK (0x4U) #define USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_SHIFT (2U) /*! OTGSESSVALID_RISE_INT_EN - Otgsessvalid rise detected interrupt enable */ #define USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_MASK) #define USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_MASK (0x8U) #define USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_SHIFT (3U) /*! OTGSESSVALID_FALL_INT_EN - Otgsessvalid fall detected interrupt enable */ #define USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_MASK) #define USB3_OTGIEN_VBUSVALID_RISE_INT_EN_MASK (0x10U) #define USB3_OTGIEN_VBUSVALID_RISE_INT_EN_SHIFT (4U) /*! VBUSVALID_RISE_INT_EN - Vbusvalid fall detected interrupt enable */ #define USB3_OTGIEN_VBUSVALID_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_VBUSVALID_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_VBUSVALID_RISE_INT_EN_MASK) #define USB3_OTGIEN_VBUSVALID_FALL_INT_EN_MASK (0x20U) #define USB3_OTGIEN_VBUSVALID_FALL_INT_EN_SHIFT (5U) /*! VBUSVALID_FALL_INT_EN - Vbusvalid fall detected interrupt enable */ #define USB3_OTGIEN_VBUSVALID_FALL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_VBUSVALID_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_VBUSVALID_FALL_INT_EN_MASK) #define USB3_OTGIEN_SENSE_RISE_INT_EN_MASK (0x40U) #define USB3_OTGIEN_SENSE_RISE_INT_EN_SHIFT (6U) /*! SENSE_RISE_INT_EN - ADP sense comparator rise detected interrupt enable */ #define USB3_OTGIEN_SENSE_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SENSE_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_SENSE_RISE_INT_EN_MASK) #define USB3_OTGIEN_PROBE_RISE_INT_EN_MASK (0x80U) #define USB3_OTGIEN_PROBE_RISE_INT_EN_SHIFT (7U) /*! PROBE_RISE_INT_EN - ADP probe comparator rise detected interrupt enable */ #define USB3_OTGIEN_PROBE_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_PROBE_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_PROBE_RISE_INT_EN_MASK) #define USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_MASK (0x100U) #define USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_SHIFT (8U) /*! ADP_PROBE_COMPLETED_INT_EN - ADP probe completed interrupt enable */ #define USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_SHIFT)) & USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_MASK) #define USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_MASK (0x200U) #define USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_SHIFT (9U) /*! TA_AIDL_BDIS_TMOUT_INT_EN - No response from B-Device for HNP interrupt enable */ #define USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_MASK) #define USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_MASK (0x400U) #define USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_SHIFT (10U) /*! TA_BIDL_ADIS_TMOUT_INT_EN - No activity from B-Device timeout interrupt enable */ #define USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_MASK) #define USB3_OTGIEN_SRP_DET_INT_EN_MASK (0x800U) #define USB3_OTGIEN_SRP_DET_INT_EN_SHIFT (11U) /*! SRP_DET_INT_EN - SRP pulse detected interrupt enable. NOTE: SRP detection can be enabled only if * core is enabled to work as a A-device (OTGSTS.OTG_MODE=0) */ #define USB3_OTGIEN_SRP_DET_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_DET_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_DET_INT_EN_MASK) #define USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_MASK (0x1000U) #define USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_SHIFT (12U) /*! SRP_NOT_COMP_DEV_REMOVED_INT_EN - Non cmpliant device disconnect interrupt enable */ #define USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_MASK) #define USB3_OTGIEN_OVERCURRENT_INT_EN_MASK (0x2000U) #define USB3_OTGIEN_OVERCURRENT_INT_EN_SHIFT (13U) /*! OVERCURRENT_INT_EN - Overcurrent condition detected interrupt enable */ #define USB3_OTGIEN_OVERCURRENT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_OVERCURRENT_INT_EN_SHIFT)) & USB3_OTGIEN_OVERCURRENT_INT_EN_MASK) #define USB3_OTGIEN_SRP_FAIL_INT_EN_MASK (0x4000U) #define USB3_OTGIEN_SRP_FAIL_INT_EN_SHIFT (14U) /*! SRP_FAIL_INT_EN - No response from SRP from A-Device interrupt enable */ #define USB3_OTGIEN_SRP_FAIL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_FAIL_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_FAIL_INT_EN_MASK) #define USB3_OTGIEN_SRP_CMPL_INT_EN_MASK (0x8000U) #define USB3_OTGIEN_SRP_CMPL_INT_EN_SHIFT (15U) /*! SRP_CMPL_INT_EN - SRP completed interrupt enable */ #define USB3_OTGIEN_SRP_CMPL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_CMPL_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_CMPL_INT_EN_MASK) #define USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_MASK (0x10000U) #define USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_SHIFT (16U) /*! TB_ASE0_BRST_TMOUT_INT_EN - No response from A-Device to HNP interrupt enable */ #define USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_MASK) #define USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_MASK (0x20000U) #define USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_SHIFT (17U) /*! TB_AIDL_BDIS_MIN_TMOUT_INT_EN - The bus has been in Idle state for the required time during HNP interrupt enable */ #define USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_MASK) #define USB3_OTGIEN_TIMER_TMOUT_INT_EN_MASK (0x40000U) #define USB3_OTGIEN_TIMER_TMOUT_INT_EN_SHIFT (18U) /*! TIMER_TMOUT_INT_EN - Timer timeout interrupt enable */ #define USB3_OTGIEN_TIMER_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TIMER_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TIMER_TMOUT_INT_EN_MASK) #define USB3_OTGIEN_H_POLL_ENTRY_INT_EN_MASK (0x80000U) #define USB3_OTGIEN_H_POLL_ENTRY_INT_EN_SHIFT (19U) /*! H_POLL_ENTRY_INT_EN - Host Polling state entry interrupt enable */ #define USB3_OTGIEN_H_POLL_ENTRY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_H_POLL_ENTRY_INT_EN_SHIFT)) & USB3_OTGIEN_H_POLL_ENTRY_INT_EN_MASK) #define USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_MASK (0x100000U) #define USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_SHIFT (20U) /*! H_WRST_GEN_CMPL_INT_EN - Host Warm Reset generation completed interrupt enable */ #define USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_SHIFT)) & USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_MASK) #define USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_MASK (0x200000U) #define USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_SHIFT (21U) /*! RID_FLOAT_FALL_INT_EN - RID floating comparator detect interrupt enable */ #define USB3_OTGIEN_RID_FLOAT_FALL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_MASK) #define USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_MASK (0x400000U) #define USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_SHIFT (22U) /*! RID_FLOAT_RISE_INT_EN - RID floating comparator rise detect interrupt enable */ #define USB3_OTGIEN_RID_FLOAT_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_MASK) #define USB3_OTGIEN_RID_GND_RISE_INT_EN_MASK (0x800000U) #define USB3_OTGIEN_RID_GND_RISE_INT_EN_SHIFT (23U) /*! RID_GND_RISE_INT_EN - RID GND comparator rise detect interrupt enable */ #define USB3_OTGIEN_RID_GND_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_GND_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_GND_RISE_INT_EN_MASK) #define USB3_OTGIEN_RID_C_RISE_INT_EN_MASK (0x1000000U) #define USB3_OTGIEN_RID_C_RISE_INT_EN_SHIFT (24U) /*! RID_C_RISE_INT_EN - RID C comparator rise detect interrupt enable */ #define USB3_OTGIEN_RID_C_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_C_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_C_RISE_INT_EN_MASK) #define USB3_OTGIEN_RID_B_RISE_INT_EN_MASK (0x2000000U) #define USB3_OTGIEN_RID_B_RISE_INT_EN_SHIFT (25U) /*! RID_B_RISE_INT_EN - RID B comparator rise detect interrupt enable */ #define USB3_OTGIEN_RID_B_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_B_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_B_RISE_INT_EN_MASK) #define USB3_OTGIEN_RID_A_RISE_INT_EN_MASK (0x4000000U) #define USB3_OTGIEN_RID_A_RISE_INT_EN_SHIFT (26U) /*! RID_A_RISE_INT_EN - RID A comparator rise detect interrupt enable */ #define USB3_OTGIEN_RID_A_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_A_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_A_RISE_INT_EN_MASK) #define USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_MASK (0x8000000U) #define USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_SHIFT (27U) /*! DM_VDAT_REF_RISE_INT_EN - DM VDAT comparator rise detect interrupt enable */ #define USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_MASK) #define USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_MASK (0x10000000U) #define USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_SHIFT (28U) /*! DP_VDAT_REF_RISE_INT_EN - DP VDAT comparator rise detect interrupt enable */ #define USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_MASK) #define USB3_OTGIEN_DCD_COMP_RISE_INT_EN_MASK (0x20000000U) #define USB3_OTGIEN_DCD_COMP_RISE_INT_EN_SHIFT (29U) /*! DCD_COMP_RISE_INT_EN - DCD comparator rise detect interrupt enable */ #define USB3_OTGIEN_DCD_COMP_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DCD_COMP_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DCD_COMP_RISE_INT_EN_MASK) #define USB3_OTGIEN_DCD_COMP_FALL_INT_EN_MASK (0x40000000U) #define USB3_OTGIEN_DCD_COMP_FALL_INT_EN_SHIFT (30U) /*! DCD_COMP_FALL_INT_EN - DCD comparator fall detect interrupt enable */ #define USB3_OTGIEN_DCD_COMP_FALL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DCD_COMP_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_DCD_COMP_FALL_INT_EN_MASK) #define USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_MASK (0x80000000U) #define USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_SHIFT (31U) /*! DM_VLGC_COMP_RISE_INT_EN - DM VLGC comparator rise detect interrupt enable */ #define USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_MASK) /*! @} */ /*! @name OTGIVECT - OTG Interrupt Vector */ /*! @{ */ #define USB3_OTGIVECT_ID_CHANGE_INT_MASK (0x1U) #define USB3_OTGIVECT_ID_CHANGE_INT_SHIFT (0U) /*! ID_CHANGE_INT - ID change interrupt */ #define USB3_OTGIVECT_ID_CHANGE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_ID_CHANGE_INT_SHIFT)) & USB3_OTGIVECT_ID_CHANGE_INT_MASK) #define USB3_OTGIVECT_VBUS_ON_FAILED_INT_MASK (0x2U) #define USB3_OTGIVECT_VBUS_ON_FAILED_INT_SHIFT (1U) /*! VBUS_ON_FAILED_INT - Enabling Vbus by A-Device has failed. This bit should be cleared before enabling subsequent connection as host */ #define USB3_OTGIVECT_VBUS_ON_FAILED_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_VBUS_ON_FAILED_INT_SHIFT)) & USB3_OTGIVECT_VBUS_ON_FAILED_INT_MASK) #define USB3_OTGIVECT_OTGSESSVALID_RISE_INT_MASK (0x4U) #define USB3_OTGIVECT_OTGSESSVALID_RISE_INT_SHIFT (2U) /*! OTGSESSVALID_RISE_INT - Otgsessvalid rise detected interrupt */ #define USB3_OTGIVECT_OTGSESSVALID_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_OTGSESSVALID_RISE_INT_SHIFT)) & USB3_OTGIVECT_OTGSESSVALID_RISE_INT_MASK) #define USB3_OTGIVECT_OTGSESSVALID_FALL_INT_MASK (0x8U) #define USB3_OTGIVECT_OTGSESSVALID_FALL_INT_SHIFT (3U) /*! OTGSESSVALID_FALL_INT - Otgsessvalid fall detected interrupt */ #define USB3_OTGIVECT_OTGSESSVALID_FALL_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_OTGSESSVALID_FALL_INT_SHIFT)) & USB3_OTGIVECT_OTGSESSVALID_FALL_INT_MASK) #define USB3_OTGIVECT_VBUSVALID_RISE_INT_MASK (0x10U) #define USB3_OTGIVECT_VBUSVALID_RISE_INT_SHIFT (4U) /*! VBUSVALID_RISE_INT - Vbusvalid fall detected interrupt */ #define USB3_OTGIVECT_VBUSVALID_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_VBUSVALID_RISE_INT_SHIFT)) & USB3_OTGIVECT_VBUSVALID_RISE_INT_MASK) #define USB3_OTGIVECT_VBUSVALID_FALL_INT_MASK (0x20U) #define USB3_OTGIVECT_VBUSVALID_FALL_INT_SHIFT (5U) /*! VBUSVALID_FALL_INT - Vbusvalid fall detected interrupt */ #define USB3_OTGIVECT_VBUSVALID_FALL_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_VBUSVALID_FALL_INT_SHIFT)) & USB3_OTGIVECT_VBUSVALID_FALL_INT_MASK) #define USB3_OTGIVECT_SENSE_RISE_INT_MASK (0x40U) #define USB3_OTGIVECT_SENSE_RISE_INT_SHIFT (6U) /*! SENSE_RISE_INT - ADP sense comparator rise detected interrupt */ #define USB3_OTGIVECT_SENSE_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SENSE_RISE_INT_SHIFT)) & USB3_OTGIVECT_SENSE_RISE_INT_MASK) #define USB3_OTGIVECT_PROBE_RISE_INT_MASK (0x80U) #define USB3_OTGIVECT_PROBE_RISE_INT_SHIFT (7U) /*! PROBE_RISE_INT - ADP probe comparator rise detected interrupt */ #define USB3_OTGIVECT_PROBE_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_PROBE_RISE_INT_SHIFT)) & USB3_OTGIVECT_PROBE_RISE_INT_MASK) #define USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_MASK (0x100U) #define USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_SHIFT (8U) /*! ADP_PROBE_COMPLETED_INT - ADP completed. Status is reported in OTGADPSTS */ #define USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_SHIFT)) & USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_MASK) #define USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_MASK (0x200U) #define USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_SHIFT (9U) /*! TA_AIDL_BDIS_TMOUT_INT - No response from B-Device for HNP interrupt */ #define USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_MASK) #define USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_MASK (0x400U) #define USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_SHIFT (10U) /*! TA_BIDL_ADIS_TMOUT_INT - No activity from B-Device timeout interrupt */ #define USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_MASK) #define USB3_OTGIVECT_SRP_DET_INT_MASK (0x800U) #define USB3_OTGIVECT_SRP_DET_INT_SHIFT (11U) /*! SRP_DET_INT - SRP pulse detected interrupt */ #define USB3_OTGIVECT_SRP_DET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_DET_INT_SHIFT)) & USB3_OTGIVECT_SRP_DET_INT_MASK) #define USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_MASK (0x1000U) #define USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_SHIFT (12U) /*! SRP_NOT_COMP_DEV_REMOVED_INT - Not cmpliant device disconnect detect interrupt */ #define USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_SHIFT)) & USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_MASK) #define USB3_OTGIVECT_OVERCURRENT_INT_MASK (0x2000U) #define USB3_OTGIVECT_OVERCURRENT_INT_SHIFT (13U) /*! OVERCURRENT_INT - Overcurrent condition detected interrupt */ #define USB3_OTGIVECT_OVERCURRENT_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_OVERCURRENT_INT_SHIFT)) & USB3_OTGIVECT_OVERCURRENT_INT_MASK) #define USB3_OTGIVECT_SRP_FAIL_INT_MASK (0x4000U) #define USB3_OTGIVECT_SRP_FAIL_INT_SHIFT (14U) /*! SRP_FAIL_INT - No response from SRP from A-Device interrupt */ #define USB3_OTGIVECT_SRP_FAIL_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_FAIL_INT_SHIFT)) & USB3_OTGIVECT_SRP_FAIL_INT_MASK) #define USB3_OTGIVECT_SRP_CMPL_INT_MASK (0x8000U) #define USB3_OTGIVECT_SRP_CMPL_INT_SHIFT (15U) /*! SRP_CMPL_INT - SRP completed interrupt */ #define USB3_OTGIVECT_SRP_CMPL_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_CMPL_INT_SHIFT)) & USB3_OTGIVECT_SRP_CMPL_INT_MASK) #define USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_MASK (0x10000U) #define USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_SHIFT (16U) /*! TB_ASE0_BRST_TMOUT_INT - No response from A-Device to HNP interrupt */ #define USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_MASK) #define USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_MASK (0x20000U) #define USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_SHIFT (17U) /*! TB_AIDL_BDIS_MIN_TMOUT_INT - The bus has been in Idle state for the required time during HNP interrupt */ #define USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_MASK) #define USB3_OTGIVECT_TIMER_TMOUT_INT_MASK (0x40000U) #define USB3_OTGIVECT_TIMER_TMOUT_INT_SHIFT (18U) /*! TIMER_TMOUT_INT - Timer timeout interrupt */ #define USB3_OTGIVECT_TIMER_TMOUT_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TIMER_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TIMER_TMOUT_INT_MASK) #define USB3_OTGIVECT_H_POLLTRY_INT_MASK (0x80000U) #define USB3_OTGIVECT_H_POLLTRY_INT_SHIFT (19U) /*! H_POLLTRY_INT - Host Polling state entry interrupt */ #define USB3_OTGIVECT_H_POLLTRY_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_H_POLLTRY_INT_SHIFT)) & USB3_OTGIVECT_H_POLLTRY_INT_MASK) #define USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_MASK (0x100000U) #define USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_SHIFT (20U) /*! H_WRST_GEN_CMPL_INT - Host Warm Reset generation completed interrupt */ #define USB3_OTGIVECT_H_WRST_GEN_CMPL_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_SHIFT)) & USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_MASK) #define USB3_OTGIVECT_RID_FLOAT_FALL_INT_MASK (0x200000U) #define USB3_OTGIVECT_RID_FLOAT_FALL_INT_SHIFT (21U) /*! RID_FLOAT_FALL_INT - RID floating comparator detect interrupt */ #define USB3_OTGIVECT_RID_FLOAT_FALL_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_FLOAT_FALL_INT_SHIFT)) & USB3_OTGIVECT_RID_FLOAT_FALL_INT_MASK) #define USB3_OTGIVECT_RID_FLOAT_RISE_INT_MASK (0x400000U) #define USB3_OTGIVECT_RID_FLOAT_RISE_INT_SHIFT (22U) /*! RID_FLOAT_RISE_INT - RID floating comparator rise detect interrupt */ #define USB3_OTGIVECT_RID_FLOAT_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_FLOAT_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_FLOAT_RISE_INT_MASK) #define USB3_OTGIVECT_RID_GND_RISE_INT_MASK (0x800000U) #define USB3_OTGIVECT_RID_GND_RISE_INT_SHIFT (23U) /*! RID_GND_RISE_INT - RID GND comparator rise detect interrupt */ #define USB3_OTGIVECT_RID_GND_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_GND_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_GND_RISE_INT_MASK) #define USB3_OTGIVECT_RID_C_RISE_INT_MASK (0x1000000U) #define USB3_OTGIVECT_RID_C_RISE_INT_SHIFT (24U) /*! RID_C_RISE_INT - RID C comparator rise detect interrupt */ #define USB3_OTGIVECT_RID_C_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_C_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_C_RISE_INT_MASK) #define USB3_OTGIVECT_RID_B_RISE_INT_MASK (0x2000000U) #define USB3_OTGIVECT_RID_B_RISE_INT_SHIFT (25U) /*! RID_B_RISE_INT - RID B comparator rise detect interrupt */ #define USB3_OTGIVECT_RID_B_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_B_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_B_RISE_INT_MASK) #define USB3_OTGIVECT_RID_A_RISE_INT_MASK (0x4000000U) #define USB3_OTGIVECT_RID_A_RISE_INT_SHIFT (26U) /*! RID_A_RISE_INT - RID A comparator rise detect interrupt */ #define USB3_OTGIVECT_RID_A_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_A_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_A_RISE_INT_MASK) #define USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_MASK (0x8000000U) #define USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_SHIFT (27U) /*! DM_VDAT_REF_RISE_INT - DM VDAT comparator rise detect interrupt */ #define USB3_OTGIVECT_DM_VDAT_REF_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_SHIFT)) & USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_MASK) #define USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_MASK (0x10000000U) #define USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_SHIFT (28U) /*! DP_VDAT_REF_RISE_INT - DP VDAT comparator rise detect interrupt */ #define USB3_OTGIVECT_DP_VDAT_REF_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_SHIFT)) & USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_MASK) #define USB3_OTGIVECT_DCD_COMP_RISE_INT_MASK (0x20000000U) #define USB3_OTGIVECT_DCD_COMP_RISE_INT_SHIFT (29U) /*! DCD_COMP_RISE_INT - DCD comparator rise detect interrupt */ #define USB3_OTGIVECT_DCD_COMP_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DCD_COMP_RISE_INT_SHIFT)) & USB3_OTGIVECT_DCD_COMP_RISE_INT_MASK) #define USB3_OTGIVECT_DCD_COMP_FALL_INT_MASK (0x40000000U) #define USB3_OTGIVECT_DCD_COMP_FALL_INT_SHIFT (30U) /*! DCD_COMP_FALL_INT - DCD comparator fall detect interrupt */ #define USB3_OTGIVECT_DCD_COMP_FALL_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DCD_COMP_FALL_INT_SHIFT)) & USB3_OTGIVECT_DCD_COMP_FALL_INT_MASK) #define USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_MASK (0x80000000U) #define USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_SHIFT (31U) /*! DM_VLGC_COMP_RISE_INT - DM VLGC comparator rise detect interrupt */ #define USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_SHIFT)) & USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_MASK) /*! @} */ /*! @name CLK_FREQ - Clock Frequency */ /*! @{ */ #define USB3_CLK_FREQ_CLK_FREQ_MHZ_MASK (0xFFFFU) #define USB3_CLK_FREQ_CLK_FREQ_MHZ_SHIFT (0U) /*! CLK_FREQ_MHZ - CLK_FREQ_MHZ defines how many cycles are needed to determine 1 us clock base for * fast clock Example: Let's say that fast clock frequency is 12MHz. With CLK_FREQ_MHZ set to 12 * time base would be 12 cycles of 12Mhz clock which gives 1 us */ #define USB3_CLK_FREQ_CLK_FREQ_MHZ(x) (((uint32_t)(((uint32_t)(x)) << USB3_CLK_FREQ_CLK_FREQ_MHZ_SHIFT)) & USB3_CLK_FREQ_CLK_FREQ_MHZ_MASK) #define USB3_CLK_FREQ_CLK_FREQ_KHZ_MASK (0xFFFF0000U) #define USB3_CLK_FREQ_CLK_FREQ_KHZ_SHIFT (16U) /*! CLK_FREQ_KHZ - CLK_FREQ_KHZ defines how many cycles are needed to determine 1 ms clock base for * stb_clk_predft. Example: Let's say that stb_clk_predft frequency is 32kHz. With CLK_FREQ_KHZ * set to 32 time base would be 32 cycles of 32khz clock which gives 1 ms */ #define USB3_CLK_FREQ_CLK_FREQ_KHZ(x) (((uint32_t)(((uint32_t)(x)) << USB3_CLK_FREQ_CLK_FREQ_KHZ_SHIFT)) & USB3_CLK_FREQ_CLK_FREQ_KHZ_MASK) /*! @} */ /*! @name OTGTMR - OTG Timer */ /*! @{ */ #define USB3_OTGTMR_TIMEOUT_VALUE_MASK (0xFFFFU) #define USB3_OTGTMR_TIMEOUT_VALUE_SHIFT (0U) /*! TIMEOUT_VALUE - Timeout value for timer. Valid only if TIMER_WRITE is 1 */ #define USB3_OTGTMR_TIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMEOUT_VALUE_SHIFT)) & USB3_OTGTMR_TIMEOUT_VALUE_MASK) #define USB3_OTGTMR_TIMEOUT_UNITS_MASK (0x30000U) #define USB3_OTGTMR_TIMEOUT_UNITS_SHIFT (16U) /*! TIMEOUT_UNITS - Time units * 0b00..hundreds of microseconds (valid only if otg controller clock is in MHz range) * 0b01..milliseconds * 0b10..tens of milliseconds * 0b11..hundreds of milliseconds, Valid only if TIMER_WRITE is 1 */ #define USB3_OTGTMR_TIMEOUT_UNITS(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMEOUT_UNITS_SHIFT)) & USB3_OTGTMR_TIMEOUT_UNITS_MASK) #define USB3_OTGTMR_TIMER_WRITE_MASK (0x40000U) #define USB3_OTGTMR_TIMER_WRITE_SHIFT (18U) /*! TIMER_WRITE - Timer value and units write strobe */ #define USB3_OTGTMR_TIMER_WRITE(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMER_WRITE_SHIFT)) & USB3_OTGTMR_TIMER_WRITE_MASK) #define USB3_OTGTMR_TIMER_START_MASK (0x80000U) #define USB3_OTGTMR_TIMER_START_SHIFT (19U) /*! TIMER_START - Start timer */ #define USB3_OTGTMR_TIMER_START(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMER_START_SHIFT)) & USB3_OTGTMR_TIMER_START_MASK) #define USB3_OTGTMR_TIMER_STOP_MASK (0x100000U) #define USB3_OTGTMR_TIMER_STOP_SHIFT (20U) /*! TIMER_STOP - Stop timer */ #define USB3_OTGTMR_TIMER_STOP(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMER_STOP_SHIFT)) & USB3_OTGTMR_TIMER_STOP_MASK) /*! @} */ /*! @name OTGVERSION - OTG Version */ /*! @{ */ #define USB3_OTGVERSION_OTGVERSION_MASK (0xFFFFU) #define USB3_OTGVERSION_OTGVERSION_SHIFT (0U) /*! OTGVERSION - OTG core revision */ #define USB3_OTGVERSION_OTGVERSION(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGVERSION_OTGVERSION_SHIFT)) & USB3_OTGVERSION_OTGVERSION_MASK) /*! @} */ /*! @name OTGCAPABILITY - OTG Capability */ /*! @{ */ #define USB3_OTGCAPABILITY_SRP_SUPPORT_MASK (0x1U) #define USB3_OTGCAPABILITY_SRP_SUPPORT_SHIFT (0U) /*! SRP_SUPPORT - SRP support. 0 - SRP not supported 1 - SRP supported */ #define USB3_OTGCAPABILITY_SRP_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_SRP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_SRP_SUPPORT_MASK) #define USB3_OTGCAPABILITY_HNP_SUPPORT_MASK (0x2U) #define USB3_OTGCAPABILITY_HNP_SUPPORT_SHIFT (1U) /*! HNP_SUPPORT - HNP support. 0 - HNP not supported 1 - HNP supported */ #define USB3_OTGCAPABILITY_HNP_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_HNP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_HNP_SUPPORT_MASK) #define USB3_OTGCAPABILITY_ADP_SUPPORT_MASK (0x4U) #define USB3_OTGCAPABILITY_ADP_SUPPORT_SHIFT (2U) /*! ADP_SUPPORT - ADP support. 0 - ADP not supported 1 - ADP supported */ #define USB3_OTGCAPABILITY_ADP_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_ADP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_ADP_SUPPORT_MASK) #define USB3_OTGCAPABILITY_BC_SUPPORT_MASK (0x8U) #define USB3_OTGCAPABILITY_BC_SUPPORT_SHIFT (3U) /*! BC_SUPPORT - BC Support (Battery Charging specification rev 1.2). 0 - BC not supported 1 - BC supported */ #define USB3_OTGCAPABILITY_BC_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_BC_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_BC_SUPPORT_MASK) #define USB3_OTGCAPABILITY_RSP_SUPPORT_MASK (0x10U) #define USB3_OTGCAPABILITY_RSP_SUPPORT_SHIFT (4U) /*! RSP_SUPPORT - RSP support. 0 - RSP not supported 1 - RSP supported */ #define USB3_OTGCAPABILITY_RSP_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_RSP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_RSP_SUPPORT_MASK) #define USB3_OTGCAPABILITY_OTG2REVISION_MASK (0xFFF00U) #define USB3_OTGCAPABILITY_OTG2REVISION_SHIFT (8U) /*! OTG2REVISION - Specifies implemeted OTG2.0 specification revision */ #define USB3_OTGCAPABILITY_OTG2REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_OTG2REVISION_SHIFT)) & USB3_OTGCAPABILITY_OTG2REVISION_MASK) #define USB3_OTGCAPABILITY_OTG3REVISION_MASK (0xFFF00000U) #define USB3_OTGCAPABILITY_OTG3REVISION_SHIFT (20U) /*! OTG3REVISION - Specifies implemeted OTG3.0 specification revision */ #define USB3_OTGCAPABILITY_OTG3REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_OTG3REVISION_SHIFT)) & USB3_OTGCAPABILITY_OTG3REVISION_MASK) /*! @} */ /*! @name OTGSIMULATE - OTG Simulate */ /*! @{ */ #define USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_MASK (0x1U) #define USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_SHIFT (0U) /*! OTG_CFG_FAST_SIMS - Debug Feature. This bit is for simulation modes only. It enables reductions * to OTG timings. '0': Normal timings '1': Enable fast simulation timing modes This bit should * be written '0' in normal operation */ #define USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_SHIFT)) & USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_MASK) /*! @} */ /*! @name OTGANASTS - OTG Attach Detection Protocol BC Status */ /*! @{ */ #define USB3_OTGANASTS_dp_vdat_ref_comp_sts_MASK (0x1U) #define USB3_OTGANASTS_dp_vdat_ref_comp_sts_SHIFT (0U) /*! dp_vdat_ref_comp_sts - 1: DP > VDAT_REF Detected 0: DP < VDAT_REF Detected Note: This status * shall be re-used from the single ended receiver output of D+ whenever dp_vdat_ref_comp_en is '1' */ #define USB3_OTGANASTS_dp_vdat_ref_comp_sts(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dp_vdat_ref_comp_sts_SHIFT)) & USB3_OTGANASTS_dp_vdat_ref_comp_sts_MASK) #define USB3_OTGANASTS_dm_vdat_ref_comp_sts_MASK (0x2U) #define USB3_OTGANASTS_dm_vdat_ref_comp_sts_SHIFT (1U) /*! dm_vdat_ref_comp_sts - 1: DM > VDAT_REF Detected 0: DM < VDAT_REF Detected Note: This status * shall be re-used from the single ended receiver output of D- whenever dm_vdat_ref_comp_en is '1' */ #define USB3_OTGANASTS_dm_vdat_ref_comp_sts(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dm_vdat_ref_comp_sts_SHIFT)) & USB3_OTGANASTS_dm_vdat_ref_comp_sts_MASK) #define USB3_OTGANASTS_dm_vlgc_comp_sts_MASK (0x4U) #define USB3_OTGANASTS_dm_vlgc_comp_sts_SHIFT (2U) /*! dm_vlgc_comp_sts - 1: DM > VLGC Detected 0: DM < VLGC Detected Note: This status shall be * re-used from the single ended receiver output of D- whenever dm_vlgc_comp_en is '1' */ #define USB3_OTGANASTS_dm_vlgc_comp_sts(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dm_vlgc_comp_sts_SHIFT)) & USB3_OTGANASTS_dm_vlgc_comp_sts_MASK) #define USB3_OTGANASTS_dcd_comp_sts_MASK (0x8U) #define USB3_OTGANASTS_dcd_comp_sts_SHIFT (3U) /*! dcd_comp_sts - Data Contact Detect (DCD) Comparator Status 1: DP line is asserted 0: DP line is not asserted */ #define USB3_OTGANASTS_dcd_comp_sts(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dcd_comp_sts_SHIFT)) & USB3_OTGANASTS_dcd_comp_sts_MASK) #define USB3_OTGANASTS_otgsessvalid_MASK (0x10U) #define USB3_OTGANASTS_otgsessvalid_SHIFT (4U) /*! otgsessvalid - B-Peripheral is Valid: Indicates if the session for a B-Peripheral is valid (0.8V * < VTH < 4.0V). The signal bvalid from OTG 1.3 is now renamed as otgsessvalid. 0: VBUS < 0.8V * 1: VBUS > 4.0V */ #define USB3_OTGANASTS_otgsessvalid(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_otgsessvalid_SHIFT)) & USB3_OTGANASTS_otgsessvalid_MASK) #define USB3_OTGANASTS_adp_probe_ana_MASK (0x20U) #define USB3_OTGANASTS_adp_probe_ana_SHIFT (5U) /*! adp_probe_ana - Output of ADP Probe Comparator. 0: VBUS < 0.6V 1: VBUS > 0.75V */ #define USB3_OTGANASTS_adp_probe_ana(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_adp_probe_ana_SHIFT)) & USB3_OTGANASTS_adp_probe_ana_MASK) #define USB3_OTGANASTS_adp_sense_ana_MASK (0x40U) #define USB3_OTGANASTS_adp_sense_ana_SHIFT (6U) /*! adp_sense_ana - Output of ADP Sense Comparator. 0: VBUS < 0.2V 1: VBUS > 0.55V */ #define USB3_OTGANASTS_adp_sense_ana(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_adp_sense_ana_SHIFT)) & USB3_OTGANASTS_adp_sense_ana_MASK) #define USB3_OTGANASTS_sessend_MASK (0x80U) #define USB3_OTGANASTS_sessend_SHIFT (7U) /*! sessend - VBUS Valid: Indicates if the voltage on VBUS is at a valid level for operation (4.4V < * VTH < 4.75V). 0: VBUS < 4.4V 1: VBUS > 4.75V */ #define USB3_OTGANASTS_sessend(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_sessend_SHIFT)) & USB3_OTGANASTS_sessend_MASK) #define USB3_OTGANASTS_rid_float_comp_sts_MASK (0x100U) #define USB3_OTGANASTS_rid_float_comp_sts_SHIFT (8U) /*! rid_float_comp_sts - RID float comparator status 1: RID_FLOAT Detected on ID Pin 0: RID_FLOAT not Detected on ID Pin */ #define USB3_OTGANASTS_rid_float_comp_sts(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_float_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_float_comp_sts_MASK) #define USB3_OTGANASTS_rid_gnd_comp_sts_MASK (0x200U) #define USB3_OTGANASTS_rid_gnd_comp_sts_SHIFT (9U) /*! rid_gnd_comp_sts - RID GND comparator status 1: RID_GND Detected on ID Pin 0: RID_GND not Detected on ID Pin */ #define USB3_OTGANASTS_rid_gnd_comp_sts(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_gnd_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_gnd_comp_sts_MASK) #define USB3_OTGANASTS_rid_c_comp_sts_MASK (0x400U) #define USB3_OTGANASTS_rid_c_comp_sts_SHIFT (10U) /*! rid_c_comp_sts - RID C comparator status 1: RID_C Detected on ID Pin 0: RID_C not Detected on ID Pin */ #define USB3_OTGANASTS_rid_c_comp_sts(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_c_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_c_comp_sts_MASK) #define USB3_OTGANASTS_rid_b_comp_sts_MASK (0x800U) #define USB3_OTGANASTS_rid_b_comp_sts_SHIFT (11U) /*! rid_b_comp_sts - RID B comparator status 1: RID_B Detected on ID Pin 0: RID_B not Detected on ID Pin */ #define USB3_OTGANASTS_rid_b_comp_sts(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_b_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_b_comp_sts_MASK) #define USB3_OTGANASTS_rid_a_comp_sts_MASK (0x1000U) #define USB3_OTGANASTS_rid_a_comp_sts_SHIFT (12U) /*! rid_a_comp_sts - RID A comparator status 1: RID_A Detected on ID Pin 0: RID_A not Detected on ID Pin */ #define USB3_OTGANASTS_rid_a_comp_sts(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_a_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_a_comp_sts_MASK) #define USB3_OTGANASTS_iddig_MASK (0x2000U) #define USB3_OTGANASTS_iddig_SHIFT (13U) /*! iddig - ID Pin Status: Indicates whether the connected USB plug is Micro-A or Micro-B. This is * only valid when idpullup is set to '1'. It must be valid within 50ms after idpullup is set to * '1'. 0: Connected plug is a Micro-A 1: Connected plug is a Micro-B */ #define USB3_OTGANASTS_iddig(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_iddig_SHIFT)) & USB3_OTGANASTS_iddig_MASK) #define USB3_OTGANASTS_linestate_MASK (0xC000U) #define USB3_OTGANASTS_linestate_SHIFT (14U) /*! linestate - Line State: These signals reflect the current state of the single ended receivers. * They are combinatorial until a 'usable' sieclock is available, then they are synchronized to * sieclock. They reflect the current state of the DP (linestate [0]) and DM (linestate [1]) * signals. 00: SE0 (Single Ended Zero) 01: 'J' State 10: 'K' State 11: SE1 (Single Ended One) */ #define USB3_OTGANASTS_linestate(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_linestate_SHIFT)) & USB3_OTGANASTS_linestate_MASK) #define USB3_OTGANASTS_rid_float_MASK (0x10000U) #define USB3_OTGANASTS_rid_float_SHIFT (16U) /*! rid_float - RID float status reg */ #define USB3_OTGANASTS_rid_float(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_float_SHIFT)) & USB3_OTGANASTS_rid_float_MASK) #define USB3_OTGANASTS_rid_gnd_MASK (0x20000U) #define USB3_OTGANASTS_rid_gnd_SHIFT (17U) /*! rid_gnd - RID GND status reg */ #define USB3_OTGANASTS_rid_gnd(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_gnd_SHIFT)) & USB3_OTGANASTS_rid_gnd_MASK) #define USB3_OTGANASTS_rid_c_MASK (0x40000U) #define USB3_OTGANASTS_rid_c_SHIFT (18U) /*! rid_c - RID C status reg */ #define USB3_OTGANASTS_rid_c(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_c_SHIFT)) & USB3_OTGANASTS_rid_c_MASK) #define USB3_OTGANASTS_rid_b_MASK (0x80000U) #define USB3_OTGANASTS_rid_b_SHIFT (19U) /*! rid_b - RID B status reg */ #define USB3_OTGANASTS_rid_b(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_b_SHIFT)) & USB3_OTGANASTS_rid_b_MASK) #define USB3_OTGANASTS_rid_a_MASK (0x100000U) #define USB3_OTGANASTS_rid_a_SHIFT (20U) /*! rid_a - RID A status reg */ #define USB3_OTGANASTS_rid_a(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_a_SHIFT)) & USB3_OTGANASTS_rid_a_MASK) #define USB3_OTGANASTS_adp_chrg_tmout_det_MASK (0x1000000U) #define USB3_OTGANASTS_adp_chrg_tmout_det_SHIFT (24U) /*! adp_chrg_tmout_det - ADP charge timeout detected */ #define USB3_OTGANASTS_adp_chrg_tmout_det(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_adp_chrg_tmout_det_SHIFT)) & USB3_OTGANASTS_adp_chrg_tmout_det_MASK) /*! @} */ /*! @name ADP_RAMP_TIME - Attach Detection Protocol Ramp Time */ /*! @{ */ #define USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_MASK (0xFFFFFFFFU) #define USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_SHIFT (0U) /*! ADP_RAMP_TIME - ADP ramp time measurement value. Software should read this register upon ADP_PROBE_COMPLETED_INT_EN interrupt detection */ #define USB3_ADP_RAMP_TIME_ADP_RAMP_TIME(x) (((uint32_t)(((uint32_t)(x)) << USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_SHIFT)) & USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_MASK) /*! @} */ /*! @name OTGCTRL1 - OTG Control */ /*! @{ */ #define USB3_OTGCTRL1_adp_en_MASK (0x1U) #define USB3_OTGCTRL1_adp_en_SHIFT (0U) /*! adp_en - ADP Feature Enable. This signal is the master enable for all the ADP PHY logics. 0: ADP * Logics are powered OFF 1: ADP Logics are powered ON */ #define USB3_OTGCTRL1_adp_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_en_SHIFT)) & USB3_OTGCTRL1_adp_en_MASK) #define USB3_OTGCTRL1_adp_probe_en_MASK (0x2U) #define USB3_OTGCTRL1_adp_probe_en_SHIFT (1U) /*! adp_probe_en - This signal enables the probe mode of the ADP. During this mode, probe * comparators and the current sources will be ON based on the source and sink current enables. 0: ADP * Probe Mode OFF 1: ADP Probe Mode ON */ #define USB3_OTGCTRL1_adp_probe_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_probe_en_SHIFT)) & USB3_OTGCTRL1_adp_probe_en_MASK) #define USB3_OTGCTRL1_adp_sense_en_MASK (0x4U) #define USB3_OTGCTRL1_adp_sense_en_SHIFT (2U) /*! adp_sense_en - This signal enables the probe mode of the ADP. During this mode, sense * comparators and the current sources will be ON based on the source and sink current enables. 0: ADP * Probe Sense OFF 1: ADP Probe Sense ON */ #define USB3_OTGCTRL1_adp_sense_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_sense_en_SHIFT)) & USB3_OTGCTRL1_adp_sense_en_MASK) #define USB3_OTGCTRL1_adp_sink_current_en_MASK (0x8U) #define USB3_OTGCTRL1_adp_sink_current_en_SHIFT (3U) /*! adp_sink_current_en - When this signal is high, VBUS is discharged to ground. This signal should * be asserted 5us after the assertion of adp_en. 0: ADP Sink Current Enable OFF 1: ADP Sink * Current Enable ON */ #define USB3_OTGCTRL1_adp_sink_current_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_sink_current_en_SHIFT)) & USB3_OTGCTRL1_adp_sink_current_en_MASK) #define USB3_OTGCTRL1_adp_source_current_en_MASK (0x10U) #define USB3_OTGCTRL1_adp_source_current_en_SHIFT (4U) /*! adp_source_current_en - When this signal is high, VBUS is charged to the probe threshold * (0.75V). This signal should be asserted 5us after the assertion of adp_en. 0: ADP Source Current * Enable OFF 1: ADP Source Current Enable ON */ #define USB3_OTGCTRL1_adp_source_current_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_source_current_en_SHIFT)) & USB3_OTGCTRL1_adp_source_current_en_MASK) #define USB3_OTGCTRL1_do_adp_prb_MASK (0x20U) #define USB3_OTGCTRL1_do_adp_prb_SHIFT (5U) /*! do_adp_prb - ADP probing enable in automated mode */ #define USB3_OTGCTRL1_do_adp_prb(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_do_adp_prb_SHIFT)) & USB3_OTGCTRL1_do_adp_prb_MASK) #define USB3_OTGCTRL1_do_adp_sns_MASK (0x40U) #define USB3_OTGCTRL1_do_adp_sns_SHIFT (6U) /*! do_adp_sns - ADP sensing enable in automated mode */ #define USB3_OTGCTRL1_do_adp_sns(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_do_adp_sns_SHIFT)) & USB3_OTGCTRL1_do_adp_sns_MASK) #define USB3_OTGCTRL1_adp_auto_MASK (0x80U) #define USB3_OTGCTRL1_adp_auto_SHIFT (7U) /*! adp_auto - ADP mode. If set to 1 ADP probing is controlled by internal FSM. If set to 0 then software should control ADP sequence */ #define USB3_OTGCTRL1_adp_auto(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_auto_SHIFT)) & USB3_OTGCTRL1_adp_auto_MASK) #define USB3_OTGCTRL1_bc_en_MASK (0x100U) #define USB3_OTGCTRL1_bc_en_SHIFT (8U) /*! bc_en - Battery Charging Circuits Master Enable. 1: BC Enabled 0: BC Disabled */ #define USB3_OTGCTRL1_bc_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_en_SHIFT)) & USB3_OTGCTRL1_bc_en_MASK) #define USB3_OTGCTRL1_idm_sink_en_MASK (0x200U) #define USB3_OTGCTRL1_idm_sink_en_SHIFT (9U) /*! idm_sink_en - 1: Current Sink on DM Enabled 0: Current Sink on DM Disabled */ #define USB3_OTGCTRL1_idm_sink_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idm_sink_en_SHIFT)) & USB3_OTGCTRL1_idm_sink_en_MASK) #define USB3_OTGCTRL1_idp_sink_en_MASK (0x400U) #define USB3_OTGCTRL1_idp_sink_en_SHIFT (10U) /*! idp_sink_en - 1: Current Sink on DP Enabled 0: Current Sink on DP Disabled */ #define USB3_OTGCTRL1_idp_sink_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idp_sink_en_SHIFT)) & USB3_OTGCTRL1_idp_sink_en_MASK) #define USB3_OTGCTRL1_idp_src_en_MASK (0x800U) #define USB3_OTGCTRL1_idp_src_en_SHIFT (11U) /*! idp_src_en - 1: Current Source on DP Enabled 0: Current Source on DP Disabled */ #define USB3_OTGCTRL1_idp_src_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idp_src_en_SHIFT)) & USB3_OTGCTRL1_idp_src_en_MASK) #define USB3_OTGCTRL1_vdm_src_en_MASK (0x1000U) #define USB3_OTGCTRL1_vdm_src_en_SHIFT (12U) /*! vdm_src_en - 1: Voltage Source on DM Enabled 0: Voltage Source on DM Disabled */ #define USB3_OTGCTRL1_vdm_src_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_vdm_src_en_SHIFT)) & USB3_OTGCTRL1_vdm_src_en_MASK) #define USB3_OTGCTRL1_vdp_src_en_MASK (0x2000U) #define USB3_OTGCTRL1_vdp_src_en_SHIFT (13U) /*! vdp_src_en - 1: Voltage Source on DP Enabled 0: Voltage Source on DP Disabled */ #define USB3_OTGCTRL1_vdp_src_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_vdp_src_en_SHIFT)) & USB3_OTGCTRL1_vdp_src_en_MASK) #define USB3_OTGCTRL1_dm_vdat_ref_comp_en_MASK (0x10000U) #define USB3_OTGCTRL1_dm_vdat_ref_comp_en_SHIFT (16U) /*! dm_vdat_ref_comp_en - 1: DM to VDAT_REF Comparator Enabled 0: DM to VDAT_REF Comparator Disabled */ #define USB3_OTGCTRL1_dm_vdat_ref_comp_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_dm_vdat_ref_comp_en_SHIFT)) & USB3_OTGCTRL1_dm_vdat_ref_comp_en_MASK) #define USB3_OTGCTRL1_dm_vlgc_comp_en_MASK (0x20000U) #define USB3_OTGCTRL1_dm_vlgc_comp_en_SHIFT (17U) /*! dm_vlgc_comp_en - 1: DM to VLGC Comparator Enabled 0: DM to VLGC Comparator Disabled */ #define USB3_OTGCTRL1_dm_vlgc_comp_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_dm_vlgc_comp_en_SHIFT)) & USB3_OTGCTRL1_dm_vlgc_comp_en_MASK) #define USB3_OTGCTRL1_dp_vdat_ref_comp_en_MASK (0x40000U) #define USB3_OTGCTRL1_dp_vdat_ref_comp_en_SHIFT (18U) /*! dp_vdat_ref_comp_en - 1: DP to VDAT_REF Comparator Enabled 0: DP to VDAT_REF Comparator Disabled */ #define USB3_OTGCTRL1_dp_vdat_ref_comp_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_dp_vdat_ref_comp_en_SHIFT)) & USB3_OTGCTRL1_dp_vdat_ref_comp_en_MASK) #define USB3_OTGCTRL1_rid_float_comp_en_MASK (0x80000U) #define USB3_OTGCTRL1_rid_float_comp_en_SHIFT (19U) /*! rid_float_comp_en - 1: RID Float Comparator Enabled 0: RID Float Comparator Disabled Note: This * ID Comparator enable is used to detect whether the ID line is floating or non-floating. If it * is identified to be non-floating, then rid_nonfloat_comp_en is enabled to check for RID_A or * RID_B or RID_C or RID_GND */ #define USB3_OTGCTRL1_rid_float_comp_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_rid_float_comp_en_SHIFT)) & USB3_OTGCTRL1_rid_float_comp_en_MASK) #define USB3_OTGCTRL1_rid_nonfloat_comp_en_MASK (0x100000U) #define USB3_OTGCTRL1_rid_nonfloat_comp_en_SHIFT (20U) /*! rid_nonfloat_comp_en - 1: RID Non-Float Comparator Enabled 0: RID Non-Float Comparator Disabled * Note: This ID Comparator enable is used to detect the presence of RID_A or RID_B or RID_C or * RID_GND when the ID pin is non-floating */ #define USB3_OTGCTRL1_rid_nonfloat_comp_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_rid_nonfloat_comp_en_SHIFT)) & USB3_OTGCTRL1_rid_nonfloat_comp_en_MASK) #define USB3_OTGCTRL1_bc_dmpulldown_MASK (0x200000U) #define USB3_OTGCTRL1_bc_dmpulldown_SHIFT (21U) /*! bc_dmpulldown - BC dmpulldown enable */ #define USB3_OTGCTRL1_bc_dmpulldown(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_dmpulldown_SHIFT)) & USB3_OTGCTRL1_bc_dmpulldown_MASK) #define USB3_OTGCTRL1_bc_dppulldown_MASK (0x400000U) #define USB3_OTGCTRL1_bc_dppulldown_SHIFT (22U) /*! bc_dppulldown - BC dppulldown enable */ #define USB3_OTGCTRL1_bc_dppulldown(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_dppulldown_SHIFT)) & USB3_OTGCTRL1_bc_dppulldown_MASK) #define USB3_OTGCTRL1_bc_pulldownctrl_MASK (0x800000U) #define USB3_OTGCTRL1_bc_pulldownctrl_SHIFT (23U) /*! bc_pulldownctrl - BC pulldowncotrol 1: puldowns are controlled by bc_dppulldown and bc_dmpulldown 0: puldowns are controlled by OTG */ #define USB3_OTGCTRL1_bc_pulldownctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_pulldownctrl_SHIFT)) & USB3_OTGCTRL1_bc_pulldownctrl_MASK) #define USB3_OTGCTRL1_idpullup_MASK (0x1000000U) #define USB3_OTGCTRL1_idpullup_SHIFT (24U) /*! idpullup - ID Pin Sample Enable: Active High. Signal that enables the sampling of the analog ID * line. 0: Sampling of ID pin is disabled, iddig is not valid 1: Sampling of ID pin is enabled */ #define USB3_OTGCTRL1_idpullup(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idpullup_SHIFT)) & USB3_OTGCTRL1_idpullup_MASK) #define USB3_OTGCTRL1_drive_vbus_sel_MASK (0x2000000U) #define USB3_OTGCTRL1_drive_vbus_sel_SHIFT (25U) /*! drive_vbus_sel - VBUS drive control select. This register allows SW driver take control over * drive_vbus as follows: 0: drive_vbus controlled from OTG controller 1: drive_vbus controlled from * SFR */ #define USB3_OTGCTRL1_drive_vbus_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_drive_vbus_sel_SHIFT)) & USB3_OTGCTRL1_drive_vbus_sel_MASK) #define USB3_OTGCTRL1_drive_vbus_sfr_MASK (0x4000000U) #define USB3_OTGCTRL1_drive_vbus_sfr_SHIFT (26U) /*! drive_vbus_sfr - SFR drive_vbus control. 0: drive_vbus = 0 1: drive_vbus = 1 This bit is valid * only with OTGCTRL1.drive_vbus_sel set to '1'. This bit is auto-cleared upon over-current * condition */ #define USB3_OTGCTRL1_drive_vbus_sfr(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_drive_vbus_sfr_SHIFT)) & USB3_OTGCTRL1_drive_vbus_sfr_MASK) #define USB3_OTGCTRL1_force_opmode01_MASK (0x8000000U) #define USB3_OTGCTRL1_force_opmode01_SHIFT (27U) /*! force_opmode01 - with both cores disabled seting this bit to '1' will result with forcing UTMI opmode set to 2'b01 (non-driving) */ #define USB3_OTGCTRL1_force_opmode01(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_force_opmode01_SHIFT)) & USB3_OTGCTRL1_force_opmode01_MASK) /*! @} */ /*! @name OTGCTRL2 - OTG Control */ /*! @{ */ #define USB3_OTGCTRL2_TA_ADP_PRB_MASK (0xFFU) #define USB3_OTGCTRL2_TA_ADP_PRB_SHIFT (0U) /*! TA_ADP_PRB - A-device ADP probing period. TA_ADP_PRB = {reg_value} * 10 ms */ #define USB3_OTGCTRL2_TA_ADP_PRB(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_TA_ADP_PRB_SHIFT)) & USB3_OTGCTRL2_TA_ADP_PRB_MASK) #define USB3_OTGCTRL2_TB_ADP_PRB_MASK (0xFF00U) #define USB3_OTGCTRL2_TB_ADP_PRB_SHIFT (8U) /*! TB_ADP_PRB - B-device ADP probing period. TB_ADP_PRB = {reg_value} * 10 ms */ #define USB3_OTGCTRL2_TB_ADP_PRB(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_TB_ADP_PRB_SHIFT)) & USB3_OTGCTRL2_TB_ADP_PRB_MASK) #define USB3_OTGCTRL2_ADP_CHRG_TMOUT_MASK (0xFF0000U) #define USB3_OTGCTRL2_ADP_CHRG_TMOUT_SHIFT (16U) /*! ADP_CHRG_TMOUT - ADP probing timeout value. Defines maximum time for ADP charging. If this time * is reached during charging then adp_chrg_tmout_det bit in OTGADPBCSTS is set ADP_CHRG_TMOUT = * {reg_value} * 1 ms */ #define USB3_OTGCTRL2_ADP_CHRG_TMOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_ADP_CHRG_TMOUT_SHIFT)) & USB3_OTGCTRL2_ADP_CHRG_TMOUT_MASK) #define USB3_OTGCTRL2_T_ADP_DSCHG_MASK (0xFF000000U) #define USB3_OTGCTRL2_T_ADP_DSCHG_SHIFT (24U) /*! T_ADP_DSCHG - ADP probing discharge time. T_ADP_DSCHG = {reg_value} * 1 ms */ #define USB3_OTGCTRL2_T_ADP_DSCHG(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_T_ADP_DSCHG_SHIFT)) & USB3_OTGCTRL2_T_ADP_DSCHG_MASK) /*! @} */ /*! @name HCIVERSION_CAPLENGTH - HCI Version and CAPLENGTH */ /*! @{ */ #define USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_SHIFT (0U) /*! CAPLENGTH - Capability Registers Length (CAPLENGTH). This register is used as an offset to add * to register base to find the beginning of the Operational Register Space */ #define USB3_HCIVERSION_CAPLENGTH_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_SHIFT)) & USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_MASK) #define USB3_HCIVERSION_CAPLENGTH_HCIVERSION_MASK (0xFFFF0000U) #define USB3_HCIVERSION_CAPLENGTH_HCIVERSION_SHIFT (16U) /*! HCIVERSION - Host Controller Interface Version Number (HCIVERSION). This is a two-byte register * containing a BCD encoding of the xHCI specification revision number supported by this host * controller. The most significant byte of this register represents a major revision and the least * significant byte is the minor revision. e.g. 0100h corresponds to xHCI version 1.0 */ #define USB3_HCIVERSION_CAPLENGTH_HCIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCIVERSION_CAPLENGTH_HCIVERSION_SHIFT)) & USB3_HCIVERSION_CAPLENGTH_HCIVERSION_MASK) /*! @} */ /*! @name HCSPARAMS1 - Structural Parameters 1 */ /*! @{ */ #define USB3_HCSPARAMS1_MaxSlots_MASK (0xFFU) #define USB3_HCSPARAMS1_MaxSlots_SHIFT (0U) /*! MaxSlots - Number of Device Slots (MaxSlots). This field specifies the maximum number of Device * Context Structures and Doorbell Array entries this host controller can support. Valid values * are in the range of 1 to 255. The value of 0 is reserved */ #define USB3_HCSPARAMS1_MaxSlots(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS1_MaxSlots_SHIFT)) & USB3_HCSPARAMS1_MaxSlots_MASK) #define USB3_HCSPARAMS1_MaxIntrs_MASK (0x7FF00U) #define USB3_HCSPARAMS1_MaxIntrs_SHIFT (8U) /*! MaxIntrs - Number of Interrupters (MaxIntrs). This field specifies the number of Interrupters * implemented on this host controller. Each Interrupter may be allocated to a MSI or MSI-X vector * and controls its generation and moderation. The value of this field determines how many * Interrupter Register Sets are addressable in the Runtime Register Space (refer to section 5.5 of * xHCI specification). Valid values are in the range of 1h to 400h. A '0' in this field is undefined */ #define USB3_HCSPARAMS1_MaxIntrs(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS1_MaxIntrs_SHIFT)) & USB3_HCSPARAMS1_MaxIntrs_MASK) #define USB3_HCSPARAMS1_MaxPorts_MASK (0xFF000000U) #define USB3_HCSPARAMS1_MaxPorts_SHIFT (24U) /*! MaxPorts - Number of Ports (MaxPorts). This field specifies the maximum Port Number value, i.e. * the highest numbered Port Register Set that are addressable in the Operational Register Space. * Valid values are in the range of 1h to FFh. The value in this field shall reflect the maximum * Port Number value assigned by an xHCI Supported Protocol Capability, described in section 7.2 * of xHCI specification. Software shall refer to these capabilities to identify whether a * specific Port Number is valid, and the protocol supported by the associated Port Register Set */ #define USB3_HCSPARAMS1_MaxPorts(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS1_MaxPorts_SHIFT)) & USB3_HCSPARAMS1_MaxPorts_MASK) /*! @} */ /*! @name HCSPARAMS2 - Structural Parameters 2 */ /*! @{ */ #define USB3_HCSPARAMS2_IST_MASK (0xFU) #define USB3_HCSPARAMS2_IST_SHIFT (0U) /*! IST - Isochronous Scheduling Threshold (IST). Default = implementation dependent. The value in * this field indicates to system software the minimum distance (in time) that it is required to * stay ahead of the host controller while adding TRBs, in order to have the host controller * process them at the correct time. The value shall be specified in terms of number of * frames/microframes. If bit [3] of IST is cleared to '0', software can add a TRB no later than IST[2:0] * Microframes before that TRB is scheduled to be executed. If bit [3] of IST is set to '1', software * can add a TRB no later than IST[2:0] Frames before that TRB is scheduled to be executed. Refer * to Section 4.14.2 of xHCI specification for details on how software uses this information for * scheduling isochronous transfers */ #define USB3_HCSPARAMS2_IST(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_IST_SHIFT)) & USB3_HCSPARAMS2_IST_MASK) #define USB3_HCSPARAMS2_ERSTMax_MASK (0xF0U) #define USB3_HCSPARAMS2_ERSTMax_SHIFT (4U) /*! ERSTMax - Event Ring Segment Table Max (ERST Max). Default = implementation dependent. Valid * values are 0-15. This field determines the maximum value supported the Event Ring Segment Table * Base Size registers (5.5.2.3.1), where: The maximum number of Event Ring Segment Table entries * = 2 ^(ERSTMax), e.g. if the ERST Max = 7, then the xHC Event Ring Segment Table(s) supports up * to 128 entries, 15 then 32K entries, etc */ #define USB3_HCSPARAMS2_ERSTMax(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_ERSTMax_SHIFT)) & USB3_HCSPARAMS2_ERSTMax_MASK) #define USB3_HCSPARAMS2_MaxSPBufHi_MASK (0x3E00000U) #define USB3_HCSPARAMS2_MaxSPBufHi_SHIFT (21U) /*! MaxSPBufHi - Max Scratchpad Buffers (Max Scratchpad Bufs Hi). Default = implementation * dependent. This field indicates the high order 5 bits of the number of Scratchpad Buffers system * software shall reserve for the xHC. Refer to section 4.20 of xHCI specification for more information */ #define USB3_HCSPARAMS2_MaxSPBufHi(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_MaxSPBufHi_SHIFT)) & USB3_HCSPARAMS2_MaxSPBufHi_MASK) #define USB3_HCSPARAMS2_SPR_MASK (0x4000000U) #define USB3_HCSPARAMS2_SPR_SHIFT (26U) /*! SPR - Scratchpad Restore (SPR). Default = implementation dependent. If Max Scratchpad Buffers is * > 0 then this flag indicates whether the xHC uses the Scratchpad Buffers for saving state * when executing Save and Restore State operations. If Max Scratchpad Buffers is = 0 then this flag * shall be 0. Refer to section 4.23.2 of xHCI specification for more information. A value of * '1' indicates that the xHC requires the integrity of the Scratchpad Buffer space to be * maintained across power events. A value of '0' indicates that the Scratchpad Buffer space may be freed * and reallocated between power events */ #define USB3_HCSPARAMS2_SPR(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_SPR_SHIFT)) & USB3_HCSPARAMS2_SPR_MASK) #define USB3_HCSPARAMS2_MaxSPBufLo_MASK (0xF8000000U) #define USB3_HCSPARAMS2_MaxSPBufLo_SHIFT (27U) /*! MaxSPBufLo - Max Scratchpad Buffers (Max Scratchpad Bufs Lo). Default = implementation * dependent. Valid values for Max Scratchpad Buffers (Hi and Lo) are 0-1023. This field indicates the low * order 5 bits of the number of Scratchpad Buffers system software shall reserve for the xHC. * Refer to section 4.20 of xHCI specification for more information */ #define USB3_HCSPARAMS2_MaxSPBufLo(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_MaxSPBufLo_SHIFT)) & USB3_HCSPARAMS2_MaxSPBufLo_MASK) /*! @} */ /*! @name HCSPARAMS3 - Structural Parameters 3 */ /*! @{ */ #define USB3_HCSPARAMS3_U1DevExitLat_MASK (0xFFU) #define USB3_HCSPARAMS3_U1DevExitLat_SHIFT (0U) /*! U1DevExitLat - U1 Device Exit Latency. Worst case latency to transition a root hub Port Link * State (PLS) from U1 to U0. Applies to all root hub ports. The following are permissible values: * 00h Zero, 01h Less than 1 s., 02h Less than 2 s., ... 0Ah Less than 10 s., 0B-FFh Reserved */ #define USB3_HCSPARAMS3_U1DevExitLat(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS3_U1DevExitLat_SHIFT)) & USB3_HCSPARAMS3_U1DevExitLat_MASK) #define USB3_HCSPARAMS3_U2DevExitLat_MASK (0xFFFF0000U) #define USB3_HCSPARAMS3_U2DevExitLat_SHIFT (16U) /*! U2DevExitLat - U2 Device Exit Latency. Worst case latency to transition from U2 to U0. Applies * to all root hub ports. The following are permissible values: 0000h Zero, 0001h Less than 1 s., * 0002h Less than 2 s., ... 07FFh Less than 2047 s., 0800-FFFFh Reserved */ #define USB3_HCSPARAMS3_U2DevExitLat(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS3_U2DevExitLat_SHIFT)) & USB3_HCSPARAMS3_U2DevExitLat_MASK) /*! @} */ /*! @name HCCPARAMS - Capability Parameters */ /*! @{ */ #define USB3_HCCPARAMS_AC64_MASK (0x1U) #define USB3_HCCPARAMS_AC64_SHIFT (0U) /*! AC64 - 64-bit Addressing Capability (AC64). This flag documents the addressing range capability * of this implementation. The value of this flag determines whether the xHC has implemented the * high order 32 bits of 64 bit register and data structure pointer fields. Values for this flag * have the following interpretation: '0': 32-bit address memory pointers implemented, '1': * 64-bit address memory pointers implemented. If 32-bit address memory pointers are implemented, the * xHC shall ignore the high order 32 bits of 64 bit data structure pointer fields, and system * software shall ignore the high order 32 bits of 64 bit xHC registers */ #define USB3_HCCPARAMS_AC64(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_AC64_SHIFT)) & USB3_HCCPARAMS_AC64_MASK) #define USB3_HCCPARAMS_BNC_MASK (0x2U) #define USB3_HCCPARAMS_BNC_SHIFT (1U) /*! BNC - BW Negotiation Capability (BNC). This flag identifies whether the xHC has implemented the * Bandwidth Negotiation. Values for this flag have the following interpretation: '0': BW * Negotiation not implemented '1': BW Negotiation implemented Refer to section 4.16 of xHCI * specification for more information on Bandwidth Negotiation */ #define USB3_HCCPARAMS_BNC(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_BNC_SHIFT)) & USB3_HCCPARAMS_BNC_MASK) #define USB3_HCCPARAMS_CSZ_MASK (0x4U) #define USB3_HCCPARAMS_CSZ_SHIFT (2U) /*! CSZ - Context Size (CSZ). If this bit is set to '1', then the xHC uses 64 byte Context data * structures. If this bit is cleared to 0, then the xHC uses 32 byte Context data structures. Note: * This flag does not apply to Stream Contexts */ #define USB3_HCCPARAMS_CSZ(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_CSZ_SHIFT)) & USB3_HCCPARAMS_CSZ_MASK) #define USB3_HCCPARAMS_PPC_MASK (0x8U) #define USB3_HCCPARAMS_PPC_SHIFT (3U) /*! PPC - Port Power Control (PPC). This flag indicates whether the host controller implementation * includes port power control. A '1' in this bit indicates the ports have port power switches. A * '0' in this bit indicates the port do not have port power switches. The value of this flag * affects the functionality of the PP flag in each port status and control register (refer to * Section 5.4.8 of xHCI specification). When DEBUG_CTRL_REG capability is used * (CDNS_RM_CBIT_DEBUG_CTRL_REG is not defined) then this bit is treated as RW. Its value can be changed only by writes * to bit 8 of DEBUG_CTRL_REG (port_pwr_ctrl_toggle). Direct writes to this bit are not possible */ #define USB3_HCCPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_PPC_SHIFT)) & USB3_HCCPARAMS_PPC_MASK) #define USB3_HCCPARAMS_PIND_MASK (0x10U) #define USB3_HCCPARAMS_PIND_SHIFT (4U) /*! PIND - Port Indicators (PIND). This bit indicates whether the xHC root hub ports support port * indicator control. When this bit is a '1', the port status and control registers include a * read/writeable field for controlling the state of the port indicator. Refer to Section 5.4.8 of * xHCI specification for definition of the Port Indicator Control field (PIC field of PORTSC * register) */ #define USB3_HCCPARAMS_PIND(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_PIND_SHIFT)) & USB3_HCCPARAMS_PIND_MASK) #define USB3_HCCPARAMS_LHRC_MASK (0x20U) #define USB3_HCCPARAMS_LHRC_SHIFT (5U) /*! LHRC - Light HC Reset Capability (LHRC). This flag indicates whether the host controller * implementation supports a Light Host Controller Reset. A '1' in this bit indicates that Light Host * Controller Reset is supported. A '0' in this bit indicates that Light Host Controller Reset is * not supported. The value of this flag affects the functionality of the Light Host Controller * Reset (LHCRST) flag in the USBCMD register (refer to Section 5.4.1 of xHCI specification) */ #define USB3_HCCPARAMS_LHRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_LHRC_SHIFT)) & USB3_HCCPARAMS_LHRC_MASK) #define USB3_HCCPARAMS_LTC_MASK (0x40U) #define USB3_HCCPARAMS_LTC_SHIFT (6U) /*! LTC - Latency Tolerance Messaging Capability (LTC). This flag indicates whether the host * controller implementation supports Latency Tolerance Messaging (LTM). A '1' in this bit indicates * that LTM is supported. A 0 in this bit indicates that LTM is not supported. Refer to section * 4.13.1 of xHCI specification for more information on LTM */ #define USB3_HCCPARAMS_LTC(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_LTC_SHIFT)) & USB3_HCCPARAMS_LTC_MASK) #define USB3_HCCPARAMS_NSS_MASK (0x80U) #define USB3_HCCPARAMS_NSS_SHIFT (7U) /*! NSS - No Secondary SID Support (NSS). This flag indicates whether the host controller * implementation supports Secondary Stream IDs. A '1'in this bit indicates that Secondary Stream ID * decoding is not supported. A '0' in this bit indicates that Secondary Stream ID decoding is * supported. (refer to Sections 4.12.2 and 6.2.3 of xHCI specification) */ #define USB3_HCCPARAMS_NSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_NSS_SHIFT)) & USB3_HCCPARAMS_NSS_MASK) #define USB3_HCCPARAMS_PAE_MASK (0x100U) #define USB3_HCCPARAMS_PAE_SHIFT (8U) /*! PAE - Parse All Event Data (PAE). This flag indicates whether the host controller implementation * Parses all Event Data TRBs while advancing to the next TD after a Short Packet, or it skips * all but the first Event Data TRB. A '1' in this bit indicates that all Event Data TRBs are * parsed. A '0' in this bit indicates that only the first Event Data TRB is parsed (refer to section * 4.10.1.1 of xHCI specification) */ #define USB3_HCCPARAMS_PAE(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_PAE_SHIFT)) & USB3_HCCPARAMS_PAE_MASK) #define USB3_HCCPARAMS_SPC_MASK (0x200U) #define USB3_HCCPARAMS_SPC_SHIFT (9U) /*! SPC - Stopped - Short Packet Capability (SPC). This flag indicates that the host controller * implementation is capable of generating a Stopped - Short Packet Completion Code. Refer to section * 4.6.9 of xHCI specification for more information */ #define USB3_HCCPARAMS_SPC(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_SPC_SHIFT)) & USB3_HCCPARAMS_SPC_MASK) #define USB3_HCCPARAMS_MaxPSASize_MASK (0xF000U) #define USB3_HCCPARAMS_MaxPSASize_SHIFT (12U) /*! MaxPSASize - Maximum Primary Stream Array Size (MaxPSASize). This fields identifies the maximum * size Primary Stream Array that the xHC supports. The Primary Stream Array size = * 2MaxPSASize+1. Valid MaxPSASize values are 0 to 15, where 0 indicates that Streams are not supported */ #define USB3_HCCPARAMS_MaxPSASize(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_MaxPSASize_SHIFT)) & USB3_HCCPARAMS_MaxPSASize_MASK) #define USB3_HCCPARAMS_xECP_MASK (0xFFFF0000U) #define USB3_HCCPARAMS_xECP_SHIFT (16U) /*! xECP - xHCI Extended Capabilities Pointer (xECP). This field indicates the existence of a * capabilities list. The value of this field indicates a relative offset, in 32-bit words, from Base * to the beginning of the first extended capability. For example, using the offset of Base is * 1000h and the xECP value of 0068h, we can calculate the following effective address of the first * extended capability: 1000h + (0068h << 2) -> 1000h + 01A0h -> 11A0h */ #define USB3_HCCPARAMS_xECP(x) (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_xECP_SHIFT)) & USB3_HCCPARAMS_xECP_MASK) /*! @} */ /*! @name DBOFF - DoorBell Array Offset */ /*! @{ */ #define USB3_DBOFF_DAO_MASK (0xFFFFFFFCU) #define USB3_DBOFF_DAO_SHIFT (2U) /*! DAO - Doorbell Array Offset, RO. Default = implementation dependent. This field defines the * offset in Dwords of the Doorbell Array base address from the Base (i.e. the base address of the * xHCI Capability register address space) */ #define USB3_DBOFF_DAO(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBOFF_DAO_SHIFT)) & USB3_DBOFF_DAO_MASK) /*! @} */ /*! @name RTSOFF - xHCI Runtime Registers Offset */ /*! @{ */ #define USB3_RTSOFF_RRSO_MASK (0xFFFFFFE0U) #define USB3_RTSOFF_RRSO_SHIFT (5U) /*! RRSO - Runtime Register Space Offset, RO. Default = implementation dependent. This field defines * the 32-byte offset of the xHCI Runtime Registers from the Base. i.e. Runtime Register Base * Address = Base + Runtime Register Set Offset */ #define USB3_RTSOFF_RRSO(x) (((uint32_t)(((uint32_t)(x)) << USB3_RTSOFF_RRSO_SHIFT)) & USB3_RTSOFF_RRSO_MASK) /*! @} */ /*! @name USBCMD - USB Command */ /*! @{ */ #define USB3_USBCMD_R_S_MASK (0x1U) #define USB3_USBCMD_R_S_SHIFT (0U) /*! R_S - Run/Stop (R/S), RW. Default = '0'. '1' = Run. '0' = Stop. When set to a '1', the xHC * proceeds with execution of the schedule. The xHC continues execution as long as this bit is set to * a '1'. When this bit is cleared to '0', the xHC completes any current or queued commands or * TDs, and any USB transactions associated with them, then halts. Refer to section 5.4.1.1 of xHCI * specification for more information on how R/S shall be managed. The xHC shall halt within 16 * ms after software clears the Run/Stop bit if the above conditions have been met. The HCHalted * (HCH) bit in the USBSTS register indicates when the xHC has finished its pending pipelined * transactions and has entered the stopped state. Software shall not write a '1' to this flag * unless the xHC is in the Halted state (i.e. HCH in the USBSTS register is '1'). Doing so may yield * undefined results. Writing a '0' to this flag when the xHC is in the Running state (i.e. HCH = * '0') and any Event Rings are in the Event Ring Full state (refer to section 4.9.4 of xHCI * specification) may result in lost events. When this register is exposed by a Virtual Function * (VF), this bit only controls the run state of the xHC instance presented by the selected VF. * Refer to section 8 of xHCI specification for more information */ #define USB3_USBCMD_R_S(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_R_S_SHIFT)) & USB3_USBCMD_R_S_MASK) #define USB3_USBCMD_HCRST_MASK (0x2U) #define USB3_USBCMD_HCRST_SHIFT (1U) /*! HCRST - Host Controller Reset (HCRST), RW. Default = '0'. This control bit is used by software * to reset the host controller. The effects of this bit on the xHC and the Root Hub registers are * similar to a Chip Hardware Reset. When software writes a '1' to this bit, the Host Controller * resets its internal pipelines, timers, counters, state machines, etc. to their initial value. * Any transaction currently in progress on the USB is immediately terminated. A USB reset shall * not be driven on USB2 downstream ports, however a Hot or Warm Reset shall be initiated on * USB3 Root Hub downstream ports. PCI Configuration registers are not affected by this reset. All * operational registers, including port registers and port state machines are set to their * initial values. Software shall reinitialize the host controller as described in Section 4.1 of xHCI * specification in order to return the host controller to an operational state. This bit is * cleared to '0' by the Host Controller when the reset process is complete. Software cannot * terminate the reset process early by writing a '0' to this bit and shall not write any xHC Operational * or Runtime registers until while HCRST is '1'. Note, the completion of the xHC reset process * is not gated by the Root Hub port reset process. Software shall not set this bit to '1' when * the HCHalted (HCH) bit in the USBSTS register is a '0'. Attempting to reset an actively running * host controller may result in undefined behavior. When this register is exposed by a Virtual * Function (VF), this bit only resets the xHC instance presented by the selected VF. Refer to * section 8 of xHCI specification for more information */ #define USB3_USBCMD_HCRST(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_HCRST_SHIFT)) & USB3_USBCMD_HCRST_MASK) #define USB3_USBCMD_INTE_MASK (0x4U) #define USB3_USBCMD_INTE_SHIFT (2U) /*! INTE - Interrupter Enable (INTE), RW. Default = '0'. This bit provides system software with a * means of enabling or disabling the host system interrupts generated by Interrupters. When this * bit is a '1', then Interrupter host system interrupt generation is allowed, e.g. the xHC shall * issue an interrupt at the next interrupt threshold if the host system interrupt mechanism * (e.g. MSI, MSIX, etc.) is enabled. The interrupt is acknowledged by a host system interrupt * specific mechanism. When this register is exposed by a Virtual Function (VF), this bit only enables * the set of Interrupters assigned to the selected VF. Refer to section 7.7.2 of xHCI * specification for more information */ #define USB3_USBCMD_INTE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_INTE_SHIFT)) & USB3_USBCMD_INTE_MASK) #define USB3_USBCMD_HSEE_MASK (0x8U) #define USB3_USBCMD_HSEE_SHIFT (3U) /*! HSEE - Host System Error Enable (HSEE), RW. Default = '0'. When this bit is a '1', and the HSE * bit in the USBSTS register is a '1', the xHC shall assert out-of-band error signaling to the * host. The signaling is acknowledged by software clearing the HSE bit. Refer to section 4.10.2.6 * of xHCI specification for more information. When this register is exposed by a Virtual * Function (VF), the effect of the assertion of this bit on the Physical Function (PF0) is determined * by the VMM. Refer to section 8 of xHCI specification for more information */ #define USB3_USBCMD_HSEE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_HSEE_SHIFT)) & USB3_USBCMD_HSEE_MASK) #define USB3_USBCMD_LHCRST_MASK (0x80U) #define USB3_USBCMD_LHCRST_SHIFT (7U) /*! LHCRST - Light Host Controller Reset (LHCRST), RO or RW. Optional normative. Default = '0'. If * the Light HC Reset Capability (LHRC) bit in the HCCPARAMS register is '1', then this flag * allows the driver to reset the xHC without affecting the state of the ports. A system software read * of this bit as '0' indicates the Light Host Controller Reset has completed and it is safe for * software to re-initialize the xHC. A software read of this bit as a '1' indicates that the * Light Host Controller Reset has not yet completed. If not implemented, a read of this flag shall * always return a '0'. All registers in the Aux Power well shall maintain the values that had * been asserted prior to the Light Host Controller Reset. Refer to section 4.23.1 of xHCI * specification for more information. When this register is exposed by a Virtual Function (VF), this * bit only generates a Light Reset to the xHC instance presented by the selected VF, e.g. Disable * the VFs device slots and set the associated VF Run bit to Stopped. Refer to section 8 of xHCI * specification for more information */ #define USB3_USBCMD_LHCRST(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_LHCRST_SHIFT)) & USB3_USBCMD_LHCRST_MASK) #define USB3_USBCMD_CSS_MASK (0x100U) #define USB3_USBCMD_CSS_SHIFT (8U) /*! CSS - Controller Save State (CSS), RW. Default = '0'. When written by software with '1' and * HCHalted (HCH) = '1', then the xHC shall save any internal state that may be restored by a * subsequent Restore State operation. When written by software with '1' and HCHalted (HCH) = '0', or * written with '0', no Save State operation shall be performed. This flag always returns '0' when * read. Refer to the Save State Status (SSS) flag in the USBSTS register for information on Save * State completion. Refer to section 4.23.2 of xHCI specification for more information on xHC * Save/Restore operation. Note that undefined behavior may occur if a Save State operation is * initiated while Restore State Status (RSS) ='1'. When this register is exposed by a Virtual * Function (VF), this bit only controls saving the state of the xHC instance presented by the * selected VF. Refer to section 8 of xHCI specifications for more information */ #define USB3_USBCMD_CSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_CSS_SHIFT)) & USB3_USBCMD_CSS_MASK) #define USB3_USBCMD_CRS_MASK (0x200U) #define USB3_USBCMD_CRS_SHIFT (9U) /*! CRS - Controller Restore State (CRS), RW. Default = '0'. When set to '1', and HCHalted (HCH) = * '1', then the xHC shall perform a Restore State operation and restore its internal state. When * set to '1' and Run/Stop (R/S) = '1' or HCHalted (HCH) = '0', or when cleared to '0', no * Restore State operation shall be performed. This flag always returns '0' when read. Refer to the * Restore State Status (RSS) flag in the USBSTS register for information on Restore State * completion. Refer to section 4.23.2 of xHCI specification for more information. Note that undefined * behavior may occur if a Restore State operation is initiated while Save State Status (SSS) = '1'. * When this register is exposed by a Virtual Function (VF), this bit only controls restoring * the state of the xHC instance presented by the selected VF. Refer to section 8 of xHCI * specification for more information */ #define USB3_USBCMD_CRS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_CRS_SHIFT)) & USB3_USBCMD_CRS_MASK) #define USB3_USBCMD_EWE_MASK (0x400U) #define USB3_USBCMD_EWE_SHIFT (10U) /*! EWE - Enable Wrap Event (EWE), RW. Default = '0'. When set to '1', the xHC shall generate a * MFINDEX Wrap Event every time the MFINDEX register transitions from 03FFFh to 0. When cleared to * '0' no MFINDEX Wrap Events are generated. Refer to section 4.14.2 of xHCI specification for * more information. When this register is exposed by a Virtual Function (VF), the generation of * MFINDEX Wrap Events to VFs shall be emulated by the VMM */ #define USB3_USBCMD_EWE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_EWE_SHIFT)) & USB3_USBCMD_EWE_MASK) #define USB3_USBCMD_EU3S_MASK (0x800U) #define USB3_USBCMD_EU3S_SHIFT (11U) /*! EU3S - Enable U3 MFINDEX Stop (EU3S), RW. Default = '0'. When set to '1', the xHC may stop the * MFINDEX counting action if all Root Hub ports are in the U3, Disconnected, Disabled, or * Powered-off state. When cleared to '0' the xHC may stop the MFINDEX counting action if all Root Hub * ports are in the Disconnected, Disabled, Training, or Powered-off state. Refer to section * 4.14.2 of xHCI specification for more information */ #define USB3_USBCMD_EU3S(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_EU3S_SHIFT)) & USB3_USBCMD_EU3S_MASK) /*! @} */ /*! @name USBSTS - USB Status */ /*! @{ */ #define USB3_USBSTS_HCH_MASK (0x1U) #define USB3_USBSTS_HCH_SHIFT (0U) /*! HCH - HCHalted (HCH), RO. Default = '1'. This bit is a '0' whenever the Run/Stop (R/S) bit is a * '1'. The xHC sets this bit to '1' after it has stopped executing as a result of the Run/Stop * (R/S) bit being cleared to '0', either by software or by the xHC hardware (e.g. internal * error). If this bit is '1', then SOFs, microSOFs, or Isochronous Timestamp Packets (ITP) shall not * be generated by the xHC, and any received Transaction Packet shall be dropped. When this * register is exposed by a Virtual Function (VF), this bit only reflects the Halted state of the xHC * instance presented by the selected VF. Refer to section 8 of xHCI specification for more * information */ #define USB3_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_HCH_SHIFT)) & USB3_USBSTS_HCH_MASK) #define USB3_USBSTS_HSE_MASK (0x4U) #define USB3_USBSTS_HSE_SHIFT (2U) /*! HSE - Host System Error (HSE), RW1C. Default = '0'. The xHC sets this bit to '1' when a serious * error is detected, either internal to the xHC or during a host system access involving the xHC * module. (In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI * Master Abort, and PCI Target Abort.) When this error occurs, the xHC clears the Run/Stop (R/S) * bit in the USBCMD register to prevent further execution of the scheduled TDs. If the HSEE bit in * the USBCMD register is a '1', the xHC shall also assert out-of-band error signaling to the * host. Refer to section 4.10.2.6 of xHCI specification for more information. When this register * is exposed by a Virtual Function (VF), the assertion of this bit affects all VFs and reflects * the Host System Error state of the Physical Function (PF0). Refer to section 8 of xHCI * specification for more information */ #define USB3_USBSTS_HSE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_HSE_SHIFT)) & USB3_USBSTS_HSE_MASK) #define USB3_USBSTS_EINT_MASK (0x8U) #define USB3_USBSTS_EINT_SHIFT (3U) /*! EINT - Event Interrupt (EINT), RW1C. Default = '0'. The xHC sets this bit to '1' when the * Interrupt Pending (IP) bit of any Interrupter transitions from '0' to '1'. Refer to section 7.1.2 of * xHCI specification for use. Software that uses EINT shall clear it prior to clearing any IP * flags. A race condition may occur if software clears the IP flags then clears the EINT flag, * and between the operations another IP '0' to '1' transition occurs. In this case the new IP * transition shall be lost. When this register is exposed by a Virtual Function (VF), this bit is * the logical 'OR' of the IP bits for the Interrupters assigned to the selected VF. And it shall * be cleared to '0' when all associated interrupter IP bits are cleared, i.e. all the VFs * Interrupter Event Ring(s) are empty. Refer to section 8 of xHCI specification for more information */ #define USB3_USBSTS_EINT(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_EINT_SHIFT)) & USB3_USBSTS_EINT_MASK) #define USB3_USBSTS_PCD_MASK (0x10U) #define USB3_USBSTS_PCD_SHIFT (4U) /*! PCD - Port Change Detect (PCD), RW1C. Default = '0'. The xHC sets this bit to a '1' when any * port has a change bit transition from a '0' to a '1'. This bit is allowed to be maintained in the * Aux Power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the * xHC, this bit is loaded with the OR of all of the PORTSC change bits. Refer to section 4.19.3 of * xHCI specification. This bit provides system software an efficient means of determining if * there has been Root Hub port activity. Refer to section 4.15.2.3 of xHCI specification for more * information. When this register is exposed by a Virtual Function (VF), the VMM determines the * state of this bit as a function of the Root Hub Ports associated with the Device Slots assigned * to the selected VF. Refer to section 8 of xHCI specification for more information */ #define USB3_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_PCD_SHIFT)) & USB3_USBSTS_PCD_MASK) #define USB3_USBSTS_SSS_MASK (0x100U) #define USB3_USBSTS_SSS_SHIFT (8U) /*! SSS - Save State Status (SSS), RO. Default = '0'. When the Controller Save State (CSS) flag in * the USBCMD register is written with '1' this bit shall be set to '1' and remain '1' while the * xHC saves its internal state. When the Save State operation is complete, this bit shall be * cleared to '0'. Refer to section 4.23.2 of xHCI specification for more information. When this * register is exposed by a Virtual Function (VF), the VMM determines the state of this bit as a * function of the saving the state for the selected VF. Refer to section 8 of xHCI specification for * more information */ #define USB3_USBSTS_SSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_SSS_SHIFT)) & USB3_USBSTS_SSS_MASK) #define USB3_USBSTS_RSS_MASK (0x200U) #define USB3_USBSTS_RSS_SHIFT (9U) /*! RSS - Restore State Status (RSS), RO. Default = '0'. When the Controller Restore State (CRS) * flag in the USBCMD register is written with '1' this bit shall be set to '1' and remain '1' while * the xHC restores its internal state. When the Restore State operation is complete, this bit * shall be cleared to '0'. Refer to section 4.23.2 of xHCI specification for more information. * When this register is exposed by a Virtual Function (VF), the VMM determines the state of this * bit as a function of the restoring the state for the selected VF. Refer to section 8 of xHCI * specification for more information */ #define USB3_USBSTS_RSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_RSS_SHIFT)) & USB3_USBSTS_RSS_MASK) #define USB3_USBSTS_SRE_MASK (0x400U) #define USB3_USBSTS_SRE_SHIFT (10U) /*! SRE - Save/Restore Error (SRE), RW1C. Default = '0'. If an error occurs during a Save or Restore * operation this bit shall be set to '1'. This bit shall be cleared to '0' when a Save or * Restore operation is initiated or when written with '1'. Refer to section 4.23.2 of xHCI * specification for more information. When this register is exposed by a Virtual Function (VF), the VMM * determines the state of this bit as a function of the Save/Restore completion status for the * selected VF. Refer to section 8 of xHCI specification for more information */ #define USB3_USBSTS_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_SRE_SHIFT)) & USB3_USBSTS_SRE_MASK) #define USB3_USBSTS_CNR_MASK (0x800U) #define USB3_USBSTS_CNR_SHIFT (11U) /*! CNR - Controller Not Ready (CNR), RO. Default = '1'. '0' = Ready and '1' = Not Ready. When this * bit is '1', software shall not read or write any register of the xHC, other than those * explicitly listed in the Design Specification section titled Register Accessibility. This flag is set * by the xHC after a Chip Hardware Reset and cleared when the xHC is ready to begin accepting * register reads or writes to all registers. This flag shall remain cleared ('0') until the next * Chip Hardware Reset */ #define USB3_USBSTS_CNR(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_CNR_SHIFT)) & USB3_USBSTS_CNR_MASK) #define USB3_USBSTS_HCE_MASK (0x1000U) #define USB3_USBSTS_HCE_SHIFT (12U) /*! HCE - Host Controller Error (HCE), RO. Default = '0'. '0' = No internal xHC error conditions * exist and '1' = Internal xHC error condition. This flag shall be set to indicate that an internal * error condition has been detected which requires software to reset and reinitialize the xHC. * Refer to section 4.24.1 of xHCI specification for more information */ #define USB3_USBSTS_HCE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_HCE_SHIFT)) & USB3_USBSTS_HCE_MASK) /*! @} */ /*! @name PAGESIZE - Page Size */ /*! @{ */ #define USB3_PAGESIZE_PAGESIZE_MASK (0xFFFFU) #define USB3_PAGESIZE_PAGESIZE_SHIFT (0U) /*! PAGESIZE - Page Size, RO. Default = Implementation defined. This field defines the page size * supported by the xHC implementation. This xHC supports a page size of 2^(n+12) if bit n is Set. * For example, if bit 0 is Set, the xHC supports 4k byte page sizes. For a Virtual Function, this * register reflects the page size selected in the System Page Size field of the SR-IOV Extended * Capability structure. For the Physical Function 0, this register reflects the implementation * dependent default xHC page size. Various xHC resources reference PAGESIZE to describe their * minimum alignment requirements. The maximum possible page size is 128M */ #define USB3_PAGESIZE_PAGESIZE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PAGESIZE_PAGESIZE_SHIFT)) & USB3_PAGESIZE_PAGESIZE_MASK) /*! @} */ /*! @name DNCTRL - Device Notification Control */ /*! @{ */ #define USB3_DNCTRL_N0_MASK (0x1U) #define USB3_DNCTRL_N0_SHIFT (0U) /*! N0 - Notification Enable flag 0 */ #define USB3_DNCTRL_N0(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N0_SHIFT)) & USB3_DNCTRL_N0_MASK) #define USB3_DNCTRL_N1_MASK (0x2U) #define USB3_DNCTRL_N1_SHIFT (1U) /*! N1 - Notification Enable flag 1 */ #define USB3_DNCTRL_N1(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N1_SHIFT)) & USB3_DNCTRL_N1_MASK) #define USB3_DNCTRL_N2_MASK (0x4U) #define USB3_DNCTRL_N2_SHIFT (2U) /*! N2 - Notification Enable flag 2. LATENCY_TOLERANCE_MESSAGE */ #define USB3_DNCTRL_N2(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N2_SHIFT)) & USB3_DNCTRL_N2_MASK) #define USB3_DNCTRL_N3_MASK (0x8U) #define USB3_DNCTRL_N3_SHIFT (3U) /*! N3 - Notification Enable flag 3. BUS_INTERVAL_ADJUSTMENT_MESSAGE */ #define USB3_DNCTRL_N3(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N3_SHIFT)) & USB3_DNCTRL_N3_MASK) #define USB3_DNCTRL_N4_MASK (0x10U) #define USB3_DNCTRL_N4_SHIFT (4U) /*! N4 - Notification Enable flag 4 */ #define USB3_DNCTRL_N4(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N4_SHIFT)) & USB3_DNCTRL_N4_MASK) #define USB3_DNCTRL_N5_MASK (0x20U) #define USB3_DNCTRL_N5_SHIFT (5U) /*! N5 - Notification Enable flag 5 */ #define USB3_DNCTRL_N5(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N5_SHIFT)) & USB3_DNCTRL_N5_MASK) #define USB3_DNCTRL_N6_MASK (0x40U) #define USB3_DNCTRL_N6_SHIFT (6U) /*! N6 - Notification Enable flag 6 */ #define USB3_DNCTRL_N6(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N6_SHIFT)) & USB3_DNCTRL_N6_MASK) #define USB3_DNCTRL_N7_MASK (0x80U) #define USB3_DNCTRL_N7_SHIFT (7U) /*! N7 - Notification Enable flag 7 */ #define USB3_DNCTRL_N7(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N7_SHIFT)) & USB3_DNCTRL_N7_MASK) #define USB3_DNCTRL_N8_MASK (0x100U) #define USB3_DNCTRL_N8_SHIFT (8U) /*! N8 - Notification Enable flag 8 */ #define USB3_DNCTRL_N8(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N8_SHIFT)) & USB3_DNCTRL_N8_MASK) #define USB3_DNCTRL_N9_MASK (0x200U) #define USB3_DNCTRL_N9_SHIFT (9U) /*! N9 - Notification Enable flag 9 */ #define USB3_DNCTRL_N9(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N9_SHIFT)) & USB3_DNCTRL_N9_MASK) #define USB3_DNCTRL_N10_MASK (0x400U) #define USB3_DNCTRL_N10_SHIFT (10U) /*! N10 - Notification Enable flag 10 */ #define USB3_DNCTRL_N10(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N10_SHIFT)) & USB3_DNCTRL_N10_MASK) #define USB3_DNCTRL_N11_MASK (0x800U) #define USB3_DNCTRL_N11_SHIFT (11U) /*! N11 - Notification Enable flag 11 */ #define USB3_DNCTRL_N11(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N11_SHIFT)) & USB3_DNCTRL_N11_MASK) #define USB3_DNCTRL_N12_MASK (0x1000U) #define USB3_DNCTRL_N12_SHIFT (12U) /*! N12 - Notification Enable flag 12 */ #define USB3_DNCTRL_N12(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N12_SHIFT)) & USB3_DNCTRL_N12_MASK) #define USB3_DNCTRL_N13_MASK (0x2000U) #define USB3_DNCTRL_N13_SHIFT (13U) /*! N13 - Notification Enable flag 13 */ #define USB3_DNCTRL_N13(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N13_SHIFT)) & USB3_DNCTRL_N13_MASK) #define USB3_DNCTRL_N14_MASK (0x4000U) #define USB3_DNCTRL_N14_SHIFT (14U) /*! N14 - Notification Enable flag 14 */ #define USB3_DNCTRL_N14(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N14_SHIFT)) & USB3_DNCTRL_N14_MASK) #define USB3_DNCTRL_N15_MASK (0x8000U) #define USB3_DNCTRL_N15_SHIFT (15U) /*! N15 - Notification Enable flag 15 */ #define USB3_DNCTRL_N15(x) (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N15_SHIFT)) & USB3_DNCTRL_N15_MASK) /*! @} */ /*! @name CRCR_LO - Command Ring Control Register Low */ /*! @{ */ #define USB3_CRCR_LO_RCS_MASK (0x1U) #define USB3_CRCR_LO_RCS_SHIFT (0U) /*! RCS - Ring Cycle State (RCS), RW. This bit identifies the value of the xHC Consumer Cycle State * (CCS) flag for the TRB referenced by the Command Ring Pointer. Refer to section 4.9.3 of xHCI * specification for more information. Writes to this flag are ignored if Command Ring Running * (CRR) is '1'. If the CRCR is written while the Command Ring is stopped (CRR = '0'), then the * value of this flag shall be used to fetch the first Command TRB the next time the Host Controller * Doorbell register is written with the DB Reason field set to Host Controller Command. If the * CRCR is not written while the Command Ring is stopped (CRR = '0'), then the Command Ring shall * begin fetching Command TRBs using the current value of the internal Command Ring CCS flag. * Reading this flag always returns '0' */ #define USB3_CRCR_LO_RCS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_RCS_SHIFT)) & USB3_CRCR_LO_RCS_MASK) #define USB3_CRCR_LO_CS_MASK (0x2U) #define USB3_CRCR_LO_CS_SHIFT (1U) /*! CS - Command Stop (CS), RW1S. Default = '0'. Writing a '1' to this bit shall stop the operation * of the Command Ring after the completion of the currently executing command, and generate a * Command Completion Event with the Completion Code set to Command Ring Stopped and the Command * TRB Pointer set to the current value of the Command Ring Dequeue Pointer. Refer to section * 4.6.1.1 of xHCI specification for more information on stopping a command. The next write to the * Host Controller Doorbell with DB Reason field set to Host Controller Command shall restart the * Command Ring operation. Writes to this flag are ignored by the xHC if Command Ring Running (CRR) * = '0'. Reading this bit shall always return '0' */ #define USB3_CRCR_LO_CS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CS_SHIFT)) & USB3_CRCR_LO_CS_MASK) #define USB3_CRCR_LO_CA_MASK (0x4U) #define USB3_CRCR_LO_CA_SHIFT (2U) /*! CA - Command Abort (CA), RW1S. Default = '0'. Writing a '1' to this bit shall immediately * terminate the currently executing command, stop the Command Ring, and generate a Command Completion * Event with the Completion Code set to Command Ring Stopped. Refer to section 4.6.1.2 of xHCI * specification for more information on aborting a command. The next write to the Host Controller * Doorbell with DB Reason field set to Host Controller Command shall restart the Command Ring * operation. Writes to this flag are ignored by the xHC if Command Ring Running (CRR) = '0'. * Reading this bit always returns '0' */ #define USB3_CRCR_LO_CA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CA_SHIFT)) & USB3_CRCR_LO_CA_MASK) #define USB3_CRCR_LO_CRR_MASK (0x8U) #define USB3_CRCR_LO_CRR_SHIFT (3U) /*! CRR - Command Ring Running (CRR), RO. Default = '0'. This flag is set to '1' if the Run/Stop * (R/S) bit is '1' and the Host Controller Doorbell register is written with the DB Reason field * set to Host Controller Command. It is cleared to '0' when the Command Ring is stopped after * writing a '1' to the Command Stop (CS) or Command Abort (CA) flags, or if the R/S bit is cleared * to '0' */ #define USB3_CRCR_LO_CRR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CRR_SHIFT)) & USB3_CRCR_LO_CRR_MASK) #define USB3_CRCR_LO_CRPtr_L_MASK (0xFFFFFFC0U) #define USB3_CRCR_LO_CRPtr_L_SHIFT (6U) /*! CRPtr_L - Command Ring Pointer Low, RW. Default = 0. This field defines low order bits of the * initial value of the 64-bit Command Ring Dequeue Pointer. Writes to this field are ignored when * Command Ring Running (CRR) = '1'. If the CRCR is written while the Command Ring is stopped * (CCR = '0'), the value of this field shall be used to fetch the first Command TRB the next time * the Host Controller Doorbell register is written with the DB Reason field set to Host * Controller Command. If the CRCR is not written while the Command Ring is stopped (CCR = '0') then the * Command Ring shall begin fetching Command TRBs at the current value of the internal xHC Command * Ring Dequeue Pointer. Reading this field always returns zero */ #define USB3_CRCR_LO_CRPtr_L(x) (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CRPtr_L_SHIFT)) & USB3_CRCR_LO_CRPtr_L_MASK) /*! @} */ /*! @name CRCR_HI - Command Ring Control Register High */ /*! @{ */ #define USB3_CRCR_HI_CRPtr_H_MASK (0xFFFFFFFFU) #define USB3_CRCR_HI_CRPtr_H_SHIFT (0U) /*! CRPtr_H - Command Ring Pointer High, RW. Default = 0. This field defines high order bits of the * initial value of the 64-bit Command Ring Dequeue Pointer. Writes to this field are ignored * when Command Ring Running (CRR) = '1'. If the CRCR is written while the Command Ring is stopped * (CCR = '0'), the value of this field shall be used to fetch the first Command TRB the next time * the Host Controller Doorbell register is written with the DB Reason field set to Host * Controller Command. If the CRCR is not written while the Command Ring is stopped (CCR = '0') then the * Command Ring shall begin fetching Command TRBs at the current value of the internal xHC * Command Ring Dequeue Pointer. Reading this field always returns zero */ #define USB3_CRCR_HI_CRPtr_H(x) (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_HI_CRPtr_H_SHIFT)) & USB3_CRCR_HI_CRPtr_H_MASK) /*! @} */ /*! @name DCBAAP_LO - Device Context Base Address Array Pointer(LOW) */ /*! @{ */ #define USB3_DCBAAP_LO_DCBAAPtr_L_MASK (0xFFFFFFC0U) #define USB3_DCBAAP_LO_DCBAAPtr_L_SHIFT (6U) /*! DCBAAPtr_L - Device Context Base Address Array Pointer, RW. Default = 0. This field defines low * order bits of the 64-bit base address of the Device Context Pointer Array. A table of address * pointers that reference Device Context structures for the devices attached to the host */ #define USB3_DCBAAP_LO_DCBAAPtr_L(x) (((uint32_t)(((uint32_t)(x)) << USB3_DCBAAP_LO_DCBAAPtr_L_SHIFT)) & USB3_DCBAAP_LO_DCBAAPtr_L_MASK) /*! @} */ /*! @name DCBAAP_HI - Device Context Base Address Array Pointer (HIGH) */ /*! @{ */ #define USB3_DCBAAP_HI_DCBAAPtr_H_MASK (0xFFFFFFFFU) #define USB3_DCBAAP_HI_DCBAAPtr_H_SHIFT (0U) /*! DCBAAPtr_H - Device Context Base Address Array Pointer, RW. Default = 0. This field defines high * order bits of the 64-bit base address of the Device Context Pointer Array. A table of address * pointers that reference Device Context structures for the devices attached to the host */ #define USB3_DCBAAP_HI_DCBAAPtr_H(x) (((uint32_t)(((uint32_t)(x)) << USB3_DCBAAP_HI_DCBAAPtr_H_SHIFT)) & USB3_DCBAAP_HI_DCBAAPtr_H_MASK) /*! @} */ /*! @name CONFIG - Configure */ /*! @{ */ #define USB3_CONFIG_MaxSlotsEn_MASK (0xFFU) #define USB3_CONFIG_MaxSlotsEn_SHIFT (0U) /*! MaxSlotsEn - Max Device Slots Enabled (MaxSlotsEn), RW. Default = 0. This field specifies the * maximum number of enabled Device Slots. Valid values are in the range of 0 to MaxSlots. Enabled * Devices Slots are allocated contiguously. e.g. A value of 16 specifies that Device Slots 1 to * 16 are active. A value of 0 disables all Device Slots. A disabled Device Slot shall not * respond to Doorbell Register references. This field shall not be modified by software if the xHC is * running (Run/Stop (R/S) = 1) */ #define USB3_CONFIG_MaxSlotsEn(x) (((uint32_t)(((uint32_t)(x)) << USB3_CONFIG_MaxSlotsEn_SHIFT)) & USB3_CONFIG_MaxSlotsEn_MASK) /*! @} */ /*! @name PORTSC1USB2 - USB2 Port Status and Control */ /*! @{ */ #define USB3_PORTSC1USB2_CCS_MASK (0x1U) #define USB3_PORTSC1USB2_CCS_SHIFT (0U) /*! CCS - Current Connect Status (CCS), ROS. Default = '0'. '1' = A device is connected to the port. * '0' = A device is not connected. This value reflects the current state of the port, and may * not correspond directly to the event that caused the Connect Status Change (CSC) bit to be set * to '1'. Refer to sections 4.19.3 and 4.19.4 of xHCI specification for more details on the * Connect Status Change (CSC) assertion conditions. This flag is '0' if PP is '0' */ #define USB3_PORTSC1USB2_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_CCS_SHIFT)) & USB3_PORTSC1USB2_CCS_MASK) #define USB3_PORTSC1USB2_PED_MASK (0x2U) #define USB3_PORTSC1USB2_PED_SHIFT (1U) /*! PED - Port Enabled/Disabled (PED), RW1CS. Default = '0'. '1' = Enabled. '0' = Disabled. Ports * may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag. A * port may be disabled by software writing a '1' to this flag. This flag shall automatically be * cleared to '0' by a disconnect event or other fault condition. Note that the bit status does * not change until the port state actually changes. There may be a delay in disabling or enabling * a port due to other host controller or bus events. When the port is disabled (PED = '0') * downstream propagation of data is blocked on this port, except for reset. When the port is in the * Disabled state, software shall reset the port (PR = '1') to transition PED to '1' and the port * to the Enabled state. Note that when software writes this bit to a '1', it shall also write a * '0' to the PR bit. This flag is '0' if PP is '0' */ #define USB3_PORTSC1USB2_PED(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PED_SHIFT)) & USB3_PORTSC1USB2_PED_MASK) #define USB3_PORTSC1USB2_OCA_MASK (0x8U) #define USB3_PORTSC1USB2_OCA_SHIFT (3U) /*! OCA - Over-current Active (OCA), RO. Default = '0'. '1' = This port currently has an * over-current condition. '0' = This port does not have an over-current condition. This bit shall * automatically transition from a '1' to a '0' when the over-current condition is removed */ #define USB3_PORTSC1USB2_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_OCA_SHIFT)) & USB3_PORTSC1USB2_OCA_MASK) #define USB3_PORTSC1USB2_PR_MASK (0x10U) #define USB3_PORTSC1USB2_PR_SHIFT (4U) /*! PR - Port Reset (PR), RW1S. Default = '0'. '1' = Port Reset signaling is asserted. '0' = Port is * not in Reset. When software writes a '1' to this bit generating a '0' to '1' transition, the * bus reset sequence is initiated; USB2 protocol ports shall execute the bus reset sequence as * defined in the USB2 Spec. PR remains set until reset signaling is completed by the root hub. * Note that software shall write a '1' to this flag to transition a USB2 port from the Polling * state to the Enabled state. Refer to sections 4.15.2.3 and 4.19.1.1 of xHCI specification. This * flag is '0' if PP is '0' */ #define USB3_PORTSC1USB2_PR(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PR_SHIFT)) & USB3_PORTSC1USB2_PR_MASK) #define USB3_PORTSC1USB2_PLS_MASK (0x1E0U) #define USB3_PORTSC1USB2_PLS_SHIFT (5U) /*! PLS - Port Link State (PLS), RWS. Default = RxDetect ('5'). This field is used to power manage * the port and reflects its current link state. When the port is in the Enabled state, system * software may set the link U state by writing this field. System software may also write this * field to force a Disabled to Disconnected state transition of the port. Write Values: 0: The link * shall transition to a U0 state from any of the U states. 2: The link should transition to the * U2 State. 3: The link shall transition to a U3 state from the U0 state. This action * selectively suspends the device connected to this port. While the Port Link State = U3, the hub does not * propagate downstream-directed traffic to this port, but the hub shall respond to resume * signaling from the port. 1,4-14: Ignored. 15: If the port is in the U3 state (PLS = U3), then the * link shall remain in the U3 state and the port shall transition to the Resume substate, else * ignored. Refer to section 4.15.2 of xHCI specification for more information. State Encoding: 0: * Link is in the U0 State, 1: Link is in the U1 State, 2: Link is in the U2 State, 3: Link is in * the U3 State (Device Suspended), 4: Link is in the Disabled State, 5: Link is in the RxDetect * State, 6: Link is in the Inactive State, 7: Link is in the Polling State, 8: Link is in the * Recovery State, 9: Link is in the Hot Reset State, 10 Link is in the Compliance Mode State, 11: * Link is in the Test Mode State, 12-14: Reserved, 15: Link is in the Resume State. Note: The * Port Link State Write Strobe (LWS) shall also be set to '1' to write this field. This field is * undefined if PP = '0'. Writing a value of '2' to this field shall request LPM, asserting L1 * signaling on the USB2 bus. Software may read this field to determine if the transition to the U2 * state was successful. Writing a value of '0' shall deassert L1 signaling on the USB. Writing * a value of '1' shall have no effect. The U1 state shall never be reported by a USB2 protocol * port. Note: Transitions between different states are not reflected until the transition is * complete. Refer to section 4.19 of xHCI specification for PLS transition conditions. Refer to * sections 4.15.2 and 4.23.5 for more information on the use of this field. Refer to the USB2 LPM * ECR for more information on USB link power management operation */ #define USB3_PORTSC1USB2_PLS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PLS_SHIFT)) & USB3_PORTSC1USB2_PLS_MASK) #define USB3_PORTSC1USB2_PP_MASK (0x200U) #define USB3_PORTSC1USB2_PP_SHIFT (9U) /*! PP - Port Power (PP), RWS. Default = '1'. This flag reflects a port's logical, power control * state. Because host controllers can implement different methods of port power switching, this * flag may or may not represent whether (VBus) power is actually applied to the port. When PP * equals a '0' the port is nonfunctional and shall not report attaches, detaches, or Port Link State * (PLS) changes. However, the port shall report over-current conditions when PP = '0' if PPC = * '0'. After modifying PP, software shall read PP and confirm that it has reached its target * state before modifying it again, undefined behavior may occur if this procedure is not followed. * '0' = This port is in the Powered-off state. '1' = This port is not in the Powered-off state. * If the Port Power Control (PPC) flag in the HCCPARAMS register is '1', then xHC has port power * control switches and this bit represents the current setting of the switch ('0' = off, * '1'=on). If the Port Power Control (PPC) flag in the HCCPARAMS register is '0', then xHC does not * have port power control switches and each port is hard wired to power, and not affected by this * bit. When an over-current condition is detected on a powered port, the xHC shall transition the * PP bit in each affected port from a '1' to '0' (removing power from the port). Refer to * section 4.19.4 for more information */ #define USB3_PORTSC1USB2_PP(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PP_SHIFT)) & USB3_PORTSC1USB2_PP_MASK) #define USB3_PORTSC1USB2_PortSpeed_MASK (0x3C00U) #define USB3_PORTSC1USB2_PortSpeed_SHIFT (10U) /*! PortSpeed - Port Speed (Port Speed), ROS. Default = '0'. This field identifies the speed of the * connected USB Device. This field is only relevant if a device is connected (CCS = '1') in all * other cases this field shall indicate Undefined Speed. Possible values: 0: Undefined Speed * 1-15: Protocol Speed ID (PSI), refer to section 7.2.1 of xHCI specification for the definition of * PSIV field in the PSI Dword. Note: This field is invalid on a USB2 protocol port until after * the port is reset */ #define USB3_PORTSC1USB2_PortSpeed(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PortSpeed_SHIFT)) & USB3_PORTSC1USB2_PortSpeed_MASK) #define USB3_PORTSC1USB2_PIC_MASK (0xC000U) #define USB3_PORTSC1USB2_PIC_SHIFT (14U) /*! PIC - Port Indicator Control (PIC), RWS. Default = '0'. Writing to these bits has no effect if * the Port Indicators (PIND) bit in the HCCPARAMS register is a '0'. If PIND bit is a '1', then * the bit encodings are: 0: Port indicators are off, 1: Amber, 2: Green, 3: Undefined. Refer to * the USB2 Specification section 11.5.3 for a description on how these bits shall be used. This * field is '0' if PP is '0' */ #define USB3_PORTSC1USB2_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PIC_SHIFT)) & USB3_PORTSC1USB2_PIC_MASK) #define USB3_PORTSC1USB2_LWS_MASK (0x10000U) #define USB3_PORTSC1USB2_LWS_SHIFT (16U) /*! LWS - Port Link State Write Strobe (LWS), RW. Default = '0'. When this bit is set to '1' on a * write reference to this register, this flag enables writes to the PLS field. When '0', write * data in PLS field is ignored. Reads to this bit return '0' */ #define USB3_PORTSC1USB2_LWS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_LWS_SHIFT)) & USB3_PORTSC1USB2_LWS_MASK) #define USB3_PORTSC1USB2_CSC_MASK (0x20000U) #define USB3_PORTSC1USB2_CSC_SHIFT (17U) /*! CSC - Connect Status Change (CSC), RW1CS. Default = '0'. '1' = Change in CCS. '0' = No change. * This flag indicates a change has occurred in the ports Current Connect Status (CCS) or Cold * Attach Status (CAS) bits. Note that this flag shall not be set if the CCS transition was due to * software setting PP to '0', or the CAS transition was due to software setting WPR to '1'. The * xHC sets this bit to '1' for all changes to the port device connect status, even if system * software has not cleared an existing Connect Status Change. For example, the insertion status * changes twice before system software has cleared the changed condition, root hub hardware will be * setting an already-set bit (i.e., the bit will remain 1). Software shall clear this bit by * writing a '1' to it. Refer to section 4.19.2 of xHCI specification for more information on change * bit usage */ #define USB3_PORTSC1USB2_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_CSC_SHIFT)) & USB3_PORTSC1USB2_CSC_MASK) #define USB3_PORTSC1USB2_PEC_MASK (0x40000U) #define USB3_PORTSC1USB2_PEC_SHIFT (18U) /*! PEC - Port Enabled/Disabled Change (PEC), RW1CS. Default = '0'. '1' = change in PED. '0' = No * change. Note that this flag shall not be set if the PED transition was due to software setting * PP to '0'. Software shall clear this bit by writing a '1' to it. Refer to section 4.19.2 of * xHCI specification for more information on change bit usage. This bit shall be set to '1' only * when the port is disabled due to the appropriate conditions existing at the EOF2 point (refer to * section 11.8.1 of the USB2 Specification for the definition of a Port Error) */ #define USB3_PORTSC1USB2_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PEC_SHIFT)) & USB3_PORTSC1USB2_PEC_MASK) #define USB3_PORTSC1USB2_WRC_MASK (0x80000U) #define USB3_PORTSC1USB2_WRC_SHIFT (19U) /*! WRC - Warm Port Reset Change (WRC), RW1CS/RsvdZ. Default = '0'. This bit is set when Warm Reset * processing on this port completes. '0' = No change. '1' = Warm Reset complete. Note that this * flag shall not be set to '1' if the Warm Reset processing was forced to terminate due to * software clearing PP or PED to '0'. Software shall clear this bit by writing a '1' to it. Refer to * section 4.19.5.1 of xHCI specification. Refer to section 4.19.2 of xHCI specification for more * information on change bit usage. This bit only applies to USB3 protocol ports. For USB2 * protocol ports it shall be RsvdZ */ #define USB3_PORTSC1USB2_WRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WRC_SHIFT)) & USB3_PORTSC1USB2_WRC_MASK) #define USB3_PORTSC1USB2_OCC_MASK (0x100000U) #define USB3_PORTSC1USB2_OCC_SHIFT (20U) /*! OCC - Over-current Change (OCC), RW1CS. Default = '0'. This bit shall be set to a '1' when there * is a '0' to '1' or '1' to '0' transition of Over-current Active (OCA). Software shall clear * this bit by writing a '1' to it. Refer to section 4.19.2 of xHCI specification for more * information on change bit usage */ #define USB3_PORTSC1USB2_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_OCC_SHIFT)) & USB3_PORTSC1USB2_OCC_MASK) #define USB3_PORTSC1USB2_PRC_MASK (0x200000U) #define USB3_PORTSC1USB2_PRC_SHIFT (21U) /*! PRC - Port Reset Change (PRC), RW1CS. Default = '0'. This flag is set to '1' due to a '1' to '0' * transition of Port Reset (PR), e.g. when any reset processing (Warm or Hot) on this port is * complete. Note that this flag shall not be set to '1' if the reset processing was forced to * terminate due to software clearing PP or PED to '0'. '0' = No change. '1' = Reset complete. * Software shall clear this bit by writing a '1' to it. Refer to section 4.19.5 of xHCI * specification. Refer to section 4.19.2 of xHCI specification for more information on change bit usage */ #define USB3_PORTSC1USB2_PRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PRC_SHIFT)) & USB3_PORTSC1USB2_PRC_MASK) #define USB3_PORTSC1USB2_PLC_MASK (0x400000U) #define USB3_PORTSC1USB2_PLC_SHIFT (22U) /*! PLC - Port Link State Change (PLC), RW1CS. Default = '0'. This flag is set to '1' due to the * following PLS transitions: U3 -> Resume (Wakeup signaling from a device), Resume -> Recovery -> * U0 (Device Resume complete (USB3 protocol ports only)), Resume -> U0 (Device Resume complete * (USB2 protocol ports only)), U3 -> Recovery -> U0 (Software Resume complete (USB3 protocol ports * only)), U3 -> U0 (Software Resume complete (USB2 protocol ports only)), U2 -> U0 (L1 Resume * complete (USB2 protocol ports only)), U0 -> U0 (L1 Entry Reject (USB2 protocol ports only)), * Any state -> Inactive (Error (USB3 protocol ports only)). Note that this flag shall not be set * if the PLS transition was due to software setting PP to 0. Refer to section 4.23.5 of xHCI * specification for more information. '0' = No change. '1' = Link Status Changed. Software shall * clear this bit by writing a '1' to it. Refer to PLC Condition: references in section 4.19.1 for * the specific port state transitions that set this flag. Refer to section 4.19.2 of xHCI * specification for more information on change bit usage */ #define USB3_PORTSC1USB2_PLC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PLC_SHIFT)) & USB3_PORTSC1USB2_PLC_MASK) #define USB3_PORTSC1USB2_CAS_MASK (0x1000000U) #define USB3_PORTSC1USB2_CAS_SHIFT (24U) /*! CAS - Cold Attach Status (CAS), RO. Default = '0'. '1' = Far-end Receiver Terminations were * detected in the Disconnected state and the Root Hub Port State Machine was unable to advance to * the Enabled state. Refer to sections 4.19.8 of xHCI specification for more details on the Cold * Attach Status (CAS) assertion conditions. Software shall clear this bit by writing a '1' to WPR * or the xHC shall clear this bit if CCS transitions to '1'. This flag is '0' for USB2 protocol * ports */ #define USB3_PORTSC1USB2_CAS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_CAS_SHIFT)) & USB3_PORTSC1USB2_CAS_MASK) #define USB3_PORTSC1USB2_WCE_MASK (0x2000000U) #define USB3_PORTSC1USB2_WCE_SHIFT (25U) /*! WCE - Wake on Connect Enable (WCE), RWS. Default = '0'. Writing this bit to a '1' enables the * port to be sensitive to device connects as system wake-up events. Refer to section 4.15 of xHCI * specification for operational model */ #define USB3_PORTSC1USB2_WCE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WCE_SHIFT)) & USB3_PORTSC1USB2_WCE_MASK) #define USB3_PORTSC1USB2_WDE_MASK (0x4000000U) #define USB3_PORTSC1USB2_WDE_SHIFT (26U) /*! WDE - Wake on Disconnect Enable (WDE), RWS. Default = '0'. Writing this bit to a '1' enables the * port to be sensitive to device disconnects as system wake-up events. Refer to section 4.15 of * xHCI specification for operational model */ #define USB3_PORTSC1USB2_WDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WDE_SHIFT)) & USB3_PORTSC1USB2_WDE_MASK) #define USB3_PORTSC1USB2_WOE_MASK (0x8000000U) #define USB3_PORTSC1USB2_WOE_SHIFT (27U) /*! WOE - Wake on Over-current Enable (WOE), RWS. Default = '0'. Writing this bit to a '1' enables * the port to be sensitive to over-current conditions as system wake-up events. Refer to section * 4.15 of xHCI specification for operational model */ #define USB3_PORTSC1USB2_WOE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WOE_SHIFT)) & USB3_PORTSC1USB2_WOE_MASK) #define USB3_PORTSC1USB2_DR_MASK (0x40000000U) #define USB3_PORTSC1USB2_DR_SHIFT (30U) /*! DR - Device Removable (DR), RO. This flag indicates if this port has a removable device * attached. '0' = Device is removable; '1' = Device is non-removable */ #define USB3_PORTSC1USB2_DR(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_DR_SHIFT)) & USB3_PORTSC1USB2_DR_MASK) /*! @} */ /*! @name PORTPMSC1USB2 - USB2 Port Power Management Status and Control */ /*! @{ */ #define USB3_PORTPMSC1USB2_L1S_MASK (0x7U) #define USB3_PORTPMSC1USB2_L1S_SHIFT (0U) /*! L1S - L1 Status (L1S), RO. Default = 0. This field is used by software to determine whether an * L1-based suspend request (LPM transaction) was successful, specifically: 0: Invalid - This * field shall be ignored by software. 1: Success - Port successfully transitioned to L1 (ACK) 2: Not * Yet - Device is unable to enter L1 at this time (NYET) 3: Not Supported - Device does not * support L1 transitions (STALL) 4: Timeout/Error - Device failed to respond to the LPM Transaction * or an error occurred 5-7: Reserved The value of this field is only valid when the port * resides in the L0 or L1 state (PLS = 0 or 2). Refer to section 4.23.5.1.1 of xHCI specification for * more information */ #define USB3_PORTPMSC1USB2_L1S(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_L1S_SHIFT)) & USB3_PORTPMSC1USB2_L1S_MASK) #define USB3_PORTPMSC1USB2_RWE_MASK (0x8U) #define USB3_PORTPMSC1USB2_RWE_SHIFT (3U) /*! RWE - Remote Wake Enable (RWE), RW. Default = '0'. System software sets this flag to enable or * disable the device for remote wake from L1. The value of this flag shall temporarily (while in * L1) override the current setting of the Remote Wake feature set by the standard * Set/ClearFeature() commands defined in Universal Serial Bus Specification, revision 2.0, Chapter 9 */ #define USB3_PORTPMSC1USB2_RWE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_RWE_SHIFT)) & USB3_PORTPMSC1USB2_RWE_MASK) #define USB3_PORTPMSC1USB2_BESL_MASK (0xF0U) #define USB3_PORTPMSC1USB2_BESL_SHIFT (4U) /*! BESL - Best Effort Service Latency (BESL), RW. Default = 0. System software sets this field to * indicate to the recipient device how long the xHC will drive resume if it (the xHC) initiates * an exit from L1. The BESL value encoding is defined in Table 13. Note that the BESL field is * used by both software and hardware controlled LPM. Refer to section 4.23.5.1.1 of xHCI * specification for more information on BESL use. Refer to section 5.2.5 of xHCI specification for * information on how DBESL may be used to establish an initial value for BESL */ #define USB3_PORTPMSC1USB2_BESL(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_BESL_SHIFT)) & USB3_PORTPMSC1USB2_BESL_MASK) #define USB3_PORTPMSC1USB2_L1DS_MASK (0xFF00U) #define USB3_PORTPMSC1USB2_L1DS_SHIFT (8U) /*! L1DS - L1 Device Slot, RW. Default = 0. System software sets this field to indicate the ID of * the Device Slot associated with the device directly attached to the Root Hub port. A value of * '0' indicates no device is present. The xHC uses this field to lookup information necessary to * generate the LPM Token packet */ #define USB3_PORTPMSC1USB2_L1DS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_L1DS_SHIFT)) & USB3_PORTPMSC1USB2_L1DS_MASK) #define USB3_PORTPMSC1USB2_HLE_MASK (0x10000U) #define USB3_PORTPMSC1USB2_HLE_SHIFT (16U) /*! HLE - Hardware LPM Enable (HLE), RW. Default = '0'. If this bit is set to '1', then hardware * controlled LPM shall be enabled for this port. Refer to section 4.23.5.1.1.1 of xHCI * specification. If the USB2 Hardware LPM Capability is not supported (HLC = '0') this field shall be RsvdZ */ #define USB3_PORTPMSC1USB2_HLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_HLE_SHIFT)) & USB3_PORTPMSC1USB2_HLE_MASK) #define USB3_PORTPMSC1USB2_PTC_MASK (0xF0000000U) #define USB3_PORTPMSC1USB2_PTC_SHIFT (28U) /*! PTC - Port Test Control, RW. Default = '0'. When this field is '0', the port is NOT operating in * a test mode. A non-zero value indicates that it is operating in test mode and the specific * test mode is indicated by the specific value. A non-zero Port Test Control value is only valid * to a port that is in the Powered-Off state (PLS = Disabled). If the port is not in this state, * the xHC shall respond with the Port Test Control field set to Port Test Control Error. Refer * to section 4.19.6 for the operational model for using these test modes. The encoding of the * Test Mode bits for a USB2 protocol port are: 0: Test mode not enabled 1: Test J_STATE 2: Test * K_STATE 3: Test SE0_NAK 4: Test Packet 5: Test FORCE_ENABLE 6-14: Reserved. 15: Port Test Control * Error. Refer to the sections 7.1.20 and 11.24.2.13 of the USB2 spec for more information on * Test Modes */ #define USB3_PORTPMSC1USB2_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_PTC_SHIFT)) & USB3_PORTPMSC1USB2_PTC_MASK) /*! @} */ /*! @name PORT1HLPMC - USB2 Port Hardware LPM Control register */ /*! @{ */ #define USB3_PORT1HLPMC_HIRDM_MASK (0x3U) #define USB3_PORT1HLPMC_HIRDM_SHIFT (0U) /*! HIRDM - Host Initiated Resume Duration Mode (HIRDM), RWS. Default = 0h. Indicates which HIRD * value should be used. The following are permissible values: 0: Initiate L1 using BESL only on * timeout. (default) 1: Initiate L1 using BESLD on timeout. If rejected by device, initiate L1 * using BESL. 3-2: Reserved */ #define USB3_PORT1HLPMC_HIRDM(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORT1HLPMC_HIRDM_SHIFT)) & USB3_PORT1HLPMC_HIRDM_MASK) #define USB3_PORT1HLPMC_L1_timeout_MASK (0x3FCU) #define USB3_PORT1HLPMC_L1_timeout_SHIFT (2U) /*! L1_timeout - L1 Timeout, RWS. Default = 00h. Timeout value for the L1 inactivity timer (LPM * Timer). This field shall be set to 00h by the assertion of PR to '1'. Refer to section * 4.23.5.1.1.1 of xHci specification for more information on L1 Timeout operation. The following are * permissible values: 00h 128 us. (default) 01h 256 us. 02h 512 us. 03h 768 us. ... FFh 65,280 us */ #define USB3_PORT1HLPMC_L1_timeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORT1HLPMC_L1_timeout_SHIFT)) & USB3_PORT1HLPMC_L1_timeout_MASK) #define USB3_PORT1HLPMC_BESLD_MASK (0x3C00U) #define USB3_PORT1HLPMC_BESLD_SHIFT (10U) /*! BESLD - Best Effort Service Latency Deep (BESLD), RWS. Default = '0'. System software sets this * field to indicate to the recipient device how long the xHC will drive resume on an exit from * U2. Refer to section 4.23.5.1.1.1 of xHCI specification for more information on BESLD use. The * BESLD value encoding is defined in Table 13. Refer to section 5.2.6 of xHCI specification for * information on how DBESLD may be used to establish an initial value for BESLD */ #define USB3_PORT1HLPMC_BESLD(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORT1HLPMC_BESLD_SHIFT)) & USB3_PORT1HLPMC_BESLD_MASK) /*! @} */ /*! @name PORTSC1USB3 - USB3 Port Status and Control */ /*! @{ */ #define USB3_PORTSC1USB3_CCS_MASK (0x1U) #define USB3_PORTSC1USB3_CCS_SHIFT (0U) /*! CCS - Current Connect Status (CCS), ROS. Default = '0'. '1' = A device is connected to the port. * '0' = A device is not connected. This value reflects the current state of the port, and may * not correspond directly to the event that caused the Connect Status Change (CSC) bit to be set * to '1'. Refer to sections 4.19.3 and 4.19.4 of xHCI specification for more details on the * Connect Status Change (CSC) assertion conditions. This flag is '0' if PP is '0' */ #define USB3_PORTSC1USB3_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CCS_SHIFT)) & USB3_PORTSC1USB3_CCS_MASK) #define USB3_PORTSC1USB3_PED_MASK (0x2U) #define USB3_PORTSC1USB3_PED_SHIFT (1U) /*! PED - Port Enabled/Disabled (PED), RW1CS. Default = '0'. '1' = Enabled. '0' = Disabled. Ports * may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag. A * port may be disabled by software writing a '1' to this flag. This flag shall automatically be * cleared to '0' by a disconnect event or other fault condition. Note that the bit status does * not change until the port state actually changes. There may be a delay in disabling or enabling * a port due to other host controller or bus events. When the port is disabled (PED = '0') * downstream propagation of data is blocked on this port, except for reset. When the port is in the * Polling state (after detecting an attach), the port shall automatically transition to the * Enabled state and set PED to '1' upon the completion of successful link training. When the port is * in the Disabled state, software shall write a 5 (RxDetect) to the PLS field to transition the * port to the Disconnected state. Refer to section 4.19.1.2 of xHCI specification. PED shall * automatically be cleared to '0' when PR is set to '1', and set to '1' when PR transitions from * '1' to '0' after a successful reset. Refer to Port Reset (PR) bit for more information on how * the PED bit is managed. Note that when software writes this bit to a '1', it shall also write a * '0' to the PR bit. This flag is '0' if PP is '0' */ #define USB3_PORTSC1USB3_PED(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PED_SHIFT)) & USB3_PORTSC1USB3_PED_MASK) #define USB3_PORTSC1USB3_OCA_MASK (0x8U) #define USB3_PORTSC1USB3_OCA_SHIFT (3U) /*! OCA - Over-current Active (OCA), RO. Default = '0'. '1' = This port currently has an * over-current condition. '0' = This port does not have an over-current condition. This bit shall * automatically transition from a '1' to a '0' when the over-current condition is removed */ #define USB3_PORTSC1USB3_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_OCA_SHIFT)) & USB3_PORTSC1USB3_OCA_MASK) #define USB3_PORTSC1USB3_PR_MASK (0x10U) #define USB3_PORTSC1USB3_PR_SHIFT (4U) /*! PR - Port Reset (PR), RW1S. Default = '0'. '1' = Port Reset signaling is asserted. '0' = Port is * not in Reset. When software writes a '1' to this bit generating a '0' to '1' transition, the * bus reset sequence is initiated; USB3 protocol ports shall execute the Hot Reset sequence as * defined in the USB3 Spec. PR remains set until reset signaling is completed by the root hub. * This flag is '0' if PP is '0' */ #define USB3_PORTSC1USB3_PR(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PR_SHIFT)) & USB3_PORTSC1USB3_PR_MASK) #define USB3_PORTSC1USB3_PLS_MASK (0x1E0U) #define USB3_PORTSC1USB3_PLS_SHIFT (5U) /*! PLS - Port Link State (PLS), RWS. Default = RxDetect ('5'). This field is used to power manage * the port and reflects its current link state. When the port is in the Enabled state, system * software may set the link U state by writing this field. System software may also write this * field to force a Disabled to Disconnected state transition of the port. Write Values: 0: The link * shall transition to a U0 state from any of the U states. 3: The link shall transition to a U3 * state from the U0 state. This action selectively suspends the device connected to this port. * While the Port Link State = U3, the hub does not propagate downstream-directed traffic to this * port, but the hub shall respond to resume signaling from the port. 5: If the port is in the * Disabled state (PLS = Disabled, PP = '1'), then the link shall transition to a RxDetect state * and the port shall transition to the Disconnected state, else ignored. 1-2,4,6-15: Ignored. * State Encoding: 0: Link is in the U0 State, 1: Link is in the U1 State, 2: Link is in the U2 * State, 3: Link is in the U3 State (Device Suspended), 4: Link is in the Disabled State, 5: Link is * in the RxDetect State, 6: Link is in the Inactive State, 7: Link is in the Polling State, 8: * Link is in the Recovery State, 9: Link is in the Hot Reset State, 10 Link is in the Compliance * Mode State, 11: Link is in the Test Mode State, 12-14: Reserved, 15: Link is in the Resume * State. Note: The Port Link State Write Strobe (LWS) shall also be set to '1' to write this field. * This field is undefined if PP = '0'. Note: Transitions between different states are not * reflected until the transition is complete. Refer to section 4.19 of xHCI specification for PLS * transition conditions. Refer to sections 4.15.2 and 4.23.5 for more information on the use of * this field */ #define USB3_PORTSC1USB3_PLS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PLS_SHIFT)) & USB3_PORTSC1USB3_PLS_MASK) #define USB3_PORTSC1USB3_PP_MASK (0x200U) #define USB3_PORTSC1USB3_PP_SHIFT (9U) /*! PP - Port Power (PP), RWS. Default = '1'. This flag reflects a port's logical, power control * state. Because host controllers can implement different methods of port power switching, this * flag may or may not represent whether (VBus) power is actually applied to the port. When PP * equals a '0' the port is nonfunctional and shall not report attaches, detaches, or Port Link State * (PLS) changes. However, the port shall report over-current conditions when PP = '0' if PPC = * '0'. After modifying PP, software shall read PP and confirm that it has reached its target * state before modifying it again, undefined behavior may occur if this procedure is not followed. * '0' = This port is in the Powered-off state. '1' = This port is not in the Powered-off state. * If the Port Power Control (PPC) flag in the HCCPARAMS register is '1', then xHC has port power * control switches and this bit represents the current setting of the switch ('0' = off, * '1'=on). If the Port Power Control (PPC) flag in the HCCPARAMS register is '0', then xHC does not * have port power control switches and each port is hard wired to power, and not affected by this * bit. When an over-current condition is detected on a powered port, the xHC shall transition the * PP bit in each affected port from a '1' to '0' (removing power from the port). Refer to * section 4.19.4 for more information */ #define USB3_PORTSC1USB3_PP(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PP_SHIFT)) & USB3_PORTSC1USB3_PP_MASK) #define USB3_PORTSC1USB3_PortSpeed_MASK (0x3C00U) #define USB3_PORTSC1USB3_PortSpeed_SHIFT (10U) /*! PortSpeed - Port Speed (Port Speed), ROS. Default = '0'. This field identifies the speed of the * connected USB Device. This field is only relevant if a device is connected (CCS = '1') in all * other cases this field shall indicate Undefined Speed. Possible values: 0: Undefined Speed * 1-15: Protocol Speed ID (PSI), refer to section 7.2.1 of xHCI specification for the definition of * PSIV field in the PSI Dword */ #define USB3_PORTSC1USB3_PortSpeed(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PortSpeed_SHIFT)) & USB3_PORTSC1USB3_PortSpeed_MASK) #define USB3_PORTSC1USB3_PIC_MASK (0xC000U) #define USB3_PORTSC1USB3_PIC_SHIFT (14U) /*! PIC - Port Indicator Control (PIC), RWS. Default = '0'. Writing to these bits has no effect if * the Port Indicators (PIND) bit in the HCCPARAMS register is a '0'. If PIND bit is a '1', then * the bit encodings are: 0: Port indicators are off, 1: Amber, 2: Green, 3: Undefined. This field * is '0' if PP is '0' */ #define USB3_PORTSC1USB3_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PIC_SHIFT)) & USB3_PORTSC1USB3_PIC_MASK) #define USB3_PORTSC1USB3_LWS_MASK (0x10000U) #define USB3_PORTSC1USB3_LWS_SHIFT (16U) /*! LWS - Port Link State Write Strobe (LWS), RW. Default = '0'. When this bit is set to '1' on a * write reference to this register, this flag enables writes to the PLS field. When '0', write * data in PLS field is ignored. Reads to this bit return '0' */ #define USB3_PORTSC1USB3_LWS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_LWS_SHIFT)) & USB3_PORTSC1USB3_LWS_MASK) #define USB3_PORTSC1USB3_CSC_MASK (0x20000U) #define USB3_PORTSC1USB3_CSC_SHIFT (17U) /*! CSC - Connect Status Change (CSC), RW1CS. Default = '0'. '1' = Change in CCS. '0' = No change. * This flag indicates a change has occurred in the ports Current Connect Status (CCS) or Cold * Attach Status (CAS) bits. Note that this flag shall not be set if the CCS transition was due to * software setting PP to '0', or the CAS transition was due to software setting WPR to '1'. The * xHC sets this bit to '1' for all changes to the port device connect status, even if system * software has not cleared an existing Connect Status Change. For example, the insertion status * changes twice before system software has cleared the changed condition, root hub hardware will be * setting an already-set bit (i.e., the bit will remain 1). Software shall clear this bit by * writing a '1' to it. Refer to section 4.19.2 of xHCI specification for more information on change * bit usage */ #define USB3_PORTSC1USB3_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CSC_SHIFT)) & USB3_PORTSC1USB3_CSC_MASK) #define USB3_PORTSC1USB3_PEC_MASK (0x40000U) #define USB3_PORTSC1USB3_PEC_SHIFT (18U) /*! PEC - Port Enabled/Disabled Change (PEC), RW1CS. Default = '0'. '1' = change in PED. '0' = No * change. Note that this flag shall not be set if the PED transition was due to software setting * PP to '0'. Software shall clear this bit by writing a '1' to it. Refer to section 4.19.2 of * xHCI specification for more information on change bit usage. This bit shall never be set to '1' */ #define USB3_PORTSC1USB3_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PEC_SHIFT)) & USB3_PORTSC1USB3_PEC_MASK) #define USB3_PORTSC1USB3_WRC_MASK (0x80000U) #define USB3_PORTSC1USB3_WRC_SHIFT (19U) /*! WRC - Warm Port Reset Change (WRC), RW1CS. Default = '0'. This bit is set when Warm Reset * processing on this port completes. '0' = No change. '1' = Warm Reset complete. Note that this flag * shall not be set to '1' if the Warm Reset processing was forced to terminate due to software * clearing PP or PED to '0'. Software shall clear this bit by writing a '1' to it. Refer to * section 4.19.5.1 of xHCI specification. Refer to section 4.19.2 of xHCI specification for more * information on change bit usage */ #define USB3_PORTSC1USB3_WRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WRC_SHIFT)) & USB3_PORTSC1USB3_WRC_MASK) #define USB3_PORTSC1USB3_OCC_MASK (0x100000U) #define USB3_PORTSC1USB3_OCC_SHIFT (20U) /*! OCC - Over-current Change (OCC), RW1CS. Default = '0'. This bit shall be set to a '1' when there * is a '0' to '1' or '1' to '0' transition of Over-current Active (OCA). Software shall clear * this bit by writing a '1' to it. Refer to section 4.19.2 of xHCI specification for more * information on change bit usage */ #define USB3_PORTSC1USB3_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_OCC_SHIFT)) & USB3_PORTSC1USB3_OCC_MASK) #define USB3_PORTSC1USB3_PRC_MASK (0x200000U) #define USB3_PORTSC1USB3_PRC_SHIFT (21U) /*! PRC - Port Reset Change (PRC), RW1CS. Default = '0'. This flag is set to '1' due to a '1' to '0' * transition of Port Reset (PR), e.g. when any reset processing (Warm or Hot) on this port is * complete. Note that this flag shall not be set to '1' if the reset processing was forced to * terminate due to software clearing PP or PED to '0'. '0' = No change. '1' = Reset complete. * Software shall clear this bit by writing a '1' to it. Refer to section 4.19.5 of xHCI * specification. Refer to section 4.19.2 of xHCI specification for more information on change bit usage */ #define USB3_PORTSC1USB3_PRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PRC_SHIFT)) & USB3_PORTSC1USB3_PRC_MASK) #define USB3_PORTSC1USB3_PLC_MASK (0x400000U) #define USB3_PORTSC1USB3_PLC_SHIFT (22U) /*! PLC - Port Link State Change (PLC), RW1CS. Default = '0'. This flag is set to '1' due to the * following PLS transitions: U3 -> Resume (Wakeup signaling from a device), Resume -> Recovery -> * U0 (Device Resume complete (USB3 protocol ports only)), Resume -> U0 (Device Resume complete * (USB2 protocol ports only)), U3 -> Recovery -> U0 (Software Resume complete (USB3 protocol ports * only)), U3 -> U0 (Software Resume complete (USB2 protocol ports only)), U2 -> U0 (L1 Resume * complete (USB2 protocol ports only)), U0 -> U0 (L1 Entry Reject (USB2 protocol ports only)), * Any state -> Inactive (Error (USB3 protocol ports only)). Note that this flag shall not be set * if the PLS transition was due to software setting PP to 0. Refer to section 4.23.5 of xHCI * specification for more information. '0' = No change. '1' = Link Status Changed. Software shall * clear this bit by writing a '1' to it. Refer to PLC Condition: references in section 4.19.1 for * the specific port state transitions that set this flag. Refer to section 4.19.2 of xHCI * specification for more information on change bit usage */ #define USB3_PORTSC1USB3_PLC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PLC_SHIFT)) & USB3_PORTSC1USB3_PLC_MASK) #define USB3_PORTSC1USB3_CEC_MASK (0x800000U) #define USB3_PORTSC1USB3_CEC_SHIFT (23U) /*! CEC - Port Config Error Change (CEC), RW1CS. Default = '0'. This flag indicates that the port * failed to configure its link partner. '0' = No change. '1' = Port Config Error detected. * Software shall clear this bit by writing a '1' to it. Refer to section 4.19.2 of xHCI specification * for more information on change bit usage */ #define USB3_PORTSC1USB3_CEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CEC_SHIFT)) & USB3_PORTSC1USB3_CEC_MASK) #define USB3_PORTSC1USB3_CAS_MASK (0x1000000U) #define USB3_PORTSC1USB3_CAS_SHIFT (24U) /*! CAS - Cold Attach Status (CAS), RO. Default = '0'. '1' = Far-end Receiver Terminations were * detected in the Disconnected state and the Root Hub Port State Machine was unable to advance to * the Enabled state. Refer to sections 4.19.8 of xHCI specification for more details on the Cold * Attach Status (CAS) assertion conditions. Software shall clear this bit by writing a '1' to WPR * or the xHC shall clear this bit if CCS transitions to '1'. This flag is 0 if PP is 0 or for * USB2 protocol ports. Note: Additionally to the xHCI spec the CAS may be set in D1/D2 state. If * customer's PLL lock time ensures finishing LFPS in tPollingLFPSTimeout (360ms) the SW driver * may ignore the CAS and wait for PORTSC.CCS. It prevents additional reset on USB port. However, * handling CAS in normal way should not have any negative impact on the device */ #define USB3_PORTSC1USB3_CAS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CAS_SHIFT)) & USB3_PORTSC1USB3_CAS_MASK) #define USB3_PORTSC1USB3_WCE_MASK (0x2000000U) #define USB3_PORTSC1USB3_WCE_SHIFT (25U) /*! WCE - Wake on Connect Enable (WCE), RWS. Default = '0'. Writing this bit to a '1' enables the * port to be sensitive to device connects as system wake-up events. Refer to section 4.15 of xHCI * specification for operational model */ #define USB3_PORTSC1USB3_WCE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WCE_SHIFT)) & USB3_PORTSC1USB3_WCE_MASK) #define USB3_PORTSC1USB3_WDE_MASK (0x4000000U) #define USB3_PORTSC1USB3_WDE_SHIFT (26U) /*! WDE - Wake on Disconnect Enable (WDE), RWS. Default = '0'. Writing this bit to a '1' enables the * port to be sensitive to device disconnects as system wake-up events. Refer to section 4.15 of * xHCI specification for operational model */ #define USB3_PORTSC1USB3_WDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WDE_SHIFT)) & USB3_PORTSC1USB3_WDE_MASK) #define USB3_PORTSC1USB3_WOE_MASK (0x8000000U) #define USB3_PORTSC1USB3_WOE_SHIFT (27U) /*! WOE - Wake on Over-current Enable (WOE), RWS. Default = '0'. Writing this bit to a '1' enables * the port to be sensitive to over-current conditions as system wake-up events. Refer to section * 4.15 of xHCI specification for operational model */ #define USB3_PORTSC1USB3_WOE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WOE_SHIFT)) & USB3_PORTSC1USB3_WOE_MASK) #define USB3_PORTSC1USB3_DR_MASK (0x40000000U) #define USB3_PORTSC1USB3_DR_SHIFT (30U) /*! DR - Device Removable (DR), RO. This flag indicates if this port has a removable device * attached. '0' = Device is removable; '1' = Device is non-removable */ #define USB3_PORTSC1USB3_DR(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_DR_SHIFT)) & USB3_PORTSC1USB3_DR_MASK) #define USB3_PORTSC1USB3_WPR_MASK (0x80000000U) #define USB3_PORTSC1USB3_WPR_SHIFT (31U) /*! WPR - Warm Port Reset (WPR), RW1S. Default = '0'. When software writes a '1' to this bit, the * Warm Reset sequence as defined in the USB3 Specification is initiated and the PR flag is set to * '1'. Once initiated, the PR, PRC, and WRC flags shall reflect the progress of the Warm Reset * sequence. This flag shall always return 0 when read. Refer to section 4.19.5.1 of xHCI * specification */ #define USB3_PORTSC1USB3_WPR(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WPR_SHIFT)) & USB3_PORTSC1USB3_WPR_MASK) /*! @} */ /*! @name PORTPMSC1USB3 - USB3 Port Power Management Status and Control */ /*! @{ */ #define USB3_PORTPMSC1USB3_U1_timeout_MASK (0xFFU) #define USB3_PORTPMSC1USB3_U1_timeout_SHIFT (0U) /*! U1_timeout - U1 Timeout, RWS. Default = 0. Timeout value for U1 inactivity timer. If equal to * FFh, the port is disabled from initiating U1 entry. This field shall be set to '0' by the * assertion of PR to '1'. Refer to section 4.19.4.1 of xHCI specification for more information on U1 * Timeout operation. The following are permissible values: 00h Zero (default) 01h 1 us. 02h 2 us. * ... 7Fh 127 us. 80h - FEh Reserved FFh Infinite */ #define USB3_PORTPMSC1USB3_U1_timeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB3_U1_timeout_SHIFT)) & USB3_PORTPMSC1USB3_U1_timeout_MASK) #define USB3_PORTPMSC1USB3_U2_timeout_MASK (0xFF00U) #define USB3_PORTPMSC1USB3_U2_timeout_SHIFT (8U) /*! U2_timeout - U2 Timeout, RWS. Default = 0. Timeout value for U2 inactivity timer. If equal to * FFh, the port is disabled from initiating U2 entry. This field shall be set to '0' by the * assertion of PR to '1'. Refer to section 4.19.4.1 of xHCI specification for more information on U2 * Timeout operation. The following are permissible values: 00h Zero (default) 01h 256 us 02h 512 * us ... FEh 65,.024 ms FFh Infinite A U2 Inactivity Timeout LMP shall be sent by the xHC to the * device connected on this port when this field is written. Refer to Sections 8.4.3 and * 10.4.2.10 of the USB3 specification for more details */ #define USB3_PORTPMSC1USB3_U2_timeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB3_U2_timeout_SHIFT)) & USB3_PORTPMSC1USB3_U2_timeout_MASK) #define USB3_PORTPMSC1USB3_FLA_MASK (0x10000U) #define USB3_PORTPMSC1USB3_FLA_SHIFT (16U) /*! FLA - Force Link PM Accept (FLA), RW. Default = '0'. When this bit is set to '1', the port shall * generate a Set Link Function LMP with the Force_LinkPM_Accept bit asserted ('1'). When this * bit is cleared to '0', the port shall generate a Set Link Function LMP with the * Force_LinkPM_Accept bit de-asserted ('0'). This flag shall be set to '0' by the assertion of PR to '1' or * when CCS = transitions from '0' to '1'. Writes to this flag have no effect if PP = '0'. The Set * Link Function LMP is sent by the xHC to the device connected on this port when this bit * transitions from '0' to '1' or '1' to '0'. Refer to Sections 8.4.2 and 10.14.2.2 of the USB3 * specification for more details. Improper use of the SS Force_LinkPM_Accept functionality can impact * the performance of the link significantly. This bit shall only be used for compliance and * testing purposes. Software shall ensure that there are no pending packets at the link level before * setting this bit. This flag is '0' if PP is '0' */ #define USB3_PORTPMSC1USB3_FLA(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB3_FLA_SHIFT)) & USB3_PORTPMSC1USB3_FLA_MASK) /*! @} */ /*! @name PORTLI1 - USB3 Port Link Info */ /*! @{ */ #define USB3_PORTLI1_LEC_MASK (0xFFFFU) #define USB3_PORTLI1_LEC_SHIFT (0U) /*! LEC - Link Error Count, RO. Default = '0'. This field returns the number of link errors detected * by the port. This value shall be reset to '0' by the assertion of a Chip Hardware Reset, * HCRST, when PR transitions from 1 to 0, or when CCS = transitions from '0' to '1' */ #define USB3_PORTLI1_LEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_PORTLI1_LEC_SHIFT)) & USB3_PORTLI1_LEC_MASK) /*! @} */ /*! @name MFINDEX - MicroFrame Index */ /*! @{ */ #define USB3_MFINDEX_MFIndex_MASK (0x3FFFU) #define USB3_MFINDEX_MFIndex_SHIFT (0U) /*! MFIndex - Microframe Index, RO. The value in this register increments at the end of each * microframe (e.g. 125us.). Bits [13:3] may be used to determine the current 1ms Frame Index. Note: * Setting frindex_wr_en to '1' (bit 31 of XECP_CMDM_CTRL_REG3) enables software writes to this field */ #define USB3_MFINDEX_MFIndex(x) (((uint32_t)(((uint32_t)(x)) << USB3_MFINDEX_MFIndex_SHIFT)) & USB3_MFINDEX_MFIndex_MASK) /*! @} */ /*! @name IMAN0 - Interrupter Management */ /*! @{ */ #define USB3_IMAN0_IP_MASK (0x1U) #define USB3_IMAN0_IP_SHIFT (0U) /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the * Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates * that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI * specification for the conditions that modify the state of this flag */ #define USB3_IMAN0_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN0_IP_SHIFT)) & USB3_IMAN0_IP_MASK) #define USB3_IMAN0_IE_MASK (0x2U) #define USB3_IMAN0_IE_SHIFT (1U) /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is * capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter * shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is * '0', then the Interrupter is prohibited from generating interrupts */ #define USB3_IMAN0_IE(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN0_IE_SHIFT)) & USB3_IMAN0_IE_MASK) /*! @} */ /*! @name IMOD0 - Interrupter Moderation */ /*! @{ */ #define USB3_IMOD0_IMODI_MASK (0xFFFFU) #define USB3_IMOD0_IMODI_SHIFT (0U) /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum * inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables * interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and * the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization * and reset. It may be loaded with an alternative value by software when the Interrupter is * initialized */ #define USB3_IMOD0_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD0_IMODI_SHIFT)) & USB3_IMOD0_IMODI_MASK) #define USB3_IMOD0_IMODC_MASK (0xFFFF0000U) #define USB3_IMOD0_IMODC_SHIFT (16U) /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with * the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated * interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE * and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time * to alter the interrupt rate */ #define USB3_IMOD0_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD0_IMODC_SHIFT)) & USB3_IMOD0_IMODC_MASK) /*! @} */ /*! @name ERSTSZ0 - Event Ring Segment Table Size */ /*! @{ */ #define USB3_ERSTSZ0_ERSTS_MASK (0xFFFFU) #define USB3_ERSTSZ0_ERSTS_SHIFT (0U) /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of * valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event * Ring Segment Table Base Address register. The maximum value supported by an xHC implementation * for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary * Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at * this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For * the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior * of the Event Ring. The Primary Event Ring cannot be disabled */ #define USB3_ERSTSZ0_ERSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ0_ERSTS_SHIFT)) & USB3_ERSTSZ0_ERSTS_MASK) /*! @} */ /*! @name ERSTBA0_LO - Event Ring Segment Table Base Address (LOW) */ /*! @{ */ #define USB3_ERSTBA0_LO_ERSTBAddr_LO_MASK (0xFFFFFFC0U) #define USB3_ERSTBA0_LO_ERSTBAddr_LO_SHIFT (6U) /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address * is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement * to the Start state. This field shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA0_LO_ERSTBAddr_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA0_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA0_LO_ERSTBAddr_LO_MASK) /*! @} */ /*! @name ERSTBA00_HI - Event Ring Segment Table Base Address (HIGH) */ /*! @{ */ #define USB3_ERSTBA00_HI_ERSTBAddr_HI_MASK (0xFFFFFFFFU) #define USB3_ERSTBA00_HI_ERSTBAddr_HI_SHIFT (0U) /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the * address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement * to the Start state. Refer to Figure 20 in xHCI specification for more information. This field * shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA00_HI_ERSTBAddr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA00_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA00_HI_ERSTBAddr_HI_MASK) /*! @} */ /*! @name ERDP0_LO - Event Ring Dequeue Pointer (LOW) */ /*! @{ */ #define USB3_ERDP0_LO_DESI_MASK (0x7U) #define USB3_ERDP0_LO_DESI_SHIFT (0U) /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to * accelerate checking the Event Ring full condition. This field is written with the low order 3 bits * of the offset of the ERST entry which defines the Event Ring segment that the Event Ring * Dequeue Pointer resides in */ #define USB3_ERDP0_LO_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_LO_DESI_SHIFT)) & USB3_ERDP0_LO_DESI_MASK) #define USB3_ERDP0_LO_EHB_MASK (0x8U) #define USB3_ERDP0_LO_EHB_SHIFT (3U) /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP * bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. * Refer to section 4.17.2 of xHCI specification for more information */ #define USB3_ERDP0_LO_EHB(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_LO_EHB_SHIFT)) & USB3_ERDP0_LO_EHB_MASK) #define USB3_ERDP0_LO_ERDPtr_MASK (0xFFFFFFF0U) #define USB3_ERDP0_LO_ERDPtr_SHIFT (4U) /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits * of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP0_LO_ERDPtr(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_LO_ERDPtr_SHIFT)) & USB3_ERDP0_LO_ERDPtr_MASK) /*! @} */ /*! @name ERDP0_HI - Event Ring Dequeue Pointer (HIGH) */ /*! @{ */ #define USB3_ERDP0_HI_ERDPtr_HI_MASK (0xFFFFFFFFU) #define USB3_ERDP0_HI_ERDPtr_HI_SHIFT (0U) /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order * bits of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP0_HI_ERDPtr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP0_HI_ERDPtr_HI_MASK) /*! @} */ /*! @name IMAN1 - Interrupter Management */ /*! @{ */ #define USB3_IMAN1_IP_MASK (0x1U) #define USB3_IMAN1_IP_SHIFT (0U) /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the * Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates * that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI * specification for the conditions that modify the state of this flag */ #define USB3_IMAN1_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN1_IP_SHIFT)) & USB3_IMAN1_IP_MASK) #define USB3_IMAN1_IE_MASK (0x2U) #define USB3_IMAN1_IE_SHIFT (1U) /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is * capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter * shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is * '0', then the Interrupter is prohibited from generating interrupts */ #define USB3_IMAN1_IE(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN1_IE_SHIFT)) & USB3_IMAN1_IE_MASK) /*! @} */ /*! @name IMOD1 - Interrupter Moderation */ /*! @{ */ #define USB3_IMOD1_IMODI_MASK (0xFFFFU) #define USB3_IMOD1_IMODI_SHIFT (0U) /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum * inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables * interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and * the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization * and reset. It may be loaded with an alternative value by software when the Interrupter is * initialized */ #define USB3_IMOD1_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD1_IMODI_SHIFT)) & USB3_IMOD1_IMODI_MASK) #define USB3_IMOD1_IMODC_MASK (0xFFFF0000U) #define USB3_IMOD1_IMODC_SHIFT (16U) /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with * the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated * interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE * and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time * to alter the interrupt rate */ #define USB3_IMOD1_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD1_IMODC_SHIFT)) & USB3_IMOD1_IMODC_MASK) /*! @} */ /*! @name ERSTSZ1 - Event Ring Segment Table Size */ /*! @{ */ #define USB3_ERSTSZ1_ERSTS_MASK (0xFFFFU) #define USB3_ERSTSZ1_ERSTS_SHIFT (0U) /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of * valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event * Ring Segment Table Base Address register. The maximum value supported by an xHC implementation * for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary * Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at * this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For * the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior * of the Event Ring. The Primary Event Ring cannot be disabled */ #define USB3_ERSTSZ1_ERSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ1_ERSTS_SHIFT)) & USB3_ERSTSZ1_ERSTS_MASK) /*! @} */ /*! @name ERSTBA1_LO - Event Ring Segment Table Base Address (LOW) */ /*! @{ */ #define USB3_ERSTBA1_LO_ERSTBAddr_LO_MASK (0xFFFFFFC0U) #define USB3_ERSTBA1_LO_ERSTBAddr_LO_SHIFT (6U) /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address * is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement * to the Start state. This field shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA1_LO_ERSTBAddr_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA1_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA1_LO_ERSTBAddr_LO_MASK) /*! @} */ /*! @name ERSTBA01_HI - Event Ring Segment Table Base Address (HIGH) */ /*! @{ */ #define USB3_ERSTBA01_HI_ERSTBAddr_HI_MASK (0xFFFFFFFFU) #define USB3_ERSTBA01_HI_ERSTBAddr_HI_SHIFT (0U) /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the * address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement * to the Start state. Refer to Figure 20 in xHCI specification for more information. This field * shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA01_HI_ERSTBAddr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA01_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA01_HI_ERSTBAddr_HI_MASK) /*! @} */ /*! @name ERDP1_LO - Event Ring Dequeue Pointer (LOW) */ /*! @{ */ #define USB3_ERDP1_LO_DESI_MASK (0x7U) #define USB3_ERDP1_LO_DESI_SHIFT (0U) /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to * accelerate checking the Event Ring full condition. This field is written with the low order 3 bits * of the offset of the ERST entry which defines the Event Ring segment that the Event Ring * Dequeue Pointer resides in */ #define USB3_ERDP1_LO_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_LO_DESI_SHIFT)) & USB3_ERDP1_LO_DESI_MASK) #define USB3_ERDP1_LO_EHB_MASK (0x8U) #define USB3_ERDP1_LO_EHB_SHIFT (3U) /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP * bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. * Refer to section 4.17.2 of xHCI specification for more information */ #define USB3_ERDP1_LO_EHB(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_LO_EHB_SHIFT)) & USB3_ERDP1_LO_EHB_MASK) #define USB3_ERDP1_LO_ERDPtr_MASK (0xFFFFFFF0U) #define USB3_ERDP1_LO_ERDPtr_SHIFT (4U) /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits * of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP1_LO_ERDPtr(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_LO_ERDPtr_SHIFT)) & USB3_ERDP1_LO_ERDPtr_MASK) /*! @} */ /*! @name ERDP1_HI - Event Ring Dequeue Pointer (HIGH) */ /*! @{ */ #define USB3_ERDP1_HI_ERDPtr_HI_MASK (0xFFFFFFFFU) #define USB3_ERDP1_HI_ERDPtr_HI_SHIFT (0U) /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order * bits of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP1_HI_ERDPtr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP1_HI_ERDPtr_HI_MASK) /*! @} */ /*! @name IMAN2 - Interrupter Management */ /*! @{ */ #define USB3_IMAN2_IP_MASK (0x1U) #define USB3_IMAN2_IP_SHIFT (0U) /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the * Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates * that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI * specification for the conditions that modify the state of this flag */ #define USB3_IMAN2_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN2_IP_SHIFT)) & USB3_IMAN2_IP_MASK) #define USB3_IMAN2_IE_MASK (0x2U) #define USB3_IMAN2_IE_SHIFT (1U) /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is * capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter * shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is * '0', then the Interrupter is prohibited from generating interrupts */ #define USB3_IMAN2_IE(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN2_IE_SHIFT)) & USB3_IMAN2_IE_MASK) /*! @} */ /*! @name IMOD2 - Interrupter Moderation */ /*! @{ */ #define USB3_IMOD2_IMODI_MASK (0xFFFFU) #define USB3_IMOD2_IMODI_SHIFT (0U) /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum * inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables * interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and * the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization * and reset. It may be loaded with an alternative value by software when the Interrupter is * initialized */ #define USB3_IMOD2_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD2_IMODI_SHIFT)) & USB3_IMOD2_IMODI_MASK) #define USB3_IMOD2_IMODC_MASK (0xFFFF0000U) #define USB3_IMOD2_IMODC_SHIFT (16U) /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with * the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated * interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE * and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time * to alter the interrupt rate */ #define USB3_IMOD2_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD2_IMODC_SHIFT)) & USB3_IMOD2_IMODC_MASK) /*! @} */ /*! @name ERSTSZ2 - Event Ring Segment Table Size */ /*! @{ */ #define USB3_ERSTSZ2_ERSTS_MASK (0xFFFFU) #define USB3_ERSTSZ2_ERSTS_SHIFT (0U) /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of * valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event * Ring Segment Table Base Address register. The maximum value supported by an xHC implementation * for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary * Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at * this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For * the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior * of the Event Ring. The Primary Event Ring cannot be disabled */ #define USB3_ERSTSZ2_ERSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ2_ERSTS_SHIFT)) & USB3_ERSTSZ2_ERSTS_MASK) /*! @} */ /*! @name ERSTBA2_LO - Event Ring Segment Table Base Address (LOW) */ /*! @{ */ #define USB3_ERSTBA2_LO_ERSTBAddr_LO_MASK (0xFFFFFFC0U) #define USB3_ERSTBA2_LO_ERSTBAddr_LO_SHIFT (6U) /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address * is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement * to the Start state. This field shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA2_LO_ERSTBAddr_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA2_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA2_LO_ERSTBAddr_LO_MASK) /*! @} */ /*! @name ERSTBA02_HI - Event Ring Segment Table Base Address (HIGH) */ /*! @{ */ #define USB3_ERSTBA02_HI_ERSTBAddr_HI_MASK (0xFFFFFFFFU) #define USB3_ERSTBA02_HI_ERSTBAddr_HI_SHIFT (0U) /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the * address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement * to the Start state. Refer to Figure 20 in xHCI specification for more information. This field * shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA02_HI_ERSTBAddr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA02_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA02_HI_ERSTBAddr_HI_MASK) /*! @} */ /*! @name ERDP2_LO - Event Ring Dequeue Pointer (LOW) */ /*! @{ */ #define USB3_ERDP2_LO_DESI_MASK (0x7U) #define USB3_ERDP2_LO_DESI_SHIFT (0U) /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to * accelerate checking the Event Ring full condition. This field is written with the low order 3 bits * of the offset of the ERST entry which defines the Event Ring segment that the Event Ring * Dequeue Pointer resides in */ #define USB3_ERDP2_LO_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_LO_DESI_SHIFT)) & USB3_ERDP2_LO_DESI_MASK) #define USB3_ERDP2_LO_EHB_MASK (0x8U) #define USB3_ERDP2_LO_EHB_SHIFT (3U) /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP * bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. * Refer to section 4.17.2 of xHCI specification for more information */ #define USB3_ERDP2_LO_EHB(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_LO_EHB_SHIFT)) & USB3_ERDP2_LO_EHB_MASK) #define USB3_ERDP2_LO_ERDPtr_MASK (0xFFFFFFF0U) #define USB3_ERDP2_LO_ERDPtr_SHIFT (4U) /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits * of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP2_LO_ERDPtr(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_LO_ERDPtr_SHIFT)) & USB3_ERDP2_LO_ERDPtr_MASK) /*! @} */ /*! @name ERDP2_HI - Event Ring Dequeue Pointer (HIGH) */ /*! @{ */ #define USB3_ERDP2_HI_ERDPtr_HI_MASK (0xFFFFFFFFU) #define USB3_ERDP2_HI_ERDPtr_HI_SHIFT (0U) /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order * bits of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP2_HI_ERDPtr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP2_HI_ERDPtr_HI_MASK) /*! @} */ /*! @name IMAN3 - Interrupter Management */ /*! @{ */ #define USB3_IMAN3_IP_MASK (0x1U) #define USB3_IMAN3_IP_SHIFT (0U) /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the * Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates * that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI * specification for the conditions that modify the state of this flag */ #define USB3_IMAN3_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN3_IP_SHIFT)) & USB3_IMAN3_IP_MASK) #define USB3_IMAN3_IE_MASK (0x2U) #define USB3_IMAN3_IE_SHIFT (1U) /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is * capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter * shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is * '0', then the Interrupter is prohibited from generating interrupts */ #define USB3_IMAN3_IE(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN3_IE_SHIFT)) & USB3_IMAN3_IE_MASK) /*! @} */ /*! @name IMOD3 - Interrupter Moderation */ /*! @{ */ #define USB3_IMOD3_IMODI_MASK (0xFFFFU) #define USB3_IMOD3_IMODI_SHIFT (0U) /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum * inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables * interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and * the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization * and reset. It may be loaded with an alternative value by software when the Interrupter is * initialized */ #define USB3_IMOD3_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD3_IMODI_SHIFT)) & USB3_IMOD3_IMODI_MASK) #define USB3_IMOD3_IMODC_MASK (0xFFFF0000U) #define USB3_IMOD3_IMODC_SHIFT (16U) /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with * the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated * interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE * and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time * to alter the interrupt rate */ #define USB3_IMOD3_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD3_IMODC_SHIFT)) & USB3_IMOD3_IMODC_MASK) /*! @} */ /*! @name ERSTSZ3 - Event Ring Segment Table Size */ /*! @{ */ #define USB3_ERSTSZ3_ERSTS_MASK (0xFFFFU) #define USB3_ERSTSZ3_ERSTS_SHIFT (0U) /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of * valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event * Ring Segment Table Base Address register. The maximum value supported by an xHC implementation * for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary * Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at * this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For * the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior * of the Event Ring. The Primary Event Ring cannot be disabled */ #define USB3_ERSTSZ3_ERSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ3_ERSTS_SHIFT)) & USB3_ERSTSZ3_ERSTS_MASK) /*! @} */ /*! @name ERSTBA3_LO - Event Ring Segment Table Base Address (LOW) */ /*! @{ */ #define USB3_ERSTBA3_LO_ERSTBAddr_LO_MASK (0xFFFFFFC0U) #define USB3_ERSTBA3_LO_ERSTBAddr_LO_SHIFT (6U) /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address * is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement * to the Start state. This field shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA3_LO_ERSTBAddr_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA3_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA3_LO_ERSTBAddr_LO_MASK) /*! @} */ /*! @name ERSTBA03_HI - Event Ring Segment Table Base Address (HIGH) */ /*! @{ */ #define USB3_ERSTBA03_HI_ERSTBAddr_HI_MASK (0xFFFFFFFFU) #define USB3_ERSTBA03_HI_ERSTBAddr_HI_SHIFT (0U) /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the * address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement * to the Start state. Refer to Figure 20 in xHCI specification for more information. This field * shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA03_HI_ERSTBAddr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA03_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA03_HI_ERSTBAddr_HI_MASK) /*! @} */ /*! @name ERDP3_LO - Event Ring Dequeue Pointer (LOW) */ /*! @{ */ #define USB3_ERDP3_LO_DESI_MASK (0x7U) #define USB3_ERDP3_LO_DESI_SHIFT (0U) /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to * accelerate checking the Event Ring full condition. This field is written with the low order 3 bits * of the offset of the ERST entry which defines the Event Ring segment that the Event Ring * Dequeue Pointer resides in */ #define USB3_ERDP3_LO_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_LO_DESI_SHIFT)) & USB3_ERDP3_LO_DESI_MASK) #define USB3_ERDP3_LO_EHB_MASK (0x8U) #define USB3_ERDP3_LO_EHB_SHIFT (3U) /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP * bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. * Refer to section 4.17.2 of xHCI specification for more information */ #define USB3_ERDP3_LO_EHB(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_LO_EHB_SHIFT)) & USB3_ERDP3_LO_EHB_MASK) #define USB3_ERDP3_LO_ERDPtr_MASK (0xFFFFFFF0U) #define USB3_ERDP3_LO_ERDPtr_SHIFT (4U) /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits * of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP3_LO_ERDPtr(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_LO_ERDPtr_SHIFT)) & USB3_ERDP3_LO_ERDPtr_MASK) /*! @} */ /*! @name ERDP3_HI - Event Ring Dequeue Pointer (HIGH) */ /*! @{ */ #define USB3_ERDP3_HI_ERDPtr_HI_MASK (0xFFFFFFFFU) #define USB3_ERDP3_HI_ERDPtr_HI_SHIFT (0U) /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order * bits of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP3_HI_ERDPtr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP3_HI_ERDPtr_HI_MASK) /*! @} */ /*! @name IMAN4 - Interrupter Management */ /*! @{ */ #define USB3_IMAN4_IP_MASK (0x1U) #define USB3_IMAN4_IP_SHIFT (0U) /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the * Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates * that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI * specification for the conditions that modify the state of this flag */ #define USB3_IMAN4_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN4_IP_SHIFT)) & USB3_IMAN4_IP_MASK) #define USB3_IMAN4_IE_MASK (0x2U) #define USB3_IMAN4_IE_SHIFT (1U) /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is * capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter * shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is * '0', then the Interrupter is prohibited from generating interrupts */ #define USB3_IMAN4_IE(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN4_IE_SHIFT)) & USB3_IMAN4_IE_MASK) /*! @} */ /*! @name IMOD4 - Interrupter Moderation */ /*! @{ */ #define USB3_IMOD4_IMODI_MASK (0xFFFFU) #define USB3_IMOD4_IMODI_SHIFT (0U) /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum * inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables * interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and * the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization * and reset. It may be loaded with an alternative value by software when the Interrupter is * initialized */ #define USB3_IMOD4_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD4_IMODI_SHIFT)) & USB3_IMOD4_IMODI_MASK) #define USB3_IMOD4_IMODC_MASK (0xFFFF0000U) #define USB3_IMOD4_IMODC_SHIFT (16U) /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with * the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated * interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE * and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time * to alter the interrupt rate */ #define USB3_IMOD4_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD4_IMODC_SHIFT)) & USB3_IMOD4_IMODC_MASK) /*! @} */ /*! @name ERSTSZ4 - Event Ring Segment Table Size */ /*! @{ */ #define USB3_ERSTSZ4_ERSTS_MASK (0xFFFFU) #define USB3_ERSTSZ4_ERSTS_SHIFT (0U) /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of * valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event * Ring Segment Table Base Address register. The maximum value supported by an xHC implementation * for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary * Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at * this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For * the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior * of the Event Ring. The Primary Event Ring cannot be disabled */ #define USB3_ERSTSZ4_ERSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ4_ERSTS_SHIFT)) & USB3_ERSTSZ4_ERSTS_MASK) /*! @} */ /*! @name ERSTBA4_LO - Event Ring Segment Table Base Address (LOW) */ /*! @{ */ #define USB3_ERSTBA4_LO_ERSTBAddr_LO_MASK (0xFFFFFFC0U) #define USB3_ERSTBA4_LO_ERSTBAddr_LO_SHIFT (6U) /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address * is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement * to the Start state. This field shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA4_LO_ERSTBAddr_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA4_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA4_LO_ERSTBAddr_LO_MASK) /*! @} */ /*! @name ERSTBA04_HI - Event Ring Segment Table Base Address (HIGH) */ /*! @{ */ #define USB3_ERSTBA04_HI_ERSTBAddr_HI_MASK (0xFFFFFFFFU) #define USB3_ERSTBA04_HI_ERSTBAddr_HI_SHIFT (0U) /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the * address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement * to the Start state. Refer to Figure 20 in xHCI specification for more information. This field * shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA04_HI_ERSTBAddr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA04_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA04_HI_ERSTBAddr_HI_MASK) /*! @} */ /*! @name ERDP4_LO - Event Ring Dequeue Pointer (LOW) */ /*! @{ */ #define USB3_ERDP4_LO_DESI_MASK (0x7U) #define USB3_ERDP4_LO_DESI_SHIFT (0U) /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to * accelerate checking the Event Ring full condition. This field is written with the low order 3 bits * of the offset of the ERST entry which defines the Event Ring segment that the Event Ring * Dequeue Pointer resides in */ #define USB3_ERDP4_LO_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_LO_DESI_SHIFT)) & USB3_ERDP4_LO_DESI_MASK) #define USB3_ERDP4_LO_EHB_MASK (0x8U) #define USB3_ERDP4_LO_EHB_SHIFT (3U) /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP * bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. * Refer to section 4.17.2 of xHCI specification for more information */ #define USB3_ERDP4_LO_EHB(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_LO_EHB_SHIFT)) & USB3_ERDP4_LO_EHB_MASK) #define USB3_ERDP4_LO_ERDPtr_MASK (0xFFFFFFF0U) #define USB3_ERDP4_LO_ERDPtr_SHIFT (4U) /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits * of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP4_LO_ERDPtr(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_LO_ERDPtr_SHIFT)) & USB3_ERDP4_LO_ERDPtr_MASK) /*! @} */ /*! @name ERDP4_HI - Event Ring Dequeue Pointer (HIGH) */ /*! @{ */ #define USB3_ERDP4_HI_ERDPtr_HI_MASK (0xFFFFFFFFU) #define USB3_ERDP4_HI_ERDPtr_HI_SHIFT (0U) /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order * bits of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP4_HI_ERDPtr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP4_HI_ERDPtr_HI_MASK) /*! @} */ /*! @name IMAN5 - Interrupter Management */ /*! @{ */ #define USB3_IMAN5_IP_MASK (0x1U) #define USB3_IMAN5_IP_SHIFT (0U) /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the * Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates * that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI * specification for the conditions that modify the state of this flag */ #define USB3_IMAN5_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN5_IP_SHIFT)) & USB3_IMAN5_IP_MASK) #define USB3_IMAN5_IE_MASK (0x2U) #define USB3_IMAN5_IE_SHIFT (1U) /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is * capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter * shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is * '0', then the Interrupter is prohibited from generating interrupts */ #define USB3_IMAN5_IE(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN5_IE_SHIFT)) & USB3_IMAN5_IE_MASK) /*! @} */ /*! @name IMOD5 - Interrupter Moderation */ /*! @{ */ #define USB3_IMOD5_IMODI_MASK (0xFFFFU) #define USB3_IMOD5_IMODI_SHIFT (0U) /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum * inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables * interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and * the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization * and reset. It may be loaded with an alternative value by software when the Interrupter is * initialized */ #define USB3_IMOD5_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD5_IMODI_SHIFT)) & USB3_IMOD5_IMODI_MASK) #define USB3_IMOD5_IMODC_MASK (0xFFFF0000U) #define USB3_IMOD5_IMODC_SHIFT (16U) /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with * the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated * interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE * and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time * to alter the interrupt rate */ #define USB3_IMOD5_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD5_IMODC_SHIFT)) & USB3_IMOD5_IMODC_MASK) /*! @} */ /*! @name ERSTSZ5 - Event Ring Segment Table Size */ /*! @{ */ #define USB3_ERSTSZ5_ERSTS_MASK (0xFFFFU) #define USB3_ERSTSZ5_ERSTS_SHIFT (0U) /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of * valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event * Ring Segment Table Base Address register. The maximum value supported by an xHC implementation * for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary * Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at * this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For * the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior * of the Event Ring. The Primary Event Ring cannot be disabled */ #define USB3_ERSTSZ5_ERSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ5_ERSTS_SHIFT)) & USB3_ERSTSZ5_ERSTS_MASK) /*! @} */ /*! @name ERSTBA5_LO - Event Ring Segment Table Base Address (LOW) */ /*! @{ */ #define USB3_ERSTBA5_LO_ERSTBAddr_LO_MASK (0xFFFFFFC0U) #define USB3_ERSTBA5_LO_ERSTBAddr_LO_SHIFT (6U) /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address * is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement * to the Start state. This field shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA5_LO_ERSTBAddr_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA5_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA5_LO_ERSTBAddr_LO_MASK) /*! @} */ /*! @name ERSTBA05_HI - Event Ring Segment Table Base Address (HIGH) */ /*! @{ */ #define USB3_ERSTBA05_HI_ERSTBAddr_HI_MASK (0xFFFFFFFFU) #define USB3_ERSTBA05_HI_ERSTBAddr_HI_SHIFT (0U) /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the * address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement * to the Start state. Refer to Figure 20 in xHCI specification for more information. This field * shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA05_HI_ERSTBAddr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA05_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA05_HI_ERSTBAddr_HI_MASK) /*! @} */ /*! @name ERDP5_LO - Event Ring Dequeue Pointer (LOW) */ /*! @{ */ #define USB3_ERDP5_LO_DESI_MASK (0x7U) #define USB3_ERDP5_LO_DESI_SHIFT (0U) /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to * accelerate checking the Event Ring full condition. This field is written with the low order 3 bits * of the offset of the ERST entry which defines the Event Ring segment that the Event Ring * Dequeue Pointer resides in */ #define USB3_ERDP5_LO_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_LO_DESI_SHIFT)) & USB3_ERDP5_LO_DESI_MASK) #define USB3_ERDP5_LO_EHB_MASK (0x8U) #define USB3_ERDP5_LO_EHB_SHIFT (3U) /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP * bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. * Refer to section 4.17.2 of xHCI specification for more information */ #define USB3_ERDP5_LO_EHB(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_LO_EHB_SHIFT)) & USB3_ERDP5_LO_EHB_MASK) #define USB3_ERDP5_LO_ERDPtr_MASK (0xFFFFFFF0U) #define USB3_ERDP5_LO_ERDPtr_SHIFT (4U) /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits * of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP5_LO_ERDPtr(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_LO_ERDPtr_SHIFT)) & USB3_ERDP5_LO_ERDPtr_MASK) /*! @} */ /*! @name ERDP5_HI - Event Ring Dequeue Pointer (HIGH) */ /*! @{ */ #define USB3_ERDP5_HI_ERDPtr_HI_MASK (0xFFFFFFFFU) #define USB3_ERDP5_HI_ERDPtr_HI_SHIFT (0U) /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order * bits of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP5_HI_ERDPtr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP5_HI_ERDPtr_HI_MASK) /*! @} */ /*! @name IMAN6 - Interrupter Management */ /*! @{ */ #define USB3_IMAN6_IP_MASK (0x1U) #define USB3_IMAN6_IP_SHIFT (0U) /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the * Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates * that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI * specification for the conditions that modify the state of this flag */ #define USB3_IMAN6_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN6_IP_SHIFT)) & USB3_IMAN6_IP_MASK) #define USB3_IMAN6_IE_MASK (0x2U) #define USB3_IMAN6_IE_SHIFT (1U) /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is * capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter * shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is * '0', then the Interrupter is prohibited from generating interrupts */ #define USB3_IMAN6_IE(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN6_IE_SHIFT)) & USB3_IMAN6_IE_MASK) /*! @} */ /*! @name IMOD6 - Interrupter Moderation */ /*! @{ */ #define USB3_IMOD6_IMODI_MASK (0xFFFFU) #define USB3_IMOD6_IMODI_SHIFT (0U) /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum * inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables * interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and * the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization * and reset. It may be loaded with an alternative value by software when the Interrupter is * initialized */ #define USB3_IMOD6_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD6_IMODI_SHIFT)) & USB3_IMOD6_IMODI_MASK) #define USB3_IMOD6_IMODC_MASK (0xFFFF0000U) #define USB3_IMOD6_IMODC_SHIFT (16U) /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with * the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated * interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE * and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time * to alter the interrupt rate */ #define USB3_IMOD6_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD6_IMODC_SHIFT)) & USB3_IMOD6_IMODC_MASK) /*! @} */ /*! @name ERSTSZ6 - Event Ring Segment Table Size */ /*! @{ */ #define USB3_ERSTSZ6_ERSTS_MASK (0xFFFFU) #define USB3_ERSTSZ6_ERSTS_SHIFT (0U) /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of * valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event * Ring Segment Table Base Address register. The maximum value supported by an xHC implementation * for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary * Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at * this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For * the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior * of the Event Ring. The Primary Event Ring cannot be disabled */ #define USB3_ERSTSZ6_ERSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ6_ERSTS_SHIFT)) & USB3_ERSTSZ6_ERSTS_MASK) /*! @} */ /*! @name ERSTBA6_LO - Event Ring Segment Table Base Address (LOW) */ /*! @{ */ #define USB3_ERSTBA6_LO_ERSTBAddr_LO_MASK (0xFFFFFFC0U) #define USB3_ERSTBA6_LO_ERSTBAddr_LO_SHIFT (6U) /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address * is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement * to the Start state. This field shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA6_LO_ERSTBAddr_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA6_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA6_LO_ERSTBAddr_LO_MASK) /*! @} */ /*! @name ERSTBA06_HI - Event Ring Segment Table Base Address (HIGH) */ /*! @{ */ #define USB3_ERSTBA06_HI_ERSTBAddr_HI_MASK (0xFFFFFFFFU) #define USB3_ERSTBA06_HI_ERSTBAddr_HI_SHIFT (0U) /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the * address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement * to the Start state. Refer to Figure 20 in xHCI specification for more information. This field * shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA06_HI_ERSTBAddr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA06_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA06_HI_ERSTBAddr_HI_MASK) /*! @} */ /*! @name ERDP6_LO - Event Ring Dequeue Pointer (LOW) */ /*! @{ */ #define USB3_ERDP6_LO_DESI_MASK (0x7U) #define USB3_ERDP6_LO_DESI_SHIFT (0U) /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to * accelerate checking the Event Ring full condition. This field is written with the low order 3 bits * of the offset of the ERST entry which defines the Event Ring segment that the Event Ring * Dequeue Pointer resides in */ #define USB3_ERDP6_LO_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_LO_DESI_SHIFT)) & USB3_ERDP6_LO_DESI_MASK) #define USB3_ERDP6_LO_EHB_MASK (0x8U) #define USB3_ERDP6_LO_EHB_SHIFT (3U) /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP * bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. * Refer to section 4.17.2 of xHCI specification for more information */ #define USB3_ERDP6_LO_EHB(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_LO_EHB_SHIFT)) & USB3_ERDP6_LO_EHB_MASK) #define USB3_ERDP6_LO_ERDPtr_MASK (0xFFFFFFF0U) #define USB3_ERDP6_LO_ERDPtr_SHIFT (4U) /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits * of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP6_LO_ERDPtr(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_LO_ERDPtr_SHIFT)) & USB3_ERDP6_LO_ERDPtr_MASK) /*! @} */ /*! @name ERDP6_HI - Event Ring Dequeue Pointer (HIGH) */ /*! @{ */ #define USB3_ERDP6_HI_ERDPtr_HI_MASK (0xFFFFFFFFU) #define USB3_ERDP6_HI_ERDPtr_HI_SHIFT (0U) /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order * bits of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP6_HI_ERDPtr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP6_HI_ERDPtr_HI_MASK) /*! @} */ /*! @name IMAN7 - Interrupter Management */ /*! @{ */ #define USB3_IMAN7_IP_MASK (0x1U) #define USB3_IMAN7_IP_SHIFT (0U) /*! IP - Interrupt Pending (IP), RW1C. Default = '0'. This flag represents the current state of the * Interrupter. If IP = '1', an interrupt is pending for this Interrupter. A '0' value indicates * that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of the xHCI * specification for the conditions that modify the state of this flag */ #define USB3_IMAN7_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN7_IP_SHIFT)) & USB3_IMAN7_IP_MASK) #define USB3_IMAN7_IE_MASK (0x2U) #define USB3_IMAN7_IE_SHIFT (1U) /*! IE - Interrupt Enable (IE), RW. Default = '0'. This flag specifies whether the Interrupter is * capable of generating an interrupt. When this bit and the IP bit are set ('1'), the Interrupter * shall generate an interrupt when the Interrupter Moderation Counter reaches 0. If this bit is * '0', then the Interrupter is prohibited from generating interrupts */ #define USB3_IMAN7_IE(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMAN7_IE_SHIFT)) & USB3_IMAN7_IE_MASK) /*! @} */ /*! @name IMOD7 - Interrupter Moderation */ /*! @{ */ #define USB3_IMOD7_IMODI_MASK (0xFFFFU) #define USB3_IMOD7_IMODI_SHIFT (0U) /*! IMODI - Interrupt Moderation Interval (IMODI), RW. Default = 'hFA0' (~1ms). Minimum * inter-interrupt interval. The interval is specified in 250ns increments. A value of zero disables * interrupt throttling logic and interrupts shall be generated immediately if IP = '0', EHB = '0', and * the Event Ring is not empty. The IMODI field shall default to 'hFA0' (1 ms) upon initialization * and reset. It may be loaded with an alternative value by software when the Interrupter is * initialized */ #define USB3_IMOD7_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD7_IMODI_SHIFT)) & USB3_IMOD7_IMODI_MASK) #define USB3_IMOD7_IMODC_MASK (0xFFFF0000U) #define USB3_IMOD7_IMODC_SHIFT (16U) /*! IMODC - Interrupt Moderation Counter (IMODC), RW. Default = undefined. Down counter. Loaded with * the IMODI value whenever IP is cleared to '0', counts down to 0, and stops. The associated * interrupt shall be signaled whenever this counter is zero, the Event Ring is not empty, the IE * and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time * to alter the interrupt rate */ #define USB3_IMOD7_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB3_IMOD7_IMODC_SHIFT)) & USB3_IMOD7_IMODC_MASK) /*! @} */ /*! @name ERSTSZ7 - Event Ring Segment Table Size */ /*! @{ */ #define USB3_ERSTSZ7_ERSTS_MASK (0xFFFFU) #define USB3_ERSTSZ7_ERSTS_SHIFT (0U) /*! ERSTS - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of * valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event * Ring Segment Table Base Address register. The maximum value supported by an xHC implementation * for this register is defined by the ERST Max field in the HCSPARAMS2 register. For Secondary * Interrupters: Writing a value of 0 to this field disables the Event Ring. Any events targeted at * this Event Ring when it is disabled shall result in undefined behavior of the Event Ring. For * the Primary Interrupter: Writing a value of 0 to this field shall result in undefined behavior * of the Event Ring. The Primary Event Ring cannot be disabled */ #define USB3_ERSTSZ7_ERSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ7_ERSTS_SHIFT)) & USB3_ERSTSZ7_ERSTS_MASK) /*! @} */ /*! @name ERSTBA7_LO - Event Ring Segment Table Base Address (LOW) */ /*! @{ */ #define USB3_ERSTBA7_LO_ERSTBAddr_LO_MASK (0xFFFFFFC0U) #define USB3_ERSTBA7_LO_ERSTBAddr_LO_SHIFT (6U) /*! ERSTBAddr_LO - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the low order bit [25:0] of the start address of the Event Ring Segment Table (the address * is 58 bits wide) . Writing this register sets the Event Ring State Machine: EREP Advancement * to the Start state. This field shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA7_LO_ERSTBAddr_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA7_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA7_LO_ERSTBAddr_LO_MASK) /*! @} */ /*! @name ERSTBA07_HI - Event Ring Segment Table Base Address (HIGH) */ /*! @{ */ #define USB3_ERSTBA07_HI_ERSTBAddr_HI_MASK (0xFFFFFFFFU) #define USB3_ERSTBA07_HI_ERSTBAddr_HI_SHIFT (0U) /*! ERSTBAddr_HI - Event Ring Segment Table Base Address Register, RW. Default = 0. This field * defines the high order bits [57:26] of the start address of the Event Ring Segment Table (the * address is 58 bits wide) . Writing this register sets the Event Ring State Machine:EREP Advancement * to the Start state. Refer to Figure 20 in xHCI specification for more information. This field * shall not be modified if HCHalted (HCH) = '0' */ #define USB3_ERSTBA07_HI_ERSTBAddr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA07_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA07_HI_ERSTBAddr_HI_MASK) /*! @} */ /*! @name ERDP7_LO - Event Ring Dequeue Pointer (LOW) */ /*! @{ */ #define USB3_ERDP7_LO_DESI_MASK (0x7U) #define USB3_ERDP7_LO_DESI_SHIFT (0U) /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to * accelerate checking the Event Ring full condition. This field is written with the low order 3 bits * of the offset of the ERST entry which defines the Event Ring segment that the Event Ring * Dequeue Pointer resides in */ #define USB3_ERDP7_LO_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_LO_DESI_SHIFT)) & USB3_ERDP7_LO_DESI_MASK) #define USB3_ERDP7_LO_EHB_MASK (0x8U) #define USB3_ERDP7_LO_EHB_SHIFT (3U) /*! EHB - Event Handler Busy (EHB), RW1C. Default = '0'. This flag shall be set to '1' when the IP * bit is set to '1' and cleared to '0' by software when the Dequeue Pointer register is written. * Refer to section 4.17.2 of xHCI specification for more information */ #define USB3_ERDP7_LO_EHB(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_LO_EHB_SHIFT)) & USB3_ERDP7_LO_EHB_MASK) #define USB3_ERDP7_LO_ERDPtr_MASK (0xFFFFFFF0U) #define USB3_ERDP7_LO_ERDPtr_SHIFT (4U) /*! ERDPtr - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 28 low order bits * of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP7_LO_ERDPtr(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_LO_ERDPtr_SHIFT)) & USB3_ERDP7_LO_ERDPtr_MASK) /*! @} */ /*! @name ERDP7_HI - Event Ring Dequeue Pointer (HIGH) */ /*! @{ */ #define USB3_ERDP7_HI_ERDPtr_HI_MASK (0xFFFFFFFFU) #define USB3_ERDP7_HI_ERDPtr_HI_SHIFT (0U) /*! ERDPtr_HI - Event Ring Dequeue Pointer, RW. Default = 0. This field defines the 32 high order * bits of the 64-bit address of the current Event Ring Dequeue Pointer */ #define USB3_ERDP7_HI_ERDPtr_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP7_HI_ERDPtr_HI_MASK) /*! @} */ /*! @name DB0 - Host Controller Doorbell */ /*! @{ */ #define USB3_DB0_DB_target_MASK (0xFFU) #define USB3_DB0_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Note that Doorbell Register 0 is dedicated to Command Ring and decodes this field differently * than the other Doorbell Registers. Possible values ( For this register, there is only one valid * value for the DB Target field, 0 (Host Controller Command). The remaining values (1-255) are * reserved.): 0: Command Doorbell 1:247 Reserved 248:255 Vendor Defined This field returns zero * when read and should be treated as undefined by software. When the Command Doorbell is * written, the DB Stream ID field shall be cleared to zero */ #define USB3_DB0_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB0_DB_target_SHIFT)) & USB3_DB0_DB_target_MASK) #define USB3_DB0_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB0_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB0_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB0_DB_stream_ID_SHIFT)) & USB3_DB0_DB_stream_ID_MASK) /*! @} */ /*! @name DB1 - Doorbell Array */ /*! @{ */ #define USB3_DB1_DB_target_MASK (0xFFU) #define USB3_DB1_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB1_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB1_DB_target_SHIFT)) & USB3_DB1_DB_target_MASK) #define USB3_DB1_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB1_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB1_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB1_DB_stream_ID_SHIFT)) & USB3_DB1_DB_stream_ID_MASK) /*! @} */ /*! @name DB2 - Doorbell Array */ /*! @{ */ #define USB3_DB2_DB_target_MASK (0xFFU) #define USB3_DB2_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB2_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB2_DB_target_SHIFT)) & USB3_DB2_DB_target_MASK) #define USB3_DB2_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB2_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB2_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB2_DB_stream_ID_SHIFT)) & USB3_DB2_DB_stream_ID_MASK) /*! @} */ /*! @name DB3 - Doorbell Array */ /*! @{ */ #define USB3_DB3_DB_target_MASK (0xFFU) #define USB3_DB3_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB3_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB3_DB_target_SHIFT)) & USB3_DB3_DB_target_MASK) #define USB3_DB3_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB3_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB3_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB3_DB_stream_ID_SHIFT)) & USB3_DB3_DB_stream_ID_MASK) /*! @} */ /*! @name DB4 - Doorbell Array */ /*! @{ */ #define USB3_DB4_DB_target_MASK (0xFFU) #define USB3_DB4_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB4_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB4_DB_target_SHIFT)) & USB3_DB4_DB_target_MASK) #define USB3_DB4_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB4_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB4_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB4_DB_stream_ID_SHIFT)) & USB3_DB4_DB_stream_ID_MASK) /*! @} */ /*! @name DB5 - Doorbell Array */ /*! @{ */ #define USB3_DB5_DB_target_MASK (0xFFU) #define USB3_DB5_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB5_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB5_DB_target_SHIFT)) & USB3_DB5_DB_target_MASK) #define USB3_DB5_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB5_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB5_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB5_DB_stream_ID_SHIFT)) & USB3_DB5_DB_stream_ID_MASK) /*! @} */ /*! @name DB6 - Doorbell Array */ /*! @{ */ #define USB3_DB6_DB_target_MASK (0xFFU) #define USB3_DB6_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB6_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB6_DB_target_SHIFT)) & USB3_DB6_DB_target_MASK) #define USB3_DB6_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB6_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB6_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB6_DB_stream_ID_SHIFT)) & USB3_DB6_DB_stream_ID_MASK) /*! @} */ /*! @name DB7 - Doorbell Array */ /*! @{ */ #define USB3_DB7_DB_target_MASK (0xFFU) #define USB3_DB7_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB7_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB7_DB_target_SHIFT)) & USB3_DB7_DB_target_MASK) #define USB3_DB7_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB7_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB7_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB7_DB_stream_ID_SHIFT)) & USB3_DB7_DB_stream_ID_MASK) /*! @} */ /*! @name DB8 - Doorbell Array */ /*! @{ */ #define USB3_DB8_DB_target_MASK (0xFFU) #define USB3_DB8_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB8_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB8_DB_target_SHIFT)) & USB3_DB8_DB_target_MASK) #define USB3_DB8_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB8_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB8_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB8_DB_stream_ID_SHIFT)) & USB3_DB8_DB_stream_ID_MASK) /*! @} */ /*! @name DB9 - Doorbell Array */ /*! @{ */ #define USB3_DB9_DB_target_MASK (0xFFU) #define USB3_DB9_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB9_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB9_DB_target_SHIFT)) & USB3_DB9_DB_target_MASK) #define USB3_DB9_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB9_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB9_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB9_DB_stream_ID_SHIFT)) & USB3_DB9_DB_stream_ID_MASK) /*! @} */ /*! @name DB10 - Doorbell Array */ /*! @{ */ #define USB3_DB10_DB_target_MASK (0xFFU) #define USB3_DB10_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB10_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB10_DB_target_SHIFT)) & USB3_DB10_DB_target_MASK) #define USB3_DB10_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB10_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB10_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB10_DB_stream_ID_SHIFT)) & USB3_DB10_DB_stream_ID_MASK) /*! @} */ /*! @name DB11 - Doorbell Array */ /*! @{ */ #define USB3_DB11_DB_target_MASK (0xFFU) #define USB3_DB11_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB11_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB11_DB_target_SHIFT)) & USB3_DB11_DB_target_MASK) #define USB3_DB11_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB11_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB11_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB11_DB_stream_ID_SHIFT)) & USB3_DB11_DB_stream_ID_MASK) /*! @} */ /*! @name DB12 - Doorbell Array */ /*! @{ */ #define USB3_DB12_DB_target_MASK (0xFFU) #define USB3_DB12_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB12_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB12_DB_target_SHIFT)) & USB3_DB12_DB_target_MASK) #define USB3_DB12_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB12_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB12_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB12_DB_stream_ID_SHIFT)) & USB3_DB12_DB_stream_ID_MASK) /*! @} */ /*! @name DB13 - Doorbell Array */ /*! @{ */ #define USB3_DB13_DB_target_MASK (0xFFU) #define USB3_DB13_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB13_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB13_DB_target_SHIFT)) & USB3_DB13_DB_target_MASK) #define USB3_DB13_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB13_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB13_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB13_DB_stream_ID_SHIFT)) & USB3_DB13_DB_stream_ID_MASK) /*! @} */ /*! @name DB14 - Doorbell Array */ /*! @{ */ #define USB3_DB14_DB_target_MASK (0xFFU) #define USB3_DB14_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB14_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB14_DB_target_SHIFT)) & USB3_DB14_DB_target_MASK) #define USB3_DB14_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB14_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB14_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB14_DB_stream_ID_SHIFT)) & USB3_DB14_DB_stream_ID_MASK) /*! @} */ /*! @name DB15 - Doorbell Array */ /*! @{ */ #define USB3_DB15_DB_target_MASK (0xFFU) #define USB3_DB15_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB15_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB15_DB_target_SHIFT)) & USB3_DB15_DB_target_MASK) #define USB3_DB15_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB15_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB15_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB15_DB_stream_ID_SHIFT)) & USB3_DB15_DB_stream_ID_MASK) /*! @} */ /*! @name DB16 - Doorbell Array */ /*! @{ */ #define USB3_DB16_DB_target_MASK (0xFFU) #define USB3_DB16_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB16_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB16_DB_target_SHIFT)) & USB3_DB16_DB_target_MASK) #define USB3_DB16_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB16_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB16_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB16_DB_stream_ID_SHIFT)) & USB3_DB16_DB_stream_ID_MASK) /*! @} */ /*! @name DB17 - Doorbell Array */ /*! @{ */ #define USB3_DB17_DB_target_MASK (0xFFU) #define USB3_DB17_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB17_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB17_DB_target_SHIFT)) & USB3_DB17_DB_target_MASK) #define USB3_DB17_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB17_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB17_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB17_DB_stream_ID_SHIFT)) & USB3_DB17_DB_stream_ID_MASK) /*! @} */ /*! @name DB18 - Doorbell Array */ /*! @{ */ #define USB3_DB18_DB_target_MASK (0xFFU) #define USB3_DB18_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB18_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB18_DB_target_SHIFT)) & USB3_DB18_DB_target_MASK) #define USB3_DB18_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB18_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB18_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB18_DB_stream_ID_SHIFT)) & USB3_DB18_DB_stream_ID_MASK) /*! @} */ /*! @name DB19 - Doorbell Array */ /*! @{ */ #define USB3_DB19_DB_target_MASK (0xFFU) #define USB3_DB19_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB19_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB19_DB_target_SHIFT)) & USB3_DB19_DB_target_MASK) #define USB3_DB19_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB19_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB19_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB19_DB_stream_ID_SHIFT)) & USB3_DB19_DB_stream_ID_MASK) /*! @} */ /*! @name DB20 - Doorbell Array */ /*! @{ */ #define USB3_DB20_DB_target_MASK (0xFFU) #define USB3_DB20_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB20_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB20_DB_target_SHIFT)) & USB3_DB20_DB_target_MASK) #define USB3_DB20_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB20_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB20_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB20_DB_stream_ID_SHIFT)) & USB3_DB20_DB_stream_ID_MASK) /*! @} */ /*! @name DB21 - Doorbell Array */ /*! @{ */ #define USB3_DB21_DB_target_MASK (0xFFU) #define USB3_DB21_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB21_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB21_DB_target_SHIFT)) & USB3_DB21_DB_target_MASK) #define USB3_DB21_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB21_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB21_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB21_DB_stream_ID_SHIFT)) & USB3_DB21_DB_stream_ID_MASK) /*! @} */ /*! @name DB22 - Doorbell Array */ /*! @{ */ #define USB3_DB22_DB_target_MASK (0xFFU) #define USB3_DB22_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB22_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB22_DB_target_SHIFT)) & USB3_DB22_DB_target_MASK) #define USB3_DB22_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB22_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB22_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB22_DB_stream_ID_SHIFT)) & USB3_DB22_DB_stream_ID_MASK) /*! @} */ /*! @name DB23 - Doorbell Array */ /*! @{ */ #define USB3_DB23_DB_target_MASK (0xFFU) #define USB3_DB23_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB23_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB23_DB_target_SHIFT)) & USB3_DB23_DB_target_MASK) #define USB3_DB23_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB23_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB23_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB23_DB_stream_ID_SHIFT)) & USB3_DB23_DB_stream_ID_MASK) /*! @} */ /*! @name DB24 - Doorbell Array */ /*! @{ */ #define USB3_DB24_DB_target_MASK (0xFFU) #define USB3_DB24_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB24_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB24_DB_target_SHIFT)) & USB3_DB24_DB_target_MASK) #define USB3_DB24_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB24_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB24_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB24_DB_stream_ID_SHIFT)) & USB3_DB24_DB_stream_ID_MASK) /*! @} */ /*! @name DB25 - Doorbell Array */ /*! @{ */ #define USB3_DB25_DB_target_MASK (0xFFU) #define USB3_DB25_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB25_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB25_DB_target_SHIFT)) & USB3_DB25_DB_target_MASK) #define USB3_DB25_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB25_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB25_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB25_DB_stream_ID_SHIFT)) & USB3_DB25_DB_stream_ID_MASK) /*! @} */ /*! @name DB26 - Doorbell Array */ /*! @{ */ #define USB3_DB26_DB_target_MASK (0xFFU) #define USB3_DB26_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB26_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB26_DB_target_SHIFT)) & USB3_DB26_DB_target_MASK) #define USB3_DB26_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB26_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB26_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB26_DB_stream_ID_SHIFT)) & USB3_DB26_DB_stream_ID_MASK) /*! @} */ /*! @name DB27 - Doorbell Array */ /*! @{ */ #define USB3_DB27_DB_target_MASK (0xFFU) #define USB3_DB27_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB27_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB27_DB_target_SHIFT)) & USB3_DB27_DB_target_MASK) #define USB3_DB27_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB27_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB27_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB27_DB_stream_ID_SHIFT)) & USB3_DB27_DB_stream_ID_MASK) /*! @} */ /*! @name DB28 - Doorbell Array */ /*! @{ */ #define USB3_DB28_DB_target_MASK (0xFFU) #define USB3_DB28_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB28_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB28_DB_target_SHIFT)) & USB3_DB28_DB_target_MASK) #define USB3_DB28_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB28_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB28_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB28_DB_stream_ID_SHIFT)) & USB3_DB28_DB_stream_ID_MASK) /*! @} */ /*! @name DB29 - Doorbell Array */ /*! @{ */ #define USB3_DB29_DB_target_MASK (0xFFU) #define USB3_DB29_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB29_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB29_DB_target_SHIFT)) & USB3_DB29_DB_target_MASK) #define USB3_DB29_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB29_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB29_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB29_DB_stream_ID_SHIFT)) & USB3_DB29_DB_stream_ID_MASK) /*! @} */ /*! @name DB30 - Doorbell Array */ /*! @{ */ #define USB3_DB30_DB_target_MASK (0xFFU) #define USB3_DB30_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB30_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB30_DB_target_SHIFT)) & USB3_DB30_DB_target_MASK) #define USB3_DB30_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB30_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB30_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB30_DB_stream_ID_SHIFT)) & USB3_DB30_DB_stream_ID_MASK) /*! @} */ /*! @name DB31 - Doorbell Array */ /*! @{ */ #define USB3_DB31_DB_target_MASK (0xFFU) #define USB3_DB31_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB31_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB31_DB_target_SHIFT)) & USB3_DB31_DB_target_MASK) #define USB3_DB31_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB31_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB31_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB31_DB_stream_ID_SHIFT)) & USB3_DB31_DB_stream_ID_MASK) /*! @} */ /*! @name DB32 - Doorbell Array */ /*! @{ */ #define USB3_DB32_DB_target_MASK (0xFFU) #define USB3_DB32_DB_target_SHIFT (0U) /*! DB_target - DB Target, RW. Doorbell Target. This field defines the target of the doorbell * reference. The table below defines the xHC notification that is generated by ringing the doorbell. * Possible values: 0: Reserved 1: Control EP 0 Enqueue Pointer Update 2: EP 1 OUT Enqueue Pointer * Update 3: EP 1 IN Enqueue Pointer Update 4: EP 2 OUT Enqueue Pointer Update 5: EP 2 IN * Enqueue Pointer Update ... 30: EP 15 OUT Enqueue Pointer Update 31: EP 15 IN Enqueue Pointer Update * 32:247: Reserved 248:255: Vendor Defined This field returns zero when read and should be * treated as undefined by software. When the Command Doorbell is written, the DB Stream ID field * shall be cleared to zero */ #define USB3_DB32_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB32_DB_target_SHIFT)) & USB3_DB32_DB_target_MASK) #define USB3_DB32_DB_stream_ID_MASK (0xFFFF0000U) #define USB3_DB32_DB_stream_ID_SHIFT (16U) /*! DB_stream_ID - DB Stream ID, RW. Doorbell Stream ID. If the endpoint of a Device Context * Doorbell defines Streams, then this field shall be used to identify which Stream of the endpoint the * doorbell reference is targeting. System software is responsible for ensuring that the value * written to this field is valid. If the endpoint defines Streams (MaxPStreams > 0), then 0, 65535 * (No Stream) and 65534 (Prime) are reserved Stream ID values and shall not be written to this * field. If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is * written to this field, the doorbell reference shall be ignored. This field only applies to Device * Context Doorbells and shall be cleared to zero for Host Controller Command Doorbells. This field * returns zero when read */ #define USB3_DB32_DB_stream_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DB32_DB_stream_ID_SHIFT)) & USB3_DB32_DB_stream_ID_MASK) /*! @} */ /*! @name XECP_PORT_CAP_REG - USB3 Extended capability */ /*! @{ */ #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_MASK (0xFFU) #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_SHIFT (0U) /*! XHCI_PORT_CAP_ID - XHCI_PORT_CAP_ID. Port capability ID */ #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_SHIFT)) & USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_MASK) #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_MASK (0xFF00U) #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_SHIFT (8U) /*! XHCI_PORT_CAPABILITY_DW - XHCI_PORT_CAPABILITY_DW. Next Item Pointer. This field provides an * offset pointing to the location of next item in the functions capability list */ #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_SHIFT)) & USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_MASK) #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_MASK (0xFF0000U) #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_SHIFT (16U) /*! XHCI_PORT_CAP_REV - XHCI_PORT_CAP_REV : revision of the Port Capability structure */ #define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_SHIFT)) & USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_MASK) #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_MASK (0x1000000U) #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_SHIFT (24U) /*! LPM_2_STB_SWITCH_CAPABLE - xHC is capable of switching to stb_clk */ #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_SHIFT)) & USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_MASK) #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_MASK (0x2000000U) #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_SHIFT (25U) /*! LPM_2_STB_SWITCH_EN - Enable switching to stb_clk */ #define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_SHIFT)) & USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_MASK) /*! @} */ /*! @name XECP_PORT_1_REG - USB3 Extended capability */ /*! @{ */ #define USB3_XECP_PORT_1_REG_TRAINING_FAIL_MASK (0x1U) #define USB3_XECP_PORT_1_REG_TRAINING_FAIL_SHIFT (0U) /*! TRAINING_FAIL - When reading: Link Polling training error flag status, When writing '1': clear * the Link Polling training error flag, When writing '0': no effect */ #define USB3_XECP_PORT_1_REG_TRAINING_FAIL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_TRAINING_FAIL_SHIFT)) & USB3_XECP_PORT_1_REG_TRAINING_FAIL_MASK) #define USB3_XECP_PORT_1_REG_TERM_DEB_MAX_MASK (0x6U) #define USB3_XECP_PORT_1_REG_TERM_DEB_MAX_SHIFT (1U) /*! TERM_DEB_MAX - Number of the consecutive lack of Far-end Rx Termination detected that causes * transition from SS.Inactive to RxDetect state */ #define USB3_XECP_PORT_1_REG_TERM_DEB_MAX(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_TERM_DEB_MAX_SHIFT)) & USB3_XECP_PORT_1_REG_TERM_DEB_MAX_MASK) #define USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_MASK (0x8U) #define USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_SHIFT (3U) /*! U3_SPUR_LFPS_FIX - Enable filtering out spurious LFPS when entering U3 state */ #define USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_SHIFT)) & USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_MASK) #define USB3_XECP_PORT_1_REG_SKP_OS_FIX_MASK (0x10U) #define USB3_XECP_PORT_1_REG_SKP_OS_FIX_SHIFT (4U) /*! SKP_OS_FIX - Change counting number of symbols for SKP OS insertion (only for the 1st SKP OS) */ #define USB3_XECP_PORT_1_REG_SKP_OS_FIX(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_SKP_OS_FIX_SHIFT)) & USB3_XECP_PORT_1_REG_SKP_OS_FIX_MASK) #define USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_MASK (0x20U) #define USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_SHIFT (5U) /*! TTIME_FOR_RESET_EN - Enable tTimeForResetError timer */ #define USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_SHIFT)) & USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_MASK) #define USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_MASK (0x7F00U) #define USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_SHIFT (8U) /*! U1_LFPS_MINGEN_TIME - Minimum U1 LFPS generation time. Written only if U1_LFPS_TIME_WR_STROBE is 1 */ #define USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_SHIFT)) & USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_MASK) #define USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_MASK (0x8000U) #define USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_SHIFT (15U) /*! U1_LFPS_TIME_WR_STROBE - Minimum U1 LFPS generation time write stobe. Returns '0' when read */ #define USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_SHIFT)) & USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_MASK) /*! @} */ /*! @name XECP_CDNS_DEBUG_BUS_CAP - xHCI Debug Bus Capability */ /*! @{ */ #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_MASK (0xFFU) #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_SHIFT (0U) /*! XHCI_DEBUG_BUS_CAP_ID - Capability ID, RO. This field identifies the extended capability. For xHCI Debug Bus its' value is 196 */ #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_MASK) #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_MASK (0xFF00U) #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_SHIFT (8U) /*! XHCI_DEBUG_BUS_DW - Next Capability Pointer, RO. This field indicates the location of the next * capability with respect to the effective address of this capability */ #define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_MASK) #define USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_MASK (0x80000000U) #define USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_SHIFT (31U) /*! cpu_debug_en - Debug Bus Enable, RW. When 0, allows the xhci_debug_sel primary input to control * selection of Debug Bus sources. When 1, allows the cpu_debug_bus_sel field in the * XECP_CDNS_DEBUG_BUS_CTRL register to control selection of Debug Bus sources. Default value after reset is * '0' */ #define USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_MASK) /*! @} */ /*! @name XECP_CDNS_DEBUG_BUS_CTRL - xHCI Debug Bus Control */ /*! @{ */ #define USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_MASK (0x1FU) #define USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_SHIFT (0U) /*! cpu_debug_bus_sel - Debug Bus Select, RW. Value of this field determines a source of Debug Bus. Default value after reset is 0 */ #define USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_MASK) /*! @} */ /*! @name XECP_CDNS_DEBUG_BUS_STATUS - xHCI Debug Bus Status */ /*! @{ */ #define USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_MASK (0xFFFFFFFFU) #define USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_SHIFT (0U) /*! xhci_debug_bus - Debug Bus, RO. Debug Bus current value. Note for multi-bit probes, this * register is only suitable for analysing a static value due to simplified clock domain synchronisation */ #define USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_MASK) /*! @} */ /*! @name XECP_PM_CAP - Extended Power Management capability */ /*! @{ */ #define USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_MASK (0xFFU) #define USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_SHIFT (0U) /*! XHCI_PM_CAP_ID - XHCI_PM_CAP_ID. Power Management capability ID */ #define USB3_XECP_PM_CAP_XHCI_PM_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_SHIFT)) & USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_MASK) #define USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_MASK (0xFF00U) #define USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_SHIFT (8U) /*! XHCI_PM_CAPABILITY_DW - XHCI_PM_CAPABILITY_DW. Next Item Pointer. This field provides an offset * pointing to the location of next item in the functions capability list */ #define USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_SHIFT)) & USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_MASK) #define USB3_XECP_PM_CAP_Version_MASK (0x70000U) #define USB3_XECP_PM_CAP_Version_SHIFT (16U) /*! Version - Power Management Capabilities: Version. Default = '011'. A value of '011' indicates * that this function complies with revision 1.2 of the PCI Power Management Interface Specification */ #define USB3_XECP_PM_CAP_Version(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_Version_SHIFT)) & USB3_XECP_PM_CAP_Version_MASK) #define USB3_XECP_PM_CAP_PME_clock_MASK (0x80000U) #define USB3_XECP_PM_CAP_PME_clock_SHIFT (19U) /*! PME_clock - Power Management Capabilities: PME Clock. Default = '0'. When this bit is a '1', it * indicates that the function relies on the presence of the PCI clock for PME# operation. When * this bit is a '0', it indicates that no PCI clock is required for the function to generate * PME#. Functions that do not support PME# generation in any state must return '0' for this field */ #define USB3_XECP_PM_CAP_PME_clock(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_PME_clock_SHIFT)) & USB3_XECP_PM_CAP_PME_clock_MASK) #define USB3_XECP_PM_CAP_reserved_MASK (0x100000U) #define USB3_XECP_PM_CAP_reserved_SHIFT (20U) /*! reserved - reserved */ #define USB3_XECP_PM_CAP_reserved(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_reserved_SHIFT)) & USB3_XECP_PM_CAP_reserved_MASK) #define USB3_XECP_PM_CAP_DSI_MASK (0x200000U) #define USB3_XECP_PM_CAP_DSI_SHIFT (21U) /*! DSI - Power Management Capabilities: DSI. Default = device specific. The Device Specific * Initialization bit indicates whether special initialization of this function is required (beyond the * standard PCI configuration header) before the generic class device driver is able to use it. * Note that this bit is not used by some operating systems. Microsoft Windows and Windows NT, for * instance, do not use this bit to determine whether to use D3. Instead, they use the drivers * capabilities to determine this. A '1' indicates that the function requires a device specific * initialization sequence following transition to the D0 uninitialized state. For more information * refer to Section 8.3. of PCI bus Power Management specification */ #define USB3_XECP_PM_CAP_DSI(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_DSI_SHIFT)) & USB3_XECP_PM_CAP_DSI_MASK) #define USB3_XECP_PM_CAP_AUX_CURRENT_MASK (0x1C00000U) #define USB3_XECP_PM_CAP_AUX_CURRENT_SHIFT (22U) /*! AUX_CURRENT - Power Management Capabilities: Aux_Current. Default = device specific. This 3 bit * field reports the 3.3Vaux auxiliary current requirements for the PCI function. If the Data * Register field of XECP_PM_PMCSR has been implemented by this function: - reads of this field must * return a value of '000', - the Data Register takes precedence over this field for 3.3Vaux * current requirement reporting. If PME# generation from D3cold is not supported by the function * (XECP_PM_CAP[15]='0'), this field must return a value of '000' when read. For functions that * support PME# from D3cold, and do not implement the Data Register, the following bit encoding for * maximum current required apply : '111': 375 mA, '110': 320 mA, '101': 270 mA, '100': 220 mA, * '011': 160 mA, '010': 100 mA, '001': 55 mA, '000': 0 (self powered) */ #define USB3_XECP_PM_CAP_AUX_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_AUX_CURRENT_SHIFT)) & USB3_XECP_PM_CAP_AUX_CURRENT_MASK) #define USB3_XECP_PM_CAP_D1_Support_MASK (0x2000000U) #define USB3_XECP_PM_CAP_D1_Support_SHIFT (25U) /*! D1_Support - Power Management Capabilities: D1_Support. Default = device specific. If this bit * is a '1', this function supports the D1 Power Management State. Functions that do not support * D1 must always return a value of '0' for this bit */ #define USB3_XECP_PM_CAP_D1_Support(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_D1_Support_SHIFT)) & USB3_XECP_PM_CAP_D1_Support_MASK) #define USB3_XECP_PM_CAP_D2_Support_MASK (0x4000000U) #define USB3_XECP_PM_CAP_D2_Support_SHIFT (26U) /*! D2_Support - Power Management Capabilities: D2_Support. Default = device specific. If this bit * is a '1', this function supports the D2 Power Management State. Functions that do not support * D2 must always return a value of '0' for this bit */ #define USB3_XECP_PM_CAP_D2_Support(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_D2_Support_SHIFT)) & USB3_XECP_PM_CAP_D2_Support_MASK) #define USB3_XECP_PM_CAP_PME_Support_MASK (0xF8000000U) #define USB3_XECP_PM_CAP_PME_Support_SHIFT (27U) /*! PME_Support - Power Management Capabilities: PME_Support. Default = device specific. This 5-bit * field indicates the power states in which the function may assert PME#. A value of '0' for any * bit indicates that the function is not capable of asserting the PME# signal while in that * power state. Encodings: bit 0 set: X XXX1b - PME# can be asserted from D0, bit 1 set: X XX1Xb - * PME# can be asserted from D1, bit 2 set: X X1XXb - PME# can be asserted from D2, bit 3 set: X * 1XXXb - PME# can be asserted from D3hot, bit 4 set: 1 XXXXb - PME# can be asserted from D3cold */ #define USB3_XECP_PM_CAP_PME_Support(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_PME_Support_SHIFT)) & USB3_XECP_PM_CAP_PME_Support_MASK) /*! @} */ /*! @name XECP_PM_PMCSR - Extended Power Management Control/Status */ /*! @{ */ #define USB3_XECP_PM_PMCSR_PowerState_MASK (0x3U) #define USB3_XECP_PM_PMCSR_PowerState_SHIFT (0U) /*! PowerState - Power Management Control/Status Register: PowerState. Default = zero. This 2-bit * field is used both to determine the current power state of a function and to set the function * into a new power state. Possible values: '00': D0, '01': D1, '10': D2, '11': D3hot. If software * attempts to write an unsupported, optional state to this field, the write operation must * complete normally on the bus; however, the data is discarded and no state change occurs */ #define USB3_XECP_PM_PMCSR_PowerState(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_PowerState_SHIFT)) & USB3_XECP_PM_PMCSR_PowerState_MASK) #define USB3_XECP_PM_PMCSR_reserved1_MASK (0x4U) #define USB3_XECP_PM_PMCSR_reserved1_SHIFT (2U) /*! reserved1 - Power Management Control/Status Register: reserved */ #define USB3_XECP_PM_PMCSR_reserved1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_reserved1_SHIFT)) & USB3_XECP_PM_PMCSR_reserved1_MASK) #define USB3_XECP_PM_PMCSR_No_Soft_Reset_MASK (0x8U) #define USB3_XECP_PM_PMCSR_No_Soft_Reset_SHIFT (3U) /*! No_Soft_Reset - Power Management Control/Status Register: No_Soft_Reset. Default = device * specific. When set to '1', this bit indicates that devices transitioning from D3hot to D0 because of * PowerState commands do not perform an internal reset. Configuration Context is preserved. * Upon transition from the D3hot to the D0 Initialized state, no additional operating system * intervention is required to preserve Configuration Context beyond writing the PowerState bits. When * cleared to '0', devices do perform an internal reset upon transitioning from D3hot to D0 via * software control of the PowerState bits. Configuration Context is lost when performing the soft * reset. Upon transition from the D3hot to the D0 state, full reinitialization sequence is * needed to return the device to D0 Initialized. Regardless of this bit, devices that transition * from D3hot to D0 by a system or bus segment reset will return to the device state D0 * Uninitialized with only PME context preserved if PME is supported and enabled */ #define USB3_XECP_PM_PMCSR_No_Soft_Reset(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_No_Soft_Reset_SHIFT)) & USB3_XECP_PM_PMCSR_No_Soft_Reset_MASK) #define USB3_XECP_PM_PMCSR_reserved2_MASK (0xF0U) #define USB3_XECP_PM_PMCSR_reserved2_SHIFT (4U) /*! reserved2 - Power Management Control/Status Register: reserved */ #define USB3_XECP_PM_PMCSR_reserved2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_reserved2_SHIFT)) & USB3_XECP_PM_PMCSR_reserved2_MASK) #define USB3_XECP_PM_PMCSR_PME_En_MASK (0x100U) #define USB3_XECP_PM_PMCSR_PME_En_SHIFT (8U) /*! PME_En - Power Management Control/Status Register: PME_En. A '1' in this field enables the * function to assert PME#. When '0', PME# assertion is disabled. This bit defaults to '0' if the * function does not support PME# generation from D3cold. If the function supports PME# from D3cold, * then this bit is sticky and must be explicitly cleared by the operating system each time it is * initially loaded. Functions that do not support PME# generation from any D-state (i.e., * XECP_PM_CAP[15:11] = '00000'), may hardwire this bit to be read-only always returning a '0' when * read by system software */ #define USB3_XECP_PM_PMCSR_PME_En(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_PME_En_SHIFT)) & USB3_XECP_PM_PMCSR_PME_En_MASK) #define USB3_XECP_PM_PMCSR_data_select_MASK (0x1E00U) #define USB3_XECP_PM_PMCSR_data_select_SHIFT (9U) /*! data_select - Power Management Control/Status Register: Data_Select. Default = zero. This 4-bit * field is used to select, which data is to be reported through the Data register and Data_Scale * fields of XECP_PM_PMCSR register. This field is a required component of the Data register and * must be implemented if the Data register is implemented. If the Data register field of * XECP_PM_PMCSR is not implemented, this field should be read only and return zero when read. Refer to * Section 3.2.6 of PCI bus Power Management for more details */ #define USB3_XECP_PM_PMCSR_data_select(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_data_select_SHIFT)) & USB3_XECP_PM_PMCSR_data_select_MASK) #define USB3_XECP_PM_PMCSR_data_scale_MASK (0x6000U) #define USB3_XECP_PM_PMCSR_data_scale_SHIFT (13U) /*! data_scale - Power Management Control/Status Register: Data_Scale. Default = device specific. * This 2-bit read-only field indicates the scaling factor to be used when interpreting the value * of the Data register field of XECP_PM_PMCSR register. The value and meaning of this field will * vary depending on which data value has been selected by the Data_Select field of this * register. This field is a required component of the Data register and must be implemented if the Data * register is implemented. If the Data register has not been implemented, this field must return * zero when read. Refer to Section 3.2.6 of PCI bus Power Management specification for more * details */ #define USB3_XECP_PM_PMCSR_data_scale(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_data_scale_SHIFT)) & USB3_XECP_PM_PMCSR_data_scale_MASK) #define USB3_XECP_PM_PMCSR_pme_status_MASK (0x8000U) #define USB3_XECP_PM_PMCSR_pme_status_SHIFT (15U) /*! pme_status - Power Management Control/Status Register: PME_Status. This bit is set when the * function would normally assert the PME# signal independent of the state of the PME_En bit. Writing * a '1' to this bit will clear it and cause the function to stop asserting a PME# (if enabled). * Writing a '0' has no effect. This bit defaults to '0' if the function does not support PME# * generation from D3cold. If the function supports PME# from D3cold, then this bit is sticky and * must be explicitly cleared by the operating system each time the operating system is initially * loaded */ #define USB3_XECP_PM_PMCSR_pme_status(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_pme_status_SHIFT)) & USB3_XECP_PM_PMCSR_pme_status_MASK) #define USB3_XECP_PM_PMCSR_reserved3_MASK (0x3F0000U) #define USB3_XECP_PM_PMCSR_reserved3_SHIFT (16U) /*! reserved3 - PMCSR Bridge Support Extensions: reserved */ #define USB3_XECP_PM_PMCSR_reserved3(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_reserved3_SHIFT)) & USB3_XECP_PM_PMCSR_reserved3_MASK) #define USB3_XECP_PM_PMCSR_B2_B3_MASK (0x400000U) #define USB3_XECP_PM_PMCSR_B2_B3_SHIFT (22U) /*! B2_B3 - PMCSR Bridge Support Extensions: B2_B3# (B2/B3 support for D3hot). External strap or * internally hardwired. The state of this bit determines the action that is to occur as a direct * result of programming the function to D3hot. A '1' indicates that when the bridge function is * programmed to D3hot, its secondary buss PCI clock will be stopped (B2). A '0' indicates that * when the bridge function is programmed to D3hot, its secondary bus will have its power removed * (B3). This bit is only meaningful if bit BPCC_En of XECP_PM_PMCSR register is a '1'. Refer to * Section 4.7.1 of PCI bus Power Management specification for details */ #define USB3_XECP_PM_PMCSR_B2_B3(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_B2_B3_SHIFT)) & USB3_XECP_PM_PMCSR_B2_B3_MASK) #define USB3_XECP_PM_PMCSR_BPCC_EN_MASK (0x800000U) #define USB3_XECP_PM_PMCSR_BPCC_EN_SHIFT (23U) /*! BPCC_EN - PMCSR Bridge Support Extensions: BPCC_En (Bus Power/Clock Control Enable). External * strap or internally hardwired. A '1' indicates that the bus power/clock control mechanism as * defined in Section 4.7.1 PCI bus Power Management specification is enabled. A '0' indicates that * the bus power/clock control policies defined in Section 4.7.1 PCI bus Power Management * specification have been disabled. When the Bus Power/Clock Control mechanism is disabled, the bridges * Power Management Control/Status Register PowerState field cannot be used by the system * software to control the power or clock of the bridges secondary bus */ #define USB3_XECP_PM_PMCSR_BPCC_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_BPCC_EN_SHIFT)) & USB3_XECP_PM_PMCSR_BPCC_EN_MASK) #define USB3_XECP_PM_PMCSR_data_register_MASK (0xFF000000U) #define USB3_XECP_PM_PMCSR_data_register_SHIFT (24U) /*! data_register - Data register. This register is used to report the state dependent data * requested by the Data_Select field of XECP_PM_PMCSR register. The value of Data register is scaled by * the value reported by the Data_Scale field of XECP_PM_PMCSR */ #define USB3_XECP_PM_PMCSR_data_register(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_data_register_SHIFT)) & USB3_XECP_PM_PMCSR_data_register_MASK) /*! @} */ /*! @name XECP_MSI_CAP - MSI configuration */ /*! @{ */ #define USB3_XECP_MSI_CAP_MSI_ID_MASK (0xFFU) #define USB3_XECP_MSI_CAP_MSI_ID_SHIFT (0U) /*! MSI_ID - Capability ID for Message Signaled Interrupts. The value of 05h in this field * identifies the function as being MSI capable */ #define USB3_XECP_MSI_CAP_MSI_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_ID_SHIFT)) & USB3_XECP_MSI_CAP_MSI_ID_MASK) #define USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_MASK (0xFF00U) #define USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_SHIFT (8U) /*! XECP_MSI_CAP_OFFSET - Pointer to the next item in the capabilities list. A non-zero value in * this field indicates a relative offset, in 32-bit words, from this 32-bit word to the beginning * of the next extended capability */ #define USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_SHIFT)) & USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_MASK) #define USB3_XECP_MSI_CAP_MSI_en_MASK (0x10000U) #define USB3_XECP_MSI_CAP_MSI_en_SHIFT (16U) /*! MSI_en - MSI Message Control: MSI enable. System configuration software sets this bit to enable * MSI. A device driver is prohibited from writing this bit to mask a functions service request. * If '0', the function is prohibited from using MSI to request service. This bits state after * reset is '0' (MSI is disabled) */ #define USB3_XECP_MSI_CAP_MSI_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_en_SHIFT)) & USB3_XECP_MSI_CAP_MSI_en_MASK) #define USB3_XECP_MSI_CAP_MSI_MMC_MASK (0xE0000U) #define USB3_XECP_MSI_CAP_MSI_MMC_SHIFT (17U) /*! MSI_MMC - MSI Message Control: Multiple Message Capable. System software reads this field to * determine the number of requested vectors. The number of requested vectors must be aligned to a * power of two (if a function requires three vectors, it requests four by initializing this field * to '010'). The encoding is defined as: '000': 1, '001': 2, '010': 4, '011': 8, '100': 16, * '101': 32, '110': Reserved, '111': Reserved. This field is read only. */ #define USB3_XECP_MSI_CAP_MSI_MMC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_MMC_SHIFT)) & USB3_XECP_MSI_CAP_MSI_MMC_MASK) #define USB3_XECP_MSI_CAP_MSI_MME_MASK (0x700000U) #define USB3_XECP_MSI_CAP_MSI_MME_SHIFT (20U) /*! MSI_MME - MSI Message Control: Multiple Message Enable. Software writes to this field to * indicate the number of allocated vectors (equal to or less than the number of requested vectors). The * number of allocated vectors is aligned to a power of two. If a function requests four vectors * (indicated by a Multiple Message Capable encoding of 010), system software can allocate * either four, two, or one vector by writing a '010', '001', or '000' to this field, respectively. * When MSI is enabled, a function will be allocated at least one vector. The encoding is defined * as: '000': 1, '001': 2, '010': 4, '011': 8, '100': 16, '101': 32, '110': Reserved, '111': * Reserved. This fields state after reset is '000' */ #define USB3_XECP_MSI_CAP_MSI_MME(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_MME_SHIFT)) & USB3_XECP_MSI_CAP_MSI_MME_MASK) #define USB3_XECP_MSI_CAP_AC64_MASK (0x800000U) #define USB3_XECP_MSI_CAP_AC64_SHIFT (23U) /*! AC64 - MSI Message Control: 64 bit address capable. If '1', the function is capable of * generating sending a 64-bit message address. If '0', the function is not capable of generating sending * a 64-bit message address. This bit is read only */ #define USB3_XECP_MSI_CAP_AC64(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_AC64_SHIFT)) & USB3_XECP_MSI_CAP_AC64_MASK) #define USB3_XECP_MSI_CAP_per_vector_masking_MASK (0x1000000U) #define USB3_XECP_MSI_CAP_per_vector_masking_SHIFT (24U) /*! per_vector_masking - MSI Message Control: Per-vector masking capable. If '1', the function * supports MSI per-vector masking. If '0', the function does not support MSI per-vector masking. This * bit is read only. Not Supported in this configuration */ #define USB3_XECP_MSI_CAP_per_vector_masking(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_per_vector_masking_SHIFT)) & USB3_XECP_MSI_CAP_per_vector_masking_MASK) /*! @} */ /*! @name XECP_MSI_ADDR_L - Message Lower Address */ /*! @{ */ #define USB3_XECP_MSI_ADDR_L_reserved_MASK (0x3U) #define USB3_XECP_MSI_ADDR_L_reserved_SHIFT (0U) /*! reserved - Reserved. Always returns zero on read. Write operations have no effect. Those bits * are driven to zero during the address phase */ #define USB3_XECP_MSI_ADDR_L_reserved(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_ADDR_L_reserved_SHIFT)) & USB3_XECP_MSI_ADDR_L_reserved_MASK) #define USB3_XECP_MSI_ADDR_L_MSI_addr_low_MASK (0xFFFFFFFCU) #define USB3_XECP_MSI_ADDR_L_MSI_addr_low_SHIFT (2U) /*! MSI_addr_low - Message Lower Address for MSI. System-specified message address. If the Message * Enable bit of MSI Message Control (bit 16 of the XCEP_MSI_CAP register) is set, the contents of * this register specify the DWORD-aligned address for the MSI memory write transaction. Note: * This field should not be written unless the Message Enable bit of MSI Message Control (bit 16 * of the XCEP_MSI_CAP register) is cleared. This field is read/write */ #define USB3_XECP_MSI_ADDR_L_MSI_addr_low(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_ADDR_L_MSI_addr_low_SHIFT)) & USB3_XECP_MSI_ADDR_L_MSI_addr_low_MASK) /*! @} */ /*! @name XECP_MSI_ADDR_H - Message Upper Address */ /*! @{ */ #define USB3_XECP_MSI_ADDR_H_MSI_addr_hi_MASK (0xFFFFFFFFU) #define USB3_XECP_MSI_ADDR_H_MSI_addr_hi_SHIFT (0U) /*! MSI_addr_hi - Message Upper Address for MSI. System-specified message upper address. Note: This * field should not be written unless the Message Enable bit of MSI Message Control (bit 16 of * the XCEP_MSI_CAP register) is cleared. This field is read/write */ #define USB3_XECP_MSI_ADDR_H_MSI_addr_hi(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_ADDR_H_MSI_addr_hi_SHIFT)) & USB3_XECP_MSI_ADDR_H_MSI_addr_hi_MASK) /*! @} */ /*! @name XECP_MSI_DATA - Message data */ /*! @{ */ #define USB3_XECP_MSI_DATA_MSI_data_MASK (0xFFFFU) #define USB3_XECP_MSI_DATA_MSI_data_SHIFT (0U) /*! MSI_data - System-specified message data. If the Message Enable bit of MSI Message Control (bit * 16 of the XCEP_MSI_CAP register) is set, the message data is driven onto the lower word (bits * [15:0]) of the memory write transactions data phase. Bits [31:16] are driven to zero during * the memory write transactions data phase. C/BE[3::0]# are asserted during the data phase of the * memory write transaction. The Multiple Message Enable field of MSI Message Control (see * MSI_MME field of XCEP_MSI_CAP register) defines the number of low order message data bits the * function is permitted to modify to generate its system software allocated vectors. For example, a * Multiple Message Enable encoding of '010' indicates the function has been allocated four vectors * and is permitted to modify message data bits 1 and 0 (a function modifies the lower message * data bits to generate the allocated number of vectors). If the Multiple Message Enable field is * '000', the function is not permitted to modify the message data. Note: This field should not * be written unless the Message Enable bit of MSI Message Control (bit 16 of the XCEP_MSI_CAP * register) is cleared. This field is read/write */ #define USB3_XECP_MSI_DATA_MSI_data(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_DATA_MSI_data_SHIFT)) & USB3_XECP_MSI_DATA_MSI_data_MASK) /*! @} */ /*! @name XECP_AXI_CAP - AXI Master Wrapper Extended Capability */ /*! @{ */ #define USB3_XECP_AXI_CAP_AXI_CAP_ID_MASK (0xFFU) #define USB3_XECP_AXI_CAP_AXI_CAP_ID_SHIFT (0U) /*! AXI_CAP_ID - VEND_DEF_AXI_MASTER_WRAPPER_CAP_ID, RO. Vendor defined xHCI Extended Capability: * 0xC2. This field identifies the AXI wrapper xHCI Extended capability */ #define USB3_XECP_AXI_CAP_AXI_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_CAP_ID_SHIFT)) & USB3_XECP_AXI_CAP_AXI_CAP_ID_MASK) #define USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_MASK (0xFF00U) #define USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_SHIFT (8U) /*! XECP_AXI_CAP_OFFSET - Next capability Offset, RO. This field points to the xHC MMIO space offset * of the next xHCI extended capability pointer. A value of 00h indicates the end of the * extended capability list. A non-zero value in this register indicates a relative offset, in Dwords, * from this Dword to the beginning of the next extended capability */ #define USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_SHIFT)) & USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_MASK) #define USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_MASK (0x10000U) #define USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_SHIFT (16U) /*! AXI_ADDRESS_WIDTH_64 - AXI address bus width capability, RO. '0': 32-bit address bus width, '1': 64-bit address bus width */ #define USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_SHIFT)) & USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_MASK) #define USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_MASK (0x400000U) #define USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_SHIFT (22U) /*! AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS - AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS, RO. Presents * information about AXI byte burst capability: '0': no byte bursts, '1': byte bursts enabled */ #define USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_SHIFT)) & USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_MASK) #define USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_MASK (0x800000U) #define USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_SHIFT (23U) /*! AXI_DISABLE_OOO - Disable Out-Of-Order R channel responses (AXI_MASTER_WRAPPER_DISABLE_OOO), RO. * This relates to number of IDs used at AXI IF. If Out-Of-Order R channel responses are not * disabled this count may be greater than one and in such a case the R channel responses may come * Out-Of-Order. The flag gives information about number of used AXI IDs: '0': single ID, '1': * multiple IDs */ #define USB3_XECP_AXI_CAP_AXI_DISABLE_OOO(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_SHIFT)) & USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_MASK) #define USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_MASK (0x7000000U) #define USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_SHIFT (24U) /*! AXI_DATA_BUS_SIZE - AXI_DATA_WORD_SIZE, RO. AXI data buses size capability. It uses AXI AxSIZE * Encoding. Values of 64-bit ('011') or 128-bit ('100') are supported through compile time * configuration */ #define USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_SHIFT)) & USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_MASK) #define USB3_XECP_AXI_CAP_AXI_ERROR_MASK (0x20000000U) #define USB3_XECP_AXI_CAP_AXI_ERROR_SHIFT (29U) /*! AXI_ERROR - AXI ERROR, RW1C. Provides an information about AXI ERROR response on B or R channel. * This flag is cleared by writing '1' to it. Once set it is held until cleared. The condition * setting this register will also assert HSE. This flag may be read by software while handling * HSE assertion to determine if the case was AXI ERROR reponse */ #define USB3_XECP_AXI_CAP_AXI_ERROR(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_ERROR_SHIFT)) & USB3_XECP_AXI_CAP_AXI_ERROR_MASK) #define USB3_XECP_AXI_CAP_AXI_IDLE_MASK (0x40000000U) #define USB3_XECP_AXI_CAP_AXI_IDLE_SHIFT (30U) /*! AXI_IDLE - AXI IDLE, RO. Information about the AXI Master wrapper state: '0': no pending action * required by the AXI Master wrapper, '1': the AXI Master wrapper has outstanding transactions. * Note: HCH halted bit will not be asserted if the AXI Master wrapper is not idle */ #define USB3_XECP_AXI_CAP_AXI_IDLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_IDLE_SHIFT)) & USB3_XECP_AXI_CAP_AXI_IDLE_MASK) #define USB3_XECP_AXI_CAP_AXI_HALT_MASK (0x80000000U) #define USB3_XECP_AXI_CAP_AXI_HALT_SHIFT (31U) /*! AXI_HALT - AXI HALT, RW. The AXI Master wrapper's control bit. When set, the AXI Master wrapper * will complete current CORE REQ (or IRQ) and stop acknowledging next ones. If the xHC is * stopped the AXI Master wrapper is halted automatically. If the xHC is started the AXI Master wrapper * is resumed automatically. Software should set this bit to stop the AXI Master issuing new AXI * transactions. It may then use the IDLE bit to determine when all previous transactions were * completed. Note: The AXI Master wrapper will execute halted only if xHC stopped its internal * operation */ #define USB3_XECP_AXI_CAP_AXI_HALT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_HALT_SHIFT)) & USB3_XECP_AXI_CAP_AXI_HALT_MASK) /*! @} */ /*! @name XECP_AXI_CFG0 - AXI Master Wrapper Extended Capability Configuration */ /*! @{ */ #define USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_MASK (0x3FU) #define USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_SHIFT (0U) /*! AXI_MAX_WR_OT - AXI MAX_WRITE_OUTSTANDING, RO. Maximum number of Outstanding Write Transactions * initiated by the AXI Master wrapper in AW channel. The value written to this field should be * the Maximum number of Outstanding Write Transactions initiated by the AXI Master wrapper minus * 1, thus the Maximum number of Outstanding Write Transactions is 1 more than the programmed * value */ #define USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_MASK) #define USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_MASK (0xFF00U) #define USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_SHIFT (8U) /*! AXI_WR_DEPTH - AXI WRITE_BUFFER_DEPTH, RO. Number of AXI Write beats that can be buffered by the * AXI Master wrapper. The value written to this field should be the number of AXI Write beats * that can be buffered by the AXI Master wrapper minus 1 */ #define USB3_XECP_AXI_CFG0_AXI_WR_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_MASK) #define USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_MASK (0x3F0000U) #define USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_SHIFT (16U) /*! AXI_MAX_RD_OT - AXI MAX_READ_OUTSTANDING, RO. Maximum number of Outstanding Read Transactions * initiated by the AXI Master wrapper in AR channel. The value written to this field should be the * Maximum number of Outstanding Read Transactions initiated by the AXI Master wrapper minus 1, * thus the Maximum number of Outstanding Read Transactions is 1 more than the programmed value */ #define USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_MASK) #define USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_MASK (0xFF000000U) #define USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_SHIFT (24U) /*! AXI_RD_DEPTH - AXI READ_BUFFER_DEPTH, RO. Number of AXI Read beats that can be buffered by the * AXI Master wrapper. The value written to this field should be the Number of AXI Read beats that * can be buffered by the AXI Master wrapper minus 1 */ #define USB3_XECP_AXI_CFG0_AXI_RD_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_MASK) /*! @} */ /*! @name XECP_AXI_CTRL0 - AXI Master Wrapper Extended Capability Control */ /*! @{ */ #define USB3_XECP_AXI_CTRL0_AXI_BMAX_MASK (0xFU) #define USB3_XECP_AXI_CTRL0_AXI_BMAX_SHIFT (0U) /*! AXI_BMAX - AXI BMAX, RW. The register controls maximum burst length - it is used by the AXI * Master wrapper to determine maximum value of AxLEN. It uses AXI AxLEN encoding. Default value is * the maximum supported one and it is implementation specific. Writing value greater than maximum * will result in setting the register to its defaults. This register can be written only when * the AXI Master wrapper is halted (AXI_HALT set to '1') and idle (AXI_IDLE is '1'). Note: This * register should only be written to during the register initialisation process */ #define USB3_XECP_AXI_CTRL0_AXI_BMAX(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL0_AXI_BMAX_SHIFT)) & USB3_XECP_AXI_CTRL0_AXI_BMAX_MASK) /*! @} */ /*! @name XECP_AXI_CTRL1 - AXI Master Wrapper Extended Capability Control */ /*! @{ */ #define USB3_XECP_AXI_CTRL1_AXI_WOT_MASK (0x3FU) #define USB3_XECP_AXI_CTRL1_AXI_WOT_SHIFT (0U) /*! AXI_WOT - AXI WRITE_OUTSTANDING, RW. Number of outstanding write transactions that can be * initiated by the AXI Master wrapper. Default value of this field is MAX_WRITE_OUTSTANDING-1 (see * AXI_MAX_WR_OT field of XECP_AXI_CFG0). Writing value greater than the default will result in * setting the register to its defaults. This register can be written only when the AXI Master * wrapper is halted (AXI_HALT set to '1') and idle (AXI_IDLE is '1'). The value written to this field * should be the requested number of outstanding write transactions minus 1, thus the actual * number of possible outstanding write transactions is one more than the programmed value. Note: * This register should only be written to during the register initialisation process */ #define USB3_XECP_AXI_CTRL1_AXI_WOT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL1_AXI_WOT_SHIFT)) & USB3_XECP_AXI_CTRL1_AXI_WOT_MASK) #define USB3_XECP_AXI_CTRL1_AXI_ROT_MASK (0x3F0000U) #define USB3_XECP_AXI_CTRL1_AXI_ROT_SHIFT (16U) /*! AXI_ROT - AXI READ_OUTSTANDING, RW. Number of outstanding read transactions that can be * initiated by the AXI Master wrapper. Default value of this field is MAX_READ_OUTSTANDING-1 (see * AXI_MAX_RD_OT field of XECP_AXI_CFG0 register). Writing value greater than the default will result * in setting the register to its defaults. This register can be written only when the AXI Master * wrapper is halted (AXI_HALT set to '1') and idle (AXI_IDLE is '1'). The value written to this * field should be the requested number of outstanding read transactions minus 1, thus the actual * number of possible outstanding read transactions is one more than the programmed value. Note: * This register should only be written to during the register initialisation process */ #define USB3_XECP_AXI_CTRL1_AXI_ROT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL1_AXI_ROT_SHIFT)) & USB3_XECP_AXI_CTRL1_AXI_ROT_MASK) /*! @} */ /*! @name XECP_AXI_CTRL2 - AXI Master Wrapper Extended Capability Control */ /*! @{ */ #define USB3_XECP_AXI_CTRL2_AXI_WTHRES_MASK (0x1FU) #define USB3_XECP_AXI_CTRL2_AXI_WTHRES_SHIFT (0U) /*! AXI_WTHRES - AXI Write Buffer Threshold, RW. When performing an AXI write burst this field * specifies the minimum number of required AXI beats buffered prior to starting the burst on AXI * W-Channel by asserting wvalid. This allows a user to balance the requirement for minimal latency * with the requirement for low bus utilisation during bursts. Burst lengths smaller than or equal * to this threshold will be buffered completely and then output on W-Channel. Burst lengths * greater than this threshold will output the burst on the W-Channel such that the first AXI_WTHRES * beats will be continuously with no drop of WVALID, beats thereafter may or may not be * continuous depending on availability of data. Legal values are between 1 and (AXI_WDD-1). A value of * 1 means that the burst is started on W-Channel as soon as any data is available without any * additional delay. A value of 0 is reserved and should not be used as may lead to unpredictable * behaviour. This register can be written only when the AXI Master wrapper is halted (AXI_HALT * set to '1') and idle (AXI_IDLE is '1'). Note: This register should only be written to during the * register initialisation process */ #define USB3_XECP_AXI_CTRL2_AXI_WTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL2_AXI_WTHRES_SHIFT)) & USB3_XECP_AXI_CTRL2_AXI_WTHRES_MASK) /*! @} */ /*! @name XECP_SUPP_USB2_CAP0 - xHCI Supported Protocol Capability */ /*! @{ */ #define USB3_XECP_SUPP_USB2_CAP0_PID_MASK (0xFFU) #define USB3_XECP_SUPP_USB2_CAP0_PID_SHIFT (0U) /*! PID - Capability ID. The value identifies the capability as Supported Protocol */ #define USB3_XECP_SUPP_USB2_CAP0_PID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_PID_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_PID_MASK) #define USB3_XECP_SUPP_USB2_CAP0_NextCapID_MASK (0xFF00U) #define USB3_XECP_SUPP_USB2_CAP0_NextCapID_SHIFT (8U) /*! NextCapID - This field indicates the location of the next capability with respect to the * effective address of this capability. Refer to Table 142 of xHCI specification for more information * on this field */ #define USB3_XECP_SUPP_USB2_CAP0_NextCapID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_NextCapID_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_NextCapID_MASK) #define USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_MASK (0xFF0000U) #define USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_SHIFT (16U) /*! Minor_Rev - Minor Specification Release Number in Binary-Coded Decimal (i.e.,version x.10 is * 10h). This field identifies the minor release number component of the specification with which * the xHC is compliant */ #define USB3_XECP_SUPP_USB2_CAP0_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_MASK) #define USB3_XECP_SUPP_USB2_CAP0_Major_Rev_MASK (0xFF000000U) #define USB3_XECP_SUPP_USB2_CAP0_Major_Rev_SHIFT (24U) /*! Major_Rev - Major Specification Release Number in Binary-Coded Decimal (i.e.,version 3.x is * 03h). This field identifies the major release number component of the specification with which the * xHC is compliant */ #define USB3_XECP_SUPP_USB2_CAP0_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_Major_Rev_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_Major_Rev_MASK) /*! @} */ /*! @name XECP_SUPP_USB2_CAP1 - xHCI Supported Protocol Capability */ /*! @{ */ #define USB3_XECP_SUPP_USB2_CAP1_USB_STRING_MASK (0xFFFFFFFFU) #define USB3_XECP_SUPP_USB2_CAP1_USB_STRING_SHIFT (0U) /*! USB_STRING - Name String, RO. This field is a mnemonic name string that references the * specification with which the xHC is compliant. Four ASCII characters may be defined. Allowed characters * are: alphanumeric, space, and underscore. Alpha characters are case sensitive. Refer to * section 7.2.2 of xHCI specification for defined values */ #define USB3_XECP_SUPP_USB2_CAP1_USB_STRING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP1_USB_STRING_SHIFT)) & USB3_XECP_SUPP_USB2_CAP1_USB_STRING_MASK) /*! @} */ /*! @name XECP_SUPP_USB2_CAP2 - xHCI Supported Protocol Capability */ /*! @{ */ #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_MASK (0xFFU) #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_SHIFT (0U) /*! Compatible_Port_Offset - This field specifies the starting Port Number of Root Hub Ports that * support this protocol. Valid values are 1 to MaxPorts */ #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_MASK) #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_MASK (0xFF00U) #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_SHIFT (8U) /*! Compatible_Port_Count - This field identifies the number of consecutive Root Hub Ports (starting * at the Compatible Port Offset) that support this protocol. Valid values are 1 to MaxPorts */ #define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_MASK) #define USB3_XECP_SUPP_USB2_CAP2_L1C_MASK (0x10000U) #define USB3_XECP_SUPP_USB2_CAP2_L1C_SHIFT (16U) /*! L1C - If '1'LPM is supported (mandatory in xHCI1_00). In xHCI specification this field is * reserved RsvdP, see section 7.2.2.1.3 */ #define USB3_XECP_SUPP_USB2_CAP2_L1C(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_L1C_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_L1C_MASK) #define USB3_XECP_SUPP_USB2_CAP2_HSO_MASK (0x20000U) #define USB3_XECP_SUPP_USB2_CAP2_HSO_SHIFT (17U) /*! HSO - High-speed Only. Default = Implementation dependent. If this bit is cleared to '0', the * USB2 ports described by this capability are Low-, Full-, and High-speed capable. If this bit is * set to '1', the USB2 ports described by this capability are High-speed only, e.g. the ports do * not support Low- or Full-speed operation. High-speed only implementations may introduce a * Tier mismatch, refer to section 4.24.2 of xHCI specification for more information */ #define USB3_XECP_SUPP_USB2_CAP2_HSO(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_HSO_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_HSO_MASK) #define USB3_XECP_SUPP_USB2_CAP2_IHI_MASK (0x40000U) #define USB3_XECP_SUPP_USB2_CAP2_IHI_SHIFT (18U) /*! IHI - Integrated Hub Implemented. Default = Implementation dependent. If this bit is cleared to * '0', the Root Hub to External xHC port mapping adheres to the default mapping described in * section 4.24.2.1 of xHCI specification. If this bit is set to '1', the Root Hub to External xHC * port mapping does not adhere to the default mapping described in section 4.24.2.1 of xHCI * specification, and an ACPI or other mechanism is required to define the mapping */ #define USB3_XECP_SUPP_USB2_CAP2_IHI(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_IHI_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_IHI_MASK) #define USB3_XECP_SUPP_USB2_CAP2_HLC_MASK (0x80000U) #define USB3_XECP_SUPP_USB2_CAP2_HLC_SHIFT (19U) /*! HLC - Hardware LPM Capability. Default = Implementation dependent. If this bit is set to '1', * the ports described by this xHCI Supported Protocol Capability support hardware controlled USB2 * Link Power Management. Refer to section 4.23.5.1.1.1 of xHCI specification */ #define USB3_XECP_SUPP_USB2_CAP2_HLC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_HLC_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_HLC_MASK) #define USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_MASK (0x100000U) #define USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_SHIFT (20U) /*! HLC_BESL - HLC_BESL. In xHCI 1.0 specification this field is reserved RsvdP, see section * 7.2.2.1.3. The field is described in xHCI 1.1 specification: BESL LPM Capability (BLC), RO. Default = * Implementation dependent. If this bit is set to '1', the ports described by this xHCI * Supported Protocol Capability shall apply BESL timing to BESL and BESLD fields of the PORTPMSC and * PORTHLPMC registers, as defined in Table 13. If this bit is cleared to '0', the ports described * by this xHCI Supported Protocol Capability shall apply HIRD timing to BESL and BESLD fields of * the PORTPMSC and PORTHLPMC registers, as defined in Table 13. Refer to section 4.23.5.1.1.1 * for more information. Note the BESL LMP Capability support (i.e. HLE = 1 and BLC = 1) shall be * mandatory for all xHCI 1.1 compliant xHCs */ #define USB3_XECP_SUPP_USB2_CAP2_HLC_BESL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_MASK) #define USB3_XECP_SUPP_USB2_CAP2_PSIC_MASK (0xF0000000U) #define USB3_XECP_SUPP_USB2_CAP2_PSIC_SHIFT (28U) /*! PSIC - Protocol Speed ID Count: 3, USB 2.0 Speed (High, Full, Low). This field indicates the * number of Protocol Speed ID (PSI) Dwords that the xHCI Supported Protocol Capability data * structure contains. If this field is non-zero, then all speeds supported by the protocol shall be * defined using PSI Dwords, i.e. no implied Speed ID mappings apply */ #define USB3_XECP_SUPP_USB2_CAP2_PSIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_PSIC_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_PSIC_MASK) /*! @} */ /*! @name XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE - Protocol Slot Type */ /*! @{ */ #define USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_MASK (0x1FU) #define USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_SHIFT (0U) /*! PST - This field specifies the Protocol Slot Type value, which may be specified when allocating * Device Slots that support this protocol. Valid values are 0 to 31. Refer to sections 4.6.3 and * 7.2.2.1.4 of xHCI specification. The value of the Protocol Slot Type field declared by a xHCI * Supported Protocol Capability structure is unique to an xHC implementation. Software shall * not assume a fixed mapping of the Protocol Slot Type value to a specific type of Supported * Protocol. Note that for compatibility reasons, the Protocol Slot Type value of 0 is the exception * to this rule and reserved for the USB Protocol Device Slot type */ #define USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_SHIFT)) & USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_MASK) /*! @} */ /*! @name XECP_PSI_FULL_SPEED - Protocol Speed ID */ /*! @{ */ #define USB3_XECP_PSI_FULL_SPEED_PSIV_MASK (0xFU) #define USB3_XECP_PSI_FULL_SPEED_PSIV_SHIFT (0U) /*! PSIV - Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by * this PSI Dword, then the value of this field shall be reported in the Port Speed field of * PORTSC register (5.4.8 of xHCI specification) of a compatible port. Note, the PSIV value of 0 is * reserved and shall not be defined by a PSI */ #define USB3_XECP_PSI_FULL_SPEED_PSIV(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PSIV_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PSIV_MASK) #define USB3_XECP_PSI_FULL_SPEED_PSIE_MASK (0x30U) #define USB3_XECP_PSI_FULL_SPEED_PSIE_SHIFT (4U) /*! PSIE - Protocol Speed ID Exponent. This field defines the base 10 exponent times 3, that shall * be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented * by this PSI Dword. PSIE Values and corresponding bit rates: 0: Bits per second 1: Kb/s 2: Mb/s * 3: Gb/s */ #define USB3_XECP_PSI_FULL_SPEED_PSIE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PSIE_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PSIE_MASK) #define USB3_XECP_PSI_FULL_SPEED_PLT_MASK (0xC0U) #define USB3_XECP_PSI_FULL_SPEED_PLT_SHIFT (6U) /*! PLT - PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric * bit rate, and if asymmetric, then this field also indicates if this Dword defines the receive or * transmit bit rate. Note that the Asymmetric PSI Dwords shall be paired, i.e. an Rx * immediately followed by a Tx, and both Dwords shall define the same value for the PSIV. PLT Values and * corresponding bit rate: 0: Symmetric (Single PSI Dword) 1: Reserved 2: Asymmetric Rx (Paired * with Asymmetric Tx PSI Dword) 3: Asymmetric Tx (Immediately follows Rx Asymmetric PSI Dword) */ #define USB3_XECP_PSI_FULL_SPEED_PLT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PLT_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PLT_MASK) #define USB3_XECP_PSI_FULL_SPEED_PFD_MASK (0x100U) #define USB3_XECP_PSI_FULL_SPEED_PFD_SHIFT (8U) /*! PFD - PSI Full-duplex. If this bit is '1' the link is full-duplex, and if '0' the link is half-duplex */ #define USB3_XECP_PSI_FULL_SPEED_PFD(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PFD_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PFD_MASK) #define USB3_XECP_PSI_FULL_SPEED_PSIM_MASK (0xFFFF0000U) #define USB3_XECP_PSI_FULL_SPEED_PSIM_SHIFT (16U) /*! PSIM - Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the * PSIE when calculating the maximum bit rate represented by this PSI Dword */ #define USB3_XECP_PSI_FULL_SPEED_PSIM(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PSIM_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PSIM_MASK) /*! @} */ /*! @name XECP_PSI_LOW_SPEED - Protocol Speed ID */ /*! @{ */ #define USB3_XECP_PSI_LOW_SPEED_PSIV_MASK (0xFU) #define USB3_XECP_PSI_LOW_SPEED_PSIV_SHIFT (0U) /*! PSIV - Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by * this PSI Dword, then the value of this field shall be reported in the Port Speed field of * PORTSC register (5.4.8 of xHCI specification) of a compatible port. Note, the PSIV value of 0 is * reserved and shall not be defined by a PSI */ #define USB3_XECP_PSI_LOW_SPEED_PSIV(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PSIV_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PSIV_MASK) #define USB3_XECP_PSI_LOW_SPEED_PSIE_MASK (0x30U) #define USB3_XECP_PSI_LOW_SPEED_PSIE_SHIFT (4U) /*! PSIE - Protocol Speed ID Exponent. This field defines the base 10 exponent times 3, that shall * be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented * by this PSI Dword. PSIE Values and corresponding bit rates: 0: Bits per second 1: Kb/s 2: Mb/s * 3: Gb/s */ #define USB3_XECP_PSI_LOW_SPEED_PSIE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PSIE_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PSIE_MASK) #define USB3_XECP_PSI_LOW_SPEED_PLT_MASK (0xC0U) #define USB3_XECP_PSI_LOW_SPEED_PLT_SHIFT (6U) /*! PLT - PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric * bit rate, and if asymmetric, then this field also indicates if this Dword defines the receive or * transmit bit rate. Note that the Asymmetric PSI Dwords shall be paired, i.e. an Rx * immediately followed by a Tx, and both Dwords shall define the same value for the PSIV. PLT Values and * corresponding bit rate: 0: Symmetric Single (PSI Dword) 1: Reserved 2: Asymmetric Rx (Paired * with Asymmetric Tx PSI Dword) 3: Asymmetric Tx (Immediately follows Rx Asymmetric PSI Dword) */ #define USB3_XECP_PSI_LOW_SPEED_PLT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PLT_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PLT_MASK) #define USB3_XECP_PSI_LOW_SPEED_PFD_MASK (0x100U) #define USB3_XECP_PSI_LOW_SPEED_PFD_SHIFT (8U) /*! PFD - PSI Full-duplex. If this bit is '1' the link is full-duplex, and if '0' the link is half-duplex */ #define USB3_XECP_PSI_LOW_SPEED_PFD(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PFD_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PFD_MASK) #define USB3_XECP_PSI_LOW_SPEED_PSIM_MASK (0xFFFF0000U) #define USB3_XECP_PSI_LOW_SPEED_PSIM_SHIFT (16U) /*! PSIM - Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the * PSIE when calculating the maximum bit rate represented by this PSI Dword */ #define USB3_XECP_PSI_LOW_SPEED_PSIM(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PSIM_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PSIM_MASK) /*! @} */ /*! @name XECP_PSI_HIGH_SPEED - Protocol Speed ID */ /*! @{ */ #define USB3_XECP_PSI_HIGH_SPEED_PSIV_MASK (0xFU) #define USB3_XECP_PSI_HIGH_SPEED_PSIV_SHIFT (0U) /*! PSIV - Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by * this PSI Dword, then the value of this field shall be reported in the Port Speed field of * PORTSC register (5.4.8 of xHCI specification) of a compatible port. Note, the PSIV value of 0 is * reserved and shall not be defined by a PSI */ #define USB3_XECP_PSI_HIGH_SPEED_PSIV(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PSIV_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PSIV_MASK) #define USB3_XECP_PSI_HIGH_SPEED_PSIE_MASK (0x30U) #define USB3_XECP_PSI_HIGH_SPEED_PSIE_SHIFT (4U) /*! PSIE - Protocol Speed ID Exponent. This field defines the base 10 exponent times 3, that shall * be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented * by this PSI Dword. PSIE Values and corresponding bit rates: 0: Bits per second 1: Kb/s 2: Mb/s * 3: Gb/s */ #define USB3_XECP_PSI_HIGH_SPEED_PSIE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PSIE_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PSIE_MASK) #define USB3_XECP_PSI_HIGH_SPEED_PLT_MASK (0xC0U) #define USB3_XECP_PSI_HIGH_SPEED_PLT_SHIFT (6U) /*! PLT - PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric * bit rate, and if asymmetric, then this field also indicates if this Dword defines the receive or * transmit bit rate. Note that the Asymmetric PSI Dwords shall be paired, i.e. an Rx * immediately followed by a Tx, and both Dwords shall define the same value for the PSIV. PLT Values and * corresponding bit rate: 0: Symmetric Single (PSI Dword) 1: Reserved 2: Asymmetric Rx (Paired * with Asymmetric Tx PSI Dword) 3: Asymmetric Tx (Immediately follows Rx Asymmetric PSI Dword) */ #define USB3_XECP_PSI_HIGH_SPEED_PLT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PLT_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PLT_MASK) #define USB3_XECP_PSI_HIGH_SPEED_PFD_MASK (0x100U) #define USB3_XECP_PSI_HIGH_SPEED_PFD_SHIFT (8U) /*! PFD - PSI Full-duplex. If this bit is '1' the link is full-duplex, and if '0' the link is half-duplex */ #define USB3_XECP_PSI_HIGH_SPEED_PFD(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PFD_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PFD_MASK) #define USB3_XECP_PSI_HIGH_SPEED_PSIM_MASK (0xFFFF0000U) #define USB3_XECP_PSI_HIGH_SPEED_PSIM_SHIFT (16U) /*! PSIM - Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the * PSIE when calculating the maximum bit rate represented by this PSI Dword */ #define USB3_XECP_PSI_HIGH_SPEED_PSIM(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PSIM_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PSIM_MASK) /*! @} */ /*! @name XECP_SUPP_USB3_CAP0 - xHCI Supported Protocol Capability */ /*! @{ */ #define USB3_XECP_SUPP_USB3_CAP0_PID_MASK (0xFFU) #define USB3_XECP_SUPP_USB3_CAP0_PID_SHIFT (0U) /*! PID - Capability ID. The value identifies the capability as Supported Protocol */ #define USB3_XECP_SUPP_USB3_CAP0_PID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_PID_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_PID_MASK) #define USB3_XECP_SUPP_USB3_CAP0_NextCapID_MASK (0xFF00U) #define USB3_XECP_SUPP_USB3_CAP0_NextCapID_SHIFT (8U) /*! NextCapID - This field indicates the location of the next capability with respect to the * effective address of this capability. Refer to Table 142 of xHCI specification for more information * on this field */ #define USB3_XECP_SUPP_USB3_CAP0_NextCapID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_NextCapID_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_NextCapID_MASK) #define USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_MASK (0xFF0000U) #define USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_SHIFT (16U) /*! Minor_Rev - Minor Specification Release Number in Binary-Coded Decimal (i.e.,version x.10 is * 10h). This field identifies the minor release number component of the specification with which * the xHC is compliant */ #define USB3_XECP_SUPP_USB3_CAP0_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_MASK) #define USB3_XECP_SUPP_USB3_CAP0_Major_Rev_MASK (0xFF000000U) #define USB3_XECP_SUPP_USB3_CAP0_Major_Rev_SHIFT (24U) /*! Major_Rev - Major Specification Release Number in Binary-Coded Decimal (i.e.,version 3.x is * 03h). This field identifies the major release number component of the specification with which the * xHC is compliant */ #define USB3_XECP_SUPP_USB3_CAP0_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_Major_Rev_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_Major_Rev_MASK) /*! @} */ /*! @name XECP_SUPP_USB3_CAP1 - xHCI Supported Protocol Capability */ /*! @{ */ #define USB3_XECP_SUPP_USB3_CAP1_USB_STRING_MASK (0xFFFFFFFFU) #define USB3_XECP_SUPP_USB3_CAP1_USB_STRING_SHIFT (0U) /*! USB_STRING - Name String, RO. This field is a mnemonic name string that references the * specification with which the xHC is compliant. Four ASCII characters may be defined. Allowed characters * are: alphanumeric, space, and underscore. Alpha characters are case sensitive. Refer to * section 7.2.2 of xHCI specification for defined values */ #define USB3_XECP_SUPP_USB3_CAP1_USB_STRING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP1_USB_STRING_SHIFT)) & USB3_XECP_SUPP_USB3_CAP1_USB_STRING_MASK) /*! @} */ /*! @name XECP_SUPP_USB3_CAP2 - xHCI Supported Protocol Capability; USB 3 */ /*! @{ */ #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_MASK (0xFFU) #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_SHIFT (0U) /*! Compatible_Port_Offset - This field specifies the starting Port Number of Root Hub Ports that * support this protocol. Valid values are 1 to MaxPorts */ #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_SHIFT)) & USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_MASK) #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_MASK (0xFF00U) #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_SHIFT (8U) /*! Compatible_Port_Count - This field identifies the number of consecutive Root Hub Ports (starting * at the Compatible Port Offset) that support this protocol. Valid values are 1 to MaxPorts */ #define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_SHIFT)) & USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_MASK) #define USB3_XECP_SUPP_USB3_CAP2_PSIC_MASK (0xF0000000U) #define USB3_XECP_SUPP_USB3_CAP2_PSIC_SHIFT (28U) /*! PSIC - Protocol Speed ID CountCount : 1, USB 3.0 Speed (Super Speed). This field indicates the * number of Protocol Speed ID (PSI) Dwords that the xHCI Supported Protocol Capability data * structure contains. If this field is non-zero, then all speeds supported by the protocol shall be * defined using PSI Dwords, i.e. no implied Speed ID mappings apply */ #define USB3_XECP_SUPP_USB3_CAP2_PSIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP2_PSIC_SHIFT)) & USB3_XECP_SUPP_USB3_CAP2_PSIC_MASK) /*! @} */ /*! @name XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE - Protocol Slot Type */ /*! @{ */ #define USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_MASK (0x1FU) #define USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_SHIFT (0U) /*! PST - This field specifies the Protocol Slot Type value, which may be specified when allocating * Device Slots that support this protocol. Valid values are 0 to 31. Refer to sections 4.6.3 and * 7.2.2.1.4 of xHCI specification. The value of the Protocol Slot Type field declared by a xHCI * Supported Protocol Capability structure is unique to an xHC implementation. Software shall * not assume a fixed mapping of the Protocol Slot Type value to a specific type of Supported * Protocol. Note that for compatibility reasons, the Protocol Slot Type value of 0 is the exception * to this rule and reserved for the USB Protocol Device Slot type */ #define USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_SHIFT)) & USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_MASK) /*! @} */ /*! @name PSI_SUPER_SPEED - Protocol Speed ID */ /*! @{ */ #define USB3_PSI_SUPER_SPEED_PSIV_MASK (0xFU) #define USB3_PSI_SUPER_SPEED_PSIV_SHIFT (0U) /*! PSIV - Protocol Speed ID Value. If a device is attached that operates at the bit rate defined by * this PSI Dword, then the value of this field shall be reported in the Port Speed field of * PORTSC register (5.4.8 of xHCI specification) of a compatible port. Note, the PSIV value of 0 is * reserved and shall not be defined by a PSI */ #define USB3_PSI_SUPER_SPEED_PSIV(x) (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PSIV_SHIFT)) & USB3_PSI_SUPER_SPEED_PSIV_MASK) #define USB3_PSI_SUPER_SPEED_PSIE_MASK (0x30U) #define USB3_PSI_SUPER_SPEED_PSIE_SHIFT (4U) /*! PSIE - Protocol Speed ID Exponent. This field defines the base 10 exponent times 3, that shall * be applied to the Protocol Speed ID Mantissa when calculating the maximum bit rate represented * by this PSI Dword. PSIE Values and corresponding bit rates: 0: Bits per second 1: Kb/s 2: Mb/s * 3: Gb/s */ #define USB3_PSI_SUPER_SPEED_PSIE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PSIE_SHIFT)) & USB3_PSI_SUPER_SPEED_PSIE_MASK) #define USB3_PSI_SUPER_SPEED_PLT_MASK (0xC0U) #define USB3_PSI_SUPER_SPEED_PLT_SHIFT (6U) /*! PLT - PSI Type. This field identifies whether the PSI Dword defines a symmetric or asymmetric * bit rate, and if asymmetric, then this field also indicates if this Dword defines the receive or * transmit bit rate. Note that the Asymmetric PSI Dwords shall be paired, i.e. an Rx * immediately followed by a Tx, and both Dwords shall define the same value for the PSIV. PLT Values and * corresponding bit rate: 0: Symmetric Single (PSI Dword) 1: Reserved 2: Asymmetric Rx (Paired * with Asymmetric Tx PSI Dword) 3: Asymmetric Tx (Immediately follows Rx Asymmetric PSI Dword) */ #define USB3_PSI_SUPER_SPEED_PLT(x) (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PLT_SHIFT)) & USB3_PSI_SUPER_SPEED_PLT_MASK) #define USB3_PSI_SUPER_SPEED_PFD_MASK (0x100U) #define USB3_PSI_SUPER_SPEED_PFD_SHIFT (8U) /*! PFD - PSI Full-duplex. If this bit is '1' the link is full-duplex, and if '0' the link is half-duplex */ #define USB3_PSI_SUPER_SPEED_PFD(x) (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PFD_SHIFT)) & USB3_PSI_SUPER_SPEED_PFD_MASK) #define USB3_PSI_SUPER_SPEED_PSIM_MASK (0xFFFF0000U) #define USB3_PSI_SUPER_SPEED_PSIM_SHIFT (16U) /*! PSIM - Protocol Speed ID Mantissa. This field defines the mantissa that shall be applied to the * PSIE when calculating the maximum bit rate represented by this PSI Dword */ #define USB3_PSI_SUPER_SPEED_PSIM(x) (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PSIM_SHIFT)) & USB3_PSI_SUPER_SPEED_PSIM_MASK) /*! @} */ /*! @name XECP_CMDM_STS0 - Command Ring related status */ /*! @{ */ #define USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_MASK (0xFFU) #define USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_SHIFT (0U) /*! VEND_DEF_CMDM_CAP_ID_193 - Vendor defined capability ID. Command Ring Manager capability ID */ #define USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_SHIFT)) & USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_MASK) #define USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_MASK (0xFF00U) #define USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_SHIFT (8U) /*! XECP_CMDM_NEXT_CAP_OFFSET - Next capability offset */ #define USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_SHIFT)) & USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_MASK) #define USB3_XECP_CMDM_STS0_cmd_running_MASK (0x10000U) #define USB3_XECP_CMDM_STS0_cmd_running_SHIFT (16U) /*! cmd_running - Indicates that the command ring is running */ #define USB3_XECP_CMDM_STS0_cmd_running(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmd_running_SHIFT)) & USB3_XECP_CMDM_STS0_cmd_running_MASK) #define USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_MASK (0x20000U) #define USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_SHIFT (17U) /*! host_cmd_db_rang_sticky - Indicates that command ring has a doorbell pending */ #define USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_SHIFT)) & USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_MASK) #define USB3_XECP_CMDM_STS0_stopping_cmd_ring_MASK (0x40000U) #define USB3_XECP_CMDM_STS0_stopping_cmd_ring_SHIFT (18U) /*! stopping_cmd_ring - Indicates that a STOP on the Command Ring is in progress */ #define USB3_XECP_CMDM_STS0_stopping_cmd_ring(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_stopping_cmd_ring_SHIFT)) & USB3_XECP_CMDM_STS0_stopping_cmd_ring_MASK) #define USB3_XECP_CMDM_STS0_trm_stall_req_MASK (0x100000U) #define USB3_XECP_CMDM_STS0_trm_stall_req_SHIFT (20U) /*! trm_stall_req - Indicates that transfer ring manager is issuing and EP state update due to stall received */ #define USB3_XECP_CMDM_STS0_trm_stall_req(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_trm_stall_req_SHIFT)) & USB3_XECP_CMDM_STS0_trm_stall_req_MASK) #define USB3_XECP_CMDM_STS0_trm_eperr_upd_req_MASK (0x200000U) #define USB3_XECP_CMDM_STS0_trm_eperr_upd_req_SHIFT (21U) /*! trm_eperr_upd_req - Indicates that Transfer Ring Manager is issuing and EP update due to an EP error condition detected */ #define USB3_XECP_CMDM_STS0_trm_eperr_upd_req(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_trm_eperr_upd_req_SHIFT)) & USB3_XECP_CMDM_STS0_trm_eperr_upd_req_MASK) #define USB3_XECP_CMDM_STS0_dbm_ep_upd_req_MASK (0x400000U) #define USB3_XECP_CMDM_STS0_dbm_ep_upd_req_SHIFT (22U) /*! dbm_ep_upd_req - Indicates that Doorbell Manager is issuing and EP update due to a doorbell ring on an EP that is in stop state */ #define USB3_XECP_CMDM_STS0_dbm_ep_upd_req(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_dbm_ep_upd_req_SHIFT)) & USB3_XECP_CMDM_STS0_dbm_ep_upd_req_MASK) #define USB3_XECP_CMDM_STS0_update_endpt_active_MASK (0x800000U) #define USB3_XECP_CMDM_STS0_update_endpt_active_SHIFT (23U) /*! update_endpt_active - Indicates that updating of EP state is in progress */ #define USB3_XECP_CMDM_STS0_update_endpt_active(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_update_endpt_active_SHIFT)) & USB3_XECP_CMDM_STS0_update_endpt_active_MASK) #define USB3_XECP_CMDM_STS0_odma_address_dev_pending_MASK (0x1000000U) #define USB3_XECP_CMDM_STS0_odma_address_dev_pending_SHIFT (24U) /*! odma_address_dev_pending - Indicates that ODMA has an address device command in progress */ #define USB3_XECP_CMDM_STS0_odma_address_dev_pending(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_odma_address_dev_pending_SHIFT)) & USB3_XECP_CMDM_STS0_odma_address_dev_pending_MASK) #define USB3_XECP_CMDM_STS0_odma_address_dev_done_MASK (0x2000000U) #define USB3_XECP_CMDM_STS0_odma_address_dev_done_SHIFT (25U) /*! odma_address_dev_done - Indicates that current address device command is done by ODMA */ #define USB3_XECP_CMDM_STS0_odma_address_dev_done(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_odma_address_dev_done_SHIFT)) & USB3_XECP_CMDM_STS0_odma_address_dev_done_MASK) #define USB3_XECP_CMDM_STS0_cmdm_clr_db_req_MASK (0x4000000U) #define USB3_XECP_CMDM_STS0_cmdm_clr_db_req_SHIFT (26U) /*! cmdm_clr_db_req - Indicates that clearing an EP out of schedule is in progress */ #define USB3_XECP_CMDM_STS0_cmdm_clr_db_req(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmdm_clr_db_req_SHIFT)) & USB3_XECP_CMDM_STS0_cmdm_clr_db_req_MASK) #define USB3_XECP_CMDM_STS0_cmdm_stop_req_MASK (0x8000000U) #define USB3_XECP_CMDM_STS0_cmdm_stop_req_SHIFT (27U) /*! cmdm_stop_req - Indicates that Command Ring stop command is in progress */ #define USB3_XECP_CMDM_STS0_cmdm_stop_req(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmdm_stop_req_SHIFT)) & USB3_XECP_CMDM_STS0_cmdm_stop_req_MASK) #define USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_MASK (0x10000000U) #define USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_SHIFT (28U) /*! cmdm_cntx_lock_req - Indicates that Command Manager has requested a context lock */ #define USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_SHIFT)) & USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_MASK) #define USB3_XECP_CMDM_STS0_trm_cntx_in_use_MASK (0x20000000U) #define USB3_XECP_CMDM_STS0_trm_cntx_in_use_SHIFT (29U) /*! trm_cntx_in_use - Indicates that TRM modules owns the context access currently */ #define USB3_XECP_CMDM_STS0_trm_cntx_in_use(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_trm_cntx_in_use_SHIFT)) & USB3_XECP_CMDM_STS0_trm_cntx_in_use_MASK) #define USB3_XECP_CMDM_STS0_odma_cntx_in_use_MASK (0x40000000U) #define USB3_XECP_CMDM_STS0_odma_cntx_in_use_SHIFT (30U) /*! odma_cntx_in_use - Indicates that ODMA module currently owns currently the context access */ #define USB3_XECP_CMDM_STS0_odma_cntx_in_use(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_odma_cntx_in_use_SHIFT)) & USB3_XECP_CMDM_STS0_odma_cntx_in_use_MASK) #define USB3_XECP_CMDM_STS0_idma_cntx_in_use_MASK (0x80000000U) #define USB3_XECP_CMDM_STS0_idma_cntx_in_use_SHIFT (31U) /*! idma_cntx_in_use - Indicates that IDMA module currently owns the context access : */ #define USB3_XECP_CMDM_STS0_idma_cntx_in_use(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_idma_cntx_in_use_SHIFT)) & USB3_XECP_CMDM_STS0_idma_cntx_in_use_MASK) /*! @} */ /*! @name XECP_CMDM_CTRL_REG1 - Command Manager Control */ /*! @{ */ #define USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_MASK (0x1U) #define USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_SHIFT (0U) /*! update_endpt_event_enable - '0': Disable generation of the completion event. '1': Enable the * command manager to generate a completion event after an EP state update due to internal error. * This bit is for test debug */ #define USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_MASK) #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_MASK (0x2U) #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_SHIFT (1U) /*! force_bandwidth_fail - '0': Bandwidth calculation handled normally. '1': Forces a failure in the * endpoint bandwidth calculation so that engine will reject a configure EP command */ #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_MASK (0x4U) #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_SHIFT (2U) /*! clr_cntx_4setdqptr - '0': Disable clearing internal TRM and DMA context during a set TR DQ * pointer command. '1': Enable clearing internal TRM and DMA context during a set TR DQ pointer * command */ #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_MASK) #define USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_MASK (0x8U) #define USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_SHIFT (3U) /*! addr_dev_slst_bsr_check_en - '0': Address device does not return the error for this condition. * '1': Enable the EP state (default state) check with address device command with BSR. If failed, * an event with context state error will be generated */ #define USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_MASK (0x10U) #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_SHIFT (4U) /*! clr_cntx_4rstdev - '0': Disable clearing internal TRM and DMA context during a reset device * command. '1': Enable clearing internal TRM and DMA context during a reset device command */ #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_MASK (0x20U) #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_SHIFT (5U) /*! clr_cntx_4enslot_reg - '0': Disable clearing internal TRM and DMA context during an enable slot * command. '1': Enable clearing internal TRM and DMA context during an enable slot command */ #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_MASK (0x40U) #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_SHIFT (6U) /*! clr_cntx_4enaddr - '0': Disable clearing internal TRM and DMA context during an address device * command. '1': Enable clearing internal TRM and DMA context during an address device command */ #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_MASK (0x80U) #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_SHIFT (7U) /*! clr_cntx_4encfgendpt - '0': Disable clearing internal TRM and DMA context during a configure * endpoint command. '1': Enable clearing internal TRM and DMA context during a configure endpoint * command */ #define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_MASK (0x100U) #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_SHIFT (8U) /*! clr_ep_cntx_4en_slot - '0': Disable clearing other internal EP status signals during an enable * slot command. '1': Enable clearing other internal EP related status signals such as EP * scheduled array, credit stored per EP. etc., during an enable slot command */ #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_MASK (0x200U) #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_SHIFT (9U) /*! clr_ep_cntx_4rst_endpt - '0': Disable clearing other internal EP status signals during a reset * endpoint command. '1': Enable clearing other internal EP related status signals such as EP * scheduled array, credit stored per EP. etc. during a reset endpoint command */ #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_MASK (0x400U) #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_SHIFT (10U) /*! clr_ep_cntx_4rst_device - '0': Disable clearing other internal EP status signals during a reset * device command. '1': Enable clearing other internal EP related status signals such as EP * scheduled array, credit stored per EP, etc. during a reset device command */ #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_MASK (0x800U) #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_SHIFT (11U) /*! clr_ep_cntx_4cfg_endpt - '0': Disable clearing other internal EP status signals during a * configure endpoint command. '1': Enable clearing other internal EP related status signals such as EP * scheduled array, credit stored per EP, etc. during a configure endpoint command */ #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_MASK) #define USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_MASK (0x1000U) #define USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_SHIFT (12U) /*! glob_tsp_en - '0': Disable the global context preservation. '1': Enable the internal context * preservation for all commands that needs to preserve some of the internal context fields as a * command with TSP would */ #define USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_MASK) #define USB3_XECP_CMDM_CTRL_REG1_init_retry_MASK (0x2000U) #define USB3_XECP_CMDM_CTRL_REG1_init_retry_SHIFT (13U) /*! init_retry - init_retry. Reserved to always read value of '1' */ #define USB3_XECP_CMDM_CTRL_REG1_init_retry(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_init_retry_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_init_retry_MASK) #define USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_MASK (0x4000U) #define USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_SHIFT (14U) /*! eval_epst_check_en - '0': Disable evaluating the endpoint state during an Evaluate Context * command, '1': Enable EP state check during an Evaluate Context command. If failed, context error * will be returned */ #define USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_MASK (0x8000U) #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_SHIFT (15U) /*! clr_ep_cntx_4dis_slot - '0': Disable clearing internal TRM and DMA context as well as the * internal EP status signals during a disable slot command. '1': Enable clearing internal TRM and DMA * context as well as the internal EP status signals during a disable slot command */ #define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_MASK) #define USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_MASK (0x10000U) #define USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_SHIFT (16U) /*! clr_split_state_with_tspset - This bit allows engine to reset the split states when reset * endpoint with TSP is posted. The split state is an internal context field in DMA engine. '0': * Indicates that reset endpoint with TSP will preserve the split state. '1': Indicates that the reset * endpoint with TSP will not preserve the split state */ #define USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_MASK) #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_MASK (0x20000U) #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_SHIFT (17U) /*! force_bandwidth_pass - force_bandwidth_pass */ #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_MASK) #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_MASK (0x40000U) #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_SHIFT (18U) /*! force_bandwidth_sys_pass - force_bandwidth_sys_pass */ #define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_MASK) #define USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_MASK (0x80000U) #define USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_SHIFT (19U) /*! report_bandwidth_skip_scan - report_bandwidth_skip_scan */ #define USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_MASK) #define USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_MASK (0x100000U) #define USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_SHIFT (20U) /*! enable_max_ep_cache - enable_max_ep_cache */ #define USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_MASK) #define USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_MASK (0x200000U) #define USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_SHIFT (21U) /*! cfg_endpt_cntx_lock_dis - Context lock mechanism to ensure command manager has exclusive access * to internal context. This is a disable bit to allow software to turn off the context lock for * configure endpoint command. This is a test/debug feature. '1': indicates disabled. '0': * Indicates enabled */ #define USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_MASK) #define USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_MASK (0x400000U) #define USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_SHIFT (22U) /*! feature_retry_en - Enable the EOB and NPKT==0 (called NYET condition for USB3) to be used to * update a retry bit during stream switching operation. This is an internal safety feature. It * should be treated as reserved bit */ #define USB3_XECP_CMDM_CTRL_REG1_feature_retry_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_MASK) #define USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_MASK (0x800000U) #define USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_SHIFT (23U) /*! eval_cntx_bw_scan_en - Enable the Host Controller's Bandwidth checks for the Evaluate Context Command. Rescan the BW during evaluate context */ #define USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_MASK) #define USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_MASK (0xF000000U) #define USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_SHIFT (24U) /*! default_isoch_ep_bandwidth - Bandwidth calculation parameter: Default bandwidth for an Isochronous Endpoint */ #define USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_MASK) #define USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_MASK (0xF0000000U) #define USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_SHIFT (28U) /*! default_intr_ep_bandwidth - Bandwidth calculation parameter: Default bandwidth for an Interrupt Endpoint */ #define USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_MASK) /*! @} */ /*! @name XECP_CMDM_CTRL_REG2 - Command Manager Control */ /*! @{ */ #define USB3_XECP_CMDM_CTRL_REG2_clr_st_MASK (0x3FFFU) #define USB3_XECP_CMDM_CTRL_REG2_clr_st_SHIFT (0U) /*! clr_st - Clear state machine present state: Setting a specified bit to '1', will reset the * corresponding command manager state machine to the starting/idle state. bit-0: disable slot state * machine; bit-1: enable slot state machine; bit-2: reset endpoint state machine; bit-3: reset * device state machine; bit-4: command ring state machine; bit-5: stop endpoint state machine; * bit-6: set dq pointer state machine; bit-7: force header state machine; bit-8: evaluate context * state machine; bit-9: update endpoint state machine; bit-10: address device state machine; * bit-11: port bandwidth state machine; bit-12: read output context state machine; bit-13: configure * endpoint state machine; */ #define USB3_XECP_CMDM_CTRL_REG2_clr_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_st_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_st_MASK) #define USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_MASK (0x4000U) #define USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_SHIFT (14U) /*! burst_size_default_en - When context is first initialized, it is assumed one remote NPKT. It is * also assumed that max burst size as remote NPKT. This bit enables to assume max burst size as * remote NPKT. '0': Assume 1 NPKT. '1': Assume max burst size as NPKT */ #define USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_MASK) #define USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_MASK (0x8000U) #define USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_SHIFT (15U) /*! disable_stall_clr_ep - '0': Stall handling does clear the internal EP status signals. '1': * Disable the clear function when stall response received */ #define USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_MASK) #define USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_MASK (0x10000U) #define USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_SHIFT (16U) /*! increase_update_ep_priority_en - Increase Update EP priority over commands in the command ring * to avoid prolonging STALL handling. '0': Pending commands have a higher priority than update * endpoint processing. '1': Update endpoint processing in the command manager has a higher * priority than pending commands. Note: Enabling this bit can prevent prolonged stall handling */ #define USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_MASK) #define USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_MASK (0x20000U) #define USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_SHIFT (17U) /*! trm_break_loop_en - trm_break_loop_en. This is an internal safeguard register. It enables a * different mechanism of handling stop endpoint command. It should be treated as a reserved field. * The default should not be alternate unless specific purpose. '0': Disable. '1': Enable */ #define USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_MASK) #define USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_MASK (0x40000U) #define USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_SHIFT (18U) /*! tsp_4set_dqptr_reg - '0': Disable sequence number preservation during set DQ pointer command. * '1': Enable sequence number to be preserved during set DQ pointer command */ #define USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_MASK) #define USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_MASK (0x80000U) #define USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_SHIFT (19U) /*! force_reset_endpt_reg - '0': Check the slot and endpoint state prior to processing a reset * endpoint command. '1': Ignore the slot and endpoint state when processing a reset endpoint command */ #define USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_MASK) #define USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_MASK (0x100000U) #define USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_SHIFT (20U) /*! set_dqptr_clr_ep_arys - '0': Disable clearing other internal EP status signals during a set DQ * pointer command. '1': Enable clearing other internal EP status signals during a set DQ pointer * command */ #define USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_MASK) #define USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_MASK (0x200000U) #define USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_SHIFT (21U) /*! cmd_st_dis_reg - '0': Delay processing command ring TRB while internal context requests are * pending. '1': Process command ring TRBs normally */ #define USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_MASK) #define USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_MASK (0x400000U) #define USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_SHIFT (22U) /*! enable_bw_cal - '0': Disable hardware bandwidth calculations. '1': Enable hardware bandwidth calculations */ #define USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_MASK) #define USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_MASK (0x800000U) #define USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_SHIFT (23U) /*! clr_cntx_4rst_endpt_reg - '0': Disable clearing internal TRM and DMA context during a reset * endpoint command. '1': Enable clearing internal TRM and DMA context during a reset endpoint command */ #define USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_MASK) #define USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_MASK (0x1000000U) #define USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_SHIFT (24U) /*! move_xfer_dqptr_2cpl_dqptr_en - '0': The internal context write DQ pointer moved to internal * read pointer during reset EP command. '1': The write DQ pointer stays as it was during reset * endpoint command */ #define USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_MASK) #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_MASK (0x2000000U) #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_SHIFT (25U) /*! clr_ep_cntx_4stall_upd - '0': Disable clearing other internal EP status signal during stall * handling. '1': Enable clearing other internal EP status signal during stall handling */ #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_MASK) #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_MASK (0x4000000U) #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_SHIFT (26U) /*! clr_ep_cntx_4stop_endpt - '0': Disable clearing other internal per EP status signal during a * stop endpoint command. '1': Enable clearing other internal per EP status signal during a stop * endpoint command */ #define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_MASK) #define USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_MASK (0x8000000U) #define USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_SHIFT (27U) /*! all_clk_gate_dis - '0': Turn ON the TTE clock. '1': Turn OFF the TTE clock */ #define USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_MASK) #define USB3_XECP_CMDM_CTRL_REG2_SRE_MASK (0x10000000U) #define USB3_XECP_CMDM_CTRL_REG2_SRE_SHIFT (28U) /*! SRE - Force and error on save command always. '0': do not force, '1': always force return save error */ #define USB3_XECP_CMDM_CTRL_REG2_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_SRE_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_SRE_MASK) #define USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_MASK (0x20000000U) #define USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_SHIFT (29U) /*! slot_id_overide_en - Force '0' on slot ID when a command transfer event is generated. '0': not forced, '1': Forced to 0 */ #define USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_MASK) #define USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_MASK (0x40000000U) #define USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_SHIFT (30U) /*! stop_endpt_2ms_timeout_en - Enable a delay to stop endpoint command that is executed in XFER * engine. '0': XFER engine will not wait. '1': XFER engine will always wait for 2 ms before it * checks whether an EP transfer ring is at a stop of packet boundary */ #define USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_MASK) #define USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_MASK (0x80000000U) #define USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_SHIFT (31U) /*! doing_2dw_ocntx_wr_en - Enable only to update the EP state to output context on every EP output * context update condition. This is to allow to have a control over either update the entire * EPoutput context field or only update the first two DWORDs. '0': update the entire output context * field. '1': update only 2 DWORDs */ #define USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_MASK) /*! @} */ /*! @name XECP_CMDM_CTRL_REG3 - Command Manager Control */ /*! @{ */ #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_MASK (0xFFU) #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_SHIFT (0U) /*! DEFAULT_PORT_BANDWD_AVAIL - The default available bandwidth to advertise on each LS, FS, SS port * in 10% increments (90%). Bandwidth calculation is a reserved field for PPT */ #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_MASK) #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_MASK (0xFF00U) #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_SHIFT (8U) /*! DEFAULT_HS_BANDWD_AVAIL - The default available bandwidth to advertise on each HS port in 10% * increments (80%). Bandwidth Calculation is a reserved field for PPT */ #define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_MASK) #define USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_MASK (0x30000U) #define USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_SHIFT (16U) /*! disable_slot_timer_select - These two bits specify the delay that we can have for disable slot * state to be completed. We can delay the generation of the command transfer event during disable * slot command. Possible values: '00': delay is disabled, '01': 100us delay, '10': 8ms delay, * '11': 10ms delay */ #define USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_MASK) #define USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_MASK (0x40000U) #define USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_SHIFT (18U) /*! clr_trm_dma_cntx_en - clr_trm_dma_cntx_en */ #define USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_MASK) #define USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_MASK (0x80000U) #define USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_SHIFT (19U) /*! stop_2timeout_en - stop_2timeout_en. Stop transaction timeout */ #define USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_MASK) #define USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_MASK (0x100000U) #define USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_SHIFT (20U) /*! break_cntx_lock_en - break_cntx_lock_en */ #define USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_MASK) #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_MASK (0x200000U) #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_SHIFT (21U) /*! stop_ep_clr_stream_st_en - stop_ep_clr_stream_st_en. Enable stop endpoint command to return stream st to disabled (0) in EP context */ #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_MASK) #define USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_MASK (0x400000U) #define USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_SHIFT (22U) /*! allow_clr_4stop - allow_clr_4stop */ #define USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_MASK) #define USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_MASK (0x800000U) #define USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_SHIFT (23U) /*! stream_always_update_cntx - stream_always_update_cntx */ #define USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_MASK) #define USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_MASK (0x1000000U) #define USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_SHIFT (24U) /*! set_burst_size_4prdc_dis - set_burst_size_4prdc_dis */ #define USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_MASK) #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_MASK (0x2000000U) #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_SHIFT (25U) /*! stop_ep_clr_lcstream_id_en - stop_ep_clr_lcstream_id_en. Enable stop endpoint command to return stream st to disabled (0) in EP context */ #define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_MASK) #define USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_MASK (0x4000000U) #define USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_SHIFT (26U) /*! update_cntx_when_stopped - update_cntx_when_stopped. Allow setTRDQPtr cmd to update the local * context anytime the EP is not running (otherwise checks CSTREAMID) */ #define USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_MASK) #define USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_MASK (0x8000000U) #define USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_SHIFT (27U) /*! disable_setdqptr_clr_stream_st - disable_setdqptr_clr_stream_st. Disable setTRDQPtr from clearing the current stream state */ #define USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_MASK) #define USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_MASK (0x10000000U) #define USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_SHIFT (28U) /*! disable_non0ep_cntx_clr - disable_non0ep_cntx_clr */ #define USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_MASK) #define USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_MASK (0x20000000U) #define USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_SHIFT (29U) /*! extra_db_rm_4stop_en - extra_db_rm_4stop_en */ #define USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_MASK) #define USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_MASK (0x40000000U) #define USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_SHIFT (30U) /*! ignore_hi_atomic_en - ignore_hi_atomic_en */ #define USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_MASK) #define USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_MASK (0x80000000U) #define USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_SHIFT (31U) /*! frindex_wr_en - MFIndex register write enable. For debug purposes */ #define USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_CAP - Host Control Capability */ /*! @{ */ #define USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_MASK (0xFFU) #define USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_SHIFT (0U) /*! VEND_DEF_HOST_CAP_ID_192 - Capability ID. This field identifies the xHCI Extended capability. * 192-255 are IDs available for vendor specific extensions to the xHCI */ #define USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_SHIFT)) & USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_MASK) #define USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_MASK (0xFF00U) #define USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_SHIFT (8U) /*! XECP_HOST_NEXT_CAP_OFFSET - Next xHCI Extended Capability Pointer. This field points to the xHC * MMIO space offset of the next xHCI extended capability pointer. A value of 00h indicates the * end of the extended capability list. A non-zero value in this register indicates a relative * offset, in Dwords, from this Dword to the beginning of the next extended capability. For example, * assuming an effective address of this data structure is 350h and assuming a pointer value of * 068h, we can calculate the following effective address: 350h + (068h << 2) -> 350h + 1A0h -> * 4F0h */ #define USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_SHIFT)) & USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_MASK) /*! @} */ /*! @name XECP_HOST_CLR_MASK_REG - Override Endpoint Flow Control */ /*! @{ */ #define USB3_XECP_HOST_CLR_MASK_REG_EP_dir_MASK (0x1U) #define USB3_XECP_HOST_CLR_MASK_REG_EP_dir_SHIFT (0U) /*! EP_dir - Indicates the direction of the Endpoint */ #define USB3_XECP_HOST_CLR_MASK_REG_EP_dir(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_MASK_REG_EP_dir_SHIFT)) & USB3_XECP_HOST_CLR_MASK_REG_EP_dir_MASK) #define USB3_XECP_HOST_CLR_MASK_REG_EP_num_MASK (0x1EU) #define USB3_XECP_HOST_CLR_MASK_REG_EP_num_SHIFT (1U) /*! EP_num - Endpoint number */ #define USB3_XECP_HOST_CLR_MASK_REG_EP_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_MASK_REG_EP_num_SHIFT)) & USB3_XECP_HOST_CLR_MASK_REG_EP_num_MASK) #define USB3_XECP_HOST_CLR_MASK_REG_Slot_num_MASK (0x3E0U) #define USB3_XECP_HOST_CLR_MASK_REG_Slot_num_SHIFT (5U) /*! Slot_num - Slot number */ #define USB3_XECP_HOST_CLR_MASK_REG_Slot_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_MASK_REG_Slot_num_SHIFT)) & USB3_XECP_HOST_CLR_MASK_REG_Slot_num_MASK) /*! @} */ /*! @name XECP_HOST_CLR_IN_EP_VALID_REG - Clear Active IN EP ID Control */ /*! @{ */ #define USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_MASK (0xFFFFFFFFU) #define USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_SHIFT (0U) /*! port_num - This field indicates the port number */ #define USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_SHIFT)) & USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_MASK) /*! @} */ /*! @name XECP_HOST_CLR_PMASK_REG - Clear Poll Mask Control */ /*! @{ */ #define USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_MASK (0x1U) #define USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_SHIFT (0U) /*! EP_dir - Indicates the direction of the Endpoint */ #define USB3_XECP_HOST_CLR_PMASK_REG_EP_dir(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_SHIFT)) & USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_MASK) #define USB3_XECP_HOST_CLR_PMASK_REG_EP_num_MASK (0x1EU) #define USB3_XECP_HOST_CLR_PMASK_REG_EP_num_SHIFT (1U) /*! EP_num - Endpoint number */ #define USB3_XECP_HOST_CLR_PMASK_REG_EP_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_PMASK_REG_EP_num_SHIFT)) & USB3_XECP_HOST_CLR_PMASK_REG_EP_num_MASK) #define USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_MASK (0x3E0U) #define USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_SHIFT (5U) /*! Slot_num - Slot number */ #define USB3_XECP_HOST_CLR_PMASK_REG_Slot_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_SHIFT)) & USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_OCRD_REG - Port Credit Control */ /*! @{ */ #define USB3_XECP_HOST_CTRL_OCRD_REG_port_num_MASK (0xFFU) #define USB3_XECP_HOST_CTRL_OCRD_REG_port_num_SHIFT (0U) /*! port_num - port number */ #define USB3_XECP_HOST_CTRL_OCRD_REG_port_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_port_num_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_port_num_MASK) #define USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_MASK (0x4000000U) #define USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_SHIFT (26U) /*! st_upd_reg - Slot state control. st_upd_reg */ #define USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_MASK) #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_MASK (0x8000000U) #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_SHIFT (27U) /*! minus_4rfifo - Indicates whether the subtract command operates on TX FIFO credit or RX FIFO credit */ #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_MASK) #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_MASK (0x10000000U) #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_SHIFT (28U) /*! minus_ocrd - Subtract one credit from a port */ #define USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_MASK) #define USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_MASK (0x20000000U) #define USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_SHIFT (29U) /*! plus_ocrd - Add one credit to a port */ #define USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_MASK) #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_MASK (0x40000000U) #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_SHIFT (30U) /*! clr_cpl_st - Write '1' to force CPL state return to IDLE */ #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_MASK) #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_MASK (0x80000000U) #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_SHIFT (31U) /*! clr_xfer_st - Write '1' to force XFER state return to IDLE */ #define USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_TEST_BUS_LO - Test Bus Low */ /*! @{ */ #define USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_MASK (0xFFFFFFFFU) #define USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_SHIFT (0U) /*! TEST_BUS_LO - Host controller test bus low 32-bits. */ #define USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_SHIFT)) & USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_TEST_BUS_HI - Test Bus High */ /*! @{ */ #define USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_MASK (0xFFFFFFFFU) #define USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_SHIFT (0U) /*! TEST_BUS_HI - Host controller test bus high 32-bits */ #define USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_SHIFT)) & USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_TRM_REG1 - Host Control Transfer Manager */ /*! @{ */ #define USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_MASK (0x1U) #define USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_SHIFT (0U) /*! in_td_pace_enable - '0': Disable TD pacing for IN endpoint. '1': Enable TD pacing for IN endpoints */ #define USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_MASK (0x2U) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_SHIFT (1U) /*! disable_fc_4inrdy - '0': Obey the NPKT0 and EOB flow control. '1': Ignore received flow control * for implied NRDY (e.g EOB or NPKT=0) for USB3 only */ #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_MASK (0x4U) #define USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_SHIFT (2U) /*! link_nop_sucess_en - '0': Process transaction errors due to CERR count reached or transaction * timeout reported by the DMA engine. '1': Ignore transaction errors reported by the DMA engine */ #define USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_MASK (0x8U) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_SHIFT (3U) /*! disable_stall - '0': Process stalls reported by the DMA engine. '1': Ignore stall response received reported by the DMA engine */ #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_MASK (0x10U) #define USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_SHIFT (4U) /*! xport_crd_disable - This bit is designed to allow XFER engine to do a transfer without checking * against the available port credit. '0': Advertises accurate buffer credit information to the * scheduler. '1': Advertises non-zero buffer credits to the scheduler (e.g. never backpressure * back on buffer credit information) */ #define USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_MASK (0x20U) #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_SHIFT (5U) /*! cpl_pkt_clr_mask_en - Enable a function, which clears a mask of an EP on any response of that * EP. '0': Clear the scheduler mask normally, '1': Clear the scheduler mask on each received packet */ #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_MASK (0x40U) #define USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_SHIFT (6U) /*! en_bb_port_disable - '0': Babble errors will not disable the port. '1': Babble errors will * disable the auto detect function This will allow engine to handle more than 4 TRBs per packet */ #define USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_MASK (0x80U) #define USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_SHIFT (7U) /*! npkt0_fc_disable - '0': USB3 responses with NumPkts equal to 0 will be treated as a flow control * condition. '1': USB3 responses with NumPkts equal to 0 will not be treated as a flow control * condition */ #define USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_MASK (0x100U) #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_SHIFT (8U) /*! trb_cache_invalide_en - '0': Disable internal TRB cache invalidation. '1': Enable internal TRB * cache invalidation auto detect function. This will allow engine to handle more than 4 TRBs per * packet */ #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_MASK (0x200U) #define USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_SHIFT (9U) /*! in_npkt_pace_disable - Setting this bit to '1' will force the transfer engine state machine to * exit the CPL_WAIT state. This is designed to avoid unexpected deadlock in CPL_WAIT state */ #define USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_MASK (0x400U) #define USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_SHIFT (10U) /*! flush_2clr_valid_en - This bit is modified to support PPTB0, LPT and CP for a feature that we * will clear the single IN EP array based on ISO flush or short flush. '0': Indicate that we do * not need to clear IN EP array based on flush conditions. '1': indicate that we do clear IN EP * array based on flush conditions */ #define USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_MASK (0x800U) #define USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_SHIFT (11U) /*! ctrl_reg_clr_bndry - Setting this bit to '1' will force the transfer engine to set the packet * boundary flag. This flag is an important flag, which may cause a deadlock. This is a safety * feature that we have plugged in */ #define USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_MASK (0x1000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_SHIFT (12U) /*! ENT_en - '0': ENT bit is ignored. '1': ENT bit is processed. The transfer engine will service the next TRB */ #define USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_MASK (0x2000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_SHIFT (13U) /*! single_burst_en - '0': Bulk and interrupt endpoints use burst size defined by endpoint context. * '1: Force the Bulk and Interrupt endpoints to use a burst size of 1 */ #define USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_MASK (0x4000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_SHIFT (14U) /*! xfer_block_en - Not used. XFER engine has a new function that provides a support to ISO EP * within a long PCIe delayed system. The long delay can cause missing service interval while pending * response has not all been returned. This bit enables engine to identify a MSI condition and * store the context bit for a pending response so that we can process a MSI event when pending * response received. '0': disable this function, '1': enable this function */ #define USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_MASK (0x8000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_SHIFT (15U) /*! iso_0len_lpf_en - Enables a special internal state branch condition for periodic EP during its * transfer ring process. If we have identified that the next TRB is a non DMAnable TRB such as * LINK TRB, or Event data TRB, then this bit enables XFER engine to continue process the next TRB * as if the ENT bit of the TRB is set. '0': disable, '1': enable */ #define USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_MASK (0x10000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_SHIFT (16U) /*! set_addr_err_en - '0': Disable error reporting if a SETUP TRB contains the following: bRequest = * SET_ADDRES, bmRequestType = (DTD) Host-to-device, Type = Standard, Recipient = Device. '1': * Enable error reporting for this case */ #define USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_MASK (0x20000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_SHIFT (17U) /*! phase1_imd_en - Enable a special branch condition of the XFER ring process state. This is to * ensure that we have a DMA request issued to DMA engine during a PHASE1 process of the TTE. '0': * disabled, '1': enabled */ #define USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_MASK (0x40000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_SHIFT (18U) /*! no_op_as_td - This bit is modified to enable the NO_OP TRB as a TD when Missing Service Interval * Error has encountered. This is only for PPT B0, LPT and CB. '0': disable, '1': enable */ #define USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_MASK (0x80000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_SHIFT (19U) /*! short_err_4msi_en - This bit is modified to enable a feature where we can control whether or not * to report an event with completion code of Missed Service Error when a short packet response * has been received not in the expected service interval. '0': Disable this function so that the * xHC engine will report an event with completion code of Short packet indication and another * event with MSE at the end of the TD, '1': Enables all completion event that supposedly is short * to the MSE */ #define USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_MASK (0x100000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_SHIFT (20U) /*! deadlock_detect_en - '0': Disable timeout of TRB error processing. '1': Enable timeout of a TRB * processing in few critical states that possibly have a deadlock for unexpected reason. A * vendor defined completion code is generated in the event of a timeout during TRB processing */ #define USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_MASK (0x200000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_SHIFT (21U) /*! disable_erdy_drop - '0': Drop ERDYs received when not in a flow control state. '1': Do not drop * ERDYs received when not in a flow control state. Note: We typically drop unexpected ERDY */ #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_MASK (0x400000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_SHIFT (22U) /*! cpl_db_rang_en - Setting this bit to '1' will force an internal doorbell ring on the EP that it has received a response */ #define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_MASK (0x800000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_SHIFT (23U) /*! write_erdp_lo - When ERDP register is updated by software, it is expected as an atomic function * since this is a 64-bit register. It is expected, that the ERDP (64-bit register) is updated * together when ERDP high 32 is written. We have this bit designed to ignore the atomic operation * required from software for ERDP low 32 bits. When this bit is set to '1', it will update the * ERDP low 32 bits when software issues a CPU write to the ERDP low 32 bits. '0': not ignore, * '1': ignore atomic operation */ #define USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_MASK (0x1000000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_SHIFT (24U) /*! disable_imd_4nodma - This is a special internal branch condition control in XFER engine which * does the EP transfer ring process. When this bit is set, the XFER will not continue even if the * next TRB is identified as a non DMA TRB. The engine will then wait for the next scheduled * request for this EP. '0': Disable, '1': Enable the branch condition */ #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_MASK (0x2000000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_SHIFT (25U) /*! trb_err_rm_db_en - This is a special internal branch condition control in XFER engine which does * the EP transfer ring process. When this bit is set a retry condition identified by completion * engine will cause XFER engine to stop what it is currently in progress and start over from * IDLE state. '0': Disable, '1': Enable the branch condition */ #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_MASK (0x4000000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_SHIFT (26U) /*! ep_halt_2retry_en - This is a special internal condition enable for CPL engine which it enables * all EP halt conditions detected to cause the proper actions in a response. '0': Disabled, '1': * Enabled. Note: Only default condition of '1' is valid */ #define USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_MASK (0x8000000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_SHIFT (27U) /*! enable_noop_upd - This bit has been modified for its usage since PPT A0. It is used to allow * NO-OP TRB to be treated in a same way as link TRB. In other words, it will update the internal * context when it is fetched while the internal context cache TRB FIFO is empty. '0': Disable the * function, '1': Enable the cache function */ #define USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_MASK (0x10000000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_SHIFT (28U) /*! disable_cpl_sst_ppipe_err - '0': Enable the error check, '1': Disable the error check for prime * PIPE stream state. It will generate a transfer event with prime PIPE error completion code if * an error is detected */ #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_MASK (0x20000000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_SHIFT (29U) /*! disable_cpl_sst_mdata_err - '0': Enable the error check. '1': Disable the error check for Data * Move stream state. It will generate a transfer event with prime PIPE error completion code if * an error is detected */ #define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_MASK (0x40000000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_SHIFT (30U) /*! usb2_nak_auto_detect_reg_en - '0': Disables a special function which detects NAK received and * goes into a single packet pace mode so that we do not burst ahead. '1': Enables a special * function which detects NAK received and goes into a single packet pace mode so that we do not burst * ahead */ #define USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_MASK (0x80000000U) #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_SHIFT (31U) /*! trb_pace_en - Must be set to '0' */ #define USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_SCH_REG1 - Host Control Scheduler */ /*! @{ */ #define USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_MASK (0x1U) #define USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_SHIFT (0U) /*! poll_delay_dis - Host Control Scheduler: Disable poll delay function */ #define USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_MASK (0x2U) #define USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_SHIFT (1U) /*! trm_active_in_ep_valid - Host Control Scheduler: Disable TRM active IN EP valid check function */ #define USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_MASK (0x4U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_SHIFT (2U) /*! sch_2 - Host Control Scheduler: Disable TTE IN overlap */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_MASK (0x8U) #define USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_SHIFT (3U) /*! tte_enable_introut_overlap_stop - Host Control Scheduler: tte_enable_introut_overlap_stop */ #define USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_MASK (0x30U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_SHIFT (4U) /*! sch_sort_pattern - Host Control Scheduler: Search priority. Possible values: '00': Sort by * Interval then ISO over interrupt, '01','10','11': Experimental sort algorithms */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_MASK (0x40U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_SHIFT (6U) /*! sch_async_out_max_perf - Host Control Scheduler: Enable maximal out performance (may cause unfairness or short term starvation) */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_MASK (0x80U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_SHIFT (7U) /*! sch_async_1pkt_perf - Host Control Scheduler: Disable burst limit '1' for async in presence of another port periodic packets */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_MASK (0x100U) #define USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_SHIFT (8U) /*! scratch_pad_en - Command Manager: Enables scratch pad function */ #define USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_MASK (0x600U) #define USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_SHIFT (9U) /*! maxEP - Command Manager: Allow dynamically setting different max EP allowed. The max EP * supported scales with the scratch pad size. This allows driver to allocate small memory sizes if it * needed. 0: 32 EPs, 1: 16 EPs, 2: 8 EPs, 3: 4 EPs */ #define USB3_XECP_HOST_CTRL_SCH_REG1_maxEP(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_MASK (0x1800U) #define USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_SHIFT (11U) /*! cache_size_ctrl - Command Manager: Context cache enable */ #define USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_MASK (0x2000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_SHIFT (13U) /*! TTE_0 - TTE: Disable interrupt complete split limit to 3 micro frames */ #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_MASK (0x4000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_SHIFT (14U) /*! TTE_1 - TTE: Disable checking of missed microframes */ #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_MASK (0x8000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_SHIFT (15U) /*! TTE_2 - TTE: Disable split error request to TRM on unserved interrupt-INs */ #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_MASK (0x30000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_SHIFT (16U) /*! TTE_3 - TTE: Reserved */ #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_MASK (0x40000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_SHIFT (18U) /*! disable_gl_hub_iso_fix - TTE: disable_gl_hub_iso_fix */ #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_MASK (0x80000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_SHIFT (19U) /*! disable_gl_hub_int_fix - TTE: disable_gl_hub_int_fix */ #define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_MASK (0x100000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_SHIFT (20U) /*! TTE_4 - TTE: Reserved */ #define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_MASK (0x200000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_SHIFT (21U) /*! sch_stop_serve_nc - Host Control Scheduler: Enable Stop serving packets to disabled port */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_MASK (0xC00000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_SHIFT (22U) /*! sch_cclk_prdc_done_check - Host Control Scheduler: sch_cclk_prdc_done_check */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_MASK (0x1000000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_SHIFT (24U) /*! sch_async_prdc_cc_dis - Host Control Scheduler: sch_async_prdc_cc_dis */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_MASK (0x2000000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_SHIFT (25U) /*! sch_tt_overlap_all_ins - Host Control Scheduler: sch_tt_overlap_all_ins */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_MASK (0x4000000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_SHIFT (26U) /*! sch_async_1pkt_split_pref - Host Control Scheduler: sch_async_1pkt_split_pref */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_MASK (0x8000000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_SHIFT (27U) /*! sch_block_pending_en - Host Control Scheduler: sch_block_pending_en */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_MASK) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_MASK (0xF0000000U) #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_SHIFT (28U) /*! sch_limit_prdc - Host Control Scheduler: sch_limit_prdc */ #define USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_ODMA_REG - Host Control ODMA */ /*! @{ */ #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_MASK (0x1U) #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_SHIFT (0U) /*! EP_trans_timeout_en - '0': Enables the EP Transaction Timeout Function, '1': Disables the EP Transaction Timeout Function */ #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_MASK (0x6U) #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_SHIFT (1U) /*! EP_trans_timeout_len - Controls the duration of the EP Transaction Timeout (depends on the * settings of EP Transaction Base Timer (bit[12])). Possible values: 0: 64us ([12]=0) or 8ms ([12]=1) * EP Transaction Timeout, 1: 32us ([12]=0) or 4ms ([12]=1) EP Transaction Timeout, 2: 16us * ([12]=0) or 2ms ([12]=1) EP Transaction Timeout, 3: EP Transaction Timer is DISABLED */ #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_MASK (0x8U) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_SHIFT (3U) /*! odma_rd_to_idle - Setting this field generates a pulse that returns the Out DMA Read Finite State Machine into the IDLE state */ #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_MASK (0x10U) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_SHIFT (4U) /*! odma_resp_to_idle - Setting this field generates a pulse that returns the Out DMA Response Finite State Machine into the IDLE state */ #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_MASK (0x20U) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_SHIFT (5U) /*! odma_completion_to_idle - Setting this field generates a pulse that returns the Out DMA Completion Finite State Machine into the IDLE state */ #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_MASK (0x40U) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_SHIFT (6U) /*! odma_set_addr_to_idle - Setting this field generates a pulse that returns the Out DMA Set Address Finite State Machine into the IDLE state */ #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_MASK (0x80U) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_SHIFT (7U) /*! odma_7 - Setting this field generates a pulse that implicitly returns all of the Out DMA ACK credits on all ports */ #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_7(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_MASK (0x100U) #define USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_SHIFT (8U) /*! clear_cntx_locks - Setting this field generates a pulse that clears the ownership of the context * semaphore that is shared between the Out DMA Response and Completion Finite State Machines */ #define USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_MASK (0x200U) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_SHIFT (9U) /*! odma_9 - Setting this field prohibits the Set Address Finite State Machine from being flow * controlled when an ACK with NPKT=0 is received in response to the SETUP DP initiated during * SET_ADDRESS */ #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_9(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_MASK (0x400U) #define USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_SHIFT (10U) /*! ep_timer_tick - Setting this field will disable the EP Transaction Timer function when the * Command Manager is performing a Stop Endpoint Command or when the LTSSM is in Recovery */ #define USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_MASK (0x800U) #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_SHIFT (11U) /*! odma_11 - Setting this field will prohibit the Set Address Finite State Machine Credit Handshake with TTE Logic */ #define USB3_XECP_HOST_CTRL_ODMA_REG_odma_11(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_MASK (0x1000U) #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_SHIFT (12U) /*! EP_base_timer - '0': Employs a 1us EP Transaction Base Timer. Enables a Timeout range from 16us * to 64us '1': Employs a 125us EP Transaction Base Timer. Enables a Timeout range from 2ms to 8ms */ #define USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_MASK (0x2000U) #define USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_SHIFT (13U) /*! ACK_crd_check_en - '0': Disable the ACK credit check function '1': Enable the ACK credit check function that ODMA provides */ #define USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_MASK) #define USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_MASK (0x4000U) #define USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_SHIFT (14U) /*! speed_up_timeout - '0': Disable the speed up transaction timeout function. '1': Enable the * transaction timeout speed up based on no-connect detected on a particular port */ #define USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_IDMA_REG - Host Control IDMA */ /*! @{ */ #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_MASK (0x1U) #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_SHIFT (0U) /*! EP_trans_timeout_en - '0': Enables the EP Transaction Timeout Function, '1': Disables the EP Transaction Timeout Function */ #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_MASK (0x6U) #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_SHIFT (1U) /*! EP_timer_tick - '00': 1us/125us/1ms/4ms EP Timer Tick '01': 2us/250us/2ms/8ms EP Timer Tick * '10': 4us/500us/4ms/16ms EP Timer Tick '11': Disabled EP Timer Tick */ #define USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_MASK (0x8U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_SHIFT (3U) /*! idma_ptr_buf_room_restore_pulse - Setting this field generates a pulse that clears all the Read * and Write Pointers associated with the various DMA Address FIFOs causing them to appear empty */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_MASK (0x10U) #define USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_SHIFT (4U) /*! restore_rdp_credits_pulse - Setting this field generates a pulse that implicitly returns all of the IN DMA Data Packet credits on all ports */ #define USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_MASK (0x20U) #define USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_SHIFT (5U) /*! ack_pst_clr_pulse - Setting this field generates a pulse that returns the IN DMA Acknowledge Finite State Machine into the IDLE state */ #define USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_MASK (0x40U) #define USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_SHIFT (6U) /*! dm_pst_clr_pulse - Setting this field generates a pulse that returns the IN DMA Data Mover Finite State Machine into the IDLE state */ #define USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_MASK (0x80U) #define USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_SHIFT (7U) /*! clear_cntx_locks - Setting this field generates a pulse that clears the ownership of the context * semaphore that is shared between the IN DMA Acknowledge and Data Mover Finite State Machines */ #define USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_MASK (0x100U) #define USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_SHIFT (8U) /*! compliance_iso_enable - Setting this field enables the Compliance Isochronous mode of operation. * It bounds the upper limit on the NPKT field for all ISO Acknowledgments generated from the * Host to the value of 2. */ #define USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_MASK (0x200U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_SHIFT (9U) /*! idma_9 - Setting this field will disable the EP Transaction Timer function when the Command * Manager is performing a Stop Endpoint Command or when the LTSSM is in Recovery */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_9(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_MASK (0x400U) #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_SHIFT (10U) /*! timer_tick0 - '0': Employs a 1us EP Transaction Base Timer. Enables a Timeout range from 16us to * 64us. '1': Employs a 125us EP Transaction Base Timer. Enables a Timeout range from 2ms to 8ms */ #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_MASK (0x800U) #define USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_SHIFT (11U) /*! seq_num_adj_on_nrdy - '0': Enable sequence number adjustment on NRDY received for USB3 when we * are expecting a response. '1': Enable sequence number adjustment on any NRDY received for USB3. */ #define USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_MASK (0x1000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_SHIFT (12U) /*! speed_up_timeout - '0': Disable the speed up transaction timeout function. '1': Enable the * transaction timeout speed up based on no-connect detected on a particular port */ #define USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_MASK (0x2000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_SHIFT (13U) /*! idma_13 - Disable dropping all deferred packets on ISO Endpoints */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_13(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_MASK (0x4000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_SHIFT (14U) /*! idma_14 - Disable drop spurious DP when EP is in flow conrtrol */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_14(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_MASK (0x8000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_SHIFT (15U) /*! idma_15 - Disable drop spurious DP when i_npkt==0 */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_15(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_MASK (0x10000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_SHIFT (16U) /*! idma_ptr_buf_room_set - '0': Default IDMA Pointer Buffer Room to 8 : Requires strobe of * host_ctrl_idma_reg[3](idma_ptr_buf_room_restore_pulse) to take effect, '1': Default IDMA Pointer * Buffer Room to 4 : Requires strobe of host_ctrl_idma_reg[3](idma_ptr_buf_room_restore_pulse) to * take effect */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_MASK (0x20000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_SHIFT (17U) /*! idma_17 - '0': All ACK ACKs are put in the Periodic Header FIFO in XPPE, '1': Only Periodic ACK * ACKs are put in the Periodic Header FIFO in XPPE */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_17(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_MASK (0x40000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_SHIFT (18U) /*! idma_addr_fifo_flush_bit - Flush IDMA Address FIFO strobe */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_MASK (0xF80000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_SHIFT (19U) /*! idma_23_19 - Port Number of Address FIFO to Flush */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_MASK (0x1000000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_SHIFT (24U) /*! idma_24 - '0': Flush an Async Address FIFO, '1': Flush a Periodic Address FIFO */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_24(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_MASK (0x2000000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_SHIFT (25U) /*! idma_25 - Flush TTE Address FIFO */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_25(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_MASK (0x4000000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_SHIFT (26U) /*! timer_tick1 - Allows to select the EP Timer Tick to be either the 1us timer tick or the 125us * timer tick or the 1ms timer tick or the 4ms timer tick based on the setting of this bit and bit * 10 of this register. The encoding is as follows (bit{[26],[10]}): '00' : 1us EP Timer Tick, * '01' : 125us EP Timer Tick, '10' : 1ms EP Timer Tick, '11' : 4ms EP Timer Tick */ #define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_MASK (0x8000000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_SHIFT (27U) /*! idma_27 - '0': Drop Deferred Stream Reject TPs. (default) (Bug #5434), '1': Allow Deferred Stream Reject TPs */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_27(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_MASK (0x10000000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_SHIFT (28U) /*! idma_28 - '0': Drop Deferred Ack/Ack TPs. (default) (Bug #5481), '1': Allow Deferred Ack/Ack TPs */ #define USB3_XECP_HOST_CTRL_IDMA_REG_idma_28(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_MASK (0x20000000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_SHIFT (29U) /*! db_event_gen_en - Used in Doorbell Manager. '0': Do not generate an event. '1': Enable an event * generated with completion code TRB_CMPL_ENDPOINT_NOT_ENABLED_ERR when a doorbell ring on an * EP, which has not running or stop state. */ #define USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_MASK (0x40000000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_SHIFT (30U) /*! event_priority - Used in Event Manager. '0': CPL Engine priority over XFER Manager, '1': XFER Manager priority over CPL Engine. */ #define USB3_XECP_HOST_CTRL_IDMA_REG_event_priority(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_MASK) #define USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_MASK (0x80000000U) #define USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_SHIFT (31U) /*! event_fifo_dis - Used in Event Manager. '0': Enable single ring optimization, '1': Disable single ring optimization. */ #define USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_PORT_CTRL - Global Port Control */ /*! @{ */ #define USB3_XECP_HOST_CTRL_PORT_CTRL_res1_MASK (0xFU) #define USB3_XECP_HOST_CTRL_PORT_CTRL_res1_SHIFT (0U) /*! res1 - Reserved to 1 (reserved for PP) */ #define USB3_XECP_HOST_CTRL_PORT_CTRL_res1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_res1_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_res1_MASK) #define USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_MASK (0x1F0U) #define USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_SHIFT (4U) #define USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_MASK) #define USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_MASK (0x800U) #define USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_SHIFT (11U) /*! PCIe_gasket - Reserved to '1'. Note: An internal register bit for PCIe gasket. It is only valid for value of '1' */ #define USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_MASK) #define USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_MASK (0x1000U) #define USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_SHIFT (12U) /*! enable_itp_xmt - Bit(s) of this field are designated to individually control each USB3 port to * enable ITP transmission. 0: Do not Transmit any ITP. 1: Transmit ITP */ #define USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_MASK) #define USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_MASK (0x1E000U) #define USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_SHIFT (13U) /*! hbuf_water_mark_reg_cclk - This 4-bit register is designed as a water mark for when to turn on * link FC credit return disable. This is used in xhc_prot_rppe.v for receive buffer management. * We have 8 header credit in per port receive buffer. When buffer received enough packets, it * will need to disable the link credit FC return in order to balance the processing delay within * DMA engine. 0: Always enable link credit FC return, 1-8: Water mark value. */ #define USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_MASK) #define USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_MASK (0x20000U) #define USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_SHIFT (17U) /*! overflow_sys_err_en - '0': Disable error generation. '1': Enable to generate a host system error when receive buffer overflow on any ports */ #define USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_MASK) #define USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_MASK (0x40000U) #define USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_SHIFT (18U) /*! rd_wr_addr_conflict_en - rd_wr_addr_conflict_en */ #define USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_MASK) #define USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_MASK (0x80000U) #define USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_SHIFT (19U) /*! lock_header_data_en - lock_header_data_en */ #define USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_MASK) /*! @} */ /*! @name XECP_AUX_CTRL_REG - AUX Reset Control */ /*! @{ */ #define USB3_XECP_AUX_CTRL_REG_force_fd_rst_MASK (0x3U) #define USB3_XECP_AUX_CTRL_REG_force_fd_rst_SHIFT (0U) /*! force_fd_rst - Writing to this field a value of 2'b11 will cause a fundamental reset. The only valid write values are 2'b11 or 2'b00 */ #define USB3_XECP_AUX_CTRL_REG_force_fd_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_force_fd_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_force_fd_rst_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_MASK (0x4U) #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_SHIFT (2U) /*! ignore_perst_4fd_rst - When fundamental reset is asserted during AUX power up, if this bit is * set, then we will ignore PERST# such that purely wait for timeout to deassert fundamental reset. */ #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_MASK (0x8U) #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_SHIFT (3U) /*! ignore_perst_4main_pwrup - When set to '1' ignore waiting for PERST# deassertion during main power show down. */ #define USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_MASK) #define USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_MASK (0x10U) #define USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_SHIFT (4U) /*! pm_ctrl_main_rst_en - When set to '1' allow main power off condition to trigger a main power domain reset */ #define USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_MASK (0x20U) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_SHIFT (5U) /*! ignore_main_pwrup_rst - When set to '1', it enables the reset isolation function that we have added during HC reset or Per port reset. */ #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_MASK (0x40U) #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_SHIFT (6U) /*! ignore_warm_rst_2usb_phy - When set to '1' ignore warm reset to the USB PHY */ #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_MASK (0x80U) #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_SHIFT (7U) /*! ignore_hc_warm_rst_2usb_phy - When set to '1' ignore HC reset to the USB PHY */ #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_MASK (0x100U) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_SHIFT (8U) /*! ignore_main_pwrup_2pcie_phy - When set to '1' ignore main power up reset to PCIe PHY */ #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_MASK (0x200U) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_SHIFT (9U) /*! ignore_main_pwrup_2pcore - When set to '1' ignore main power up reset to PCIe core */ #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_MASK (0x400U) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_SHIFT (10U) /*! ignore_main_pwrup_4u2port - When set to '1' ignore main power up reset to USB2 port logic */ #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_MASK (0x800U) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_SHIFT (11U) /*! ignore_main_pwrup_4u3port - When set to '1' ignore main power up reset to USB3 port logic */ #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_MASK (0x1000U) #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_SHIFT (12U) /*! ignore_warm_rst_4u3port - When set to '1' ignore warm reset to the USB3 port logic */ #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_MASK (0x2000U) #define USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_SHIFT (13U) /*! ignore_hot_rst_4u3port - When set to '1' ignore hot reset to the USB3 port logic */ #define USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_MASK) #define USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_MASK (0x4000U) #define USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_SHIFT (14U) /*! pcie_linkdown_rst_en - When set to '1' allow PCIe link down to cause a reset to the rest of the core as the HC reset would */ #define USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_MASK (0x8000U) #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_SHIFT (15U) /*! ignore_warm_rst_4uphy_pon - When set to '1' ignore warm reset of the portSC to the USB PHY power on reset */ #define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_MASK (0x10000U) #define USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_SHIFT (16U) /*! ignore_mac_phy_pipe_rst - When set to '1' ignore the LTSSM of USB link state transition caused reset to USB PHY PIPE reset */ #define USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_MASK (0x20000U) #define USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_SHIFT (17U) /*! ignore_hc_rst_2pcie_phy - When set to '1' ignore HC reset to the PCIe PHY PIPE reset */ #define USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_MASK) #define USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_MASK (0x40000U) #define USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_SHIFT (18U) /*! eeprom_load_on_main - When set to '1' enable EEPROM reload on every main power-up */ #define USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_SHIFT)) & USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_MASK (0x80000U) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_SHIFT (19U) /*! ignore_main_pwrup_hc_2pcore - When set to '1' enable the HC liked reset caused by PCIe link down * condition detected. If PCIe link down detected, a link down reset will always be fired to * PCIe core. */ #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_MASK (0x100000U) #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_SHIFT (20U) /*! ignore_hc_warm_rst_4uphy_pon - When set to '1' ignore HC reset to the USB PHY power-on reset */ #define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_MASK (0x200000U) #define USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_SHIFT (21U) /*! ignore_hcreset_4usb2 - When set to '1' ignore HC reset to reset the USB2 Port logic */ #define USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_MASK) #define USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_MASK (0x400000U) #define USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_SHIFT (22U) /*! cold_rst_n_pulse - When set to '1' allow software to fire a cold reset to USB port logic */ #define USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_SHIFT)) & USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_MASK (0x800000U) #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_SHIFT (23U) /*! ignore_main_pwrup_2usb_phy - When set to '1' ignore main powerup reset to USB PHY PIPE reset */ #define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_MASK (0x1000000U) #define USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_SHIFT (24U) /*! ignore_linkdown_rst_4uport - When set to '1' ignore a port reset that is caused by a USB port link went down. */ #define USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_MASK) #define USB3_XECP_AUX_CTRL_REG_fast_sim_rst_MASK (0x2000000U) #define USB3_XECP_AUX_CTRL_REG_fast_sim_rst_SHIFT (25U) /*! fast_sim_rst - This bit enables a speed up function or AUX reset at startup. Normally we wait * for 20ms after AUX power level has reached. When in speed up mode, we wait only around 3-4us. * '0: Disabled, '1: Enabled for fast sim */ #define USB3_XECP_AUX_CTRL_REG_fast_sim_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_fast_sim_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_fast_sim_rst_MASK) #define USB3_XECP_AUX_CTRL_REG_ignore_perst_en_MASK (0x4000000U) #define USB3_XECP_AUX_CTRL_REG_ignore_perst_en_SHIFT (26U) /*! ignore_perst_en - This bit disables the PERST# to cause an internal reset. '0: enable '1: disable the PERST# */ #define USB3_XECP_AUX_CTRL_REG_ignore_perst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_perst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_perst_en_MASK) #define USB3_XECP_AUX_CTRL_REG_perst_4main_en_MASK (0x8000000U) #define USB3_XECP_AUX_CTRL_REG_perst_4main_en_SHIFT (27U) /*! perst_4main_en - This bit enables the internal reset control module to immediately start a reset * assertion process when PERST# is deasserted without waiting for PCIe device is out of D3 * state. This is for warm reboot only. The PERST# can still have impact as a reset if the xHC is in * D3 and allow PERST# as a powerup reset bit set. '0: disabled '1: enabled PERST# as an * immediately reset */ #define USB3_XECP_AUX_CTRL_REG_perst_4main_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_perst_4main_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_perst_4main_en_MASK) #define USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_MASK (0x10000000U) #define USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_SHIFT (28U) /*! perst_2pwdown_en - This bit enables the AUX PM control module to assert mac_phy_powerdown state * to P1 as soon as PERST# is deasserted. If disabled, then the AUX PM control state will follow * its nature cause to determine the power down states for PIPE. '0': disabled, '1': enabled. */ #define USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_MASK) #define USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_MASK (0x20000000U) #define USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_SHIFT (29U) /*! pcie_phy_rst_sel - This bit enables AUX reset control module to assert the pcie_phy_reset either * from PIPE reset or from Aux power up reset only. The pcie_phy_reset is an internal signal for * CB PHY only. '0': Aux PowerUp Reset, '1': PIPE PHY reset */ #define USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_SHIFT)) & USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_MASK) #define USB3_XECP_AUX_CTRL_REG_perst_filter_dis_MASK (0x40000000U) #define USB3_XECP_AUX_CTRL_REG_perst_filter_dis_SHIFT (30U) /*! perst_filter_dis - reserved. perst_filter_dis */ #define USB3_XECP_AUX_CTRL_REG_perst_filter_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_perst_filter_dis_SHIFT)) & USB3_XECP_AUX_CTRL_REG_perst_filter_dis_MASK) /*! @} */ /*! @name XECP_HOST_BW_OV_SS_REG - Super Speed Bandwidth Overload */ /*! @{ */ #define USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_MASK (0xFFFU) #define USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_SHIFT (0U) /*! ss_bw_calc - BW calculation: Overhead per packet for SS BW calculations. See white paper. */ #define USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_MASK) #define USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_MASK (0xFFF000U) #define USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_SHIFT (12U) /*! max_tt_bw - Max. TT BW allowed. See white paper */ #define USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_SHIFT)) & USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_MASK) /*! @} */ /*! @name XECP_HOST_BW_OV_HS_REG - High Speed TT Bandwidth Overload */ /*! @{ */ #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_MASK (0xFFFU) #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_SHIFT (0U) /*! bw_ov_hs_tt - BW calculation: Overhead per packet for HS BW calculations. See white paper. */ #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_SHIFT)) & USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_MASK) #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_MASK (0xFFF000U) #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_SHIFT (12U) /*! bw_ov_hs - BW calculation: Overhead per packet for HS-TT BW calculations. See white paper. */ #define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_SHIFT)) & USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_MASK) /*! @} */ /*! @name XECP_HOST_BW_OV_FS_LS_REG - Bandwidth Overload Full and Low Speed */ /*! @{ */ #define USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_MASK (0xFFFU) #define USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_SHIFT (0U) /*! ls_bw_calc - BW calculation: Overhead per packet for LS BW calculations. See white paper. */ #define USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_MASK) #define USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_MASK (0xFFF000U) #define USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_SHIFT (12U) /*! fs_bw_calc - BW calculation: Overhead per packet for FS BW calculations. See white paper. */ #define USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_MASK) /*! @} */ /*! @name XECP_HOST_BW_OV_SYS_REG - System Bandwidth Overload */ /*! @{ */ #define USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_MASK (0xFFFU) #define USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_SHIFT (0U) /*! sys_bw_calc - BW calculation: Overhead per packet for System BW calculations. See white paper. */ #define USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_MASK) #define USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_MASK (0xFFF000U) #define USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_SHIFT (12U) /*! bw_ov_sys_tt - BW calculation: Overhead per TT packet for System BW calculations. See white paper. */ #define USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_SHIFT)) & USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG - Scheduler Async Delay */ /*! @{ */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_MASK (0x7U) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_SHIFT (0U) /*! ls_ctrl_delay_def - Low-Speed Control Delay Default (0=125us,1=250us,2=500us,3=1ms,) */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_MASK) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_MASK (0x8U) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_SHIFT (3U) /*! ls_ctrl_delay_en - Low-Speed Control Delay Enable */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_MASK) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_MASK (0x70U) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_SHIFT (4U) /*! fs_ctrl_delay_def - Full-Speed Control Default (0=125us,1=250us,2=500us,3=1ms,) */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_MASK) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_MASK (0x80U) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_SHIFT (7U) /*! fs_ctrl_delay_en - Full-Speed Control Delay Enable */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_MASK) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_MASK (0x700U) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_SHIFT (8U) /*! hs_ctrl_delay_def - High-Speed Control Delay Default (0=125us,1=250us,2=500us,3=1ms,) */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_MASK) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_MASK (0x800U) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_SHIFT (11U) /*! hs_ctrl_delay_en - High-Speed Control Delay Enable */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_MASK) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_MASK (0x7000U) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_SHIFT (12U) /*! fs_bulk_delay_def - Full-Speed Bulk Delay Default (0=125us,1=250us,2=500us,3=1ms,) */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_MASK) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_MASK (0x8000U) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_SHIFT (15U) /*! fs_bulk_delay_en - Full-Speed Bulk Delay Enable */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_MASK) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_MASK (0x70000U) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_SHIFT (16U) /*! hs_bulk_delay_def - High-Speed Bulk Delay Default (0=125us,1=250us,2=500us,3=1ms,) */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_MASK) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_MASK (0x80000U) #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_SHIFT (19U) /*! hs_bulk_delay_en - High-Speed Bulk Delay Enable */ #define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_MASK) /*! @} */ /*! @name XECP_UPORTS_PON_RST_REG - AUX Power PHY Reset */ /*! @{ */ #define USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_MASK (0xFU) #define USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_SHIFT (0U) /*! usb_phy_port_num - Indicates the port number of the USB PHY */ #define USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_SHIFT)) & USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_TRM_REG3 - Host Control Transfer Manager (TRM) */ /*! @{ */ #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_MASK (0x1U) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_SHIFT (0U) /*! cfg_en_cache - '0': Disable cache control, '1': Enable cache control */ #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_MASK (0x2U) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_SHIFT (1U) /*! cfg_en_lookahead - '0': Disable cache control lookahead, '1': Enable cache control lookahead */ #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_MASK (0x4U) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_SHIFT (2U) /*! cfg_en_hit_invalid - '0': Disable cache control hit invalid with invalid CS, '1': Enable cache control hit invalid with invalid CS */ #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_MASK (0x8U) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_SHIFT (3U) /*! cfg_cache_debug - cfg_cache_debug. Available when TRB_CACHE_DEBUG_EN is defined */ #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_MASK (0x30U) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_SHIFT (4U) /*! cfg_en_look_pos - Enable cache control trigger position lookahead */ #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_MASK (0x40U) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_SHIFT (6U) /*! cfg_en_defer_bc - '0': Disable cache control to defer misses on bulk/control EPs. '1': Enable * cache control to defer misses on bulk/control EPs */ #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_MASK (0x80U) #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_SHIFT (7U) /*! cfg_en_miss_double - '0': Do not enable cache control to double fetch on miss. '1': Enable cache control to double fetch on miss */ #define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_MASK) #define USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_MASK (0x100U) #define USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_SHIFT (8U) /*! cpl_extra_db_rang_en - cpl_extra_db_rang_en */ #define USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_MASK) /*! @} */ /*! @name XECP_AUX_CTRL_REG1 - AUX Power Management Control 1 */ /*! @{ */ #define USB3_XECP_AUX_CTRL_REG1_force_pm_state_MASK (0x1U) #define USB3_XECP_AUX_CTRL_REG1_force_pm_state_SHIFT (0U) /*! force_pm_state - When set to '1' force PM state to go to the state indicated in field pm_state * (bits [4:1]). This bit is the force PM state register, it is a pulse only (read by software * will always give '0') */ #define USB3_XECP_AUX_CTRL_REG1_force_pm_state(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_force_pm_state_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_force_pm_state_MASK) #define USB3_XECP_AUX_CTRL_REG1_pm_state_MASK (0x1EU) #define USB3_XECP_AUX_CTRL_REG1_pm_state_SHIFT (1U) /*! pm_state - Forced power management state can be set here. States encoding: PM_ACTIVE : 4'h0; * REQ_CLK_SWITCH_2AUX : 4'h1; DRIVE_PHY_2P2 : 4'h2; WAIT_4WAKE : 4'h3; WAIT_4PERST_DSRT : 4'h4; * RATE_CHANGE_2FAST : 4'h5; REQ_CLK_SWITCH_2PCLK : 4'h6; PM_EXIT : 4'h7; WAIT_4PCLK : 4'h8; * DRIVE_PHY_STATUS : 4'h9; PM_IDLE : 4'hA; PWRUP_REQ_CLK_SWITCH_2PCLK : 4'hB; RATE_CHANGE_2SLOW : 4'hC; * WAIT_4LTSSM_WAIT_DONE : 4'hD; WAIT_4CLK_GATE : 4'hE; IN_P2_TIMEOUT : 4'hF; Those bits have * also another functionality: [1]: always_wake_n_en, [2]: timeout_16ms_en, [3]: * always_force_clk_sw_en, ![4]: rc_p2_exit_en */ #define USB3_XECP_AUX_CTRL_REG1_pm_state(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_pm_state_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_pm_state_MASK) #define USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_MASK (0x20U) #define USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_SHIFT (5U) /*! enable_p2_enter - When set to '1' enables the remote wake function by allowing P2 clock/switching and P2 entering */ #define USB3_XECP_AUX_CTRL_REG1_enable_p2_enter(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_MASK) #define USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_MASK (0x40U) #define USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_SHIFT (6U) /*! p2_overwrite_p1_en - When set to '1' enable P2 overwrite P1 when PCIe core has indicated the * transition from P0 to P1. This is to enable entering the even lower power state. */ #define USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_MASK (0x80U) #define USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_SHIFT (7U) /*! ignore_aux_pme_en - When set to '1' ignore the aux_pm_en reg from PCIe core to continue the remote wake/clock switching support */ #define USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_MASK (0x100U) #define USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_SHIFT (8U) /*! phystatus_fall_timeout_en - When set to '1' enable PHY status timeout function, which is * designed to cover the PCIePHY issue that we may have not be able to detect the PHY status toggle. * This is a safety feature in case we have gotten into a deadlock during PHY status acknowledgement. */ #define USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_MASK (0x200U) #define USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_SHIFT (9U) /*! cclk_gate_disable - When set to '1' disable core clock gating based on low power state entered */ #define USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_MASK) #define USB3_XECP_AUX_CTRL_REG1_new_ow_en_MASK (0x400U) #define USB3_XECP_AUX_CTRL_REG1_new_ow_en_SHIFT (10U) /*! new_ow_en - This bit allows the AUX PM control module to decide whether we entered into P2 * overwrite condition based on the power down state of the PCIe core is at P1 or the LTSSM of PCIe * core is in L1. What we used to have is based on P1 of the PCIe core mac_phy_powerdown signal. * This is not correct because LTSSM can be in RX detect to result a P1 of power down state. To * preserve our old function, we add this chicken bit. '0': P2Pverwrite function based on PCIe core * PIPE mac_phy_powerdown is in P1, '1': P2OverWrite function based on LTSSM in L1 */ #define USB3_XECP_AUX_CTRL_REG1_new_ow_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_new_ow_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_new_ow_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_isolation_en_MASK (0x800U) #define USB3_XECP_AUX_CTRL_REG1_isolation_en_SHIFT (11U) /*! isolation_en - When set to '1' enable isolation function for dual power zone. */ #define USB3_XECP_AUX_CTRL_REG1_isolation_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_isolation_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_isolation_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_pme_status_en_MASK (0x1000U) #define USB3_XECP_AUX_CTRL_REG1_pme_status_en_SHIFT (12U) /*! pme_status_en - This bit enables the PCIe status function. '0': xHC as a PCIe device will not * generate any PME nor report PME status. '1': xHC as a PCIe device will generate the PME message. */ #define USB3_XECP_AUX_CTRL_REG1_pme_status_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_pme_status_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_pme_status_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_MASK (0x2000U) #define USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_SHIFT (13U) /*! elecidle_mask_en - This bit enables the AUX PM control state machine to take over txelecidle * signal of the PIPE during several special conditions. '0': Disable the mask. '1': Allow mask to * mac_phy_txeleidle of PCIe core. */ #define USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_MASK (0x4000U) #define USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_SHIFT (14U) /*! cfg_pipe_rst_en - Cfg_pipe_rst_en_sync */ #define USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_MASK (0x8000U) #define USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_SHIFT (15U) /*! cfg_rxdet_p3_en - Cfg_rxdet_p3_en. Enable rxdet U3 mode */ #define USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_MASK (0x10000U) #define USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_SHIFT (16U) /*! cfg_clk_gate_dis - Cfg_clk_gate_dis */ #define USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_MASK) #define USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_MASK (0x20000U) #define USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_SHIFT (17U) /*! cfg_usb_p2_en - Cfg_Usb_p2_en */ #define USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_MASK (0xC0000U) #define USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_SHIFT (18U) /*! cfg_iob_drivestrength - Controls the drive strength of the IO buffer. Set default IO Strength to 8ma */ #define USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_MASK) #define USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_MASK (0x100000U) #define USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_SHIFT (20U) /*! cfg_pcie_txreg_pd - cfg_pcie_txreg_pd */ #define USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_MASK) #define USB3_XECP_AUX_CTRL_REG1_clr_save_flag_MASK (0x200000U) #define USB3_XECP_AUX_CTRL_REG1_clr_save_flag_SHIFT (21U) #define USB3_XECP_AUX_CTRL_REG1_clr_save_flag(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_clr_save_flag_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_clr_save_flag_MASK) #define USB3_XECP_AUX_CTRL_REG1_reservedrw_MASK (0x400000U) #define USB3_XECP_AUX_CTRL_REG1_reservedrw_SHIFT (22U) /*! reservedrw - reserved, RW */ #define USB3_XECP_AUX_CTRL_REG1_reservedrw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_reservedrw_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_reservedrw_MASK) #define USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_MASK (0x800000U) #define USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_SHIFT (23U) #define USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_MASK (0x1000000U) #define USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_SHIFT (24U) /*! clr_ssv_en - When set to '1' clear the SSV flag */ #define USB3_XECP_AUX_CTRL_REG1_clr_ssv_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_set_ssv_en_MASK (0x2000000U) #define USB3_XECP_AUX_CTRL_REG1_set_ssv_en_SHIFT (25U) /*! set_ssv_en - When set to '1' set the SSV flag. */ #define USB3_XECP_AUX_CTRL_REG1_set_ssv_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_set_ssv_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_set_ssv_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_MASK (0x4000000U) #define USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_SHIFT (26U) /*! powerdown_p1_en - This is a test/control bit. This bit is designed to control the lowest * powerdown state of the PCIe that AUX PM module signaled to PIPE is P1. '0': drive as normal * operation. '1': always drive to P1 instead of P2 */ #define USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_MASK (0x8000000U) #define USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_SHIFT (27U) /*! use_perst_4fd_rst - Enable AUX reset module to treat every PERST# as a fundamental reset '0': disabled, '1': enabled */ #define USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_MASK) #define USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_MASK (0x10000000U) #define USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_SHIFT (28U) /*! direct_rate_pass_en - Disable the overwrite function in AUX PM control module for its initiated * rate change. '0': allows AUX PM control module to initiate its PCIE rate change when it needs * to enable P2 overwrite P1 function. '1': AUX PM control module will not alter the PCIe rate * change function . */ #define USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_MASK (0x20000000U) #define USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_SHIFT (29U) /*! extend_phystatus_en - This bit is there for a bug fix where we need to ensure that phystatus did * not get lost during the rate change where clock switch logic takes some cycles to complete; * such that the PCie's core clock is at half of the PCIe PHY pclk. '0': not extended phystatus, * '1': extended phystatus assertion */ #define USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_MASK (0x40000000U) #define USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_SHIFT (30U) /*! low_pwr_cclk_gate_en - This bit enables gate-off the core clock when AUX PM control is in low * power state. '0': disable this function, '1': enabled to gate off the core clock. */ #define USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_MASK) #define USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_MASK (0x80000000U) #define USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_SHIFT (31U) /*! d3_hot_pme_en - d3_hot_pme_en */ #define USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_WATERMARK_REG - Port Watermark */ /*! @{ */ #define USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_MASK (0xFFFFU) #define USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_SHIFT (0U) /*! xbuf_water_mark - XBUF water mark */ #define USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_SHIFT)) & USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_MASK) #define USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_MASK (0xFFFF0000U) #define USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_SHIFT (16U) /*! rbuf_water_mark - RBUF water mark */ #define USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_SHIFT)) & USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_PORT_LINK_REG - SuperSpeed Port Link Control */ /*! @{ */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_MASK (0x1U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_SHIFT (0U) /*! cfg_dis_comp - '0': Enable link compliance mode, '1': Disable link compliance mode */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_MASK (0x2U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_SHIFT (1U) /*! cfg_lpbk_mode - '0': Disable link loopback master mode, '1': Enable link loopback master mode */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_MASK (0x4U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_SHIFT (2U) /*! cfg_u1_enable - '0': Normal operation mode, '1': Direct link to U1 from U0. This bit is for test * purpose only. It shall be written '0' in normal operation mode. */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_MASK (0x8U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_SHIFT (3U) /*! cfg_u2_enable - '0': Normal operation mode, '1': Direct link to U2 from U0. This bit is for test * purpose only. It shall be written '0' in normal operation mode. */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_MASK (0x10U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_SHIFT (4U) /*! cfg_symbol_err_en - '0': Disable detecting RxData error using RxStatus signal, '1': Enable detecting RxData error using RxStatus signal. */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_MASK (0x20U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_SHIFT (5U) /*! cfg_dis_scrmb - '0': Enable link scrambler, '1': Disable link scrambler */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_MASK (0x40U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_SHIFT (6U) /*! cfg_fast_training - '0': Normal operation mode, '1': Link fast training mode. This bit should be written '0' in normal operation. */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_MASK (0x80U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_SHIFT (7U) /*! cfg_recovery - '0': Normal operation mode, '1': Direct link to Recovery from U0 */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_MASK (0x100U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_SHIFT (8U) /*! cfg_force_pm_accept - '0': Normal operation mode. '1': Force link to accept power management command */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_MASK (0xE00U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_SHIFT (9U) /*! cfg_u3_recov_val - This value defines the minimum time for the link to stay in Polling.Active * and Recovery.Active from U3. The granuity is 128us. */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_MASK (0x7000U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_SHIFT (12U) /*! cfg_norm_recov_val - This value defines the minimum time for the link to stay in Recovery. Active other than from U3. The granuity is 128us */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_MASK (0x18000U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_SHIFT (15U) /*! cfg_lowpower_latency - cfg_lowpower_latency */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_MASK (0xE0000U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_SHIFT (17U) /*! dbg_mode_sel - Debug mode select: bit[0]: cfg_port_init_ctrl (if set to '1' tPortConfiguration < * 21us), bit[1]: cfg_relax_ts2_en, bit[2]: cfg_relax_lfps_en */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_MASK (0x100000U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_SHIFT (20U) /*! link_err_cnt_slv_en - link_err_cnt_slv_en */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_MASK (0x1E00000U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_SHIFT (21U) /*! force_comp_pattern - Compliance pattern to be forced to enter compliance mode. This value is for test purpose only. */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_MASK (0x2000000U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_SHIFT (25U) /*! force_ltssm_u0 - '0': Normal operation mode, '1': Direct link to U0 This bit is for test purpose * only. It shall be written '0' in normal operation mode. */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_MASK (0x4000000U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_SHIFT (26U) /*! force_ltssm - '0': Normal operation mode, '1': Direct link to a specific state specified by * force_ltssm_state field (bits [31:27]). This bit is for test purpose only. It shall be written '0' * in normal operation mode. */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_MASK) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_MASK (0xF8000000U) #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_SHIFT (27U) /*! force_ltssm_state - LTSSM state to be forced. This value is for test purpose only. Setting bit 4 * enables: cfg_relax_rxpolarity_en; Setting bit 3 enables: cfg_relax_linkfunc_en; Setting bit 2 * enables: cfg_link_func_en; */ #define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_MASK) /*! @} */ /*! @name XECP_USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control */ /*! @{ */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_MASK (0x1U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_SHIFT (0U) /*! USB2_PM_DEBUG_QUICK_SIM - Short Timer Values For Simulation of USB2.0 parameters. Please refer to Integration Guide section on Debug Features */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_MASK (0x2U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_SHIFT (1U) /*! USB2_PM_DEBUG_PHY_RST - Control PHY Reset Directly */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_MASK (0x4U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_SHIFT (2U) /*! USB2_PM_DEBUG_PHY_RSTDISCON - Disable Clock Gate */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_MASK (0x8U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_SHIFT (3U) /*! USB2_PM_DEBUG_PHY_CLKGATEDIS - Disable PHY suspend during disconnect */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_MASK (0x10U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_SHIFT (4U) /*! USB2_PM_DEBUG_PHY_SUSDISALL - Disable PHY suspend for all states */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_MASK (0x20U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_SHIFT (5U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_MASK (0x40U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_SHIFT (6U) /*! USB2_PM_DEBUG_FORCEPING - If retry on endpoint that should have PING, force the PING */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_MASK (0x80U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_SHIFT (7U) /*! USB2_PM_DEBUG_DROPPING - If new ping on endpoint that already had PING, drop the PING */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_MASK (0x100U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_SHIFT (8U) /*! USB2_PM_DEBUG_DIRECT_RESUME - Use FS/LS serial I/F to drive resume */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_MASK (0x200U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_SHIFT (9U) /*! USB2_PM_DEBUG_DIS_ISO_PEEK - Disable waiting for last indication for USB2 ISO */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_MASK (0x400U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_SHIFT (10U) /*! USB2_PM_DEBUG_DIS_PORT_ERR - Enable Remote Wake Resume Trap */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_MASK (0x800U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_SHIFT (11U) /*! USB2_PM_DEBUG_ENABLE_DISC_WIN - Enable HS disconnect Window */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_MASK (0x1000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_SHIFT (12U) /*! USB2_PM_DEBUG_UTMIRST1 - Select UTMI Reset Source 1 */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_MASK (0x2000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_SHIFT (13U) /*! USB2_PM_DEBUG_UTMIRST2 - Select UTMI Reset Source 2 */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_MASK (0x4000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_SHIFT (14U) /*! USB2_PM_DEBUG_FS_LS_EXT_DISCON - Use UTMI HostDisconnect input for FS/LS */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_MASK (0x8000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_SHIFT (15U) /*! USB2_PM_DEBUG_SPLIT_192_LIMITDIS - Use to disable 192 byte limit checking on */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_MASK (0x10000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_SHIFT (16U) /*! USB2_PM_DEBUG_FORCE_FULL_SPEED - Set to reject device chirp and force full-speed */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_MASK (0x20000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_SHIFT (17U) /*! USB2_PM_DEBUG_EOP_DETECT - Set to enable full length SE0 detect */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_MASK (0x40000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_SHIFT (18U) /*! USB2_PM_DEBUG_ENABLE_FLUSH_TO - Set to enable flush state timeouts */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_MASK (0x80000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_SHIFT (19U) /*! USB2_PM_DEBUG_HW_LPM_ERRATA1 - Set to change the scale of HW LPM timeout to 256us increments */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_MASK (0x100000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_SHIFT (20U) /*! USB2_PM_DEBUG_HW_LPM_ERRATA - Set to switch the HIRD to BESL format */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_MASK (0x200000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_SHIFT (21U) /*! USB2_PM_DEBUG_RESUME_DEB_DIS - Clr to eliminate debounce on remote wake detect */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_MASK (0x400000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_SHIFT (22U) /*! USB2_PM_DEBUG_LATENCY_TOL_MSG - Latency Tolerance Scheme ('0'=when HWLPM is enabled / '1'=when L1 is active) */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_MASK (0x800000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SHIFT (23U) /*! USB2_PM_DEBUG - USB2_PM_DEBUG. usb2_link_mgr_debug */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_MASK (0xFF000000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_SHIFT (24U) /*! TIMER_DISCONNECT_DETECT_lo - Number of microseconds of SE0 in FS/LS mode to register disconnect had occurred. First 8 MSB */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_MASK) /*! @} */ /*! @name XECP_USB2_LINK_MGR_CTRL_REG2 - USB2 Port Link Control */ /*! @{ */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_MASK (0x1FU) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_SHIFT (0U) /*! TIMER_DISCONNECT_DETECT_hi - Number of microseconds of SE0 in FS/LS mode to register disconnect had occurred. Last 5 LSBs */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_MASK (0x3FFE0U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_SHIFT (5U) /*! TIMER_CONNECT_DETECT - Number of microseconds of K/J in disconnected state to register connect has occurred. Last 5 LSBs */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_MASK (0x7FFC0000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_SHIFT (18U) /*! TIMER_CHIRP_K_DETECT - Number of microseconds of Chirp-K to register that a device is chirping */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_MASK (0x80000000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_SHIFT (31U) /*! TIMER_RESET_0 - Number of microseconds for total reset duration */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_MASK) /*! @} */ /*! @name XECP_USB2_LINK_MGR_CTRL_REG3 - USB2 Port Link Control */ /*! @{ */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_MASK (0x7FFFU) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_SHIFT (0U) /*! TIMER_RESET - Number of microseconds for total reset duration */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_MASK (0xFFF8000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_SHIFT (15U) /*! TIMER_U3_SETTLE - Number of microseconds after entering U3; linestate changes are ignored as bus settles */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_MASK (0xF0000000U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_SHIFT (28U) /*! TIMER_U2_SETTLE - Number of microseconds after entering U2; linestate changes are ignored as bus settles. First 4 LSB */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_MASK) /*! @} */ /*! @name XECP_USB2_LINK_MGR_CTRL_REG4 - USB2 Port Link Control */ /*! @{ */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_MASK (0x1FFU) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_SHIFT (0U) /*! TIMER_U2_SETTLE - Number of microseconds after entering U2; linestate changes are ignored as bus settles. Last 9 MSB */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_MASK) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_MASK (0x1FFFE00U) #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_SHIFT (9U) /*! TIMER_RESUME_U2_REFLECT - Number of microseconds after detecting U2 remote wake condition to reflect K */ #define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_MASK) /*! @} */ /*! @name XECP_HOST_CTRL_BW_MAX_REG - USB2 Max Bandwidth Control */ /*! @{ */ #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_MASK (0xFFU) #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_SHIFT (0U) /*! fsls_max_bw - Max. Percentage BW allowed for FS/LS (default: 90) */ #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_MASK) #define USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_MASK (0xFF00U) #define USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_SHIFT (8U) /*! hs_max_bw - Max. Percentage BW allowed for HS (default: 80) */ #define USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_MASK) #define USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_MASK (0xFF0000U) #define USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_SHIFT (16U) /*! ss_max_bw - Max. Percentage BW allowed for SS (default: 80) */ #define USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_MASK) #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_MASK (0xFF000000U) #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_SHIFT (24U) /*! fsls_bhub_max_bw - Max. Percentage BW allowed for FS/LS behind hub (default: 90) */ #define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_MASK) /*! @} */ /*! @name XECP_FPGA_REVISION_REG - FPGA_REVISION_REG */ /*! @{ */ #define USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_MASK (0xFFFFFFFFU) #define USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_SHIFT (0U) /*! FPGA_REVISION_REG_DEFAULT - FPGA_REVISION_REG_DEFAULT */ #define USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_SHIFT)) & USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_MASK) /*! @} */ /*! @name XECP_HOST_INTF_CTRL_REG - Host interface control */ /*! @{ */ #define USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_MASK (0x1U) #define USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_SHIFT (0U) /*! host_err_mask - host_err_mask. If set to '1' do not mask the host system error */ #define USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_MASK) #define USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_MASK (0x2U) #define USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_SHIFT (1U) /*! hc_halt_timeout_en - hc_halt_timeout_en. An internal register bit used to control whether or not to use the hc halt status timer of 15ms */ #define USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_MASK) #define USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_MASK (0x3CU) #define USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_SHIFT (2U) /*! host_intf_ctrl - host_intf_ctrl */ #define USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_MASK) #define USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_MASK (0xC0U) #define USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_SHIFT (6U) /*! cfg_max_num_of_rd - cfg_max_num_of_rd. This is to control how many max number of read that we * allow ODMA read to issue. '00': can issue 16 reads '10': can issue 8 reads '01': can issue 4 * reads */ #define USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_MASK) #define USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_MASK (0x100U) #define USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_SHIFT (8U) /*! prot_hdr_rbuf_overflow_cclk - prot_hdr_rbuf_overflow_cclk */ #define USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_MASK) /*! @} */ /*! @name XECP_USBLEGSUP - USB Legacy Support Capability */ /*! @{ */ #define USB3_XECP_USBLEGSUP_CID_MASK (0xFFU) #define USB3_XECP_USBLEGSUP_CID_SHIFT (0U) /*! CID - USB Legacy Support Capability ID, RO. This capability provides the xHCI Pre-OS to OS * Handoff Synchronization support capability */ #define USB3_XECP_USBLEGSUP_CID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_CID_SHIFT)) & USB3_XECP_USBLEGSUP_CID_MASK) #define USB3_XECP_USBLEGSUP_NextCP_MASK (0xFF00U) #define USB3_XECP_USBLEGSUP_NextCP_SHIFT (8U) /*! NextCP - Next Capability Pointer, RO. This field indicates the location of the next capability * with respect to the effective address of this capability. A non-zero value in this register * indicates a relative offset, in Dwords, from this Dword to the beginning of the next extended * capability */ #define USB3_XECP_USBLEGSUP_NextCP(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_NextCP_SHIFT)) & USB3_XECP_USBLEGSUP_NextCP_MASK) #define USB3_XECP_USBLEGSUP_HCBIOSOS_MASK (0x10000U) #define USB3_XECP_USBLEGSUP_HCBIOSOS_SHIFT (16U) /*! HCBIOSOS - HC BIOS Owned Semaphore (HCBIOSOS), RW. Default = '0'. The BIOS sets this bit to * establish ownership of the xHC. System BIOS will set this bit to '0' in response to a request for * ownership of the xHC by system software */ #define USB3_XECP_USBLEGSUP_HCBIOSOS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_HCBIOSOS_SHIFT)) & USB3_XECP_USBLEGSUP_HCBIOSOS_MASK) #define USB3_XECP_USBLEGSUP_HCOSOS_MASK (0x1000000U) #define USB3_XECP_USBLEGSUP_HCOSOS_SHIFT (24U) /*! HCOSOS - HC OS Owned Semaphore, RW. Default = '0'. System software sets this bit to request * ownership of the xHC. Ownership is obtained when this bit reads as '1' and the HC BIOS Owned * Semaphore bit (HCBIOSOS) reads as '0' */ #define USB3_XECP_USBLEGSUP_HCOSOS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_HCOSOS_SHIFT)) & USB3_XECP_USBLEGSUP_HCOSOS_MASK) /*! @} */ /*! @name XECP_USBLEGCTLSTS - USB Legacy Support Control Status */ /*! @{ */ #define USB3_XECP_USBLEGCTLSTS_USBSMIE_MASK (0x1U) #define USB3_XECP_USBLEGCTLSTS_USBSMIE_SHIFT (0U) /*! USBSMIE - USB SMI Enable, RW. Default = '0'. When this bit is a '1', and the SMI on Event * Interrupt bit (below) in this register is a '1', the host controller will issue an SMI immediately */ #define USB3_XECP_USBLEGCTLSTS_USBSMIE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_USBSMIE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_USBSMIE_MASK) #define USB3_XECP_USBLEGCTLSTS_SMIHSEE_MASK (0x10U) #define USB3_XECP_USBLEGCTLSTS_SMIHSEE_SHIFT (4U) /*! SMIHSEE - SMI on Host System Error Enable, RW. Default = '0'. When this bit is a '1', and the * SMI on Host System Error bit (below) in this register is a '1', the host controller will issue * an SMI immediately */ #define USB3_XECP_USBLEGCTLSTS_SMIHSEE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIHSEE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIHSEE_MASK) #define USB3_XECP_USBLEGCTLSTS_SMIOSOE_MASK (0x2000U) #define USB3_XECP_USBLEGCTLSTS_SMIOSOE_SHIFT (13U) /*! SMIOSOE - SMI on OS Ownership Enable, RW. Default = '0'. When this bit is a '1' AND the OS * Ownership Change bit is '1', the host controller will issue an SMI */ #define USB3_XECP_USBLEGCTLSTS_SMIOSOE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIOSOE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIOSOE_MASK) #define USB3_XECP_USBLEGCTLSTS_SMIPCICE_MASK (0x4000U) #define USB3_XECP_USBLEGCTLSTS_SMIPCICE_SHIFT (14U) /*! SMIPCICE - SMI on PCI Command Enable, RW. Default = '0'. When this bit is '1' and SMI on PCI * Command is '1', then the host controller will issue an SMI */ #define USB3_XECP_USBLEGCTLSTS_SMIPCICE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIPCICE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIPCICE_MASK) #define USB3_XECP_USBLEGCTLSTS_SMIBARE_MASK (0x8000U) #define USB3_XECP_USBLEGCTLSTS_SMIBARE_SHIFT (15U) /*! SMIBARE - SMI on BAR Enable, RW. Default = '0'. When this bit is '1' and SMI on BAR is '1', then * the host controller will issue an SMI */ #define USB3_XECP_USBLEGCTLSTS_SMIBARE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIBARE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIBARE_MASK) #define USB3_XECP_USBLEGCTLSTS_SMIEI_MASK (0x10000U) #define USB3_XECP_USBLEGCTLSTS_SMIEI_SHIFT (16U) /*! SMIEI - SMI on Event Interrupt, RO. Default = '0'. Shadow bit of Event Interrupt (EINT) bit in * the USBSTS register. Refer to Section 5.4.2 of xHCI specification for definition. This bit * follows the state the Event Interrupt (EINT) bit in the USBSTS register, e.g. it automatically * clears when EINT clears or set when EINT is set */ #define USB3_XECP_USBLEGCTLSTS_SMIEI(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIEI_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIEI_MASK) #define USB3_XECP_USBLEGCTLSTS_SMIHSE_MASK (0x100000U) #define USB3_XECP_USBLEGCTLSTS_SMIHSE_SHIFT (20U) /*! SMIHSE - SMI on Host System Error, RO. Default = '0'. Shadow bit of Host System Error (HSE) bit * in the USBSTS register. Refer to Section 5.4.2 of xHCI specification for definition and * effects of the events associated with this bit being set to '1'. To clear this bit to a '0', system * software shall write a '1' to the Host System Error (HSE) bit in the USBSTS */ #define USB3_XECP_USBLEGCTLSTS_SMIHSE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIHSE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIHSE_MASK) #define USB3_XECP_USBLEGCTLSTS_SMIOSOC_MASK (0x20000000U) #define USB3_XECP_USBLEGCTLSTS_SMIOSOC_SHIFT (29U) /*! SMIOSOC - SMI on OS Ownership Change, RW1C. Default = '0'. This bit is set to '1' whenever the * HC OS Owned Semaphore bit in the USBLEGSUP register transitions from '1' to a '0' or '0' to a * '1' */ #define USB3_XECP_USBLEGCTLSTS_SMIOSOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIOSOC_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIOSOC_MASK) #define USB3_XECP_USBLEGCTLSTS_SMIPCIC_MASK (0x40000000U) #define USB3_XECP_USBLEGCTLSTS_SMIPCIC_SHIFT (30U) /*! SMIPCIC - SMI on PCI Command, RW1C. Default = '0'. This bit is set to '1' whenever the PCI Command Register is written */ #define USB3_XECP_USBLEGCTLSTS_SMIPCIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIPCIC_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIPCIC_MASK) #define USB3_XECP_USBLEGCTLSTS_SMIBAR_MASK (0x80000000U) #define USB3_XECP_USBLEGCTLSTS_SMIBAR_SHIFT (31U) /*! SMIBAR - SMI on BAR, RW1C. Default = '0'. This bit is set to '1' whenever the Base Address Register (BAR) is written */ #define USB3_XECP_USBLEGCTLSTS_SMIBAR(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIBAR_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIBAR_MASK) /*! @} */ /*! @name XECP_DCID - Debug Capability ID */ /*! @{ */ #define USB3_XECP_DCID_CapID_MASK (0xFFU) #define USB3_XECP_DCID_CapID_SHIFT (0U) /*! CapID - Debug capability ID, RO */ #define USB3_XECP_DCID_CapID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCID_CapID_SHIFT)) & USB3_XECP_DCID_CapID_MASK) #define USB3_XECP_DCID_NextCapID_MASK (0xFF00U) #define USB3_XECP_DCID_NextCapID_SHIFT (8U) /*! NextCapID - Next Capability Pointer, RO. Default = 0. This field indicates the location of the * next capability with respect to the effective address of this capability. A non-zero value in * this register indicates a relative offset, in Dwords, from this Dword to the beginning of the * next extended capability */ #define USB3_XECP_DCID_NextCapID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCID_NextCapID_SHIFT)) & USB3_XECP_DCID_NextCapID_MASK) #define USB3_XECP_DCID_DCERST_Max_MASK (0x1F0000U) #define USB3_XECP_DCID_DCERST_Max_SHIFT (16U) /*! DCERST_Max - Debug Capability Event Ring Segment Table Max (DCERST Max), RO. Default = 3. Valid * values are 0 to 15. This field determines the maximum value supported by the Debug Capability * Event Ring Segment Table Base Size registers, where: The maximum number of Event Ring Segment * Table entries = 2^DCERST_Max; e.g. if DCERST_Max = 7, then the Debug Capability Event Ring * Segment Table(s) supports up to 128 entries, 15 then 32K entries, etc */ #define USB3_XECP_DCID_DCERST_Max(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCID_DCERST_Max_SHIFT)) & USB3_XECP_DCID_DCERST_Max_MASK) /*! @} */ /*! @name XECP_DCDB - Debug Capability Doorbell */ /*! @{ */ #define USB3_XECP_DCDB_DB_target_MASK (0xFF00U) #define USB3_XECP_DCDB_DB_target_SHIFT (8U) /*! DB_target - Doorbell Target (DB Target), RW. This field defines the target of the doorbell * reference. Debug Capability notifications generated by ringing the doorbell: 0: Data EP 1 OUT * Enqueue Pointer Update 1: Data EP 1 IN Enqueue Pointer Update 2: 255 Reserved; This field returns * zero when read and it should be treated as undefined by software */ #define USB3_XECP_DCDB_DB_target(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDB_DB_target_SHIFT)) & USB3_XECP_DCDB_DB_target_MASK) /*! @} */ /*! @name XECP_DCERSTSZ - Debug Capability Event Ring Segment Table Size */ /*! @{ */ #define USB3_XECP_DCERSTSZ_ERSTSZ_MASK (0xFFFFU) #define USB3_XECP_DCERSTSZ_ERSTSZ_SHIFT (0U) /*! ERSTSZ - Event Ring Segment Table Size, RW. Default = 0. This field identifies the number of * valid Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the Debug * Capability Event Ring Segment Table Base Address register. The maximum value supported by an xHC * implementation for this register is defined by the DCERST_Max field in the DCID register. * Software shall initialize this register before setting the Debug Capability Enable field in the * DCCTRL register to '1' */ #define USB3_XECP_DCERSTSZ_ERSTSZ(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERSTSZ_ERSTSZ_SHIFT)) & USB3_XECP_DCERSTSZ_ERSTSZ_MASK) /*! @} */ /*! @name XECP_DCERSTBA_LOW - Debug Capability Event Ring Segment Table Base Address */ /*! @{ */ #define USB3_XECP_DCERSTBA_LOW_ERSTBA_L_MASK (0xFFFFFFF0U) #define USB3_XECP_DCERSTBA_LOW_ERSTBA_L_SHIFT (4U) /*! ERSTBA_L - Event Ring Segment Table Base Address Register RW. Default = 0. This field defines * the high order bits of the start address of the Debug Capability Event Ring Segment Table. * Software shall initialize this register before setting the Debug Capability Enable field in the * DCCTRL register to '1' */ #define USB3_XECP_DCERSTBA_LOW_ERSTBA_L(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERSTBA_LOW_ERSTBA_L_SHIFT)) & USB3_XECP_DCERSTBA_LOW_ERSTBA_L_MASK) /*! @} */ /*! @name XECP_DCERSTBA_HIGH - Debug Capability Event Ring Segment Table Base Address */ /*! @{ */ #define USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_MASK (0xFFFFFFFFU) #define USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_SHIFT (0U) /*! ERSTBA_H - Event Ring Segment Table Base Address Register RW. Default = 0. This field defines * the high order bits of the start address of the Debug Capability Event Ring Segment Table. * Software shall initialize this register before setting the Debug Capability Enable field in the * DCCTRL register to '1' */ #define USB3_XECP_DCERSTBA_HIGH_ERSTBA_H(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_SHIFT)) & USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_MASK) /*! @} */ /*! @name XECP_DCERDP_LOW - Debug Capability Event Ring Dequeue Pointer */ /*! @{ */ #define USB3_XECP_DCERDP_LOW_DESI_MASK (0x7U) #define USB3_XECP_DCERDP_LOW_DESI_SHIFT (0U) /*! DESI - Dequeue ERST Segment Index (DESI). Default = 0. This field may be used by the xHC to * accelerate checking the Event Ring full condition. This field is written with the low order 3 bits * of the offset of the ERST entry which defines the Event Ring segment that the Event Ring * Dequeue Pointer resides in */ #define USB3_XECP_DCERDP_LOW_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERDP_LOW_DESI_SHIFT)) & USB3_XECP_DCERDP_LOW_DESI_MASK) #define USB3_XECP_DCERDP_LOW_Deq_Ptr_L_MASK (0xFFFFFFF0U) #define USB3_XECP_DCERDP_LOW_Deq_Ptr_L_SHIFT (4U) /*! Deq_Ptr_L - Dequeue Pointer, RW. Default = 0. This field defines the high order bits of the * 64-bit address of the current Debug Capability Event Ring Dequeue Pointer. Software shall * initialize this register before setting the Debug Capability Enable field in the DCCTRL register to '1' */ #define USB3_XECP_DCERDP_LOW_Deq_Ptr_L(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERDP_LOW_Deq_Ptr_L_SHIFT)) & USB3_XECP_DCERDP_LOW_Deq_Ptr_L_MASK) /*! @} */ /*! @name XECP_DCERDP_HIGH - Debug Capability Event Ring Dequeue Pointer */ /*! @{ */ #define USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_MASK (0xFFFFFFFFU) #define USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_SHIFT (0U) /*! Deq_Ptr_H - Dequeue Pointer, RW. Default = 0. This field defines the high order bits of the * 64-bit address of the current Debug Capability Event Ring Dequeue Pointer. Software shall * initialize this register before setting the Debug Capability Enable field in the DCCTRL register to '1' */ #define USB3_XECP_DCERDP_HIGH_Deq_Ptr_H(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_SHIFT)) & USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_MASK) /*! @} */ /*! @name XECP_DCCTRL - Debug Capability Control */ /*! @{ */ #define USB3_XECP_DCCTRL_DCR_MASK (0x1U) #define USB3_XECP_DCCTRL_DCR_SHIFT (0U) /*! DCR - DbC Run (DCR), RO. Default = '0'. When '0', Debug Device is not in the Configured state. * When '1', Debug Device is in the Configured state and bulk Data pipe transactions are accepted * by Debug Capability and routed to the IN and OUT Transfer Rings. A '0' to '1' transition of * the Port Reset (DCPORTSC:PR) bit will clear this bit to '0' */ #define USB3_XECP_DCCTRL_DCR(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DCR_SHIFT)) & USB3_XECP_DCCTRL_DCR_MASK) #define USB3_XECP_DCCTRL_LSE_MASK (0x2U) #define USB3_XECP_DCCTRL_LSE_SHIFT (1U) /*! LSE - Link Status Event Enable (LSE), RW. Default = '0'. Setting this bit to a '1' enables the * Debug Capability to generate Port Status Change Events due the Port Link Status Change bit * transitioning from a '0' to a '1'. Refer to section 4.19.2 of xHCI specification for more * information */ #define USB3_XECP_DCCTRL_LSE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_LSE_SHIFT)) & USB3_XECP_DCCTRL_LSE_MASK) #define USB3_XECP_DCCTRL_HOT_MASK (0x4U) #define USB3_XECP_DCCTRL_HOT_SHIFT (2U) /*! HOT - Halt OUT TR (HOT), RW1S. Default = '0'. While this bit is '1' the Debug Capability shall * generate STALL TPs for all IN TPs received for the OUT TR. The Debug Capability shall clear * this bit when a ClearFeature(ENDPOINT_HALT) request is received for the endpoint. This field is * valid only when the Debug Capability is in Run Mode (DCR = 1). When not in Run Mode, this field * shall return '0' when read, and writes will have no effect. Refer to section 7.6.4.3 of xHCI * specification */ #define USB3_XECP_DCCTRL_HOT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_HOT_SHIFT)) & USB3_XECP_DCCTRL_HOT_MASK) #define USB3_XECP_DCCTRL_HIT_MASK (0x8U) #define USB3_XECP_DCCTRL_HIT_SHIFT (3U) /*! HIT - Halt IN TR (HIT), RW1S. Default = '0'. While this bit is '1' the Debug Capability shall * generate STALL TPs for all OUT DPs received for the IN TR. The Debug Capability shall clear this * bit when a ClearFeature(ENDPOINT_HALT) request is received for the endpoint. This field is * valid only when the Debug Capability is in Run Mode (DCR = '1'). When not in Run Mode, this * field shall return '0' when read, and writes will have no effect. Refer to section 7.6.4.3 of xHCI * specification */ #define USB3_XECP_DCCTRL_HIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_HIT_SHIFT)) & USB3_XECP_DCCTRL_HIT_MASK) #define USB3_XECP_DCCTRL_DRC_MASK (0x10U) #define USB3_XECP_DCCTRL_DRC_SHIFT (4U) /*! DRC - DbC Run Change (DRC), RW1C. Default = '0'. This bit shall be set to '1' when DCR bit is * cleared to '0', i.e. by any DbC Port State transition that exits the DbC-Configured state. While * this bit is '1' the Debug Capability Doorbell Register (DCDB) is disabled. Software shall * clear this bit to re-enable the DCDB */ #define USB3_XECP_DCCTRL_DRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DRC_SHIFT)) & USB3_XECP_DCCTRL_DRC_MASK) #define USB3_XECP_DCCTRL_DMaxBSize_MASK (0xFF0000U) #define USB3_XECP_DCCTRL_DMaxBSize_SHIFT (16U) /*! DMaxBSize - Debug Max Burst Size, RO. Default = xHC.Vendor defined. This field identifies the * maximum burst size supported by the bulk endpoints of this DbC implementation */ #define USB3_XECP_DCCTRL_DMaxBSize(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DMaxBSize_SHIFT)) & USB3_XECP_DCCTRL_DMaxBSize_MASK) #define USB3_XECP_DCCTRL_Dev_addr_MASK (0x7F000000U) #define USB3_XECP_DCCTRL_Dev_addr_SHIFT (24U) /*! Dev_addr - Device Address, RO. Default = 0. This field reports the USB device address assigned * to the Debug Device during the enumeration process. This field is valid when the DbC Run bit is * '1' */ #define USB3_XECP_DCCTRL_Dev_addr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_Dev_addr_SHIFT)) & USB3_XECP_DCCTRL_Dev_addr_MASK) #define USB3_XECP_DCCTRL_DCE_MASK (0x80000000U) #define USB3_XECP_DCCTRL_DCE_SHIFT (31U) /*! DCE - Debug Capability Enable, RW. Default = '0'. Setting this bit to a '1' enables xHCI USB * Debug Capability operation. This bit is a '0' if the USB Debug Capability is disabled. Clearing * this bit releases the Root Hub port assigned to the Debug Capability, and terminates any Debug * Capability Transfer or Event Ring activity */ #define USB3_XECP_DCCTRL_DCE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DCE_SHIFT)) & USB3_XECP_DCCTRL_DCE_MASK) /*! @} */ /*! @name XECP_DCST - Debug Capability Status */ /*! @{ */ #define USB3_XECP_DCST_ER_MASK (0x1U) #define USB3_XECP_DCST_ER_SHIFT (0U) /*! ER - Event Ring Not Empty, RO. Default = '0'. When '1', this field indicates that the Debug * Capability Event Ring has a Transfer Event on it. It is automatically cleared to '0' by the xHC * when the Debug Capability Event Ring is empty, i.e. the Debug Capability Enqueue Pointer is * equal to the Debug Capability Event Ring Dequeue Pointer */ #define USB3_XECP_DCST_ER(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCST_ER_SHIFT)) & USB3_XECP_DCST_ER_MASK) #define USB3_XECP_DCST_Dbgp_num_MASK (0xFF000000U) #define USB3_XECP_DCST_Dbgp_num_SHIFT (24U) /*! Dbgp_num - Debug Port Number, RO. Default = 0. This field provides the ID of the Root Hub port * that the Debug Capability has been automatically attached to. The value is 0 when the Debug * Capability is not attached to a Root Hub port */ #define USB3_XECP_DCST_Dbgp_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCST_Dbgp_num_SHIFT)) & USB3_XECP_DCST_Dbgp_num_MASK) /*! @} */ /*! @name XECP_DCPORTSC - Debug Capability Port Status and Control */ /*! @{ */ #define USB3_XECP_DCPORTSC_CCS_MASK (0x1U) #define USB3_XECP_DCPORTSC_CCS_SHIFT (0U) /*! CCS - Current Connect Status, RO. Default = '0'. '1' = A Root Hub port is connected to a Debug * Host and assigned to the Debug Capability. '0' = No Debug Host is present. This value reflects * the current state of the port, and may not correspond to the value reported by the Connect * Status Change (CSC) field in the Port Status Change Event that was generated by a '0' to '1' * transition of this bit. This flag is '0' if Debug Capability Enable (DCE) is '0' */ #define USB3_XECP_DCPORTSC_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_CCS_SHIFT)) & USB3_XECP_DCPORTSC_CCS_MASK) #define USB3_XECP_DCPORTSC_PED_MASK (0x2U) #define USB3_XECP_DCPORTSC_PED_SHIFT (1U) /*! PED - Port Enabled/Disabled, RW. Default = '0'. '1' = Debug Capability Root Hub port is enabled. * '0' = Debug Capability Root Hub port is disabled. This flag shall be set to '1' by a '0' to * '1' transition of CCS or a '1' to '0' transition of the PR. When PED transitions from '1' to * '0' due to the assertion of PR, the port's link shall transition to the Rx.Detect state. This * flag may be used by software to enable or disable the operation of the Root Hub port assigned to * the Debug Capability. The Debug Capability Root Hub port operation may be disabled by a fault * condition (disconnect event or other fault condition, e.g. a LTSSM Polling substate timeout, * tPortConfiguration timeout error, etc.), the assertion of DCPORTSC PR, or by software. When * the port is disabled (PED = '0') the ports link shall enter the SS.Disabled state and remain * there until PED is reasserted ('1') or DCE is negated ('0'). Note that the Root Hub port remains * mapped to Debug Capability while PED = '0'. While PED = '0' the Debug Capability will appear * to be disconnected to the Debug Host. Note, this bit is not affected by PORTSC PR bit * transitions. This field is '0' if DCE or CCS are '0' */ #define USB3_XECP_DCPORTSC_PED(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PED_SHIFT)) & USB3_XECP_DCPORTSC_PED_MASK) #define USB3_XECP_DCPORTSC_PR_MASK (0x10U) #define USB3_XECP_DCPORTSC_PR_SHIFT (4U) /*! PR - Port Reset, RO. Default = '0'. '1' = Port is in Reset. '0' = Port is not in Reset. This bit * is set to '1' when the bus reset sequence as defined in the USB Specification is detected on * the Root Hub port assigned to the Debug capability. It is cleared when the bus reset sequence * is completed by the Debug Host, and the DbC shall transition to the USB Default state. A '0' * to '1' transition of this bit shall clear DCPORTSC PED (0). This field is '0' if DCE or CCS are * '0' */ #define USB3_XECP_DCPORTSC_PR(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PR_SHIFT)) & USB3_XECP_DCPORTSC_PR_MASK) #define USB3_XECP_DCPORTSC_PLS_MASK (0x1E0U) #define USB3_XECP_DCPORTSC_PLS_SHIFT (5U) /*! PLS - Port Link State, RO. Default = RxDetect. This field reflects its current link state. This * field is only relevant when a Debug Host is attached (Debug Port Number > 0). Possible values: * 0: Link is in the U0 State 1: Link is in the U1 State 2: Link is in the U2 State 3: Link is * in the U3 State (Device Suspended) 4: Link is in the Disabled State 5: Link is in the RxDetect * State 6: Link is in the Inactive State 7: Link is in the Polling State 8: Link is in the * Recovery State 9: Link is in the Hot Reset State 10-15: Reserved Note: Transitions between * different states are not reflected until the transition is complete */ #define USB3_XECP_DCPORTSC_PLS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PLS_SHIFT)) & USB3_XECP_DCPORTSC_PLS_MASK) #define USB3_XECP_DCPORTSC_PortSpeed_MASK (0x3C00U) #define USB3_XECP_DCPORTSC_PortSpeed_SHIFT (10U) /*! PortSpeed - Port Speed, RO. Default = '0'. This field identifies the speed of the port. This * field is only relevant when a Debug Host is attached (CCS = '1') in all other cases this field * shall indicate Undefined Speed. Possible values: 0: Undefined Speed 1-15: Protocol Speed ID * (PSI), refer to section 7.2.1 of xHCI specification for the definition of PSIs. Note: The Debug * Capability does not support LS, FS, or HS operation */ #define USB3_XECP_DCPORTSC_PortSpeed(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PortSpeed_SHIFT)) & USB3_XECP_DCPORTSC_PortSpeed_MASK) #define USB3_XECP_DCPORTSC_CSC_MASK (0x20000U) #define USB3_XECP_DCPORTSC_CSC_SHIFT (17U) /*! CSC - Connect Status Change, RW1C. Default = '0'. '1' = Change in CCS. '0' = No change. * Indicates a change has occurred in the ports Current Connect Status. The xHC sets this bit to '1' for * all changes to the Debug Device connect status, even if system software has not cleared an * existing DbC Connect Status Change. For example, the insertion status changes twice before system * software has cleared the changed condition, hardware will be setting an already-set bit * (i.e., the bit will remain '1'). Software shall clear this bit by writing a '1' to it. This field * is '0' if DCE is '0' */ #define USB3_XECP_DCPORTSC_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_CSC_SHIFT)) & USB3_XECP_DCPORTSC_CSC_MASK) #define USB3_XECP_DCPORTSC_PRC_MASK (0x200000U) #define USB3_XECP_DCPORTSC_PRC_SHIFT (21U) /*! PRC - Port Reset Change, RW1C. Default = '0'. This bit is set when reset processing on this port * is complete (i.e. a '1' to '0' transition of PR). '0' = No change. '1' = Reset complete. * Software shall clear this bit by writing a '1' to it. This field is '0' if DCE is '0' */ #define USB3_XECP_DCPORTSC_PRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PRC_SHIFT)) & USB3_XECP_DCPORTSC_PRC_MASK) #define USB3_XECP_DCPORTSC_PLC_MASK (0x400000U) #define USB3_XECP_DCPORTSC_PLC_SHIFT (22U) /*! PLC - Port Link State Change, RW1C. Default = '0'. This flag is set to '1' due to the following * PLS transitions: U0 -> U3 (Suspend signaling detected from Debug Host) U3 -> U0 (Resume * complete) Polling -> Disabled (Training Error) Ux or Recovery -> Inactive (Error) Software shall * clear this bit by writing a '1' to it. This field is '0' if DCE is '0' */ #define USB3_XECP_DCPORTSC_PLC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PLC_SHIFT)) & USB3_XECP_DCPORTSC_PLC_MASK) #define USB3_XECP_DCPORTSC_CEC_MASK (0x800000U) #define USB3_XECP_DCPORTSC_CEC_SHIFT (23U) /*! CEC - Port Config Error Change, RW1C. Default = '0'. This flag indicates that the port failed to * configure its link partner. '0' = No change. '1' = Port Config Error detected. Software shall * clear this bit by writing a '1' to it */ #define USB3_XECP_DCPORTSC_CEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_CEC_SHIFT)) & USB3_XECP_DCPORTSC_CEC_MASK) /*! @} */ /*! @name XECP_DCCP_LOW - Debug Capability Context Pointer */ /*! @{ */ #define USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_MASK (0xFFFFFFF0U) #define USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_SHIFT (4U) /*! DBGP_CNTX_PTR_L - Debug Capability Context Pointer Register, RW. Default = 0. This field defines * the high order bits of the start address of the Debug Capability Context data structure * (refer to section 7.6.9 of xHCI specification) associated with the Debug Capability. Software shall * initialize this register before setting the Debug Capability Enable bit in the Debug * Capability Control Register to '1' */ #define USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_SHIFT)) & USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_MASK) /*! @} */ /*! @name XECP_DCCP_HIGH - Debug Capability Context Pointer */ /*! @{ */ #define USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_MASK (0xFFFFFFFFU) #define USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_SHIFT (0U) /*! DBGP_CNTX_PTR_H - Debug Capability Context Pointer Register, RW. Default = 0. This field defines * the high order bits of the start address of the Debug Capability Context data structure * (refer to section 7.6.9 of xHCI specification) associated with the Debug Capability. Software shall * initialize this register before setting the Debug Capability Enable bit in the Debug * Capability Control Register to '1' */ #define USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_SHIFT)) & USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_MASK) /*! @} */ /*! @name XECP_DCDDI1 - Debug Capability Device Descriptor Info */ /*! @{ */ #define USB3_XECP_DCDDI1_DbC_PROT_MASK (0xFFU) #define USB3_XECP_DCDDI1_DbC_PROT_SHIFT (0U) /*! DbC_PROT - DbC Protocol, RW. This field is presented by the Debug Device in the USB Interface * Descriptor bInterfaceProtocol field. 0: Debug Target vendor defined. 1: GNU Remote Debug Command * Set supported. 2-255: Reserved */ #define USB3_XECP_DCDDI1_DbC_PROT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI1_DbC_PROT_SHIFT)) & USB3_XECP_DCDDI1_DbC_PROT_MASK) #define USB3_XECP_DCDDI1_VID_MASK (0xFFFF0000U) #define USB3_XECP_DCDDI1_VID_SHIFT (16U) /*! VID - Vendor ID, RW. This field is presented by the Debug Device in the USB Device Descriptor idVendor field */ #define USB3_XECP_DCDDI1_VID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI1_VID_SHIFT)) & USB3_XECP_DCDDI1_VID_MASK) /*! @} */ /*! @name XECP_DCDDI2 - The Debug Capability Device Descriptor */ /*! @{ */ #define USB3_XECP_DCDDI2_PROD_ID_MASK (0xFFFFU) #define USB3_XECP_DCDDI2_PROD_ID_SHIFT (0U) /*! PROD_ID - Product ID, RW. This field is presented by the Debug Device in the USB Device Descriptor idProduct field */ #define USB3_XECP_DCDDI2_PROD_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI2_PROD_ID_SHIFT)) & USB3_XECP_DCDDI2_PROD_ID_MASK) #define USB3_XECP_DCDDI2_DEV_REV_MASK (0xFFFF0000U) #define USB3_XECP_DCDDI2_DEV_REV_SHIFT (16U) /*! DEV_REV - Device Revision, RW. This field is presented by the Debug Device in the USB Device Descriptor bcdDevice field */ #define USB3_XECP_DCDDI2_DEV_REV(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI2_DEV_REV_SHIFT)) & USB3_XECP_DCDDI2_DEV_REV_MASK) /*! @} */ /*! @name USB_CONF - Global Configuration */ /*! @{ */ #define USB3_USB_CONF_CFGRST_MASK (0x1U) #define USB3_USB_CONF_CFGRST_SHIFT (0U) /*! CFGRST - Reset USB device configuration. Writing '1' to this bit resets USB device * configuration, leaving only EP0 IN/OUT active (all other EP-related registers will be loaded with default * values). Any configuration/interface change, including adding new IF, must be preceded with * configuration reset, adding current IF's as well as new IF. Writing '0' has no effect. This bit * is always '0' while reading */ #define USB3_USB_CONF_CFGRST(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CFGRST_SHIFT)) & USB3_USB_CONF_CFGRST_MASK) #define USB3_USB_CONF_CFGSET_MASK (0x2U) #define USB3_USB_CONF_CFGSET_SHIFT (1U) /*! CFGSET - Set Configuration. Software writes '1' to this bit when it receives SET_CONFIGURATION * request with non-zero configuration number. CPU sets this bit after setting requested * configuration and before setting REQ_CMPL bit in the EP_CMD register. Configuration will be set * internally in the hardware when REQ_CMPL bit will be set. Writing '0' has no effect. The actual * configuration status can be checked in the USB_STS register. This bit is always '0' while reading */ #define USB3_USB_CONF_CFGSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CFGSET_SHIFT)) & USB3_USB_CONF_CFGSET_MASK) #define USB3_USB_CONF_RESERVED0_MASK (0x4U) #define USB3_USB_CONF_RESERVED0_SHIFT (2U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_CONF_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_RESERVED0_SHIFT)) & USB3_USB_CONF_RESERVED0_MASK) #define USB3_USB_CONF_USB3DIS_MASK (0x8U) #define USB3_USB_CONF_USB3DIS_SHIFT (3U) /*! USB3DIS - Disconnect USB device in SuperSpeed. Writing '1' to this bit disconnects USB in Super * Speed. The actual USB connection status in the SS mode can be checked in the USB_STS register. * If link is in U3 (SuperSpeed PHY clock is disabled) while software writes USB3DIS bit, first * the hardware automatically wakes up the PHY to the P2 to turn on the PHY clock (clklink), and * second, all operations related to device disconnection cease. Writing '0' has no effect. To * connect disconnected device, CPU performs software reset (UCB_CFG.SWRST). This bit is always '0' * while reading */ #define USB3_USB_CONF_USB3DIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_USB3DIS_SHIFT)) & USB3_USB_CONF_USB3DIS_MASK) #define USB3_USB_CONF_USB2DIS_MASK (0x10U) #define USB3_USB_CONF_USB2DIS_SHIFT (4U) /*! USB2DIS - Disconnect USB device in HS/FS. Writing '1' to this bit disconnects USB in HS/FS. The * actual USB connection status in HS/FS can be checked in the USB_STS register. Writing '0' has * no effect. To connect disconnected device, CPU performs software reset (UCB_CFG.SWRST). This * bit is always '0' while reading */ #define USB3_USB_CONF_USB2DIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_USB2DIS_SHIFT)) & USB3_USB_CONF_USB2DIS_MASK) #define USB3_USB_CONF_LENDIAN_MASK (0x20U) #define USB3_USB_CONF_LENDIAN_SHIFT (5U) /*! LENDIAN - Little Endian access. Writing '1' to this bit sets Little Endian byte order for SFRs * access. By default (after hardware reset), USBSS-DEV acts as little-endian device. Writing '0' * has no effect. When both LENDIAN and BENDIAN bits are set to '1' while writing to USB_CONF * register, the device behaviour is udefined. This bit is always '0' while reading */ #define USB3_USB_CONF_LENDIAN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LENDIAN_SHIFT)) & USB3_USB_CONF_LENDIAN_MASK) #define USB3_USB_CONF_BENDIAN_MASK (0x40U) #define USB3_USB_CONF_BENDIAN_SHIFT (6U) /*! BENDIAN - Big Endian Access. Writing '1' to this bit sets Big Endian byte order for SFRs access. * Writing '0' has no effect. When both LENDIAN and BENDIAN bits are set to '1' while writing to * USB_CONF register, the device behaviour is udefined. This bit is always '0' while reading */ #define USB3_USB_CONF_BENDIAN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_BENDIAN_SHIFT)) & USB3_USB_CONF_BENDIAN_MASK) #define USB3_USB_CONF_SWRST_MASK (0x80U) #define USB3_USB_CONF_SWRST_SHIFT (7U) /*! SWRST - Device software reset. When set to 1, the entire USBSS-DEV is reset. The SWRST resets * most flip-flops in entire USBSS-DEV. This bit is also used to connect disconnected device. * Writing '0' has no effect */ #define USB3_USB_CONF_SWRST(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_SWRST_SHIFT)) & USB3_USB_CONF_SWRST_MASK) #define USB3_USB_CONF_DSING_MASK (0x100U) #define USB3_USB_CONF_DSING_SHIFT (8U) /*! DSING - Singular DMA transfer mode. When set to '1', all DMA transfers are singular: when single * TRB chain ends, the transfer ends. Writing '0' has no effect. This bit is always '0' while * reading. The status of this settings can be check in the USB_STS.DTRANS bit */ #define USB3_USB_CONF_DSING(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DSING_SHIFT)) & USB3_USB_CONF_DSING_MASK) #define USB3_USB_CONF_DMULT_MASK (0x200U) #define USB3_USB_CONF_DMULT_SHIFT (9U) /*! DMULT - Multiple DMA transfers mode. When set to '1', all DMA transfers are multiple: when * current TRB chain ends, the DMA checks if next TRB is ready and, if owner bit (C) is correct, * starts next chain; otherwise, it stops current EP transfer. Writing '0' has no effect. This bit is * always '0' while reading. The status of this settings can be check in the USB_STS.DTRANS bit */ #define USB3_USB_CONF_DMULT(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DMULT_SHIFT)) & USB3_USB_CONF_DMULT_MASK) #define USB3_USB_CONF_DMAOFFEN_MASK (0x400U) #define USB3_USB_CONF_DMAOFFEN_SHIFT (10U) /*! DMAOFFEN - DMA clock turn-off enable. Writing '1' to this bit enables DMA clock turning-off when * device exits U0 link state in SuperSpeed mode. When both DMAOFFDS and DMAOFFEN bits are set * to '1' while writing to USB_CONF register, the device behaviour is udefined. This bit is always * '0' while reading */ #define USB3_USB_CONF_DMAOFFEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DMAOFFEN_SHIFT)) & USB3_USB_CONF_DMAOFFEN_MASK) #define USB3_USB_CONF_DMAOFFDS_MASK (0x800U) #define USB3_USB_CONF_DMAOFFDS_SHIFT (11U) /*! DMAOFFDS - DMA clock turn-off disable. Writing '1' to this bit disables DMA clock turning-off * when device exits U0 link state in SuperSpeed mode. When both DMAOFFDS and DMAOFFEN bits are set * to '1' while writing to USB_CONF register, the device behaviour is udefined. This bit is * always '0' while reading */ #define USB3_USB_CONF_DMAOFFDS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DMAOFFDS_SHIFT)) & USB3_USB_CONF_DMAOFFDS_MASK) #define USB3_USB_CONF_CFORCE_FS_MASK (0x1000U) #define USB3_USB_CONF_CFORCE_FS_SHIFT (12U) /*! CFORCE_FS - Clear Force Full Speed. Writing '1' to this bit stop forcing Full Speed when * USBSS-DEV operates in USB2.0 mode (stop disabling High Speed). When both SFORCE_FS and CFORCE_FS bits * are set to '1' while writing to USB_CONF register, the device behaviour is udefined. The * status of this settings can be check in the USB_STS.DISABLE_HS bit. This bit is always '0' while * reading */ #define USB3_USB_CONF_CFORCE_FS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CFORCE_FS_SHIFT)) & USB3_USB_CONF_CFORCE_FS_MASK) #define USB3_USB_CONF_SFORCE_FS_MASK (0x2000U) #define USB3_USB_CONF_SFORCE_FS_SHIFT (13U) /*! SFORCE_FS - Set Force Full Speed. Writing '1' to this bit forces Full Speed when USBSS-DEV * operates in USB2.0 mode (disables High Speed). When both SFORCE_FS and CFORCE_FS bits are set to * '1' while writing to USB_CONF register, the device behaviour is udefined. The status of this * settings can be check in the USB_STS.DISABLE_HS bit. This bit is always '0' while reading */ #define USB3_USB_CONF_SFORCE_FS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_SFORCE_FS_SHIFT)) & USB3_USB_CONF_SFORCE_FS_MASK) #define USB3_USB_CONF_DEVEN_MASK (0x4000U) #define USB3_USB_CONF_DEVEN_SHIFT (14U) /*! DEVEN - Device enable. After Power-On-Reset the USBSS_DEV is disconnected from the USB bus. To * connect the device into the USB bus the software has to write '1' to DEVEN bit - this couse * connection of the VBUS input to the internal device logic and connetion to the USB bus as a * result (inside of USBSS_DEV an internal VBUS is used which which is the and gate: VBUS input AND * USB_STS.DEVS bit in SFRs). Writing '1' to the DEVEN bit sets to '1' the USB_STS.DEVS bit. * Writing '0' has no effect. This bit is always '0' while reading */ #define USB3_USB_CONF_DEVEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DEVEN_SHIFT)) & USB3_USB_CONF_DEVEN_MASK) #define USB3_USB_CONF_DEVDS_MASK (0x8000U) #define USB3_USB_CONF_DEVDS_SHIFT (15U) /*! DEVDS - Device disable. Writing '1' to the DEVDS bit sets to '0' the USB_STS.DEVS bit. Check * also the DEVEN bit description. Writing '0' has no effect. This bit is always '0' while reading */ #define USB3_USB_CONF_DEVDS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DEVDS_SHIFT)) & USB3_USB_CONF_DEVDS_MASK) #define USB3_USB_CONF_L1EN_MASK (0x10000U) #define USB3_USB_CONF_L1EN_SHIFT (16U) /*! L1EN - L1 LPM state entry enable (device side, HS/FS mode only). Writing '1' to this bit enables * USB2.0 LPM to enter L1 state. Status of this bit can be checked in the USB_STS register. * Writing '0' has no effect. When both L1EN and L1DS bits are set to '1' while writing to USB_CONF * register, the device behaviour is udefined. This bit is always '0' while reading */ #define USB3_USB_CONF_L1EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_L1EN_SHIFT)) & USB3_USB_CONF_L1EN_MASK) #define USB3_USB_CONF_L1DS_MASK (0x20000U) #define USB3_USB_CONF_L1DS_SHIFT (17U) /*! L1DS - L1 LPM state entry disable (HS/FS mode only). Writing '1' to this bit disables USB2.0 LPM * from entering L1 state. Status of this bit can be checked in the USB_STS register. Writing * '0' has no effect. When both L1EN and L1DS bits are set to '1' while writing to USB_CONF * register, the device behaviour is udefined. This bit is always '0' while reading */ #define USB3_USB_CONF_L1DS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_L1DS_SHIFT)) & USB3_USB_CONF_L1DS_MASK) #define USB3_USB_CONF_CLK2OFFEN_MASK (0x40000U) #define USB3_USB_CONF_CLK2OFFEN_SHIFT (18U) /*! CLK2OFFEN - USB 2.0 clock gate disable. Writing '1' to this bit enables hsfs clock turning-off * when device enters L2 LPM state in HS/FS mode. The actual 'USB 2.0 clock gate' status in can be * checked in the USB_STS.USB2OFF register. When both CLK2OFFDS and CLK2OFFEN bits are set to * '1' while writing to USB_CONF register, the device behaviour is udefined. This bit is always '0' * while reading */ #define USB3_USB_CONF_CLK2OFFEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK2OFFEN_SHIFT)) & USB3_USB_CONF_CLK2OFFEN_MASK) #define USB3_USB_CONF_CLK2OFFDS_MASK (0x80000U) #define USB3_USB_CONF_CLK2OFFDS_SHIFT (19U) /*! CLK2OFFDS - USB 2.0 clock gate enable. Writing '1' to this bit disables hsfs clock turning-off * when device enters L2 LPM state in HS/FS mode. The actual 'USB 2.0 clock gate' status in can be * checked in the USB_STS.USB2OFF register. When both CLK2OFFDS and CLK2OFFEN bits are set to * '1' while writing to USB_CONF register, the device behaviour is udefined. This bit is always '0' * while reading */ #define USB3_USB_CONF_CLK2OFFDS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK2OFFDS_SHIFT)) & USB3_USB_CONF_CLK2OFFDS_MASK) #define USB3_USB_CONF_LGO_L0_MASK (0x100000U) #define USB3_USB_CONF_LGO_L0_SHIFT (20U) /*! LGO_L0 - L0 LPM state entry request (HS/FS mode only). Writing '1' will trigger an attempt to * perform transition to L0 LPM state. This bit will be automatically cleared to '0' after LPM * enter L0 state. Result of the request (LPM enters L0 or not) can be verified by reading LPMST (LPM * state) field in USB_STS register. Writing '0' has no effect. If the LPM is suspended (L2 * state) and CPU set this bit to'1', upstream will start driving resume signaling to indicate remote * wakeup */ #define USB3_USB_CONF_LGO_L0(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_L0_SHIFT)) & USB3_USB_CONF_LGO_L0_MASK) #define USB3_USB_CONF_CLK3OFFEN_MASK (0x200000U) #define USB3_USB_CONF_CLK3OFFEN_SHIFT (21U) /*! CLK3OFFEN - USB 3.0 clock gate disable. Writing '1' to this bit enables pclk clock turning-off * when device enters U3 link state in SS mode. The actual 'USB 3.0 clock gate' status in can be * checked in the USB_STS.USB3OFF register. When both CLK3OFFDS and CLK3OFFEN bits are set to '1' * while writing to USB_CONF register, the device behaviour is udefined. This bit is always '0' * while reading */ #define USB3_USB_CONF_CLK3OFFEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK3OFFEN_SHIFT)) & USB3_USB_CONF_CLK3OFFEN_MASK) #define USB3_USB_CONF_CLK3OFFDS_MASK (0x400000U) #define USB3_USB_CONF_CLK3OFFDS_SHIFT (22U) /*! CLK3OFFDS - USB 3.0 clock gate enable. Writing '1' to this bit disables pclk clock turning-off * when device enters U3 link state in SS mode. The actual 'USB 3.0 clock gate' status in can be * checked in the USB_STS.USB3OFF register. When both CLK3OFFDS and CLK3OFFEN bits are set to '1' * while writing to USB_CONF register, the device behaviour is udefined. This bit is always '0' * while reading */ #define USB3_USB_CONF_CLK3OFFDS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK3OFFDS_SHIFT)) & USB3_USB_CONF_CLK3OFFDS_MASK) #define USB3_USB_CONF_RESERVED1_MASK (0x800000U) #define USB3_USB_CONF_RESERVED1_SHIFT (23U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_CONF_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_RESERVED1_SHIFT)) & USB3_USB_CONF_RESERVED1_MASK) #define USB3_USB_CONF_U1EN_MASK (0x1000000U) #define USB3_USB_CONF_U1EN_SHIFT (24U) /*! U1EN - U1 state entry enable (device side, SS mode only), Writing '1' to this bit enables link * layer to enter U1 state. Status of this bit can be checked in the USB_STS register. Writing '0' * has no effect. When both U1EN and U1DS bits are set to '1' while writing to USB_CONF * register, none of the operations associated with these bits will be performed. This bit is always '0' * while reading */ #define USB3_USB_CONF_U1EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U1EN_SHIFT)) & USB3_USB_CONF_U1EN_MASK) #define USB3_USB_CONF_U1DS_MASK (0x2000000U) #define USB3_USB_CONF_U1DS_SHIFT (25U) /*! U1DS - U1 state entry disable (SS mode only). Writing '1' to this bit disables link layer from * entering U1 state. Status of this bit can be checked in the USB_STS register. Writing '0' has * no effect. When both U1EN and U1DS bits are set to '1' while writing to USB_CONF register, none * of the operations associated with these bits will be performed. This bit is always '0' while * reading */ #define USB3_USB_CONF_U1DS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U1DS_SHIFT)) & USB3_USB_CONF_U1DS_MASK) #define USB3_USB_CONF_U2EN_MASK (0x4000000U) #define USB3_USB_CONF_U2EN_SHIFT (26U) /*! U2EN - U2 state entry enable (device side, SS mode only). Writing '1' to this bit enables link * layer to enter U2 state. Status of this bit can be checked in the USB_STS register. Writing '0' * has no effect. When both U2EN and U2DS bits are set to '1' while writing to USB_CONF * register, the device behaviour is udefined. This bit is always '0' while reading */ #define USB3_USB_CONF_U2EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U2EN_SHIFT)) & USB3_USB_CONF_U2EN_MASK) #define USB3_USB_CONF_U2DS_MASK (0x8000000U) #define USB3_USB_CONF_U2DS_SHIFT (27U) /*! U2DS - U2 state entry disable (SS mode only). Writing '1' to this bit disables link layer from * entering U2 state. Status of this bit can be checked in the USB_STS register. When both U2EN * and U2DS bits are set to '1' while writing to USB_CONF register, the device behaviour is * udefined. Writing '0' has no effect. This bit is always '0' while reading */ #define USB3_USB_CONF_U2DS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U2DS_SHIFT)) & USB3_USB_CONF_U2DS_MASK) #define USB3_USB_CONF_LGO_U0_MASK (0x10000000U) #define USB3_USB_CONF_LGO_U0_SHIFT (28U) /*! LGO_U0 - U0 state entry request (SS mode only). Writing '1' will trigger an attempt to perform * transition to U0 state. If the link is suspended (U3 state) and CPU set this bit to'1', link * will start driving resume signaling on its upstream link to indicate remote wakeup. The Function * Wake Notification should be send using USB_CMD.SDNFW bit. Writing '0' has no effect */ #define USB3_USB_CONF_LGO_U0(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_U0_SHIFT)) & USB3_USB_CONF_LGO_U0_MASK) #define USB3_USB_CONF_LGO_U1_MASK (0x20000000U) #define USB3_USB_CONF_LGO_U1_SHIFT (29U) /*! LGO_U1 - U1 state entry request (SS mode only). Writing '1' will trigger an attempt to perform * transition to U1 state. This bit will be automatically cleared to '0' after link layer finishes * U1 request. Result of the request (link layer enters U1 or not) can be verified by reading * LTS (link state) field in USB_STS register. Writing '1' has no effect when USB_STS.LGOU1ENS is * set to '0'. Writing '0' has no effect */ #define USB3_USB_CONF_LGO_U1(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_U1_SHIFT)) & USB3_USB_CONF_LGO_U1_MASK) #define USB3_USB_CONF_LGO_U2_MASK (0x40000000U) #define USB3_USB_CONF_LGO_U2_SHIFT (30U) /*! LGO_U2 - U2 state entry request (SS mode only). Writing '1' will trigger an attempt to perform * transition to U2 state. This bit will be automatically cleared to '0' after link layer finishes * U2 request. Result of the request (link layer enters U2 or not) can be verified by reading * LTS (link state) field in USB_STS register. Writing '1' has no effect when USB_STS.LGOU2ENS is * set to '0'. Writing '0' has no effect */ #define USB3_USB_CONF_LGO_U2(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_U2_SHIFT)) & USB3_USB_CONF_LGO_U2_MASK) #define USB3_USB_CONF_LGO_SSINACT_MASK (0x80000000U) #define USB3_USB_CONF_LGO_SSINACT_SHIFT (31U) /*! LGO_SSINACT - SS.Inactive state entry request (SS mode only). This bit can be used only if * USBSS-DEV is part of the CDNS USB OTG Controller (USB_CAP.OTG_READY bit is 1 while reading). In * other cases should not be used and returns 0 when read. Writing '1' will trigger an attempt to * perform transition to SS.Inactive state. Should be used only if Link is in U0 or Recovery state. * This bit will be automatically cleared to '0' after link layer finishes SS.Inactive request. * Result of the request (link layer enters SS.Inactive or not) can be verified by reading LTS * (link state) field in USB_STS register. Writing '0' has no effect */ #define USB3_USB_CONF_LGO_SSINACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_SSINACT_SHIFT)) & USB3_USB_CONF_LGO_SSINACT_MASK) /*! @} */ /*! @name USB_STS - Global Status */ /*! @{ */ #define USB3_USB_STS_CFGSTS_MASK (0x1U) #define USB3_USB_STS_CFGSTS_SHIFT (0U) /*! CFGSTS - Configuration status. 1 - device is in the configured state 0 - device is not * configured This bit set during SET_CONFIGURATION request means that status stage of this request was * finished successfully, thus device configuration was finished successfully */ #define USB3_USB_STS_CFGSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_CFGSTS_SHIFT)) & USB3_USB_STS_CFGSTS_MASK) #define USB3_USB_STS_MEM_OV_MASK (0x2U) #define USB3_USB_STS_MEM_OV_SHIFT (1U) /*! MEM_OV - On-chip memory overflow. 0 - On-chip memory status OK 1 - On-chip memory overflow * Memory overflow may occur if, during enumeration (SET_CONFIGURATION request) device software will * try to turn on too many endpoints or will try to set too much endpoinds buffers (see * EP_CFG.BUFFERING). After each completion of enumeration software should check this bit, and when a * memory overflow occurred, software must delete current configuration (using USB_CONF.CFGRST bit) * and then set the one that requires less on-chip memory. For available memory calculation, the * CDNS_USBSSDEV_ATTACHED_MEM_SIZE define parameter is used */ #define USB3_USB_STS_MEM_OV(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_MEM_OV_SHIFT)) & USB3_USB_STS_MEM_OV_MASK) #define USB3_USB_STS_USB3CONS_MASK (0x4U) #define USB3_USB_STS_USB3CONS_SHIFT (2U) /*! USB3CONS - SuperSpeed connection status. 0 - USB in SuperSpeed mode disconnected 1 - USB in SuperSpeed mode connected */ #define USB3_USB_STS_USB3CONS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_USB3CONS_SHIFT)) & USB3_USB_STS_USB3CONS_MASK) #define USB3_USB_STS_DTRANS_MASK (0x8U) #define USB3_USB_STS_DTRANS_SHIFT (3U) /*! DTRANS - DMA transfer configuration status. 0 - single request - Single TRB chain. Single * request (DRDY/Doorbell) triggers DMA, which transfers single TRB chain only and ends the EP * transfer. 1 - single request - Multiple TRB chain. Single request (DRDY/Doorbell) triggers DMA which * transfers TRB chains until the owner of the new chain is not DMA (this causes a TRB error * interrupt). This DMA transfer configuration settings can be changed by using bits USB_CONF.DSING * and USB_CONF.DMULT */ #define USB3_USB_STS_DTRANS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DTRANS_SHIFT)) & USB3_USB_STS_DTRANS_MASK) #define USB3_USB_STS_USBSPEED_MASK (0x70U) #define USB3_USB_STS_USBSPEED_SHIFT (4U) /*! USBSPEED - Device speed: 0: undef., 1: LowSpeed (not supported), 2: FullSpeed, 3: HighSpeed, 4: SuperSpeed, 5-7: Reserved */ #define USB3_USB_STS_USBSPEED(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_USBSPEED_SHIFT)) & USB3_USB_STS_USBSPEED_MASK) #define USB3_USB_STS_ENDIAN_MIRROR_MASK (0x80U) #define USB3_USB_STS_ENDIAN_MIRROR_SHIFT (7U) /*! ENDIAN_MIRROR - Little/Big Endian byte order for SFR access. 0 - Little Endian order (default * after hardware reset) 1 - Big Endian order Endian byte order for SFR access can be changed by * setting BENDIAN or LEDNIAN bits in USB_CONF */ #define USB3_USB_STS_ENDIAN_MIRROR(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_ENDIAN_MIRROR_SHIFT)) & USB3_USB_STS_ENDIAN_MIRROR_MASK) #define USB3_USB_STS_CLK2OFF_MASK (0x100U) #define USB3_USB_STS_CLK2OFF_SHIFT (8U) /*! CLK2OFF - HS/FS clock turn-off status. When CLK2OFF bit is '0', the utmisuspendm output signal * is not set low in USB2.0 suspend state (L2 state), thus USB2.0 PHY does not turn off the hsfs * clock 0 - hsfs clock is always on 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled * (default after hardware reset) */ #define USB3_USB_STS_CLK2OFF(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_CLK2OFF_SHIFT)) & USB3_USB_STS_CLK2OFF_MASK) #define USB3_USB_STS_CLK3OFF_MASK (0x200U) #define USB3_USB_STS_CLK3OFF_SHIFT (9U) /*! CLK3OFF - PCLK clock turn-off status. When CLK3OFF bit is '0', the phypowerdown output signal is * not set to '11' in U3 link state, thus USB3.0 PHY does not turn off the pclk clock. 0 - pclk * clock is always on 1 - pclk clock turn-off in U3 (SS mode) is enabled (default after hardware * reset) */ #define USB3_USB_STS_CLK3OFF(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_CLK3OFF_SHIFT)) & USB3_USB_STS_CLK3OFF_MASK) #define USB3_USB_STS_IN_RST_MASK (0x400U) #define USB3_USB_STS_IN_RST_SHIFT (10U) /*! IN_RST - Controler in reset state. This bit indicate that whole (in case of POR) or part of * controller (in case of SWRST or USB resets) currently is in reset state. As controller has * registers in both clock domains (system, and USB), internal reset synchronization between these * domains may take longer than the cause of the reset (e.g active reset_n input). Thus it is * recommended to check if controller is not in reset state, before software starts its operations * (especially after POR). 0 - Internal reset is active 1 - Internal reset is not active and controller * is fully operational */ #define USB3_USB_STS_IN_RST(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_IN_RST_SHIFT)) & USB3_USB_STS_IN_RST_MASK) #define USB3_USB_STS_RESERVED0_MASK (0x3800U) #define USB3_USB_STS_RESERVED0_SHIFT (11U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_STS_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_RESERVED0_SHIFT)) & USB3_USB_STS_RESERVED0_MASK) #define USB3_USB_STS_DEVS_MASK (0x4000U) #define USB3_USB_STS_DEVS_SHIFT (14U) /*! DEVS - Device enable Status 0 - USB device is disabled (VBUS input is disconnected from internal * logic) 1 - USB device is enabled (VBUS input is connected to the internal logic) This bit can * be changed by setting DEVEN or DEVDS bits in USB_CONF */ #define USB3_USB_STS_DEVS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DEVS_SHIFT)) & USB3_USB_STS_DEVS_MASK) #define USB3_USB_STS_ADDRESSED_MASK (0x8000U) #define USB3_USB_STS_ADDRESSED_SHIFT (15U) /*! ADDRESSED - Address status: 0 - USB device is default state 1 - USB device is at least in * address state (Function Address was set by the SW) */ #define USB3_USB_STS_ADDRESSED(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_ADDRESSED_SHIFT)) & USB3_USB_STS_ADDRESSED_MASK) #define USB3_USB_STS_L1ENS_MASK (0x10000U) #define USB3_USB_STS_L1ENS_SHIFT (16U) /*! L1ENS - L1 LPM state enable status (valid for HS/FS mode only). 0 - Entering to L1 LPM state * disabled 1 - Entering to L1 LPM state enabled */ #define USB3_USB_STS_L1ENS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_L1ENS_SHIFT)) & USB3_USB_STS_L1ENS_MASK) #define USB3_USB_STS_VBUSS_MASK (0x20000U) #define USB3_USB_STS_VBUSS_SHIFT (17U) /*! VBUSS - Internal VBUS connection status. 0 - internal VBUS is not detected 1 - internal VBUS is detected */ #define USB3_USB_STS_VBUSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_VBUSS_SHIFT)) & USB3_USB_STS_VBUSS_MASK) #define USB3_USB_STS_LPMST_MASK (0xC0000U) #define USB3_USB_STS_LPMST_SHIFT (18U) /*! LPMST - HS/FS LPM state (valid for HS/FS mode only). This field reflects USBSS-DEV current LPM * (used in HS/FS mode) state: 0 - L0 State 1 - L1 State 2 - L2 State 3 - L3 State */ #define USB3_USB_STS_LPMST(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_LPMST_SHIFT)) & USB3_USB_STS_LPMST_MASK) #define USB3_USB_STS_USB2CONS_MASK (0x100000U) #define USB3_USB_STS_USB2CONS_SHIFT (20U) /*! USB2CONS - HS/FS mode connection enable status (valid for HS/FS mode only). 0 - the disconnect * bit for HS/FS mode is set (USB_CONF.USB2DIS) 1 - the disconnect bit for HS/FS mode is not set * (device can be connected in this mode) The actual connection status can be checked in the * USB_STS.USBSPEED */ #define USB3_USB_STS_USB2CONS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_USB2CONS_SHIFT)) & USB3_USB_STS_USB2CONS_MASK) #define USB3_USB_STS_DISABLE_HS_MASK (0x200000U) #define USB3_USB_STS_DISABLE_HS_SHIFT (21U) /*! DISABLE_HS - DisableHS status (valid for HS/FS mode only) 0 - High Speed operations in USB2.0 * (FS/HS) mode not disabled 1 - High Speed operations in USB2.0 (FS/HS) mode disabled */ #define USB3_USB_STS_DISABLE_HS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DISABLE_HS_SHIFT)) & USB3_USB_STS_DISABLE_HS_MASK) #define USB3_USB_STS_RESERVED1_MASK (0xC00000U) #define USB3_USB_STS_RESERVED1_SHIFT (22U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_STS_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_RESERVED1_SHIFT)) & USB3_USB_STS_RESERVED1_MASK) #define USB3_USB_STS_U1ENS_MASK (0x1000000U) #define USB3_USB_STS_U1ENS_SHIFT (24U) /*! U1ENS - U1 state enable status (valid in SS mode only): 0 - Entering to U1 state disabled 1 - Entering to U1 state enabled */ #define USB3_USB_STS_U1ENS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_U1ENS_SHIFT)) & USB3_USB_STS_U1ENS_MASK) #define USB3_USB_STS_U2ENS_MASK (0x2000000U) #define USB3_USB_STS_U2ENS_SHIFT (25U) /*! U2ENS - U2 state enable status (valid in SS mode only): 0 - Entering to U2 state disabled 1 - Entering to U2 state enabled */ #define USB3_USB_STS_U2ENS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_U2ENS_SHIFT)) & USB3_USB_STS_U2ENS_MASK) #define USB3_USB_STS_LST_MASK (0x3C000000U) #define USB3_USB_STS_LST_SHIFT (26U) /*! LST - SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current SuperSpeed link state: * 0 - U0 State 1 - U1 State 2 - U2 State 3 - U3 State (Device Suspended) 4 - Disabled State 5 - * RxDetect State 6 - Inactive State 7 - Polling State 8 - Recovery State 9 - Hot Reset State 10 * - Compliance Mode State 11 - Loopback State 12:14 - Reserved 15 - Uninitialized */ #define USB3_USB_STS_LST(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_LST_SHIFT)) & USB3_USB_STS_LST_MASK) #define USB3_USB_STS_DMAOFF_MASK (0x40000000U) #define USB3_USB_STS_DMAOFF_SHIFT (30U) /*! DMAOFF - DMA clock turn-off status. DMA clock turn-off/enable status: 0 - DMA clock is always on * (default after hardware reset) 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled */ #define USB3_USB_STS_DMAOFF(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DMAOFF_SHIFT)) & USB3_USB_STS_DMAOFF_MASK) #define USB3_USB_STS_ENDIAN_MASK (0x80000000U) #define USB3_USB_STS_ENDIAN_SHIFT (31U) /*! ENDIAN - SFR Endian status. Little/Big Endian byte order for SFR access: 0 - Little Endian order * (default after hardware reset) 1 - Big Endian order */ #define USB3_USB_STS_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_ENDIAN_SHIFT)) & USB3_USB_STS_ENDIAN_MASK) /*! @} */ /*! @name USB_CMD - Global Command */ /*! @{ */ #define USB3_USB_CMD_SET_ADDR_MASK (0x1U) #define USB3_USB_CMD_SET_ADDR_SHIFT (0U) /*! SET_ADDR - Set Function Address. Writing the value '1 'to this bit causes the device is assigned * to the USB Function Address according to the FADDR field. The device address must be saved by * software when operating SET_ADDRESS request. After saving device address, software should set * the EP_CMD.ERDY bit (as with all other requests) to quit the setup phase and then set bit * EP_CMD.REQ_CMPL to confirm the status of the host phase. Writing '0 'has no effect. This bit is * always '0' while reading */ #define USB3_USB_CMD_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SET_ADDR_SHIFT)) & USB3_USB_CMD_SET_ADDR_MASK) #define USB3_USB_CMD_FADDR_MASK (0xFEU) #define USB3_USB_CMD_FADDR_SHIFT (1U) /*! FADDR - Function Address. This field is saved to the device only when the field SET_ADDR is set * '1 ' during write to USB_CMD register. Software is responsible for entering the address of the * device during SET_ADDRESS request service. This field should be set immediately after the * SETUP packet is decoded, and prior to confirmation of the status phase (what is done by bit * EP_CMD.REQ_CMPL) Verify that the device successfully completed the SET_ADDRESS request and is in * ADRESSED state (as defined in USB3 spec) can be realized by checking the bit USB_STS. ADRESSED. * USB_CMD.FADDR field can also be read at any time. This field is always '0' while reading */ #define USB3_USB_CMD_FADDR(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_FADDR_SHIFT)) & USB3_USB_CMD_FADDR_MASK) #define USB3_USB_CMD_SDNFW_MASK (0x100U) #define USB3_USB_CMD_SDNFW_SHIFT (8U) /*! SDNFW - Send Function Wake Device Notification TP (SS mode only). Writing '1' will trigger an * attempt to send 'Device Notification' with 'Interface' field set to DNFW_INT. This bit will be * automatically cleared if the FW Notification TP is sent and only then the new FW Notification * TP or the other TP (by means of SPKT or SDNLTM bits) can be send again. Writing '0' has no * effect. This bit cannot be written by '1' simultaneously with SPKT and SDNLTM bits */ #define USB3_USB_CMD_SDNFW(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SDNFW_SHIFT)) & USB3_USB_CMD_SDNFW_MASK) #define USB3_USB_CMD_STMODE_MASK (0x200U) #define USB3_USB_CMD_STMODE_SHIFT (9U) /*! STMODE - Set Test Mode (HS/FS mode only). Writing the value '1 'to this bit causes the device * enters into test mode selected by the TMODE_SEL field. Writing '0' has no effect. This bit is * always '0' while reading */ #define USB3_USB_CMD_STMODE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_STMODE_SHIFT)) & USB3_USB_CMD_STMODE_MASK) #define USB3_USB_CMD_TMODE_SEL_MASK (0xC00U) #define USB3_USB_CMD_TMODE_SEL_SHIFT (10U) /*! TMODE_SEL - Test mode selector (HS/FS mode only). This field contains selected Test Mode - * Device will enter this Test mode when '1' is written to STMODE. USB 2.0 Test mode selector: 00 - * Test_J, 01 - Test_K, 10 - Test_SE0_NAK, 11 - Test_Packet This field is always '0' while reading */ #define USB3_USB_CMD_TMODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_TMODE_SEL_SHIFT)) & USB3_USB_CMD_TMODE_SEL_MASK) #define USB3_USB_CMD_SDNLTM_MASK (0x1000U) #define USB3_USB_CMD_SDNLTM_SHIFT (12U) /*! SDNLTM - Send Latency Tolerance Message Device Notification TP (SS mode only). Writing '1' will * trigger an attempt to send Device Notification 'Latency Tolerance Message' with 'BELT' field * set to DNLTM_BELT. This bit will be automatically cleared if the LTM Notification TP is sent * and only then the new LTM Notification TP or the other TP (by means of SPKT or SDNFW bits) can * be send again. Writing '0' has no effect. This bit cannot be written by '1' simultaneously with * SPKT and SDNFW bits */ #define USB3_USB_CMD_SDNLTM(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SDNLTM_SHIFT)) & USB3_USB_CMD_SDNLTM_MASK) #define USB3_USB_CMD_SPKT_MASK (0x2000U) #define USB3_USB_CMD_SPKT_SHIFT (13U) /*! SPKT - Send Custom Transaction Packet (SS mode only) Writing '1' will trigger an attempt to send * Custom TP as defined in the USB3.0 specification. The packet contents that will be send as TP * to the host must be previously prepared in the CPKT1 (will be sent as DWORD 0 in the TP), * CPKT2 (will be sent as DWORD 1 in the TP) and CPKT3 (will be sent as DWORD 2 in the TP) * registers. Note that TP DWORD 3 will be automatically inserted by the device controller. This bit will * be automatically cleared if this TP is sent and only then the new Custom TP (by means of SPKT * bit) or other Notification TP (by means of SDNLTM or SDNFW bits) can be send again. Writing 0 * has no effect. This bit cannot be written by 1 simultaneously with SDNLTM and SDNFW bits */ #define USB3_USB_CMD_SPKT(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SPKT_SHIFT)) & USB3_USB_CMD_SPKT_MASK) #define USB3_USB_CMD_RESERVED0_MASK (0xC000U) #define USB3_USB_CMD_RESERVED0_SHIFT (14U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_CMD_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_RESERVED0_SHIFT)) & USB3_USB_CMD_RESERVED0_MASK) #define USB3_USB_CMD_DNLTM_BELT_7_0_MASK (0xFF0000U) #define USB3_USB_CMD_DNLTM_BELT_7_0_SHIFT (16U) /*! DNLTM_BELT_7_0 - Device Notification 'Latency Tolerance Message' - BELT value [7:0] / Device * Notification 'Function Wake' - Interface value (SS mode only). This field must be filled up * before one of the USB_CMD.SDNLTM/SDNFW bits is set, and cannot be changed while * USB_CMD.SDNLTM/SDNFW bits are not zero (Device Notification is being sent by the device controller). If user * writes '1' to SDNFW bit the device will send Device Notification 'Function Wake' with * 'Interface[7:0]' field value equal to DNLTM_BELT_7_0. If user writes '1' to SDNLTM bit, the device will * send Device Notification 'Latency Tolerance Message' with 'BELT[7:0]' field value equal to * DNLTM_BELT_7_0. This field is always '0' while reading */ #define USB3_USB_CMD_DNLTM_BELT_7_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_DNLTM_BELT_7_0_SHIFT)) & USB3_USB_CMD_DNLTM_BELT_7_0_MASK) #define USB3_USB_CMD_DNLTM_BELT_11_8_MASK (0xF000000U) #define USB3_USB_CMD_DNLTM_BELT_11_8_SHIFT (24U) /*! DNLTM_BELT_11_8 - Device Notification 'Latency Tolerance Message' - BELT value [11:8] (SS mode * only). If user writes '1' to SDNLTM bit, the device will send Device Notification 'Latency * Tolerance Message' with 'BELT[11:8]' field value equal to DNLTM_BELT_11_8. This field must be * filled up before the USB_CMD.SDNLTM bit is set, and cannot be changed while USB_CMD.SDNLTM bit is * not zero (Device Notification is being sent by the device controller) This field is always '0' * while reading */ #define USB3_USB_CMD_DNLTM_BELT_11_8(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_DNLTM_BELT_11_8_SHIFT)) & USB3_USB_CMD_DNLTM_BELT_11_8_MASK) #define USB3_USB_CMD_RESERVED1_MASK (0xF0000000U) #define USB3_USB_CMD_RESERVED1_SHIFT (28U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_CMD_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_RESERVED1_SHIFT)) & USB3_USB_CMD_RESERVED1_MASK) /*! @} */ /*! @name USB_IPTN - ITP Number */ /*! @{ */ #define USB3_USB_IPTN_ITPN_MASK (0x3FFFU) #define USB3_USB_IPTN_ITPN_SHIFT (0U) /*! ITPN - ITP(SS) / SOF (HS/FS) number. In SS mode this field represent number of last ITP received * from host. In HS/FS mode this field represent number of last SOF received from host */ #define USB3_USB_IPTN_ITPN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IPTN_ITPN_SHIFT)) & USB3_USB_IPTN_ITPN_MASK) #define USB3_USB_IPTN_RESERVED_MASK (0xFFFFC000U) #define USB3_USB_IPTN_RESERVED_SHIFT (14U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_USB_IPTN_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IPTN_RESERVED_SHIFT)) & USB3_USB_IPTN_RESERVED_MASK) /*! @} */ /*! @name USB_LPM - Link Power Management */ /*! @{ */ #define USB3_USB_LPM_HIRD_MASK (0xFU) #define USB3_USB_LPM_HIRD_SHIFT (0U) /*! HIRD - Host Initiated Resume Duration. This is the Resume duration from L1 LPM state, received * from the host in the latest Extended Token packet. For more information see chapter: 'HS/FS * mode - Link Power Management' */ #define USB3_USB_LPM_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_LPM_HIRD_SHIFT)) & USB3_USB_LPM_HIRD_MASK) #define USB3_USB_LPM_BRW_MASK (0x10U) #define USB3_USB_LPM_BRW_SHIFT (4U) /*! BRW - Remote Wakeup Enable (bRemoteWake) */ #define USB3_USB_LPM_BRW(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_LPM_BRW_SHIFT)) & USB3_USB_LPM_BRW_MASK) #define USB3_USB_LPM_RESERVED_MASK (0xFFFFFFE0U) #define USB3_USB_LPM_RESERVED_SHIFT (5U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_USB_LPM_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_LPM_RESERVED_SHIFT)) & USB3_USB_LPM_RESERVED_MASK) /*! @} */ /*! @name USB_IEN - Interrupt Enable */ /*! @{ */ #define USB3_USB_IEN_CONIEN_MASK (0x1U) #define USB3_USB_IEN_CONIEN_SHIFT (0U) /*! CONIEN - SS connection interrupt enable. This bit enables requesting a CONI interrupt */ #define USB3_USB_IEN_CONIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_CONIEN_SHIFT)) & USB3_USB_IEN_CONIEN_MASK) #define USB3_USB_IEN_DISIEN_MASK (0x2U) #define USB3_USB_IEN_DISIEN_SHIFT (1U) /*! DISIEN - SS disconnection interrupt enable. This bit enables requesting a DISI interrupt */ #define USB3_USB_IEN_DISIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_DISIEN_SHIFT)) & USB3_USB_IEN_DISIEN_MASK) #define USB3_USB_IEN_UWRESIEN_MASK (0x4U) #define USB3_USB_IEN_UWRESIEN_SHIFT (2U) /*! UWRESIEN - USB SS warm reset interrupt enable. This bit enables requesting an UWRESI interrupt */ #define USB3_USB_IEN_UWRESIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UWRESIEN_SHIFT)) & USB3_USB_IEN_UWRESIEN_MASK) #define USB3_USB_IEN_UHRESIEN_MASK (0x8U) #define USB3_USB_IEN_UHRESIEN_SHIFT (3U) /*! UHRESIEN - USB SS hot reset interrupt enable. This bit enables requesting an UHRESI interrupt */ #define USB3_USB_IEN_UHRESIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UHRESIEN_SHIFT)) & USB3_USB_IEN_UHRESIEN_MASK) #define USB3_USB_IEN_U3ENTIEN_MASK (0x10U) #define USB3_USB_IEN_U3ENTIEN_SHIFT (4U) /*! U3ENTIEN - SS link U3 state enter interrupt enable (suspend). This bit enables requesting an U3ENTI interrupt */ #define USB3_USB_IEN_U3ENTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U3ENTIEN_SHIFT)) & USB3_USB_IEN_U3ENTIEN_MASK) #define USB3_USB_IEN_U3EXTIEN_MASK (0x20U) #define USB3_USB_IEN_U3EXTIEN_SHIFT (5U) /*! U3EXTIEN - SS link U3 state exit interrupt enable (wakeup). This bit enables requesting an U3EXTI interrupt */ #define USB3_USB_IEN_U3EXTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U3EXTIEN_SHIFT)) & USB3_USB_IEN_U3EXTIEN_MASK) #define USB3_USB_IEN_U2ENTIEN_MASK (0x40U) #define USB3_USB_IEN_U2ENTIEN_SHIFT (6U) /*! U2ENTIEN - SS link U2 state enter interrupt enable. This bit enables requesting an U2ENTI interrupt */ #define USB3_USB_IEN_U2ENTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U2ENTIEN_SHIFT)) & USB3_USB_IEN_U2ENTIEN_MASK) #define USB3_USB_IEN_U2EXTIEN_MASK (0x80U) #define USB3_USB_IEN_U2EXTIEN_SHIFT (7U) /*! U2EXTIEN - SS link U2 state exit interrupt enable. This bit enables requesting an U2EXTI interrupt */ #define USB3_USB_IEN_U2EXTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U2EXTIEN_SHIFT)) & USB3_USB_IEN_U2EXTIEN_MASK) #define USB3_USB_IEN_U1ENTIEN_MASK (0x100U) #define USB3_USB_IEN_U1ENTIEN_SHIFT (8U) /*! U1ENTIEN - SS link U1 state enter interrupt enable. This bit enables requesting an U1ENTI interrupt */ #define USB3_USB_IEN_U1ENTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U1ENTIEN_SHIFT)) & USB3_USB_IEN_U1ENTIEN_MASK) #define USB3_USB_IEN_U1EXTIEN_MASK (0x200U) #define USB3_USB_IEN_U1EXTIEN_SHIFT (9U) /*! U1EXTIEN - SS link U1 state exit interrupt enable. This bit enables requesting an U1EXTI interrupt */ #define USB3_USB_IEN_U1EXTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U1EXTIEN_SHIFT)) & USB3_USB_IEN_U1EXTIEN_MASK) #define USB3_USB_IEN_ITPIEN_MASK (0x400U) #define USB3_USB_IEN_ITPIEN_SHIFT (10U) /*! ITPIEN - ITP/SOF packet detected interrupt enable. This bit enables requesting an ITPI interrupt */ #define USB3_USB_IEN_ITPIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_ITPIEN_SHIFT)) & USB3_USB_IEN_ITPIEN_MASK) #define USB3_USB_IEN_WAKEIEN_MASK (0x800U) #define USB3_USB_IEN_WAKEIEN_SHIFT (11U) /*! WAKEIEN - Wakeup interrupt enable. This bit enables requesting a Wakeup interrupt */ #define USB3_USB_IEN_WAKEIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_WAKEIEN_SHIFT)) & USB3_USB_IEN_WAKEIEN_MASK) #define USB3_USB_IEN_SPKTIEN_MASK (0x1000U) #define USB3_USB_IEN_SPKTIEN_SHIFT (12U) /*! SPKTIEN - Send Custom Packet interrupt enable. This bit enables requesting a Send Custom Packet interrupt */ #define USB3_USB_IEN_SPKTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_SPKTIEN_SHIFT)) & USB3_USB_IEN_SPKTIEN_MASK) #define USB3_USB_IEN_RESERVED0_MASK (0xE000U) #define USB3_USB_IEN_RESERVED0_SHIFT (13U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_IEN_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED0_SHIFT)) & USB3_USB_IEN_RESERVED0_MASK) #define USB3_USB_IEN_CON2IEN_MASK (0x10000U) #define USB3_USB_IEN_CON2IEN_SHIFT (16U) /*! CON2IEN - HS/FS mode connection interrupt enable. This bit enables requesting a CON2I interrupt */ #define USB3_USB_IEN_CON2IEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_CON2IEN_SHIFT)) & USB3_USB_IEN_CON2IEN_MASK) #define USB3_USB_IEN_DIS2IEN_MASK (0x20000U) #define USB3_USB_IEN_DIS2IEN_SHIFT (17U) /*! DIS2IEN - HS/FS mode disconnection interrupt enable. This bit enables requesting a DIS2I interrupt */ #define USB3_USB_IEN_DIS2IEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_DIS2IEN_SHIFT)) & USB3_USB_IEN_DIS2IEN_MASK) #define USB3_USB_IEN_U2RESIEN_MASK (0x40000U) #define USB3_USB_IEN_U2RESIEN_SHIFT (18U) /*! U2RESIEN - USB reset (HS/FS mode) interrupt enable. This bit enables requesting an U2RESI interrupt */ #define USB3_USB_IEN_U2RESIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U2RESIEN_SHIFT)) & USB3_USB_IEN_U2RESIEN_MASK) #define USB3_USB_IEN_RESERVED1_MASK (0x80000U) #define USB3_USB_IEN_RESERVED1_SHIFT (19U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_IEN_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED1_SHIFT)) & USB3_USB_IEN_RESERVED1_MASK) #define USB3_USB_IEN_L2ENTIEN_MASK (0x100000U) #define USB3_USB_IEN_L2ENTIEN_SHIFT (20U) /*! L2ENTIEN - LPM L2 state enter interrupt enable. This bit enables requesting a L2ENTI interrupt */ #define USB3_USB_IEN_L2ENTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L2ENTIEN_SHIFT)) & USB3_USB_IEN_L2ENTIEN_MASK) #define USB3_USB_IEN_L2EXTIEN_MASK (0x200000U) #define USB3_USB_IEN_L2EXTIEN_SHIFT (21U) /*! L2EXTIEN - LPM L2 state exit interrupt enable. This bit enables requesting a L2EXTI interrupt */ #define USB3_USB_IEN_L2EXTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L2EXTIEN_SHIFT)) & USB3_USB_IEN_L2EXTIEN_MASK) #define USB3_USB_IEN_RESERVED2_MASK (0xC00000U) #define USB3_USB_IEN_RESERVED2_SHIFT (22U) /*! RESERVED2 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_IEN_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED2_SHIFT)) & USB3_USB_IEN_RESERVED2_MASK) #define USB3_USB_IEN_L1ENTIEN_MASK (0x1000000U) #define USB3_USB_IEN_L1ENTIEN_SHIFT (24U) /*! L1ENTIEN - LPM L1 state enter interrupt enable. This bit enables requesting an L1ENTI interrupt */ #define USB3_USB_IEN_L1ENTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L1ENTIEN_SHIFT)) & USB3_USB_IEN_L1ENTIEN_MASK) #define USB3_USB_IEN_L1EXTIEN_MASK (0x2000000U) #define USB3_USB_IEN_L1EXTIEN_SHIFT (25U) /*! L1EXTIEN - LPM L1 state exit interrupt enable. This bit enables requesting an L1EXTI interrupt */ #define USB3_USB_IEN_L1EXTIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L1EXTIEN_SHIFT)) & USB3_USB_IEN_L1EXTIEN_MASK) #define USB3_USB_IEN_CFGRESIEN_MASK (0x4000000U) #define USB3_USB_IEN_CFGRESIEN_SHIFT (26U) /*! CFGRESIEN - Configuration reset interrupt enable. This bit enables requesting a CFGRESI interrupt */ #define USB3_USB_IEN_CFGRESIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_CFGRESIEN_SHIFT)) & USB3_USB_IEN_CFGRESIEN_MASK) #define USB3_USB_IEN_RESERVED3_MASK (0x8000000U) #define USB3_USB_IEN_RESERVED3_SHIFT (27U) /*! RESERVED3 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_IEN_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED3_SHIFT)) & USB3_USB_IEN_RESERVED3_MASK) #define USB3_USB_IEN_UWRESSIEN_MASK (0x10000000U) #define USB3_USB_IEN_UWRESSIEN_SHIFT (28U) /*! UWRESSIEN - Start of the USB SS warm reset interrupt enable. This bit enables requesting a UWRESSI interrupt */ #define USB3_USB_IEN_UWRESSIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UWRESSIEN_SHIFT)) & USB3_USB_IEN_UWRESSIEN_MASK) #define USB3_USB_IEN_UWRESEIEN_MASK (0x20000000U) #define USB3_USB_IEN_UWRESEIEN_SHIFT (29U) /*! UWRESEIEN - End of the USB SS warm reset interrupt enable. This bit enables requesting a UWRESEI interrupt */ #define USB3_USB_IEN_UWRESEIEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UWRESEIEN_SHIFT)) & USB3_USB_IEN_UWRESEIEN_MASK) #define USB3_USB_IEN_RESERVED4_MASK (0xC0000000U) #define USB3_USB_IEN_RESERVED4_SHIFT (30U) /*! RESERVED4 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_IEN_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED4_SHIFT)) & USB3_USB_IEN_RESERVED4_MASK) /*! @} */ /*! @name USB_ISTS - Interrupt Status */ /*! @{ */ #define USB3_USB_ISTS_CONI_MASK (0x1U) #define USB3_USB_ISTS_CONI_SHIFT (0U) /*! CONI - SS connection detected This interrupt informs that SuperSpeed link was conncted to the * USB line This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_CONI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_CONI_SHIFT)) & USB3_USB_ISTS_CONI_MASK) #define USB3_USB_ISTS_DISI_MASK (0x2U) #define USB3_USB_ISTS_DISI_SHIFT (1U) /*! DISI - SS disconnection detected This interrupt informs that SuperSpeed link was disconncted * from the USB line. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_DISI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_DISI_SHIFT)) & USB3_USB_ISTS_DISI_MASK) #define USB3_USB_ISTS_UWRESI_MASK (0x4U) #define USB3_USB_ISTS_UWRESI_SHIFT (2U) /*! UWRESI - USB SS warm reset detected This interrupt is requested after the SuperSpeed warm reset * ends or when USBSS-DEVs LTSSM exits Polling.LFPS state. After this reset, SW should * reininitialize the controller. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_UWRESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UWRESI_SHIFT)) & USB3_USB_ISTS_UWRESI_MASK) #define USB3_USB_ISTS_UHRESI_MASK (0x8U) #define USB3_USB_ISTS_UHRESI_SHIFT (3U) /*! UHRESI - USB SS hot reset detected This interrupt is requested after the SuperSpeed hot reset * ends. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_UHRESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UHRESI_SHIFT)) & USB3_USB_ISTS_UHRESI_MASK) #define USB3_USB_ISTS_U3ENTI_MASK (0x10U) #define USB3_USB_ISTS_U3ENTI_SHIFT (4U) /*! U3ENTI - SS link U3 state enter detected (suspend) This interrupt informs that SuperSpeed link * enter U3 state. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_U3ENTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U3ENTI_SHIFT)) & USB3_USB_ISTS_U3ENTI_MASK) #define USB3_USB_ISTS_U3EXTI_MASK (0x20U) #define USB3_USB_ISTS_U3EXTI_SHIFT (5U) /*! U3EXTI - SS link U3 state exit detected (wakeup) This interrupt informs that SuperSpeed link * exit U3 state. This interrupt is reported on the irqs[1] pin */ #define USB3_USB_ISTS_U3EXTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U3EXTI_SHIFT)) & USB3_USB_ISTS_U3EXTI_MASK) #define USB3_USB_ISTS_U2ENTI_MASK (0x40U) #define USB3_USB_ISTS_U2ENTI_SHIFT (6U) /*! U2ENTI - SS link U2 state enter detected This interrupt informs that SuperSpeed link enter U2 * state. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_U2ENTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U2ENTI_SHIFT)) & USB3_USB_ISTS_U2ENTI_MASK) #define USB3_USB_ISTS_U2EXTI_MASK (0x80U) #define USB3_USB_ISTS_U2EXTI_SHIFT (7U) /*! U2EXTI - SS link U2 state exit detected This interrupt informs that SuperSpeed link exit U2 * state. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_U2EXTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U2EXTI_SHIFT)) & USB3_USB_ISTS_U2EXTI_MASK) #define USB3_USB_ISTS_U1ENTI_MASK (0x100U) #define USB3_USB_ISTS_U1ENTI_SHIFT (8U) /*! U1ENTI - SS link U1 state enter detected This interrupt informs that SuperSpeed link enter U1 * state. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_U1ENTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U1ENTI_SHIFT)) & USB3_USB_ISTS_U1ENTI_MASK) #define USB3_USB_ISTS_U1EXTI_MASK (0x200U) #define USB3_USB_ISTS_U1EXTI_SHIFT (9U) /*! U1EXTI - SS link U1 state exit detected This interrupt informs that SuperSpeed link exit U1 * state. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_U1EXTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U1EXTI_SHIFT)) & USB3_USB_ISTS_U1EXTI_MASK) #define USB3_USB_ISTS_ITPI_MASK (0x400U) #define USB3_USB_ISTS_ITPI_SHIFT (10U) /*! ITPI - ITP/SOF packet detected In SuperSpeed mode this interrupt informs that ITP packet was * received. In FS/HS mode this interrupt informs that SOF was detected. This interrupt is reported * on the irqs[0] pin */ #define USB3_USB_ISTS_ITPI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_ITPI_SHIFT)) & USB3_USB_ISTS_ITPI_MASK) #define USB3_USB_ISTS_WAKEI_MASK (0x800U) #define USB3_USB_ISTS_WAKEI_SHIFT (11U) /*! WAKEI - This interrupt informs that at wakeup pin appeared active state. This interrupt is reported on the irqs[1] pin */ #define USB3_USB_ISTS_WAKEI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_WAKEI_SHIFT)) & USB3_USB_ISTS_WAKEI_MASK) #define USB3_USB_ISTS_SPKTI_MASK (0x1000U) #define USB3_USB_ISTS_SPKTI_SHIFT (12U) /*! SPKTI - Send Custom Packet This interrupt informs that Custom Packet prepared in the USB_CPKT1-3 * registers and triggered with USB_CMD.SPKT bit was already sent. This interrupt is reported on * the irqs[0] pin */ #define USB3_USB_ISTS_SPKTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_SPKTI_SHIFT)) & USB3_USB_ISTS_SPKTI_MASK) #define USB3_USB_ISTS_RESERVED0_MASK (0xE000U) #define USB3_USB_ISTS_RESERVED0_SHIFT (13U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_ISTS_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED0_SHIFT)) & USB3_USB_ISTS_RESERVED0_MASK) #define USB3_USB_ISTS_CON2I_MASK (0x10000U) #define USB3_USB_ISTS_CON2I_SHIFT (16U) /*! CON2I - HS/FS mode connection detected This interrupt informs that HS/FS upstream port was * conncted to the USB line This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_CON2I(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_CON2I_SHIFT)) & USB3_USB_ISTS_CON2I_MASK) #define USB3_USB_ISTS_DIS2I_MASK (0x20000U) #define USB3_USB_ISTS_DIS2I_SHIFT (17U) /*! DIS2I - HS/FS mode disconnection detected This interrupt informs that HS/FS upstream port was * disconncted from the USB line. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_DIS2I(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_DIS2I_SHIFT)) & USB3_USB_ISTS_DIS2I_MASK) #define USB3_USB_ISTS_U2RESI_MASK (0x40000U) #define USB3_USB_ISTS_U2RESI_SHIFT (18U) /*! U2RESI - USB reset (HS/FS mode) detected This interrupt is requested after the USB reset in * HS/FS mode ends. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_U2RESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U2RESI_SHIFT)) & USB3_USB_ISTS_U2RESI_MASK) #define USB3_USB_ISTS_RESERVED1_MASK (0x80000U) #define USB3_USB_ISTS_RESERVED1_SHIFT (19U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_ISTS_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED1_SHIFT)) & USB3_USB_ISTS_RESERVED1_MASK) #define USB3_USB_ISTS_L2ENTI_MASK (0x100000U) #define USB3_USB_ISTS_L2ENTI_SHIFT (20U) /*! L2ENTI - LPM L2 state enter detected This interrupt informs that HS/FS LPM enter L2 state. This * interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_L2ENTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L2ENTI_SHIFT)) & USB3_USB_ISTS_L2ENTI_MASK) #define USB3_USB_ISTS_L2EXTI_MASK (0x200000U) #define USB3_USB_ISTS_L2EXTI_SHIFT (21U) /*! L2EXTI - LPM L2 state exit detected This interrupt informs that HS/FS LPM exit L2 state. This * interrupt is reported on the irqs[1] pin */ #define USB3_USB_ISTS_L2EXTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L2EXTI_SHIFT)) & USB3_USB_ISTS_L2EXTI_MASK) #define USB3_USB_ISTS_RESERVED2_MASK (0xC00000U) #define USB3_USB_ISTS_RESERVED2_SHIFT (22U) /*! RESERVED2 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_ISTS_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED2_SHIFT)) & USB3_USB_ISTS_RESERVED2_MASK) #define USB3_USB_ISTS_L1ENTI_MASK (0x1000000U) #define USB3_USB_ISTS_L1ENTI_SHIFT (24U) /*! L1ENTI - LPM L1 state enter detected This interrupt informs that HS/FS LPM enter L1 state. This * interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_L1ENTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L1ENTI_SHIFT)) & USB3_USB_ISTS_L1ENTI_MASK) #define USB3_USB_ISTS_L1EXTI_MASK (0x2000000U) #define USB3_USB_ISTS_L1EXTI_SHIFT (25U) /*! L1EXTI - LPM L1 state exit detected This interrupt informs that HS/FS LPM exit L1 state. This * interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_L1EXTI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L1EXTI_SHIFT)) & USB3_USB_ISTS_L1EXTI_MASK) #define USB3_USB_ISTS_CFGRESI_MASK (0x4000000U) #define USB3_USB_ISTS_CFGRESI_SHIFT (26U) /*! CFGRESI - USB configuration reset detected. This interrupt is requested after the device * internally resets its endpoints onfiguration. This is done after each USB reset (UWRESI, UWRESI or * U2RESI), after each connection event (CONI, CON2I) and after configuration reset initiated by * software (USB_CONF.CFGRST). Generally this interrupt is generated in the same time as mentioned * interrupts, however due to internal clock domain synchronisation this configuration reset can * be performed a little later, so one can use this interrupt to perform some software * operations. This interrupt informs that controller did the following operations: disabled all non * control endpoints, cleared all pending endpoints transfers and interrupts. The configuration reset * does not clear general device configuration (set in USB_CONF) and EP0 configuration settings. * This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_CFGRESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_CFGRESI_SHIFT)) & USB3_USB_ISTS_CFGRESI_MASK) #define USB3_USB_ISTS_RESERVED3_MASK (0x8000000U) #define USB3_USB_ISTS_RESERVED3_SHIFT (27U) /*! RESERVED3 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_ISTS_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED3_SHIFT)) & USB3_USB_ISTS_RESERVED3_MASK) #define USB3_USB_ISTS_UWRESSI_MASK (0x10000000U) #define USB3_USB_ISTS_UWRESSI_SHIFT (28U) /*! UWRESSI - Start of the USB warm reset detected. This interrupt is requested as soon as the * SuperSpeed warm reset signalling is detected. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_UWRESSI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UWRESSI_SHIFT)) & USB3_USB_ISTS_UWRESSI_MASK) #define USB3_USB_ISTS_UWRESEI_MASK (0x20000000U) #define USB3_USB_ISTS_UWRESEI_SHIFT (29U) /*! UWRESEI - End of the USB warm reset detected. This interrupt is requested after the SuperSpeed * warm reset ends. This interrupt is reported on the irqs[0] pin */ #define USB3_USB_ISTS_UWRESEI(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UWRESEI_SHIFT)) & USB3_USB_ISTS_UWRESEI_MASK) #define USB3_USB_ISTS_RESERVED4_MASK (0xC0000000U) #define USB3_USB_ISTS_RESERVED4_SHIFT (30U) /*! RESERVED4 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_ISTS_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED4_SHIFT)) & USB3_USB_ISTS_RESERVED4_MASK) /*! @} */ /*! @name EP_SEL - Endpoint Select */ /*! @{ */ #define USB3_EP_SEL_EPNO_MASK (0xFU) #define USB3_EP_SEL_EPNO_SHIFT (0U) /*! EPNO - Selected Endpoint number */ #define USB3_EP_SEL_EPNO(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_EPNO_SHIFT)) & USB3_EP_SEL_EPNO_MASK) #define USB3_EP_SEL_RESERVED0_MASK (0x70U) #define USB3_EP_SEL_RESERVED0_SHIFT (4U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_EP_SEL_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_RESERVED0_SHIFT)) & USB3_EP_SEL_RESERVED0_MASK) #define USB3_EP_SEL_DIR_MASK (0x80U) #define USB3_EP_SEL_DIR_SHIFT (7U) /*! DIR - Selected Endpoint direction. 0-OUT Endpoint selected, 1-IN Endpoint selected */ #define USB3_EP_SEL_DIR(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_DIR_SHIFT)) & USB3_EP_SEL_DIR_MASK) #define USB3_EP_SEL_RESERVED1_MASK (0xFFFFFF00U) #define USB3_EP_SEL_RESERVED1_SHIFT (8U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_EP_SEL_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_RESERVED1_SHIFT)) & USB3_EP_SEL_RESERVED1_MASK) /*! @} */ /*! @name EP_TRADDR - Endpoint Transfer Ring Address */ /*! @{ */ #define USB3_EP_TRADDR_TRADDR_MASK (0xFFFFFFFFU) #define USB3_EP_TRADDR_TRADDR_SHIFT (0U) /*! TRADDR - Transfer Ring address. Address of transfer ring for endpoint selected by endpoint * select register. Based on this address, DMA will fetch transfer descriptors from system memory. * This register can be used as dequeue pointer. CPU can use this register (read it or write to it) * only when endpoint is configured and enabled (using EP_CFG register) */ #define USB3_EP_TRADDR_TRADDR(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_TRADDR_TRADDR_SHIFT)) & USB3_EP_TRADDR_TRADDR_MASK) /*! @} */ /*! @name EP_CFG - Endpoint Configuration */ /*! @{ */ #define USB3_EP_CFG_ENABLE_MASK (0x1U) #define USB3_EP_CFG_ENABLE_SHIFT (0U) /*! ENABLE - Endpoint enable. If endpoint is disabled (the ENABLE bit is cleared), the endpoint will * not: - request any interrupts - start any transmission over the DMA Even if Endpoint is * disabled, software can set DRDY bit for it, but the DMA transmission will not begin until the * endpoint is enabled. 0: disabled 1: enabled Reset value of this bit for EP0 is 1, for other EP's is * 0 */ #define USB3_EP_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_ENABLE_SHIFT)) & USB3_EP_CFG_ENABLE_MASK) #define USB3_EP_CFG_EPTYPE_MASK (0x6U) #define USB3_EP_CFG_EPTYPE_SHIFT (1U) /*! EPTYPE - Endpoint type. 0: control, 1: isochronous, 2: bulk, 3: interrupt. Endpoint type is * programmable, however, certain types of transmissions require hardware support that must be * incorporated prior to implementation. That can be done only for selected endpoints. Selective * inclusion of hardware support is to reduce the size of the controller. Accordingly: - Endpoint-type * iso should be set by the software only for those endpoints for which isochronous transmission * hardware support is enabled. - A bulk endpoint can handle transmission with Bulk Streams * support only for those endpoints for which Bulk Stream transmission hardware support is enabled. * For detailed description how to implement hardware support for ISO transfers or Bulk Stream * transfers see chapter 'Endpoints Implementation' */ #define USB3_EP_CFG_EPTYPE(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_EPTYPE_SHIFT)) & USB3_EP_CFG_EPTYPE_MASK) #define USB3_EP_CFG_STREAM_EN_MASK (0x8U) #define USB3_EP_CFG_STREAM_EN_SHIFT (3U) /*! STREAM_EN - Stream support enable (only in SS mode). This bit must be set to enable a stream * transfes on a bulk endpoint 0: Stream support OFF 1: Stream support ON */ #define USB3_EP_CFG_STREAM_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_STREAM_EN_SHIFT)) & USB3_EP_CFG_STREAM_EN_MASK) #define USB3_EP_CFG_TDL_CHK_MASK (0x10U) #define USB3_EP_CFG_TDL_CHK_SHIFT (4U) /*! TDL_CHK - TDL check(only in SS mode for BULK OUT EP). This field has to be set for stream * capable SS bulk endpoints and it can be set for other bulk endpoint. The OUT bulk endpoints If the * TDL_CHK bit is set if the device takes the packets to the OUT endpoint only when the value of * the TDL (EP_CMD.TDL) for this endpoint is different from zero. Each received packet for the * particular endpoint decrements the value of a TDL. If the TDL_CHK bit is not set, then each * packet from the host to the OUT endpoint is taken as long as it free space in the on-chip device * buffers. The IN bulk endpoints This bit is is used by USBSS_DEV to set EOB bit when TDL * (programmed value) reach zero. 0: Do not check the TDL value when sending/receiving packets to the * endpoints 1: Check the TDL value when sending/receiving packets to the endpoint */ #define USB3_EP_CFG_TDL_CHK(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_TDL_CHK_SHIFT)) & USB3_EP_CFG_TDL_CHK_MASK) #define USB3_EP_CFG_SID_CHK_MASK (0x20U) #define USB3_EP_CFG_SID_CHK_SHIFT (5U) /*! SID_CHK - SID check(only in SS mode for BULK OUT EP) This field can be set only for SS bulk OUT * endpoints with stream support enabled 1) If SID_CHK bit is set, the device checks whether the * incoming packets from the host to the particular OUT endpoint have the SID field set to the * expected value. If the packet has an expected SID value is then taken and stored in the on-chip * device buffers. If the packet has a different SID than expected, then the packet is rejected * (NRDY) and the SIDERROR interrupt is reported to the software. The value of the SID to which * incoming packets will be compared, are written to the device during sending ERDY TP (EP_CMD.ERDY * and EP_CMD.ERDY_SID). The SID value from the incoming packet that has been rejected and * caused the SIDERR interrupt can be read from the EP_STS_SID register. 2) If SID_CHK bit is not set, * then each packet from the host is taken to the on-chip buffers is transmitted by the DMA * regardless of the SID field in the TD. 0: SID chceck at device input OFF 1: SID chceck at device * input ON */ #define USB3_EP_CFG_SID_CHK(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_SID_CHK_SHIFT)) & USB3_EP_CFG_SID_CHK_MASK) #define USB3_EP_CFG_RESERVED0_MASK (0x40U) #define USB3_EP_CFG_RESERVED0_SHIFT (6U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_EP_CFG_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_RESERVED0_SHIFT)) & USB3_EP_CFG_RESERVED0_MASK) #define USB3_EP_CFG_EPENDIAN_MASK (0x80U) #define USB3_EP_CFG_EPENDIAN_SHIFT (7U) /*! EPENDIAN - DMA transfer endianness. When the conversion is ON, the byte order within DWORD is * inverted. While the bit is set, the software confirms that the transfer length is a * multiplication of 4 bytes. Enabling the conversion is possible only when SUPPORT_ENDIANESS_CONV is * defined. By default this parameter is not defined, so endianess conversion is disabled. 0: Endianess * conversion OFF 1: Endianess conversion ON */ #define USB3_EP_CFG_EPENDIAN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_EPENDIAN_SHIFT)) & USB3_EP_CFG_EPENDIAN_MASK) #define USB3_EP_CFG_MAXBURST_MASK (0xF00U) #define USB3_EP_CFG_MAXBURST_SHIFT (8U) /*! MAXBURST - Maximum Burst size. The maximum number of packets the endpoint can send or receive as * part of a burst. Valid values are from 0 to 15. A value of 0 indicates that the endpoint can * only burst one packet at a time, and a value of 15 indicates that the endpoint can burst up to * 16 packets at a time. For endpoints of type control this is set to 0. This field is * meaningfull only in SuperSpeed mode */ #define USB3_EP_CFG_MAXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_MAXBURST_SHIFT)) & USB3_EP_CFG_MAXBURST_MASK) #define USB3_EP_CFG_RESERVED1_MASK (0x3000U) #define USB3_EP_CFG_RESERVED1_SHIFT (12U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_EP_CFG_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_RESERVED1_SHIFT)) & USB3_EP_CFG_RESERVED1_MASK) #define USB3_EP_CFG_MULT_MASK (0xC000U) #define USB3_EP_CFG_MULT_SHIFT (14U) /*! MULT - ISO max burst SuperSpeed mode: A zero-based value that indicates the maximum number of * bursts within a service interval that this endpoint supports. This field is only valid for * isochronous endpoints. A value of zero indicates that the device supports one Burst of bMaxBurst * packets per service interval. The max value that can be set in this field in SuperSpeed is '2'. * HS/FS mode: This field indicates how many packets will be transferred during micro frame. In * Full-Speed mode only one ISO IN packet can be transferred per endpoint, per frame, thus this * field has to be always '0'. In High-Speed mode, up to three ISO IN packets can be transferred * per endpoint, per microframe, so the max value that can be set in this field in HighSpeed is '2' */ #define USB3_EP_CFG_MULT(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_MULT_SHIFT)) & USB3_EP_CFG_MULT_MASK) #define USB3_EP_CFG_MAXPKTSIZE_MASK (0x7FF0000U) #define USB3_EP_CFG_MAXPKTSIZE_SHIFT (16U) /*! MAXPKTSIZE - Max packet size. The maximum packet size this endpoint is capable of sending or * receiving. SuperSpeed mode: For control endpoints, this field is set to 512. For bulk endpoint * types, this field is set to 1024. For interrupt and isochronous endpoints, this field is set to * 1024 if this endpoint defines a value in the bMaxBurst field greater than zero. If the value * in the bMaxBurst field is set to zero, then this field can have any value from 0 to 1024 for an * isochronous endpoint, and 1 to 1024 for an interrupt endpoint. High Speed/Full Speed mode: * For control endpoints, this field is set to 64. For other endpoint types this field can have any * value from 0 to 1024 */ #define USB3_EP_CFG_MAXPKTSIZE(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_MAXPKTSIZE_SHIFT)) & USB3_EP_CFG_MAXPKTSIZE_MASK) #define USB3_EP_CFG_BUFFERING_MASK (0xF8000000U) #define USB3_EP_CFG_BUFFERING_SHIFT (27U) /*! BUFFERING - Max number of buffered packets. The maximum number of packets the device can buffer * in the on-chip memory for a specified endpoint. Valid values are from 0 to 15. Value 0 means * that 1 on-chip buffer is available for the appropriate endpoint. Value 15 means that 16 on-chip * buffers are available for the appropriate endpoint. Each IN endpoint has individual buffers * associated with it. OUT endpoints have common buffers, so buffering for OUT endpoints is * determined by the maximum buffering value along all enabled OUT endpoints. The number of possible * endpoint buffers depends on the on-chip memory size and the size of endpoint buffers */ #define USB3_EP_CFG_BUFFERING(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_BUFFERING_SHIFT)) & USB3_EP_CFG_BUFFERING_MASK) /*! @} */ /*! @name EP_CMD - Endpoint Command */ /*! @{ */ #define USB3_EP_CMD_EPRST_MASK (0x1U) #define USB3_EP_CMD_EPRST_SHIFT (0U) /*! EPRST - Endpoint reset. 0: no effect 1: resets endpoint This command performs the following * actions for particular endpoint: - clears DRDY bit and stops DMA transfer - clears on-chip buffers * - clears sequence number in SS mode or Data Toggle in HS/FS mode This command does not clear * Endpoint interrupt if already requested (irq[0] pin was asserted) thus it is recommended first * to clear all interrupts from endpoint scheduled to reset. When EPRST operation is started * ('1' is written), CPU must wait until this bit becomes again '0' (it indicates that HW finishes * all internal opertations related to DFLUSH), and only then can proceed with next software * operations. Additionally, when DMA already started processing TD for this EP, the EPRST command * cause that DMA engine will once more access the descriptor in external memory. After endpoint * reset the software is responsible for it to re-set the Endpoint TRADDR. Writing '0 'has no effect */ #define USB3_EP_CMD_EPRST(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_EPRST_SHIFT)) & USB3_EP_CMD_EPRST_MASK) #define USB3_EP_CMD_SSTALL_MASK (0x2U) #define USB3_EP_CMD_SSTALL_SHIFT (1U) /*! SSTALL - Endpoint STALL set. Writing '1' to this bit cause the endpoint is halted. 0: no effect 1: STALLs endpoint */ #define USB3_EP_CMD_SSTALL(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_SSTALL_SHIFT)) & USB3_EP_CMD_SSTALL_MASK) #define USB3_EP_CMD_CSTALL_MASK (0x4U) #define USB3_EP_CMD_CSTALL_SHIFT (2U) /*! CSTALL - Endpoint STALL clear. Writing '1' to this bit cause the endpoint becames not halted. 0: * no effect 1: clears endpoint STALL */ #define USB3_EP_CMD_CSTALL(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_CSTALL_SHIFT)) & USB3_EP_CMD_CSTALL_MASK) #define USB3_EP_CMD_ERDY_MASK (0x8U) #define USB3_EP_CMD_ERDY_SHIFT (3U) /*! ERDY - Send ERDY TP. Writing '1' to this bit forces the device to send ERDY TP with stream ID * equal to ERDY_SID. This bit is necessary to support SS bulk stream transfers. This bit is also * used during control transfers (in both modes: HS/FS and SS): writing '1' instruct device * controller HW that it can exit from Setup Stage to the Data Stage (or directly to the Status Stage * if USB Request is without Data Stage). However the ERDY packet is only actually sent in SS * mode. Writing '0' has no effect */ #define USB3_EP_CMD_ERDY(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_ERDY_SHIFT)) & USB3_EP_CMD_ERDY_MASK) #define USB3_EP_CMD_RESERVED_MASK (0x10U) #define USB3_EP_CMD_RESERVED_SHIFT (4U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_EP_CMD_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_RESERVED_SHIFT)) & USB3_EP_CMD_RESERVED_MASK) #define USB3_EP_CMD_REQ_CMPL_MASK (0x20U) #define USB3_EP_CMD_REQ_CMPL_SHIFT (5U) /*! REQ_CMPL - Request complete. 0 : no effect 1 : informs device that Request service is complete * Bit valid only for endpoint 0. Writing '1' to this bit informs USBSS-DEV that software finished * USB request service and device can send ACK answer for the Status Stage within USB request. * This bit is automatically cleared by USBSS-DEV after device answers to the status stage with * ACK or STALL. Until software do not set this bit, during proceeding current host request, the * device will answer to the status stage with NRDY answer */ #define USB3_EP_CMD_REQ_CMPL(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_REQ_CMPL_SHIFT)) & USB3_EP_CMD_REQ_CMPL_MASK) #define USB3_EP_CMD_DRDY_MASK (0x40U) #define USB3_EP_CMD_DRDY_SHIFT (6U) /*! DRDY - Transfer descriptor ready. Transfer Descriptor Ready for selected endpoint (0 - no * effect, 1 - starts transfer). Writing '1' to this bit informs USBSS-DEV that in-system memory has * prepared a new Transfer Descriptor for selected endpoints. If an IN endpoint is 'Not Ready' * (NRDY=1 in Endpoint Status Register), then setting the DRDY bit (which is proceeded by DMA * transfer to the on-chip buffers) will cause the device to send the ERDY packet. If the TRB error * occurs, the DRDY bit is cleared and held in the low state until the TRBERR is not cleared (even if * the DTRANS bit is set, the Multiple TRB chain mode is enabled). This bit is duplicated in the * Doorbell register. Writing '1' to this bit while DESCMIS interrupt flag is set for the same * endpoint will also clear the DESCMIS flag */ #define USB3_EP_CMD_DRDY(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_DRDY_SHIFT)) & USB3_EP_CMD_DRDY_MASK) #define USB3_EP_CMD_DFLUSH_MASK (0x80U) #define USB3_EP_CMD_DFLUSH_SHIFT (7U) /*! DFLUSH - Data flush. Writing '1' to this bit performs the following actions for particular * endpoint: - clears DRDY bit and stops DMA transfer - flush endpoint data from on chip buffers As in * case of Endpoint reset (EPRST bit), after endpoint data flush the software is responsible for * it to re-set the Endpoint TRADDR. When DFLUSH operation is started ('1' is written), CPU must * wait until this bit becomes again '0' (it indicates that HW finishes all internal opertations * related to DFLUSH), and only then can proceed with next software operations. Writing '0' has * no effect */ #define USB3_EP_CMD_DFLUSH(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_DFLUSH_SHIFT)) & USB3_EP_CMD_DFLUSH_MASK) #define USB3_EP_CMD_STDL_MASK (0x100U) #define USB3_EP_CMD_STDL_SHIFT (8U) /*! STDL - Transfer Descriptor Length write (used only for Bulk Stream capable endpoints in SS * mode). Writing '1' to this bit writes to the device the TDL field. The bit is automatically cleared. */ #define USB3_EP_CMD_STDL(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_STDL_SHIFT)) & USB3_EP_CMD_STDL_MASK) #define USB3_EP_CMD_TDL_MASK (0xFE00U) #define USB3_EP_CMD_TDL_SHIFT (9U) /*! TDL - Transfer Descriptor Length (used only in SS mode for bulk endpoints). Using the field TDL * for bulk EP assumes TDL_CHK bit enabled. This field will be writen to the device when the * EP_CMD.STDL bit is set to '1'. This field is used by the device when particular endpoint: - is * configured as Stream capable (EP_CFG.STREAM_EN bit is set) or - the IOT interrupt is to be used * This field should be written each time, when bit EP_CMD.DRDY is written (i.e. device is * notified that new TD is ready). The written value should correspond to the prepared data size * (multiple of endpoint MAXPKTSIZE eg. in KB for BULK EP) in the transfer descriptor (which has been * prepared for this endpoint before DRDY bit is set) rounded up (if short packet expected). This * field has to be written no later than DRDY (or Dorbel) bit. 1) For OUT endpoints device will * decrement this field by one after each successful packet received from the host. 2) For IN * endpoints device will decrement this field by one after each successful handshake packet received * from the host. As long as this field is not decremented to zero, then for each response NRDY * that device send to the host (e.g. due to temporary lack of space (OUT EP) / packets (IN EP) in * the on-chip buffers), device will automatically send the ERDY package to the host as soon as * free spece (OUT EP) / new packet (IN EP) will be available in the on-chip buffers. When the * field TDL is decremented to zero then, it will mean that the device does not expect to have more * packets from the host (OUT EP) / does not want to send more packets (IN EP). Then device * generates IOT interrupt and from this moment ERDY TP will not be sent automatically if endpoint * enters flow control. Additionally, if TDL_CHK is set (only for BULK EP), and TDL value is equal * to zero, device will: - for OUT EP - not accept any data packet from host for particular EP, * even if there are empty OUT buffers. In this case device answer with NRDY TP and NRDY interrupt * will be requested. - for IN EP - send last programmed (according to the TDL field) with EOB * bit set. Writing into this field any value at the time when the previous value of this field was * not zero, will result in adding these two values */ #define USB3_EP_CMD_TDL(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_TDL_SHIFT)) & USB3_EP_CMD_TDL_MASK) #define USB3_EP_CMD_ERDY_SID_MASK (0xFFFF0000U) #define USB3_EP_CMD_ERDY_SID_SHIFT (16U) /*! ERDY_SID - ERDY Stream ID value (used in SS mode). This field contains SID - it will be sent to * host in ERDY packet (by writing '1' to ERDY). This field is meaningfull only in SuperSpeed mode */ #define USB3_EP_CMD_ERDY_SID(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_ERDY_SID_SHIFT)) & USB3_EP_CMD_ERDY_SID_MASK) /*! @} */ /*! @name EP_STS - Endpoint Status */ /*! @{ */ #define USB3_EP_STS_SETUP_MASK (0x1U) #define USB3_EP_STS_SETUP_SHIFT (0U) /*! SETUP - Setup transfer complete. Bit used only for EP0. If setup type transmission has been * completed and data from host has been received and copied to system memory, this bit is set to '1' * and interrupt is generated. Setup packet is applicable only to control transmissions (EP0). * This interrupt can be masked by the corresponding bit in EP_STS_EN register. Writing '1' to * this bit clears the interrupt */ #define USB3_EP_STS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SETUP_SHIFT)) & USB3_EP_STS_SETUP_MASK) #define USB3_EP_STS_STALL_MASK (0x2U) #define USB3_EP_STS_STALL_SHIFT (1U) /*! STALL - Endpoint STALL status 0 - endpoint is not stalled 1 - endpoint is stalled This bit is * not treated as an interrupt (not reported in the EP__ISTS register). This bit is read-only */ #define USB3_EP_STS_STALL(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_STALL_SHIFT)) & USB3_EP_STS_STALL_MASK) #define USB3_EP_STS_IOC_MASK (0x4U) #define USB3_EP_STS_IOC_SHIFT (2U) /*! IOC - Interrupt On Complete When DMA transfer is completed and transfer descriptor is updated, * then this bit is set to 1 and interrupt is generated. Enabling or disabling of this interrupt * is realized by IOC bit in transfer descriptor. Additionally, this interrupt can be masked for a * particular endpoint in EP__ISTS register. When in given transfer descriptor both interrupts * (IOC and ISP interrupts) are enabled, then in the case of short packet, only one interrupt is * generated - SP. Writing '1' to this bit clears the interrupt */ #define USB3_EP_STS_IOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_IOC_SHIFT)) & USB3_EP_STS_IOC_MASK) #define USB3_EP_STS_ISP_MASK (0x8U) #define USB3_EP_STS_ISP_SHIFT (3U) /*! ISP - Interrupt on Short Packet. This bit is set to 1 and interrupt is generated when a transfer * containing less data than MaxPacket for a given endpoint has been completed and transfer * descriptor has been updated.Enabling or disabling of interrupt is realized by ISP bit in transfer * descriptor. Additionally, this interrupt can be masked for a particular endpoint in EP__ISTS * register. When in given transfer descriptor both interrupts are enabled (IOC and ISP), then in * the case of short packet only one interrupt is generated - SP. Writing '1' to this bit clears * the interrupt */ #define USB3_EP_STS_ISP(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_ISP_SHIFT)) & USB3_EP_STS_ISP_MASK) #define USB3_EP_STS_DESCMIS_MASK (0x10U) #define USB3_EP_STS_DESCMIS_SHIFT (4U) /*! DESCMIS - Transfer descriptor missing. This bit is set to 1 and interrupt is generated when any * of the following conditions are met: - device is requested to send data to host and none of * Transfer Descriptor is prepared (IN transfer) - device receives OUT packet and cannot transmit * it using DMA as Transfer Descriptor has not been prepared (DRDY was not set) for it (OUT * transfer) Note1: This interrupt is not generated for ISO IN endpoints. For such endpoints the ISOERR * interrupt should be used. Note2: DMA will not start operating on transfer descriptor array * until the OUT packet is received (or host requests IN packet) and processor has not previously * notified DMA (by writing to EP_CMD register of DRDY register). Note2: For BULK OUT endpoints * with TDL_CHK bit set this interrupt will not by requested as device will not accept any packet * from host when TRB is not prepared (and TDL is not written with non-zero value). In this case * the NRDY interrupt should be used instead of DESMIS. Writing '1' to this bit or writing '1' to * EP_CMD.DRDY bit of endpoints which generated interrupt will delete the interrupt. This * interrupt can be masked by the corresponding bit in EP_STS_EN register. Writing '1' to this bit * clears the interrupt */ #define USB3_EP_STS_DESCMIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_DESCMIS_SHIFT)) & USB3_EP_STS_DESCMIS_MASK) #define USB3_EP_STS_STREAMR_MASK (0x20U) #define USB3_EP_STS_STREAMR_SHIFT (5U) /*! STREAMR - Stream Rejected (used only in SS mode). This bit is set to '1' if device tries to * initiate stream number and host does not accept it. Stream support is class-dependent. This * interrupt can be masked by the corresponding bit in STREAMREN register. Writing '1' to this bit * clears the interrupt */ #define USB3_EP_STS_STREAMR(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_STREAMR_SHIFT)) & USB3_EP_STS_STREAMR_MASK) #define USB3_EP_STS_MD_EXIT_MASK (0x40U) #define USB3_EP_STS_MD_EXIT_SHIFT (6U) /*! MD_EXIT - EXIT from MOVE DATA State (used only for stream transfers in SS mode) This bit is set * to '1' if stream capable endpoint exits from MOVE DATA state of Bulk IN/OUT Stream Ptrotocol * State Machine (ISPSM/OSPSM). Stream support is class-dependent. This interrupt can be masked by * the corresponding bit in MD_EXITEN register. Writing '1' to this bit clears the interrupt */ #define USB3_EP_STS_MD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_MD_EXIT_SHIFT)) & USB3_EP_STS_MD_EXIT_MASK) #define USB3_EP_STS_TRBERR_MASK (0x80U) #define USB3_EP_STS_TRBERR_SHIFT (7U) /*! TRBERR - TRB error. This bit is set if DMA read corrupted TRB (wrong C bit value or TRB type). * Address of the TRB is stored in the EP_TRADDR register. This interrupt can be masked by the * corresponding bit in EP_STS_EN register. If this error occurs, the bit DRDY is cleared and held * in the low state until the TRBERR is not cleared. To start the DMA again, the software has to * clear this interrupt and set the DRDY bit once more. Writing '1' to this bit clears the * interrupt */ #define USB3_EP_STS_TRBERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_TRBERR_SHIFT)) & USB3_EP_STS_TRBERR_MASK) #define USB3_EP_STS_NRDY_MASK (0x100U) #define USB3_EP_STS_NRDY_SHIFT (8U) /*! NRDY - Not ready (used only in SS mode). This bit is automatically set to 1 when for some reason * endpoint enters Flow Control. If ERDY is sent automatically by the endpoint (what is done * when current TDL value is greater then zero), this interrupt bit is not automatically cleared * (although the endpoint itself leaves FlowControl). Note: For BULK OUT endpoints with TDL_CHK bit * seting this interrupt should be used instead of DESCMIS interrupt. See also DESCMIS * description. Writing '1' to this bit clears the interrupt */ #define USB3_EP_STS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_NRDY_SHIFT)) & USB3_EP_STS_NRDY_MASK) #define USB3_EP_STS_DBUSY_MASK (0x200U) #define USB3_EP_STS_DBUSY_SHIFT (9U) /*! DBUSY - DMA busy. This bit is set to '1' while the DMA services the endpoint. Through the * service means either actual transmission of data between on-chip cache and system memory for * particular endpoint or a pending data transmission which has already begun but was interrupted by * endpoint with a higher priority. Such pending transmissions will begin automatically themselves * after these higher priority. This bit is only a status bit (not an interrupt flag) */ #define USB3_EP_STS_DBUSY(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_DBUSY_SHIFT)) & USB3_EP_STS_DBUSY_MASK) #define USB3_EP_STS_BUFFEMPTY_MASK (0x400U) #define USB3_EP_STS_BUFFEMPTY_SHIFT (10U) /*! BUFFEMPTY - Endpoint Buffer Empty. When this bit is set to '1', there are no packets for the * particular endpoint in the on-chip buffers. This bit is only a status bit (not an interrupt flag) */ #define USB3_EP_STS_BUFFEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_BUFFEMPTY_SHIFT)) & USB3_EP_STS_BUFFEMPTY_MASK) #define USB3_EP_STS_CCS_MASK (0x800U) #define USB3_EP_STS_CCS_SHIFT (11U) /*! CCS - Current Cycle Status. Informs about current value of C bit corresponding to DMA ownership * of TRBs for selected endpoint. For more information about TRBs C bit see chapter 2.11.3. This * bit is only a status bit (not an interrupt flag) */ #define USB3_EP_STS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_CCS_SHIFT)) & USB3_EP_STS_CCS_MASK) #define USB3_EP_STS_PRIME_MASK (0x1000U) #define USB3_EP_STS_PRIME_SHIFT (12U) /*! PRIME - Prime (used only in SS mode). This bit is set when the device receives the packet with * PRIME ID. This interrupt can be masked by the corresponding bit in EP_STS_EN register. Writing * '1' to this bit clears the interrupt */ #define USB3_EP_STS_PRIME(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_PRIME_SHIFT)) & USB3_EP_STS_PRIME_MASK) #define USB3_EP_STS_SIDERR_MASK (0x2000U) #define USB3_EP_STS_SIDERR_SHIFT (13U) /*! SIDERR - Stream error (used only in SS mode) If host requested IN (sent OUT) packet with * particular Stream ID, and device is actually programmed to transfer packets with different Stream ID * (SID written in the EP_CMD.ERDY_SID field) the host IN request (OUT packet) is rejected (NRDY) * and the SIDERR interrupt is requested. In case of IN direction, the SIDERR interrupt will not * be requested when device is not prepared for any transfer (EP_CMD.TDL= 0 for this endpoint). * In this case (and additionally when EP_CMD.DRDY= 0 and EP_STS.DBUSY=0), the DESCMIS interrupt * will be requested. This interrupt can be masked by the corresponding bit in EP_STS_EN * register. Writing '1' to this bit clears the interrupt */ #define USB3_EP_STS_SIDERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SIDERR_SHIFT)) & USB3_EP_STS_SIDERR_MASK) #define USB3_EP_STS_OUTSMM_MASK (0x4000U) #define USB3_EP_STS_OUTSMM_SHIFT (14U) /*! OUTSMM - OUT size mismatch. This bit is set when host sends a different data size than device * was anticipating (according to Data Length field in TRB). In such a case, the DMA updates length * field in current TRB, updates TRADDR (next TRB address), and triggers the interrupt. DMA will * not start processing TRB ring of this EP until its DRDY is set. This interrupt can be masked * by the corresponding bit in EP_STS_EN register. Writing '1' to this bit clears the interrupt */ #define USB3_EP_STS_OUTSMM(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_OUTSMM_SHIFT)) & USB3_EP_STS_OUTSMM_MASK) #define USB3_EP_STS_ISOERR_MASK (0x8000U) #define USB3_EP_STS_ISOERR_SHIFT (15U) /*! ISOERR - ISO transmission error. Error of isochronous transmission. This bit is set during data * transmission to/from ISO endpoints while the last data transfer at PIPE IF is in current micro * frame. For ISO IN endpoints: If host asks for data packet and device is not ready for sent * data immediatelly, then ISOERR flag is set for particular endpoint and core sends a 0-length * DATA packet to the host. The next data portion transfer (for the next micro frame) from system * memory to on-chip buffers is automatically started (when EP_CMD.DRDY bit is set or DMA works in * DMULT mode). For ISO OUT endpoints: When host issues an OUT data packet for the specific * endpoint but the OUT buffers are full, then device is unable to receive data packet and the ISOERR * flag is set. For more information about ISO trasfer see chapter 'Isochronous Transfers'. This * interrupt can be masked by the corresponding bit in EP_STS_EN register. Writing '1' to this * bit clears the interrupt */ #define USB3_EP_STS_ISOERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_ISOERR_SHIFT)) & USB3_EP_STS_ISOERR_MASK) #define USB3_EP_STS_HOSTPP_MASK (0x10000U) #define USB3_EP_STS_HOSTPP_SHIFT (16U) /*! HOSTPP - Host Packet Pending (only for SS mode). Depending on whether the endpoint is enabled * for streams or not, this bit behaves as follows: 1)For stream enabled bulk endpoints * (EP_CFG.EPSTREAM_EN bit set): This bit reflects the PP bit in the last packet received from the host * during Move Data state of the DOSPSM for the OUT endpoint. This bit is updated on exit from the * MOVE DATA state of the DOSPSM and can be analyzed during servicing MD_EXIT interrupt for BULK * OUT endpoint with Stream support enabled. If this bit is set to '0' during MD_EXIT interrupt, it * means that the host terminated current stream. If this bit is set to '1' during MD_EXIT * interrupt, it means that the host doesn't terminated current stream and still has data for this * stream. 2)Non stream bulk endpoints (EP_CFG.EPSTREAM_EN bit not set): This bit reflects the PP * bit in the packets received from the host. This bit is updated as long as the EP_CMD.TDL is * nonzero and it can be analyzed during servicing IOT interrupt for BULK endpoints. This bit is only * a status bit (not an interrupt flag) */ #define USB3_EP_STS_HOSTPP(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_HOSTPP_SHIFT)) & USB3_EP_STS_HOSTPP_MASK) #define USB3_EP_STS_SPSMST_MASK (0x60000U) #define USB3_EP_STS_SPSMST_SHIFT (17U) /*! SPSMST - Stream Protocol State Machine State (only for Bulk stream endpoints) This field is * valid only for stream capable bulk endpoints and reflects the current state of the Stream Protocol * State Machine for selected endpoint: 0 - DISABLED 1 - IDLE 2 - START_STREAM 3 - MOVE_DATA * Soft should check if the SPSM is in IDLE state before sending ERDY TP from stream EP (leading to * the transition from IDE to START_STREAM) Before software will order to send an ERDY TP from * stream capable endpoint (leading to the transition from IDLE to START_STREAM) it should first * check if the SPSM is in IDLE state. This bit is only a status bit (not an interrupt flag) */ #define USB3_EP_STS_SPSMST(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SPSMST_SHIFT)) & USB3_EP_STS_SPSMST_MASK) #define USB3_EP_STS_IOT_MASK (0x80000U) #define USB3_EP_STS_IOT_SHIFT (19U) /*! IOT - Interrupt On Transfer complete. This interrupt is generated when the field EP_CMD.TDL is * decremented to zero. It means that the device - does not expect to have more packets from the * host (OUT EP) - does not want to send more packets (IN EP) More information can be found in the * description of EP_CMD.TDL field. Writing '1' to this bit clears the interrupt */ #define USB3_EP_STS_IOT(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_IOT_SHIFT)) & USB3_EP_STS_IOT_MASK) #define USB3_EP_STS_RESERVED0_MASK (0xF00000U) #define USB3_EP_STS_RESERVED0_SHIFT (20U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_EP_STS_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_RESERVED0_SHIFT)) & USB3_EP_STS_RESERVED0_MASK) #define USB3_EP_STS_OUTQ_NO_MASK (0xF000000U) #define USB3_EP_STS_OUTQ_NO_SHIFT (24U) /*! OUTQ_NO - OUT queue endpoint number. This field shows the number of the endpoint to which the * packet, received by the host, currently is waiting to be transmitted by the DMA from the on-chip * buffers to the system memory. As there is one buffers queue for all Out Endpoints, this field * is not endpoint related, and thus it can be read regardless of current value stored in the * EP_SEL register. This bit is only a status bit (not an interrupt flag) */ #define USB3_EP_STS_OUTQ_NO(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_OUTQ_NO_SHIFT)) & USB3_EP_STS_OUTQ_NO_MASK) #define USB3_EP_STS_OUTQ_VAL_MASK (0x10000000U) #define USB3_EP_STS_OUTQ_VAL_SHIFT (28U) /*! OUTQ_VAL - OUT queue valid flag. This field indicates whether the endpoint number of the OUT * packet waiting for transmission by the DMA, is valid or not. In other words, whether the packet * queue is not empty. As there is one buffers queue for all Out Endpoints, this field is not * endpoint related, and thus it can be read regardless of current value stored in the EP_SEL * register. 0 - queue of out packets is empty thus OUTQ_NO is not valid 1 - queue of out packets is not * empty thus OUTQ_NO is valid This bit is only a status bit (not an interrupt flag) */ #define USB3_EP_STS_OUTQ_VAL(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_OUTQ_VAL_SHIFT)) & USB3_EP_STS_OUTQ_VAL_MASK) #define USB3_EP_STS_RESERVED1_MASK (0x60000000U) #define USB3_EP_STS_RESERVED1_SHIFT (29U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_EP_STS_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_RESERVED1_SHIFT)) & USB3_EP_STS_RESERVED1_MASK) #define USB3_EP_STS_STPWAIT_MASK (0x80000000U) #define USB3_EP_STS_STPWAIT_SHIFT (31U) /*! STPWAIT - Bit used only for EP0. If setup packet is received correctly and stored in the on-chip * buffer, this bit is set to 1 and interrupt is generated. Setup packet is applicable only to * control transmissions (EP0). This interrupt can be masked by the corresponding bit in EP_STS_EN * register. Writing '1' to this bit clears the interrupt */ #define USB3_EP_STS_STPWAIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_STPWAIT_SHIFT)) & USB3_EP_STS_STPWAIT_MASK) /*! @} */ /*! @name EP_STS_SID - Endpoint Status */ /*! @{ */ #define USB3_EP_STS_SID_SID_MASK (0xFFFFU) #define USB3_EP_STS_SID_SID_SHIFT (0U) /*! SID - Stream ID (used only in SS mode). Stream ID of packet, which generates interrupt. The * interrupts that update the SID field are: - SIDERR for EP OUT - SIDERR/DESCMIS for EP IN For the * above interrupts, the values of the SID field reflects: - in case of SIDERR for EP OUT this * field reflects the Stream ID of OUT packet sent by host which was rejected by the device, due to * SID_CHK bit set - in case of SIDERR/DESCMIS for EP IN this field reflects the Stream ID of ACK * TP sent by host which was rejected by the device */ #define USB3_EP_STS_SID_SID(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SID_SID_SHIFT)) & USB3_EP_STS_SID_SID_MASK) #define USB3_EP_STS_SID_RESERVED_MASK (0xFFFF0000U) #define USB3_EP_STS_SID_RESERVED_SHIFT (16U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_EP_STS_SID_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SID_RESERVED_SHIFT)) & USB3_EP_STS_SID_RESERVED_MASK) /*! @} */ /*! @name EP_STS_EN - Endpoint Status Register Enable */ /*! @{ */ #define USB3_EP_STS_EN_SETUPEN_MASK (0x1U) #define USB3_EP_STS_EN_SETUPEN_SHIFT (0U) /*! SETUPEN - Setup transfer complete. This bit enables the SETUP interrupt. Valid only for EP0 */ #define USB3_EP_STS_EN_SETUPEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_SETUPEN_SHIFT)) & USB3_EP_STS_EN_SETUPEN_MASK) #define USB3_EP_STS_EN_RESERVED0_MASK (0xEU) #define USB3_EP_STS_EN_RESERVED0_SHIFT (1U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_EP_STS_EN_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED0_SHIFT)) & USB3_EP_STS_EN_RESERVED0_MASK) #define USB3_EP_STS_EN_DESCMISEN_MASK (0x10U) #define USB3_EP_STS_EN_DESCMISEN_SHIFT (4U) /*! DESCMISEN - OUT transfer missing descriptor enable. This bit enables the DESCMIS interrupt */ #define USB3_EP_STS_EN_DESCMISEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_DESCMISEN_SHIFT)) & USB3_EP_STS_EN_DESCMISEN_MASK) #define USB3_EP_STS_EN_STREAMREN_MASK (0x20U) #define USB3_EP_STS_EN_STREAMREN_SHIFT (5U) /*! STREAMREN - Stream Rejected enable. This bit enables the STREAMR interrupt */ #define USB3_EP_STS_EN_STREAMREN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_STREAMREN_SHIFT)) & USB3_EP_STS_EN_STREAMREN_MASK) #define USB3_EP_STS_EN_MD_EXITEN_MASK (0x40U) #define USB3_EP_STS_EN_MD_EXITEN_SHIFT (6U) /*! MD_EXITEN - Move Data Exit enable. This bit enables the MD_EXIT interrupt */ #define USB3_EP_STS_EN_MD_EXITEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_MD_EXITEN_SHIFT)) & USB3_EP_STS_EN_MD_EXITEN_MASK) #define USB3_EP_STS_EN_TRBERREN_MASK (0x80U) #define USB3_EP_STS_EN_TRBERREN_SHIFT (7U) /*! TRBERREN - TRB enable. This bit enables the TRBERR interrupt */ #define USB3_EP_STS_EN_TRBERREN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_TRBERREN_SHIFT)) & USB3_EP_STS_EN_TRBERREN_MASK) #define USB3_EP_STS_EN_NRDYEN_MASK (0x100U) #define USB3_EP_STS_EN_NRDYEN_SHIFT (8U) /*! NRDYEN - NRDY enable. This bit enables the NRDY interrupt */ #define USB3_EP_STS_EN_NRDYEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_NRDYEN_SHIFT)) & USB3_EP_STS_EN_NRDYEN_MASK) #define USB3_EP_STS_EN_RESERVED1_MASK (0xE00U) #define USB3_EP_STS_EN_RESERVED1_SHIFT (9U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_EP_STS_EN_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED1_SHIFT)) & USB3_EP_STS_EN_RESERVED1_MASK) #define USB3_EP_STS_EN_PRIMEEN_MASK (0x1000U) #define USB3_EP_STS_EN_PRIMEEN_SHIFT (12U) /*! PRIMEEN - Prime enable. This bit enables the PRIME interrupt */ #define USB3_EP_STS_EN_PRIMEEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_PRIMEEN_SHIFT)) & USB3_EP_STS_EN_PRIMEEN_MASK) #define USB3_EP_STS_EN_SIDERREN_MASK (0x2000U) #define USB3_EP_STS_EN_SIDERREN_SHIFT (13U) /*! SIDERREN - Stream error enable. This bit enables the SIDERR interrupt */ #define USB3_EP_STS_EN_SIDERREN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_SIDERREN_SHIFT)) & USB3_EP_STS_EN_SIDERREN_MASK) #define USB3_EP_STS_EN_OUTSMMEN_MASK (0x4000U) #define USB3_EP_STS_EN_OUTSMMEN_SHIFT (14U) /*! OUTSMMEN - OUT size mismatch enable. This bit enables the OUTSMM interrupt */ #define USB3_EP_STS_EN_OUTSMMEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_OUTSMMEN_SHIFT)) & USB3_EP_STS_EN_OUTSMMEN_MASK) #define USB3_EP_STS_EN_ISOERREN_MASK (0x8000U) #define USB3_EP_STS_EN_ISOERREN_SHIFT (15U) /*! ISOERREN - ISO transmission error enable. This bit enables the ISOERR interrupt */ #define USB3_EP_STS_EN_ISOERREN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_ISOERREN_SHIFT)) & USB3_EP_STS_EN_ISOERREN_MASK) #define USB3_EP_STS_EN_RESERVED2_MASK (0x70000U) #define USB3_EP_STS_EN_RESERVED2_SHIFT (16U) /*! RESERVED2 - Reserved field. Write ignored. 0 when read */ #define USB3_EP_STS_EN_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED2_SHIFT)) & USB3_EP_STS_EN_RESERVED2_MASK) #define USB3_EP_STS_EN_IOTEN_MASK (0x80000U) #define USB3_EP_STS_EN_IOTEN_SHIFT (19U) /*! IOTEN - Interrupt on Transmission complete enable. This bit enables the IOT interrupt */ #define USB3_EP_STS_EN_IOTEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_IOTEN_SHIFT)) & USB3_EP_STS_EN_IOTEN_MASK) #define USB3_EP_STS_EN_RESERVED3_MASK (0x7FF00000U) #define USB3_EP_STS_EN_RESERVED3_SHIFT (20U) /*! RESERVED3 - Reserved field. Write ignored. 0 when read */ #define USB3_EP_STS_EN_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED3_SHIFT)) & USB3_EP_STS_EN_RESERVED3_MASK) #define USB3_EP_STS_EN_STPWAITEN_MASK (0x80000000U) #define USB3_EP_STS_EN_STPWAITEN_SHIFT (31U) /*! STPWAITEN - Setup Wait interrupt enable. This bit enables the STPWAIT interrupt. Valid only for EP0 */ #define USB3_EP_STS_EN_STPWAITEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_STPWAITEN_SHIFT)) & USB3_EP_STS_EN_STPWAITEN_MASK) /*! @} */ /*! @name DRBL - Doorbell Register */ /*! @{ */ #define USB3_DRBL_DRBL0O_MASK (0x1U) #define USB3_DRBL_DRBL0O_SHIFT (0U) /*! DRBL0O - DRBL0O */ #define USB3_DRBL_DRBL0O(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL0O_SHIFT)) & USB3_DRBL_DRBL0O_MASK) #define USB3_DRBL_DRBL1O_MASK (0x2U) #define USB3_DRBL_DRBL1O_SHIFT (1U) /*! DRBL1O - DRBL1O */ #define USB3_DRBL_DRBL1O(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL1O_SHIFT)) & USB3_DRBL_DRBL1O_MASK) #define USB3_DRBL_DRBL2O_MASK (0x4U) #define USB3_DRBL_DRBL2O_SHIFT (2U) /*! DRBL2O - DRBL2O */ #define USB3_DRBL_DRBL2O(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL2O_SHIFT)) & USB3_DRBL_DRBL2O_MASK) #define USB3_DRBL_DRBL3O_MASK (0x8U) #define USB3_DRBL_DRBL3O_SHIFT (3U) /*! DRBL3O - DRBL3O */ #define USB3_DRBL_DRBL3O(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL3O_SHIFT)) & USB3_DRBL_DRBL3O_MASK) #define USB3_DRBL_DRBL4O_MASK (0x10U) #define USB3_DRBL_DRBL4O_SHIFT (4U) /*! DRBL4O - DRBL4O */ #define USB3_DRBL_DRBL4O(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL4O_SHIFT)) & USB3_DRBL_DRBL4O_MASK) #define USB3_DRBL_DRBL5O_MASK (0x20U) #define USB3_DRBL_DRBL5O_SHIFT (5U) /*! DRBL5O - DRBL5O */ #define USB3_DRBL_DRBL5O(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL5O_SHIFT)) & USB3_DRBL_DRBL5O_MASK) #define USB3_DRBL_DRBL6O_MASK (0x40U) #define USB3_DRBL_DRBL6O_SHIFT (6U) /*! DRBL6O - DRBL6O */ #define USB3_DRBL_DRBL6O(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL6O_SHIFT)) & USB3_DRBL_DRBL6O_MASK) #define USB3_DRBL_DRBL7O_MASK (0x80U) #define USB3_DRBL_DRBL7O_SHIFT (7U) /*! DRBL7O - DRBL7O */ #define USB3_DRBL_DRBL7O(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL7O_SHIFT)) & USB3_DRBL_DRBL7O_MASK) #define USB3_DRBL_reserved8_MASK (0x100U) #define USB3_DRBL_reserved8_SHIFT (8U) /*! reserved8 - reserved8 */ #define USB3_DRBL_reserved8(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved8_SHIFT)) & USB3_DRBL_reserved8_MASK) #define USB3_DRBL_reserved9_MASK (0x200U) #define USB3_DRBL_reserved9_SHIFT (9U) /*! reserved9 - reserved9 */ #define USB3_DRBL_reserved9(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved9_SHIFT)) & USB3_DRBL_reserved9_MASK) #define USB3_DRBL_reserved10_MASK (0x400U) #define USB3_DRBL_reserved10_SHIFT (10U) /*! reserved10 - reserved10 */ #define USB3_DRBL_reserved10(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved10_SHIFT)) & USB3_DRBL_reserved10_MASK) #define USB3_DRBL_reserved11_MASK (0x800U) #define USB3_DRBL_reserved11_SHIFT (11U) /*! reserved11 - reserved11 */ #define USB3_DRBL_reserved11(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved11_SHIFT)) & USB3_DRBL_reserved11_MASK) #define USB3_DRBL_reserved12_MASK (0x1000U) #define USB3_DRBL_reserved12_SHIFT (12U) /*! reserved12 - reserved12 */ #define USB3_DRBL_reserved12(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved12_SHIFT)) & USB3_DRBL_reserved12_MASK) #define USB3_DRBL_reserved13_MASK (0x2000U) #define USB3_DRBL_reserved13_SHIFT (13U) /*! reserved13 - reserved13 */ #define USB3_DRBL_reserved13(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved13_SHIFT)) & USB3_DRBL_reserved13_MASK) #define USB3_DRBL_reserved14_MASK (0x4000U) #define USB3_DRBL_reserved14_SHIFT (14U) /*! reserved14 - reserved14 */ #define USB3_DRBL_reserved14(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved14_SHIFT)) & USB3_DRBL_reserved14_MASK) #define USB3_DRBL_reserved15_MASK (0x8000U) #define USB3_DRBL_reserved15_SHIFT (15U) /*! reserved15 - reserved15 */ #define USB3_DRBL_reserved15(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved15_SHIFT)) & USB3_DRBL_reserved15_MASK) #define USB3_DRBL_DRBL0I_MASK (0x10000U) #define USB3_DRBL_DRBL0I_SHIFT (16U) /*! DRBL0I - DRBL0I */ #define USB3_DRBL_DRBL0I(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL0I_SHIFT)) & USB3_DRBL_DRBL0I_MASK) #define USB3_DRBL_DRBL1I_MASK (0x20000U) #define USB3_DRBL_DRBL1I_SHIFT (17U) /*! DRBL1I - DRBL1I */ #define USB3_DRBL_DRBL1I(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL1I_SHIFT)) & USB3_DRBL_DRBL1I_MASK) #define USB3_DRBL_DRBL2I_MASK (0x40000U) #define USB3_DRBL_DRBL2I_SHIFT (18U) /*! DRBL2I - DRBL2I */ #define USB3_DRBL_DRBL2I(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL2I_SHIFT)) & USB3_DRBL_DRBL2I_MASK) #define USB3_DRBL_DRBL3I_MASK (0x80000U) #define USB3_DRBL_DRBL3I_SHIFT (19U) /*! DRBL3I - DRBL3I */ #define USB3_DRBL_DRBL3I(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL3I_SHIFT)) & USB3_DRBL_DRBL3I_MASK) #define USB3_DRBL_DRBL4I_MASK (0x100000U) #define USB3_DRBL_DRBL4I_SHIFT (20U) /*! DRBL4I - DRBL4I */ #define USB3_DRBL_DRBL4I(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL4I_SHIFT)) & USB3_DRBL_DRBL4I_MASK) #define USB3_DRBL_DRBL5I_MASK (0x200000U) #define USB3_DRBL_DRBL5I_SHIFT (21U) /*! DRBL5I - DRBL5I */ #define USB3_DRBL_DRBL5I(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL5I_SHIFT)) & USB3_DRBL_DRBL5I_MASK) #define USB3_DRBL_DRBL6I_MASK (0x400000U) #define USB3_DRBL_DRBL6I_SHIFT (22U) /*! DRBL6I - DRBL6I */ #define USB3_DRBL_DRBL6I(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL6I_SHIFT)) & USB3_DRBL_DRBL6I_MASK) #define USB3_DRBL_DRBL7I_MASK (0x800000U) #define USB3_DRBL_DRBL7I_SHIFT (23U) /*! DRBL7I - DRBL7I */ #define USB3_DRBL_DRBL7I(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL7I_SHIFT)) & USB3_DRBL_DRBL7I_MASK) #define USB3_DRBL_reserved24_MASK (0x1000000U) #define USB3_DRBL_reserved24_SHIFT (24U) /*! reserved24 - reserved24 */ #define USB3_DRBL_reserved24(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved24_SHIFT)) & USB3_DRBL_reserved24_MASK) #define USB3_DRBL_reserved25_MASK (0x2000000U) #define USB3_DRBL_reserved25_SHIFT (25U) /*! reserved25 - reserved25 */ #define USB3_DRBL_reserved25(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved25_SHIFT)) & USB3_DRBL_reserved25_MASK) #define USB3_DRBL_reserved26_MASK (0x4000000U) #define USB3_DRBL_reserved26_SHIFT (26U) /*! reserved26 - reserved26 */ #define USB3_DRBL_reserved26(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved26_SHIFT)) & USB3_DRBL_reserved26_MASK) #define USB3_DRBL_reserved27_MASK (0x8000000U) #define USB3_DRBL_reserved27_SHIFT (27U) /*! reserved27 - reserved27 */ #define USB3_DRBL_reserved27(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved27_SHIFT)) & USB3_DRBL_reserved27_MASK) #define USB3_DRBL_reserved28_MASK (0x10000000U) #define USB3_DRBL_reserved28_SHIFT (28U) /*! reserved28 - reserved28 */ #define USB3_DRBL_reserved28(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved28_SHIFT)) & USB3_DRBL_reserved28_MASK) #define USB3_DRBL_reserved29_MASK (0x20000000U) #define USB3_DRBL_reserved29_SHIFT (29U) /*! reserved29 - reserved29 */ #define USB3_DRBL_reserved29(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved29_SHIFT)) & USB3_DRBL_reserved29_MASK) #define USB3_DRBL_reserved30_MASK (0x40000000U) #define USB3_DRBL_reserved30_SHIFT (30U) /*! reserved30 - reserved30 */ #define USB3_DRBL_reserved30(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved30_SHIFT)) & USB3_DRBL_reserved30_MASK) #define USB3_DRBL_reserved31_MASK (0x80000000U) #define USB3_DRBL_reserved31_SHIFT (31U) /*! reserved31 - reserved31 */ #define USB3_DRBL_reserved31(x) (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved31_SHIFT)) & USB3_DRBL_reserved31_MASK) /*! @} */ /*! @name EP_IEN - Endpoints Interrupt Enable) */ /*! @{ */ #define USB3_EP_IEN_EOUTEN0_MASK (0x1U) #define USB3_EP_IEN_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUTEN0 */ #define USB3_EP_IEN_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN0_SHIFT)) & USB3_EP_IEN_EOUTEN0_MASK) #define USB3_EP_IEN_EOUTEN1_MASK (0x2U) #define USB3_EP_IEN_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUTEN1 */ #define USB3_EP_IEN_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN1_SHIFT)) & USB3_EP_IEN_EOUTEN1_MASK) #define USB3_EP_IEN_EOUTEN2_MASK (0x4U) #define USB3_EP_IEN_EOUTEN2_SHIFT (2U) /*! EOUTEN2 - EOUTEN2 */ #define USB3_EP_IEN_EOUTEN2(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN2_SHIFT)) & USB3_EP_IEN_EOUTEN2_MASK) #define USB3_EP_IEN_EOUTEN3_MASK (0x8U) #define USB3_EP_IEN_EOUTEN3_SHIFT (3U) /*! EOUTEN3 - EOUTEN3 */ #define USB3_EP_IEN_EOUTEN3(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN3_SHIFT)) & USB3_EP_IEN_EOUTEN3_MASK) #define USB3_EP_IEN_EOUTEN4_MASK (0x10U) #define USB3_EP_IEN_EOUTEN4_SHIFT (4U) /*! EOUTEN4 - EOUTEN4 */ #define USB3_EP_IEN_EOUTEN4(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN4_SHIFT)) & USB3_EP_IEN_EOUTEN4_MASK) #define USB3_EP_IEN_EOUTEN5_MASK (0x20U) #define USB3_EP_IEN_EOUTEN5_SHIFT (5U) /*! EOUTEN5 - EOUTEN5 */ #define USB3_EP_IEN_EOUTEN5(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN5_SHIFT)) & USB3_EP_IEN_EOUTEN5_MASK) #define USB3_EP_IEN_EOUTEN6_MASK (0x40U) #define USB3_EP_IEN_EOUTEN6_SHIFT (6U) /*! EOUTEN6 - EOUTEN6 */ #define USB3_EP_IEN_EOUTEN6(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN6_SHIFT)) & USB3_EP_IEN_EOUTEN6_MASK) #define USB3_EP_IEN_EOUTEN7_MASK (0x80U) #define USB3_EP_IEN_EOUTEN7_SHIFT (7U) /*! EOUTEN7 - EOUTEN7 */ #define USB3_EP_IEN_EOUTEN7(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN7_SHIFT)) & USB3_EP_IEN_EOUTEN7_MASK) #define USB3_EP_IEN_reserved8_MASK (0x100U) #define USB3_EP_IEN_reserved8_SHIFT (8U) /*! reserved8 - reserved8 */ #define USB3_EP_IEN_reserved8(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved8_SHIFT)) & USB3_EP_IEN_reserved8_MASK) #define USB3_EP_IEN_reserved9_MASK (0x200U) #define USB3_EP_IEN_reserved9_SHIFT (9U) /*! reserved9 - reserved9 */ #define USB3_EP_IEN_reserved9(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved9_SHIFT)) & USB3_EP_IEN_reserved9_MASK) #define USB3_EP_IEN_reserved10_MASK (0x400U) #define USB3_EP_IEN_reserved10_SHIFT (10U) /*! reserved10 - reserved10 */ #define USB3_EP_IEN_reserved10(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved10_SHIFT)) & USB3_EP_IEN_reserved10_MASK) #define USB3_EP_IEN_reserved11_MASK (0x800U) #define USB3_EP_IEN_reserved11_SHIFT (11U) /*! reserved11 - reserved11 */ #define USB3_EP_IEN_reserved11(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved11_SHIFT)) & USB3_EP_IEN_reserved11_MASK) #define USB3_EP_IEN_reserved12_MASK (0x1000U) #define USB3_EP_IEN_reserved12_SHIFT (12U) /*! reserved12 - reserved12 */ #define USB3_EP_IEN_reserved12(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved12_SHIFT)) & USB3_EP_IEN_reserved12_MASK) #define USB3_EP_IEN_reserved13_MASK (0x2000U) #define USB3_EP_IEN_reserved13_SHIFT (13U) /*! reserved13 - reserved13 */ #define USB3_EP_IEN_reserved13(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved13_SHIFT)) & USB3_EP_IEN_reserved13_MASK) #define USB3_EP_IEN_reserved14_MASK (0x4000U) #define USB3_EP_IEN_reserved14_SHIFT (14U) /*! reserved14 - reserved14 */ #define USB3_EP_IEN_reserved14(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved14_SHIFT)) & USB3_EP_IEN_reserved14_MASK) #define USB3_EP_IEN_reserved15_MASK (0x8000U) #define USB3_EP_IEN_reserved15_SHIFT (15U) /*! reserved15 - reserved15 */ #define USB3_EP_IEN_reserved15(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved15_SHIFT)) & USB3_EP_IEN_reserved15_MASK) #define USB3_EP_IEN_EINEN0_MASK (0x10000U) #define USB3_EP_IEN_EINEN0_SHIFT (16U) /*! EINEN0 - EINEN0 */ #define USB3_EP_IEN_EINEN0(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN0_SHIFT)) & USB3_EP_IEN_EINEN0_MASK) #define USB3_EP_IEN_EINEN1_MASK (0x20000U) #define USB3_EP_IEN_EINEN1_SHIFT (17U) /*! EINEN1 - EINEN1 */ #define USB3_EP_IEN_EINEN1(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN1_SHIFT)) & USB3_EP_IEN_EINEN1_MASK) #define USB3_EP_IEN_EINEN2_MASK (0x40000U) #define USB3_EP_IEN_EINEN2_SHIFT (18U) /*! EINEN2 - EINEN2 */ #define USB3_EP_IEN_EINEN2(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN2_SHIFT)) & USB3_EP_IEN_EINEN2_MASK) #define USB3_EP_IEN_EINEN3_MASK (0x80000U) #define USB3_EP_IEN_EINEN3_SHIFT (19U) /*! EINEN3 - EINEN3 */ #define USB3_EP_IEN_EINEN3(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN3_SHIFT)) & USB3_EP_IEN_EINEN3_MASK) #define USB3_EP_IEN_EINEN4_MASK (0x100000U) #define USB3_EP_IEN_EINEN4_SHIFT (20U) /*! EINEN4 - EINEN4 */ #define USB3_EP_IEN_EINEN4(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN4_SHIFT)) & USB3_EP_IEN_EINEN4_MASK) #define USB3_EP_IEN_EINEN5_MASK (0x200000U) #define USB3_EP_IEN_EINEN5_SHIFT (21U) /*! EINEN5 - EINEN5 */ #define USB3_EP_IEN_EINEN5(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN5_SHIFT)) & USB3_EP_IEN_EINEN5_MASK) #define USB3_EP_IEN_EINEN6_MASK (0x400000U) #define USB3_EP_IEN_EINEN6_SHIFT (22U) /*! EINEN6 - EINEN6 */ #define USB3_EP_IEN_EINEN6(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN6_SHIFT)) & USB3_EP_IEN_EINEN6_MASK) #define USB3_EP_IEN_EINEN7_MASK (0x800000U) #define USB3_EP_IEN_EINEN7_SHIFT (23U) /*! EINEN7 - EINEN7 */ #define USB3_EP_IEN_EINEN7(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN7_SHIFT)) & USB3_EP_IEN_EINEN7_MASK) #define USB3_EP_IEN_reserved24_MASK (0x1000000U) #define USB3_EP_IEN_reserved24_SHIFT (24U) /*! reserved24 - reserved24 */ #define USB3_EP_IEN_reserved24(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved24_SHIFT)) & USB3_EP_IEN_reserved24_MASK) #define USB3_EP_IEN_reserved25_MASK (0x2000000U) #define USB3_EP_IEN_reserved25_SHIFT (25U) /*! reserved25 - reserved25 */ #define USB3_EP_IEN_reserved25(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved25_SHIFT)) & USB3_EP_IEN_reserved25_MASK) #define USB3_EP_IEN_reserved26_MASK (0x4000000U) #define USB3_EP_IEN_reserved26_SHIFT (26U) /*! reserved26 - reserved26 */ #define USB3_EP_IEN_reserved26(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved26_SHIFT)) & USB3_EP_IEN_reserved26_MASK) #define USB3_EP_IEN_reserved27_MASK (0x8000000U) #define USB3_EP_IEN_reserved27_SHIFT (27U) /*! reserved27 - reserved27 */ #define USB3_EP_IEN_reserved27(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved27_SHIFT)) & USB3_EP_IEN_reserved27_MASK) #define USB3_EP_IEN_reserved28_MASK (0x10000000U) #define USB3_EP_IEN_reserved28_SHIFT (28U) /*! reserved28 - reserved28 */ #define USB3_EP_IEN_reserved28(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved28_SHIFT)) & USB3_EP_IEN_reserved28_MASK) #define USB3_EP_IEN_reserved29_MASK (0x20000000U) #define USB3_EP_IEN_reserved29_SHIFT (29U) /*! reserved29 - reserved29 */ #define USB3_EP_IEN_reserved29(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved29_SHIFT)) & USB3_EP_IEN_reserved29_MASK) #define USB3_EP_IEN_reserved30_MASK (0x40000000U) #define USB3_EP_IEN_reserved30_SHIFT (30U) /*! reserved30 - reserved30 */ #define USB3_EP_IEN_reserved30(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved30_SHIFT)) & USB3_EP_IEN_reserved30_MASK) #define USB3_EP_IEN_reserved31_MASK (0x80000000U) #define USB3_EP_IEN_reserved31_SHIFT (31U) /*! reserved31 - reserved31 */ #define USB3_EP_IEN_reserved31(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved31_SHIFT)) & USB3_EP_IEN_reserved31_MASK) /*! @} */ /*! @name EP_ISTS - Endpoints Interrupt Status */ /*! @{ */ #define USB3_EP_ISTS_EOUT0_MASK (0x1U) #define USB3_EP_ISTS_EOUT0_SHIFT (0U) /*! EOUT0 - EOUT0 */ #define USB3_EP_ISTS_EOUT0(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT0_SHIFT)) & USB3_EP_ISTS_EOUT0_MASK) #define USB3_EP_ISTS_EOUT1_MASK (0x2U) #define USB3_EP_ISTS_EOUT1_SHIFT (1U) /*! EOUT1 - EOUT1 */ #define USB3_EP_ISTS_EOUT1(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT1_SHIFT)) & USB3_EP_ISTS_EOUT1_MASK) #define USB3_EP_ISTS_EOUT2_MASK (0x4U) #define USB3_EP_ISTS_EOUT2_SHIFT (2U) /*! EOUT2 - EOUT2 */ #define USB3_EP_ISTS_EOUT2(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT2_SHIFT)) & USB3_EP_ISTS_EOUT2_MASK) #define USB3_EP_ISTS_EOUT3_MASK (0x8U) #define USB3_EP_ISTS_EOUT3_SHIFT (3U) /*! EOUT3 - EOUT3 */ #define USB3_EP_ISTS_EOUT3(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT3_SHIFT)) & USB3_EP_ISTS_EOUT3_MASK) #define USB3_EP_ISTS_EOUT4_MASK (0x10U) #define USB3_EP_ISTS_EOUT4_SHIFT (4U) /*! EOUT4 - EOUT4 */ #define USB3_EP_ISTS_EOUT4(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT4_SHIFT)) & USB3_EP_ISTS_EOUT4_MASK) #define USB3_EP_ISTS_EOUT5_MASK (0x20U) #define USB3_EP_ISTS_EOUT5_SHIFT (5U) /*! EOUT5 - EOUT5 */ #define USB3_EP_ISTS_EOUT5(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT5_SHIFT)) & USB3_EP_ISTS_EOUT5_MASK) #define USB3_EP_ISTS_EOUT6_MASK (0x40U) #define USB3_EP_ISTS_EOUT6_SHIFT (6U) /*! EOUT6 - EOUT6 */ #define USB3_EP_ISTS_EOUT6(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT6_SHIFT)) & USB3_EP_ISTS_EOUT6_MASK) #define USB3_EP_ISTS_EOUT7_MASK (0x80U) #define USB3_EP_ISTS_EOUT7_SHIFT (7U) /*! EOUT7 - EOUT7 */ #define USB3_EP_ISTS_EOUT7(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT7_SHIFT)) & USB3_EP_ISTS_EOUT7_MASK) #define USB3_EP_ISTS_reserved8_MASK (0x100U) #define USB3_EP_ISTS_reserved8_SHIFT (8U) /*! reserved8 - reserved8 */ #define USB3_EP_ISTS_reserved8(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved8_SHIFT)) & USB3_EP_ISTS_reserved8_MASK) #define USB3_EP_ISTS_reserved9_MASK (0x200U) #define USB3_EP_ISTS_reserved9_SHIFT (9U) /*! reserved9 - reserved9 */ #define USB3_EP_ISTS_reserved9(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved9_SHIFT)) & USB3_EP_ISTS_reserved9_MASK) #define USB3_EP_ISTS_reserved10_MASK (0x400U) #define USB3_EP_ISTS_reserved10_SHIFT (10U) /*! reserved10 - reserved10 */ #define USB3_EP_ISTS_reserved10(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved10_SHIFT)) & USB3_EP_ISTS_reserved10_MASK) #define USB3_EP_ISTS_reserved11_MASK (0x800U) #define USB3_EP_ISTS_reserved11_SHIFT (11U) /*! reserved11 - reserved11 */ #define USB3_EP_ISTS_reserved11(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved11_SHIFT)) & USB3_EP_ISTS_reserved11_MASK) #define USB3_EP_ISTS_reserved12_MASK (0x1000U) #define USB3_EP_ISTS_reserved12_SHIFT (12U) /*! reserved12 - reserved12 */ #define USB3_EP_ISTS_reserved12(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved12_SHIFT)) & USB3_EP_ISTS_reserved12_MASK) #define USB3_EP_ISTS_reserved13_MASK (0x2000U) #define USB3_EP_ISTS_reserved13_SHIFT (13U) /*! reserved13 - reserved13 */ #define USB3_EP_ISTS_reserved13(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved13_SHIFT)) & USB3_EP_ISTS_reserved13_MASK) #define USB3_EP_ISTS_reserved14_MASK (0x4000U) #define USB3_EP_ISTS_reserved14_SHIFT (14U) /*! reserved14 - reserved14 */ #define USB3_EP_ISTS_reserved14(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved14_SHIFT)) & USB3_EP_ISTS_reserved14_MASK) #define USB3_EP_ISTS_reserved15_MASK (0x8000U) #define USB3_EP_ISTS_reserved15_SHIFT (15U) /*! reserved15 - reserved15 */ #define USB3_EP_ISTS_reserved15(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved15_SHIFT)) & USB3_EP_ISTS_reserved15_MASK) #define USB3_EP_ISTS_EIN0_MASK (0x10000U) #define USB3_EP_ISTS_EIN0_SHIFT (16U) /*! EIN0 - EIN0 */ #define USB3_EP_ISTS_EIN0(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN0_SHIFT)) & USB3_EP_ISTS_EIN0_MASK) #define USB3_EP_ISTS_EIN1_MASK (0x20000U) #define USB3_EP_ISTS_EIN1_SHIFT (17U) /*! EIN1 - EIN1 */ #define USB3_EP_ISTS_EIN1(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN1_SHIFT)) & USB3_EP_ISTS_EIN1_MASK) #define USB3_EP_ISTS_EIN2_MASK (0x40000U) #define USB3_EP_ISTS_EIN2_SHIFT (18U) /*! EIN2 - EIN2 */ #define USB3_EP_ISTS_EIN2(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN2_SHIFT)) & USB3_EP_ISTS_EIN2_MASK) #define USB3_EP_ISTS_EIN3_MASK (0x80000U) #define USB3_EP_ISTS_EIN3_SHIFT (19U) /*! EIN3 - EIN3 */ #define USB3_EP_ISTS_EIN3(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN3_SHIFT)) & USB3_EP_ISTS_EIN3_MASK) #define USB3_EP_ISTS_EIN4_MASK (0x100000U) #define USB3_EP_ISTS_EIN4_SHIFT (20U) /*! EIN4 - EIN4 */ #define USB3_EP_ISTS_EIN4(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN4_SHIFT)) & USB3_EP_ISTS_EIN4_MASK) #define USB3_EP_ISTS_EIN5_MASK (0x200000U) #define USB3_EP_ISTS_EIN5_SHIFT (21U) /*! EIN5 - EIN5 */ #define USB3_EP_ISTS_EIN5(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN5_SHIFT)) & USB3_EP_ISTS_EIN5_MASK) #define USB3_EP_ISTS_EIN6_MASK (0x400000U) #define USB3_EP_ISTS_EIN6_SHIFT (22U) /*! EIN6 - EIN6 */ #define USB3_EP_ISTS_EIN6(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN6_SHIFT)) & USB3_EP_ISTS_EIN6_MASK) #define USB3_EP_ISTS_EIN7_MASK (0x800000U) #define USB3_EP_ISTS_EIN7_SHIFT (23U) /*! EIN7 - EIN7 */ #define USB3_EP_ISTS_EIN7(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN7_SHIFT)) & USB3_EP_ISTS_EIN7_MASK) #define USB3_EP_ISTS_reserved24_MASK (0x1000000U) #define USB3_EP_ISTS_reserved24_SHIFT (24U) /*! reserved24 - reserved24 */ #define USB3_EP_ISTS_reserved24(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved24_SHIFT)) & USB3_EP_ISTS_reserved24_MASK) #define USB3_EP_ISTS_reserved25_MASK (0x2000000U) #define USB3_EP_ISTS_reserved25_SHIFT (25U) /*! reserved25 - reserved25 */ #define USB3_EP_ISTS_reserved25(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved25_SHIFT)) & USB3_EP_ISTS_reserved25_MASK) #define USB3_EP_ISTS_reserved26_MASK (0x4000000U) #define USB3_EP_ISTS_reserved26_SHIFT (26U) /*! reserved26 - reserved26 */ #define USB3_EP_ISTS_reserved26(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved26_SHIFT)) & USB3_EP_ISTS_reserved26_MASK) #define USB3_EP_ISTS_reserved27_MASK (0x8000000U) #define USB3_EP_ISTS_reserved27_SHIFT (27U) /*! reserved27 - reserved27 */ #define USB3_EP_ISTS_reserved27(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved27_SHIFT)) & USB3_EP_ISTS_reserved27_MASK) #define USB3_EP_ISTS_reserved28_MASK (0x10000000U) #define USB3_EP_ISTS_reserved28_SHIFT (28U) /*! reserved28 - reserved28 */ #define USB3_EP_ISTS_reserved28(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved28_SHIFT)) & USB3_EP_ISTS_reserved28_MASK) #define USB3_EP_ISTS_reserved29_MASK (0x20000000U) #define USB3_EP_ISTS_reserved29_SHIFT (29U) /*! reserved29 - reserved29 */ #define USB3_EP_ISTS_reserved29(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved29_SHIFT)) & USB3_EP_ISTS_reserved29_MASK) #define USB3_EP_ISTS_reserved30_MASK (0x40000000U) #define USB3_EP_ISTS_reserved30_SHIFT (30U) /*! reserved30 - reserved30 */ #define USB3_EP_ISTS_reserved30(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved30_SHIFT)) & USB3_EP_ISTS_reserved30_MASK) #define USB3_EP_ISTS_reserved31_MASK (0x80000000U) #define USB3_EP_ISTS_reserved31_SHIFT (31U) /*! reserved31 - reserved31 */ #define USB3_EP_ISTS_reserved31(x) (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved31_SHIFT)) & USB3_EP_ISTS_reserved31_MASK) /*! @} */ /*! @name USB_PWR - Global power configuration */ /*! @{ */ #define USB3_USB_PWR_PSO_EN_MASK (0x1U) #define USB3_USB_PWR_PSO_EN_SHIFT (0U) /*! PSO_EN - Power Shut Off capability enable. Writing '1' to this bit enables dower domains * switching capability and clears the PSO_DS bit. The Domain will be switched off if both PSO_EN will * be set and the USB controller will be in the in the U3 state. It is recommended to set this bit * in U3ENTI interrupt service, after software ensures that no data transfer is pending. If this * bit will be always set, the controller will automatically switch off the power in the * switchable PD after USB controller will enter U3 state */ #define USB3_USB_PWR_PSO_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_PSO_EN_SHIFT)) & USB3_USB_PWR_PSO_EN_MASK) #define USB3_USB_PWR_PSO_DS_MASK (0x2U) #define USB3_USB_PWR_PSO_DS_SHIFT (1U) /*! PSO_DS - Power Shut Off capability disable. Writing '1' to this bit disables power domains * switching capability and clears the PSO_EN bit. It is recommended to set this bit after during * U3EXTI interrupt service */ #define USB3_USB_PWR_PSO_DS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_PSO_DS_SHIFT)) & USB3_USB_PWR_PSO_DS_MASK) #define USB3_USB_PWR_RESERVED0_MASK (0xFCU) #define USB3_USB_PWR_RESERVED0_SHIFT (2U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_PWR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_RESERVED0_SHIFT)) & USB3_USB_PWR_RESERVED0_MASK) #define USB3_USB_PWR_STB_CLK_SWITCH_EN_MASK (0x100U) #define USB3_USB_PWR_STB_CLK_SWITCH_EN_SHIFT (8U) /*! STB_CLK_SWITCH_EN - Enables turning-off Reference Clock. This bit is optional and implemented * only when support for OTG is implemented (indicated by OTG_READY bit set to 1) */ #define USB3_USB_PWR_STB_CLK_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_STB_CLK_SWITCH_EN_SHIFT)) & USB3_USB_PWR_STB_CLK_SWITCH_EN_MASK) #define USB3_USB_PWR_STB_CLK_SWITCH_DONE_MASK (0x200U) #define USB3_USB_PWR_STB_CLK_SWITCH_DONE_SHIFT (9U) /*! STB_CLK_SWITCH_DONE - Status bit indicating that operation required by STB_CLK_SWITCH_EN write * is completed. This bit is optional and implemented only when support for OTG is implemented * (indicated by OTG_READY bit set to 1) */ #define USB3_USB_PWR_STB_CLK_SWITCH_DONE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_STB_CLK_SWITCH_DONE_SHIFT)) & USB3_USB_PWR_STB_CLK_SWITCH_DONE_MASK) #define USB3_USB_PWR_RESERVED1_MASK (0x3FFFFC00U) #define USB3_USB_PWR_RESERVED1_SHIFT (10U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_USB_PWR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_RESERVED1_SHIFT)) & USB3_USB_PWR_RESERVED1_MASK) #define USB3_USB_PWR_FAST_REG_ACCESS_STAT_MASK (0x40000000U) #define USB3_USB_PWR_FAST_REG_ACCESS_STAT_SHIFT (30U) /*! FAST_REG_ACCESS_STAT - Fast Registers Access status. This bit informs if Fast Registers Access * is enabled. It should be used as described in FAST_REG_ACCESS bit */ #define USB3_USB_PWR_FAST_REG_ACCESS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_FAST_REG_ACCESS_STAT_SHIFT)) & USB3_USB_PWR_FAST_REG_ACCESS_STAT_MASK) #define USB3_USB_PWR_FAST_REG_ACCESS_MASK (0x80000000U) #define USB3_USB_PWR_FAST_REG_ACCESS_SHIFT (31U) /*! FAST_REG_ACCESS - Fast Registers Access. When Device Port is in a low power state (U3/L2/Not * Connected), accesses to registers listed in section 2.3 of USBSS-DEV design specification may * take long time. In order to enable fast register access in that case, user can use this register * in the following way: - set FAST_REG_ACCESS bit - wait until FAST_REG_ACCESS_STAT bit is set - * perform required accesses - clear FAST_REG_ACCESS bit Note that to enable USBSS-DEV low power * state entry (U3/L2), the FAST_REG_ACCESS bit has to be cleared */ #define USB3_USB_PWR_FAST_REG_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_FAST_REG_ACCESS_SHIFT)) & USB3_USB_PWR_FAST_REG_ACCESS_MASK) /*! @} */ /*! @name USB_CONF2 - USB configuration */ /*! @{ */ #define USB3_USB_CONF2_AHB_RETRY_EN_MASK (0x1U) #define USB3_USB_CONF2_AHB_RETRY_EN_SHIFT (0U) /*! AHB_RETRY_EN - AHB retry enable. This bit enables the AHB retrys for AHB slave interface. This * bit has no effect when AHB slave interface is not implemented */ #define USB3_USB_CONF2_AHB_RETRY_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF2_AHB_RETRY_EN_SHIFT)) & USB3_USB_CONF2_AHB_RETRY_EN_MASK) #define USB3_USB_CONF2_RESERVED_MASK (0xFFFFFFFEU) #define USB3_USB_CONF2_RESERVED_SHIFT (1U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_USB_CONF2_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF2_RESERVED_SHIFT)) & USB3_USB_CONF2_RESERVED_MASK) /*! @} */ /*! @name USB_CAP1 - USB Capability */ /*! @{ */ #define USB3_USB_CAP1_SFR_TYPE_MASK (0xFU) #define USB3_USB_CAP1_SFR_TYPE_SHIFT (0U) /*! SFR_TYPE - SFR Interface type. This field reflects type of SFR interface implemented: 0x0 - OCP, * 0x1 - AHB, 0x2 - PLB, 0x3 - AXI, 0x4-0xF - reserved */ #define USB3_USB_CAP1_SFR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_SFR_TYPE_SHIFT)) & USB3_USB_CAP1_SFR_TYPE_MASK) #define USB3_USB_CAP1_SFR_WIDTH_MASK (0xF0U) #define USB3_USB_CAP1_SFR_WIDTH_SHIFT (4U) /*! SFR_WIDTH - SFR Interface width. This field reflects width of SFR interface implemented: - 0x0: * 8 bit interface, - 0x1: 16 bit interface, - 0x2: 32 bit interface, - 0x3: 64 bit interface, - * 0x4-0xF: reserved */ #define USB3_USB_CAP1_SFR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_SFR_WIDTH_SHIFT)) & USB3_USB_CAP1_SFR_WIDTH_MASK) #define USB3_USB_CAP1_DMA_TYPE_MASK (0xF00U) #define USB3_USB_CAP1_DMA_TYPE_SHIFT (8U) /*! DMA_TYPE - DMA Interface type. This field reflects type of DMA interface implemented: - 0x0: * OCP, - 0x1: AHB, - 0x2: PLB, - 0x3: AXI, - 0x4-0xF: reserved */ #define USB3_USB_CAP1_DMA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_DMA_TYPE_SHIFT)) & USB3_USB_CAP1_DMA_TYPE_MASK) #define USB3_USB_CAP1_DMA_WIDTH_MASK (0xF000U) #define USB3_USB_CAP1_DMA_WIDTH_SHIFT (12U) /*! DMA_WIDTH - DMA Interface width. This field reflects width of DMA interface implemented: - 0x0: * reserved, - 0x1: reserved, - 0x2: 32 bit interface, - 0x3: 64 bit interface, - 0x4-0xF: * reserved */ #define USB3_USB_CAP1_DMA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_DMA_WIDTH_SHIFT)) & USB3_USB_CAP1_DMA_WIDTH_MASK) #define USB3_USB_CAP1_U3PHY_TYPE_MASK (0xF0000U) #define USB3_USB_CAP1_U3PHY_TYPE_SHIFT (16U) /*! U3PHY_TYPE - USB3 PHY Interface type. This field reflects type of USB3 PHY interface * implemented: - 0x0: USB PIPE, - 0x1: RMMI, - 0x2-0xF: reserved */ #define USB3_USB_CAP1_U3PHY_TYPE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U3PHY_TYPE_SHIFT)) & USB3_USB_CAP1_U3PHY_TYPE_MASK) #define USB3_USB_CAP1_U3PHY_WIDTH_MASK (0xF00000U) #define USB3_USB_CAP1_U3PHY_WIDTH_SHIFT (20U) /*! U3PHY_WIDTH - USB3 PHY Interface width. This field reflects width of USB3 PHY interface * implemented: - 0x0: 8 bit PIPE interface, - 0x1: 16 bit PIPE interface, - 0x2: 32 bit PIPE interface, * - 0x3: 64 bit PIPE interface, - 0x4-0xF: reserved. Note: When SSIC interface is implemented * this field shows the width of internal PIPE interface. The RMMI interface is always 20-bit wide */ #define USB3_USB_CAP1_U3PHY_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U3PHY_WIDTH_SHIFT)) & USB3_USB_CAP1_U3PHY_WIDTH_MASK) #define USB3_USB_CAP1_U2PHY_EN_MASK (0x1000000U) #define USB3_USB_CAP1_U2PHY_EN_SHIFT (24U) /*! U2PHY_EN - USB2 PHY Interface enable. This field informs if USB2 PHY interface is implemented: - * interface NOT implemented: 0x0, - interface implemented: 0x1 */ #define USB3_USB_CAP1_U2PHY_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U2PHY_EN_SHIFT)) & USB3_USB_CAP1_U2PHY_EN_MASK) #define USB3_USB_CAP1_U2PHY_TYPE_MASK (0x2000000U) #define USB3_USB_CAP1_U2PHY_TYPE_SHIFT (25U) /*! U2PHY_TYPE - USB2 PHY Interface type. This field reflects type of USB2 PHY interface implemented: - UTMI: 0x0, - ULPI: 0x1 */ #define USB3_USB_CAP1_U2PHY_TYPE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U2PHY_TYPE_SHIFT)) & USB3_USB_CAP1_U2PHY_TYPE_MASK) #define USB3_USB_CAP1_U2PHY_WIDTH_MASK (0x4000000U) #define USB3_USB_CAP1_U2PHY_WIDTH_SHIFT (26U) /*! U2PHY_WIDTH - USB2 PHY Interface width. This field reflects width of USB2 PHY interface * implemented: - 8 bit interface: 0x0, - 16 bit interface: 0x1. Note: The ULPI interface is always 8-bit * wide */ #define USB3_USB_CAP1_U2PHY_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U2PHY_WIDTH_SHIFT)) & USB3_USB_CAP1_U2PHY_WIDTH_MASK) #define USB3_USB_CAP1_OTG_READY_MASK (0x8000000U) #define USB3_USB_CAP1_OTG_READY_SHIFT (27U) /*! OTG_READY - This field informs if device is OTG ready: - pure device mode: 0x0, - some features * and ports for CDNS USB OTG controller are implemented: 0x1 */ #define USB3_USB_CAP1_OTG_READY(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_OTG_READY_SHIFT)) & USB3_USB_CAP1_OTG_READY_MASK) #define USB3_USB_CAP1_RESERVED_MASK (0xF0000000U) #define USB3_USB_CAP1_RESERVED_SHIFT (28U) /*! RESERVED - This field is reserved and it is always 0 when reading */ #define USB3_USB_CAP1_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_RESERVED_SHIFT)) & USB3_USB_CAP1_RESERVED_MASK) /*! @} */ /*! @name USB_CAP2 - USB Capability */ /*! @{ */ #define USB3_USB_CAP2_ACTUAL_MEM_SIZE_MASK (0xFFU) #define USB3_USB_CAP2_ACTUAL_MEM_SIZE_SHIFT (0U) /*! ACTUAL_MEM_SIZE - The actual size of the connected On-chip RAM memory in kB: - 0 means 256 kB * (max supported mem size) - value other than 0 reflects the mem size in kB. This value reflects * the CDNS_USBSSDEV_ATTACHED_MEM_SIZE parameter defined in the usbss_dev_defines.v file. This * value has to be adequately set before synthesis by engineer who connects the on-chip memory for * controller */ #define USB3_USB_CAP2_ACTUAL_MEM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP2_ACTUAL_MEM_SIZE_SHIFT)) & USB3_USB_CAP2_ACTUAL_MEM_SIZE_MASK) #define USB3_USB_CAP2_MAX_MEM_SIZE_MASK (0x1F00U) #define USB3_USB_CAP2_MAX_MEM_SIZE_SHIFT (8U) /*! MAX_MEM_SIZE - Max supported mem size. This field reflects width of on-chip RAM address bus * width, which determines max supported mem size: 0x0-0x7 reserved, 0x8 - support for 4kB mem, 0x9 - * support for 8kB mem, 0xA - support for 16kB mem, 0xB - support for 32kB mem, 0xC - support * for 64kB mem, 0xD - support for 128kB mem, 0xE - support for 256kB mem, 0xF - reserved */ #define USB3_USB_CAP2_MAX_MEM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP2_MAX_MEM_SIZE_SHIFT)) & USB3_USB_CAP2_MAX_MEM_SIZE_MASK) #define USB3_USB_CAP2_RESERVED_MASK (0xFFFFE000U) #define USB3_USB_CAP2_RESERVED_SHIFT (13U) /*! RESERVED - RESERVED */ #define USB3_USB_CAP2_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP2_RESERVED_SHIFT)) & USB3_USB_CAP2_RESERVED_MASK) /*! @} */ /*! @name USB_CAP3 - USB Capability */ /*! @{ */ #define USB3_USB_CAP3_EPOUT_N_MASK (0xFFFFU) #define USB3_USB_CAP3_EPOUT_N_SHIFT (0U) /*! EPOUT_N - EPOUT_N */ #define USB3_USB_CAP3_EPOUT_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP3_EPOUT_N_SHIFT)) & USB3_USB_CAP3_EPOUT_N_MASK) #define USB3_USB_CAP3_EPIN_N_MASK (0xFFFF0000U) #define USB3_USB_CAP3_EPIN_N_SHIFT (16U) /*! EPIN_N - EPIN_N */ #define USB3_USB_CAP3_EPIN_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP3_EPIN_N_SHIFT)) & USB3_USB_CAP3_EPIN_N_MASK) /*! @} */ /*! @name USB_CAP4 - ISO HW support */ /*! @{ */ #define USB3_USB_CAP4_EPOUTI_N_MASK (0xFFFFU) #define USB3_USB_CAP4_EPOUTI_N_SHIFT (0U) /*! EPOUTI_N - EPOUTI_N */ #define USB3_USB_CAP4_EPOUTI_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP4_EPOUTI_N_SHIFT)) & USB3_USB_CAP4_EPOUTI_N_MASK) #define USB3_USB_CAP4_EPINI_N_MASK (0xFFFF0000U) #define USB3_USB_CAP4_EPINI_N_SHIFT (16U) /*! EPINI_N - EPINI_N */ #define USB3_USB_CAP4_EPINI_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP4_EPINI_N_SHIFT)) & USB3_USB_CAP4_EPINI_N_MASK) /*! @} */ /*! @name USB_CAP5 - Bulk Stream HW */ /*! @{ */ #define USB3_USB_CAP5_EPOUTI_N_MASK (0xFFFFU) #define USB3_USB_CAP5_EPOUTI_N_SHIFT (0U) /*! EPOUTI_N - EPOUTI_N */ #define USB3_USB_CAP5_EPOUTI_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP5_EPOUTI_N_SHIFT)) & USB3_USB_CAP5_EPOUTI_N_MASK) #define USB3_USB_CAP5_EPINI_N_MASK (0xFFFF0000U) #define USB3_USB_CAP5_EPINI_N_SHIFT (16U) /*! EPINI_N - EPINI_N */ #define USB3_USB_CAP5_EPINI_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP5_EPINI_N_SHIFT)) & USB3_USB_CAP5_EPINI_N_MASK) /*! @} */ /*! @name USB_CAP6 - Device controller version */ /*! @{ */ #define USB3_USB_CAP6_VERSION_MASK (0xFFFFFFFFU) #define USB3_USB_CAP6_VERSION_SHIFT (0U) /*! VERSION - VERSION */ #define USB3_USB_CAP6_VERSION(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP6_VERSION_SHIFT)) & USB3_USB_CAP6_VERSION_MASK) /*! @} */ /*! @name USB_CPKT1 - Custom Packet value */ /*! @{ */ #define USB3_USB_CPKT1_CPKT1_MASK (0xFFFFFFFFU) #define USB3_USB_CPKT1_CPKT1_SHIFT (0U) /*! CPKT1 - CPKT1 */ #define USB3_USB_CPKT1_CPKT1(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CPKT1_CPKT1_SHIFT)) & USB3_USB_CPKT1_CPKT1_MASK) /*! @} */ /*! @name USB_CPKT2 - Custom Packet value */ /*! @{ */ #define USB3_USB_CPKT2_CPKT2_MASK (0xFFFFFFFFU) #define USB3_USB_CPKT2_CPKT2_SHIFT (0U) /*! CPKT2 - CPKT2 */ #define USB3_USB_CPKT2_CPKT2(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CPKT2_CPKT2_SHIFT)) & USB3_USB_CPKT2_CPKT2_MASK) /*! @} */ /*! @name USB_CPKT3 - Custom Packet value */ /*! @{ */ #define USB3_USB_CPKT3_CPKT3_MASK (0xFFFFFFFFU) #define USB3_USB_CPKT3_CPKT3_SHIFT (0U) /*! CPKT3 - CPKT3 */ #define USB3_USB_CPKT3_CPKT3(x) (((uint32_t)(((uint32_t)(x)) << USB3_USB_CPKT3_CPKT3_SHIFT)) & USB3_USB_CPKT3_CPKT3_MASK) /*! @} */ /*! @name CFG_REG1 - VBUS debouncer Configuration */ /*! @{ */ #define USB3_CFG_REG1_DEBOUNCER_CNT_MASK (0x3FFFFU) #define USB3_CFG_REG1_DEBOUNCER_CNT_SHIFT (0U) /*! DEBOUNCER_CNT - This parameter defines the VBUS debouncer delay i.e. the time interval between * the VBUS detection on device input and the start of using it internally. Resolution of this * parameter is 128 ns. For simulation purposes it is recommended to set the value 1 (128ns) For * synthesis purposes it is recommended to set the value 230000 (~30ms) */ #define USB3_CFG_REG1_DEBOUNCER_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG1_DEBOUNCER_CNT_SHIFT)) & USB3_CFG_REG1_DEBOUNCER_CNT_MASK) #define USB3_CFG_REG1_RESERVED_MASK (0xFFFC0000U) #define USB3_CFG_REG1_RESERVED_SHIFT (18U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG1_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG1_RESERVED_SHIFT)) & USB3_CFG_REG1_RESERVED_MASK) /*! @} */ /*! @name DBG_LINK1 - Link */ /*! @{ */ #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_MASK (0xFFU) #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SHIFT (0U) /*! LFPS_MIN_DET_U1_EXIT - LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum time * required for decoding the received LFPS as an LFPS.U1_Exit. Example is shown in the chapter 4. * This field is saved to the device only when the field LFPS_MIN_DET_U1_EXIT_SET is set to '1' * during write to the DBG_LINK1 register. Resolution of this parameter is 8 ns. For simulation * purposes it is recommended to set the value 36 (~300ns). For synthesis purposes it is recommended * to set the value 36 (~300ns) */ #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_MASK) #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK (0xFF00U) #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SHIFT (8U) /*! LFPS_MIN_GEN_U1_EXIT - LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for * phytxelecidle deassertion when LFPS.U1_Exit signalling is generated as shown in the chapter * 4. This field is saved to the device only when the field LFPS_MIN_GEN_U1_EXIT_SET is set to '1' * during write to the DBG_LINK1 register. Resolution of this parameter is 8 ns. For simulation * purposes it is recommended to set the value 87 (~696ns) For synthesis purposes it is * recommended to set the value 87 (~696ns) */ #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK) #define USB3_DBG_LINK1_RXDET_BREAK_DIS_MASK (0x10000U) #define USB3_DBG_LINK1_RXDET_BREAK_DIS_SHIFT (16U) /*! RXDET_BREAK_DIS - RXDET_BREAK_DIS value This parameter configures terminating the Far-end * Receiver termination detection sequence: '0': it is possible that USBSS_DEV will terminate Far-end * receiver termination detection sequence '1': USBSS_DEV will not terminate Far-end receiver * termination detection sequence The impact of the bit to the link behaviour is shown in chapter 4. * This field is saved to the device only when the field RXDET_BREAK_DIS_SET is set to '1' during * write to the DBG_LINK1 */ #define USB3_DBG_LINK1_RXDET_BREAK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RXDET_BREAK_DIS_SHIFT)) & USB3_DBG_LINK1_RXDET_BREAK_DIS_MASK) #define USB3_DBG_LINK1_LFPS_GEN_PING_MASK (0x3E0000U) #define USB3_DBG_LINK1_LFPS_GEN_PING_SHIFT (17U) /*! LFPS_GEN_PING - LFPS_GEN_PING value This parameter configures the LFPS.Ping generation time as * shown in the chapter 4. This field is saved to the device only when the field LFPS_GEN_PING_SET * is set to '1' during write to the DBG_LINK1 register. Resolution of this parameter is 8 ns. * For simulation purposes it is recommended to set the value 24 (~200ns) For synthesis purposes * it is recommended to set the value 24 (~200ns) */ #define USB3_DBG_LINK1_LFPS_GEN_PING(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_GEN_PING_SHIFT)) & USB3_DBG_LINK1_LFPS_GEN_PING_MASK) #define USB3_DBG_LINK1_RESERVED0_MASK (0xC00000U) #define USB3_DBG_LINK1_RESERVED0_SHIFT (22U) /*! RESERVED0 - Reserved field. Write ignored. 0 when read */ #define USB3_DBG_LINK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RESERVED0_SHIFT)) & USB3_DBG_LINK1_RESERVED0_MASK) #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_MASK (0x1000000U) #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_SHIFT (24U) /*! LFPS_MIN_DET_U1_EXIT_SET - Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically cleared. Writing * '0' has no effect */ #define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_MASK) #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_MASK (0x2000000U) #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_SHIFT (25U) /*! LFPS_MIN_GEN_U1_EXIT_SET - Set the LFPS_MIN_GEN_U1_EXIT value Writing '1' to this bit writes the * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically cleared. Writing * '0' has no effect */ #define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_MASK) #define USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_MASK (0x4000000U) #define USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_SHIFT (26U) /*! RXDET_BREAK_DIS_SET - Set the RXDET_BREAK_DIS value Writing '1' to this bit writes the * RXDET_BREAK_DIS field value to the device. This bit is automatically cleared. Writing '0' has no effect */ #define USB3_DBG_LINK1_RXDET_BREAK_DIS_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_SHIFT)) & USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_MASK) #define USB3_DBG_LINK1_LFPS_GEN_PING_SET_MASK (0x8000000U) #define USB3_DBG_LINK1_LFPS_GEN_PING_SET_SHIFT (27U) /*! LFPS_GEN_PING_SET - Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes the * LFPS_GEN_PING field value to the device. This bit is automatically cleared. Writing '0' has no effect */ #define USB3_DBG_LINK1_LFPS_GEN_PING_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_GEN_PING_SET_SHIFT)) & USB3_DBG_LINK1_LFPS_GEN_PING_SET_MASK) #define USB3_DBG_LINK1_RESERVED1_MASK (0xF0000000U) #define USB3_DBG_LINK1_RESERVED1_SHIFT (28U) /*! RESERVED1 - Reserved field. Write ignored. 0 when read */ #define USB3_DBG_LINK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RESERVED1_SHIFT)) & USB3_DBG_LINK1_RESERVED1_MASK) /*! @} */ /*! @name DBG_LINK2 - Link */ /*! @{ */ #define USB3_DBG_LINK2_RXEQTR_AVAL_MASK (0xFFU) #define USB3_DBG_LINK2_RXEQTR_AVAL_SHIFT (0U) /*! RXEQTR_AVAL - Rxeqtraining assertion value This parameter configures phyrxeqtraining asserting * time as shown in the chapter 4. This field is saved to the device only when the field * RXEQTR_AVAL_SET is set to '1' during write to the DBG_LINK2 */ #define USB3_DBG_LINK2_RXEQTR_AVAL(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_AVAL_SHIFT)) & USB3_DBG_LINK2_RXEQTR_AVAL_MASK) #define USB3_DBG_LINK2_RXEQTR_DVAL_MASK (0xFF00U) #define USB3_DBG_LINK2_RXEQTR_DVAL_SHIFT (8U) /*! RXEQTR_DVAL - Rxeqtraining deassertion value This parameter configures phyrxeqtraining * deasserting time as shown in the chapter 4. This field is saved to the device only when the field * RXEQTR_DVAL_SET is set to '1' during write to the DBG_LINK2 */ #define USB3_DBG_LINK2_RXEQTR_DVAL(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_DVAL_SHIFT)) & USB3_DBG_LINK2_RXEQTR_DVAL_MASK) #define USB3_DBG_LINK2_PHYRXVAL_DVAL_MASK (0xFF0000U) #define USB3_DBG_LINK2_PHYRXVAL_DVAL_SHIFT (16U) /*! PHYRXVAL_DVAL - Phyrxvalid latency deassertion value This parameter enables extending internal * phyrxdata and phyrxdatak validity as shown in the chapter 4. This field is saved to the device * only when the field PHYRXVAL_DVAL_SET is set to '1' during write to the DBG_LINK2 */ #define USB3_DBG_LINK2_PHYRXVAL_DVAL(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_PHYRXVAL_DVAL_SHIFT)) & USB3_DBG_LINK2_PHYRXVAL_DVAL_MASK) #define USB3_DBG_LINK2_TXDET_DVAL_MASK (0x7000000U) #define USB3_DBG_LINK2_TXDET_DVAL_SHIFT (24U) /*! TXDET_DVAL - TXDET deassertion value This parameter configures the phytxdetrx_loop deassertion * time after phystatus deassertion during Far-end receiver termination sequence as shown in the * chapter 4. This field is saved to the device only when the field TXDET_DVAL_SET is set to '1' * during write to the DBG_LINK2 */ #define USB3_DBG_LINK2_TXDET_DVAL(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_TXDET_DVAL_SHIFT)) & USB3_DBG_LINK2_TXDET_DVAL_MASK) #define USB3_DBG_LINK2_RESERVED_MASK (0x8000000U) #define USB3_DBG_LINK2_RESERVED_SHIFT (27U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_DBG_LINK2_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RESERVED_SHIFT)) & USB3_DBG_LINK2_RESERVED_MASK) #define USB3_DBG_LINK2_RXEQTR_AVAL_SET_MASK (0x10000000U) #define USB3_DBG_LINK2_RXEQTR_AVAL_SET_SHIFT (28U) /*! RXEQTR_AVAL_SET - Set the rxeqtraining assertion value Writing '1' to this bit writes the * RXEQTR_AVAL field value to the device. This bit is automatically cleared. Writing '0' has no effect */ #define USB3_DBG_LINK2_RXEQTR_AVAL_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_AVAL_SET_SHIFT)) & USB3_DBG_LINK2_RXEQTR_AVAL_SET_MASK) #define USB3_DBG_LINK2_RXEQTR_DVAL_SET_MASK (0x20000000U) #define USB3_DBG_LINK2_RXEQTR_DVAL_SET_SHIFT (29U) /*! RXEQTR_DVAL_SET - Set the rxeqtraining deassertion value Writing '1' to this bit writes the * RXEQTR_DVAL field value to the device. This bit is automatically cleared. Writing '0' has no effect */ #define USB3_DBG_LINK2_RXEQTR_DVAL_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_DVAL_SET_SHIFT)) & USB3_DBG_LINK2_RXEQTR_DVAL_SET_MASK) #define USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_MASK (0x40000000U) #define USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_SHIFT (30U) /*! PHYRXVAL_DVAL_SET - Set the Phyrxvalid latency deassertion value Writing '1' to this bit writes * the PHYRXVAL_DVAL field value to the device. This bit is automatically cleared. Writing '0' * has no effect.0 */ #define USB3_DBG_LINK2_PHYRXVAL_DVAL_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_SHIFT)) & USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_MASK) #define USB3_DBG_LINK2_TXDET_DVAL_SET_MASK (0x80000000U) #define USB3_DBG_LINK2_TXDET_DVAL_SET_SHIFT (31U) /*! TXDET_DVAL_SET - Set the TXDET deassertion value Writing '1' to this bit writes the TXDET_DVAL * field value to the device. This bit is automatically cleared. Writing '0' has no effect */ #define USB3_DBG_LINK2_TXDET_DVAL_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_TXDET_DVAL_SET_SHIFT)) & USB3_DBG_LINK2_TXDET_DVAL_SET_MASK) /*! @} */ /*! @name CFG_REG4 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_MASK (0xFFU) #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_SHIFT (0U) /*! RXDETECT_QUIET_TIMEOUT - RXDETECT_QUIET_TIMEOUT value Resolution of this parameter is selected * by RXDETECT_QUIET_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: * - 11*100us =~1ms (SystemC device ENV) - 13*1us =~12us (VIP based ENV) For synthesis purposes * it is recommended to set the value 121*100us =~12ms */ #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_SHIFT)) & USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_MASK) #define USB3_CFG_REG4_RESERVED_MASK (0x3FFFFF00U) #define USB3_CFG_REG4_RESERVED_SHIFT (8U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG4_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG4_RESERVED_SHIFT)) & USB3_CFG_REG4_RESERVED_MASK) #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_SHIFT (30U) /*! RXDETECT_QUIET_TIMEOUT_PRESCALE - PRESCALER for RXDETECT_QUIET_TIMEOUT : - 0x0 : 8ns (PHY pclk * clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG5 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_MASK (0x7FFU) #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_SHIFT (0U) /*! U3_HDSK_FAIL_TIMEOUT - U3_HDSK_FAIL_TIMEOUT value Resolution of this parameter is selected by * U3_HDSK_FAIL_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - * 11*100us =~1ms (SystemC device ENV) - 11*100us =~1ms (VIP based ENV) For synthesis purposes it is * recommended to set the value 1001*100us =~100ms */ #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_SHIFT)) & USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_MASK) #define USB3_CFG_REG5_RESERVED_MASK (0x3FFFF800U) #define USB3_CFG_REG5_RESERVED_SHIFT (11U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG5_RESERVED_SHIFT)) & USB3_CFG_REG5_RESERVED_MASK) #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_SHIFT (30U) /*! U3_HDSK_FAIL_TIMEOUT_PRESCALE - PRESCALER for U3_HDSK_FAIL_TIMEOUT : - 0x0 : 8ns (PHY pclk * clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG6 - Configuration Register 6 */ /*! @{ */ #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_MASK (0xFFU) #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_SHIFT (0U) /*! SSINACTIVE_QUIET_TIMEOUT - SSINACTIVE_QUIET_TIMEOUT value Resolution of this parameter is * selected by SSINACTIVE_QUIET_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the * value: - 11*100us =~1ms (SystemC device ENV) - 13*1us =~12us (VIP based ENV) For synthesis * purposes it is recommended to set the value: - 121*100us =~12ms */ #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_SHIFT)) & USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_MASK) #define USB3_CFG_REG6_RESERVED_MASK (0x3FFFFF00U) #define USB3_CFG_REG6_RESERVED_SHIFT (8U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG6_RESERVED_SHIFT)) & USB3_CFG_REG6_RESERVED_MASK) #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_SHIFT (30U) /*! SSINACTIVE_QUIET_TIMEOUT_PRESCALE - PRESCALER for SSINACTIVE_QUIET_TIMEOUT value: - 0x0 : 8ns * (PHY pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG7 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_MASK (0x1FFFU) #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_SHIFT (0U) /*! POLLING_LFPS_TIMEOUT - POLLING_LFPS_TIMEOUT value Resolution of this parameter is selected by * POLLING_LFPS_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - * 11*100us =~1ms (SystemC device ENV) - 481*1us =~480us (VIP based ENV) For synthesis purposes it * is recommended to set the value: - 3601*100us =~360ms */ #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_SHIFT)) & USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_MASK) #define USB3_CFG_REG7_RESERVED_MASK (0x3FFFE000U) #define USB3_CFG_REG7_RESERVED_SHIFT (13U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG7_RESERVED_SHIFT)) & USB3_CFG_REG7_RESERVED_MASK) #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_SHIFT (30U) /*! POLLING_LFPS_TIMEOUT_PRESCALE - PRESCALER for POLLING_LFPS_TIMEOUT value: - 0x0 : 8ns (PHY pclk * clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG8 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_MASK (0x3FFU) #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_SHIFT (0U) /*! POLLING_ACTIVE_TIMEOUT - POLLING_ACTIVE_TIMEOUT value Resolution of this parameter is selected * by POLLING_ACTIVE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: * - 11*100us =~1ms (SystemC device ENV) - 31*1us =~30us (VIP based ENV) For synthesis purposes * it is recommended to set the value: - 121*100us =~12ms */ #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_SHIFT)) & USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_MASK) #define USB3_CFG_REG8_RESERVED_MASK (0x3FFFFC00U) #define USB3_CFG_REG8_RESERVED_SHIFT (10U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG8_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG8_RESERVED_SHIFT)) & USB3_CFG_REG8_RESERVED_MASK) #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_SHIFT (30U) /*! POLLING_ACTIVE_TIMEOUT_PRESCALE - PRESCALER for POLLING_ACTIVE_TIMEOUT value: - 0x0 : 8ns (PHY * pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG9 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_MASK (0x1FU) #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_SHIFT (0U) /*! POLLING_IDLE_TIMEOUT - POLLING_IDLE_TIMEOUT value Resolution of this parameter is selected by * POLLING_IDLE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - * 21*100us =~2ms (SystemC device ENV) - 3*1us =~2us (VIP based ENV) For synthesis purposes it is * recommended to set the value: - 21*100us =~2ms */ #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_SHIFT)) & USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_MASK) #define USB3_CFG_REG9_RESERVED_MASK (0x3FFFFFE0U) #define USB3_CFG_REG9_RESERVED_SHIFT (5U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG9_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG9_RESERVED_SHIFT)) & USB3_CFG_REG9_RESERVED_MASK) #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_SHIFT (30U) /*! POLLING_IDLE_TIMEOUT_PRESCALE - PRESCALER for POLLING_IDLE_TIMEOUT value: - 0x0 : 8ns (PHY pclk * clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG10 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_MASK (0xFFU) #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_SHIFT (0U) /*! POLLING_CONF_TIMEOUT - POLLING_CONF_TIMEOUT value Resolution of this parameter is selected by * POLLING_CONF_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - * 11*100us =~1ms (SystemC device ENV) - 31*1us =~30us (VIP based ENV) For synthesis purposes it is * recommended to set the value: - 121*100us =~12ms */ #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG10_POLLING_CONF_TIMEOUT_SHIFT)) & USB3_CFG_REG10_POLLING_CONF_TIMEOUT_MASK) #define USB3_CFG_REG10_RESERVED_MASK (0x3FFFFF00U) #define USB3_CFG_REG10_RESERVED_SHIFT (8U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG10_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG10_RESERVED_SHIFT)) & USB3_CFG_REG10_RESERVED_MASK) #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_SHIFT (30U) /*! POLLING_CONF_TIMEOUT_PRESCALE - PRESCALER for POLLING_CONF_TIMEOUT value: - 0x0 : 8ns (PHY pclk * clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG11 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_MASK (0xFFU) #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_SHIFT (0U) /*! RECOVERY_ACTIVE_TIMEOUT - RECOVERY_ACTIVE_TIMEOUT value Resolution of this parameter is selected * by RECOVERY_ACTIVE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the * value: - 11*100us =~1ms (SystemC device ENV) - 101*1us =~100us (VIP based ENV) For synthesis * purposes it is recommended to set the value: - 121*100us =~12ms */ #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_SHIFT)) & USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_MASK) #define USB3_CFG_REG11_RESERVED_MASK (0x3FFFFF00U) #define USB3_CFG_REG11_RESERVED_SHIFT (8U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG11_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG11_RESERVED_SHIFT)) & USB3_CFG_REG11_RESERVED_MASK) #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_SHIFT (30U) /*! RECOVERY_ACTIVE_TIMEOUT_PRESCALE - PRESCALER for RECOVERY_ACTIVE_TIMEOUT value: - 0x0 : 8ns (PHY * pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG12 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_MASK (0xFFU) #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_SHIFT (0U) /*! RECOVERY_CONF_TIMEOUT - RECOVERY_CONF_TIMEOUT value Resolution of this parameter is selected by * RECOVERY_CONF_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - * 11*100us =~1ms (SystemC device ENV) - 101*1us =~100us (VIP based ENV) For synthesis purposes * it is recommended to set the value: - 61*100us =~6ms */ #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_SHIFT)) & USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_MASK) #define USB3_CFG_REG12_RESERVED_MASK (0x3FFFFF00U) #define USB3_CFG_REG12_RESERVED_SHIFT (8U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG12_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG12_RESERVED_SHIFT)) & USB3_CFG_REG12_RESERVED_MASK) #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_SHIFT (30U) /*! RECOVERY_CONF_TIMEOUT_PRESCALE - PRESCALER for RECOVERY_CONF_TIMEOUT value: - 0x0 : 8ns (PHY * pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG13 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_MASK (0x1FU) #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_SHIFT (0U) /*! RECOVERY_IDLE_TIMEOUT - RECOVERY_IDLE_TIMEOUT value Resolution of this parameter is selected by * RECOVERY_IDLE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - * 21*100us =~2ms (SystemC device ENV) - 3*1us =~3us (VIP based ENV) For synthesis purposes it is * recommended to set the value: - 21*100us =~2ms */ #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_SHIFT)) & USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_MASK) #define USB3_CFG_REG13_RESERVED_MASK (0xFFFFFE0U) #define USB3_CFG_REG13_RESERVED_SHIFT (5U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG13_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG13_RESERVED_SHIFT)) & USB3_CFG_REG13_RESERVED_MASK) #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_SHIFT (30U) /*! RECOVERY_IDLE_TIMEOUT_PRESCALE - PRESCALER for RECOVERY_IDLE_TIMEOUT value: - 0x0 : 8ns (PHY * pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG14 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_MASK (0xFFU) #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_SHIFT (0U) /*! HOTRESET_ACTIVE_TIMEOUT - HOTRESET_ACTIVE_TIMEOUT value Resolution of this parameter is selected * by HOTRESET_ACTIVE_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the * value: - 21*100us =~2ms (SystemC device ENV) - 13*1us =~13us (VIP based ENV) For synthesis * purposes it is recommended to set the value: - 121*100us =~12ms */ #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_SHIFT)) & USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_MASK) #define USB3_CFG_REG14_RESERVED_MASK (0x3FFFFF00U) #define USB3_CFG_REG14_RESERVED_SHIFT (8U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG14_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG14_RESERVED_SHIFT)) & USB3_CFG_REG14_RESERVED_MASK) #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_SHIFT (30U) /*! HOTRESET_ACTIVE_TIMEOUT_PRESCALE - PRESCALER for HOTRESET_ACTIVE_TIMEOUT value: - 0x0 : 8ns (PHY * pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG15 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_MASK (0x1FU) #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_SHIFT (0U) /*! HOTRESET_EXIT_TIMEOUT - HOTRESET_EXIT_TIMEOUT value Resolution of this parameter is selected by * HOTRESET_EXIT_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - * 21*100us =~2ms (SystemC device ENV) - 3*1us =~3us (VIP based ENV) For synthesis purposes it is * recommended to set the value: - 21*100us =~2ms */ #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_SHIFT)) & USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_MASK) #define USB3_CFG_REG15_RESERVED_MASK (0x3FFFFFE0U) #define USB3_CFG_REG15_RESERVED_SHIFT (5U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG15_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG15_RESERVED_SHIFT)) & USB3_CFG_REG15_RESERVED_MASK) #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_SHIFT (30U) /*! HOTRESET_EXIT_TIMEOUT_PRESCALE - PRESCALER for HOTRESET_EXIT_TIMEOUT value: - 0x0 : 8ns (PHY * pclk clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG16 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG16_LFPS_PING_REPEAT_MASK (0xFFFU) #define USB3_CFG_REG16_LFPS_PING_REPEAT_SHIFT (0U) /*! LFPS_PING_REPEAT - LFPS_PING_REPEAT value Resolution of this parameter is selected by * LFPS_PING_REPEAT_PRESCALE. For simulation purposes it is recommended to set the value: - 6*100us =~0.5ms * (SystemC device ENV) - 4*100us =~400us (VIP based ENV) For synthesis purposes it is * recommended to set the value: - 2001*100us =~200ms */ #define USB3_CFG_REG16_LFPS_PING_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG16_LFPS_PING_REPEAT_SHIFT)) & USB3_CFG_REG16_LFPS_PING_REPEAT_MASK) #define USB3_CFG_REG16_RESERVED_MASK (0x3FFFF000U) #define USB3_CFG_REG16_RESERVED_SHIFT (12U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG16_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG16_RESERVED_SHIFT)) & USB3_CFG_REG16_RESERVED_MASK) #define USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_SHIFT (30U) /*! LFPS_PING_REPEAT_PRESCALE - PRESCALER for LFPS_PING_REPEAT value: - 0x0 : 8ns (PHY pclk clock) - * 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_SHIFT)) & USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG17 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG17_PENDING_HP_TIMEOUT_MASK (0x3FFU) #define USB3_CFG_REG17_PENDING_HP_TIMEOUT_SHIFT (0U) /*! PENDING_HP_TIMEOUT - PENDING_HP_TIMEOUT value Resolution of this parameter is selected by * PENDING_HP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 437*8ns * =~3.5us (SystemC device ENV) - 437*8ns =~3.5us (VIP based ENV) For synthesis purposes it is * recommended to set the value: - 437*8ns =~3.5us */ #define USB3_CFG_REG17_PENDING_HP_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG17_PENDING_HP_TIMEOUT_SHIFT)) & USB3_CFG_REG17_PENDING_HP_TIMEOUT_MASK) #define USB3_CFG_REG17_RESERVED_MASK (0x3FFFFC00U) #define USB3_CFG_REG17_RESERVED_SHIFT (10U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG17_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG17_RESERVED_SHIFT)) & USB3_CFG_REG17_RESERVED_MASK) #define USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_SHIFT (30U) /*! PENDING_HP_TIMEOUT_PRESCALE - PRESCALER for PENDING_HP_TIMEOUT value: - 0x0 : 8ns (PHY pclk * clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG18 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_MASK (0x7FU) #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_SHIFT (0U) /*! CREDIT_HP_TIMEOUT - CREDIT_HP_TIMEOUT value Resolution of this parameter is selected by * CREDIT_HP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us * =~1ms (SystemC device ENV) - 11*100us =~1ms (VIP based ENV) For synthesis purposes it is * recommended to set the value: - 52*100us =~5.1ms */ #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG18_CREDIT_HP_TIMEOUT_SHIFT)) & USB3_CFG_REG18_CREDIT_HP_TIMEOUT_MASK) #define USB3_CFG_REG18_RESERVED_MASK (0x3FFFFF80U) #define USB3_CFG_REG18_RESERVED_SHIFT (7U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG18_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG18_RESERVED_SHIFT)) & USB3_CFG_REG18_RESERVED_MASK) #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_SHIFT (30U) /*! CREDIT_HP_TIMEOUT_PRESCALE - PRESCALER for CREDIT_HP_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) * - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG19 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG19_LUP_TIMEOUT_MASK (0x3FFU) #define USB3_CFG_REG19_LUP_TIMEOUT_SHIFT (0U) /*! LUP_TIMEOUT - LUP_TIMEOUT value Resolution of this parameter is selected by * LUP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*1us =~11us (SystemC device * ENV) - 11*1us =~11us (VIP based ENV) For synthesis purposes it is recommended to set the * value: - 11*1us =~11us */ #define USB3_CFG_REG19_LUP_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG19_LUP_TIMEOUT_SHIFT)) & USB3_CFG_REG19_LUP_TIMEOUT_MASK) #define USB3_CFG_REG19_RESERVED_MASK (0x3FFFFC00U) #define USB3_CFG_REG19_RESERVED_SHIFT (10U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG19_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG19_RESERVED_SHIFT)) & USB3_CFG_REG19_RESERVED_MASK) #define USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_SHIFT (30U) /*! LUP_TIMEOUT_PRESCALE - PRESCALER for LUP_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) - 0x1 : 1us * - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG20 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG20_LDN_TIMEOUT_MASK (0xFFU) #define USB3_CFG_REG20_LDN_TIMEOUT_SHIFT (0U) /*! LDN_TIMEOUT - LDN_TIMEOUT value Resolution of this parameter is selected by * LDN_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 11*100us =~1ms (SystemC device * ENV) - 129*1us =~129us (VIP based ENV) For synthesis purposes it is recommended to set the * value: - 11*100us =~1ms */ #define USB3_CFG_REG20_LDN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG20_LDN_TIMEOUT_SHIFT)) & USB3_CFG_REG20_LDN_TIMEOUT_MASK) #define USB3_CFG_REG20_RESERVED_MASK (0x3FFFFF00U) #define USB3_CFG_REG20_RESERVED_SHIFT (8U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG20_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG20_RESERVED_SHIFT)) & USB3_CFG_REG20_RESERVED_MASK) #define USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_SHIFT (30U) /*! LDN_TIMEOUT_PRESCALE - PRESCALER for LDN_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) - 0x1 : 1us * - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG21 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG21_PM_LC_TIMEOUT_MASK (0x3FFU) #define USB3_CFG_REG21_PM_LC_TIMEOUT_SHIFT (0U) /*! PM_LC_TIMEOUT - PM_LC_TIMEOUT value Resolution of this parameter is selected by * PM_LC_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 400*8ns =~3.2us (SystemC * device ENV) - 400*8ns =~3.2us (VIP based ENV) For synthesis purposes it is recommended to set * the value: - 400*8ns =~3.2us */ #define USB3_CFG_REG21_PM_LC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG21_PM_LC_TIMEOUT_SHIFT)) & USB3_CFG_REG21_PM_LC_TIMEOUT_MASK) #define USB3_CFG_REG21_RESERVED_MASK (0x3FFFFC00U) #define USB3_CFG_REG21_RESERVED_SHIFT (10U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG21_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG21_RESERVED_SHIFT)) & USB3_CFG_REG21_RESERVED_MASK) #define USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_SHIFT (30U) /*! PM_LC_TIMEOUT_PRESCALE - PRESCALER for PM_LC_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) - 0x1 : * 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG22 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_MASK (0x7FFU) #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_SHIFT (0U) /*! PM_ENTRY_TIMEOUT - PM_ENTRY_TIMEOUT value Resolution of this parameter is selected by * PM_ENTRY_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 800*8ns =~6.4us * (SystemC device ENV) - 800*8ns =~6.4us (VIP based ENV) For synthesis purposes it is * recommended to set the value: - 800*8ns =~6.4us */ #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG22_PM_ENTRY_TIMEOUT_SHIFT)) & USB3_CFG_REG22_PM_ENTRY_TIMEOUT_MASK) #define USB3_CFG_REG22_RESERVED_MASK (0x3FFFF800U) #define USB3_CFG_REG22_RESERVED_SHIFT (11U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG22_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG22_RESERVED_SHIFT)) & USB3_CFG_REG22_RESERVED_MASK) #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_SHIFT (30U) /*! PM_ENTRY_TIMEOUT_PRESCALE - PRESCALER for PM_ENTRY_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) - * 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG23 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG23_UX_EXIT_TIMEOUT_MASK (0x7FU) #define USB3_CFG_REG23_UX_EXIT_TIMEOUT_SHIFT (0U) /*! UX_EXIT_TIMEOUT - UX_EXIT_TIMEOUT value Resolution of this parameter is selected by * UX_EXIT_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 8*100us =~800us * (SystemC device ENV) - 3*100us =~300us (VIP based ENV) For synthesis purposes it is recommended * to set the value: - 62*100us =~6.2ms */ #define USB3_CFG_REG23_UX_EXIT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG23_UX_EXIT_TIMEOUT_SHIFT)) & USB3_CFG_REG23_UX_EXIT_TIMEOUT_MASK) #define USB3_CFG_REG23_RESERVED_MASK (0x3FFFFF80U) #define USB3_CFG_REG23_RESERVED_SHIFT (7U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG23_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG23_RESERVED_SHIFT)) & USB3_CFG_REG23_RESERVED_MASK) #define USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_SHIFT (30U) /*! UX_EXIT_TIMEOUT_PRESCALE - PRESCALER for UX_EXIT_TIMEOUT value: - 0x0 : 8ns (PHY pclk clock) - * 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG24 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG24_LFPS_DET_RESET_MIN_MASK (0x7FFFFFU) #define USB3_CFG_REG24_LFPS_DET_RESET_MIN_SHIFT (0U) /*! LFPS_DET_RESET_MIN - LFPS_DET_RESET_MIN value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 395833 (~3.16ms) For synthesis purposes it is * recommended to set the value 2375000 (~19ms) */ #define USB3_CFG_REG24_LFPS_DET_RESET_MIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG24_LFPS_DET_RESET_MIN_SHIFT)) & USB3_CFG_REG24_LFPS_DET_RESET_MIN_MASK) #define USB3_CFG_REG24_RESERVED_MASK (0xFF800000U) #define USB3_CFG_REG24_RESERVED_SHIFT (23U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG24_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG24_RESERVED_SHIFT)) & USB3_CFG_REG24_RESERVED_MASK) /*! @} */ /*! @name CFG_REG25 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG25_LFPS_DET_RESET_MAX_MASK (0xFFFFFFU) #define USB3_CFG_REG25_LFPS_DET_RESET_MAX_SHIFT (0U) /*! LFPS_DET_RESET_MAX - LFPS_DET_RESET_MAX value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 5000000 (~40ms) For synthesis purposes it is * recommended to set the value 15000000 (~120ms) */ #define USB3_CFG_REG25_LFPS_DET_RESET_MAX(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG25_LFPS_DET_RESET_MAX_SHIFT)) & USB3_CFG_REG25_LFPS_DET_RESET_MAX_MASK) #define USB3_CFG_REG25_RESERVED_MASK (0xFF000000U) #define USB3_CFG_REG25_RESERVED_SHIFT (24U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG25_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG25_RESERVED_SHIFT)) & USB3_CFG_REG25_RESERVED_MASK) /*! @} */ /*! @name CFG_REG26 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG26_LFPS_DET_POLLING_MIN_MASK (0x7FU) #define USB3_CFG_REG26_LFPS_DET_POLLING_MIN_SHIFT (0U) /*! LFPS_DET_POLLING_MIN - LFPS_DET_POLLING_MIN value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 75 (~0.6us) For synthesis purposes it is * recommended to set the value 75 (~0.6us) */ #define USB3_CFG_REG26_LFPS_DET_POLLING_MIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG26_LFPS_DET_POLLING_MIN_SHIFT)) & USB3_CFG_REG26_LFPS_DET_POLLING_MIN_MASK) #define USB3_CFG_REG26_RESERVED_MASK (0xFFFFFF80U) #define USB3_CFG_REG26_RESERVED_SHIFT (7U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG26_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG26_RESERVED_SHIFT)) & USB3_CFG_REG26_RESERVED_MASK) /*! @} */ /*! @name CFG_REG27 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG27_LFPS_DET_POLLING_MAX_MASK (0xFFU) #define USB3_CFG_REG27_LFPS_DET_POLLING_MAX_SHIFT (0U) /*! LFPS_DET_POLLING_MAX - LFPS_DET_POLLING_MAX value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 175 (~1.4us) For synthesis purposes it is * recommended to set the value 175 (~1.4us) */ #define USB3_CFG_REG27_LFPS_DET_POLLING_MAX(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG27_LFPS_DET_POLLING_MAX_SHIFT)) & USB3_CFG_REG27_LFPS_DET_POLLING_MAX_MASK) #define USB3_CFG_REG27_RESERVED_MASK (0xFFFFFF00U) #define USB3_CFG_REG27_RESERVED_SHIFT (8U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG27_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG27_RESERVED_SHIFT)) & USB3_CFG_REG27_RESERVED_MASK) /*! @} */ /*! @name CFG_REG28 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG28_LFPS_DET_PING_MIN_MASK (0x7U) #define USB3_CFG_REG28_LFPS_DET_PING_MIN_SHIFT (0U) /*! LFPS_DET_PING_MIN - LFPS_DET_PING_MIN value Resolution of this parameter is 8 ns. For simulation * purposes it is recommended to set the value 4 (~40ns) For synthesis purposes it is * recommended to set the value 4 (~40ns) */ #define USB3_CFG_REG28_LFPS_DET_PING_MIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG28_LFPS_DET_PING_MIN_SHIFT)) & USB3_CFG_REG28_LFPS_DET_PING_MIN_MASK) #define USB3_CFG_REG28_RESERVED_MASK (0xFFFFFFF8U) #define USB3_CFG_REG28_RESERVED_SHIFT (3U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG28_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG28_RESERVED_SHIFT)) & USB3_CFG_REG28_RESERVED_MASK) /*! @} */ /*! @name CFG_REG29 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG29_LFPS_DET_PING_MAX_MASK (0x1FU) #define USB3_CFG_REG29_LFPS_DET_PING_MAX_SHIFT (0U) /*! LFPS_DET_PING_MAX - LFPS_DET_PING_MAX value Resolution of this parameter is 8 ns. For simulation * purposes it is recommended to set the value 23 (~200ns) For synthesis purposes it is * recommended to set the value 23 (~200ns) */ #define USB3_CFG_REG29_LFPS_DET_PING_MAX(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG29_LFPS_DET_PING_MAX_SHIFT)) & USB3_CFG_REG29_LFPS_DET_PING_MAX_MASK) #define USB3_CFG_REG29_RESERVED_MASK (0xFFFFFFE0U) #define USB3_CFG_REG29_RESERVED_SHIFT (5U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG29_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG29_RESERVED_SHIFT)) & USB3_CFG_REG29_RESERVED_MASK) /*! @} */ /*! @name CFG_REG30 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_MASK (0x3FU) #define USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_SHIFT (0U) /*! LFPS_DET_U1EXIT_MIN - LFPS_DET_U1EXIT_MIN value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 36 (~300ns) For synthesis purposes it is * recommended to set the value 36 (~300ns) */ #define USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_SHIFT)) & USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_MASK) #define USB3_CFG_REG30_RESERVED_MASK (0xFFFFFFC0U) #define USB3_CFG_REG30_RESERVED_SHIFT (6U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG30_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG30_RESERVED_SHIFT)) & USB3_CFG_REG30_RESERVED_MASK) /*! @} */ /*! @name CFG_REG31 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_MASK (0x7FU) #define USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_SHIFT (0U) /*! LFPS_DET_U1EXIT_MAX - LFPS_DET_U1EXIT_MAX value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 111 (~900ns) For synthesis purposes it is * recommended to set the value 111 (~900ns) */ #define USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_SHIFT)) & USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_MASK) #define USB3_CFG_REG31_RESERVED_MASK (0xFFFFFF80U) #define USB3_CFG_REG31_RESERVED_SHIFT (7U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG31_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG31_RESERVED_SHIFT)) & USB3_CFG_REG31_RESERVED_MASK) /*! @} */ /*! @name CFG_REG32 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_MASK (0x3FU) #define USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_SHIFT (0U) /*! LFPS_DET_U2EXIT_MIN - LFPS_DET_U2EXIT_MIN value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 36 (~300ns) For synthesis purposes it is * recommended to set the value 36 (~300ns) */ #define USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_SHIFT)) & USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_MASK) #define USB3_CFG_REG32_RESERVED_MASK (0xFFFFFFC0U) #define USB3_CFG_REG32_RESERVED_SHIFT (6U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG32_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG32_RESERVED_SHIFT)) & USB3_CFG_REG32_RESERVED_MASK) /*! @} */ /*! @name CFG_REG33 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_MASK (0x3FFFFU) #define USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_SHIFT (0U) /*! LFPS_DET_U2EXIT_MAX - LFPS_DET_U2EXIT_MAX value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 250000 (~2ms) For synthesis purposes it is * recommended to set the value 250000 (~2ms) */ #define USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_SHIFT)) & USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_MASK) #define USB3_CFG_REG33_RESERVED_MASK (0xFFFC0000U) #define USB3_CFG_REG33_RESERVED_SHIFT (18U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG33_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG33_RESERVED_SHIFT)) & USB3_CFG_REG33_RESERVED_MASK) /*! @} */ /*! @name CFG_REG34 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_MASK (0x3FU) #define USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_SHIFT (0U) /*! LFPS_DET_U3EXIT_MIN - LFPS_DET_U3EXIT_MIN value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 36 (~300ns) For synthesis purposes it is * recommended to set the value 36 (~300ns) */ #define USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_SHIFT)) & USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_MASK) #define USB3_CFG_REG34_RESERVED_MASK (0xFFFFFFC0U) #define USB3_CFG_REG34_RESERVED_SHIFT (6U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG34_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG34_RESERVED_SHIFT)) & USB3_CFG_REG34_RESERVED_MASK) /*! @} */ /*! @name CFG_REG35 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_MASK (0x1FFFFFU) #define USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_SHIFT (0U) /*! LFPS_DET_U3EXIT_MAX - LFPS_DET_U3EXIT_MAX value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 1250000 (~10ms) For synthesis purposes it is * recommended to set the value 1250000 (~10ms) */ #define USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_SHIFT)) & USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_MASK) #define USB3_CFG_REG35_RESERVED_MASK (0xFFE00000U) #define USB3_CFG_REG35_RESERVED_SHIFT (21U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG35_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG35_RESERVED_SHIFT)) & USB3_CFG_REG35_RESERVED_MASK) /*! @} */ /*! @name CFG_REG36 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG36_LFPS_GEN_PING_MASK (0x1FU) #define USB3_CFG_REG36_LFPS_GEN_PING_SHIFT (0U) /*! LFPS_GEN_PING - LFPS_GEN_PING value Resolution of this parameter is 8 ns. For simulation * purposes it is recommended to set the value 24 (~200ns) For synthesis purposes it is recommended to * set the value 24 (~200ns) */ #define USB3_CFG_REG36_LFPS_GEN_PING(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG36_LFPS_GEN_PING_SHIFT)) & USB3_CFG_REG36_LFPS_GEN_PING_MASK) #define USB3_CFG_REG36_RESERVED_MASK (0xFFFFFFE0U) #define USB3_CFG_REG36_RESERVED_SHIFT (5U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG36_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG36_RESERVED_SHIFT)) & USB3_CFG_REG36_RESERVED_MASK) /*! @} */ /*! @name CFG_REG37 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG37_LFPS_GEN_POLLING_MASK (0xFFU) #define USB3_CFG_REG37_LFPS_GEN_POLLING_SHIFT (0U) /*! LFPS_GEN_POLLING - LFPS_GEN_POLLING value Resolution of this parameter is 8 ns. For simulation * purposes it is recommended to set the value 125 (~1us) For synthesis purposes it is recommended * to set the value 125 (~1us) */ #define USB3_CFG_REG37_LFPS_GEN_POLLING(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG37_LFPS_GEN_POLLING_SHIFT)) & USB3_CFG_REG37_LFPS_GEN_POLLING_MASK) #define USB3_CFG_REG37_RESERVED_MASK (0xFFFFFF00U) #define USB3_CFG_REG37_RESERVED_SHIFT (8U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG37_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG37_RESERVED_SHIFT)) & USB3_CFG_REG37_RESERVED_MASK) /*! @} */ /*! @name CFG_REG38 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG38_LFPS_GEN_U1EXIT_MASK (0x3FFFFU) #define USB3_CFG_REG38_LFPS_GEN_U1EXIT_SHIFT (0U) /*! LFPS_GEN_U1EXIT - LFPS_GEN_U1EXIT value Resolution of this parameter is 8 ns. For simulation * purposes it is recommended to set the value 62500 (~500us) For synthesis purposes it is * recommended to set the value 250000 (~2ms) */ #define USB3_CFG_REG38_LFPS_GEN_U1EXIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG38_LFPS_GEN_U1EXIT_SHIFT)) & USB3_CFG_REG38_LFPS_GEN_U1EXIT_MASK) #define USB3_CFG_REG38_RESERVED_MASK (0xFFFC0000U) #define USB3_CFG_REG38_RESERVED_SHIFT (18U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG38_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG38_RESERVED_SHIFT)) & USB3_CFG_REG38_RESERVED_MASK) /*! @} */ /*! @name CFG_REG39 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG39_LFPS_GEN_U3EXIT_MASK (0x1FFFFFU) #define USB3_CFG_REG39_LFPS_GEN_U3EXIT_SHIFT (0U) /*! LFPS_GEN_U3EXIT - LFPS_GEN_U3EXIT value Resolution of this parameter is 8 ns. For simulation * purposes it is recommended to set the value 125000 (~1ms) For synthesis purposes it is * recommended to set the value 1250000 (~10ms) */ #define USB3_CFG_REG39_LFPS_GEN_U3EXIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG39_LFPS_GEN_U3EXIT_SHIFT)) & USB3_CFG_REG39_LFPS_GEN_U3EXIT_MASK) #define USB3_CFG_REG39_RESERVED_MASK (0xFFE00000U) #define USB3_CFG_REG39_RESERVED_SHIFT (21U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG39_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG39_RESERVED_SHIFT)) & USB3_CFG_REG39_RESERVED_MASK) /*! @} */ /*! @name CFG_REG40 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_MASK (0x7FU) #define USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_SHIFT (0U) /*! LFPS_MIN_GEN_U1EXIT - LFPS_MIN_GEN_U1EXIT value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 87 (~696ns) For synthesis purposes it is * recommended to set the value 87 (~696ns) */ #define USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_SHIFT)) & USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_MASK) #define USB3_CFG_REG40_RESERVED_MASK (0xFFFFFF80U) #define USB3_CFG_REG40_RESERVED_SHIFT (7U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG40_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG40_RESERVED_SHIFT)) & USB3_CFG_REG40_RESERVED_MASK) /*! @} */ /*! @name CFG_REG41 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_MASK (0x7FFFU) #define USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_SHIFT (0U) /*! LFPS_MIN_GEN_U2EXIT - LFPS_MIN_GEN_U2EXIT value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 12500 (~100us) For synthesis purposes it is * recommended to set the value 12500 (~100us) */ #define USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_SHIFT)) & USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_MASK) #define USB3_CFG_REG41_RESERVED_MASK (0xFFFF8000U) #define USB3_CFG_REG41_RESERVED_SHIFT (15U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG41_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG41_RESERVED_SHIFT)) & USB3_CFG_REG41_RESERVED_MASK) /*! @} */ /*! @name CFG_REG42 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG42_LFPS_POLLING_REPEAT_MASK (0x7FFU) #define USB3_CFG_REG42_LFPS_POLLING_REPEAT_SHIFT (0U) /*! LFPS_POLLING_REPEAT - LFPS_POLLING_REPEAT value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 1250 (~10us) For synthesis purposes it is * recommended to set the value 1250 (~10us) */ #define USB3_CFG_REG42_LFPS_POLLING_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG42_LFPS_POLLING_REPEAT_SHIFT)) & USB3_CFG_REG42_LFPS_POLLING_REPEAT_MASK) #define USB3_CFG_REG42_RESERVED_MASK (0xFFFFF800U) #define USB3_CFG_REG42_RESERVED_SHIFT (11U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG42_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG42_RESERVED_SHIFT)) & USB3_CFG_REG42_RESERVED_MASK) /*! @} */ /*! @name CFG_REG43 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_MASK (0x7FFU) #define USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_SHIFT (0U) /*! LFPS_POLLING_MAX_TREPEAT - LFPS_POLLING_MAX_TREPEAT value Resolution of this parameter is 8 ns. * For simulation purposes it is recommended to set the value 1750 (~14us) For synthesis purposes * it is recommended to set the value 1750 (~14us) */ #define USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_SHIFT)) & USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_MASK) #define USB3_CFG_REG43_RESERVED_MASK (0xFFFFF800U) #define USB3_CFG_REG43_RESERVED_SHIFT (11U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG43_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG43_RESERVED_SHIFT)) & USB3_CFG_REG43_RESERVED_MASK) /*! @} */ /*! @name CFG_REG44 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_MASK (0x7FFU) #define USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_SHIFT (0U) /*! LFPS_POLLING_MIN_TREPEAT - LFPS_POLLING_MIN_TREPEAT value Resolution of this parameter is 8 ns. * For simulation purposes it is recommended to set the value 748 (~6us) For synthesis purposes * it is recommended to set the value 748 (~6us) */ #define USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_SHIFT)) & USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_MASK) #define USB3_CFG_REG44_RESERVED_MASK (0xFFFFF800U) #define USB3_CFG_REG44_RESERVED_SHIFT (11U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG44_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG44_RESERVED_SHIFT)) & USB3_CFG_REG44_RESERVED_MASK) /*! @} */ /*! @name CFG_REG45 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_MASK (0x7FU) #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_SHIFT (0U) /*! ITP_WAKEUP_TIMEOUT - ITP_WAKEUP_TIMEOUT value Resolution of this parameter is selected by * ITP_WAKEUP_TIMEOUT_PRESCALE. For simulation purposes it is recommended to set the value: - 101*1us * =~100us (SystemC device ENV) - 101*1us =~100us (VIP based ENV) For synthesis purposes it is * recommended to set the value: - 101*1us =~100us */ #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_SHIFT)) & USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_MASK) #define USB3_CFG_REG45_RESERVED_MASK (0x3FFFFF80U) #define USB3_CFG_REG45_RESERVED_SHIFT (7U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG45_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG45_RESERVED_SHIFT)) & USB3_CFG_REG45_RESERVED_MASK) #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_SHIFT (30U) /*! ITP_WAKEUP_TIMEOUT_PRESCALE - PRESCALER for ITP_WAKEUP_TIMEOUT value: - 0x0 : 8ns (PHY pclk * clock) - 0x1 : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG46 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG46_TSEQ_QUANTITY_MASK (0xFFFFU) #define USB3_CFG_REG46_TSEQ_QUANTITY_SHIFT (0U) /*! TSEQ_QUANTITY - TSEQ_QUANTITY value This parameter defines the number of TSEQ training sequences * to be sent during Polling.RxEq state. For simulation purposes it is recommended to set the * value 655 For synthesis purposes it is recommended to set the value 65535 */ #define USB3_CFG_REG46_TSEQ_QUANTITY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG46_TSEQ_QUANTITY_SHIFT)) & USB3_CFG_REG46_TSEQ_QUANTITY_MASK) #define USB3_CFG_REG46_RESERVED_MASK (0xFFFF0000U) #define USB3_CFG_REG46_RESERVED_SHIFT (16U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG46_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG46_RESERVED_SHIFT)) & USB3_CFG_REG46_RESERVED_MASK) /*! @} */ /*! @name CFG_REG47 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG47_ERDY_TIMEOUT_CNT_MASK (0xFFFFFU) #define USB3_CFG_REG47_ERDY_TIMEOUT_CNT_SHIFT (0U) /*! ERDY_TIMEOUT_CNT - ERDY_TIMEOUT_CNT value Resolution of this parameter is 1 us. For simulation * purposes it is recommended to set the value 16 (~15 us) For synthesis purposes it is * recommended to set the value ~512001 (~512ms) */ #define USB3_CFG_REG47_ERDY_TIMEOUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG47_ERDY_TIMEOUT_CNT_SHIFT)) & USB3_CFG_REG47_ERDY_TIMEOUT_CNT_MASK) #define USB3_CFG_REG47_RESERVED_MASK (0xFFF00000U) #define USB3_CFG_REG47_RESERVED_SHIFT (20U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG47_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG47_RESERVED_SHIFT)) & USB3_CFG_REG47_RESERVED_MASK) /*! @} */ /*! @name CFG_REG48 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG48_TWTRSTFS_J_CNT_MASK (0x3FFFFU) #define USB3_CFG_REG48_TWTRSTFS_J_CNT_SHIFT (0U) /*! TWTRSTFS_J_CNT - TWTRSTFS_J_CNT value Resolution of this parameter is 33.3 ns. For simulation * purposes it is recommended to set the value 98304 (~3.28ms) For synthesis purposes it is * recommended to set the value 98304 (~3.28ms) */ #define USB3_CFG_REG48_TWTRSTFS_J_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG48_TWTRSTFS_J_CNT_SHIFT)) & USB3_CFG_REG48_TWTRSTFS_J_CNT_MASK) #define USB3_CFG_REG48_RESERVED_MASK (0xFFFC0000U) #define USB3_CFG_REG48_RESERVED_SHIFT (18U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG48_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG48_RESERVED_SHIFT)) & USB3_CFG_REG48_RESERVED_MASK) /*! @} */ /*! @name CFG_REG49 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG49_TUCH_CNT_MASK (0xFFFFU) #define USB3_CFG_REG49_TUCH_CNT_SHIFT (0U) /*! TUCH_CNT - TUCH_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes it is * recommended to set the value 129 (~4.3us) For synthesis purposes it is recommended to set the * value 35584 (~1.19ms) */ #define USB3_CFG_REG49_TUCH_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG49_TUCH_CNT_SHIFT)) & USB3_CFG_REG49_TUCH_CNT_MASK) #define USB3_CFG_REG49_RESERVED_MASK (0xFFFF0000U) #define USB3_CFG_REG49_RESERVED_SHIFT (16U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG49_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG49_RESERVED_SHIFT)) & USB3_CFG_REG49_RESERVED_MASK) /*! @} */ /*! @name CFG_REG50 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG50_TWAITCHK_CNT_MASK (0xFFFU) #define USB3_CFG_REG50_TWAITCHK_CNT_SHIFT (0U) /*! TWAITCHK_CNT - TWAITCHK_CNT value Resolution of this parameter is 33.3 ns. For simulation * purposes it is recommended to set the value 30 (~1us) For synthesis purposes it is recommended to * set the value 2400 (~80us) */ #define USB3_CFG_REG50_TWAITCHK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG50_TWAITCHK_CNT_SHIFT)) & USB3_CFG_REG50_TWAITCHK_CNT_MASK) #define USB3_CFG_REG50_RESERVED_MASK (0xFFFFF000U) #define USB3_CFG_REG50_RESERVED_SHIFT (12U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG50_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG50_RESERVED_SHIFT)) & USB3_CFG_REG50_RESERVED_MASK) /*! @} */ /*! @name CFG_REG51 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG51_TWTFS_CNT_MASK (0x1FFFFU) #define USB3_CFG_REG51_TWTFS_CNT_SHIFT (0U) /*! TWTFS_CNT - TWTFS_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes it * is recommended to set the value 1000 (~33.3us) For synthesis purposes it is recommended to set * the value 104963 (~3.5ms) */ #define USB3_CFG_REG51_TWTFS_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG51_TWTFS_CNT_SHIFT)) & USB3_CFG_REG51_TWTFS_CNT_MASK) #define USB3_CFG_REG51_RESERVED_MASK (0xFFFE0000U) #define USB3_CFG_REG51_RESERVED_SHIFT (17U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG51_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG51_RESERVED_SHIFT)) & USB3_CFG_REG51_RESERVED_MASK) /*! @} */ /*! @name CFG_REG52 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG52_TWTREV_CNT_MASK (0x1FFFFU) #define USB3_CFG_REG52_TWTREV_CNT_SHIFT (0U) /*! TWTREV_CNT - TWTREV_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes * it is recommended to set the value 90112 (~3ms) For synthesis purposes it is recommended to set * the value 90112 (~3ms) */ #define USB3_CFG_REG52_TWTREV_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG52_TWTREV_CNT_SHIFT)) & USB3_CFG_REG52_TWTREV_CNT_MASK) #define USB3_CFG_REG52_RESERVED_MASK (0xFFFE0000U) #define USB3_CFG_REG52_RESERVED_SHIFT (17U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG52_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG52_RESERVED_SHIFT)) & USB3_CFG_REG52_RESERVED_MASK) /*! @} */ /*! @name CFG_REG53 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG53_TWTRSTHS_CNT_MASK (0x7FFFU) #define USB3_CFG_REG53_TWTRSTHS_CNT_SHIFT (0U) /*! TWTRSTHS_CNT - TWTRSTHS_CNT value Resolution of this parameter is 33.3 ns. For simulation * purposes it is recommended to set the value 23552 (~785us) For synthesis purposes it is recommended * to set the value 23552 (~785us) */ #define USB3_CFG_REG53_TWTRSTHS_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG53_TWTRSTHS_CNT_SHIFT)) & USB3_CFG_REG53_TWTRSTHS_CNT_MASK) #define USB3_CFG_REG53_RESERVED_MASK (0xFFFF8000U) #define USB3_CFG_REG53_RESERVED_SHIFT (15U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG53_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG53_RESERVED_SHIFT)) & USB3_CFG_REG53_RESERVED_MASK) /*! @} */ /*! @name CFG_REG54 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG54_TWTRSM_CNT_MASK (0x3FFFFU) #define USB3_CFG_REG54_TWTRSM_CNT_SHIFT (0U) /*! TWTRSM_CNT - TWTRSM_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes * it is recommended to set the value 150016 (~5ms) For synthesis purposes it is recommended to * set the value 150016 (~5ms) */ #define USB3_CFG_REG54_TWTRSM_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG54_TWTRSM_CNT_SHIFT)) & USB3_CFG_REG54_TWTRSM_CNT_MASK) #define USB3_CFG_REG54_RESERVED_MASK (0xFFFC0000U) #define USB3_CFG_REG54_RESERVED_SHIFT (18U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG54_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG54_RESERVED_SHIFT)) & USB3_CFG_REG54_RESERVED_MASK) /*! @} */ /*! @name CFG_REG55 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG55_TDRSMUP_CNT_MASK (0xFFFFU) #define USB3_CFG_REG55_TDRSMUP_CNT_SHIFT (0U) /*! TDRSMUP_CNT - TDRSMUP_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes * it is recommended to set the value 32768 (~1.1ms) For synthesis purposes it is recommended to * set the value 32768 (~1.1ms) */ #define USB3_CFG_REG55_TDRSMUP_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG55_TDRSMUP_CNT_SHIFT)) & USB3_CFG_REG55_TDRSMUP_CNT_MASK) #define USB3_CFG_REG55_RESERVED_MASK (0xFFFF0000U) #define USB3_CFG_REG55_RESERVED_SHIFT (16U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG55_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG55_RESERVED_SHIFT)) & USB3_CFG_REG55_RESERVED_MASK) /*! @} */ /*! @name CFG_REG56 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG56_TOUTHS_CNT_MASK (0x3FU) #define USB3_CFG_REG56_TOUTHS_CNT_SHIFT (0U) /*! TOUTHS_CNT - TOUTHS_CNT value Resolution of this parameter is 33.3 ns. For simulation purposes * it is recommended to set the value 48 (~1.6us) For synthesis purposes it is recommended to set * the value 48 (~1.6us) */ #define USB3_CFG_REG56_TOUTHS_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG56_TOUTHS_CNT_SHIFT)) & USB3_CFG_REG56_TOUTHS_CNT_MASK) #define USB3_CFG_REG56_RESERVED_MASK (0xFFFFFFC0U) #define USB3_CFG_REG56_RESERVED_SHIFT (6U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG56_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG56_RESERVED_SHIFT)) & USB3_CFG_REG56_RESERVED_MASK) /*! @} */ /*! @name CFG_REG57 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG57_LFPS_DEB_WIDTH_MASK (0x3U) #define USB3_CFG_REG57_LFPS_DEB_WIDTH_SHIFT (0U) /*! LFPS_DEB_WIDTH - LFPS_DEB_WIDTH value This parameter defines the LFPS debouncer delay. Only two * values are allowed: 0x1 or 0x2. For simulation purposes it is recommended to set the value 1. * For synthesis purposes it is recommended to set the value 2 */ #define USB3_CFG_REG57_LFPS_DEB_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG57_LFPS_DEB_WIDTH_SHIFT)) & USB3_CFG_REG57_LFPS_DEB_WIDTH_MASK) #define USB3_CFG_REG57_RESERVED_MASK (0xFFFFFFFCU) #define USB3_CFG_REG57_RESERVED_SHIFT (2U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG57_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG57_RESERVED_SHIFT)) & USB3_CFG_REG57_RESERVED_MASK) /*! @} */ /*! @name CFG_REG58 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG58_LFPS_GEN_U2EXIT_MASK (0x3FFFFU) #define USB3_CFG_REG58_LFPS_GEN_U2EXIT_SHIFT (0U) /*! LFPS_GEN_U2EXIT - LFPS_GEN_U2EXIT value Resolution of this parameter is 8 ns. For simulation * purposes it is recommended to set the value 62500 (~500us) For synthesis purposes it is * recommended to set the value 250000 (~2ms) */ #define USB3_CFG_REG58_LFPS_GEN_U2EXIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG58_LFPS_GEN_U2EXIT_SHIFT)) & USB3_CFG_REG58_LFPS_GEN_U2EXIT_MASK) #define USB3_CFG_REG58_RESERVED_MASK (0xFFFC0000U) #define USB3_CFG_REG58_RESERVED_SHIFT (18U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG58_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG58_RESERVED_SHIFT)) & USB3_CFG_REG58_RESERVED_MASK) /*! @} */ /*! @name CFG_REG59 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_MASK (0xFFFFU) #define USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_SHIFT (0U) /*! LFPS_MIN_GEN_U3EXIT - LFPS_MIN_GEN_U3EXIT value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 12500 (~100us) For synthesis purposes it is * recommended to set the value 12500 (~100us) */ #define USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_SHIFT)) & USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_MASK) #define USB3_CFG_REG59_RESERVED_MASK (0xFFFF0000U) #define USB3_CFG_REG59_RESERVED_SHIFT (16U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG59_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG59_RESERVED_SHIFT)) & USB3_CFG_REG59_RESERVED_MASK) /*! @} */ /*! @name CFG_REG60 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_MASK (0x7FU) #define USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_SHIFT (0U) /*! PORT_CONFIG_TIMEOUT - PORT_CONFIG_TIMEOUT value Resolution of this parameter is 1 us. For * simulation purposes it is recommended to set the value 21 (~20us) For synthesis purposes it is * recommended to set the value 21 (~20us) */ #define USB3_CFG_REG60_PORT_CONFIG_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_SHIFT)) & USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_MASK) #define USB3_CFG_REG60_RESERVED_MASK (0xFFFFFF80U) #define USB3_CFG_REG60_RESERVED_SHIFT (7U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG60_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG60_RESERVED_SHIFT)) & USB3_CFG_REG60_RESERVED_MASK) /*! @} */ /*! @name CFG_REG61 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_MASK (0x7FFU) #define USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_SHIFT (0U) /*! LFPS_POL_LFPS_TO_RXEQ - LFPS_POL_LFPS_TO_RXEQ value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value 250 (~2us) For synthesis purposes it is * recommended to set the value 250 (~2us) */ #define USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_SHIFT)) & USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_MASK) #define USB3_CFG_REG61_RESERVED_MASK (0xFFFFF800U) #define USB3_CFG_REG61_RESERVED_SHIFT (11U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG61_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG61_RESERVED_SHIFT)) & USB3_CFG_REG61_RESERVED_MASK) /*! @} */ /*! @name CFG_REG62 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG62_PHY_TX_LATENCY_MASK (0x3FU) #define USB3_CFG_REG62_PHY_TX_LATENCY_SHIFT (0U) /*! PHY_TX_LATENCY - PHY_TX_LATENCY value This parameter defines latency from when data appear on * PIPE interface to channel + 3 time units (defined by PHY_TX_LATENCY_PRESCALE). For simulation * purposes it is recommended to set the value 11. For synthesis purposes it is recommended to set * the value 11 */ #define USB3_CFG_REG62_PHY_TX_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG62_PHY_TX_LATENCY_SHIFT)) & USB3_CFG_REG62_PHY_TX_LATENCY_MASK) #define USB3_CFG_REG62_RESERVED_MASK (0x3FFFFFC0U) #define USB3_CFG_REG62_RESERVED_SHIFT (6U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG62_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG62_RESERVED_SHIFT)) & USB3_CFG_REG62_RESERVED_MASK) #define USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_MASK (0xC0000000U) #define USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_SHIFT (30U) /*! PHY_TX_LATENCY_PRESCALE - PRESCALER for PHY_TX_LATENCY value: - 0x0 : 8ns (PHY pclk clock) - 0x1 * : 1us - 0x2 : 100us - 0x3 : no clock - allows disabling certain timeout */ #define USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_SHIFT)) & USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_MASK) /*! @} */ /*! @name CFG_REG63 - USB3 Configuration */ /*! @{ */ #define USB3_CFG_REG63_U2_INACTIVITY_TMOUT_MASK (0x7FFFU) #define USB3_CFG_REG63_U2_INACTIVITY_TMOUT_SHIFT (0U) /*! U2_INACTIVITY_TMOUT - U2_INACTIVITY_TMOUT value Resolution of this parameter is 8 ns. For * simulation purposes it is recommended to set the value: - 31999*8ns =~256us (SystemC device ENV) - * 249*8ns =~2us (VIP based ENV) For synthesis purposes it is recommended to set the value: - * 31999*8ns =~256us */ #define USB3_CFG_REG63_U2_INACTIVITY_TMOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG63_U2_INACTIVITY_TMOUT_SHIFT)) & USB3_CFG_REG63_U2_INACTIVITY_TMOUT_MASK) #define USB3_CFG_REG63_RESERVED_MASK (0xFFFF8000U) #define USB3_CFG_REG63_RESERVED_SHIFT (15U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG63_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG63_RESERVED_SHIFT)) & USB3_CFG_REG63_RESERVED_MASK) /*! @} */ /*! @name CFG_REG64 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG64_TFILTSE0_MASK (0x7FU) #define USB3_CFG_REG64_TFILTSE0_SHIFT (0U) /*! TFILTSE0 - TFILTSE0 value Resolution of this parameter is 33.3ns. For simulation purposes it is * recommended to set the value: - 74*33.3ns =~2.46us (SystemC device ENV) - 57*33.3ns =~1.9us * (VIP based ENV) For synthesis purposes it is recommended to set the value: - 74*33.3ns =~2.46us */ #define USB3_CFG_REG64_TFILTSE0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG64_TFILTSE0_SHIFT)) & USB3_CFG_REG64_TFILTSE0_MASK) #define USB3_CFG_REG64_RESERVED_MASK (0xFFFFFF80U) #define USB3_CFG_REG64_RESERVED_SHIFT (7U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG64_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG64_RESERVED_SHIFT)) & USB3_CFG_REG64_RESERVED_MASK) /*! @} */ /*! @name CFG_REG65 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG65_TFILT_MASK (0x7FU) #define USB3_CFG_REG65_TFILT_SHIFT (0U) /*! TFILT - TFILT value Resolution of this parameter is 33.3 ns. For simulation purposes it is * recommended to set the value: - 75*33.3ns =~2.5us (SystemC device ENV) - 57*33.3ns =~1.9us (VIP * based ENV) For synthesis purposes it is recommended to set the value: - 75*33.3ns =~2.5us */ #define USB3_CFG_REG65_TFILT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG65_TFILT_SHIFT)) & USB3_CFG_REG65_TFILT_MASK) #define USB3_CFG_REG65_RESERVED_MASK (0xFFFF8000U) #define USB3_CFG_REG65_RESERVED_SHIFT (15U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG65_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG65_RESERVED_SHIFT)) & USB3_CFG_REG65_RESERVED_MASK) /*! @} */ /*! @name CFG_REG66 - USB2 Configuration */ /*! @{ */ #define USB3_CFG_REG66_TWTRSTFS_SE0_MASK (0x7FU) #define USB3_CFG_REG66_TWTRSTFS_SE0_SHIFT (0U) /*! TWTRSTFS_SE0 - TWTRSTFS_SE0 value Resolution of this parameter is 33.3 ns. For simulation * purposes it is recommended to set the value: - 73*33.3ns =~2.43us (SystemC device ENV) - 57*33.3ns * =~1.9us (VIP based ENV) For synthesis purposes it is recommended to set the value: - 73*33.3ns * =~2.43us */ #define USB3_CFG_REG66_TWTRSTFS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG66_TWTRSTFS_SE0_SHIFT)) & USB3_CFG_REG66_TWTRSTFS_SE0_MASK) #define USB3_CFG_REG66_RESERVED_MASK (0xFFFF8000U) #define USB3_CFG_REG66_RESERVED_SHIFT (15U) /*! RESERVED - Reserved field. Write ignored. 0 when read */ #define USB3_CFG_REG66_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG66_RESERVED_SHIFT)) & USB3_CFG_REG66_RESERVED_MASK) /*! @} */ /*! @name DMA_AXI_CTRL - DMA AXI Master Control */ /*! @{ */ #define USB3_DMA_AXI_CTRL_MARPROT_MASK (0x7U) #define USB3_DMA_AXI_CTRL_MARPROT_SHIFT (0U) /*! MARPROT - MARPROT */ #define USB3_DMA_AXI_CTRL_MARPROT(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MARPROT_SHIFT)) & USB3_DMA_AXI_CTRL_MARPROT_MASK) #define USB3_DMA_AXI_CTRL_RESERVED0_MASK (0x8U) #define USB3_DMA_AXI_CTRL_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define USB3_DMA_AXI_CTRL_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED0_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED0_MASK) #define USB3_DMA_AXI_CTRL_MARCACHE_MASK (0xF0U) #define USB3_DMA_AXI_CTRL_MARCACHE_SHIFT (4U) /*! MARCACHE - MARCACHE */ #define USB3_DMA_AXI_CTRL_MARCACHE(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MARCACHE_SHIFT)) & USB3_DMA_AXI_CTRL_MARCACHE_MASK) #define USB3_DMA_AXI_CTRL_MARLOCK_MASK (0x300U) #define USB3_DMA_AXI_CTRL_MARLOCK_SHIFT (8U) /*! MARLOCK - MARLOCK */ #define USB3_DMA_AXI_CTRL_MARLOCK(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MARLOCK_SHIFT)) & USB3_DMA_AXI_CTRL_MARLOCK_MASK) #define USB3_DMA_AXI_CTRL_RESERVED1_MASK (0xFC00U) #define USB3_DMA_AXI_CTRL_RESERVED1_SHIFT (10U) /*! RESERVED1 - RESERVED1 */ #define USB3_DMA_AXI_CTRL_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED1_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED1_MASK) #define USB3_DMA_AXI_CTRL_MAWPROT_MASK (0x70000U) #define USB3_DMA_AXI_CTRL_MAWPROT_SHIFT (16U) /*! MAWPROT - MAWPROT */ #define USB3_DMA_AXI_CTRL_MAWPROT(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MAWPROT_SHIFT)) & USB3_DMA_AXI_CTRL_MAWPROT_MASK) #define USB3_DMA_AXI_CTRL_RESERVED2_MASK (0x80000U) #define USB3_DMA_AXI_CTRL_RESERVED2_SHIFT (19U) /*! RESERVED2 - RESERVED2 */ #define USB3_DMA_AXI_CTRL_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED2_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED2_MASK) #define USB3_DMA_AXI_CTRL_MAWCACHE_MASK (0xF00000U) #define USB3_DMA_AXI_CTRL_MAWCACHE_SHIFT (20U) /*! MAWCACHE - MAWCACHE */ #define USB3_DMA_AXI_CTRL_MAWCACHE(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MAWCACHE_SHIFT)) & USB3_DMA_AXI_CTRL_MAWCACHE_MASK) #define USB3_DMA_AXI_CTRL_MAWLOCK_MASK (0x3000000U) #define USB3_DMA_AXI_CTRL_MAWLOCK_SHIFT (24U) /*! MAWLOCK - MAWLOCK */ #define USB3_DMA_AXI_CTRL_MAWLOCK(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MAWLOCK_SHIFT)) & USB3_DMA_AXI_CTRL_MAWLOCK_MASK) #define USB3_DMA_AXI_CTRL_RESERVED3_MASK (0xFC000000U) #define USB3_DMA_AXI_CTRL_RESERVED3_SHIFT (26U) /*! RESERVED3 - RESERVED3 */ #define USB3_DMA_AXI_CTRL_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED3_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED3_MASK) /*! @} */ /*! @name DMA_AXI_ID - DMA AXI Master ID */ /*! @{ */ #define USB3_DMA_AXI_ID_MAW_ID_MASK (0x1FU) #define USB3_DMA_AXI_ID_MAW_ID_SHIFT (0U) /*! MAW_ID - MAW_ID */ #define USB3_DMA_AXI_ID_MAW_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_MAW_ID_SHIFT)) & USB3_DMA_AXI_ID_MAW_ID_MASK) #define USB3_DMA_AXI_ID_RESERVED0_MASK (0xFFE0U) #define USB3_DMA_AXI_ID_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define USB3_DMA_AXI_ID_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_RESERVED0_SHIFT)) & USB3_DMA_AXI_ID_RESERVED0_MASK) #define USB3_DMA_AXI_ID_MAR_ID_MASK (0x1F0000U) #define USB3_DMA_AXI_ID_MAR_ID_SHIFT (16U) /*! MAR_ID - MAR_ID */ #define USB3_DMA_AXI_ID_MAR_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_MAR_ID_SHIFT)) & USB3_DMA_AXI_ID_MAR_ID_MASK) #define USB3_DMA_AXI_ID_RESERVED1_MASK (0xFFE00000U) #define USB3_DMA_AXI_ID_RESERVED1_SHIFT (21U) /*! RESERVED1 - RESERVED1 */ #define USB3_DMA_AXI_ID_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_RESERVED1_SHIFT)) & USB3_DMA_AXI_ID_RESERVED1_MASK) /*! @} */ /*! @name DMA_AXI_CAP - DMA AXI Master Extended Capability */ /*! @{ */ #define USB3_DMA_AXI_CAP_RESERVED0_MASK (0xFFFFFU) #define USB3_DMA_AXI_CAP_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define USB3_DMA_AXI_CAP_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_RESERVED0_SHIFT)) & USB3_DMA_AXI_CAP_RESERVED0_MASK) #define USB3_DMA_AXI_CAP_AXI_DECERR_EN_MASK (0x100000U) #define USB3_DMA_AXI_CAP_AXI_DECERR_EN_SHIFT (20U) /*! AXI_DECERR_EN - This bit enables interrupt on AXI DECODE ERROR detection. When 1 and AXI_DECERR * is 1 then AXI DECODE ERROR interrupt is requested. When 0 - disabled interrupt from this source */ #define USB3_DMA_AXI_CAP_AXI_DECERR_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_DECERR_EN_SHIFT)) & USB3_DMA_AXI_CAP_AXI_DECERR_EN_MASK) #define USB3_DMA_AXI_CAP_AXI_SLVERR_EN_MASK (0x200000U) #define USB3_DMA_AXI_CAP_AXI_SLVERR_EN_SHIFT (21U) /*! AXI_SLVERR_EN - This bit enables interrupt on AXI SLAVE ERROR detection. When 1 and AXI_SLVERR * is 1 then AXI SLAVE ERROR interrupt is requested. When 0 - disabled interrupt from this source */ #define USB3_DMA_AXI_CAP_AXI_SLVERR_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_SLVERR_EN_SHIFT)) & USB3_DMA_AXI_CAP_AXI_SLVERR_EN_MASK) #define USB3_DMA_AXI_CAP_RESERVED1_MASK (0xFC00000U) #define USB3_DMA_AXI_CAP_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define USB3_DMA_AXI_CAP_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_RESERVED1_SHIFT)) & USB3_DMA_AXI_CAP_RESERVED1_MASK) #define USB3_DMA_AXI_CAP_AXI_DECERR_MASK (0x10000000U) #define USB3_DMA_AXI_CAP_AXI_DECERR_SHIFT (28U) /*! AXI_DECERR - This bit provides an information about AXI DECODE ERROR response on B or R channel. * This flag is cleared by writing '1' to it. Once set it is held until cleared */ #define USB3_DMA_AXI_CAP_AXI_DECERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_DECERR_SHIFT)) & USB3_DMA_AXI_CAP_AXI_DECERR_MASK) #define USB3_DMA_AXI_CAP_AXI_SLVERR_MASK (0x20000000U) #define USB3_DMA_AXI_CAP_AXI_SLVERR_SHIFT (29U) /*! AXI_SLVERR - This bit provides an information about AXI SLAVE ERROR response on B or R channel. * This flag is cleared by writing '1' to it. Once set it is held until cleared */ #define USB3_DMA_AXI_CAP_AXI_SLVERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_SLVERR_SHIFT)) & USB3_DMA_AXI_CAP_AXI_SLVERR_MASK) #define USB3_DMA_AXI_CAP_AXI_IDLE_MASK (0x40000000U) #define USB3_DMA_AXI_CAP_AXI_IDLE_SHIFT (30U) /*! AXI_IDLE - This bit provides information about the AXI Master state: '1': no pending action * required by the AXI Master wrapper, '0': the AXI Master wrapper has outstanding transactions */ #define USB3_DMA_AXI_CAP_AXI_IDLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_IDLE_SHIFT)) & USB3_DMA_AXI_CAP_AXI_IDLE_MASK) #define USB3_DMA_AXI_CAP_RESERVED2_MASK (0x80000000U) #define USB3_DMA_AXI_CAP_RESERVED2_SHIFT (31U) /*! RESERVED2 - RESERVED2 */ #define USB3_DMA_AXI_CAP_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_RESERVED2_SHIFT)) & USB3_DMA_AXI_CAP_RESERVED2_MASK) /*! @} */ /*! @name DMA_AXI_CTRL0 - DMA AXI Master Control */ /*! @{ */ #define USB3_DMA_AXI_CTRL0_B_MAX_MASK (0xFU) #define USB3_DMA_AXI_CTRL0_B_MAX_SHIFT (0U) /*! B_MAX - The register controls maximum burst length - it is used by the AXI Master wrapper to * determine maximum value of AxLEN. It uses AXI AxLEN encoding. Default value is the maximum * supported one and it is implementation specific. Width of this register is the same as AxLEN signals * width. Note: This register should only be written to during the register initialisation * process */ #define USB3_DMA_AXI_CTRL0_B_MAX(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL0_B_MAX_SHIFT)) & USB3_DMA_AXI_CTRL0_B_MAX_MASK) #define USB3_DMA_AXI_CTRL0_RESERVED_MASK (0xFFFFFFF0U) #define USB3_DMA_AXI_CTRL0_RESERVED_SHIFT (4U) /*! RESERVED - RESERVED */ #define USB3_DMA_AXI_CTRL0_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL0_RESERVED_SHIFT)) & USB3_DMA_AXI_CTRL0_RESERVED_MASK) /*! @} */ /*! @name DMA_AXI_CTRL1 - DMA AXI Master Control */ /*! @{ */ #define USB3_DMA_AXI_CTRL1_ROT_MASK (0x1FU) #define USB3_DMA_AXI_CTRL1_ROT_SHIFT (0U) /*! ROT - Number of outstanding read transactions that can be initiated by the AXI Master wrapper. * Default value of this field is CDNS_USBSSDEV_AXI_WCD-1 (define parameter). The value written to * this field should be the requested number of outstanding read transactions minus 1, thus the * actual number of possible outstanding read transactions is one more than the programmed value. * Note: This register should only be written to during the register initialization process */ #define USB3_DMA_AXI_CTRL1_ROT(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_ROT_SHIFT)) & USB3_DMA_AXI_CTRL1_ROT_MASK) #define USB3_DMA_AXI_CTRL1_RESERVED0_MASK (0xFFE0U) #define USB3_DMA_AXI_CTRL1_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define USB3_DMA_AXI_CTRL1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_RESERVED0_SHIFT)) & USB3_DMA_AXI_CTRL1_RESERVED0_MASK) #define USB3_DMA_AXI_CTRL1_WOT_MASK (0x1F0000U) #define USB3_DMA_AXI_CTRL1_WOT_SHIFT (16U) /*! WOT - Number of outstanding write transactions that can be initiated by the AXI Master wrapper. * Default value of this field is CDNS_USBSSDEV_AXI_WCD-1 (define parameter). The value written * to this field should be the requested number of outstanding write transactions minus 1, thus * the actual number of possible outstanding write transactions is one more than the programmed * value. Note: This register should only be written to during the register initialization process */ #define USB3_DMA_AXI_CTRL1_WOT(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_WOT_SHIFT)) & USB3_DMA_AXI_CTRL1_WOT_MASK) #define USB3_DMA_AXI_CTRL1_RESERVED1_MASK (0xFFE00000U) #define USB3_DMA_AXI_CTRL1_RESERVED1_SHIFT (21U) /*! RESERVED1 - RESERVED1 */ #define USB3_DMA_AXI_CTRL1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_RESERVED1_SHIFT)) & USB3_DMA_AXI_CTRL1_RESERVED1_MASK) /*! @} */ /*! * @} */ /* end of group USB3_Register_Masks */ /* USB3 - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__USB3 base address */ #define CONNECTIVITY__USB3_BASE (0x5B110000u) /** Peripheral CONNECTIVITY__USB3 base pointer */ #define CONNECTIVITY__USB3 ((USB3_Type *)CONNECTIVITY__USB3_BASE) /** Array initializer of USB3 peripheral base addresses */ #define USB3_BASE_ADDRS { CONNECTIVITY__USB3_BASE } /** Array initializer of USB3 peripheral base pointers */ #define USB3_BASE_PTRS { CONNECTIVITY__USB3 } /** Interrupt vectors for the USB3 peripheral type */ #define USB3_IRQS { CONNECTIVITY_USB3_INT_IRQn } /*! * @} */ /* end of group USB3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBDCD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer * @{ */ /** USBDCD - Register Layout Typedef */ typedef struct { __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */ __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */ __I uint32_t STATUS; /**< Status register, offset: 0x8 */ __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */ __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */ __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */ union { /* offset: 0x18 */ __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */ __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */ }; } USBDCD_Type; /* ---------------------------------------------------------------------------- -- USBDCD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBDCD_Register_Masks USBDCD Register Masks * @{ */ /*! @name CONTROL - Control register */ /*! @{ */ #define USBDCD_CONTROL_IACK_MASK (0x1U) #define USBDCD_CONTROL_IACK_SHIFT (0U) /*! IACK - Interrupt Acknowledge * 0b0..Do not clear the interrupt. * 0b1..Clear the IF bit (interrupt flag). */ #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK) #define USBDCD_CONTROL_IF_MASK (0x100U) #define USBDCD_CONTROL_IF_SHIFT (8U) /*! IF - Interrupt Flag * 0b0..No interrupt is pending. * 0b1..An interrupt is pending. */ #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK) #define USBDCD_CONTROL_IE_MASK (0x10000U) #define USBDCD_CONTROL_IE_SHIFT (16U) /*! IE - Interrupt Enable * 0b0..Disable interrupts to the system. * 0b1..Enable interrupts to the system. */ #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK) #define USBDCD_CONTROL_BC12_MASK (0x20000U) #define USBDCD_CONTROL_BC12_SHIFT (17U) /*! BC12 - BC12 * 0b0..Compatible with BC1.1 (default) * 0b1..Compatible with BC1.2 */ #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK) #define USBDCD_CONTROL_START_MASK (0x1000000U) #define USBDCD_CONTROL_START_SHIFT (24U) /*! START - Start Change Detection Sequence * 0b0..Do not start the sequence. Writes of this value have no effect. * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. */ #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK) #define USBDCD_CONTROL_SR_MASK (0x2000000U) #define USBDCD_CONTROL_SR_SHIFT (25U) /*! SR - Software Reset * 0b0..Do not perform a software reset. * 0b1..Perform a software reset. */ #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK) /*! @} */ /*! @name CLOCK - Clock register */ /*! @{ */ #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed * 0b0..kHz Speed (between 1 kHz and 1023 kHz) * 0b1..MHz Speed (between 1 MHz and 1023 MHz) */ #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK) #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */ #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK) /*! @} */ /*! @name STATUS - Status register */ /*! @{ */ #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U) #define USBDCD_STATUS_SEQ_RES_SHIFT (16U) /*! SEQ_RES - Charger Detection Sequence Results * 0b00..No results to report. * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. * 0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a * DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type * detection has completed.) * 0b11..Attached to a DCP. */ #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK) #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U) #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U) /*! SEQ_STAT - Charger Detection Sequence Status * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected. * 0b01..Data pin contact detection is complete. * 0b10..Charging port detection is complete. * 0b11..Charger type detection is complete. */ #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK) #define USBDCD_STATUS_ERR_MASK (0x100000U) #define USBDCD_STATUS_ERR_SHIFT (20U) /*! ERR - Error Flag * 0b0..No sequence errors. * 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred. */ #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK) #define USBDCD_STATUS_TO_MASK (0x200000U) #define USBDCD_STATUS_TO_SHIFT (21U) /*! TO - Timeout Flag * 0b0..The detection sequence has not been running for over 1 s. * 0b1..It has been over 1 s since the data pin contact was detected and debounced. */ #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK) #define USBDCD_STATUS_ACTIVE_MASK (0x400000U) #define USBDCD_STATUS_ACTIVE_SHIFT (22U) /*! ACTIVE - Active Status Indicator * 0b0..The sequence is not running. * 0b1..The sequence is running. */ #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK) /*! @} */ /*! @name SIGNAL_OVERRIDE - Signal Override Register */ /*! @{ */ #define USBDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U) #define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U) /*! PS - Phase Selection * 0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent * unexpected conditions on USB_DP and USB_DM pins. (Default) * 0b01..Reserved, not for customer use. * 0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. * 0b11..Reserved, not for customer use. */ #define USBDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK) /*! @} */ /*! @name TIMER0 - TIMER0 register */ /*! @{ */ #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU) #define USBDCD_TIMER0_TUNITCON_SHIFT (0U) /*! TUNITCON - Unit Connection Timer Elapse (in ms) */ #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK) #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U) /*! TSEQ_INIT - Sequence Initiation Time */ #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK) /*! @} */ /*! @name TIMER1 - TIMER1 register */ /*! @{ */ #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) /*! TVDPSRC_ON - Time Period Comparator Enabled */ #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK) #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U) /*! TDCD_DBNC - Time Period to Debounce D+ Signal */ #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK) /*! @} */ /*! @name TIMER2_BC11 - TIMER2_BC11 register */ /*! @{ */ #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) /*! CHECK_DM - Time Before Check of D- Line */ #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup */ #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) /*! @} */ /*! @name TIMER2_BC12 - TIMER2_BC12 register */ /*! @{ */ #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) /*! TVDMSRC_ON - TVDMSRC_ON */ #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD */ #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) /*! @} */ /*! * @} */ /* end of group USBDCD_Register_Masks */ /* USBDCD - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__USBDCD base address */ #define CONNECTIVITY__USBDCD_BASE (0x5B100800u) /** Peripheral CONNECTIVITY__USBDCD base pointer */ #define CONNECTIVITY__USBDCD ((USBDCD_Type *)CONNECTIVITY__USBDCD_BASE) /** Array initializer of USBDCD peripheral base addresses */ #define USBDCD_BASE_ADDRS { CONNECTIVITY__USBDCD_BASE } /** Array initializer of USBDCD peripheral base pointers */ #define USBDCD_BASE_PTRS { CONNECTIVITY__USBDCD } /*! * @} */ /* end of group USBDCD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBNC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer * @{ */ /** USBNC - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[512]; __IO uint32_t CTRL1; /**< , offset: 0x200 */ __IO uint32_t CTRL2; /**< , offset: 0x204 */ uint8_t RESERVED_1[40]; __IO uint32_t PHY_CFG1; /**< USB OTG PHY Configuration Register 1, offset: 0x230 */ __IO uint32_t PHY_CFG2; /**< USB OTG PHY Configuration Register 2, offset: 0x234 */ uint8_t RESERVED_2[4]; __I uint32_t PHY_STATUS; /**< USB OTG PHY Status Register, offset: 0x23C */ uint8_t RESERVED_3[16]; __IO uint32_t ADP_CFG1; /**< , offset: 0x250 */ __IO uint32_t ADP_CFG2; /**< , offset: 0x254 */ __I uint32_t ADP_STATUS; /**< , offset: 0x258 */ } USBNC_Type; /* ---------------------------------------------------------------------------- -- USBNC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Register_Masks USBNC Register Masks * @{ */ /*! @name CTRL1 - */ /*! @{ */ #define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) /*! OVER_CUR_DIS * 0b1..Disables overcurrent detection * 0b0..Enables overcurrent detection */ #define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) #define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) #define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) /*! OVER_CUR_POL * 0b1..Low active (low on this signal represents an overcurrent condition) * 0b0..High active (high on this signal represents an overcurrent condition) */ #define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) #define USBNC_CTRL1_PWR_POL_MASK (0x200U) #define USBNC_CTRL1_PWR_POL_SHIFT (9U) /*! PWR_POL * 0b1..PMIC Power Pin is High active. * 0b0..PMIC Power Pin is Low active. */ #define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) #define USBNC_CTRL1_WIE_MASK (0x400U) #define USBNC_CTRL1_WIE_SHIFT (10U) /*! WIE * 0b1..Interrupt Enabled * 0b0..Interrupt Disabled */ #define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) #define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) #define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) /*! WKUP_SW_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) #define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) #define USBNC_CTRL1_WKUP_SW_SHIFT (15U) /*! WKUP_SW * 0b1..Force wake-up * 0b0..Inactive */ #define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) #define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) #define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) /*! WKUP_ID_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) #define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) /*! WKUP_VBUS_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) #define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) /*! WKUP_DPDM_EN * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. */ #define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) #define USBNC_CTRL1_WIR_MASK (0x80000000U) #define USBNC_CTRL1_WIR_SHIFT (31U) /*! WIR * 0b1..Wake-up Interrupt Request received * 0b0..No wake-up interrupt request received */ #define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) /*! @} */ /*! @name CTRL2 - */ /*! @{ */ #define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) #define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) #define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK) #define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U) #define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U) /*! AUTURESUME_EN - Auto Resume Enable * 0b0..Default */ #define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK) #define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) #define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) /*! LOWSPEED_EN * 0b0..Default */ #define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) #define USBNC_CTRL2_TERMSEL_OVERRIDE_MASK (0x10U) #define USBNC_CTRL2_TERMSEL_OVERRIDE_SHIFT (4U) #define USBNC_CTRL2_TERMSEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_TERMSEL_OVERRIDE_SHIFT)) & USBNC_CTRL2_TERMSEL_OVERRIDE_MASK) #define USBNC_CTRL2_TERMSEL_OVERRIDEEN_MASK (0x20U) #define USBNC_CTRL2_TERMSEL_OVERRIDEEN_SHIFT (5U) /*! TERMSEL_OVERRIDEEN * 0b0..The state of the UTMI TermSelect signal to the USB PHY is set by the USB controller. * 0b1..The state of the UTMI TermSelect signal to the USB PHY is set by the value in the USBNC_x_CTRL2[TERMSEL_OVERRIDE] bit field. */ #define USBNC_CTRL2_TERMSEL_OVERRIDEEN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_TERMSEL_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_TERMSEL_OVERRIDEEN_MASK) #define USBNC_CTRL2_OPMODE_OVERRIDE_MASK (0xC0U) #define USBNC_CTRL2_OPMODE_OVERRIDE_SHIFT (6U) #define USBNC_CTRL2_OPMODE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_OPMODE_OVERRIDE_SHIFT)) & USBNC_CTRL2_OPMODE_OVERRIDE_MASK) #define USBNC_CTRL2_OPMODE_OVERRIDEEN_MASK (0x100U) #define USBNC_CTRL2_OPMODE_OVERRIDEEN_SHIFT (8U) /*! OPMODE_OVERRIDEEN * 0b0..The state of the UTMI OpMode signals to the USB PHY is set by the USB controller. * 0b1..The state of the UTMI OpMode signals to the USB PHY is set by the values in the USBNC_x_CTRL2[OPMODE_OVERRIDE] bit field. */ #define USBNC_CTRL2_OPMODE_OVERRIDEEN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_OPMODE_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_OPMODE_OVERRIDEEN_MASK) #define USBNC_CTRL2_XCVRSEL_OVERRIDE_MASK (0x600U) #define USBNC_CTRL2_XCVRSEL_OVERRIDE_SHIFT (9U) #define USBNC_CTRL2_XCVRSEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_XCVRSEL_OVERRIDE_SHIFT)) & USBNC_CTRL2_XCVRSEL_OVERRIDE_MASK) #define USBNC_CTRL2_XCVRSEL_OVERRIDEEN_MASK (0x800U) #define USBNC_CTRL2_XCVRSEL_OVERRIDEEN_SHIFT (11U) /*! XCVRSEL_OVERRIDEEN * 0b0..The state of the UTMI XcvrSelect signals to the USB PHY is set by the USB controller. * 0b1..The state of the UTMI XcvrSelect signals to the USB PHY is set by the values in the USBNC_x_CTRL2[XCVRSEL_OVERRIDE] bit field. */ #define USBNC_CTRL2_XCVRSEL_OVERRIDEEN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_XCVRSEL_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_XCVRSEL_OVERRIDEEN_MASK) #define USBNC_CTRL2_DPPULLDOWN_OVERRIDE_MASK (0x1000U) #define USBNC_CTRL2_DPPULLDOWN_OVERRIDE_SHIFT (12U) /*! DPPULLDOWN_OVERRIDE * 0b0..DP pulldown resistor disabled * 0b1..DP pulldown resistor enabled */ #define USBNC_CTRL2_DPPULLDOWN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_DPPULLDOWN_OVERRIDE_SHIFT)) & USBNC_CTRL2_DPPULLDOWN_OVERRIDE_MASK) #define USBNC_CTRL2_DPPULLDOWN_OVERRIDEEN_MASK (0x2000U) #define USBNC_CTRL2_DPPULLDOWN_OVERRIDEEN_SHIFT (13U) /*! DPPULLDOWN_OVERRIDEEN * 0b0..USB controller enables/disables the DP pulldown resistor in the USB PHY. * 0b1..Use the value set by the USBNC_n_CTRL2[DPPULLDOWN_OVERRIDE] bit field to enable/disable the DP pulldown resistor in the USB PHY. */ #define USBNC_CTRL2_DPPULLDOWN_OVERRIDEEN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_DPPULLDOWN_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_DPPULLDOWN_OVERRIDEEN_MASK) #define USBNC_CTRL2_DMPULLDOWN_OVERRIDE_MASK (0x4000U) #define USBNC_CTRL2_DMPULLDOWN_OVERRIDE_SHIFT (14U) /*! DMPULLDOWN_OVERRIDE * 0b0..DM pulldown resistor disabled * 0b1..DM pulldown resistor enabled */ #define USBNC_CTRL2_DMPULLDOWN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_DMPULLDOWN_OVERRIDE_SHIFT)) & USBNC_CTRL2_DMPULLDOWN_OVERRIDE_MASK) #define USBNC_CTRL2_DMPULLDOWN_OVERRIDEEN_MASK (0x8000U) #define USBNC_CTRL2_DMPULLDOWN_OVERRIDEEN_SHIFT (15U) /*! DMPULLDOWN_OVERRIDEEN * 0b0..USB controller enables/disables the DM pulldown resistor in the USB PHY. * 0b1..Use the value set by the USBNC_n_CTRL2[DMPULLDOWN_OVERRIDE] bit field to enable/disable the DM pulldown resistor in the USB PHY. */ #define USBNC_CTRL2_DMPULLDOWN_OVERRIDEEN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_DMPULLDOWN_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_DMPULLDOWN_OVERRIDEEN_MASK) #define USBNC_CTRL2_DIG_ID_SEL_MASK (0x100000U) #define USBNC_CTRL2_DIG_ID_SEL_SHIFT (20U) /*! DIG_ID_SEL * 0b0..Use the USB_OTG*_ID pin for the USB OTG ID pin detection function(default) * 0b1..Use the pin configured by the IOMUXC_USB_OTG*_ID_SELECT_INPUT register for the USB OTG ID pin detection function */ #define USBNC_CTRL2_DIG_ID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_DIG_ID_SEL_SHIFT)) & USBNC_CTRL2_DIG_ID_SEL_MASK) #define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) #define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) /*! UTMI_CLK_VLD * 0b0..UTMI clock to USB PHY is not toggling (Default) * 0b1..UTMI clock to USB PHY has toggled several times */ #define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) /*! @} */ /*! @name PHY_CFG1 - USB OTG PHY Configuration Register 1 */ /*! @{ */ #define USBNC_PHY_CFG1_COMMONONN_MASK (0x1U) #define USBNC_PHY_CFG1_COMMONONN_SHIFT (0U) /*! COMMONONN - Common Block Power-Down Control * 0b0..In Suspend or Sleep modes, the Bias and PLL blocks remain powered * 0b1..In Suspend or Sleep modes, the Bias and PLL blocks are powered down * 0b0.. */ #define USBNC_PHY_CFG1_COMMONONN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_COMMONONN_SHIFT)) & USBNC_PHY_CFG1_COMMONONN_MASK) #define USBNC_PHY_CFG1_FSEL_MASK (0xEU) #define USBNC_PHY_CFG1_FSEL_SHIFT (1U) /*! FSEL - Reference Clock Frequency Select * 0b000..9.6 MHz * 0b001..10 MHz * 0b010..12 MHz * 0b011..19.2 MHz * 0b100..20 MHz * 0b101..24 MHz (only valid setting for this SOC) * 0b110..Reserved * 0b111..50 MHz */ #define USBNC_PHY_CFG1_FSEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_FSEL_SHIFT)) & USBNC_PHY_CFG1_FSEL_MASK) #define USBNC_PHY_CFG1_COMPDISTUNE0_MASK (0x70U) #define USBNC_PHY_CFG1_COMPDISTUNE0_SHIFT (4U) /*! COMPDISTUNE0 - Disconnect Threshold Adjustment * 0b000..-6% * 0b001..-4.5% * 0b010..-3% * 0b011..-1.5% * 0b100..Design default * 0b101..+1.5% * 0b110..+3% * 0b111..+4.5% */ #define USBNC_PHY_CFG1_COMPDISTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_COMPDISTUNE0_SHIFT)) & USBNC_PHY_CFG1_COMPDISTUNE0_MASK) #define USBNC_PHY_CFG1_SQRXTUNE0_MASK (0x380U) #define USBNC_PHY_CFG1_SQRXTUNE0_SHIFT (7U) /*! SQRXTUNE0 - Squelch Threshold Adjustment * 0b000..+15% * 0b001..+10% * 0b010..+5% * 0b011..Design default * 0b100..-5% * 0b101..-10% * 0b110..-15% * 0b111..-20% */ #define USBNC_PHY_CFG1_SQRXTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_SQRXTUNE0_SHIFT)) & USBNC_PHY_CFG1_SQRXTUNE0_MASK) #define USBNC_PHY_CFG1_OTGTUNE0_MASK (0x1C00U) #define USBNC_PHY_CFG1_OTGTUNE0_SHIFT (10U) /*! OTGTUNE0 - VBUS Valid Threshold Adjustment * 0b000..-6% * 0b001..-4.5% * 0b010..-3% * 0b011..-1.5% * 0b100..Design default * 0b101..+1.5% * 0b110..+3% * 0b111..+4.5% */ #define USBNC_PHY_CFG1_OTGTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_OTGTUNE0_SHIFT)) & USBNC_PHY_CFG1_OTGTUNE0_MASK) #define USBNC_PHY_CFG1_TXHSXVTUNE0_MASK (0x6000U) #define USBNC_PHY_CFG1_TXHSXVTUNE0_SHIFT (13U) /*! TXHSXVTUNE0 - Transmitter High-Speed Crossover Adjustment * 0b00..Reserved * 0b01..-15mV * 0b10..+15mV * 0b11..Design default */ #define USBNC_PHY_CFG1_TXHSXVTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXHSXVTUNE0_SHIFT)) & USBNC_PHY_CFG1_TXHSXVTUNE0_MASK) #define USBNC_PHY_CFG1_TXFSLSTUNE0_MASK (0xF0000U) #define USBNC_PHY_CFG1_TXFSLSTUNE0_SHIFT (16U) /*! TXFSLSTUNE0 - FS/LS Source Impedance Adjustment * 0b0000..+5% * 0b0001..+2.5% * 0b0011..Design default * 0b0111..-2.5% * 0b1111..-5% */ #define USBNC_PHY_CFG1_TXFSLSTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXFSLSTUNE0_SHIFT)) & USBNC_PHY_CFG1_TXFSLSTUNE0_MASK) #define USBNC_PHY_CFG1_TXVREFTUNE0_MASK (0xF00000U) #define USBNC_PHY_CFG1_TXVREFTUNE0_SHIFT (20U) /*! TXVREFTUNE0 - HS DC Voltage Level Adjustment * 0b0000..-6% * 0b0001..-4% * 0b0010..-2% * 0b0011..Design default * 0b0100..+2% * 0b0101..+4% * 0b0110..+6% * 0b0111..+8% * 0b1000..+10% * 0b1001..+12% * 0b1010..+14% * 0b1011..+16% * 0b1100..+18% * 0b1101..+20% * 0b1110..+22% * 0b1111..+24% */ #define USBNC_PHY_CFG1_TXVREFTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXVREFTUNE0_SHIFT)) & USBNC_PHY_CFG1_TXVREFTUNE0_MASK) #define USBNC_PHY_CFG1_TXRISETUNE0_MASK (0x3000000U) #define USBNC_PHY_CFG1_TXRISETUNE0_SHIFT (24U) /*! TXRISETUNE0 - HS Transmitter Rise/Fall Time Adjustment * 0b00..-10% * 0b01..Design default * 0b10..+15% * 0b11..+20% */ #define USBNC_PHY_CFG1_TXRISETUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXRISETUNE0_SHIFT)) & USBNC_PHY_CFG1_TXRISETUNE0_MASK) #define USBNC_PHY_CFG1_TXRESTUNE0_MASK (0xC000000U) #define USBNC_PHY_CFG1_TXRESTUNE0_SHIFT (26U) /*! TXRESTUNE0 - USB Source Impedance Adjustment * 0b00..Source impedance is increased by approximately 1.5 ohm * 0b01..Design default * 0b10..Source impedance is decreased by approximately 2 ohm * 0b11..Source impedance is decreased by approximately 4 ohm */ #define USBNC_PHY_CFG1_TXRESTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXRESTUNE0_SHIFT)) & USBNC_PHY_CFG1_TXRESTUNE0_MASK) #define USBNC_PHY_CFG1_TXPREEMPAMPTUNE0_MASK (0x30000000U) #define USBNC_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT (28U) /*! TXPREEMPAMPTUNE0 - HS Treansmitter Pre-Emphasis Current Control * 0b00..HS Transmitter pre-emphasis is disabled * 0b01..HS Transmitter pre-emphasis circuit sources 1X pre-emphasis current (design default) * 0b10..HS Transmitter pre-emphasis circuit sources 2X pre-emphasis current * 0b11..HS Transmitter pre-emphasis circuit sources 3X pre-emphasis current */ #define USBNC_PHY_CFG1_TXPREEMPAMPTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT)) & USBNC_PHY_CFG1_TXPREEMPAMPTUNE0_MASK) #define USBNC_PHY_CFG1_TXPREEMPPULSETUNE0_MASK (0x40000000U) #define USBNC_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT (30U) /*! TXPREEMPPULSETUNE0 - HS Transmitter Pre-Emphasis Duration Control * 0b0..2X, long pre-emphasis current duration (design default) * 0b1..1X, short pre-emphasis current duration */ #define USBNC_PHY_CFG1_TXPREEMPPULSETUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT)) & USBNC_PHY_CFG1_TXPREEMPPULSETUNE0_MASK) #define USBNC_PHY_CFG1_CHRGDET_Megamix_MASK (0x80000000U) #define USBNC_PHY_CFG1_CHRGDET_Megamix_SHIFT (31U) /*! CHRGDET_Megamix - USB_OTG1_CHD_B output control * 0b0..The external state of USB_OTG1_CHD_B is only controlled by the state of the CHRGDET signal * 0b1..The external state of USB_OTG1_CHD_B is forced low */ #define USBNC_PHY_CFG1_CHRGDET_Megamix(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG1_CHRGDET_Megamix_SHIFT)) & USBNC_PHY_CFG1_CHRGDET_Megamix_MASK) /*! @} */ /*! @name PHY_CFG2 - USB OTG PHY Configuration Register 2 */ /*! @{ */ #define USBNC_PHY_CFG2_CHRGSEL_MASK (0x1U) #define USBNC_PHY_CFG2_CHRGSEL_SHIFT (0U) /*! CHRGSEL - Battery Charging Source Select * 0b0..VDP_SRC is connected to USB_OTG*_DP and IDM_SINK is connected to USB_OTG*_DN. Used for Primary Detection. * 0b1..VDM_SRC is connected to USB_OTG*_DN and IDP_SINK is connected to USB_OTG*_DP. Used for Secondary Detection. */ #define USBNC_PHY_CFG2_CHRGSEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_CHRGSEL_SHIFT)) & USBNC_PHY_CFG2_CHRGSEL_MASK) #define USBNC_PHY_CFG2_VDATDETENB0_MASK (0x2U) #define USBNC_PHY_CFG2_VDATDETENB0_SHIFT (1U) /*! VDATDETENB0 - Battery Charging Detection Comparator Enable * 0b0..Battery Charging detection comparator connected to USB_OTG*_D* pin is disabled * 0b1..Battery Charging detection comparator connected to USB_OTG*_D* pin is enabled */ #define USBNC_PHY_CFG2_VDATDETENB0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_VDATDETENB0_SHIFT)) & USBNC_PHY_CFG2_VDATDETENB0_MASK) #define USBNC_PHY_CFG2_VDATSRCENB0_MASK (0x4U) #define USBNC_PHY_CFG2_VDATSRCENB0_SHIFT (2U) /*! VDATSRCENB0 - Battery Charging Source Select * 0b0..VD*_SRC and ID*_SINK are disabled * 0b1..VD*_SRC and ID*_SINK are enabled */ #define USBNC_PHY_CFG2_VDATSRCENB0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_VDATSRCENB0_SHIFT)) & USBNC_PHY_CFG2_VDATSRCENB0_MASK) #define USBNC_PHY_CFG2_DCDENB_MASK (0x8U) #define USBNC_PHY_CFG2_DCDENB_SHIFT (3U) /*! DCDENB - Data Contact Detection Enable * 0b0..IDP_SRC current and RDM_DWN pull-down resistance are disabled * 0b1..IDP_SRC current and RDM_DWN pull-down resistance are enabled */ #define USBNC_PHY_CFG2_DCDENB(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_DCDENB_SHIFT)) & USBNC_PHY_CFG2_DCDENB_MASK) #define USBNC_PHY_CFG2_ACAENB0_MASK (0x10U) #define USBNC_PHY_CFG2_ACAENB0_SHIFT (4U) /*! ACAENB0 - ACA USB_OTG*_ID Pin Resistance Detection Enable * 0b0..Disables detection of resistance on the USB_OTG*_ID pin * 0b1..Enables detection of resistance on the USB_OTG*_ID pin */ #define USBNC_PHY_CFG2_ACAENB0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_ACAENB0_SHIFT)) & USBNC_PHY_CFG2_ACAENB0_MASK) #define USBNC_PHY_CFG2_SLEEPM0_MASK (0x20U) #define USBNC_PHY_CFG2_SLEEPM0_SHIFT (5U) /*! SLEEPM0 - Sleep Mode Assertion * 0b0..Sleep mode * 0b1..Normal operating mode */ #define USBNC_PHY_CFG2_SLEEPM0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_SLEEPM0_SHIFT)) & USBNC_PHY_CFG2_SLEEPM0_MASK) #define USBNC_PHY_CFG2_LOOPBACKENB0_MASK (0x40U) #define USBNC_PHY_CFG2_LOOPBACKENB0_SHIFT (6U) /*! LOOPBACKENB0 - Loopback Test Enable * 0b0..During data transmission, the receive logic is disabled * 0b1..During data transmission, the receive logic is enabled */ #define USBNC_PHY_CFG2_LOOPBACKENB0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_LOOPBACKENB0_SHIFT)) & USBNC_PHY_CFG2_LOOPBACKENB0_MASK) #define USBNC_PHY_CFG2_TXBITSTUFFEN0_MASK (0x100U) #define USBNC_PHY_CFG2_TXBITSTUFFEN0_SHIFT (8U) /*! TXBITSTUFFEN0 - Low-Byte Transmit Bit-Stuffing Enable * 0b0..Bit stuffing is disabled * 0b1..Bit stuffing is enabled */ #define USBNC_PHY_CFG2_TXBITSTUFFEN0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_TXBITSTUFFEN0_SHIFT)) & USBNC_PHY_CFG2_TXBITSTUFFEN0_MASK) #define USBNC_PHY_CFG2_TXBITSTUFFENH0_MASK (0x200U) #define USBNC_PHY_CFG2_TXBITSTUFFENH0_SHIFT (9U) /*! TXBITSTUFFENH0 - High-Byte Transmit Bit-Stuffing Enable * 0b0..Bit stuffing is disabled * 0b1..Bit stuffing is enabled */ #define USBNC_PHY_CFG2_TXBITSTUFFENH0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_TXBITSTUFFENH0_SHIFT)) & USBNC_PHY_CFG2_TXBITSTUFFENH0_MASK) #define USBNC_PHY_CFG2_OTGDISABLE0_MASK (0x400U) #define USBNC_PHY_CFG2_OTGDISABLE0_SHIFT (10U) /*! OTGDISABLE0 - OTG Block Disable * 0b0..The OTG block is powered up * 0b1..The OTG block is powered down */ #define USBNC_PHY_CFG2_OTGDISABLE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_OTGDISABLE0_SHIFT)) & USBNC_PHY_CFG2_OTGDISABLE0_MASK) #define USBNC_PHY_CFG2_ADPCHRG0_MASK (0x800U) #define USBNC_PHY_CFG2_ADPCHRG0_SHIFT (11U) /*! ADPCHRG0 - VBUS Input ADP Charge Enable * 0b0..Disables charging USB_OTG*_VBUS during ADP * 0b1..Disables charging USB_OTG*_VBUS during ADP */ #define USBNC_PHY_CFG2_ADPCHRG0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_ADPCHRG0_SHIFT)) & USBNC_PHY_CFG2_ADPCHRG0_MASK) #define USBNC_PHY_CFG2_ADPDISCHRG0_MASK (0x1000U) #define USBNC_PHY_CFG2_ADPDISCHRG0_SHIFT (12U) /*! ADPDISCHRG0 - VBUS Input ADP Discharge Enable * 0b0..Disables discharging USB_OTG*_VBUS during ADP * 0b1..Enables discharging USB_OTG*_VBUS during ADP */ #define USBNC_PHY_CFG2_ADPDISCHRG0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_ADPDISCHRG0_SHIFT)) & USBNC_PHY_CFG2_ADPDISCHRG0_MASK) #define USBNC_PHY_CFG2_ADPPRBENB0_MASK (0x2000U) #define USBNC_PHY_CFG2_ADPPRBENB0_SHIFT (13U) /*! ADPPRBENB0 - ADP Probe Enable * 0b0..ADP Probe comparator is disabled * 0b1..ADP Probe comparator is enabled */ #define USBNC_PHY_CFG2_ADPPRBENB0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_ADPPRBENB0_SHIFT)) & USBNC_PHY_CFG2_ADPPRBENB0_MASK) #define USBNC_PHY_CFG2_VBUSVLDEXTSEL0_MASK (0x4000U) #define USBNC_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT (14U) /*! VBUSVLDEXTSEL0 - External VBUS Valid Select * 0b0..The USB OTG PHY internal Session Valid comparator is used to enable the pull-up resistor on the USB_OTG*_DP pin * 0b1..The VBUSVLDEXT signal is used to enable the pull-up resistor on the USB_OTG*_DP pin */ #define USBNC_PHY_CFG2_VBUSVLDEXTSEL0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT)) & USBNC_PHY_CFG2_VBUSVLDEXTSEL0_MASK) #define USBNC_PHY_CFG2_VBUSVLDEXT_MASK (0x8000U) #define USBNC_PHY_CFG2_VBUSVLDEXT_SHIFT (15U) /*! VBUSVLDEXT - External VBUS Valid Indicator * 0b0..The VBUS signal sensed outside the USB OTG PHY is not valid, and the pull-up resistor on USB_OTG*_DP is disabled * 0b1..The VBUS signal sensed outside the USB OTG PHY is valid, and the pull-up resistor on USB_OTG*_DP is enabled */ #define USBNC_PHY_CFG2_VBUSVLDEXT(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_VBUSVLDEXT_SHIFT)) & USBNC_PHY_CFG2_VBUSVLDEXT_MASK) #define USBNC_PHY_CFG2_DRVVBUS0_MASK (0x10000U) #define USBNC_PHY_CFG2_DRVVBUS0_SHIFT (16U) /*! DRVVBUS0 - VBUS Valid Comparator Enable * 0b0..The VBUS Valid comparator is disabled * 0b1..The VBUS Valid comparator is enabled */ #define USBNC_PHY_CFG2_DRVVBUS0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_CFG2_DRVVBUS0_SHIFT)) & USBNC_PHY_CFG2_DRVVBUS0_MASK) /*! @} */ /*! @name PHY_STATUS - USB OTG PHY Status Register */ /*! @{ */ #define USBNC_PHY_STATUS_LINE_STATE_MASK (0x3U) #define USBNC_PHY_STATUS_LINE_STATE_SHIFT (0U) /*! LINE_STATE - Line State Indicator outputs from USB OTG PHY * 0b00..SE0 (DP low, DN low) * 0b01..J state for high-speed and full-speed USB traffic; K state for low-speed USB traffic (DP high, DN low) * 0b10..K state for high-speed and full-speed USB traffic; J state for low-speed USB traffic (DP low, DN high) * 0b11..SE1 (DP high, DN high) */ #define USBNC_PHY_STATUS_LINE_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_LINE_STATE_SHIFT)) & USBNC_PHY_STATUS_LINE_STATE_MASK) #define USBNC_PHY_STATUS_SESS_VLD_MASK (0x4U) #define USBNC_PHY_STATUS_SESS_VLD_SHIFT (2U) /*! SESS_VLD - OTG Device Session Valid Indicator from USB OTG PHY * 0b0..The voltage on USB_OTG*_VBUS is below the OTG Device Session Valid threshold * 0b1..The voltage on USB_OTG*_VBUS is above the OTG Device Session Valid threshold */ #define USBNC_PHY_STATUS_SESS_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_SESS_VLD_SHIFT)) & USBNC_PHY_STATUS_SESS_VLD_MASK) #define USBNC_PHY_STATUS_VBUS_VLD_MASK (0x8U) #define USBNC_PHY_STATUS_VBUS_VLD_SHIFT (3U) /*! VBUS_VLD - VBUS Valid Indicator from USB OTG PHY * 0b0..The voltage on USB_OTG*_VBUS is below the VBUS Valid threshold * 0b1..The voltage on USB_OTG*_VBUS is above the VBUS Valid threshold */ #define USBNC_PHY_STATUS_VBUS_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_VBUS_VLD_SHIFT)) & USBNC_PHY_STATUS_VBUS_VLD_MASK) #define USBNC_PHY_STATUS_ID_DIG_MASK (0x10U) #define USBNC_PHY_STATUS_ID_DIG_SHIFT (4U) /*! ID_DIG - Micro- or Mini- A/B Plug Indicator * 0b0..The connnected plug is a Micro- or Mini-A plug * 0b1..The connnected plug is a Micro- or Mini-B plug */ #define USBNC_PHY_STATUS_ID_DIG(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_ID_DIG_SHIFT)) & USBNC_PHY_STATUS_ID_DIG_MASK) #define USBNC_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) #define USBNC_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) /*! HOST_DISCONNECT - Peripheral Disconnect Indicator * 0b0..Peripheral is connected * 0b1..No peripheral is connected */ #define USBNC_PHY_STATUS_HOST_DISCONNECT(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_HOST_DISCONNECT_SHIFT)) & USBNC_PHY_STATUS_HOST_DISCONNECT_MASK) #define USBNC_PHY_STATUS_RIDC0_MASK (0x1000000U) #define USBNC_PHY_STATUS_RIDC0_SHIFT (24U) /*! RIDC0 - ACA USB_OTG*_ID Pin Resistance Indicator * 0b0..ACA OTG_ID pin resistance is >= RID_B (min) and <= RID_GND max * 0b1..ACA OTG_ID pin resistance is >= RID_C (min) and <= RID_C max */ #define USBNC_PHY_STATUS_RIDC0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_RIDC0_SHIFT)) & USBNC_PHY_STATUS_RIDC0_MASK) #define USBNC_PHY_STATUS_RIDB0_MASK (0x2000000U) #define USBNC_PHY_STATUS_RIDB0_SHIFT (25U) /*! RIDB0 - ACA USB_OTG*_ID Pin Resistance Indicator * 0b0..ACA OTG_ID pin resistance is >= RID_A (min) and <= RID_C max * 0b1..ACA OTG_ID pin resistance is >= RID_B (min) and <= RID_B max */ #define USBNC_PHY_STATUS_RIDB0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_RIDB0_SHIFT)) & USBNC_PHY_STATUS_RIDB0_MASK) #define USBNC_PHY_STATUS_RIDA0_MASK (0x4000000U) #define USBNC_PHY_STATUS_RIDA0_SHIFT (26U) /*! RIDA0 - ACA USB_OTG*_ID Pin Resistance Indicator * 0b0..ACA OTG_ID pin resistance is >= RID_FLOAT (min) and <= RID_B max * 0b1..ACA OTG_ID pin resistance is >= RID_A (min) and <= RID_A max */ #define USBNC_PHY_STATUS_RIDA0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_RIDA0_SHIFT)) & USBNC_PHY_STATUS_RIDA0_MASK) #define USBNC_PHY_STATUS_RIDGND0_MASK (0x8000000U) #define USBNC_PHY_STATUS_RIDGND0_SHIFT (27U) /*! RIDGND0 - ACA USB_OTG*_ID Pin Resistance Indicator * 0b0..ACA OTG_ID pin resistance is >= RID_C (min) * 0b1..ACA OTG_ID pin resistance is <= RID_GND (max) */ #define USBNC_PHY_STATUS_RIDGND0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_RIDGND0_SHIFT)) & USBNC_PHY_STATUS_RIDGND0_MASK) #define USBNC_PHY_STATUS_RIDFLOAT0_MASK (0x10000000U) #define USBNC_PHY_STATUS_RIDFLOAT0_SHIFT (28U) /*! RIDFLOAT0 - ACA USB_OTG*_ID Pin Resistance Indicator * 0b0..ACA OTG_ID pin resistance is <= RID_A (max) * 0b1..ACA OTG_ID pin resistance is >= RID_FLOAT (min) */ #define USBNC_PHY_STATUS_RIDFLOAT0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_RIDFLOAT0_SHIFT)) & USBNC_PHY_STATUS_RIDFLOAT0_MASK) #define USBNC_PHY_STATUS_CHRGDET_MASK (0x20000000U) #define USBNC_PHY_STATUS_CHRGDET_SHIFT (29U) /*! CHRGDET - Battery Charger Detection Output * 0b0..VD* < VDAT_REF * 0b1..VD* > VDAT_REF */ #define USBNC_PHY_STATUS_CHRGDET(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_CHRGDET_SHIFT)) & USBNC_PHY_STATUS_CHRGDET_MASK) #define USBNC_PHY_STATUS_ADPPRB0_MASK (0x40000000U) #define USBNC_PHY_STATUS_ADPPRB0_SHIFT (30U) /*! ADPPRB0 - ADP Probe Indicator * 0b0..The voltage on USB_OTG*_VBUS is below the ADP probing voltage * 0b1..The voltage on USB_OTG*_VBUS is above the ADP probing voltage */ #define USBNC_PHY_STATUS_ADPPRB0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_ADPPRB0_SHIFT)) & USBNC_PHY_STATUS_ADPPRB0_MASK) #define USBNC_PHY_STATUS_ADPSNS0_MASK (0x80000000U) #define USBNC_PHY_STATUS_ADPSNS0_SHIFT (31U) /*! ADPSNS0 - ADP Sense Indicator * 0b0..The voltage on USB_OTG*_VBUS is below the ADP sensing voltage * 0b1..The voltage on USB_OTG*_VBUS is above the ADP sensing voltage */ #define USBNC_PHY_STATUS_ADPSNS0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_PHY_STATUS_ADPSNS0_SHIFT)) & USBNC_PHY_STATUS_ADPSNS0_MASK) /*! @} */ /*! @name ADP_CFG1 - */ /*! @{ */ #define USBNC_ADP_CFG1_ADP_WAIT_MASK (0x3FFFFU) #define USBNC_ADP_CFG1_ADP_WAIT_SHIFT (0U) /*! ADP_WAIT * 0b001100000000000000..Default */ #define USBNC_ADP_CFG1_ADP_WAIT(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_WAIT_SHIFT)) & USBNC_ADP_CFG1_ADP_WAIT_MASK) #define USBNC_ADP_CFG1_TIMER_EN_MASK (0x100000U) #define USBNC_ADP_CFG1_TIMER_EN_SHIFT (20U) /*! TIMER_EN - ADP Timer Test Enable * 0b0..Default */ #define USBNC_ADP_CFG1_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_TIMER_EN_SHIFT)) & USBNC_ADP_CFG1_TIMER_EN_MASK) #define USBNC_ADP_CFG1_ADP_SNS_INT_EN_MASK (0x200000U) #define USBNC_ADP_CFG1_ADP_SNS_INT_EN_SHIFT (21U) /*! ADP_SNS_INT_EN - ADP Sense Interrupt Enable * 0b0..Default */ #define USBNC_ADP_CFG1_ADP_SNS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_SNS_INT_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_SNS_INT_EN_MASK) #define USBNC_ADP_CFG1_ADP_PRB_INT_EN_MASK (0x400000U) #define USBNC_ADP_CFG1_ADP_PRB_INT_EN_SHIFT (22U) /*! ADP_PRB_INT_EN * 0b0..Default */ #define USBNC_ADP_CFG1_ADP_PRB_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_PRB_INT_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_PRB_INT_EN_MASK) #define USBNC_ADP_CFG1_ADP_PRB_EN_MASK (0x800000U) #define USBNC_ADP_CFG1_ADP_PRB_EN_SHIFT (23U) /*! ADP_PRB_EN * 0b0..Default */ #define USBNC_ADP_CFG1_ADP_PRB_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_PRB_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_PRB_EN_MASK) /*! @} */ /*! @name ADP_CFG2 - */ /*! @{ */ #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK (0x7FU) #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT (0U) /*! ADP_CHRG_DELTA * 0b0010000..Default */ #define USBNC_ADP_CFG2_ADP_CHRG_DELTA(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK) #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK (0x80U) #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT (7U) /*! ADP_CHRG_SWCMP * 0b0..Default */ #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK) #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK (0xFF00U) #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT (8U) /*! ADP_CHRG_SWTIME * 0b01000000..Default */ #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK) #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK (0xFF0000U) #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT (16U) /*! ADP_DISCHG_TIME - ADP Discharge time * 0b01000110..Default */ #define USBNC_ADP_CFG2_ADP_DISCHG_TIME(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT)) & USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK) /*! @} */ /*! @name ADP_STATUS - */ /*! @{ */ #define USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK (0xFFU) #define USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT (0U) /*! ADP_PRB_TIMR - ADP Probe Time * 0b00000000..Default */ #define USBNC_ADP_STATUS_ADP_PRB_TIMR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT)) & USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK) #define USBNC_ADP_STATUS_ADP_CNT_MASK (0x3FFFF00U) #define USBNC_ADP_STATUS_ADP_CNT_SHIFT (8U) /*! ADP_CNT - ADP Internal 18-bit Counter */ #define USBNC_ADP_STATUS_ADP_CNT(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_CNT_SHIFT)) & USBNC_ADP_STATUS_ADP_CNT_MASK) #define USBNC_ADP_STATUS_ADP_SNS_INT_MASK (0x4000000U) #define USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT (26U) /*! ADP_SNS_INT - ADP Sense Interrupt Status * 0b0..Default */ #define USBNC_ADP_STATUS_ADP_SNS_INT(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT)) & USBNC_ADP_STATUS_ADP_SNS_INT_MASK) #define USBNC_ADP_STATUS_ADP_PRB_INT_MASK (0x8000000U) #define USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT (27U) /*! ADP_PRB_INT - ADP Probe Interrupt Status * 0b0..Default */ #define USBNC_ADP_STATUS_ADP_PRB_INT(x) (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT)) & USBNC_ADP_STATUS_ADP_PRB_INT_MASK) /*! @} */ /*! * @} */ /* end of group USBNC_Register_Masks */ /* USBNC - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__USBNC base address */ #define CONNECTIVITY__USBNC_BASE (0x5B0D0000u) /** Peripheral CONNECTIVITY__USBNC base pointer */ #define CONNECTIVITY__USBNC ((USBNC_Type *)CONNECTIVITY__USBNC_BASE) /** Array initializer of USBNC peripheral base addresses */ #define USBNC_BASE_ADDRS { CONNECTIVITY__USBNC_BASE } /** Array initializer of USBNC peripheral base pointers */ #define USBNC_BASE_PTRS { CONNECTIVITY__USBNC } /*! * @} */ /* end of group USBNC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBPHY Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer * @{ */ /** USBPHY - Register Layout Typedef */ typedef struct { __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ uint8_t RESERVED_0[12]; __IO uint32_t DEBUG0; /**< USB PHY Debug Register 0, offset: 0x50 */ __IO uint32_t DEBUG0_SET; /**< USB PHY Debug Register 0, offset: 0x54 */ __IO uint32_t DEBUG0_CLR; /**< USB PHY Debug Register 0, offset: 0x58 */ __IO uint32_t DEBUG0_TOG; /**< USB PHY Debug Register 0, offset: 0x5C */ uint8_t RESERVED_1[16]; __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ uint8_t RESERVED_2[28]; __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ uint8_t RESERVED_3[16]; __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */ uint8_t RESERVED_4[12]; __IO uint32_t USB1_CHRG_DETECT; /**< USB PHY Charger Detect Control Register, offset: 0xE0 */ __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB PHY Charger Detect Control Register, offset: 0xE4 */ __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB PHY Charger Detect Control Register, offset: 0xE8 */ __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB PHY Charger Detect Control Register, offset: 0xEC */ __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */ uint8_t RESERVED_5[12]; __IO uint32_t ANACTRL; /**< USB PHY Analog Control Register, offset: 0x100 */ __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ __IO uint32_t USB1_LOOPBACK; /**< USB PHY Loopback Control/Status Register, offset: 0x110 */ __IO uint32_t USB1_LOOPBACK_SET; /**< USB PHY Loopback Control/Status Register, offset: 0x114 */ __IO uint32_t USB1_LOOPBACK_CLR; /**< USB PHY Loopback Control/Status Register, offset: 0x118 */ __IO uint32_t USB1_LOOPBACK_TOG; /**< USB PHY Loopback Control/Status Register, offset: 0x11C */ __IO uint32_t USB1_LOOPBACK_HSFSCNT; /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */ __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET; /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */ __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR; /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */ __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG; /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */ __IO uint32_t TRIM_OVERRIDE_EN; /**< USB PHY Trim Override Enable Register, offset: 0x130 */ __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< USB PHY Trim Override Enable Register, offset: 0x134 */ __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< USB PHY Trim Override Enable Register, offset: 0x138 */ __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< USB PHY Trim Override Enable Register, offset: 0x13C */ } USBPHY_Type; /* ---------------------------------------------------------------------------- -- USBPHY Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBPHY_Register_Masks USBPHY Register Masks * @{ */ /*! @name PWD - USB PHY Power-Down Register */ /*! @{ */ #define USBPHY_PWD_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TXPWDFS_SHIFT (10U) /*! TXPWDFS * 0b0..Normal operation. * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output */ #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS * 0b0..Normal operation * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB * is in suspend mode. This effectively powers down the entire USB transmit path */ #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I * 0b0..Normal operation. * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) #define USBPHY_PWD_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_RXPWDENV_SHIFT (17U) /*! RXPWDENV * 0b0..Normal operation. * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 * 0b0..Normal operation * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF * 0b0..Normal operation. * 0b1..Power-down the USB high-speed differential receiver */ #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) #define USBPHY_PWD_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_RXPWDRX_SHIFT (20U) /*! RXPWDRX * 0b0..Normal operation * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver */ #define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) /*! @} */ /*! @name PWD_SET - USB PHY Power-Down Register */ /*! @{ */ #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) /*! TXPWDFS * 0b0..Normal operation. * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output */ #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS * 0b0..Normal operation * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB * is in suspend mode. This effectively powers down the entire USB transmit path */ #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I * 0b0..Normal operation. * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) /*! RXPWDENV * 0b0..Normal operation. * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 * 0b0..Normal operation * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF * 0b0..Normal operation. * 0b1..Power-down the USB high-speed differential receiver */ #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) /*! RXPWDRX * 0b0..Normal operation * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver */ #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) /*! @} */ /*! @name PWD_CLR - USB PHY Power-Down Register */ /*! @{ */ #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) /*! TXPWDFS * 0b0..Normal operation. * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output */ #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS * 0b0..Normal operation * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB * is in suspend mode. This effectively powers down the entire USB transmit path */ #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I * 0b0..Normal operation. * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) /*! RXPWDENV * 0b0..Normal operation. * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 * 0b0..Normal operation * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF * 0b0..Normal operation. * 0b1..Power-down the USB high-speed differential receiver */ #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) /*! RXPWDRX * 0b0..Normal operation * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver */ #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) /*! @} */ /*! @name PWD_TOG - USB PHY Power-Down Register */ /*! @{ */ #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) /*! TXPWDFS * 0b0..Normal operation. * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output */ #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS * 0b0..Normal operation * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB * is in suspend mode. This effectively powers down the entire USB transmit path */ #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I * 0b0..Normal operation. * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) /*! RXPWDENV * 0b0..Normal operation. * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 * 0b0..Normal operation * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF * 0b0..Normal operation. * 0b1..Power-down the USB high-speed differential receiver */ #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) /*! RXPWDRX * 0b0..Normal operation * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver */ #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) /*! @} */ /*! @name TX - USB PHY Transmitter Control Register */ /*! @{ */ #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) /*! D_CAL * 0b0000..Maximum current, approximately 19% above nominal. * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) #define USBPHY_TX_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_TXCAL45DM_SHIFT (8U) /*! TXCAL45DM * 0b0000..+19.95% * 0b0001..+17.35% * 0b0010..+14.85% * 0b0011..+12.46% * 0b0100..+9.07% * 0b0101..+5.87% * 0b0110..+2.85% * 0b0111..0% * 0b1000..-2.70% * 0b1001..-5.25% * 0b1010..-7.67% * 0b1011..-9.98% * 0b1100..-12.17% * 0b1101..-14.25% * 0b1110..-18.14% * 0b1111..-21.68% */ #define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) #define USBPHY_TX_TXENCAL45DM_MASK (0x2000U) #define USBPHY_TX_TXENCAL45DM_SHIFT (13U) #define USBPHY_TX_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DM_SHIFT)) & USBPHY_TX_TXENCAL45DM_MASK) #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TXCAL45DP_SHIFT (16U) /*! TXCAL45DP * 0b0000..+19.95% * 0b0001..+17.35% * 0b0010..+14.85% * 0b0011..+12.46% * 0b0100..+9.07% * 0b0101..+5.87% * 0b0110..+2.85% * 0b0111..0% * 0b1000..-2.70% * 0b1001..-5.25% * 0b1010..-7.67% * 0b1011..-9.98% * 0b1100..-12.17% * 0b1101..-14.25% * 0b1110..-18.14% * 0b1111..-21.68% */ #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) #define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) /*! @} */ /*! @name TX_SET - USB PHY Transmitter Control Register */ /*! @{ */ #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) /*! D_CAL * 0b0000..Maximum current, approximately 19% above nominal. * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) #define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) /*! TXCAL45DM * 0b0000..+19.95% * 0b0001..+17.35% * 0b0010..+14.85% * 0b0011..+12.46% * 0b0100..+9.07% * 0b0101..+5.87% * 0b0110..+2.85% * 0b0111..0% * 0b1000..-2.70% * 0b1001..-5.25% * 0b1010..-7.67% * 0b1011..-9.98% * 0b1100..-12.17% * 0b1101..-14.25% * 0b1110..-18.14% * 0b1111..-21.68% */ #define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) #define USBPHY_TX_SET_TXENCAL45DM_MASK (0x2000U) #define USBPHY_TX_SET_TXENCAL45DM_SHIFT (13U) #define USBPHY_TX_SET_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DM_SHIFT)) & USBPHY_TX_SET_TXENCAL45DM_MASK) #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) /*! TXCAL45DP * 0b0000..+19.95% * 0b0001..+17.35% * 0b0010..+14.85% * 0b0011..+12.46% * 0b0100..+9.07% * 0b0101..+5.87% * 0b0110..+2.85% * 0b0111..0% * 0b1000..-2.70% * 0b1001..-5.25% * 0b1010..-7.67% * 0b1011..-9.98% * 0b1100..-12.17% * 0b1101..-14.25% * 0b1110..-18.14% * 0b1111..-21.68% */ #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) #define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) /*! @} */ /*! @name TX_CLR - USB PHY Transmitter Control Register */ /*! @{ */ #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) /*! D_CAL * 0b0000..Maximum current, approximately 19% above nominal. * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) #define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) /*! TXCAL45DM * 0b0000..+19.95% * 0b0001..+17.35% * 0b0010..+14.85% * 0b0011..+12.46% * 0b0100..+9.07% * 0b0101..+5.87% * 0b0110..+2.85% * 0b0111..0% * 0b1000..-2.70% * 0b1001..-5.25% * 0b1010..-7.67% * 0b1011..-9.98% * 0b1100..-12.17% * 0b1101..-14.25% * 0b1110..-18.14% * 0b1111..-21.68% */ #define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) #define USBPHY_TX_CLR_TXENCAL45DM_MASK (0x2000U) #define USBPHY_TX_CLR_TXENCAL45DM_SHIFT (13U) #define USBPHY_TX_CLR_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DM_MASK) #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) /*! TXCAL45DP * 0b0000..+19.95% * 0b0001..+17.35% * 0b0010..+14.85% * 0b0011..+12.46% * 0b0100..+9.07% * 0b0101..+5.87% * 0b0110..+2.85% * 0b0111..0% * 0b1000..-2.70% * 0b1001..-5.25% * 0b1010..-7.67% * 0b1011..-9.98% * 0b1100..-12.17% * 0b1101..-14.25% * 0b1110..-18.14% * 0b1111..-21.68% */ #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) #define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) /*! @} */ /*! @name TX_TOG - USB PHY Transmitter Control Register */ /*! @{ */ #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) /*! D_CAL * 0b0000..Maximum current, approximately 19% above nominal. * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) #define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) /*! TXCAL45DM * 0b0000..+19.95% * 0b0001..+17.35% * 0b0010..+14.85% * 0b0011..+12.46% * 0b0100..+9.07% * 0b0101..+5.87% * 0b0110..+2.85% * 0b0111..0% * 0b1000..-2.70% * 0b1001..-5.25% * 0b1010..-7.67% * 0b1011..-9.98% * 0b1100..-12.17% * 0b1101..-14.25% * 0b1110..-18.14% * 0b1111..-21.68% */ #define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) #define USBPHY_TX_TOG_TXENCAL45DM_MASK (0x2000U) #define USBPHY_TX_TOG_TXENCAL45DM_SHIFT (13U) #define USBPHY_TX_TOG_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DM_MASK) #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) /*! TXCAL45DP * 0b0000..+19.95% * 0b0001..+17.35% * 0b0010..+14.85% * 0b0011..+12.46% * 0b0100..+9.07% * 0b0101..+5.87% * 0b0110..+2.85% * 0b0111..0% * 0b1000..-2.70% * 0b1001..-5.25% * 0b1010..-7.67% * 0b1011..-9.98% * 0b1100..-12.17% * 0b1101..-14.25% * 0b1110..-18.14% * 0b1111..-21.68% */ #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) #define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) /*! @} */ /*! @name RX - USB PHY Receiver Control Register */ /*! @{ */ #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) /*! ENVADJ * 0b000..Trip-Level Voltage is 0.1000 V * 0b001..Trip-Level Voltage is 0.1125 V * 0b010..Trip-Level Voltage is 0.1250 V * 0b011..Trip-Level Voltage is 0.0875 V * 0b1xx..Reserved */ #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) #define USBPHY_RX_DISCONADJ_MASK (0x70U) #define USBPHY_RX_DISCONADJ_SHIFT (4U) /*! DISCONADJ * 0b000..Trip-Level Voltage is 0.56875 V * 0b001..Trip-Level Voltage is 0.55000 V * 0b010..Trip-Level Voltage is 0.58125 V * 0b011..Trip-Level Voltage is 0.60000 V * 0b1xx..Reserved */ #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) #define USBPHY_RX_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS * 0b0..Normal operation. * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver */ #define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) /*! @} */ /*! @name RX_SET - USB PHY Receiver Control Register */ /*! @{ */ #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) /*! ENVADJ * 0b000..Trip-Level Voltage is 0.1000 V * 0b001..Trip-Level Voltage is 0.1125 V * 0b010..Trip-Level Voltage is 0.1250 V * 0b011..Trip-Level Voltage is 0.0875 V * 0b1xx..Reserved */ #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) /*! DISCONADJ * 0b000..Trip-Level Voltage is 0.56875 V * 0b001..Trip-Level Voltage is 0.55000 V * 0b010..Trip-Level Voltage is 0.58125 V * 0b011..Trip-Level Voltage is 0.60000 V * 0b1xx..Reserved */ #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) #define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS * 0b0..Normal operation. * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver */ #define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) /*! @} */ /*! @name RX_CLR - USB PHY Receiver Control Register */ /*! @{ */ #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) /*! ENVADJ * 0b000..Trip-Level Voltage is 0.1000 V * 0b001..Trip-Level Voltage is 0.1125 V * 0b010..Trip-Level Voltage is 0.1250 V * 0b011..Trip-Level Voltage is 0.0875 V * 0b1xx..Reserved */ #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) /*! DISCONADJ * 0b000..Trip-Level Voltage is 0.56875 V * 0b001..Trip-Level Voltage is 0.55000 V * 0b010..Trip-Level Voltage is 0.58125 V * 0b011..Trip-Level Voltage is 0.60000 V * 0b1xx..Reserved */ #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) #define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS * 0b0..Normal operation. * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver */ #define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) /*! @} */ /*! @name RX_TOG - USB PHY Receiver Control Register */ /*! @{ */ #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) /*! ENVADJ * 0b000..Trip-Level Voltage is 0.1000 V * 0b001..Trip-Level Voltage is 0.1125 V * 0b010..Trip-Level Voltage is 0.1250 V * 0b011..Trip-Level Voltage is 0.0875 V * 0b1xx..Reserved */ #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) /*! DISCONADJ * 0b000..Trip-Level Voltage is 0.56875 V * 0b001..Trip-Level Voltage is 0.55000 V * 0b010..Trip-Level Voltage is 0.58125 V * 0b011..Trip-Level Voltage is 0.60000 V * 0b1xx..Reserved */ #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) #define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS * 0b0..Normal operation. * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver */ #define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) /*! @} */ /*! @name CTRL - USB PHY General Control Register */ /*! @{ */ #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) #define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) /*! @} */ /*! @name CTRL_SET - USB PHY General Control Register */ /*! @{ */ #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) #define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL_CLR - USB PHY General Control Register */ /*! @{ */ #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL_TOG - USB PHY General Control Register */ /*! @{ */ #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) /*! @} */ /*! @name STATUS - USB PHY Status Register */ /*! @{ */ #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) /*! HOSTDISCONDETECT_STATUS * 0b0..USB cable disconnect has not been detected at the local host * 0b1..USB cable disconnect has been detected at the local host */ #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) /*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection * 0b0..No attachment to a USB host is detected * 0b1..Cable attachment to a USB host is detected */ #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) /*! @} */ /*! @name DEBUG0 - USB PHY Debug Register 0 */ /*! @{ */ #define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U) #define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U) #define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK) #define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) #define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) #define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) #define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U) #define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U) #define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK) #define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U) #define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U) #define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK) #define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U) #define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U) #define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK) #define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U) #define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U) #define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK) #define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U) #define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U) #define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK) #define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U) #define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U) #define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK) #define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U) #define USBPHY_DEBUG0_CLKGATE_SHIFT (30U) #define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK) /*! @} */ /*! @name DEBUG0_SET - USB PHY Debug Register 0 */ /*! @{ */ #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) #define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) #define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK) #define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) #define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) #define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) #define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U) #define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U) #define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK) #define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U) #define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U) #define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK) #define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) #define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U) #define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK) #define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U) #define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U) #define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK) #define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) #define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U) #define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK) #define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) #define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U) #define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK) #define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U) #define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U) #define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK) /*! @} */ /*! @name DEBUG0_CLR - USB PHY Debug Register 0 */ /*! @{ */ #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) #define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) #define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK) #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) #define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) #define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) #define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U) #define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U) #define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK) #define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U) #define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U) #define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK) #define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) #define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U) #define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK) #define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U) #define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U) #define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK) #define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) #define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U) #define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK) #define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) #define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U) #define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK) #define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U) #define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U) #define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK) /*! @} */ /*! @name DEBUG0_TOG - USB PHY Debug Register 0 */ /*! @{ */ #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) #define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) #define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) #define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) #define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK) #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) #define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) #define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) #define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) #define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U) #define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U) #define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK) #define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U) #define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U) #define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK) #define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) #define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U) #define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK) #define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U) #define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U) #define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK) #define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) #define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U) #define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK) #define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) #define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U) #define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK) #define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U) #define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U) #define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK) /*! @} */ /*! @name DEBUG1 - UTMI Debug Status Register 1 */ /*! @{ */ #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) /*! ENTAILADJVD * 0b00..Delay is nominal * 0b01..Delay is +20% * 0b10..Delay is -20% * 0b11..Delay is -40% */ #define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */ #define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK) /*! @} */ /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ /*! @{ */ #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) /*! ENTAILADJVD * 0b00..Delay is nominal * 0b01..Delay is +20% * 0b10..Delay is -20% * 0b11..Delay is -40% */ #define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */ #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK) /*! @} */ /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ /*! @{ */ #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) /*! ENTAILADJVD * 0b00..Delay is nominal * 0b01..Delay is +20% * 0b10..Delay is -20% * 0b11..Delay is -40% */ #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */ #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK) /*! @} */ /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ /*! @{ */ #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) /*! ENTAILADJVD * 0b00..Delay is nominal * 0b01..Delay is +20% * 0b10..Delay is -20% * 0b11..Delay is -40% */ #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */ #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK) /*! @} */ /*! @name VERSION - UTMI RTL Version */ /*! @{ */ #define USBPHY_VERSION_STEP_MASK (0xFFFFU) #define USBPHY_VERSION_STEP_SHIFT (0U) #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) #define USBPHY_VERSION_MINOR_MASK (0xFF0000U) #define USBPHY_VERSION_MINOR_SHIFT (16U) #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) #define USBPHY_VERSION_MAJOR_SHIFT (24U) #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) /*! @} */ /*! @name PLL_SIC - USB PHY PLL Control/Status Register */ /*! @{ */ #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) #define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) #define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL * 0b0..Selects PLL_POWER to control the reference bias * 0b1..Selects REFBIAS_PWD to control the reference bias. */ #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL * 0b000..Divide by 13 * 0b001..Divide by 15 * 0b010..Divide by 16 * 0b011..Divide by 20 * 0b100..Divide by 22 * 0b101..Divide by 25 * 0b110..Divide by 30 * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK * 0b0..PLL is not currently locked * 0b1..PLL is currently locked */ #define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ /*! @{ */ #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL * 0b0..Selects PLL_POWER to control the reference bias * 0b1..Selects REFBIAS_PWD to control the reference bias. */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL * 0b000..Divide by 13 * 0b001..Divide by 15 * 0b010..Divide by 16 * 0b011..Divide by 20 * 0b100..Divide by 22 * 0b101..Divide by 25 * 0b110..Divide by 30 * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK * 0b0..PLL is not currently locked * 0b1..PLL is currently locked */ #define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ /*! @{ */ #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL * 0b0..Selects PLL_POWER to control the reference bias * 0b1..Selects REFBIAS_PWD to control the reference bias. */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL * 0b000..Divide by 13 * 0b001..Divide by 15 * 0b010..Divide by 16 * 0b011..Divide by 20 * 0b100..Divide by 22 * 0b101..Divide by 25 * 0b110..Divide by 30 * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK * 0b0..PLL is not currently locked * 0b1..PLL is currently locked */ #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ /*! @{ */ #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL * 0b0..Selects PLL_POWER to control the reference bias * 0b1..Selects REFBIAS_PWD to control the reference bias. */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL * 0b000..Divide by 13 * 0b001..Divide by 15 * 0b010..Divide by 16 * 0b011..Divide by 20 * 0b100..Divide by 22 * 0b101..Divide by 25 * 0b110..Divide by 30 * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK * 0b0..PLL is not currently locked * 0b1..PLL is currently locked */ #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V * 0b100..4.4 V (Default) * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b01..Use the Session Valid comparator results for signal reported to the USB controller * 0b10..Use the Session Valid comparator results for signal reported to the USB controller * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U) #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator * 0b0..Powers down the VBUS_VALID comparator * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor * 0b0..VBUS discharge resistor is disabled (Default) * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V * 0b100..4.4 V (Default) * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b01..Use the Session Valid comparator results for signal reported to the USB controller * 0b10..Use the Session Valid comparator results for signal reported to the USB controller * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U) #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator * 0b0..Powers down the VBUS_VALID comparator * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor * 0b0..VBUS discharge resistor is disabled (Default) * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V * 0b100..4.4 V (Default) * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b01..Use the Session Valid comparator results for signal reported to the USB controller * 0b10..Use the Session Valid comparator results for signal reported to the USB controller * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U) #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator * 0b0..Powers down the VBUS_VALID comparator * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor * 0b0..VBUS discharge resistor is disabled (Default) * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ /*! @{ */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V * 0b011..4.3 V * 0b100..4.4 V (Default) * 0b101..4.5 V * 0b110..4.6 V * 0b111..4.7 V */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) * 0b01..Use the Session Valid comparator results for signal reported to the USB controller * 0b10..Use the Session Valid comparator results for signal reported to the USB controller * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U) #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator * 0b0..Powers down the VBUS_VALID comparator * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor * 0b0..VBUS discharge resistor is disabled (Default) * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ /*! @{ */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) /*! SESSEND - Session End indicator * 0b0..The VBUS voltage is above the Session Valid threshold * 0b1..The VBUS voltage is below the Session Valid threshold */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) /*! BVALID - B-Device Session Valid status * 0b0..The VBUS voltage is below the Session Valid threshold * 0b1..The VBUS voltage is above the Session Valid threshold */ #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) /*! AVALID - A-Device Session Valid status * 0b0..The VBUS voltage is below the Session Valid threshold * 0b1..The VBUS voltage is above the Session Valid threshold */ #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) /*! VBUS_VALID - VBUS voltage status * 0b0..VBUS is below the comparator threshold * 0b1..VBUS is above the comparator threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) /*! VBUS_VALID_3V - VBUS_VALID_3V detector status * 0b0..VBUS voltage is below VBUS_VALID_3V threshold * 0b1..VBUS voltage is above VBUS_VALID_3V threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U) #define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U) /*! BGR_IBIAS - USB charge detector bias current reference * 0b0..Bias current is derived from the USB PHY internal current generator. * 0b1..Bias current is derived from the reference generator of the bandgap. */ #define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U) #define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U) /*! BGR_IBIAS - USB charge detector bias current reference * 0b0..Bias current is derived from the USB PHY internal current generator. * 0b1..Bias current is derived from the reference generator of the bandgap. */ #define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U) #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U) /*! BGR_IBIAS - USB charge detector bias current reference * 0b0..Bias current is derived from the USB PHY internal current generator. * 0b1..Bias current is derived from the reference generator of the bandgap. */ #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */ /*! @{ */ #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U) #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U) /*! BGR_IBIAS - USB charge detector bias current reference * 0b0..Bias current is derived from the USB PHY internal current generator. * 0b1..Bias current is derived from the reference generator of the bandgap. */ #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */ /*! @{ */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) /*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output * 0b0..No USB cable attachment has been detected * 0b1..A USB cable attachment between the device and host has been detected */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) /*! CHRG_DETECTED - Battery Charging Primary Detection phase output * 0b0..Standard Downstream Port (SDP) has been detected * 0b1..Charging Port has been detected */ #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) /*! DM_STATE * 0b0..USB_DM pin voltage is < 0.8V * 0b1..USB_DM pin voltage is > 2.0V */ #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) /*! DP_STATE * 0b0..USB_DP pin voltage is < 0.8V * 0b1..USB_DP pin voltage is > 2.0V */ #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) /*! SECDET_DCP - Battery Charging Secondary Detection phase output * 0b0..Charging Downstream Port (CDP) has been detected * 0b1..Downstream Charging Port (DCP) has been detected */ #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) /*! @} */ /*! @name ANACTRL - USB PHY Analog Control Register */ /*! @{ */ #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. */ #define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_SET - USB PHY Analog Control Register */ /*! @{ */ #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. */ #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_CLR - USB PHY Analog Control Register */ /*! @{ */ #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. */ #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_TOG - USB PHY Analog Control Register */ /*! @{ */ #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. */ #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) /*! @} */ /*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U) #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK) #define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK) #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK) #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK) #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */ /*! @{ */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */ /*! @{ */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK) /*! @} */ /*! * @} */ /* end of group USBPHY_Register_Masks */ /* USBPHY - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__USBPHY base address */ #define CONNECTIVITY__USBPHY_BASE (0x5B100000u) /** Peripheral CONNECTIVITY__USBPHY base pointer */ #define CONNECTIVITY__USBPHY ((USBPHY_Type *)CONNECTIVITY__USBPHY_BASE) /** Array initializer of USBPHY peripheral base addresses */ #define USBPHY_BASE_ADDRS { CONNECTIVITY__USBPHY_BASE } /** Array initializer of USBPHY peripheral base pointers */ #define USBPHY_BASE_PTRS { CONNECTIVITY__USBPHY } /*! * @} */ /* end of group USBPHY_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USDHC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer * @{ */ /** USDHC - Register Layout Typedef */ typedef struct { __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ uint8_t RESERVED_0[4]; __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */ __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ uint8_t RESERVED_1[4]; __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ uint8_t RESERVED_2[4]; __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL control, offset: 0x70 */ __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL status, offset: 0x74 */ uint8_t RESERVED_3[72]; __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ __IO uint32_t MMC_BOOT; /**< MMC Boot, offset: 0xC4 */ __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ __IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */ uint8_t RESERVED_4[48]; uint32_t CQE; /**< Command Queue, offset: 0x100 */ } USDHC_Type; /* ---------------------------------------------------------------------------- -- USDHC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USDHC_Register_Masks USDHC Register Masks * @{ */ /*! @name DS_ADDR - DMA System Address */ /*! @{ */ #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) /*! DS_ADDR - System address */ #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) /*! @} */ /*! @name BLK_ATT - Block Attributes */ /*! @{ */ #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) /*! BLKSIZE - Transfer block size * 0b1000000000000..4096 bytes * 0b0100000000000..2048 bytes * 0b0001000000000..512 bytes * 0b0000111111111..511 bytes * 0b0000000000100..4 bytes * 0b0000000000011..3 bytes * 0b0000000000010..2 bytes * 0b0000000000001..1 byte * 0b0000000000000..No data transfer */ #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) /*! BLKCNT - Blocks count for current transfer * 0b1111111111111111..65535 blocks * 0b0000000000000010..2 blocks * 0b0000000000000001..1 block * 0b0000000000000000..Stop count */ #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) /*! @} */ /*! @name CMD_ARG - Command Argument */ /*! @{ */ #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) #define USDHC_CMD_ARG_CMDARG_SHIFT (0U) /*! CMDARG - Command argument */ #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) /*! @} */ /*! @name CMD_XFR_TYP - Command Transfer Type */ /*! @{ */ #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) /*! RSPTYP - Response type select * 0b00..No response * 0b01..Response length 136 * 0b10..Response length 48 * 0b11..Response length 48, check busy after response */ #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) /*! CCCEN - Command CRC check enable * 0b1..Enables command CRC check * 0b0..Disables command CRC check */ #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) /*! CICEN - Command index check enable * 0b1..Enables command index check * 0b0..Disable command index check */ #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) /*! DPSEL - Data present select * 0b1..Data present * 0b0..No data present */ #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) /*! CMDTYP - Command type * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR * 0b10..Resume CMD52 for writing function select in CCCR * 0b01..Suspend CMD52 for writing bus suspend in CCCR * 0b00..Normal other commands */ #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) /*! CMDINX - Command index */ #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) /*! @} */ /*! @name CMD_RSP0 - Command Response0 */ /*! @{ */ #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) /*! CMDRSP0 - Command response 0 */ #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) /*! @} */ /*! @name CMD_RSP1 - Command Response1 */ /*! @{ */ #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) /*! CMDRSP1 - Command response 1 */ #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) /*! @} */ /*! @name CMD_RSP2 - Command Response2 */ /*! @{ */ #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) /*! CMDRSP2 - Command response 2 */ #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) /*! @} */ /*! @name CMD_RSP3 - Command Response3 */ /*! @{ */ #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) /*! CMDRSP3 - Command response 3 */ #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) /*! @} */ /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ /*! @{ */ #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) /*! DATCONT - Data content */ #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) /*! @} */ /*! @name PRES_STATE - Present State */ /*! @{ */ #define USDHC_PRES_STATE_CIHB_MASK (0x1U) #define USDHC_PRES_STATE_CIHB_SHIFT (0U) /*! CIHB - Command inhibit (CMD) * 0b1..Cannot issue command * 0b0..Can issue command using only CMD line */ #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) #define USDHC_PRES_STATE_CDIHB_MASK (0x2U) #define USDHC_PRES_STATE_CDIHB_SHIFT (1U) /*! CDIHB - Command inhibit (DATA) * 0b1..Cannot issue command that uses the DATA line * 0b0..Can issue command that uses the DATA line */ #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) #define USDHC_PRES_STATE_DLA_MASK (0x4U) #define USDHC_PRES_STATE_DLA_SHIFT (2U) /*! DLA - Data line active * 0b1..DATA line active * 0b0..DATA line inactive */ #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) #define USDHC_PRES_STATE_SDSTB_MASK (0x8U) #define USDHC_PRES_STATE_SDSTB_SHIFT (3U) /*! SDSTB - SD clock stable * 0b1..Clock is stable. * 0b0..Clock is changing frequency and not stable. */ #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) #define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) #define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) /*! IPGOFF - Peripheral clock gated off internally * 0b1..Peripheral clock is gated off. * 0b0..Peripheral clock is active. */ #define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) #define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) #define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) /*! HCKOFF - HCLK gated off internally * 0b1..HCLK is gated off. * 0b0..HCLK is active. */ #define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) #define USDHC_PRES_STATE_PEROFF_MASK (0x40U) #define USDHC_PRES_STATE_PEROFF_SHIFT (6U) /*! PEROFF - IPG_PERCLK gated off internally * 0b1..IPG_PERCLK is gated off. * 0b0..IPG_PERCLK is active. */ #define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) #define USDHC_PRES_STATE_SDOFF_MASK (0x80U) #define USDHC_PRES_STATE_SDOFF_SHIFT (7U) /*! SDOFF - SD clock gated off internally * 0b1..SD clock is gated off. * 0b0..SD clock is active. */ #define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) #define USDHC_PRES_STATE_WTA_MASK (0x100U) #define USDHC_PRES_STATE_WTA_SHIFT (8U) /*! WTA - Write transfer active * 0b1..Transferring data * 0b0..No valid data */ #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) #define USDHC_PRES_STATE_RTA_MASK (0x200U) #define USDHC_PRES_STATE_RTA_SHIFT (9U) /*! RTA - Read transfer active * 0b1..Transferring data * 0b0..No valid data */ #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) #define USDHC_PRES_STATE_BWEN_MASK (0x400U) #define USDHC_PRES_STATE_BWEN_SHIFT (10U) /*! BWEN - Buffer write enable * 0b1..Write enable * 0b0..Write disable */ #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) #define USDHC_PRES_STATE_BREN_MASK (0x800U) #define USDHC_PRES_STATE_BREN_SHIFT (11U) /*! BREN - Buffer read enable * 0b1..Read enable * 0b0..Read disable */ #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) #define USDHC_PRES_STATE_RTR_MASK (0x1000U) #define USDHC_PRES_STATE_RTR_SHIFT (12U) /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) * 0b1..Sampling clock needs re-tuning * 0b0..Fixed or well tuned sampling clock */ #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) #define USDHC_PRES_STATE_TSCD_MASK (0x8000U) #define USDHC_PRES_STATE_TSCD_SHIFT (15U) /*! TSCD - Tape select change done * 0b1..Delay cell select change is finished. * 0b0..Delay cell select change is not finished. */ #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) #define USDHC_PRES_STATE_CINST_MASK (0x10000U) #define USDHC_PRES_STATE_CINST_SHIFT (16U) /*! CINST - Card inserted * 0b1..Card inserted * 0b0..Power on reset or no card */ #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) #define USDHC_PRES_STATE_CDPL_MASK (0x40000U) #define USDHC_PRES_STATE_CDPL_SHIFT (18U) /*! CDPL - Card detect pin level * 0b1..Card present (CD_B = 0) * 0b0..No card present (CD_B = 1) */ #define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) #define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) #define USDHC_PRES_STATE_WPSPL_SHIFT (19U) /*! WPSPL - Write protect switch pin level * 0b1..Write enabled (WP = 0) * 0b0..Write protected (WP = 1) */ #define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) #define USDHC_PRES_STATE_CLSL_MASK (0x800000U) #define USDHC_PRES_STATE_CLSL_SHIFT (23U) /*! CLSL - CMD line signal level */ #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) /*! DLSL - DATA[7:0] line signal level * 0b00000111..Data 7 line signal level * 0b00000110..Data 6 line signal level * 0b00000101..Data 5 line signal level * 0b00000100..Data 4 line signal level * 0b00000011..Data 3 line signal level * 0b00000010..Data 2 line signal level * 0b00000001..Data 1 line signal level * 0b00000000..Data 0 line signal level */ #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) /*! @} */ /*! @name PROT_CTRL - Protocol Control */ /*! @{ */ #define USDHC_PROT_CTRL_LCTL_MASK (0x1U) #define USDHC_PROT_CTRL_LCTL_SHIFT (0U) /*! LCTL - LED control * 0b1..LED on * 0b0..LED off */ #define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) #define USDHC_PROT_CTRL_DTW_MASK (0x6U) #define USDHC_PROT_CTRL_DTW_SHIFT (1U) /*! DTW - Data transfer width * 0b10..8-bit mode * 0b01..4-bit mode * 0b00..1-bit mode * 0b11..Reserved */ #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) #define USDHC_PROT_CTRL_D3CD_MASK (0x8U) #define USDHC_PROT_CTRL_D3CD_SHIFT (3U) /*! D3CD - DATA3 as card detection pin * 0b1..DATA3 as card detection pin * 0b0..DATA3 does not monitor card insertion */ #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) #define USDHC_PROT_CTRL_EMODE_MASK (0x30U) #define USDHC_PROT_CTRL_EMODE_SHIFT (4U) /*! EMODE - Endian mode * 0b00..Big endian mode * 0b01..Half word big endian mode * 0b10..Little endian mode * 0b11..Reserved */ #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) #define USDHC_PROT_CTRL_CDTL_MASK (0x40U) #define USDHC_PROT_CTRL_CDTL_SHIFT (6U) /*! CDTL - Card detect test level * 0b1..Card detect test level is 1, card inserted * 0b0..Card detect test level is 0, no card inserted */ #define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) #define USDHC_PROT_CTRL_CDSS_MASK (0x80U) #define USDHC_PROT_CTRL_CDSS_SHIFT (7U) /*! CDSS - Card detect signal selection * 0b1..Card detection test level is selected (for test purpose). * 0b0..Card detection level is selected (for normal purpose). */ #define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) /*! DMASEL - DMA select * 0b00..No DMA or simple DMA is selected. * 0b01..ADMA1 is selected. * 0b10..ADMA2 is selected. * 0b11..Reserved */ #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) /*! SABGREQ - Stop at block gap request * 0b1..Stop * 0b0..Transfer */ #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) #define USDHC_PROT_CTRL_CREQ_SHIFT (17U) /*! CREQ - Continue request * 0b1..Restart * 0b0..No effect */ #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) /*! RWCTL - Read wait control * 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set * 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set */ #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) #define USDHC_PROT_CTRL_IABG_MASK (0x80000U) #define USDHC_PROT_CTRL_IABG_SHIFT (19U) /*! IABG - Interrupt at block gap * 0b1..Enables interrupt at block gap * 0b0..Disables interrupt at block gap */ #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) /*! RD_DONE_NO_8CLK - Read performed number 8 clock */ #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) #define USDHC_PROT_CTRL_WECINT_SHIFT (24U) /*! WECINT - Wakeup event enable on card interrupt * 0b1..Enables wakeup event enable on card interrupt * 0b0..Disables wakeup event enable on card interrupt */ #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) #define USDHC_PROT_CTRL_WECINS_SHIFT (25U) /*! WECINS - Wakeup event enable on SD card insertion * 0b1..Enable wakeup event enable on SD card insertion * 0b0..Disable wakeup event enable on SD card insertion */ #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) #define USDHC_PROT_CTRL_WECRM_SHIFT (26U) /*! WECRM - Wakeup event enable on SD card removal * 0b1..Enables wakeup event enable on SD card removal * 0b0..Disables wakeup event enable on SD card removal */ #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) /*! NON_EXACT_BLK_RD - Non-exact block read * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. * 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read. */ #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) /*! @} */ /*! @name SYS_CTRL - System Control */ /*! @{ */ #define USDHC_SYS_CTRL_DVS_MASK (0xF0U) #define USDHC_SYS_CTRL_DVS_SHIFT (4U) /*! DVS - Divisor * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) /*! SDCLKFS - SDCLK frequency select */ #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) /*! DTOCV - Data timeout counter value * 0b1111..SDCLK x 2 29 * 0b1110..SDCLK x 2 28 * 0b1101..SDCLK x 2 27 * 0b1100..SDCLK x 2 26 * 0b1011..SDCLK x 2 25 * 0b1010..SDCLK x 2 24 * 0b1001..SDCLK x 2 23 * 0b1000..SDCLK x 2 22 * 0b0111..SDCLK x 2 21 * 0b0110..SDCLK x 2 20 * 0b0101..SDCLK x 2 19 * 0b0100..SDCLK x 2 18 * 0b0011..SDCLK x 2 17 * 0b0010..SDCLK x 2 16 * 0b0001..SDCLK x 2 15 * 0b0000..SDCLK x 2 14 */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) /*! IPP_RST_N - Hardware reset */ #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) #define USDHC_SYS_CTRL_RSTA_SHIFT (24U) /*! RSTA - Software reset for all * 0b1..Reset * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) #define USDHC_SYS_CTRL_RSTC_SHIFT (25U) /*! RSTC - Software reset for CMD line * 0b1..Reset * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) #define USDHC_SYS_CTRL_RSTD_SHIFT (26U) /*! RSTD - Software reset for data line * 0b1..Reset * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) #define USDHC_SYS_CTRL_INITA_SHIFT (27U) /*! INITA - Initialization active */ #define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) #define USDHC_SYS_CTRL_RSTT_SHIFT (28U) /*! RSTT - Reset tuning */ #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status */ /*! @{ */ #define USDHC_INT_STATUS_CC_MASK (0x1U) #define USDHC_INT_STATUS_CC_SHIFT (0U) /*! CC - Command complete * 0b1..Command complete * 0b0..Command not complete */ #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) #define USDHC_INT_STATUS_TC_MASK (0x2U) #define USDHC_INT_STATUS_TC_SHIFT (1U) /*! TC - Transfer complete * 0b1..Transfer complete * 0b0..Transfer does not complete */ #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) #define USDHC_INT_STATUS_BGE_MASK (0x4U) #define USDHC_INT_STATUS_BGE_SHIFT (2U) /*! BGE - Block gap event * 0b1..Transaction stopped at block gap * 0b0..No block gap event */ #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) #define USDHC_INT_STATUS_DINT_MASK (0x8U) #define USDHC_INT_STATUS_DINT_SHIFT (3U) /*! DINT - DMA interrupt * 0b1..DMA interrupt is generated. * 0b0..No DMA interrupt */ #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) #define USDHC_INT_STATUS_BWR_MASK (0x10U) #define USDHC_INT_STATUS_BWR_SHIFT (4U) /*! BWR - Buffer write ready * 0b1..Ready to write buffer * 0b0..Not ready to write buffer */ #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) #define USDHC_INT_STATUS_BRR_MASK (0x20U) #define USDHC_INT_STATUS_BRR_SHIFT (5U) /*! BRR - Buffer read ready * 0b1..Ready to read buffer * 0b0..Not ready to read buffer */ #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) #define USDHC_INT_STATUS_CINS_MASK (0x40U) #define USDHC_INT_STATUS_CINS_SHIFT (6U) /*! CINS - Card insertion * 0b1..Card inserted * 0b0..Card state unstable or removed */ #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) #define USDHC_INT_STATUS_CRM_MASK (0x80U) #define USDHC_INT_STATUS_CRM_SHIFT (7U) /*! CRM - Card removal * 0b1..Card removed * 0b0..Card state unstable or inserted */ #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) #define USDHC_INT_STATUS_CINT_MASK (0x100U) #define USDHC_INT_STATUS_CINT_SHIFT (8U) /*! CINT - Card interrupt * 0b1..Generate card interrupt * 0b0..No card interrupt */ #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) #define USDHC_INT_STATUS_RTE_MASK (0x1000U) #define USDHC_INT_STATUS_RTE_SHIFT (12U) /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) * 0b1..Re-tuning should be performed. * 0b0..Re-tuning is not required. */ #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) #define USDHC_INT_STATUS_TP_MASK (0x2000U) #define USDHC_INT_STATUS_TP_SHIFT (13U) /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) */ #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) #define USDHC_INT_STATUS_CQI_MASK (0x4000U) #define USDHC_INT_STATUS_CQI_SHIFT (14U) /*! CQI - Command queuing interrupt */ #define USDHC_INT_STATUS_CQI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK) #define USDHC_INT_STATUS_CTOE_MASK (0x10000U) #define USDHC_INT_STATUS_CTOE_SHIFT (16U) /*! CTOE - Command timeout error * 0b1..Time out * 0b0..No error */ #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) #define USDHC_INT_STATUS_CCE_MASK (0x20000U) #define USDHC_INT_STATUS_CCE_SHIFT (17U) /*! CCE - Command CRC error * 0b1..CRC error generated * 0b0..No error */ #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) #define USDHC_INT_STATUS_CEBE_MASK (0x40000U) #define USDHC_INT_STATUS_CEBE_SHIFT (18U) /*! CEBE - Command end bit error * 0b1..End bit error generated * 0b0..No error */ #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) #define USDHC_INT_STATUS_CIE_MASK (0x80000U) #define USDHC_INT_STATUS_CIE_SHIFT (19U) /*! CIE - Command index error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) #define USDHC_INT_STATUS_DTOE_MASK (0x100000U) #define USDHC_INT_STATUS_DTOE_SHIFT (20U) /*! DTOE - Data timeout error * 0b1..Time out * 0b0..No error */ #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) #define USDHC_INT_STATUS_DCE_MASK (0x200000U) #define USDHC_INT_STATUS_DCE_SHIFT (21U) /*! DCE - Data CRC error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) #define USDHC_INT_STATUS_DEBE_MASK (0x400000U) #define USDHC_INT_STATUS_DEBE_SHIFT (22U) /*! DEBE - Data end bit error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) #define USDHC_INT_STATUS_AC12E_SHIFT (24U) /*! AC12E - Auto CMD12 error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) #define USDHC_INT_STATUS_TNE_MASK (0x4000000U) #define USDHC_INT_STATUS_TNE_SHIFT (26U) /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) */ #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) #define USDHC_INT_STATUS_DMAE_SHIFT (28U) /*! DMAE - DMA error * 0b1..Error * 0b0..No error */ #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) /*! @} */ /*! @name INT_STATUS_EN - Interrupt Status Enable */ /*! @{ */ #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) /*! CCSEN - Command complete status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) /*! TCSEN - Transfer complete status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) /*! BGESEN - Block gap event status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) /*! DINTSEN - DMA interrupt status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) /*! BWRSEN - Buffer write ready status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) /*! BRRSEN - Buffer read ready status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) /*! CINSSEN - Card insertion status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) /*! CRMSEN - Card removal status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) /*! CINTSEN - Card interrupt status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) /*! RTESEN - Re-tuning event status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x2000U) #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (13U) /*! TPSEN - Tuning pass status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) #define USDHC_INT_STATUS_EN_CQISEN_MASK (0x4000U) #define USDHC_INT_STATUS_EN_CQISEN_SHIFT (14U) /*! CQISEN - Command queuing status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CQISEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK) #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) /*! CTOESEN - Command timeout error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) /*! CCESEN - Command CRC error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) /*! CEBESEN - Command end bit error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) /*! CIESEN - Command index error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) /*! DTOESEN - Data timeout error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) /*! DCESEN - Data CRC error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) /*! DEBESEN - Data end bit error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) /*! AC12ESEN - Auto CMD12 error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) /*! TNESEN - Tuning error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) /*! DMAESEN - DMA error status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) /*! @} */ /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ /*! @{ */ #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) /*! CCIEN - Command complete interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) /*! TCIEN - Transfer complete interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) /*! BGEIEN - Block gap event interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) /*! DINTIEN - DMA interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) /*! BWRIEN - Buffer write ready interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) /*! BRRIEN - Buffer read ready interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) /*! CINSIEN - Card insertion interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) /*! CRMIEN - Card removal interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) /*! CINTIEN - Card interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) /*! RTEIEN - Re-tuning event interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x2000U) #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (13U) /*! TPIEN - Tuning pass interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) #define USDHC_INT_SIGNAL_EN_CQIIEN_MASK (0x4000U) #define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT (14U) /*! CQIIEN - Command queuing signal enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CQIIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK) #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) /*! CTOEIEN - Command timeout error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) /*! CCEIEN - Command CRC error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) /*! CEBEIEN - Command end bit error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) /*! CIEIEN - Command index error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) /*! DTOEIEN - Data timeout error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) /*! DCEIEN - Data CRC error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) /*! DEBEIEN - Data end bit error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) /*! AC12EIEN - Auto CMD12 error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) /*! TNEIEN - Tuning error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) /*! DMAEIEN - DMA error interrupt enable * 0b1..Enable * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) /*! @} */ /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ /*! @{ */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) /*! AC12NE - Auto CMD12 not executed * 0b1..Not executed * 0b0..Executed */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) /*! AC12TOE - Auto CMD12 / 23 timeout error * 0b1..Time out * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) /*! AC12EBE - Auto CMD12 / 23 end bit error * 0b1..End bit error generated * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) /*! AC12CE - Auto CMD12 / 23 CRC error * 0b1..CRC error met in Auto CMD12/23 response * 0b0..No CRC error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) /*! AC12IE - Auto CMD12 / 23 index error * 0b1..Error, the CMD index in response is not CMD12/23 * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) /*! CNIBAC12E - Command not issued by Auto CMD12 error * 0b1..Not issued * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) /*! EXECUTE_TUNING - Execute tuning */ #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Sample clock select * 0b1..Tuned clock is used to sample data * 0b0..Fixed clock is used to sample data */ #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) /*! @} */ /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ /*! @{ */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) /*! SDR50_SUPPORT - SDR50 support */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) /*! SDR104_SUPPORT - SDR104 support */ #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) /*! DDR50_SUPPORT - DDR50 support */ #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) /*! TIME_COUNT_RETUNING - Time counter for retuning */ #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) /*! USE_TUNING_SDR50 - Use Tuning for SDR50 * 0b1..SDR50 requires tuning. * 0b0..SDR does not require tuning. */ #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) /*! RETUNING_MODE - Retuning Mode * 0b00..Mode 1 * 0b01..Mode 2 * 0b10..Mode 3 * 0b11..Reserved */ #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) /*! MBL - Max block length * 0b000..512 bytes * 0b001..1024 bytes * 0b010..2048 bytes * 0b011..4096 bytes */ #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) /*! ADMAS - ADMA support * 0b1..Advanced DMA supported * 0b0..Advanced DMA not supported */ #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) /*! HSS - High speed support * 0b1..High speed supported * 0b0..High speed not supported */ #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) /*! DMAS - DMA support * 0b1..DMA supported * 0b0..DMA not supported */ #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) /*! SRS - Suspend / resume support * 0b1..Supported * 0b0..Not supported */ #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) /*! VS33 - Voltage support 3.3 V * 0b1..3.3 V supported * 0b0..3.3 V not supported */ #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) /*! VS30 - Voltage support 3.0 V * 0b1..3.0 V supported * 0b0..3.0 V not supported */ #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) /*! VS18 - Voltage support 1.8 V * 0b1..1.8 V supported * 0b0..1.8 V not supported */ #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) /*! @} */ /*! @name WTMK_LVL - Watermark Level */ /*! @{ */ #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) /*! RD_WML - Read watermark level */ #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) #define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) #define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) /*! WR_WML - Write watermark level */ #define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) /*! @} */ /*! @name MIX_CTRL - Mixer Control */ /*! @{ */ #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) /*! DMAEN - DMA enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) #define USDHC_MIX_CTRL_BCEN_MASK (0x2U) #define USDHC_MIX_CTRL_BCEN_SHIFT (1U) /*! BCEN - Block count enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) /*! AC12EN - Auto CMD12 enable * 0b1..Enable * 0b0..Disable */ #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) /*! DDR_EN - Dual data rate mode selection */ #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) /*! DTDSEL - Data transfer direction select * 0b1..Read (Card to host) * 0b0..Write (Host to card) */ #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) /*! MSBSEL - Multi / Single block select * 0b1..Multiple blocks * 0b0..Single block */ #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) /*! NIBBLE_POS - Nibble position indication */ #define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) #define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) #define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) /*! AC23EN - Auto CMD23 enable */ #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) * 0b1..Execute tuning * 0b0..Not tuned or tuning completed */ #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Clock selection * 0b1..Tuned clock is used to sample data / cmd * 0b0..Fixed clock is used to sample data / cmd */ #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) * 0b1..Enable auto tuning * 0b0..Disable auto tuning */ #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) * 0b1..Feedback clock comes from the ipp_card_clk_out * 0b0..Feedback clock comes from the loopback CLK */ #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) #define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) #define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) /*! HS400_MODE - Enable HS400 mode */ #define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK) #define USDHC_MIX_CTRL_EN_HS400_MODE_MASK (0x8000000U) #define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT (27U) /*! EN_HS400_MODE - Enable enhance HS400 mode */ #define USDHC_MIX_CTRL_EN_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK) /*! @} */ /*! @name FORCE_EVENT - Force Event */ /*! @{ */ #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) /*! FEVTAC12NE - Force event auto command 12 not executed */ #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) /*! FEVTAC12TOE - Force event auto command 12 time out error */ #define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) /*! FEVTAC12CE - Force event auto command 12 CRC error */ #define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) /*! FEVTAC12EBE - Force event Auto Command 12 end bit error */ #define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) /*! FEVTAC12IE - Force event Auto Command 12 index error */ #define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */ #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) #define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) /*! FEVTCTOE - Force event command time out error */ #define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) #define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) /*! FEVTCCE - Force event command CRC error */ #define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) #define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) /*! FEVTCEBE - Force event command end bit error */ #define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) #define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) /*! FEVTCIE - Force event command index error */ #define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) #define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) /*! FEVTDTOE - Force event data time out error */ #define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) #define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) /*! FEVTDCE - Force event data CRC error */ #define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) #define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) /*! FEVTDEBE - Force event data end bit error */ #define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) #define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) /*! FEVTAC12E - Force event Auto Command 12 error */ #define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) #define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) /*! FEVTTNE - Force tuning error */ #define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) #define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) /*! FEVTDMAE - Force event DMA error */ #define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) /*! FEVTCINT - Force event card interrupt */ #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) /*! @} */ /*! @name ADMA_ERR_STATUS - ADMA Error Status */ /*! @{ */ #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) /*! ADMAES - ADMA error state (when ADMA error is occurred) */ #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) /*! ADMALME - ADMA length mismatch error * 0b1..Error * 0b0..No error */ #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) /*! ADMADCE - ADMA descriptor error * 0b1..Error * 0b0..No error */ #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) /*! @} */ /*! @name ADMA_SYS_ADDR - ADMA System Address */ /*! @{ */ #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) /*! ADS_ADDR - ADMA system address */ #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) /*! @} */ /*! @name DLL_CTRL - DLL (Delay Line) Control */ /*! @{ */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) /*! DLL_CTRL_ENABLE - DLL and delay chain */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) /*! DLL_CTRL_RESET - DLL reset */ #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) /*! DLL_CTRL_GATE_UPDATE - DLL gate update */ #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */ #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name DLL_STATUS - DLL Status */ /*! @{ */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) /*! DLL_STS_SLV_LOCK - Slave delay-line lock status */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) /*! DLL_STS_REF_LOCK - Reference DLL lock status */ #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) /*! DLL_STS_SLV_SEL - Slave delay line select status */ #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) /*! DLL_STS_REF_SEL - Reference delay line select taps */ #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) /*! @} */ /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ /*! @{ */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) /*! NXT_ERR - NXT error */ #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) /*! TAP_SEL_PRE - TAP_SEL_PRE */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) /*! PRE_ERR - PRE error */ #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) /*! @} */ /*! @name STROBE_DLL_CTRL - Strobe DLL control */ /*! @{ */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) /*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) /*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) /*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U) /*! STROBE_DLL_CTRL_GATE_UPDATE_0 - Strobe DLL control gate update */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U) /*! STROBE_DLL_CTRL_GATE_UPDATE_1 - Strobe DLL control gate update */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) /*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) /*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name STROBE_DLL_STATUS - Strobe DLL status */ /*! @{ */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) /*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) /*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) /*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) /*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) /*! @} */ /*! @name VEND_SPEC - Vendor Specific Register */ /*! @{ */ #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) /*! VSELECT - Voltage selection * 0b1..Change the voltage to low voltage range, around 1.8 V * 0b0..Change the voltage to high voltage range, around 3.0 V */ #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) /*! CONFLICT_CHK_EN - Conflict check enable * 0b0..Conflict check disable * 0b1..Conflict check enable */ #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) /*! AC12_WR_CHKBUSY_EN - Check busy enable * 0b0..Do not check busy after auto CMD12 for write data packet * 0b1..Check busy after auto CMD12 for write data packet */ #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) /*! FRC_SDCLK_ON - Force CLK * 0b0..CLK active or inactive is fully controlled by the hardware. * 0b1..Force CLK active */ #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) /*! CRC_CHK_DIS - CRC Check Disable * 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet * 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet */ #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) /*! CMD_BYTE_EN - Byte access * 0b0..Disable * 0b1..Enable */ #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) /*! @} */ /*! @name MMC_BOOT - MMC Boot */ /*! @{ */ #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) /*! DTOCV_ACK - DTOCV_ACK * 0b0000..SDCLK x 2^32 * 0b0001..SDCLK x 2^33 * 0b0010..SDCLK x 2^18 * 0b0011..SDCLK x 2^19 * 0b0100..SDCLK x 2^20 * 0b0101..SDCLK x 2^21 * 0b0110..SDCLK x 2^22 * 0b0111..SDCLK x 2^23 * 0b1110..SDCLK x 2^30 * 0b1111..SDCLK x 2^31 */ #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) /*! BOOT_ACK - BOOT ACK * 0b0..No ack * 0b1..Ack */ #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) /*! BOOT_MODE - Boot mode * 0b0..Normal boot * 0b1..Alternative boot */ #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) /*! BOOT_EN - Boot enable * 0b0..Fast boot disable * 0b1..Fast boot enable */ #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) /*! AUTO_SABG_EN - Auto stop at block gap */ #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) /*! DISABLE_TIME_OUT - Time out * 0b0..Enable time out * 0b1..Disable time out */ #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */ #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) /*! @} */ /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ /*! @{ */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) /*! CARD_INT_D3_TEST - Card interrupt detection test * 0b0..Check the card interrupt only when DATA3 is high. * 0b1..Check the card interrupt by ignoring the status of DATA3. */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) /*! TUNING_8bit_EN - Tuning 8bit enable */ #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) /*! TUNING_1bit_EN - Tuning 1bit enable */ #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) /*! TUNING_CMD_EN - Tuning command enable * 0b0..Auto tuning circuit does not check the CMD line. * 0b1..Auto tuning circuit checks the CMD line. */ #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) /*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */ #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) /*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */ #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. * 0b0..Disable */ #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) #define USDHC_VEND_SPEC2_EN_32K_CLK_MASK (0x8000U) #define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT (15U) /*! EN_32K_CLK - Enable 32khz clock for card detection */ #define USDHC_VEND_SPEC2_EN_32K_CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK) #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK (0xFFFF0000U) #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT (16U) /*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock */ #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK) /*! @} */ /*! @name TUNING_CTRL - Tuning Control */ /*! @{ */ #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) /*! TUNING_START_TAP - Tuning start */ #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) /*! TUNING_COUNTER - Tuning counter */ #define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) #define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) /*! TUNING_STEP - TUNING_STEP */ #define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) /*! TUNING_WINDOW - Data window */ #define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) /*! STD_TUNING_EN - Standard tuning circuit and procedure enable */ #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) /*! @} */ /*! * @} */ /* end of group USDHC_Register_Masks */ /* USDHC - Peripheral instance base addresses */ /** Peripheral CONNECTIVITY__USDHC0 base address */ #define CONNECTIVITY__USDHC0_BASE (0x5B010000u) /** Peripheral CONNECTIVITY__USDHC0 base pointer */ #define CONNECTIVITY__USDHC0 ((USDHC_Type *)CONNECTIVITY__USDHC0_BASE) /** Peripheral CONNECTIVITY__USDHC1 base address */ #define CONNECTIVITY__USDHC1_BASE (0x5B020000u) /** Peripheral CONNECTIVITY__USDHC1 base pointer */ #define CONNECTIVITY__USDHC1 ((USDHC_Type *)CONNECTIVITY__USDHC1_BASE) /** Peripheral CONNECTIVITY__USDHC2 base address */ #define CONNECTIVITY__USDHC2_BASE (0x5B030000u) /** Peripheral CONNECTIVITY__USDHC2 base pointer */ #define CONNECTIVITY__USDHC2 ((USDHC_Type *)CONNECTIVITY__USDHC2_BASE) /** Array initializer of USDHC peripheral base addresses */ #define USDHC_BASE_ADDRS { CONNECTIVITY__USDHC0_BASE, CONNECTIVITY__USDHC1_BASE, CONNECTIVITY__USDHC2_BASE } /** Array initializer of USDHC peripheral base pointers */ #define USDHC_BASE_PTRS { CONNECTIVITY__USDHC0, CONNECTIVITY__USDHC1, CONNECTIVITY__USDHC2 } /** Interrupt vectors for the USDHC peripheral type */ #define USDHC_IRQS { CONNECTIVITY_USDHC0_INT_IRQn, CONNECTIVITY_USDHC1_INT_IRQn, CONNECTIVITY_USDHC2_INT_IRQn } /*! * @} */ /* end of group USDHC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VPU_CSR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_CSR_Peripheral_Access_Layer VPU_CSR Peripheral Access Layer * @{ */ /** VPU_CSR - Register Layout Typedef */ typedef struct { __IO uint32_t CM0PX_ADDR_OFFSET; /**< CM0Px Boot vector address offset, offset: 0x0 */ __IO uint32_t CM0PX_CPUWAIT; /**< CM0Px CPUWAIT signal control, offset: 0x4 */ __IO uint32_t CM0PX_CTL; /**< CM0Px Control register, offset: 0x8 */ __I uint32_t CM0PX_STAT; /**< CM0Px Status register, offset: 0xC */ struct { /* offset: 0x10 */ __IO uint32_t RW; /**< CM0Px Interrupt register, offset: 0x10 */ __IO uint32_t SET; /**< CM0Px Interrupt register, offset: 0x14 */ __IO uint32_t CLR; /**< CM0Px Interrupt register, offset: 0x18 */ __IO uint32_t TOG; /**< CM0Px Interrupt register, offset: 0x1C */ } CM0PX_INT; __I uint32_t CM0PX_INT_STAT; /**< CM0Px Interrupt status register, offset: 0x20 */ __IO uint32_t CM0PX_INT_EN; /**< CM0Px Interrupt enable register, offset: 0x24 */ __IO uint32_t EXT_INT_OVR; /**< External interrupt override register, offset: 0x28 */ } VPU_CSR_Type; /* ---------------------------------------------------------------------------- -- VPU_CSR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_CSR_Register_Masks VPU_CSR Register Masks * @{ */ /*! @name CM0PX_ADDR_OFFSET - CM0Px Boot vector address offset */ /*! @{ */ #define VPU_CSR_CM0PX_ADDR_OFFSET_OFFSET_MASK (0xFFFFFFFFU) #define VPU_CSR_CM0PX_ADDR_OFFSET_OFFSET_SHIFT (0U) /*! OFFSET - CM0Px output address bus offset */ #define VPU_CSR_CM0PX_ADDR_OFFSET_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_ADDR_OFFSET_OFFSET_SHIFT)) & VPU_CSR_CM0PX_ADDR_OFFSET_OFFSET_MASK) /*! @} */ /*! @name CM0PX_CPUWAIT - CM0Px CPUWAIT signal control */ /*! @{ */ #define VPU_CSR_CM0PX_CPUWAIT_CPW_MASK (0x1U) #define VPU_CSR_CM0PX_CPUWAIT_CPW_SHIFT (0U) /*! CPW - Control CM0Px CPUWAIT input signal * 0b0..Processor is running * 0b1..Processor is waiting */ #define VPU_CSR_CM0PX_CPUWAIT_CPW(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CPUWAIT_CPW_SHIFT)) & VPU_CSR_CM0PX_CPUWAIT_CPW_MASK) /*! @} */ /*! @name CM0PX_CTL - CM0Px Control register */ /*! @{ */ #define VPU_CSR_CM0PX_CTL_REV_MASK (0x1U) #define VPU_CSR_CM0PX_CTL_REV_SHIFT (0U) /*! REV * 0b0..No override * 0b1..RXEV is forced low */ #define VPU_CSR_CM0PX_CTL_REV(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_REV_SHIFT)) & VPU_CSR_CM0PX_CTL_REV_MASK) #define VPU_CSR_CM0PX_CTL_TEV_MASK (0x2U) #define VPU_CSR_CM0PX_CTL_TEV_SHIFT (1U) /*! TEV - Override TXEV output signal * 0b0..No override * 0b1..TXEV is forced low */ #define VPU_CSR_CM0PX_CTL_TEV(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_TEV_SHIFT)) & VPU_CSR_CM0PX_CTL_TEV_MASK) #define VPU_CSR_CM0PX_CTL_ILT_MASK (0x3FCU) #define VPU_CSR_CM0PX_CTL_ILT_SHIFT (2U) /*! ILT - Control CM0Px IRQLATENCY[7:0] input */ #define VPU_CSR_CM0PX_CTL_ILT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_ILT_SHIFT)) & VPU_CSR_CM0PX_CTL_ILT_MASK) #define VPU_CSR_CM0PX_CTL_CLR_MASK (0x400U) #define VPU_CSR_CM0PX_CTL_CLR_SHIFT (10U) /*! CLR - Clear LPCAC data cache * 0b0..Disable clear * 0b1..Enable clear */ #define VPU_CSR_CM0PX_CTL_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_CLR_SHIFT)) & VPU_CSR_CM0PX_CTL_CLR_MASK) #define VPU_CSR_CM0PX_CTL_NAL_MASK (0x800U) #define VPU_CSR_CM0PX_CTL_NAL_SHIFT (11U) /*! NAL - Disable LPCAC data cache allocation * 0b0..Enable LPCAC data cache allocation * 0b1..Disable LPCAC data cache allocation */ #define VPU_CSR_CM0PX_CTL_NAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_NAL_SHIFT)) & VPU_CSR_CM0PX_CTL_NAL_MASK) #define VPU_CSR_CM0PX_CTL_DWB_MASK (0x1000U) #define VPU_CSR_CM0PX_CTL_DWB_SHIFT (12U) /*! DWB - Disable LPCAC write buffer * 0b0..Enable write buffer * 0b1..Disable write buffer */ #define VPU_CSR_CM0PX_CTL_DWB(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_DWB_SHIFT)) & VPU_CSR_CM0PX_CTL_DWB_MASK) #define VPU_CSR_CM0PX_CTL_DIS_MASK (0x2000U) #define VPU_CSR_CM0PX_CTL_DIS_SHIFT (13U) /*! DIS - Disable LPCAC * 0b0..Enable LPCAC * 0b1..Disable LPCAC */ #define VPU_CSR_CM0PX_CTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_DIS_SHIFT)) & VPU_CSR_CM0PX_CTL_DIS_MASK) #define VPU_CSR_CM0PX_CTL_MCT_MASK (0x4000U) #define VPU_CSR_CM0PX_CTL_MCT_SHIFT (14U) /*! MCT - Disable CACHE_MAP and force all memory space to be cached * 0b0..CACHE_MAP enable * 0b1..CACHE_MAP disable */ #define VPU_CSR_CM0PX_CTL_MCT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_CTL_MCT_SHIFT)) & VPU_CSR_CM0PX_CTL_MCT_MASK) /*! @} */ /*! @name CM0PX_STAT - CM0Px Status register */ /*! @{ */ #define VPU_CSR_CM0PX_STAT_LKP_MASK (0x1U) #define VPU_CSR_CM0PX_STAT_LKP_SHIFT (0U) /*! LKP - CM0Px LOCKUP output signal value */ #define VPU_CSR_CM0PX_STAT_LKP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_STAT_LKP_SHIFT)) & VPU_CSR_CM0PX_STAT_LKP_MASK) /*! @} */ /*! @name CM0PX_INT - CM0Px Interrupt register */ /*! @{ */ #define VPU_CSR_CM0PX_INT_INT_MASK (0x1FU) #define VPU_CSR_CM0PX_INT_INT_SHIFT (0U) /*! INT - CM0Px CSR interrupt register. CSR interrupt register is ORed with MFD/VENC interrupts. */ #define VPU_CSR_CM0PX_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_INT_INT_SHIFT)) & VPU_CSR_CM0PX_INT_INT_MASK) /*! @} */ /*! @name CM0PX_INT_STAT - CM0Px Interrupt status register */ /*! @{ */ #define VPU_CSR_CM0PX_INT_STAT_IST_MASK (0x1FU) #define VPU_CSR_CM0PX_INT_STAT_IST_SHIFT (0U) /*! IST - CM0Px CSR override interrupt status. CSR interrupt register interrupt is ORed with MFD/VENC interrupts. */ #define VPU_CSR_CM0PX_INT_STAT_IST(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_INT_STAT_IST_SHIFT)) & VPU_CSR_CM0PX_INT_STAT_IST_MASK) /*! @} */ /*! @name CM0PX_INT_EN - CM0Px Interrupt enable register */ /*! @{ */ #define VPU_CSR_CM0PX_INT_EN_IEN_MASK (0x1FU) #define VPU_CSR_CM0PX_INT_EN_IEN_SHIFT (0U) /*! IEN - CM0Px interrupt enable. Enable MFD/VENC and override interrupts. */ #define VPU_CSR_CM0PX_INT_EN_IEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_CM0PX_INT_EN_IEN_SHIFT)) & VPU_CSR_CM0PX_INT_EN_IEN_MASK) /*! @} */ /*! @name EXT_INT_OVR - External interrupt override register */ /*! @{ */ #define VPU_CSR_EXT_INT_OVR_IOV_MASK (0x1FU) #define VPU_CSR_EXT_INT_OVR_IOV_SHIFT (0U) /*! IOV - Enable MFD/VENC and override external interrupts. */ #define VPU_CSR_EXT_INT_OVR_IOV(x) (((uint32_t)(((uint32_t)(x)) << VPU_CSR_EXT_INT_OVR_IOV_SHIFT)) & VPU_CSR_EXT_INT_OVR_IOV_MASK) /*! @} */ /*! * @} */ /* end of group VPU_CSR_Register_Masks */ /* VPU_CSR - Peripheral instance base addresses */ /** Peripheral VPU_CSR0 base address */ #define VPU_CSR0_BASE (0x2D040000u) /** Peripheral VPU_CSR0 base pointer */ #define VPU_CSR0 ((VPU_CSR_Type *)VPU_CSR0_BASE) /** Peripheral VPU_CSR1 base address */ #define VPU_CSR1_BASE (0x2D050000u) /** Peripheral VPU_CSR1 base pointer */ #define VPU_CSR1 ((VPU_CSR_Type *)VPU_CSR1_BASE) /** Array initializer of VPU_CSR peripheral base addresses */ #define VPU_CSR_BASE_ADDRS { VPU_CSR0_BASE, VPU_CSR1_BASE } /** Array initializer of VPU_CSR peripheral base pointers */ #define VPU_CSR_BASE_PTRS { VPU_CSR0, VPU_CSR1 } /*! * @} */ /* end of group VPU_CSR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer * @{ */ /** WDOG - Register Layout Typedef */ typedef struct { __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ } WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /*! @name CS - Watchdog Control and Status Register */ /*! @{ */ #define WDOG_CS_STOP_MASK (0x1U) #define WDOG_CS_STOP_SHIFT (0U) /*! STOP - Stop Enable * 0b0..Watchdog disabled in chip stop mode. * 0b1..Watchdog enabled in chip stop mode. */ #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) #define WDOG_CS_WAIT_MASK (0x2U) #define WDOG_CS_WAIT_SHIFT (1U) /*! WAIT - Wait Enable * 0b0..Watchdog disabled in chip wait mode. * 0b1..Watchdog enabled in chip wait mode. */ #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) #define WDOG_CS_DBG_MASK (0x4U) #define WDOG_CS_DBG_SHIFT (2U) /*! DBG - Debug Enable * 0b0..Watchdog disabled in chip debug mode. * 0b1..Watchdog enabled in chip debug mode. */ #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) #define WDOG_CS_TST_MASK (0x18U) #define WDOG_CS_TST_SHIFT (3U) /*! TST - Watchdog Test * 0b00..Watchdog test mode disabled. * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should * use this setting to indicate that the watchdog is functioning normally in user mode. * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. */ #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) #define WDOG_CS_UPDATE_MASK (0x20U) #define WDOG_CS_UPDATE_SHIFT (5U) /*! UPDATE - Allow updates * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. */ #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) #define WDOG_CS_INT_MASK (0x40U) #define WDOG_CS_INT_SHIFT (6U) /*! INT - Watchdog Interrupt * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. */ #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) #define WDOG_CS_EN_MASK (0x80U) #define WDOG_CS_EN_SHIFT (7U) /*! EN - Watchdog Enable * 0b0..Watchdog disabled. * 0b1..Watchdog enabled. */ #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) #define WDOG_CS_CLK_MASK (0x300U) #define WDOG_CS_CLK_SHIFT (8U) /*! CLK - Watchdog Clock * 0b00..Bus clock * 0b01..LPO clock * 0b10..INTCLK (internal clock) * 0b11..ERCLK (external reference clock) */ #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) #define WDOG_CS_RCS_MASK (0x400U) #define WDOG_CS_RCS_SHIFT (10U) /*! RCS - Reconfiguration Success * 0b0..Reconfiguring WDOG. * 0b1..Reconfiguration is successful. */ #define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK) #define WDOG_CS_ULK_MASK (0x800U) #define WDOG_CS_ULK_SHIFT (11U) /*! ULK - Unlock status * 0b0..WDOG is locked. * 0b1..WDOG is unlocked. */ #define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK) #define WDOG_CS_PRES_MASK (0x1000U) #define WDOG_CS_PRES_SHIFT (12U) /*! PRES - Watchdog prescaler * 0b0..256 prescaler disabled. * 0b1..256 prescaler enabled. */ #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) #define WDOG_CS_CMD32EN_MASK (0x2000U) #define WDOG_CS_CMD32EN_SHIFT (13U) /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. */ #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) #define WDOG_CS_FLG_MASK (0x4000U) #define WDOG_CS_FLG_SHIFT (14U) /*! FLG - Watchdog Interrupt Flag * 0b0..No interrupt occurred. * 0b1..An interrupt occurred. */ #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) #define WDOG_CS_WIN_MASK (0x8000U) #define WDOG_CS_WIN_SHIFT (15U) /*! WIN - Watchdog Window * 0b0..Window mode disabled. * 0b1..Window mode enabled. */ #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) /*! @} */ /*! @name CNT - Watchdog Counter Register */ /*! @{ */ #define WDOG_CNT_CNTLOW_MASK (0xFFU) #define WDOG_CNT_CNTLOW_SHIFT (0U) /*! CNTLOW - Low byte of the Watchdog Counter */ #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) #define WDOG_CNT_CNTHIGH_MASK (0xFF00U) #define WDOG_CNT_CNTHIGH_SHIFT (8U) /*! CNTHIGH - High byte of the Watchdog Counter */ #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) /*! @} */ /*! @name TOVAL - Watchdog Timeout Value Register */ /*! @{ */ #define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) #define WDOG_TOVAL_TOVALLOW_SHIFT (0U) /*! TOVALLOW - Low byte of the timeout value */ #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) #define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) #define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) /*! TOVALHIGH - High byte of the timeout value */ #define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) /*! @} */ /*! @name WIN - Watchdog Window Register */ /*! @{ */ #define WDOG_WIN_WINLOW_MASK (0xFFU) #define WDOG_WIN_WINLOW_SHIFT (0U) /*! WINLOW - Low byte of Watchdog Window */ #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) #define WDOG_WIN_WINHIGH_MASK (0xFF00U) #define WDOG_WIN_WINHIGH_SHIFT (8U) /*! WINHIGH - High byte of Watchdog Window */ #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) /*! @} */ /*! * @} */ /* end of group WDOG_Register_Masks */ /* WDOG - Peripheral instance base addresses */ /** Peripheral CM4__WDOG base address */ #define CM4__WDOG_BASE (0x41420000u) /** Peripheral CM4__WDOG base pointer */ #define CM4__WDOG ((WDOG_Type *)CM4__WDOG_BASE) /** Peripheral SCU__WDOG base address */ #define SCU__WDOG_BASE (0x33420000u) /** Peripheral SCU__WDOG base pointer */ #define SCU__WDOG ((WDOG_Type *)SCU__WDOG_BASE) /** Array initializer of WDOG peripheral base addresses */ #define WDOG_BASE_ADDRS { CM4__WDOG_BASE, SCU__WDOG_BASE } /** Array initializer of WDOG peripheral base pointers */ #define WDOG_BASE_PTRS { CM4__WDOG, SCU__WDOG } /* Extra definition */ #define WDOG_UPDATE_KEY (0xD928C520U) #define WDOG_REFRESH_KEY (0xB480A602U) /*! * @} */ /* end of group WDOG_Peripheral_Access_Layer */ /* ** End of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #else #pragma pop #endif #elif defined(__GNUC__) /* leave anonymous unions enabled */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=default #else #error Not supported compiler type #endif /*! * @} */ /* end of group Peripheral_access_layer */ /* ---------------------------------------------------------------------------- -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). ---------------------------------------------------------------------------- */ /*! * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). * @{ */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang system_header #endif #elif defined(__IAR_SYSTEMS_ICC__) #pragma system_include #endif /** * @brief Mask and left-shift a bit field value for use in a register bit range. * @param field Name of the register bit field. * @param value Value of the bit field. * @return Masked and shifted value. */ #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) /** * @brief Mask and right-shift a register value to extract a bit field value. * @param field Name of the register bit field. * @param value Value of the register. * @return Masked and shifted bit field value. */ #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) /*! * @} */ /* end of group Bit_Field_Generic_Macros */ /* ---------------------------------------------------------------------------- -- SDK Compatibility ---------------------------------------------------------------------------- */ /*! * @addtogroup SDK_Compatibility_Symbols SDK Compatibility * @{ */ /* No SDK compatibility issues. */ /*! * @} */ /* end of group SDK_Compatibility_Symbols */ #endif /* _MIMX8UX5_CM4_H_ */